WO2025023129A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2025023129A1
WO2025023129A1 PCT/JP2024/025693 JP2024025693W WO2025023129A1 WO 2025023129 A1 WO2025023129 A1 WO 2025023129A1 JP 2024025693 W JP2024025693 W JP 2024025693W WO 2025023129 A1 WO2025023129 A1 WO 2025023129A1
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region
high concentration
main surface
gate structure
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French (fr)
Japanese (ja)
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誠悟 森
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Rohm Co Ltd
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Rohm Co Ltd
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  • Patent document 1 discloses a semiconductor device including a p-type doped region formed in an n-type epitaxial layer directly below a trench gate structure.
  • the present disclosure provides a semiconductor device having a novel layout.
  • the present disclosure provides a semiconductor device including a chip having a main surface, a first region of a first conductivity type formed in a surface layer of the main surface within the chip, a second region of a second conductivity type formed in a region of the chip on the main surface side relative to the first region, a trench-type gate structure formed in the main surface away from a bottom of the second region, an impurity region of the first conductivity type formed in the surface layer of the main surface along the gate structure, and a drift region of the first conductivity type formed in a thickness range between the bottom of the second region and a bottom wall of the gate structure, and partitioning the impurity region from a channel.
  • the present disclosure provides a semiconductor device including a chip having a main surface, a first region of a first conductivity type formed in a surface layer portion of the main surface within the chip, a second region of a second conductivity type formed in a region of the chip on the main surface side relative to the first region, a trench-type gate structure formed in the main surface away from the bottom of the second region, a drift region of a first conductivity type formed in a thickness range between the bottom of the second region and a bottom wall of the gate structure, and a high-concentration region of a second conductivity type formed to the side of the gate structure within the second region and having an impurity concentration higher than the impurity concentration of the second region.
  • FIG. 1 is a plan view showing a semiconductor device.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a perspective view showing the shape of the chip.
  • FIG. 4 is a plan view showing an example of the layout of the first main surface.
  • FIG. 5 is an enlarged plan view showing a main portion of the first main surface.
  • FIG. 6 is a cross-sectional view showing a cross-sectional structure taken along line VI-VI shown in FIG. 5 together with the high concentration region according to the first embodiment.
  • FIG. 7 is an enlarged cross-sectional view showing a main portion of the area shown in FIG.
  • FIG. 8A is an enlarged cross-sectional view showing a high concentration region according to the second embodiment.
  • FIG. 8B is an enlarged cross-sectional view showing a high concentration region according to the third embodiment.
  • FIG. 8C is an enlarged cross-sectional view showing a high concentration region according to the fourth embodiment.
  • FIG. 8D is an enlarged cross-sectional view showing a high concentration region according to the fifth embodiment.
  • FIG. 8E is an enlarged cross-sectional view showing a high concentration region according to the sixth embodiment.
  • FIG. 8F is an enlarged cross-sectional view showing a high concentration region according to the seventh embodiment.
  • FIG. 8G is an enlarged cross-sectional view showing a high concentration region according to the eighth embodiment.
  • FIG. 8H is an enlarged cross-sectional view showing a high concentration region according to the ninth embodiment.
  • FIG. 8I is an enlarged cross-sectional view showing a high concentration region according to the tenth embodiment.
  • FIG. 8J is an enlarged cross-sectional view showing a high concentration region according to the eleventh embodiment.
  • FIG. 8K is an enlarged cross-sectional view showing a high concentration region according to the twelfth embodiment.
  • FIG. 8L is an enlarged cross-sectional view showing a high concentration region according to the thirteenth embodiment.
  • FIG. 8M is an enlarged cross-sectional view showing a high concentration region according to the fourteenth embodiment.
  • FIG. 8N is an enlarged cross-sectional view showing a high concentration region according to the fifteenth embodiment.
  • FIG. 8O is an enlarged cross-sectional view showing a high concentration region according to the sixteenth embodiment.
  • FIG. 10A is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.
  • FIG. 10B is a cross-sectional view showing a step subsequent to that of FIG. 10A.
  • FIG. 10C is a cross-sectional view showing a step subsequent to FIG. 10B.
  • FIG. 10D is a cross-sectional view showing a step subsequent to FIG. 10C.
  • FIG. 10E is a cross-sectional view showing a step subsequent to FIG. 10D.
  • FIG. 10F is a cross-sectional view showing a step subsequent to FIG. 10E.
  • FIG. 10G is a cross-sectional view showing a step subsequent to FIG. 10F.
  • FIG. 10A is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.
  • FIG. 10B is a cross-sectional view showing a step subsequent to that of FIG. 10A.
  • FIG. 10C is a cross-sectional view showing a step subsequent to FIG
  • FIG. 10H is a cross-sectional view showing a step subsequent to FIG. 10G.
  • FIG. 10I is a cross-sectional view showing a step subsequent to FIG. 10H.
  • FIG. 10J is a cross-sectional view showing a step subsequent to FIG. 10I.
  • FIG. 10K is a cross-sectional view showing a step subsequent to FIG. 10J.
  • FIG. 10L is a cross-sectional view showing a step subsequent to FIG. 10K.
  • FIG. 10M is a cross-sectional view showing a step subsequent to FIG. 10L.
  • FIG. 10N is a cross-sectional view showing a step subsequent to FIG. 10M.
  • FIG. 11 is an enlarged cross-sectional view showing a semiconductor device according to a modified example.
  • this term includes a numerical value (shape) that is equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • shape a numerical value that is equal to the numerical value (shape) of the comparison target
  • error a numerical error within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • the conductivity type of a semiconductor is indicated using “p-type” or “n-type”, but “p-type” may also be referred to as the “first conductivity type” and “n-type” as the “second conductivity type”. Of course, “n-type” may also be referred to as the "first conductivity type” and “p-type” as the “second conductivity type”.
  • P-type is a conductivity type resulting from a trivalent element
  • n-type is a conductivity type resulting from a pentavalent element.
  • the trivalent element is at least one of boron, aluminum, gallium, and indium.
  • the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • FIG. 1 is a plan view showing a semiconductor device 1.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1.
  • FIG. 3 is a perspective view showing the shape of a chip 2.
  • FIG. 4 is a plan view showing an example of the layout of a first main surface 3.
  • FIG. 5 is an enlarged plan view showing a main portion of the first main surface 3.
  • FIG. 6 is a cross-sectional view showing a cross-sectional structure taken along line VI-VI shown in FIG. 5 together with a high concentration region 30 according to a first embodiment.
  • FIG. 7 is an enlarged cross-sectional view showing a main portion of the region shown in FIG. 6.
  • semiconductor device 1 includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape).
  • chip 2 includes a single crystal of a wide bandgap semiconductor.
  • semiconductor device 1 is a "wide bandgap semiconductor device.”
  • Chip 2 may also be referred to as a “semiconductor chip,” a “wide bandgap semiconductor chip,” etc.
  • a wide bandgap semiconductor is a semiconductor that has a bandgap that exceeds the bandgap of Si (silicon).
  • Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond).
  • chip 2 is a "SiC chip” that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor.
  • semiconductor device 1 is a "SiC semiconductor device.”
  • the semiconductor device 1 may be referred to as a "SiC-MISFET.”
  • the hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like.
  • the chip 2 includes a 4H-SiC single crystal, but the chip 2 may include other polytypes.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view").
  • the vertical direction Z is also the thickness direction of the chip 2.
  • the first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal.
  • the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal
  • the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.
  • the first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.
  • the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal
  • the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal.
  • the first direction X may be the a-axis direction of the SiC single crystal
  • the second direction Y may be the m-axis direction of the SiC single crystal.
  • the direction extending along the first main surface 3 may be referred to as the "horizontal direction.”
  • the horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.
  • the chip 2 (first main surface 3 and second main surface 4) has an off angle that is inclined at a predetermined angle in a predetermined off direction relative to the c-plane of the SiC single crystal.
  • the c-axis ((0001) axis) of the SiC single crystal is inclined by the off angle from a vertical line along the vertical direction Z toward the off direction.
  • the c-plane of the SiC single crystal is inclined by the off angle relative to the horizontal plane.
  • the off-direction is preferably the a-axis direction of the SiC single crystal (the second direction Y in this embodiment).
  • the off-angle may be greater than 0° and less than or equal to 10°.
  • the off-angle may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.
  • the off angle is preferably 5° or less. It is particularly preferable that the off angle be 2° or more and 4.5° or less.
  • the off angle is typically set in the range of 4° ⁇ 0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane relative to the c-plane).
  • the semiconductor device 1 includes an n-type base region 6 formed in a surface layer of the second main surface 4.
  • a drain potential is applied to the base region 6 as a first potential (high potential).
  • the base region 6 may also be referred to as a "base layer,” a “semiconductor layer,” a “drain region,” etc.
  • the base region 6 is formed in a layer extending along the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the base region 6 is made of an n-type semiconductor layer.
  • the base region 6 is made of a substrate (SiC substrate) containing SiC single crystal (semiconductor single crystal), and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the base region 6 (substrate) has the off direction and off angle described above.
  • the base region 6 may have a thickness of 10 ⁇ m or more and 500 ⁇ m or less.
  • the thickness of the base region 6 may have a value that falls within at least one of the following ranges: 10 ⁇ m or more and 50 ⁇ m or less, 50 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 150 ⁇ m or less, 150 ⁇ m or more and 200 ⁇ m or less, 200 ⁇ m or more and 300 ⁇ m or less, 300 ⁇ m or more and 400 ⁇ m or less, and 400 ⁇ m or more and 500 ⁇ m or less.
  • the semiconductor device 1 includes an n-type first region 7 formed in a surface layer portion of the first main surface 3.
  • the first region 7 may be referred to as a "first semiconductor region,” a “first semiconductor layer,” a “base drift region (layer),” or the like.
  • the first region 7 has an n-type impurity concentration that is less than the n-type impurity concentration of the base region 6.
  • the first region 7 is formed in a region on the first main surface 3 side relative to the base region 6 in a cross-sectional view, and is electrically connected to the base region 6.
  • the first region 7 is formed in a layer extending along the first main surface 3 and is exposed from the first to fourth side surfaces 5A to 5D.
  • the first region 7 is made of an n-type semiconductor layer.
  • the first region 7 is made of an epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal), and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the first region 7 (epitaxial layer) has the off-direction and off-angle described above. It is preferable that the first region 7 has a thickness less than that of the base region 6. Of course, the thickness of the first region 7 may be greater than that of the base region 6.
  • the thickness of the first region 7 may be 5 ⁇ m or more and 15 ⁇ m or less.
  • the thickness of the first region 7 may have a value that falls within at least one of the following ranges: 5 ⁇ m or more and 7.5 ⁇ m or less, 7.5 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 12.5 ⁇ m or less, and 12.5 ⁇ m or more and 15 ⁇ m or less.
  • the semiconductor device 1 includes a first surface portion 8, a second surface portion 9, and first to fourth connection surface portions 10A to 10D formed on the first main surface 3.
  • the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D define a mesa on the first main surface 3.
  • the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D may be considered to be components of the chip 2 (first main surface 3).
  • the first surface portion 8 may be referred to as the "active surface”
  • the second surface portion 9 may be referred to as the “outer surface”
  • the first to fourth connecting surface portions 10A to 10D may be referred to as “connecting surfaces”
  • the mesa may be referred to as the "active mesa”.
  • the first surface portion 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3.
  • the first surface portion 8 has a flat surface extending horizontally, and is formed by a c-plane (Si-plane).
  • the first surface portion 8 is formed in a polygonal shape (specifically, a quadrilateral shape) having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.
  • the planar area of the first surface portion 8 is preferably 50% to 90% of the planar area of the first main surface 3.
  • the second surface portion 9 is located on the peripheral side of the first main surface 3 relative to the first surface portion 8, and is recessed from the height position of the first surface portion 8 in the thickness direction of the chip 2 (towards the second main surface 4).
  • the second surface portion 9 extends in a band shape along the first surface portion 8 in a plan view, and is formed in a ring shape (specifically, a square ring shape) surrounding the first surface portion 8.
  • the second surface portion 9 is connected to the first to fourth side surfaces 5A to 5D.
  • the second surface 9 is formed approximately parallel to the first surface 8, and has a flat surface extending horizontally.
  • the second surface 9 is formed by the c-plane (Si-plane).
  • the second surface 9 is formed in the first region 7 with a gap between it and the base region 6. In other words, the second surface 9 is recessed to a depth less than the thickness of the first region 7, exposing the first region 7.
  • the second surface portion 9 may have a depth of 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the second surface portion 9 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the second surface portion 9 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the first to fourth connection surface portions 10A to 10D extend in the vertical direction Z and are connected to the first surface portion 8 and the second surface portion 9.
  • the first connection surface portion 10A is located on the first side surface 5A side
  • the second connection surface portion 10B is located on the second side surface 5B side
  • the third connection surface portion 10C is located on the third side surface 5C side
  • the fourth connection surface portion 10D is located on the fourth side surface 5D side.
  • the first connection surface portion 10A and the second connection surface portion 10B extend in the first direction X and face the second direction Y.
  • the third connection surface portion 10C and the fourth connection surface portion 10D extend in the second direction Y and face the first direction X.
  • the mesa is defined in a protruding (convex) shape on the first main surface 3.
  • the mesa is formed only in the first region 7, and not in the base region 6.
  • the first to fourth connection surface portions 10A to 10D may extend almost vertically between the first surface portion 8 and the second surface portion 9, defining a mesa in the shape of a rectangular prism.
  • the first to fourth connection surface portions 10A to 10D may be inclined obliquely downward from the first surface portion 8 toward the second surface portion 9, defining a mesa in the shape of a truncated quadrangular pyramid.
  • the first to fourth connection surface portions 10A to 10D may be inclined at an angle of more than 90° and not more than 135° with respect to the first surface portion 8.
  • the semiconductor device 1 includes an active region 11 set in the chip 2.
  • the active region 11 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated.
  • the active region 11 is set in the inner part of the chip 2. Specifically, the active region 11 is set in the first surface portion 8.
  • the second region 13 is formed at a distance from the bottom (base region 6) of the first region 7 toward the first main surface 3 (first surface portion 8).
  • the second region 13 is formed in a region on the first main surface 3 (first surface portion 8) side of the first region 7 in a cross-sectional view, and is electrically connected to the first region 7.
  • the second region 13 is formed in a thickness range between the first main surface 3 (first surface portion 8) and the first region 7 in a cross-sectional view, and forms a pn junction with the first region 7.
  • the second region 13 is formed at a distance inward from the periphery of the first surface portion 8 (the first to fourth connection surface portions 10A to 10D), and has a periphery located within the active region 11.
  • the second region 13 may be exposed from at least one (for example, all) of the first to fourth connection surface portions 10A to 10D.
  • the second region 13 may be drawn from the first surface 8 to the second surface 9 across at least one (e.g., all) of the first to fourth connection surface portions 10A to 10D, and may be exposed from part or all of the second surface portion 9. In this case, the second region 13 may be exposed from at least one (e.g., all) of the first to fourth side surfaces 5A to 5D. Of course, the second region 13 may be formed spaced inward from at least one (e.g., all) of the first to fourth side surfaces 5A to 5D.
  • the distance between the upper ends of the first surface portion 8 and the second region 13 may be 0 ⁇ m or more and 1 ⁇ m or less.
  • the distance between the upper ends of the first surface portion 8 and the second region 13 may have a value that falls within any one of the ranges of 0 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, and 0.75 ⁇ m or more and 1 ⁇ m or less.
  • the distance between the bottom of the first region 7 and the bottom of the second region 13 may be greater than 0 ⁇ m and less than 10 ⁇ m.
  • the distance between the bottom of the first region 7 and the bottom of the second region 13 may have a value that falls within any one of the following ranges: greater than 0 ⁇ m and less than 1 ⁇ m, 1 ⁇ m or more and less than 2 ⁇ m, 2 ⁇ m or more and less than 4 ⁇ m, 4 ⁇ m or more and less than 6 ⁇ m, 6 ⁇ m or more and less than 8 ⁇ m, and 8 ⁇ m or more and less than 10 ⁇ m.
  • the thickness of the second region 13 is preferably less than the distance between the bottom of the first region 7 and the bottom of the second region 13. Of course, the thickness of the second region 13 may be greater than the distance between the bottom of the first region 7 and the bottom of the second region 13. Also, the second region 13 may have a bottom that crosses the boundary between the base region 6 and the first region 7 and is located within the base region 6.
  • the second region 13 may be formed by introducing a trivalent element (p-type impurity) into the n-type first region 7.
  • the second region 13 is preferably formed of a single impurity region extending in the thickness direction in a cross-sectional view.
  • the second region 13 may also be formed of multiple impurity regions introduced in a multi-stage stack in the thickness direction in a cross-sectional view.
  • the second region 13 may be a p-type channeling region that extends along the axial channel of the chip 2 (first region 7) in a cross-sectional view.
  • the axial channel is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal that constitutes the chip 2 (first region 7), and is surrounded by atomic rows that form a crystal axis that extends in the thickness direction (crystal growth direction).
  • the axial channel is a region in which the atomic rows are sparse extending in the thickness direction, and in which the atomic rows (atomic distance/atomic density) are sparse in the horizontal direction in a planar view.
  • the axial channel is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.
  • a low-index crystal axis is a crystal axis in which the absolute values of "a1", "a2", “a3” and "c" are all expressed as 2 or less (preferably 1 or less) with respect to the Miller indices (a1, a2, a3, c).
  • the axial channel consists of a region surrounded by atomic rows along the c-axis ((0001) axis) of the SiC single crystal.
  • the axial channel extends along the c-axis and has the off-direction and off-angle described above.
  • the axial channel is inclined from the vertical axis toward the off-direction by the off-angle.
  • the second region 13 When the second region 13 is a channeling region, the second region 13 may be an impurity region introduced parallel or nearly parallel to a region (axial channel) surrounded by atomic rows along a low-index crystal axis in the chip 2, and may be inclined obliquely with respect to the first main surface 3.
  • the second region 13 may be a p-type random region extending in a random direction intersecting the axial channel of the chip 2 (first region 7).
  • the random direction may be the vertical direction Z.
  • the semiconductor device 1 includes a plurality of trench-type (trench electrode-type) gate structures 15 formed on the first main surface 3 (first surface portion 8) in the active region 11.
  • the gate structures 15 may be referred to as “trench structures", “trench gate structures”, etc.
  • a gate potential is applied to the plurality of gate structures 15 as a control potential.
  • the plurality of gate structures 15 control the inversion and non-inversion of the channel in the second region 13 in response to the gate potential.
  • the multiple gate structures 15 are arranged on the first surface portion 8 with gaps between them inward from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D).
  • the extension direction of the multiple gate structures 15 coincides with the off-direction of the SiC single crystal.
  • the gate pitch may be 1 ⁇ m or more and 5 ⁇ m or less.
  • the gate pitch may have a value that belongs to at least one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the multiple gate structures 15 are formed on the first surface portion 8 so as to be positioned within the second region 13. Specifically, the multiple gate structures 15 are formed at intervals from the depth position of the bottom of the second region 13 toward the first surface portion 8. It is preferable that the multiple gate structures 15 cross the depth position of the middle portion of the second region 13.
  • the multiple gate structures 15 may be formed at intervals from the depth position of the middle part of the second region 13 toward the first surface portion 8. In this embodiment, the multiple gate structures 15 are formed almost perpendicular to the first surface portion 8. Of course, the multiple gate structures 15 may be formed in a tapered shape toward the bottom of the first region 7.
  • the side walls (long sides) of the multiple gate structures 15 are each formed by the m-plane ((1-100) plane) of the SiC single crystal.
  • the side walls (long sides) of the multiple gate structures 15 may each be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 15.
  • the side walls of the multiple gate structures 15 are formed approximately perpendicular to the first main surface 3.
  • the bottom walls of the multiple gate structures 15 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the multiple gate structures 15 extend almost flat along the horizontal direction. Of course, the bottom walls of the multiple gate structures 15 may be curved in an arc shape toward the second main surface 4.
  • the inclination angle (absolute value) of the side wall (long side) of the gate structure 15 relative to the vertical line may be 85° or more and 95° or less.
  • the inclination angle may have a value that belongs to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less.
  • the inclination angle is preferably 87° or more and 93° or less.
  • the gate structure 15 may have a width of 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the width of the gate structure 15 may have a value that falls within at least one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, and 1.75 ⁇ m or more and 2 ⁇ m or less.
  • the gate structure 15 may have a depth that is approximately equal to the depth of the second surface portion 9. Of course, the depth of the gate structure 15 may be greater than the depth of the second surface portion 9, or may be less than the depth of the second surface portion 9.
  • the depth of the gate structure 15 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the gate structure 15 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the gate structure 15 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the gate structure 15 may have an aspect ratio of 1 to 3.
  • the aspect ratio of the gate structure 15 is the ratio of the depth of the gate structure 15 to the width of the gate structure 15.
  • the aspect ratio may have a value that falls within at least one of the following ranges: 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. It is preferable that the aspect ratio is 1.5 to 2.5.
  • the configuration of one gate structure 15 is described below.
  • the gate structure 15 includes a trench 16, an insulating film 17, and a buried electrode 18.
  • the trench 16 is formed in the first surface portion 8, and defines the walls (side walls and bottom wall) of the gate structure 15.
  • the insulating film 17 covers the wall surface of the trench 16.
  • the insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 17 includes a silicon oxide film made of an oxide of the chip 2.
  • the insulating film 17 includes a first film portion and a second film portion.
  • the first film portion covers the sidewall of the trench 16 in a film-like manner.
  • the second film portion covers the bottom wall of the trench 16 in a film-like manner and is connected to the first film portion.
  • the second film portion has a thickness greater than the thickness of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion.
  • the insulating film 17 may have a thickness of 10 nm or more and 150 nm or less.
  • the thickness of the insulating film 17 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the buried electrode 18 is buried in the trench 16 with the insulating film 17 in between.
  • the buried electrode 18 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon.
  • the buried electrode 18 faces the second region 13 with the insulating film 17 in between.
  • the buried electrode 18 has an electrode surface exposed from the trench 16.
  • the electrode surface of the buried electrode 18 is located on the bottom wall side of the trench 16 relative to the height position of the first surface portion 8.
  • the electrode surface of the buried electrode 18 is located on the first main surface 3 side relative to the depth position of the bottom of the second region 13.
  • the electrode surface of the buried electrode 18 has a recess in an inner portion that tapers toward the bottom wall side of the trench 16.
  • the semiconductor device 1 includes a plurality of n-type source regions 20 (impurity regions) formed in the surface layer of the first main surface 3 (first surface portion 8) in the active region 11. A source potential is applied to the plurality of source regions 20.
  • the plurality of source regions 20 have an n-type impurity concentration higher than the n-type impurity concentration of the first region 7.
  • the n-type impurity concentration of the plurality of source regions 20 is higher than the p-type impurity concentration of the second region 13.
  • the multiple source regions 20 are formed in regions along the multiple gate structures 15 in the surface layer portion of the second region 13. Specifically, the multiple source regions 20 are formed in regions between the multiple gate structures 15, and extend in a strip shape along the multiple gate structures 15 in the second direction Y.
  • the multiple source regions 20 are formed on both sides of the multiple gate structures 15, respectively, and face the corresponding buried electrodes 18 across the corresponding insulating films 17.
  • the multiple source regions 20 have a bottom portion located on the bottom wall side of the gate structure 15 relative to the electrode surface of the buried electrode 18, and a surface portion located on the first surface 8 side relative to the electrode surface of the buried electrode 18. The surface portion of the source region 20 is exposed from the first surface 8.
  • the multiple source regions 20 are formed at intervals from the depth position of the bottom wall of the gate structure 15 toward the first surface portion 8, and extend in layers along the first surface portion 8. In other words, the multiple source regions 20 are formed in a region on the first surface portion 8 side with respect to the second region 13 in a cross-sectional view, and are electrically connected to the second region 13. In other words, the multiple source regions 20 are formed in a thickness range between the first surface portion 8 and the second region 13 in a cross-sectional view. The multiple source regions 20 are formed at intervals from the depth position of the second surface portion 9 toward the first surface portion 8.
  • the multiple source regions 20 are formed at intervals inward from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D). Therefore, the multiple source regions 20 are not exposed from the first to fourth connection surface portions 10A to 10D. Of course, the multiple source regions 20 may be exposed from the first to fourth connection surface portions 10A to 10D.
  • the semiconductor device 1 includes a plurality of p-type contact regions 21 formed in the surface layer of the first main surface 3 (first surface portion 8) in the active region 11.
  • the plurality of contact regions 21 have a p-type impurity concentration higher than the p-type impurity concentration of the second region 13.
  • the multiple contact regions 21 are formed in regions along the multiple gate structures 15 in the surface layer portion of the second region 13. Specifically, the multiple contact regions 21 are formed in regions outside the multiple source regions 20 between the multiple gate structures 15. In this embodiment, the multiple contact regions 21 are each interposed in the region between the multiple source regions 20 adjacent to each other, and each extend in a band shape in the second direction Y along the multiple gate structures 15.
  • the multiple contact regions 21 may be arranged at intervals in the second direction Y along the multiple gate structures 15. Also, the multiple contact regions 21 may have portions connected to the multiple gate structures 15.
  • the multiple contact regions 21 have bottom portions located on the bottom wall side of the gate structure 15 relative to the electrode surface of the buried electrode 18, and surface portions located on the first surface 8 side relative to the electrode surface of the buried electrode 18. The surface portions of the multiple contact regions 21 are exposed from the first surface 8. The bottoms of the multiple contact regions 21 are located on the bottom wall side of the gate structure 15 relative to the depth position of the bottoms of the multiple source regions 20. In other words, the multiple contact regions 21 are formed deeper than the multiple source regions 20.
  • the multiple contact regions 21 are formed at intervals from the depth position of the bottom wall of the gate structure 15 toward the first main surface 3 (first surface portion 8) and extend in layers along the first surface portion 8. That is, the multiple contact regions 21 are formed in a region on the first main surface 3 (first surface portion 8) side with respect to the second region 13 in a cross-sectional view, and are electrically connected to the second region 13. In other words, the multiple contact regions 21 are formed in a thickness range between the first main surface 3 (first surface portion 8) and the second region 13 in a cross-sectional view. The multiple contact regions 21 are formed at intervals from the depth position of the second surface portion 9 toward the first main surface 3 (first surface portion 8).
  • the multiple contact regions 21 are formed at intervals inward from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D). Therefore, the multiple contact regions 21 are not exposed from the first to fourth connection surface portions 10A to 10D. Of course, the multiple contact regions 21 may be exposed from the first to fourth connection surface portions 10A to 10D.
  • the semiconductor device 1 includes a plurality of n-type drift regions 25 formed in regions directly below a plurality of gate structures 15 within the chip 2.
  • the drift regions 25 may be referred to as "JFET (Junction Field Effect Transistor) sections," “JFET regions (layers),” etc.
  • the drift region 25 is formed by introducing a pentavalent element (n-type impurity) into the second region 13, and replaces the conductivity type of the second region 13 from p-type to n-type.
  • the drift region 25 has an n-type impurity concentration higher than the p-type impurity concentration of the second region 13.
  • the n-type impurity concentration of the drift region 25 may be higher than the n-type impurity concentration of the first region 7, or may be lower than the n-type impurity concentration of the first region 7.
  • the n-type impurity concentration of the drift region 25 is preferably lower than the n-type impurity concentration of the source region 20.
  • the multiple drift regions 25 are formed in the second region 13 at intervals in the horizontal direction (first direction X).
  • the multiple drift regions 25 are each formed in the thickness range between the bottom of the second region 13 and the bottom walls of the multiple gate structures 15, and overlap the multiple gate structures 15 in a one-to-one correspondence in the thickness direction.
  • the extension direction of the multiple drift regions 25 coincides with the off-direction of the SiC single crystal.
  • the multiple drift regions 25 may also extend in the first direction X.
  • the multiple drift regions 25 intersect (specifically, are perpendicular to) the off-direction.
  • multiple drift regions 25 may be spaced apart in the second direction Y and interposed in the region between the bottom of the second region 13 and the bottom wall of a corresponding one of the gate structures 15.
  • the multiple drift regions 25 may each extend in a band shape in the second direction Y in a plan view.
  • the drift pitch is approximately equal to the gate pitch of the multiple gate structures 15.
  • the drift pitch may be greater than the gate pitch or less than the gate pitch.
  • the drift pitch may be 1 ⁇ m or more and 5 ⁇ m or less.
  • the drift pitch may have a value that falls within at least one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the ratio of the drift pitch to the gate pitch may be 0.8 or more and 1.2 or less.
  • the pitch ratio may have a value that falls within any one of the following ranges: 0.8 or more and 0.85 or less, 0.85 or more and 0.9 or less, 0.9 or more and 0.95 or less, 0.95 or more and 1 or less, 1 or more and 1.05 or less, 1.05 or more and 1.1 or less, 1.1 or more and 1.15 or less, and 1.15 or more and 1.2 or less.
  • the pitch ratio is preferably 0.9 or more and 1.1 or less.
  • the multiple drift regions 25 are formed at intervals from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D) toward the inside of the first surface portion 8. Both ends of the multiple drift regions 25 may be located on the inside side of the gate structure 15 relative to both ends of the gate structure 15. Both ends of the multiple drift regions 25 may be located on the periphery side of the first surface portion 8 relative to both ends of the gate structure 15.
  • the drift region 25 has a width greater than the width of the gate structure 15, and extends from the region directly below to both sides of the gate structure 15.
  • the width of the drift region 25 may be less than the width of the gate structure 15.
  • the drift region 25 is formed in a columnar shape extending horizontally along the first surface portion 8 in a cross-sectional view.
  • the drift region 25 has an aspect ratio of less than 1.
  • the aspect ratio is the ratio of the depth of the drift region 25 to the width of the drift region 25.
  • the aspect ratio may have a value that belongs to at least one of the following ranges: greater than 0 and less than 0.25, 0.25 or more and less than 0.5, 0.5 or more and less than 0.75, and 0.75 or more and less than 1.
  • the drift region 25 may be formed in a columnar shape extending in the thickness direction of the chip 2 in a cross-sectional view.
  • the drift region 25 may have an aspect ratio of 1 or more.
  • the aspect ratio may be 1 or more and 3 or less.
  • the aspect ratio may have a value that belongs to at least one of the following ranges: 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, and 2.75 or more and 3 or less.
  • the drift region 25 is preferably formed by a single impurity region extending in the thickness direction in a cross-sectional view.
  • the first drift region 26 may be formed by multiple impurity regions that are layered and introduced in multiple stages in the thickness direction in a cross-sectional view.
  • the drift region 25 has an upper end located on the bottom wall side of the gate structure 15, and a lower end (bottom) located on the bottom side of the second region 13.
  • the upper end of the drift region 25 is connected to the bottom wall of the gate structure 15 and faces the buried electrode 18 in the vertical direction Z, sandwiching the insulating film 17 therebetween.
  • the upper end of the drift region 25 has an extension that protrudes from the region directly below the gate structure 15 to both sides of the gate structure 15 and extends along the sidewalls of the gate structure 15 toward the first surface portion 8.
  • the extensions of the drift region 25 extend in the vertical direction Z. It is preferable that the thickness in the horizontal direction (first direction X) of the portion of the drift region 25 that runs along the sidewall of the gate structure 15 (extension) is less than the thickness in the vertical direction Z of the portion of the drift region 25 that runs along the bottom wall of the gate structure 15.
  • the upper end of the drift region 25 preferably has an edge that is located closer to the gate structure 15 than the edge of the source region 20 on the opposite side to the gate structure 15. In other words, it is preferable that the upper end of the drift region 25 does not face the contact region 21 in the thickness direction.
  • the upper end of the drift region 25 may have a portion that partially faces the edge of the contact region 21 in the thickness direction.
  • the extension of the drift region 25 faces the buried electrode 18 across the insulating film 17 in the horizontal direction (first direction X).
  • the extension of the drift region 25 is formed at intervals from the bottom of the multiple source regions 20 toward the bottom wall side of the gate structure 15, and faces the source region 20 across a part of the second region 13.
  • the drift region 25, together with the multiple source regions 20, defines the channel of the transistor structure Tr in the second region 13.
  • the drift region 25 forms a current path that connects the first region 7 and the multiple source regions 20 via the channel.
  • the inversion and non-inversion of the channel is controlled by the gate structure 15. It is preferable that the extension of the drift region 25 is located on the bottom wall side of the gate structure 15 with respect to the depth position of the middle part of the gate structure 15.
  • the lower end of the drift region 25 crosses the bottom of the second region 13 and is directly connected to the first region 7. This electrically connects the drift region 25 to the first region 7. It is preferable that the lower end of the drift region 25 is located closer to the bottom of the second region 13 than the depth position of the intermediate portion between the bottom of the first region 7 and the bottom of the second region 13. Of course, the lower end of the drift region 25 may also be located closer to the first region 7 than the depth position of the intermediate portion between the bottom of the first region 7 and the bottom of the second region 13.
  • the depth of the drift region 25 may be equal to or greater than the distance between the bottom of the second region 13 and the bottom wall of the gate structure 15.
  • the depth of the drift region 25 may be equal to or less than 1, 1.25, 1.5, 1.75, or 2 times the distance between the bottom of the second region 13 and the bottom wall of the gate structure 15.
  • the semiconductor device 1 includes a plurality of p-type high concentration regions 30 formed on the sides of the plurality of gate structures 15 in the chip 2.
  • the plurality of high concentration regions 30 are formed by introducing a trivalent element (p-type impurity) into the second region 13, and have a p-type impurity concentration higher than the p-type impurity concentration of the second region 13.
  • the p-type impurity concentration of the high concentration regions 30 may be higher than the p-type impurity concentration of the contact region 21, or may be lower than the p-type impurity concentration of the contact region 21.
  • the extension direction of the multiple high concentration regions 30 coincides with the off direction of the SiC single crystal.
  • the multiple high concentration regions 30 may also extend in the first direction X.
  • the multiple high concentration regions 30 intersect (specifically, are perpendicular to) the off direction.
  • the multiple high concentration regions 30 may be formed at intervals in the second direction Y in the region between the multiple adjacent gate structures 15.
  • the multiple high concentration regions 30 may each be formed in a band shape extending in the second direction Y in a plan view.
  • the multiple high concentration regions 30 are formed at intervals from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D) toward the inside of the first surface portion 8. Both ends of the multiple high concentration regions 30 may be located on the inside side of the multiple gate structures 15 relative to both ends of the multiple gate structures 15. Both ends of the multiple high concentration regions 30 may be located on the periphery side of the first surface portion 8 relative to both ends of the multiple gate structures 15.
  • the configuration of one high concentration region 30 is described below.
  • the high concentration region 30 is formed at a distance from the multiple gate structures 15 in the horizontal direction (first direction X).
  • the high concentration region 30 is formed in a columnar shape extending in the thickness direction of the chip 2 (vertical direction Z).
  • the high concentration region 30 faces at least the portion of the gate structure 15 where the channel is formed.
  • the high concentration region 30 has a portion that faces the gate structure 15 in the horizontal direction, sandwiching a portion of the second region 13 therebetween, and a portion that faces the drift region 25 in the horizontal direction, sandwiching a portion of the second region 13 therebetween.
  • the high concentration region 30 has an upper end on the first surface portion 8 side and a lower end on the bottom side of the second region 13.
  • the upper end of the high concentration region 30 is located on the first surface portion 8 side with respect to the depth position of the bottom wall of the gate structure 15.
  • the upper end of the high concentration region 30 is located on the first surface portion 8 side with respect to the depth position of the second surface portion 9.
  • the upper end of the high concentration region 30 is located on the first surface portion 8 side with respect to the depth position of the upper end (extension) of the drift region 25.
  • the upper end of the high concentration region 30 is formed at a distance from the first surface portion 8 to the bottom side of the second region 13, and faces the gate structure 15 in the horizontal direction (first direction X) across a part of the second region 13.
  • the upper end of the high concentration region 30 is formed at a distance from the bottom of the source region 20 to the bottom side of the second region 13.
  • the upper end of the high concentration region 30 is formed at a distance from the bottom of the contact region 21 to the bottom side of the second region 13.
  • the high concentration region 30 has a width greater than the width of the contact region 21. Therefore, the upper end of the high concentration region 30 has a portion that faces the entire contact region 21 across a portion of the second region 13, and a portion that faces the source region 20 across a portion of the second region 13.
  • the high concentration region 30 is electrically connected to the contact region 21 through a portion of the second region 13.
  • the high concentration region 30 may have a width less than the width of the contact region 21 and face either or both of the source region 20 and the contact region 21.
  • the width of the high concentration region 30 may be less than the width of the gate structure 15 or may be greater than the width of the gate structure 15.
  • the width of the high concentration region 30 may be less than the width of the drift region 25 or may be greater than the width of the drift region 25.
  • the width of the high concentration region 30 may be 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the width of the high concentration region 30 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, and 1.75 ⁇ m or more and 2 ⁇ m or less.
  • the upper end of the high concentration region 30 may be formed with a distance of more than 0 ⁇ m and not more than 1.5 ⁇ m from the bottom of the contact region 21.
  • the distance between the upper end of the high concentration region 30 and the bottom of the contact region 21 may have a value that belongs to at least one of the following ranges: more than 0 ⁇ m and not more than 0.1 ⁇ m, 0.1 ⁇ m to 0.25 ⁇ m, 0.25 ⁇ m to 0.5 ⁇ m, 0.5 ⁇ m to 0.75 ⁇ m, 0.75 ⁇ m to 1 ⁇ m, 1 ⁇ m to 1.25 ⁇ m, and 1.25 ⁇ m to 1.5 ⁇ m.
  • the lower end of the high concentration region 30 is located on the bottom side of the second region 13 with respect to the depth position of the upper end (extension) of the drift region 25.
  • the lower end of the high concentration region 30 is located on the bottom side of the second region 13 with respect to the depth position of the bottom wall of the gate structure 15.
  • the lower end of the high concentration region 30 is located on the bottom side of the second region 13 with respect to the depth position of the second surface portion 9.
  • the lower end of the high concentration region 30 may be located on the first surface portion 8 with respect to the depth position of the second surface portion 9.
  • the lower end of the high concentration region 30 is located on the bottom wall side (first surface portion 8 side) of the gate structure 15 with respect to the depth position of the bottom of the second region 13.
  • the lower end of the high concentration region 30 faces the first region 7 in the thickness direction, sandwiching a part of the second region 13 therebetween, and faces the drift region 25 in the horizontal direction (first direction X), sandwiching a part of the second region 13 therebetween.
  • the lower end of the high concentration region 30 may be formed with a distance of more than 0 ⁇ m and not more than 5 ⁇ m from the bottom of the second region 13.
  • the distance between the lower end of the high concentration region 30 and the bottom of the second region 13 may have a value that belongs to at least one of the following ranges: more than 0 ⁇ m and not more than 0.5 ⁇ m, 0.5 ⁇ m to 1 ⁇ m, 1 ⁇ m to 1.5 ⁇ m, 1.5 ⁇ m to 2 ⁇ m, 2 ⁇ m to 2.5 ⁇ m, 2.5 ⁇ m to 3 ⁇ m, 3 ⁇ m to 3.5 ⁇ m, 3.5 ⁇ m to 4 ⁇ m, 4 ⁇ m to 4.5 ⁇ m, and 4.5 ⁇ m to 5 ⁇ m.
  • the high concentration region 30 may cross the depth position of the middle part of the second region 13.
  • the upper end of the high concentration region 30 may be located on the first surface portion 8 side relative to the depth position of the middle part of the second region 13
  • the lower end of the high concentration region 30 may be located on the bottom side of the second region 13 relative to the depth position of the middle part of the second region 13.
  • the ratio (depth ratio) of the depth of the high concentration region 30 to the depth of the gate structure 15 may be 0.1 or more and 2 or less.
  • the depth ratio may have a value that belongs to at least one of the following ranges: 0.1 or more and 0.25 or less, 0.25 or more and 0.5 or less, 0.5 or more and 1 or less, 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, and 1.75 or more and 2 or less.
  • the depth of the high concentration region 30 may be greater than 0 ⁇ m and less than 5 ⁇ m.
  • the depth of the high concentration region 30 may have a value that falls within at least one of the following ranges: greater than 0 ⁇ m and less than 0.5 ⁇ m, 0.5 ⁇ m to 1 ⁇ m, 1 ⁇ m to 1.5 ⁇ m, 1.5 ⁇ m to 2 ⁇ m, 2 ⁇ m to 2.5 ⁇ m, 2.5 ⁇ m to 3 ⁇ m, 3 ⁇ m to 3.5 ⁇ m, 3.5 ⁇ m to 4 ⁇ m, 4 ⁇ m to 4.5 ⁇ m, and 4.5 ⁇ m to 5 ⁇ m.
  • the semiconductor device 1 includes a plurality of p-type middle regions 31 formed in the second region 13.
  • Each of the plurality of middle regions 31 is made up of an area partitioned by a plurality of drift regions 25 in the second region 13.
  • each of the plurality of middle regions 31 includes a portion of the second region 13 and a portion of the high concentration region 30.
  • the extension direction of the multiple middle regions 31 coincides with the off-direction of the SiC single crystal.
  • the multiple middle regions 31 may also extend in the first direction X. In this case, the multiple middle regions 31 intersect (specifically, perpendicular to) the off-direction.
  • the middle region 31 has a width greater than the width of the drift region 25.
  • the width of the middle region 31 may be approximately equal to the width of the drift region 25, or may be less than the width of the drift region 25.
  • the ratio of the width of the middle region 31 to the width of the drift region 25 may be 0.5 or more and 4 or less.
  • the width ratio may have a value belonging to at least one of the following ranges: 0.5 to 0.75, 0.75 to 1, 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, 2.75 to 3, 3 to 3.25, 3.25 to 3.5, 3.5 to 3.75, and 3.75 to 4.
  • the width ratio is preferably 0.75 to 2.25.
  • the multiple middle regions 31 do not necessarily have to form a superjunction structure, and may simply form a body diode structure together with the first region 7 and the multiple drift regions 25.
  • the semiconductor device 1 includes a main surface insulating film 35 that covers the first main surface 3.
  • the main surface insulating film 35 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the main surface insulating film 35 preferably includes the same type of insulating material as the insulating film 17.
  • the main surface insulating film 35 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 35 includes a silicon oxide film made of an oxide of the chip 2.
  • the main surface insulating film 35 selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D.
  • the main surface insulating film 35 is selectively connected to the insulating films 17 of the multiple gate structures 15 on the first surface portion 8, exposing the buried electrodes 18 of the multiple gate structures 15.
  • the main surface insulating film 35 is continuous with the first to fourth side surfaces 5A to 5D at the periphery of the second surface 9.
  • the main surface insulating film 35 may be formed at a distance inward from the periphery of the second surface 9, exposing the periphery of the second surface 9.
  • the semiconductor device 1 includes an insulating interlayer film 36 that covers the main surface insulating film 35.
  • the interlayer film 36 may be called an "insulating film,” an "interlayer insulating film,” an “intermediate insulating film,” or the like.
  • the interlayer film 36 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the interlayer film 36 include a silicon oxide film.
  • the interlayer film 36 selectively covers the first surface 8, the second surface 9, and the first to fourth connection surface portions 10A to 10D, sandwiching the main surface insulating film 35.
  • the interlayer film 36 covers the multiple gate structures 15 (buried electrodes 18) on the first surface 8.
  • the interlayer film 36 is continuous with the first to fourth side surfaces 5A to 5D at the periphery of the second surface 9.
  • the interlayer film 36 may be formed at a distance inward from the periphery of the second surface 9, exposing the periphery of the second surface 9.
  • the interlayer film 36 may have a thickness of 0.5 ⁇ m or more and 3 ⁇ m or less.
  • the thickness of the interlayer film 36 may have a value that falls within at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the semiconductor device 1 includes a plurality of source openings 37 formed in the interlayer film 36.
  • the plurality of source openings 37 are formed in the regions between the plurality of gate structures 15, respectively, and expose the corresponding plurality of source regions 20 and the corresponding contact regions 21.
  • the plurality of source openings 37 each extend in a band shape along the plurality of gate structures 15 in the second direction Y. It is preferable that the plurality of source openings 37 each have an opening end curved in an arc shape.
  • the multiple source openings 37 may be formed in a one-to-many correspondence with the regions between the multiple gate structures 15. In this case, the multiple source openings 37 may be formed at intervals in the second direction Y in the regions between the multiple gate structures 15. Furthermore, in this case, the multiple source openings 37 may be formed in a quadrangular shape, a rectangular shape (strip shape) extending in the first direction X, a rectangular shape (strip shape) extending in the second direction Y, a circular shape, etc. in a plan view.
  • the semiconductor device 1 includes a plurality of gate openings 38 formed in the interlayer film 36 (see FIG. 4).
  • the plurality of gate openings 38 expose a corresponding one of the gate structures 15 in a one-to-many correspondence.
  • the plurality of gate openings 38 are formed at both ends of the plurality of gate structures 15 (buried electrodes 18), respectively, and expose one end or the other end of the corresponding gate structure 15 (buried electrode 18).
  • the multiple gate openings 38 preferably each have an opening end curved in an arc, similar to the source opening 37.
  • the multiple gate openings 38 may be formed in a quadrangular shape, a rectangular shape (strip shape) extending in the first direction X, a rectangular shape (strip shape) extending in the second direction Y, a circular shape, etc., in a plan view.
  • the semiconductor device 1 includes a source electrode 40 disposed on the first main surface 3.
  • the source electrode 40 is a terminal electrode to which a source potential is applied from the outside.
  • the source electrode 40 may also be referred to as a "source pad electrode,” a “first pad electrode,” a “first main surface electrode,” a “first terminal electrode,” etc.
  • the source electrode 40 is disposed on a portion of the interlayer film 36 that covers the first surface portion 8.
  • the source electrode 40 has a first pad portion 40a, a second pad portion 40b, and a third pad portion 40c.
  • the first pad portion 40a has a relatively large planar area and forms the main body of the source electrode 40.
  • the first pad portion 40a is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is biased toward the fourth side surface 5D relative to the center of the first surface portion 8.
  • the second pad portion 40b has a planar area less than that of the first pad portion 40a, and is drawn out in a strip (rectangular) shape from one end of the first pad portion 40a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C.
  • the third pad portion 40c has a planar area less than that of the first pad portion 40a, and is drawn out in a strip (rectangular) shape from the other end of the first pad portion 40a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 40b in the second direction Y.
  • the plane area of the third pad portion 40c may be approximately equal to the plane area of the second pad portion 40b. Of course, the plane area of the third pad portion 40c may be greater than the plane area of the second pad portion 40b, or may be less than the plane area of the second pad portion 40b. Either or both of the second pad portion 40b and the third pad portion 40c may be used as a terminal portion for monitoring a current.
  • the source electrode 40 does not necessarily have to have both the second pad portion 40b and the third pad portion 40c at the same time.
  • the source electrode 40 may have only one of the second pad portion 40b and the third pad portion 40c.
  • the source electrode 40 may be composed of only the first pad portion 40a and may not have both the second pad portion 40b and the third pad portion 40c.
  • the source electrode 40 extends from above the interlayer film 36 into the multiple source openings 37 and is electrically connected to the multiple source regions 20 and multiple contact regions 21 within the multiple source openings 37.
  • the first electrode film 43 has a thickness less than the thickness of the interlayer film 36.
  • the thickness of the first electrode film 43 may be 10 nm or more and 100 nm or less.
  • the thickness of the first electrode film 43 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.
  • the second electrode film 44 has a thickness less than the thickness of the interlayer film 36.
  • the thickness of the second electrode film 44 is preferably greater than the thickness of the first electrode film 43.
  • the thickness of the second electrode film 44 may be 50 nm or more and 200 nm or less.
  • the thickness of the second electrode film 44 may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.
  • the first electrode film 43 collectively covers the region of the interlayer film 36 in which the multiple source openings 37 are formed, and extends from above the interlayer film 36 into the multiple source openings 37.
  • the first electrode film 43 has a portion that covers the insulating main surface of the interlayer film 36 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 37 in a film-like manner, and a portion that covers the first main surface 3 in the multiple source openings 37 in a film-like manner.
  • the first electrode film 43 covers the first main surface 3 (first surface portion 8) in the source openings 37 in a film-like manner, and is mechanically and electrically connected to the multiple source regions 20 and the multiple contact regions 21.
  • the second electrode film 44 directly covers the first electrode film 43.
  • the second electrode film 44 collectively covers the area of the interlayer film 36 in which the multiple source openings 37 are formed, sandwiching the first electrode film 43 between them, and penetrates into the multiple source openings 37 from above the interlayer film 36.
  • the second electrode film 44 has a portion that covers the insulating main surface of the interlayer film 36 in a film-like manner by sandwiching the first electrode film 43 therebetween, a portion that covers the wall surfaces of the multiple source openings 37 in a film-like manner by sandwiching the first electrode film 43 therebetween, and a portion that covers the first main surface 3 in a film-like manner by sandwiching the first electrode film 43 therebetween within the multiple source openings 37.
  • the second electrode film 44 covers the first main surface 3 (first surface portion 8) in a film-like manner by sandwiching the first electrode film 43 therebetween within the source openings 37, and is electrically connected to the multiple source regions 20 and the multiple contact regions 21 via the first electrode film 43.
  • the main electrode film 42 contains a conductive material different from that of the lower electrode film 41 (the first electrode film 43 and the second electrode film 44).
  • the main electrode film 42 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the main electrode film 42 has a thickness greater than the thickness (total thickness) of the lower electrode film 41.
  • the thickness of the main electrode film 42 is preferably greater than the thickness of the interlayer film 36.
  • the thickness of the main electrode film 42 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the main electrode film 42 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the main electrode film 42 directly covers the lower electrode film 41 (second electrode film 44).
  • the main electrode film 42 backfills the multiple source openings 37, and collectively covers the area of the interlayer film 36 in which the multiple source openings 37 are formed.
  • the main electrode film 42 has a portion that covers the insulating main surface of the interlayer film 36 with the lower electrode film 41 in between, a portion that covers the wall surfaces of the multiple source openings 37 with the lower electrode film 41 in between, and a portion that covers the first main surface 3 with the lower electrode film 41 in between.
  • the main electrode film 42 covers the first main surface 3 (first surface portion 8) within the source opening 37, sandwiching the lower electrode film 41, and is electrically connected to the multiple source regions 20 and the multiple contact regions 21 via the lower electrode film 41.
  • the semiconductor device 1 includes a gate electrode 45 disposed on the first main surface 3.
  • the gate electrode 45 is a terminal electrode to which a gate potential is applied from the outside.
  • the gate electrode 45 may also be referred to as a "second pad electrode,” a “second main surface electrode,” a “second terminal electrode,” etc.
  • the gate electrode 45 includes a lower electrode film 41 and a main electrode film 42 that are stacked in this order from the chip 2 side, similar to the source electrode 40.
  • the gate electrode 45 is disposed on a portion of the interlayer film 36 that covers the first surface portion 8, spaced apart from the source electrode 40.
  • the gate electrode 45 is disposed in a region on the third side surface 5C side of the first pad portion 40a, and faces the first pad portion 40a in the first direction X.
  • the gate electrode 45 is also interposed in a region between the second pad portion 40b and the third pad portion 40c, and faces both the second pad portion 40b and the third pad portion 40c in the second direction Y.
  • the gate electrode 45 is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the gate electrode 45 has a planar area less than the planar area of the source electrode 40.
  • the gate electrode 45 has a planar area less than the planar area of the first pad portion 40a.
  • the gate electrode 45 may have a planar area less than the planar area of the second pad portion 40b (third pad portion 40c).
  • the gate electrode 45 partially faces the multiple gate structures 15 across the interlayer film 36. Specifically, the gate electrode 45 is disposed spaced inward from both ends of the multiple gate structures 15, and faces the inner parts of the multiple gate structures 15 across the interlayer film 36. In this form, the gate electrode 45 does not have any direct electrical connection to the multiple gate structures 15.
  • the gate electrode 45 may be electrically connected to the multiple gate structures 15 via the multiple gate openings 38.
  • the portions of the multiple gate structures 15 that are located at the gate electrode 45 may be removed.
  • the gate electrode 45 may face the second region 13 with the main surface insulating film 35 and the interlayer film 36 sandwiched therebetween.
  • the semiconductor device 1 includes a gate wiring 46 extending from the gate electrode 45 onto the first main surface 3.
  • the gate wiring 46 may also be referred to as a "gate finger” or “gate finger electrode.”
  • the gate wiring 46 transmits the gate potential applied to the gate electrode 45 to other regions.
  • the gate wiring 46 includes a lower electrode film 41 and a main electrode film 42, which are stacked in this order from the chip 2 side, similar to the source electrode 40 (gate electrode 45).
  • the gate wiring 46 is drawn out from the gate electrode 45 onto the portion of the interlayer film 36 that covers the first surface 8.
  • the gate wiring 46 is routed in a strip shape in the region between the periphery of the first surface 8 and the source electrode 40.
  • the gate wiring 46 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y.
  • the gate wiring 46 is formed in a strip shape with ends having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 40.
  • the gate wiring 46 intersects (specifically, perpendicular to) the ends (both ends in this embodiment) of the multiple gate structures 15.
  • the gate wiring 46 enters the multiple gate openings 38 from above the interlayer film 36, and is mechanically and electrically connected to the ends (both ends) of the multiple gate structures 15 (buried electrodes 18) within the multiple gate openings 38.
  • the gate potential applied to the gate electrode 45 is applied to the multiple gate structures 15 via the gate wiring 46.
  • the semiconductor device 1 includes a drain electrode 47 covering the second main surface 4.
  • the drain electrode 47 is a terminal electrode to which a drain potential is applied from the outside.
  • the drain electrode 47 may be referred to as a "third pad electrode,” a “third main surface electrode,” a “third terminal electrode,” etc.
  • the drain electrode 47 is electrically connected to the base region 6.
  • the drain electrode 47 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (the first to fourth side surfaces 5A to 5D).
  • the drain electrode 47 may partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.
  • the breakdown voltage that can be applied between the source electrode 40 and the drain electrode 47 (between the first major surface 3 and the second major surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that belongs to at least one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • FIG. 8A to 8O are enlarged cross-sectional views showing the high concentration region 30 according to the second to sixteenth embodiment examples.
  • the semiconductor device 1 can include any one of the high concentration regions 30 according to the first to sixteenth embodiment examples.
  • the features of the high concentration region 30 according to the first to sixteenth embodiments can be combined as appropriate.
  • the semiconductor device 1 can simultaneously include at least two of the features of the high concentration region 30 according to the first to sixteenth embodiments in the same or different regions.
  • the high concentration region 30 may be located on the first surface 8 side with respect to the depth position of the bottom of the contact region 21, and may have an upper end connected to the contact region 21.
  • the upper end of the high concentration region 30 may be located on the first surface 8 side with respect to the depth positions of the bottoms of the multiple source regions 20, and may be connected to the multiple source regions 20.
  • the upper end of the high concentration region 30 may be formed with a gap from the first surface 8 to the bottom side of the second region 13.
  • the upper end of the high concentration region 30 may be exposed from the first surface portion 8 in the case of the second embodiment.
  • the upper end of the high concentration region 30 may overlap a part or the entire area of the contact region 21.
  • the upper end of the high concentration region 30 may be formed as the contact region 21, and the contact region 21 may be omitted.
  • the upper end of the high concentration region 30 may be formed at a distance from the bottom of the multiple source regions 20 toward the bottom of the second region 13, and may be connected to the contact region 21 in the region between the bottom of the second region 13 (depth position of the bottom wall of the gate structure 15) and the bottom of the multiple source regions 20.
  • the high concentration region 30 may cross the bottom of the second region 13 and have a lower end located within the first region 7. In other words, the high concentration region 30 may be directly electrically connected to the first region 7.
  • the lower end of the high concentration region 30 may be located closer to the bottom of the first region 7 than the lower ends of the multiple drift regions 25, or closer to the bottom of the second region 13 than the lower ends of the multiple drift regions 25. It is preferable that the lower end of the high concentration region 30 is located closer to the bottom of the second region 13 than the depth position of the intermediate portion between the bottom of the first region 7 and the bottom of the second region 13.
  • the high concentration region 30 may have an upper end connected to the contact region 21, as in any one of the second to fourth embodiments.
  • the high concentration region 30 may have a lower end formed at a distance from the depth position of the bottom walls of the multiple gate structures 15 toward the first surface portion 8. In other words, the entire area of the high concentration region 30 may be located in the area between the multiple gate structures 15.
  • the high concentration region 30 may have either or both of a portion facing the gate structure 15 in the horizontal direction (first direction X) and a portion facing the drift region 25 in the horizontal direction (first direction X).
  • the high concentration region 30 may only have a portion facing the gate structure 15 in the horizontal direction (first direction X), and may not have a portion facing the drift region 25 in the horizontal direction (first direction X).
  • the high concentration region 30 may have an upper end connected to the contact region 21, as in any one of the second to fourth embodiments.
  • the high concentration region 30 may have an upper end formed at a distance from the depth position of the bottom walls of the multiple gate structures 15 toward the bottom of the second region 13. In other words, the entire high concentration region 30 may be located closer to the bottom of the second region 13 than the depth position of the bottom walls of the multiple gate structures 15.
  • the high concentration region 30 does not have a portion facing the gate structure 15 in the horizontal direction (first direction X), and only has a portion facing the drift region 25 in the horizontal direction (first direction X). In other words, in this embodiment, the high concentration region 30 is formed only in the region between multiple adjacent drift regions 25.
  • the high concentration region 30 may cross the bottom of the second region 13 and have a lower end located within the first region 7, as in the fifth embodiment.
  • the high concentration region 30 may have a low concentration portion 50 extending in the thickness direction in the inner portion, and may be separated by the low concentration portion 50 into a first high concentration portion 51 on one side of the first direction X, and a second high concentration portion 52 on the other side of the first direction X.
  • the low concentration portion 50 may be formed by a part of the second region 13, and may have a p-type impurity concentration higher than the p-type impurity concentration of the second region 13.
  • the low concentration portion 50 may be formed in a band shape extending along the multiple gate structures 15 in a planar view. In this case, the low concentration portion 50 may separate the high concentration region 30 into a first high concentration portion 51 and a second high concentration portion 52 over the entire area of the high concentration region 30.
  • the first high concentration portion 51 has a p-type impurity concentration higher than the p-type impurity concentration of the low concentration portion 50.
  • the first high concentration portion 51 is formed at a distance from the one and other gate structures 15, and is biased toward the one gate structure 15 side.
  • the first high concentration portion 51 is formed at a distance from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D) toward the inside of the first surface portion 8. Both ends of the first high concentration portion 51 may be located on the inside side of one gate structure 15 relative to both ends of one gate structure 15. Both ends of the first high concentration portion 51 may be located on the periphery side of the first surface portion 8 relative to both ends of one gate structure 15.
  • the first high concentration portion 51 is formed in a columnar shape extending in the thickness direction (vertical direction Z) of the chip 2.
  • the first high concentration portion 51 faces a portion of at least one of the gate structures 15 in which a channel is formed.
  • the first high concentration portion 51 has a portion that faces one of the gate structures 15 in the horizontal direction, sandwiching a portion of the second region 13 therebetween, and a portion that faces the drift region 25 in the horizontal direction, sandwiching a portion of the second region 13 therebetween.
  • the second high concentration portion 52 is formed with a space between one and the other gate structure 15, and is biased toward the other gate structure 15.
  • the second high concentration portion 52 faces the first high concentration portion 51 in the horizontal direction (first direction X) across the low concentration portion 50.
  • the second high concentration portion 52 is formed at a distance from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D) toward the inside of the first surface portion 8. Both ends of the second high concentration portion 52 may be located on the inside side of the other gate structure 15 relative to both ends of the other gate structure 15. Both ends of the second high concentration portion 52 may be located on the periphery side of the first surface portion 8 relative to both ends of the other gate structure 15.
  • the second high concentration portion 52 is formed in a columnar shape extending in the thickness direction (vertical direction Z) of the chip 2.
  • the second high concentration portion 52 faces at least a portion of the other gate structure 15 in which a channel is formed.
  • the second high concentration portion 52 has a portion that faces the other gate structure 15 in the horizontal direction across a portion of the second region 13, and a portion that faces the drift region 25 in the horizontal direction across a portion of the second region 13.
  • the second high concentration section 52 may have a length in the thickness direction that is approximately equal to the length of the first high concentration section 51, and may face the first high concentration section 51 across the entire thickness direction, sandwiching the low concentration section 50 between them.
  • the second high concentration section 52 may have a length in the thickness direction that is different from the length of the first high concentration section 51, and may face part or the entire first high concentration section 51 across the low concentration section 50 between them.
  • the length of the second high concentration section 52 may be greater than the length of the first high concentration section 51, or may be less than the length of the first high concentration section 51.
  • the upper end of the first high concentration portion 51 forms part of the upper end of the high concentration region 30, and the upper end of the first high concentration portion 51 forms part of the lower end of the high concentration region 30.
  • the upper end of the second high concentration portion 52 forms part of the upper end of the high concentration region 30, and the upper end of the second high concentration portion 52 forms part of the lower end of the high concentration region 30.
  • the upper end of the second high concentration portion 52 is located at a depth position that is approximately equal to the upper end of the first high concentration portion 51.
  • the upper end of the second high concentration portion 52 may be located closer to the first surface portion 8 than the depth position of the upper end of the first high concentration portion 51, or may be located closer to the bottom of the second region 13 than the depth position of the upper end of the first high concentration portion 51.
  • the lower end of the second high concentration portion 52 is located at a depth position that is approximately equal to the lower end of the first high concentration portion 51.
  • the lower end of the second high concentration portion 52 may be located closer to the first surface portion 8 than the depth position of the lower end of the first high concentration portion 51, or may be located closer to the bottom of the second region 13 than the depth position of the lower end of the first high concentration portion 51.
  • the upper ends of the first and second high concentration portions 51, 52 are located on the first surface portion 8 side with respect to the depth position of the bottom wall of the gate structure 15.
  • the upper ends of the first and second high concentration portions 51, 52 are located on the first surface portion 8 side with respect to the depth position of the second surface portion 9.
  • the upper ends of the first and second high concentration portions 51, 52 are located on the first surface portion 8 side with respect to the depth position of the upper end (extension portion) of the drift region 25.
  • the upper ends of the first and second high concentration portions 51, 52 are formed at intervals from the first surface portion 8 to the bottom side of the second region 13, and face the gate structure 15 in the horizontal direction (first direction X) across a part of the second region 13.
  • the upper ends of the first and second high concentration portions 51, 52 are formed at intervals from the bottom of the source region 20 to the bottom side of the second region 13.
  • the upper ends of the first and second high concentration portions 51, 52 are formed at intervals from the bottom of the contact region 21 to the bottom side of the second region 13.
  • the first and second high concentration portions 51, 52 have a width less than the width of the contact region 21, and face either or both of a part of the source region 20 and a part of the contact region 21, sandwiching a part of the second region 13 therebetween.
  • the width of the first and second high concentration portions 51, 52 may be greater than the width of the contact region 21.
  • the first and second high concentration portions 51, 52 are electrically connected to the contact region 21 via a part of the second region 13.
  • the width of the first and second high concentration portions 51, 52 may be less than the width of the gate structure 15 or may be greater than the width of the gate structure 15.
  • the width of the first and second high concentration portions 51, 52 may be less than the width of the drift region 25 or may be greater than the width of the drift region 25.
  • the width of the first and second high concentration portions 51, 52 may be greater than 0 ⁇ m and less than 2 ⁇ m.
  • the width of the first and second high concentration portions 51, 52 may have a value that belongs to at least one of the following ranges: greater than 0 ⁇ m and less than 0.1 ⁇ m, 0.1 ⁇ m to 0.25 ⁇ m, 0.25 ⁇ m to 0.5 ⁇ m, 0.5 ⁇ m to 0.75 ⁇ m, 0.75 ⁇ m to 1 ⁇ m, 1 ⁇ m to 1.25 ⁇ m, 1.25 ⁇ m to 1.5 ⁇ m, 1.5 ⁇ m to 1.75 ⁇ m, and 1.75 ⁇ m to 2 ⁇ m.
  • the width of the first and second high concentration portions 51, 52 is preferably less than 1 ⁇ m.
  • the lower ends of the first and second high concentration portions 51, 52 are located on the bottom side of the second region 13 with respect to the depth position of the upper end (extension) of the drift region 25.
  • the lower ends of the first and second high concentration portions 51, 52 are located on the bottom side of the second region 13 with respect to the depth position of the bottom wall of the gate structure 15.
  • the lower ends of the first and second high concentration portions 51, 52 are located on the bottom side of the second region 13 with respect to the depth position of the second surface portion 9.
  • the lower ends of the first and second high concentration portions 51, 52 may be located on the first surface portion 8 with respect to the depth position of the second surface portion 9.
  • the lower ends of the first and second high concentration portions 51, 52 are located on the bottom wall side (first surface portion 8 side) of the gate structure 15 with respect to the depth position of the bottom of the second region 13.
  • the lower ends of the first and second high concentration portions 51, 52 face the first region 7 in the thickness direction across a portion of the second region 13, and face the drift region 25 in the horizontal direction (first direction X) across a portion of the second region 13.
  • the first and second high concentration portions 51, 52 may cross the depth position of the middle part of the second region 13.
  • the upper ends of the first and second high concentration portions 51, 52 may be located on the first surface portion 8 side relative to the depth position of the middle part of the second region 13
  • the lower ends of the first and second high concentration portions 51, 52 may be located on the bottom side of the second region 13 relative to the depth position of the middle part of the second region 13.
  • the first and second high concentration portions 51, 52 may have a depth (thickness) less than the depth of the gate structure 15. Of course, the depth of the first and second high concentration portions 51, 52 may be greater than the depth of the gate structure 15. The depth of the first and second high concentration portions 51, 52 may be less than the depth of the second surface portion 9 or greater than the depth of the second surface portion 9. The depth of the first and second high concentration portions 51, 52 may be less than the depth of the drift region 25 or greater than the depth of the drift region 25.
  • the ratio (depth ratio) of the depth of the first and second high concentration portions 51, 52 to the depth of the gate structure 15 may be 0.1 or more and 2 or less.
  • the depth ratio may have a value that belongs to at least one of the following ranges: 0.1 or more and 0.25 or less, 0.25 or more and 0.5 or less, 0.5 or more and 1 or less, 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, and 1.75 or more and 2 or less.
  • the depth of the first and second high concentration portions 51, 52 may be greater than 0 ⁇ m and less than 5 ⁇ m.
  • the depth of the first and second high concentration portions 51, 52 may have a value that falls within at least one of the following ranges: greater than 0 ⁇ m and less than 0.5 ⁇ m, 0.5 ⁇ m to 1 ⁇ m, 1 ⁇ m to 1.5 ⁇ m, 1.5 ⁇ m to 2 ⁇ m, 2 ⁇ m to 2.5 ⁇ m, 2.5 ⁇ m to 3 ⁇ m, 3 ⁇ m to 3.5 ⁇ m, 3.5 ⁇ m to 4 ⁇ m, 4 ⁇ m to 4.5 ⁇ m, and 4.5 ⁇ m to 5 ⁇ m.
  • the first and second high concentration portions 51, 52 may have an aspect ratio of 1 or more and 20 or less.
  • the aspect ratio of the first and second high concentration portions 51, 52 is the ratio of the depth of the first and second high concentration portions 51, 52 to the width of the first and second high concentration portions 51, 52.
  • the aspect ratio may have a value that belongs to at least one of the ranges of 1 or more and 2 or less, 2 or more and 4 or less, 4 or more and 6 or less, 6 or more and 8 or less, 8 or more and 10 or less, 10 or more and 12 or less, 12 or more and 14 or less, 14 or more and 16 or less, 16 or more and 18 or less, and 18 or more and 20 or less.
  • the first and second high concentration portions 51, 52 may have upper ends connected to the contact region 21, as in any one of the second to fourth embodiments.
  • the upper ends of the first and second high concentration portions 51, 52 may be connected to the source region 20.
  • the upper ends of the first and second high concentration portions 51, 52 may be connected to either or both of the contact region 21 and the source region 20.
  • the first and second high concentration portions 51, 52 may cross the bottom of the second region 13 and have lower ends located within the first region 7, as in the fifth embodiment.
  • the first and second high concentration portions 51, 52 may have upper ends connected to either or both of the contact region 21 and the source region 20, as in any one of the second to fourth embodiments.
  • the first and second high concentration portions 51, 52 may have lower ends formed at a distance from the depth position of the bottom walls of the multiple gate structures 15 toward the first surface portion 8, as in the 7th or 8th embodiment.
  • the first and second high concentration portions 51, 52 may have upper ends connected to either or both of the contact region 21 and the source region 20, as in the 14th embodiment.
  • the first and second high concentration portions 51, 52 may have upper ends spaced apart from the depth position of the bottom walls of the multiple gate structures 15 toward the bottom of the second region 13, as in the 9th or 10th embodiment.
  • the first and second high concentration portions 51, 52 may have lower ends located within the first region 7, as in the 13th embodiment.
  • the semiconductor device 1 includes the chip 2, the first region 7 of n-type (first conductivity type), the second region 13 of p-type (second conductivity type), the trench-type gate structure 15, the n-type source region 20, and the n-type drift region 25.
  • the chip 2 has a first main surface 3.
  • the first region 7 is formed in a surface layer of the first main surface 3 within the chip 2.
  • the second region 13 is formed in a region on the first main surface 3 side relative to the first region 7 within the chip 2.
  • the gate structure 15 is formed on the first main surface 3, spaced apart from the bottom of the second region 13.
  • the source region 20 is formed in the surface layer of the first main surface 3 along the gate structure 15.
  • the drift region 25 is formed in the thickness range between the bottom of the second region 13 and the bottom wall of the gate structure 15, and separates the source region 20 from the channel.
  • the bottom wall of the gate structure 15 is positioned below the depth position of the bottom of the second region 13. Therefore, the depletion layer caused by the boundary (pn junction) between the first region 7 and the second region 13 spreads in the region below the bottom wall of the gate structure 15. This makes it possible to improve the breakdown voltage with a relatively simple configuration.
  • the chip 2 may contain SiC.
  • a SiC semiconductor device is provided as the semiconductor device 1 having a novel layout.
  • the physical properties of SiC can be utilized to further improve the breakdown voltage.
  • the drift region 25 may cross the bottom of the second region 13 and be connected to the first region 7.
  • the drift region 25 may be connected to the bottom wall of the gate structure 15.
  • the drift region 25 may be formed to be wider than the gate structure 15.
  • the drift region 25 may have a depth less than the depth of the gate structure 15 when the depth position of the bottom wall of the gate structure 15 is used as a reference. With this configuration, the variation in the depth of the drift region 25 can be suppressed. This allows a current path connecting the first region 7 and the source region 20 to be appropriately formed.
  • the drift region 25 may have an extension extending along the sidewall of the gate structure 15 toward the first main surface 3 and formed at a distance from the source region 20 to the bottom wall side of the gate structure 15. With this configuration, a current path connecting the first region 7 and the source region 20 can be appropriately formed by utilizing the extension of the drift region 25.
  • a plurality of gate structures 15 may be formed on the first main surface 3 at intervals.
  • a plurality of source regions 20 may be formed along the plurality of gate structures 15.
  • a plurality of drift regions 25 may be formed in the thickness range between the bottom of the second region 13 and the bottom wall of the gate structure 15, respectively.
  • the semiconductor device 1 may include a p-type high concentration region 30.
  • the high concentration region 30 may be formed in the second region 13 on the side of the gate structure 15, and may have a p-type impurity concentration higher than the p-type impurity concentration of the second region 13. This configuration provides a semiconductor device 1 that can improve electrical characteristics.
  • the p-type impurity concentration in the second region 13 near the gate structure 15 is locally increased by the high concentration region 30, and the increase in the overall p-type impurity concentration in the second region 13 is suppressed by the high concentration region 30. This allows the electric field strength near the gate structure 15 to be alleviated by the high concentration region 30.
  • the decrease in the p-type impurity concentration in the second region 13 caused by the n-type impurity concentration in the drift region 25 is suppressed on the side of the gate structure 15.
  • the short channel effect caused by the n-type impurity concentration in the drift region 25 and the leakage current caused by the short channel effect can be suppressed by the high concentration region 30.
  • the increase in the overall p-type impurity concentration in the second region 13 is suppressed by the high concentration region 30, the decrease in the n-type impurity concentration in the drift region 25 caused by the high concentration in the second region 13 can be suppressed. This makes it possible to suppress fluctuations in the electrical characteristics of the drift region 25.
  • the high concentration region 30 may be adjacent to the drift region 25 in a direction along the first main surface 3.
  • the high concentration region 30 may be formed at a distance from the first main surface 3 to the bottom side of the second region 13.
  • the high concentration region 30 may be formed at a distance from the bottom of the second region 13 to the first main surface 3.
  • the high concentration region 30 may have a portion located on the first main surface 3 side with respect to the depth position of the bottom wall of the gate structure 15. With this configuration, the short channel effect can be appropriately suppressed.
  • the high concentration region 30 may have a portion located on the bottom side of the second region 13 relative to the depth position of the bottom wall of the gate structure 15. With this configuration, the electric field concentration on the bottom wall of the gate structure 15 can be appropriately alleviated.
  • the high concentration region 30 may extend in the thickness direction of the chip 2 in a cross-sectional view. With this configuration, the high concentration region 30 extending in the thickness direction exerts an electric field relaxation effect and a short channel effect suppression effect.
  • the high concentration region 30 may be formed at a distance from the drift region 25. With this configuration, the fluctuation in the electrical characteristics of the high concentration region 30 caused by the n-type impurity concentration of the drift region 25 can be suppressed, and at the same time, the fluctuation in the electrical characteristics of the drift region 25 caused by the p-type impurity concentration of the high concentration region 30 can be suppressed.
  • the semiconductor device 1 may include a p-type contact region 21 formed in a surface layer of the second region 13 and having a p-type impurity concentration higher than the p-type impurity concentration of the second region 13.
  • the high concentration region 30 may be electrically connected to the contact region 21. With this configuration, the electrical response characteristics of the high concentration region 30 can be improved by the contact region 21.
  • the high concentration region 30 may be formed in a region that overlaps the contact region 21 in the thickness direction of the chip 2.
  • the high concentration region 30 may be formed to be wider than the contact region 21.
  • the high concentration region 30 may be directly connected to the contact region 21.
  • the high concentration region 30 may be formed at a distance from the contact region 21 to the bottom side of the second region 13, and may be electrically connected to the contact region 21 via a part of the second region 13.
  • the semiconductor device 1 includes a chip 2, a first region 7 of n-type (first conductivity type), a second region 13 of p-type (second conductivity type), a trench-type gate structure 15, an n-type drift region 25, and a p-type high-concentration region 30.
  • the chip 2 has a first main surface 3.
  • the first region 7 is formed in a surface layer of the first main surface 3 within the chip 2.
  • the second region 13 is formed in a region on the first main surface 3 side relative to the first region 7 within the chip 2.
  • the gate structure 15 is formed on the first main surface 3, spaced apart from the bottom of the second region 13.
  • the drift region 25 is formed in a thickness range between the bottom of the second region 13 and the bottom wall of the gate structure 15.
  • the high concentration region 30 is formed to the side of the gate structure 15 within the second region 13, and has an impurity concentration higher than the impurity concentration of the second region 13.
  • This configuration makes it possible to provide a semiconductor device 1 having a novel layout.
  • the high concentration region 30 locally increases the p-type impurity concentration in the second region 13 near the gate structure 15, and the high concentration region 30 suppresses an increase in the overall p-type impurity concentration in the second region 13. This allows the electric field strength near the gate structure 15 to be alleviated by the high concentration region 30.
  • the decrease in the p-type impurity concentration in the second region 13 caused by the n-type impurity concentration in the drift region 25 is suppressed on the side of the gate structure 15.
  • the short channel effect caused by the n-type impurity concentration in the drift region 25 and the leakage current caused by the short channel effect can be suppressed by the high concentration region 30.
  • the increase in the overall p-type impurity concentration in the second region 13 is suppressed by the high concentration region 30, the decrease in the n-type impurity concentration in the drift region 25 caused by the high concentration in the second region 13 can be suppressed. This makes it possible to suppress fluctuations in the electrical characteristics of the drift region 25.
  • the high concentration region 30 may have a portion facing the drift region 25 in a direction along the first main surface 3. With this configuration, the high concentration region 30 having a portion facing the drift region 25 exerts an electric field relaxation effect and a short channel effect suppression effect.
  • FIG. 9 is a schematic diagram showing a wafer 60 used in the manufacture of a semiconductor device 1.
  • the wafer 60 is the base material of the chip 2 and contains a SiC single crystal.
  • the wafer 60 is formed in a flat disk shape. Of course, the wafer 60 may also be formed in a flat rectangular parallelepiped shape.
  • the wafer 60 has a first wafer main surface 61 on one side, a second wafer main surface 62 on the other side, and a wafer side surface 63 connecting the first wafer main surface 61 and the second wafer main surface 62.
  • the first wafer main surface 61 corresponds to the first main surface 3 of the chip 2
  • the second wafer main surface 62 corresponds to the second main surface 4 of the chip 2.
  • the first wafer main surface 61 and the second wafer main surface 62 are formed by the c-plane of the SiC single crystal.
  • the first wafer main surface 61 is formed by the silicon surface of the SiC single crystal
  • the second wafer main surface 62 is formed by the carbon surface of the SiC single crystal.
  • the wafer 60 (the first wafer main surface 61 and the second wafer main surface 62) has the off-direction and off-angle described above.
  • the wafer 60 has a mark 64 on the wafer side surface 63 that indicates the crystal orientation of the SiC single crystal.
  • the mark 64 may include either or both of an orientation flat and an orientation notch.
  • the orientation flat consists of a cutout that is cut in a straight line in a plan view.
  • the orientation notch consists of a cutout that is cut in a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 61 in a plan view.
  • the wafer 60 includes an n-type base region 6 formed in a surface layer of the second wafer main surface 62.
  • the base region 6 is formed in a layer extending along the second wafer main surface 62, and is exposed from the second wafer main surface 62 and the wafer side surface 63.
  • the base region 6 is made of an n-type semiconductor wafer (SiC wafer) containing SiC single crystal (semiconductor single crystal), and has the off direction and off angle described above.
  • the wafer 60 includes an n-type first region 7 formed in the surface layer of the first wafer main surface 61.
  • the first region 7 is formed in a layer extending along the first wafer main surface 61 and is exposed from the first wafer main surface 61 and the wafer side surface 63.
  • the first region 7 is made of an n-type epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal) and is layered on the base region 6. That is, in this form, the wafer 60 is made of an epitaxial wafer (so-called epiwafer) having a layered structure including a semiconductor wafer and an epitaxial layer.
  • the first region 7 has the off-direction and off-angle described above.
  • the wafer 60 includes a plurality of device regions 65 and a plurality of cutting lines 66.
  • the plurality of device regions 65 and the plurality of cutting lines 66 are defined by alignment marks or the like formed on the first wafer main surface 61 side.
  • Each device region 65 is a region corresponding to a semiconductor device 1.
  • the plurality of device regions 65 are each set to have a rectangular shape in a plan view.
  • the multiple device regions 65 are set in a matrix along the first direction X and the second direction Y in a plan view.
  • the multiple device regions 65 are each set at intervals inward from the periphery of the first wafer main surface 61 in a plan view.
  • the multiple cutting lines 66 are set in a lattice extending along the first direction X and the second direction Y to partition the multiple device regions 65.
  • FIGS. 10A to 10N are cross-sectional views showing an example of a manufacturing method for semiconductor device 1.
  • FIG. 10A to FIG. 10N a cross section of a region corresponding to FIG. 6 is shown.
  • the aforementioned wafer 60 (FIG. 9) is prepared.
  • the second region 13 is formed on the surface layer of the first wafer main surface 61.
  • a mask (not shown) having a predetermined layout is formed on the first wafer main surface 61.
  • the mask (not shown) may have a single layer structure or a multilayer structure including either or both of an inorganic mask and an organic mask (resist mask).
  • the mask (not shown) exposes the area where the second region 13 is to be formed and covers the other areas.
  • p-type impurities are introduced into the first region 7 by ion implantation through a mask (not shown).
  • the ion implantation may be either or both of channeling ion implantation and random ion implantation.
  • p-type impurities are introduced into the first region 7 along the axial channel of the first region 7 (wafer 60).
  • the p-type impurity is implanted deep into the first region 7 while repeatedly undergoing small-angle scattering due to the channeling effect.
  • the channeling implantation method reduces the probability of the p-type impurity colliding with the atomic rows of the SiC single crystal. Therefore, the channeling ion implantation process is effective when forming a relatively deep second region 13.
  • the random ion implantation process p-type impurities are introduced into the first region 7 in a random direction.
  • the random direction is a direction other than the axial channel of the first region 7 (i.e., a direction intersecting the axial channel).
  • the random direction is the vertical direction Z.
  • the probability of collision of the p-type impurities with the atomic rows of the SiC single crystal is high, so the second region 13 is formed in a relatively shallow region. Therefore, the random ion implantation process is effective when forming a relatively shallow second region 13.
  • the p-type impurity is introduced into the surface region of the first region 7 so as to leave the bottom region of the first region 7.
  • the p-type impurity may be implanted in a single step into a single target depth range into the first region 7 (wafer 60).
  • the p-type impurity may be implanted in multiple steps into multiple different target depth ranges into the first region 7 (wafer 60). This forms the second region 13 in the surface region of the first wafer main surface 61.
  • a plurality of source regions 20 are formed in the surface layer of the first wafer main surface 61.
  • a first mask 70 having a predetermined layout is first formed on the first wafer main surface 61.
  • the first mask 70 may have a single-layer structure or a multilayer structure including either or both of an inorganic mask and an organic mask (resist mask).
  • the first mask 70 exposes the areas where the plurality of source regions 20 are to be formed and covers the other areas.
  • n-type impurities are introduced into the surface layer of the first wafer main surface 61 by ion implantation through the first mask 70.
  • the ion implantation may be either or both of channeling ion implantation and random ion implantation.
  • the ion implantation is preferably random ion implantation.
  • a plurality of source regions 20 are formed in the surface layer of the first wafer main surface 61.
  • the first mask 70 is then removed.
  • a plurality of contact regions 21 are formed on the surface layer of the first wafer main surface 61.
  • a second mask 71 having a predetermined layout is first formed on the first wafer main surface 61.
  • the second mask 71 may have a single layer structure or a multilayer structure including either or both of an inorganic mask and an organic mask (resist mask).
  • the second mask 71 exposes the areas where the plurality of contact regions 21 are to be formed and covers the other areas.
  • p-type impurities are introduced into the surface layer of the first wafer main surface 61 by ion implantation through the second mask 71.
  • the ion implantation may be either or both of channeling ion implantation and random ion implantation.
  • the ion implantation is preferably random ion implantation.
  • a plurality of contact regions 21 are formed in the surface layer of the first wafer main surface 61.
  • the second mask 71 is then removed.
  • the n-type impurities may be formed over the entire surface layer of the first wafer main surface 61 without using the first mask 70.
  • a base source region (20) that serves as the base of the multiple source regions 20 is formed over the entire surface layer of the first wafer main surface 61.
  • p-type impurities are introduced into the surface layer of the first wafer main surface 61 by ion implantation through the second mask 71 so as to change the conductivity type of the base source region (20) from n-type to p-type.
  • the order of the process of forming the source region 20 and the process of forming the contact region 21 may be reversed.
  • the second surface 9 and the multiple trenches 16 are formed on the first wafer main surface 61.
  • a third mask 72 having a predetermined layout is formed on the first wafer main surface 61.
  • the third mask 72 may have a single layer structure or a multilayer structure including either or both of an inorganic mask and an organic mask (resist mask).
  • the third mask 72 exposes the areas where the second surface 9 and the multiple trenches 16 are to be formed, and covers the other areas.
  • the etching method may be either or both of wet etching and dry etching.
  • the etching method is preferably the RIE (Reactive Ion Etching method), which is an example of a dry etching method.
  • RIE Reactive Ion Etching method
  • This forms the second surface 9 and a plurality of trenches 16.
  • the plurality of trenches 16 are formed approximately perpendicular to the first wafer main surface 61.
  • the bottom walls of the plurality of trenches 16 are formed flat.
  • a plurality of drift regions 25 are formed in the wafer 60 (second region 13).
  • a fourth mask 73 having a predetermined layout is formed on the first wafer main surface 61.
  • the fourth mask 73 may have a single-layer structure or a multilayer structure including either or both of an inorganic mask and an organic mask (resist mask).
  • the fourth mask 73 exposes the regions where the plurality of drift regions 25 are to be formed (i.e., the plurality of trenches 16) and covers the other regions.
  • n-type impurities are introduced into the second region 13 through the bottom walls of the trenches 16 by ion implantation using a fourth mask 73.
  • the n-type impurities are introduced into the thickness range between the bottom walls of the trenches 16 and the bottom of the second region 13 so as to reach the first region 7.
  • the n-type impurities are introduced so as to connect to the bottom walls of the trenches 16 and the bottom of the second region 13.
  • the ion implantation method may be either one or both of a channeling ion implantation method and a random ion implantation method.
  • the ion implantation method is preferably a random ion implantation method.
  • the random ion implantation method may be either one or both of a vertical ion implantation method and an oblique ion implantation method.
  • the n-type impurity is introduced into the second region 13 at an implantation angle that is nearly perpendicular to the first wafer main surface 61.
  • the n-type impurity is introduced into the second region 13 at an implantation angle that is oblique to the first wafer main surface 61.
  • the n-type impurity is introduced into the second region 13 through the bottom walls of the multiple trenches 16 and the lower ends of the side walls of the multiple trenches 16.
  • the implantation angle of the n-type impurity with respect to the vertical axis (0°) may be greater than 0° and less than 45°.
  • the implantation angle may have a value that falls within at least one of the following ranges: greater than 0° and less than 5°, 5° to 10°, 10° to 15°, 15° to 20°, 20° to 25°, 25° to 30°, 30° to 35°, 35° to 40°, and 40° to 45°.
  • n-type impurities are implanted at positive and negative implantation angles relative to the vertical line.
  • Positive and negative implantation angles are defined relatively. Therefore, if one side of the horizontal direction (first direction X in this embodiment) relative to the vertical line is defined as a positive implantation angle, the other side of the horizontal direction (first direction X in this embodiment) relative to the vertical line is defined as a negative implantation angle.
  • the n-type impurity may be implanted in a single step into a single target depth range in the second region 13 (wafer 60).
  • the n-type impurity may be implanted in multiple steps into multiple different target depth ranges in the second region 13 (wafer 60).
  • the multiple trenches 16 have flat bottom walls, the variation in the introduction depth of the n-type impurities caused by the variation in the depth of the bottom walls of the trenches 16 is suppressed. This improves the accuracy of introducing the n-type impurities into the second region 13, and the multiple drift regions 25 are appropriately formed. This forms the multiple drift regions 25.
  • multiple high concentration regions 30 are formed inside the second region 13.
  • p-type impurities are introduced into the second region 13 through the sidewalls of the multiple trenches 16 at an implantation angle oblique to the first wafer main surface 61 by oblique ion implantation through a fourth mask 73.
  • the p-type impurities are introduced into the regions between the multiple trenches 16.
  • the implantation angle of the p-type impurity with respect to the vertical axis (0°) may be greater than 0° and less than 45°.
  • the implantation angle may have a value that falls within at least one of the following ranges: greater than 0° and less than 5°, 5° to 10°, 10° to 15°, 15° to 20°, 20° to 25°, 25° to 30°, 30° to 35°, 35° to 40°, and 40° to 45°.
  • p-type impurities are implanted at positive and negative implantation angles relative to the vertical line.
  • the high concentration regions 30 (see Figures 7 and 8A to 8O) according to the first to sixteenth embodiments described above are formed by appropriately adjusting the p-type impurity implantation angle, p-type impurity implantation energy, trench 16 opening width, trench 16 depth, spacing between multiple trenches 16 (gate pitch), thickness of fourth mask 73, etc.
  • the p-type impurities may be implanted in a single step into a single target depth range in the second region 13 (wafer 60).
  • the p-type impurities may be implanted in multiple steps into multiple different target depth ranges in the second region 13 (wafer 60). This forms multiple high concentration regions 30 in the second region 13 in the regions between the multiple trenches 16.
  • the order of the process of forming the drift region 25 and the process of forming the high concentration region 30 is arbitrary. Therefore, the process of forming the drift region 25 may be performed after the process of forming the high concentration region 30.
  • the drift region 25 and the high concentration region 30 are formed using the fourth mask 73, but the drift region 25 and the high concentration region 30 may be formed using multiple masks having different materials and/or different thicknesses.
  • the high concentration region 30 may be formed using a mask different from the fourth mask 73.
  • the multiple high concentration regions 30 may be formed by introducing p-type impurities into the second region 13 (wafer 60) through the first wafer main surface 61.
  • a mask is formed that fills the multiple trenches 16 and selectively exposes the first wafer main surface 61.
  • P-type impurities are introduced into the second region 13 (wafer 60) by ion implantation through the mask.
  • the ion implantation may be either or both of channeling ion implantation and random ion implantation.
  • a base insulating film 74 is formed on the first wafer main surface 61.
  • the base insulating film 74 serves as a base for the multiple insulating films 17 and the main surface insulating film 35.
  • the base insulating film 74 collectively covers the first surface portion 8, the second surface portion 9, the first to fourth connection surface portions 10A to 10D, and the wall surfaces of the multiple trenches 16 in a film-like manner.
  • the base insulating film 74 may be formed by either one or both of a CVD method and an oxidation method (for example, a thermal oxidation method).
  • a first base electrode film 75 is formed on the base insulating film 74.
  • the first base electrode film 75 serves as a base for the multiple buried electrodes 18.
  • the first base electrode film 75 has a portion that covers the first wafer main surface 61 with the base insulating film 74 in between, and a portion that is embedded in the multiple trenches 16 with the base insulating film 74 in between.
  • the base insulating film 74 may be formed by a CVD method.
  • the etching method may be either or both of a wet etching method and a dry etching method. As a result, a plurality of buried electrodes 18 are formed. Also, a plurality of gate structures 15 are formed.
  • the interlayer film 36 is formed on the first wafer main surface 61 (specifically, the first base electrode film 75).
  • the interlayer film 36 collectively covers the first surface portion 8, the second surface portion 9, the first to fourth connection surface portions 10A to 10D, and the multiple gate structures 15 in a film-like manner.
  • the interlayer film 36 may be formed by a CVD method.
  • a fifth mask 76 having a predetermined layout is formed on the interlayer film 36.
  • the fifth mask 76 may be an organic mask (resist mask).
  • the fifth mask 76 exposes the regions where the source openings 37 and the gate openings 38 are to be formed, and covers the other regions.
  • unnecessary portions of the interlayer film 36 are removed by an etching method via the fifth mask 76.
  • the etching method may be either or both of a wet etching method and a dry etching method.
  • unnecessary portions of the base insulating film 74 are removed by etching through the fifth mask 76.
  • the etching method may be either wet etching or dry etching, or both.
  • the unnecessary portions of the base insulating film 74 may be removed simultaneously with the interlayer film 36.
  • a plurality of source openings 37 and a plurality of gate openings 38 are formed in the interlayer film 36.
  • a plurality of insulating films 17 and a main surface insulating film 35 are formed.
  • the fifth mask 76 is then removed.
  • a second base electrode film 77 is formed on the interlayer film 36.
  • the second base electrode film 77 is the base for the source electrode 40, the gate electrode 45, and the gate wiring 46.
  • the second base electrode film 77 has a layered structure including a lower electrode film 41 and a main electrode film 42.
  • the lower electrode film 41 has a layered structure including a first electrode film 43 and a second electrode film 44.
  • the first electrode film 43 may be formed by either one or both of a sputtering method and a vapor deposition method.
  • the first electrode film 43 is formed in a film shape along the first wafer main surface 61, the interlayer film 36, the wall surfaces of the multiple source openings 37, and the wall surfaces of the multiple gate openings 38.
  • the second electrode film 44 may be formed by either one or both of a sputtering method and a vapor deposition method.
  • the second electrode film 44 is laminated on the first electrode film 43, and is formed in a film shape along the first wafer main surface 61, the interlayer film 36, the wall surfaces of the multiple source openings 37, and the wall surfaces of the multiple gate openings 38.
  • the main electrode film 42 is formed on the lower electrode film 41.
  • the main electrode film 42 may be formed by either or both of a sputtering method and a vapor deposition method.
  • the main electrode film 42 is laminated on the lower electrode film 41 and formed in the form of a film along the first wafer main surface 61, the interlayer film 36, the wall surfaces of the multiple source openings 37, and the wall surfaces of the multiple gate openings 38.
  • the second base electrode film 77 is divided into the source electrode 40, the gate electrode 45, and the gate wiring 46.
  • a mask (not shown) having a predetermined layout is formed on the main electrode film 42.
  • the mask (not shown) covers the areas where the source electrode 40, the gate electrode 45, and the gate wiring 46 are to be formed, and leaves the other areas exposed.
  • unnecessary portions of the main electrode film 42 are removed by etching through a mask (not shown).
  • the unnecessary portions of the main electrode film 42 are removed until the lower electrode film 41 is exposed.
  • the etching method may be either or both of a wet etching method and a dry etching method.
  • the mask (not shown) is removed after the etching process of the main electrode film 42.
  • the process of removing the lower electrode film 41 includes a process of removing the second electrode film 44 by an etching method, and a process of removing the first electrode film 43 by an etching method.
  • the etching method may be either or both of a wet etching method and a dry etching method.
  • unnecessary portions of the lower electrode film 41 may be removed by an etching method using a mask (not shown) in the etching process of the main electrode film 42.
  • a drain electrode 47 is formed on the second wafer main surface 62.
  • the drain electrode 47 may be formed by either or both of a sputtering method and a vapor deposition method. Thereafter, the wafer 60 is cut along the intended cutting lines 66 (see FIG. 9) to cut out a plurality of semiconductor devices 1. Through the steps including those described above, the semiconductor device 1 is manufactured.
  • FIG. 11 is an enlarged cross-sectional view showing a semiconductor device 1 according to a modified example.
  • the semiconductor device 1 includes a plurality of p-type high concentration regions 30 formed in regions along the sidewalls of the plurality of gate structures 15 in the second region 13.
  • the multiple high concentration regions 30 are formed at intervals in the regions between the multiple gate structures 15, and face each other with a portion of the second region 13 in between.
  • the multiple high concentration regions 30 are formed on both sides of the multiple gate structures 15, and face the corresponding buried electrodes 18 across the corresponding insulating films 17.
  • the multiple high concentration regions 30 each extend in a strip shape in the second direction Y along the multiple gate structures 15 in a plan view.
  • the multiple high concentration regions 30 are formed in the regions between the multiple source regions 20 and the multiple drift regions 25 in a cross-sectional view, and extend in the vertical direction Z along the sidewalls of the corresponding gate structures 15. In other words, part or all of the channel of the transistor structure Tr is formed in the multiple high concentration regions 30.
  • the multiple high concentration regions 30 are formed at intervals from the adjacent gate structures 15 towards the corresponding gate structure 15, and face each other with a part of the second region 13 in between.
  • the multiple high concentration regions 30 are formed at intervals in the horizontal direction (first direction X) from the multiple contact regions 21, and are electrically connected to the multiple contact regions 21 via a part of the second region 13.
  • the high concentration region 30 may be connected to the multiple contact regions 21.
  • the configuration of one high concentration region 30 is described below.
  • the high concentration region 30 has an upper end on the first surface portion 8 side and a lower end (bottom) on the bottom wall side of the gate structure 15.
  • the upper end of the high concentration region 30 may be located on the first surface portion 8 side relative to the depth position of the middle part of the gate structure 15, or may be located on the bottom wall side of the gate structure 15 relative to the depth position of the middle part of the gate structure 15.
  • the upper end of the high concentration region 30 is connected to the source region 20.
  • the upper end of the high concentration region 30 may be formed at a distance from the source region 20 toward the bottom wall of the gate structure 15.
  • the lower end of the high concentration region 30 may be located on the first surface portion 8 side relative to the depth position of the middle part of the gate structure 15, or may be located on the bottom wall side of the gate structure 15 relative to the depth position of the middle part of the gate structure 15.
  • the lower end of the high concentration region 30 is connected to the drift region 25 (specifically, the upper end of the drift region 25).
  • the lower end of the high concentration region 30 may be formed at a distance from the drift region 25 (specifically, the upper end of the drift region 25) toward the first surface portion 8.
  • the high concentration region 30 may have an edge that protrudes outward (towards the adjacent gate structure 15) from the drift region 25.
  • the edge of the high concentration region 30 may be located closer to the gate structure 15 than the drift region 25. It is preferable that the edge of the high concentration region 30 is formed with a gap from the contact region 21 to the corresponding gate structure 15 side. Of course, the edge of the high concentration region 30 may be connected to the contact region 21.
  • the chip 2 including a SiC single crystal is used.
  • the chip 2 may include a silicon single crystal.
  • the base region 6 may include a silicon single crystal.
  • the first region 7 may include a silicon single crystal.
  • a p-type collector region may be formed in the surface layer of the second main surface 4 of the chip 2.
  • the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure.
  • IGBT Insulated Gate Bipolar Transistor
  • a specific configuration in this case is obtained by replacing the "source” of the MISFET structure with the "emitter” of the IGBT structure, and replacing the "drain” of the MISFET structure with the "collector” of the IGBT structure in the above description.
  • the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.
  • a semiconductor device (1) including: a chip (2) having a main surface (3); a first region (7) of a first conductivity type (n-type) formed in the surface layer of the main surface (3) in the chip (2); a second region (13) of a second conductivity type (p-type) formed in a region of the chip (2) on the main surface (3) side relative to the first region (7); a trench-type gate structure (15) formed in the main surface (3) away from the bottom of the second region (13); a first conductivity type (n-type) impurity region (20) formed in the surface layer of the main surface (3) along the gate structure (15); and a first conductivity type (n-type) drift region (25) formed in a thickness range between the bottom of the second region (13) and the bottom wall of the gate structure (15) and defining the impurity region (20) and a channel.
  • a high concentration region (30) of a second conductivity type (p-type) formed in the second region (13) on the side of the gate structure (15) and having an impurity concentration higher than the impurity concentration of the second region (13).
  • a contact region (21) of a second conductivity type (p-type) formed in a surface layer portion of the second region (13) and having an impurity concentration higher than the impurity concentration of the second region (13), and the high concentration region (30) is electrically connected to the contact region (21).
  • a semiconductor device (1) including: a chip (2) having a main surface (3); a first region (7) of a first conductivity type (n-type) formed in the surface layer of the main surface (3) in the chip (2); a second region (13) of a second conductivity type (p-type) formed in a region of the chip (2) on the main surface (3) side relative to the first region (7); a trench-type gate structure (15) formed in the main surface (3) away from the bottom of the second region (13); a drift region (25) of a first conductivity type (n-type) formed in a thickness range between the bottom of the second region (13) and the bottom wall of the gate structure (15); and a high-concentration region (30) of a second conductivity type (p-type) formed in the second region (13) on the side of the gate structure (15) and having an impurity concentration higher than the impurity concentration of the second region (13).

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003505864A (ja) * 1999-07-20 2003-02-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ トレンチ・ゲート電界効果トランジスタとその製造方法
JP2009146946A (ja) * 2007-12-11 2009-07-02 Rohm Co Ltd 半導体装置およびその製造方法
JP2011216783A (ja) * 2010-04-01 2011-10-27 Toyota Motor Corp 半導体装置及び半導体装置の製造方法

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JP2003505864A (ja) * 1999-07-20 2003-02-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ トレンチ・ゲート電界効果トランジスタとその製造方法
JP2009146946A (ja) * 2007-12-11 2009-07-02 Rohm Co Ltd 半導体装置およびその製造方法
JP2011216783A (ja) * 2010-04-01 2011-10-27 Toyota Motor Corp 半導体装置及び半導体装置の製造方法

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