WO2025018033A1 - 電源装置 - Google Patents

電源装置 Download PDF

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Publication number
WO2025018033A1
WO2025018033A1 PCT/JP2024/019747 JP2024019747W WO2025018033A1 WO 2025018033 A1 WO2025018033 A1 WO 2025018033A1 JP 2024019747 W JP2024019747 W JP 2024019747W WO 2025018033 A1 WO2025018033 A1 WO 2025018033A1
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Prior art keywords
voltage
boot
switching element
node
current
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PCT/JP2024/019747
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English (en)
French (fr)
Japanese (ja)
Inventor
貴嗣 和智
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2025533891A priority Critical patent/JPWO2025018033A1/ja
Publication of WO2025018033A1 publication Critical patent/WO2025018033A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • This disclosure relates to a power supply device.
  • the power supply device includes a first switching element provided between a reference node having a potential lower than an input voltage and a first node, a second switching element provided between the first node and a second node, a third switching element provided between the second node and a third node, a fourth switching element provided between the third node and a fourth node receiving the input voltage, a boost circuit configured to generate a first boot voltage on a first boot wiring that is supplied to a gate of the second switching element to turn on the second switching element, generate a second boot voltage on a second boot wiring that is supplied to a gate of the third switching element to turn on the third switching element, and generate a third boot voltage on a third boot wiring that is supplied to a gate of the fourth switching element to turn on the fourth switching element, a control circuit configured to generate a control signal that specifies the state of each switching element, and a control circuit configured to control the first switching element in response to the control signal using a predetermined drive voltage and the first boot voltage to the third boot voltage
  • the boost circuit comprising a first boot capacitor provided between the first node and the first boot wiring, a second boot capacitor provided between the second node and the second boot wiring, a third boot capacitor provided between the third node and the third boot wiring, a first boot switch provided between the drive wiring to which the drive voltage is applied and the first boot wiring, a second boot switch provided between the first boot wiring and the second boot wiring, and a third boot switch provided between the second boot wiring and the third boot wiring, and the first boot voltage to the third boot voltage are generated by controlling the states of each switching element and each boot switch by the control circuit.
  • FIG. 1 is an overall configuration diagram of a power supply device according to a first embodiment of the present disclosure.
  • FIG. 2 is a diagram showing the relationship between each control signal, each gate signal, and the state of each switching element according to the first embodiment of the present disclosure.
  • FIG. 3 is a diagram for explaining a current flow when switching control is performed in the power supply device according to the first embodiment of the present disclosure.
  • FIG. 4 is a configuration diagram of a power supply device showing the internal configuration of a control circuit according to the first embodiment of the present disclosure.
  • FIG. 5 is a timing chart of the power supply device according to the first embodiment of the present disclosure.
  • FIG. 6 is a diagram showing an internal configuration of a drive circuit according to the first embodiment of the present disclosure.
  • FIG. 7 is a diagram showing an internal configuration of a boost circuit according to the first embodiment of the present disclosure.
  • FIG. 8 is a diagram showing an internal configuration of a drive circuit and a boost circuit according to the first embodiment of the present disclosure.
  • FIG. 9 is a diagram showing the state of each switching element and each boot switch in state ST_A1 according to the first embodiment of the present disclosure.
  • FIG. 10 is a diagram showing the state of each switching element and each boot switch in state ST_A2 according to the first embodiment of the present disclosure.
  • FIG. 11 is an external perspective view of the power supply control device according to the first embodiment of the present disclosure.
  • FIG. 12 is a diagram illustrating the relationship between the power supply control device and a group of discrete components according to the first embodiment of the present disclosure.
  • FIG. 13 is an overall configuration diagram of a power supply device according to a second embodiment of the present disclosure.
  • FIG. 14 is a diagram showing the state and generated current of each switching element in state ST_B1 according to the second embodiment of the present disclosure.
  • FIG. 15 is a diagram showing the state and generated current of each switching element in state ST_B2 according to the second embodiment of the present disclosure.
  • FIG. 16 is a diagram showing the state and generated current of each switching element in state ST_B3 according to the second embodiment of the present disclosure.
  • FIG. 17 is a diagram showing the state of each switching element and the generated current in state ST_B4 according to the second embodiment of the present disclosure.
  • FIG. 18 is an overall configuration diagram of a power supply device according to a third embodiment of the present disclosure.
  • FIG. 14 is a diagram showing the state and generated current of each switching element in state ST_B1 according to the second embodiment of the present disclosure.
  • FIG. 15 is a diagram showing the state and generated current of each switching element in state ST_B2 according
  • FIG. 19 is a diagram showing the state and generated current of each switching element in state ST_C1 according to the third embodiment of the present disclosure.
  • FIG. 20 is a diagram showing the state of each switching element and the generated current in state ST_C2 according to the third embodiment of the present disclosure.
  • FIG. 21 is a diagram showing the state and generated current of each switching element in state ST_C3 according to the third embodiment of the present disclosure.
  • FIG. 22 is a diagram showing the state and generated current of each switching element in state ST_C4 according to the third embodiment of the present disclosure.
  • FIG. 23 is a diagram showing an internal configuration of a control circuit according to the third embodiment of the present disclosure.
  • FIG. 24 is a timing chart of the power supply device according to the third embodiment of the present disclosure.
  • FIG. 25 is a diagram showing a modified example of the power supply device according to the third embodiment of the present disclosure.
  • Ground refers to a reference conductive part having a reference potential of 0V (zero volts) or the reference potential of 0V itself.
  • 0V zero volts
  • ground When a certain component, electrode, or node is connected to ground, it means that the component, electrode, or node is connected to a reference node having a reference potential of 0V.
  • the reference node and ground can be read as interchangeable terms.
  • Level refers to the level of potential, and for any given signal or voltage, a high level has a higher potential than a low level.
  • a high level signal or voltage strictly means that the signal or voltage level is at a high level
  • a low level signal or voltage strictly means that the signal or voltage level is at a low level.
  • the switch from low level to high level is called a rising edge
  • the switch from high level to low level is called a falling edge.
  • Any switching element can be composed of a transistor.
  • a transistor configured as a FET (field effect transistor), including a MOSFET
  • the on state refers to a state in which the drain and source of the transistor are conductive
  • the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state).
  • MOSFET is understood to be an enhancement-type MOSFET.
  • MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor.”
  • the backgate of any MOSFET can be considered to be shorted to the source.
  • the on and off states of any switching element may be simply expressed as on and off.
  • switching from the off state to the on state will be expressed as turning on, and switching from the on state to the off state will be expressed as turning off.
  • the period during which the switching element is in the on state will be referred to as the on period, and the period during which the switching element is in the off state will be referred to as the off period.
  • the period during which the signal is at a high level is called a high-level period
  • the period during which the signal is at a low level is called a low-level period.
  • connections between multiple parts that form a circuit can be understood to refer to electrical connections.
  • FIG. 1 is an overall configuration diagram of a power supply device 1A according to the first embodiment of the present disclosure.
  • the power supply device 1A receives a positive input voltage V IN from a voltage source (not shown) and generates a positive output voltage V OUT by stepping down the input voltage V IN .
  • the output voltage V OUT is lower than the input voltage V IN .
  • the power supply device 1A stabilizes the output voltage V OUT at a predetermined target voltage. That is, in a steady state, the output voltage V OUT substantially coincides with the target voltage.
  • the target voltage is referred to by the symbol "V TG ".
  • An intermediate voltage V MID is generated in the power supply device 1A.
  • the output voltage V OUT is lower than the intermediate voltage V MID .
  • the intermediate voltage V MID is substantially 1/2 of the input voltage V IN . Therefore, "V IN > 2 ⁇ V OUT " is established.
  • the values of the input voltage V IN and the output voltage V OUT are arbitrary. In other words, as long as "V IN > 2 ⁇ V TG " is satisfied, the values of the input voltage V IN and the target voltage V TG are arbitrary.
  • the input voltage V IN is 48 V
  • the target voltage V TG i.e., the output voltage V OUT in the steady state
  • a steady state refers to a state in which the output voltage VOUT rises from 0 V and reaches the target voltage VTG as the power supply device 1A starts up, and then the output voltage VOUT is stabilized at the target voltage VTG .
  • the power supply device 1A is in a steady state.
  • the power supply device 1A includes, as its main components, switching elements M1 to M4, capacitors C FLY , C MID and C OUT , an inductor L1, a control circuit 30A, a drive circuit 40A and a boost circuit 50A.
  • Capacitor C FLY can be referred to as a flying capacitor.
  • Capacitor C MID can be referred to as an intermediate capacitor.
  • Capacitor C OUT can be referred to as an output capacitor.
  • the power supply 1A has a buck converter and a stacked converter.
  • the buck converter in the power supply 1A includes switching elements M1 and M2 and an inductor L1, and generates an output voltage V OUT at an output node ND OUT by stepping down an intermediate voltage V MID .
  • the capacitor C OUT may also be considered to be included in the components of the buck converter.
  • the switching elements M1 and M2 function as a low-side switching element and a high-side switching element in the buck converter.
  • the stacked converter in the power supply 1A includes switching elements M3 and M4 and a capacitor C FLY , and generates an intermediate voltage V MID from an input voltage V IN .
  • the capacitor C MID may also be considered to be included in the components of the stacked converter.
  • the switching elements M1 to M4 are each configured with an N-channel MOSFET. For this reason, hereinafter, the switching elements M1 to M4 may be referred to as transistors M1 to M4.
  • the transistors M1 to M4 are connected in series between the ground and a node ND4.
  • the transistor M1 is provided between the ground and the node ND1
  • the transistor M2 is provided between the nodes ND1 and ND2
  • the transistor M3 is provided between the nodes ND2 and ND3
  • the transistor M4 is provided between the nodes ND3 and ND4. More specifically, the source of the transistor M1 is connected to the ground.
  • the drain of the transistor M1 and the source of the transistor M2 are connected to the node ND1.
  • the drain of the transistor M2 and the source of the transistor M3 are connected to the node ND2.
  • the drain of the transistor M3 and the source of the transistor M4 are connected to the node ND3.
  • the drain of the transistor M4 is connected to the node ND4.
  • the node ND4 is a power supply node that receives the input voltage V IN . That is, the input voltage V IN is supplied to the node ND4.
  • the signals supplied to the gates of the transistors M1 to M4 are called gate signals G1 to G4, respectively.
  • the capacitor C FLY is provided between the nodes ND3 and ND1, that is, a first end of the capacitor C FLY is connected to the node ND3, and a second end of the capacitor C FLY is connected to the node ND1.
  • the capacitor C MID is provided between the node ND2 and the ground. That is, a first end of the capacitor C MID is connected to the node ND2, and a second end of the capacitor C MID is connected to the ground. The first end of the capacitor C MID corresponds to the positive electrode of the capacitor C MID .
  • the voltage at the node ND2 is the intermediate voltage V MID . That is, the intermediate voltage V MID is generated between both ends of the capacitor C MID .
  • the voltage at the node ND1 is referred to as a voltage V LX
  • the voltage at the node ND3 is referred to as a voltage V FLY .
  • the inductor L1 is provided between the node ND1 and the output node ND OUT , that is, a first end of the inductor L1 is connected to the node ND1, and a second end of the inductor L1 is connected to the output node ND OUT .
  • the capacitor COUT is provided between the output node NDOUT and the ground. That is, a first end of the capacitor COUT is connected to the output node NDOUT , and a second end of the capacitor COUT is connected to the ground. The first end of the capacitor COUT corresponds to the positive electrode of the capacitor COUT .
  • the voltage at the output node NDOUT is the output voltage VOUT . That is, the output voltage VOUT is generated across the capacitor COUT .
  • the control circuit 30A generates and outputs control signals that specify the state (on or off) of the transistors M1 to M4.
  • the control signals generated by the control circuit 30A include the control signals CNT1 to CNT4.
  • the control signals CNT1 to CNT4 are binary signals. Any binary signal has a low level or a high level.
  • the control circuit 30A can set the levels of the control signals CNT1 to CNT4 individually to a high level or a low level.
  • the drive circuit 40A is connected to each gate of the transistors M1 to M4, and sets the state of the transistors M1 to M4 individually to on or off by supplying gate signals G1 to G4 to the transistors M1 to M4 according to the control signals CNT1 to CNT4.
  • the boost circuit 50A generates the voltage required to turn on the transistors M2 to M4, and supplies the generated voltage to the drive circuit 40A. Details of the boost circuit 50A will be described later.
  • the control circuit 30A cooperates with the drive circuit 40A and the boost circuit 50A to control the states of the transistors M1-M4, thereby generating a desired output voltage V OUT at the output node ND OUT , which is lower than the input voltage V IN .
  • Figure 2 shows the relationship between the control signals CNT1 to CNT4, the gate signals G1 to G4, and the states of the transistors M1 to M4.
  • High-level control signals CNT1, CNT2, CNT3, and CNT4 are signals that specify that the transistors M1, M2, M3, and M4 are turned on, respectively.
  • Low-level control signals CNT1, CNT2, CNT3, and CNT4 are signals that specify that the transistors M1, M2, M3, and M4 are turned off, respectively. Therefore, during the high-level period of the control signal CNT1, the gate signal G1 also has a high level, and the transistor M1 is turned on. During the low-level period of the control signal CNT1, the gate signal G1 also has a low level, and the transistor M1 is turned off.
  • the gate signal G2 also has a high level, and the transistor M2 is turned on.
  • the gate signal G2 also has a low level, and the transistor M2 is turned off.
  • the gate signal G3 also has a high level, and the transistor M3 is turned on.
  • the gate signal G3 also has a low level, and the transistor M3 is turned off.
  • the gate signal G4 also has a high level, and the transistor M4 is turned on.
  • the gate signal G4 also has a low level, and the transistor M4 is turned off.
  • the output node ND OUT is connected to a load (not shown).
  • the load is any load that is driven based on the output voltage V OUT .
  • the current supplied from the output node ND OUT to the load is called the load current I LD .
  • the load current I LD corresponds to the output current of the power supply device 1A.
  • the current flowing through the inductor L1 is called the inductor current I L.
  • the inductor current I L flowing from the node ND1 to the output node ND OUT has a positive polarity, and the inductor current I L flowing from the output node ND OUT to the node ND1 has a negative polarity.
  • the control circuit 30A can use the drive circuit 40A to set the states of the transistors M1 to M4 to one of a number of states and to switch between the states.
  • the states include states ST_A1 and ST_A2 shown in FIG. 3. In state ST_A1, the transistors M2 and M4 are on and the transistors M1 and M3 are off. In state ST_A2, the transistors M2 and M4 are off and the transistors M1 and M3 are on.
  • the states may include a state in which the transistors M1 to M4 are all off, but in the following description of this embodiment, the situation in which the transistors M1 to M4 are all off will be ignored.
  • the control circuit 30A can use the drive circuit 40A to execute switching control for alternately switching the states of the transistors M1 to M4 between states ST_A1 and ST_A2.
  • the current generated when the switching control is executed will be described.
  • the current in the direction that increases the potential of the first end of the capacitor C i.e. , the potential of the node ND3 based on the potential of the second end of the capacitor C (i.e., the potential of the node ND1)
  • the current in the opposite direction is the discharging current of the capacitor C.
  • the current in the direction that increases the intermediate voltage V MID is the charging current
  • the current in the direction that decreases the intermediate voltage V MID is the discharging current.
  • currents 811 and 813 are generated.
  • the current 811 flows from the capacitor C MID through the transistor M2 and the inductor L1 to the output node ND OUT , and is generated by discharging the capacitor C MID .
  • the current 813 flows from the node ND4, which is the application terminal of the input voltage VIN, to the capacitor C FLY through the transistor M4, and the capacitor C FLY is charged by the current 813.
  • currents 812 and 814 are generated.
  • the current 812 flows from the ground to the output node ND OUT through the transistor M1 and the inductor L1.
  • the current 814 flows from the capacitor C FLY to the positive electrode of the capacitor C MID through the transistor M3.
  • the current 814 is generated by discharging the capacitor C FLY and contributes to charging the capacitor C MID .
  • state ST_A1 is equivalent to a state in which the capacitors C FLY and C MID are connected in series. Also, in state ST_A2, the capacitors C FLY and C MID are connected in parallel through the switching elements M1 and M3. As a result, a switched capacitor circuit is formed by the transistors M1 to M4 and the capacitors C FLY and C MID . Therefore, in the steady state, the intermediate voltage V MID, which is the voltage of the positive electrode of the capacitor C MID , is approximately the voltage (V IN /2).
  • the control circuit 30A operates the circuit having the transistors M1 to M4 and the capacitors C MID and C FLY as a switched capacitor circuit in switching control, thereby generating the intermediate voltage V MID at the node ND2.
  • a synchronous buck converter that steps down the intermediate voltage V MID is formed by the transistors M1 and M2 and the inductor L1.
  • the power supply device 1A can be called a hybrid buck converter that combines a switched capacitor circuit and a synchronous buck converter.
  • High efficiency can be achieved by using a switched capacitor circuit to reduce the input voltage V IN by half and then further stepping down the resulting intermediate voltage V MID using a synchronous buck converter.
  • an output voltage V OUT of 12 V is generated from an input voltage V IN of 48 V.
  • a square wave voltage (a square wave voltage that fluctuates between approximately 0 V and 48 V) is generated by switching the input voltage V IN of 48 V, and an output voltage of 12 V is obtained by rectifying and smoothing the square wave voltage.
  • a square wave voltage (a square wave voltage that fluctuates between approximately 0 V and 24 V) is generated by switching a voltage (V IN /2), and an output voltage of 12 V is obtained by rectifying and smoothing the square wave voltage. Therefore, the power supply device 1A can suppress switching loss to a lower level compared to the power supply device according to the reference method.
  • the switching duty is relatively small.
  • the impact of losses during periods when the instantaneous value of the square wave voltage rises and falls is relatively large.
  • the input voltage to the synchronous buck converter is voltage (V IN /2), so the switching duty is relatively large compared to the reference method, leading to an improvement in switching loss.
  • the input voltage to the synchronous buck converter is voltage (V IN /2), so that the loss associated with charging and discharging the parasitic capacitances can be kept relatively low compared to the reference method.
  • Fig. 4 shows a configuration diagram of the power supply 1A showing an example of the internal configuration of the control circuit 30A. It is assumed here that the power supply 1A operates in a continuous current mode where "I L >0" at all times, and unless otherwise specified, only the configuration related to the continuous current mode will be described.
  • Fig. 5 shows, from top to bottom, the waveforms of the voltage V LX , inductor current I L , error voltage V ERR , slope voltage V SLP , and signals CLK, CMPOUT, CNT1, CNT2, CNT3, and CNT4.
  • the control circuit 30A includes an error amplifier 31, a ramp circuit 32, a current information acquisition circuit 33, an adder 34, a PWM comparator 35, an oscillator circuit (clock generation circuit) 36, and a controller 37.
  • the power supply device 1A is also provided with resistors R1 and R2. A first end of the resistor R1 is connected to the output node ND OUT , a second end of the resistor R1 is connected to a first end of the resistor R2, and a second end of the resistor R2 is connected to ground.
  • a feedback voltage V FB corresponding to the output voltage V OUT is generated at the connection node between the resistors R1 and R2.
  • the feedback voltage V FB is a divided voltage of the output voltage V OUT , and is therefore proportional to the output voltage V OUT .
  • the resistors R1 and R2 form a feedback voltage generation circuit that generates the feedback voltage V FB .
  • the feedback voltage V FB is supplied to the control circuit 30A. However, it may be understood that the feedback voltage generation circuit is included in the components of the control circuit 30A.
  • the output voltage V OUT itself may be used as the feedback voltage V FB . In any case, the feedback voltage V FB contains information about the output voltage V OUT (more specifically, information indicating the value of the output voltage V OUT ).
  • the error amplifier 31 is a current output type transconductance amplifier.
  • the error amplifier 31 has an inverting input terminal, a non-inverting input terminal, and an output terminal.
  • a feedback voltage VFB is supplied to the inverting input terminal of the error amplifier 31.
  • a predetermined reference voltage VREF is supplied to the non-inverting input terminal of the error amplifier 31.
  • the reference voltage VREF is a DC voltage having a positive predetermined voltage value, and is generated by a reference voltage generating circuit (not shown) in the control circuit 30A.
  • the output terminal of the error amplifier 31 is connected to the wiring WR ERR .
  • a soft start control may be performed to gradually increase the value of the reference voltage VREF from 0V to a positive predetermined voltage value, but the existence of the soft start control will be ignored below.
  • the error amplifier 31 generates an error voltage V ERR corresponding to the difference between the feedback voltage V FB and the reference voltage V REF on the wiring WR ERR by outputting a current signal corresponding to the difference between the feedback voltage V FB and the reference voltage V REF from its output terminal. Specifically, when the feedback voltage V FB is lower than the reference voltage V REF , the error amplifier 31 outputs a current from its output terminal to the wiring WR ERR so that the error voltage V ERR increases, and when the feedback voltage V FB is higher than the reference voltage V REF , the error amplifier 31 draws a current from the wiring WR ERR to its output terminal so that the error voltage V ERR decreases.
  • a phase compensation circuit including a capacitor may be connected between the wiring WR ERR and ground.
  • the ramp circuit 32 generates a ramp voltage V RAMP that monotonically rises at a predetermined rate of change from a predetermined initial voltage V INT during an ON period of the transistor M2.
  • the initial voltage V INT is, for example, 0 V, but may be different from 0 V.
  • the ramp voltage V RAMP is fixed at the initial voltage V INT .
  • the current information acquisition circuit 33 acquires current information of the inductor L1, and generates a sense voltage VIL indicating the current information of the inductor L1.
  • the current information of the inductor L1 is information indicating the value of the inductor current IL .
  • the sense voltage VIL may be generated in any manner.
  • the sense voltage VIL may be generated by directly detecting the inductor current I L with a current sensor.
  • the current sensor here may be a shunt resistor (not shown) inserted in series between the inductor L1 and the node ND1.
  • the sense voltage VIL may be generated by detecting the current (hence the inductor current I L ) flowing through the transistor M2 during the on-period of the transistor M2, or by detecting the current (hence the inductor current I L ) flowing through the transistor M1 during the on-period of the transistor M1.
  • the sense voltage VIL may be generated by detecting the voltage at any point where a voltage corresponding to the inductor current I L is generated.
  • the PWM comparator 35 compares the error voltage VERR and the slope voltage VSLP , and generates and outputs a signal CMPOUT indicating the comparison result.
  • the error voltage VERR is input to the inverting input terminal of the PWM comparator 35
  • the slope voltage VSLP is input to the non-inverting input terminal of the PWM comparator 35.
  • the PWM comparator 35 outputs a low-level signal CMPOUT when " VSLP ⁇ VERR " is true, and outputs a high-level signal CMPOUT when " VSLP > VERR " is true.
  • the signal CMPOUT has a low level or a high level.
  • the oscillator circuit 36 generates and outputs a clock signal CLK by oscillating.
  • the clock signal CLK is a rectangular wave signal having a predetermined frequency f PWM , and alternates between high and low signal levels.
  • the duty of the clock signal CLK is arbitrary.
  • the clock signal CLK has a low level in principle, and has a high level for a very short time at intervals of the reciprocal of the frequency f PWM (see FIG. 5).
  • Signal CMPOUT and clock signal CLK are input to controller 37.
  • controller 37 In response to a predetermined level change in clock signal CLK, controller 37 generates a rising edge in control signals CNT2 and CNT4 (i.e. switches the levels of control signals CNT2 and CNT4 from low level to high level) and generates a falling edge in control signals CNT1 and CNT3 (i.e. switches the levels of control signals CNT1 and CNT3 from high level to low level).
  • the predetermined level change in clock signal CLK here is a change in clock signal CLK from low level to high level, but it may also be a change in clock signal CLK from high level to low level.
  • Control signals CNT1 to CNT4 from controller 37 are supplied to drive circuit 40A.
  • the drive circuit 40A turns on the transistors M2 and M4 by generating a rising edge in the gate signals G2 and G4 in response to the rising edge of the control signals CNT2 and CNT4, and turns off the transistors M1 and M3 by generating a falling edge in the gate signals G1 and G3 in response to the falling edge of the control signals CNT1 and CNT3.
  • the slope voltage V SLP rises monotonically and transitions from a state where "V SLP ⁇ V ERR " is satisfied to a state where "V SLP > V ERR " is satisfied, generating a rising edge in the signal CMPOUT.
  • the controller 37 In switching control, when a rising edge occurs in the signal CMPOUT, the controller 37 generates a falling edge in the control signals CNT2 and CNT4 and generates a rising edge in the control signals CNT1 and CNT3.
  • the drive circuit 40A turns off the transistors M2 and M4 by generating a falling edge in the gate signals G2 and G4 in response to the falling edge of the control signals CNT2 and CNT4, and turns on the transistors M1 and M3 by generating a rising edge in the gate signals G1 and G3 in response to the rising edge of the control signals CNT1 and CNT3.
  • the ramp voltage V RAMP drops to the sufficiently low initial voltage V INT , returning to the state where "V SLP ⁇ V ERR " is satisfied, and a falling edge is quickly generated in the signal CMPOUT.
  • time t ON the time from when the transistors M2 and M4 are turned on and the transistors M1 and M3 are turned off to when the transistors M2 and M4 are turned off and the transistors M1 and M3 are turned on.
  • the above-mentioned time tON depends on the error voltage V ERR (and therefore on the information of the output voltage V OUT ) and on the sense voltage V IL (and therefore on the current information of the inductor L1). That is, the controller 37 performs switching control of the transistors M1 to M4 in synchronization with the clock signal CLK based on the information of the output voltage V OUT and the current information of the inductor L1.
  • the controller 37 uses the drive circuit 40A to perform switching control, in which the controller 37 turns on the transistors M2 and M4 and turns off the transistors M1 and M3 in response to a predetermined level change in the clock signal CLK, and then, when the time tON corresponding to the information of the output voltage V OUT and the current information of the inductor L1 has elapsed, turns off the transistors M2 and M4 and turns on the transistors M1 and M3.
  • the controller 37 generates an intermediate voltage V MID across the capacitor C MID through the above-mentioned switching control, and also generates an output voltage V OUT at the output node ND OUT by stepping down the intermediate voltage V MID using a buck converter including transistors M1 and M2 and an inductor L1.
  • Fig. 6 shows the internal configuration of the drive circuit 40A.
  • the drive circuit 40A includes level shifters 41_1 to 41_4 and gate drivers 42_1 to 42_4.
  • Fig. 7 shows the internal configuration of the boost circuit 50A.
  • the boost circuit 50A includes boot switches Ma, Mb, and Mc, boot capacitors C BOOT1 , C BOOT2 , and C BOOT3 , level shifters 51_2 to 51_4, and gate drivers 52_2 to 52_4.
  • the level shifters 41_2 to 41_4 and the gate drivers 42_2 to 42_4 may function as the level shifters 51_2 to 51_4 and the gate drivers 52_2 to 52_4.
  • Each component in the control circuit 30A (and therefore the controller 37) operates using a voltage VDD as a positive power supply voltage and a voltage VSS as a negative power supply voltage.
  • the voltage VSS corresponds to the ground voltage here.
  • the voltage VDD and a voltage V DRV described below are positive DC voltages lower than the input voltage V IN and may be generated based on the input voltage V IN within the power supply device 1A.
  • the voltages VDD and V DRV may have different voltage values.
  • the voltage V DRV may also be referred to as a drive voltage.
  • the drive voltage V DRV is the voltage on the drive wiring W DRV .
  • the boot wirings W BOOT1 , W BOOT2, and W BOOT3 and the drive wiring W DRV may also be understood to be included in the components of the boost circuit 50A.
  • the voltage on the boot wiring W BOOT1 is referred to as a boot voltage V BOOT1 .
  • the voltage on the boot wiring W BOOT2 is referred to as a boot voltage V BOOT2 .
  • the voltage on the boot wiring W BOOT3 is referred to as a boot voltage V BOOT3 .
  • the boot voltages V BOOT1 , V BOOT2 , and V BOOT3 are voltages supplied to the gates of the transistors M2, M3, and M4 to turn on the transistors M2, M3, and M4, respectively.
  • the controller 37 outputs control signals CNT1 to CNT4 to the level shifters 41_1 to 41_4, respectively.
  • a high-level control signal output from the controller 37 has a voltage VDD level
  • a low-level control signal output from the controller 37 has a voltage VSS level.
  • the level shifter 41_1 is connected to wiring to which the voltages VDD, VSS, and V DRV are applied, and receives the supply of these voltages.
  • the level shifter 41_1 shifts the level of the control signal CNT1 from the controller 37 using the voltages VDD, VSS, and V DRV , and outputs the level-shifted control signal CNT1.
  • the output signal of the level shifter 41_1 is supplied to the gate driver 42_1.
  • the output signal of the level shifter 41_1 has a high level when the controller 37 outputs a high-level control signal CNT1, and has a low level when the controller 37 outputs a low-level control signal CNT1.
  • the high level of the output signal of the level shifter 41_1 has the level of the drive voltage V DRV
  • the low level of the output signal of the level shifter 41_1 has the level of the voltage VSS.
  • the gate driver 42_1 is connected to the gate of the transistor M1.
  • the gate driver 42_1 drives the gate of the transistor M1 in response to the control signal CNT1 (specifically, in response to the control signal CNT1 after level shifting from the level shifter 41_1) based on the voltages V DRV and VSS to turn the transistor M1 on or off.
  • the gate driver 42_1 supplies a high-level gate signal G1 to the gate of the transistor M1 to set the state of the transistor M1 on.
  • the gate driver 42_1 supplies a low-level gate signal G1 to the gate of the transistor M1 to set the state of the transistor M1 off.
  • the high-level gate signal G1 has the level of the driving voltage V DRV
  • the low-level gate signal G1 has the level of the voltage VSS.
  • the driving voltage V DRV is higher than the gate threshold voltage of the transistor M1.
  • the level shifter 41_2 is connected to wiring to which the voltages VDD, VSS, VBOOT1 , and VLX are applied, and receives the supply of these voltages.
  • the level shifter 41_2 shifts the level of the control signal CNT2 from the controller 37 using the voltages VDD, VSS, VBOOT1 , and VLX , and outputs the level-shifted control signal CNT2.
  • the output signal of the level shifter 41_2 is supplied to the gate driver 42_2.
  • the output signal of the level shifter 41_2 has a high level when the controller 37 outputs a high-level control signal CNT2, and has a low level when the controller 37 outputs a low-level control signal CNT2.
  • the high level of the output signal of the level shifter 41_2 has the level of the boot voltage VBOOT1
  • the low level of the output signal of the level shifter 41_2 has the level of the voltage VLX .
  • the gate driver 42_2 is connected to the gate of the transistor M2.
  • the gate driver 42_2 drives the gate of the transistor M2 in response to the control signal CNT2 based on the voltages V BOOT1 and V LX (specifically, in response to the control signal CNT2 after level shifting from the level shifter 41_2), thereby turning the transistor M2 on or off.
  • the gate driver 42_2 supplies a high-level gate signal G2 to the gate of the transistor M2 to set the state of the transistor M2 to on.
  • the gate driver 42_2 supplies a low-level gate signal G2 to the gate of the transistor M2 to set the state of the transistor M2 to off.
  • the high-level gate signal G2 has the level of the boot voltage V BOOT1
  • the low-level gate signal G2 has the level of the voltage V LX .
  • the difference voltage (V BOOT1 -V LX ) is higher than the gate threshold voltage of the transistor M2.
  • the level shifter 41_3 is connected to wiring to which the voltages VDD, VSS, VBOOT2 , and VMID are applied, and receives the supply of these voltages.
  • the level shifter 41_3 shifts the level of the control signal CNT3 from the controller 37 using the voltages VDD, VSS, VBOOT2 , and VMID , and outputs the level-shifted control signal CNT3.
  • the output signal of the level shifter 41_3 is supplied to the gate driver 42_3.
  • the output signal of the level shifter 41_3 has a high level when the controller 37 outputs a high-level control signal CNT3, and has a low level when the controller 37 outputs a low-level control signal CNT3.
  • the high level of the output signal of the level shifter 41_3 has the level of the boot voltage VBOOT2
  • the low level of the output signal of the level shifter 41_3 has the level of the intermediate voltage VMID .
  • the gate driver 42_3 is connected to the gate of the transistor M3.
  • the gate driver 42_3 drives the gate of the transistor M3 in response to the control signal CNT3 based on the voltages V BOOT2 and V MID (specifically, in response to the control signal CNT3 after level shifting from the level shifter 41_3), thereby turning the transistor M3 on or off.
  • the gate driver 42_3 supplies a high-level gate signal G3 to the gate of the transistor M3 to set the state of the transistor M3 on.
  • the gate driver 42_3 supplies a low-level gate signal G3 to the gate of the transistor M3 to set the state of the transistor M3 off.
  • the high-level gate signal G3 has the level of the boot voltage V BOOT2
  • the low-level gate signal G3 has the level of the intermediate voltage V MID .
  • the difference voltage (V BOOT2 -V MID ) is higher than the gate threshold voltage of the transistor M3.
  • the level shifter 41_4 is connected to wiring to which the voltages VDD, VSS, VBOOT3 , and VFLY are applied, and receives the supply of these voltages.
  • the level shifter 41_4 shifts the level of the control signal CNT4 from the controller 37 using the voltages VDD, VSS, VBOOT3 , and VFLY , and outputs the level-shifted control signal CNT4.
  • the output signal of the level shifter 41_4 is supplied to the gate driver 42_4.
  • the output signal of the level shifter 41_4 has a high level when the controller 37 outputs a high-level control signal CNT4, and has a low level when the controller 37 outputs a low-level control signal CNT4.
  • the high level of the output signal of the level shifter 41_4 has the level of the boot voltage VBOOT3
  • the low level of the output signal of the level shifter 41_4 has the level of the voltage VFLY .
  • the gate driver 42_4 is connected to the gate of the transistor M4.
  • the gate driver 42_4 drives the gate of the transistor M4 in response to the control signal CNT4 based on the voltages V BOOT3 and V FLY (specifically, in response to the control signal CNT4 after level shifting from the level shifter 41_4), thereby turning the transistor M4 on or off.
  • the gate driver 42_4 supplies a high-level gate signal G4 to the gate of the transistor M4 to set the state of the transistor M4 to on.
  • the gate driver 42_4 supplies a low-level gate signal G4 to the gate of the transistor M4 to set the state of the transistor M4 to off.
  • the high-level gate signal G4 has the level of the boot voltage V BOOT3
  • the low-level gate signal G4 has the level of the voltage V FLY .
  • the difference voltage (V BOOT3 -V FLY ) is higher than the gate threshold voltage of the transistor M4.
  • the boot switches Ma to Mc are each composed of a P-channel MOSFET.
  • the boot switches Ma to Mc may be referred to as transistors Ma to Mc.
  • FIG. 7 also illustrates the parasitic diodes added to the transistors Ma to Mc (the same applies to several drawings shown below in which the transistors Ma to Mc are shown).
  • the parasitic diode has a forward direction that is from the drain to the source.
  • the boot capacitor C BOOT1 is provided between the node ND1 and the boot wiring W BOOT1 . That is, a first end and a second end of the boot capacitor C BOOT1 are connected to the node ND1 and the boot wiring W BOOT1, respectively.
  • the boot capacitor C BOOT1 is charged by a current that flows from the boot wiring W BOOT1 to the node ND1 via the boot capacitor C BOOT1 , and the boot capacitor C BOOT1 is discharged by the current in the opposite direction. Charging the boot capacitor C BOOT1 increases the boot voltage V BOOT1 .
  • the boot capacitor C BOOT2 is provided between the node ND2 and the boot wiring W BOOT2 . That is, a first end and a second end of the boot capacitor C BOOT2 are connected to the node ND2 and the boot wiring W BOOT2, respectively.
  • the boot capacitor C BOOT2 is charged by a current that flows from the boot wiring W BOOT2 to the node ND2 via the boot capacitor C BOOT2 , and the boot capacitor C BOOT2 is discharged by the current in the opposite direction. Charging the boot capacitor C BOOT2 increases the boot voltage V BOOT2 .
  • the boot capacitor C BOOT3 is provided between the node ND3 and the boot wiring W BOOT3 . That is, a first end and a second end of the boot capacitor C BOOT3 are connected to the node ND3 and the boot wiring W BOOT3, respectively.
  • the boot capacitor C BOOT3 is charged by a current that flows from the boot wiring W BOOT3 to the node ND3 via the boot capacitor C BOOT3 , and the boot capacitor C BOOT3 is discharged by the current in the opposite direction. Charging the boot capacitor C BOOT3 increases the boot voltage V BOOT3 .
  • the transistor Ma is provided between the drive wiring W DRV to which the drive voltage V DRV is applied and the boot wiring W BOOT1 . Specifically, the drain of the transistor Ma is connected to the drive wiring W DRV , and the source of the transistor Ma is connected to the boot wiring W BOOT1 .
  • the transistor Mb is provided between the boot wiring W BOOT1 and the boot wiring W BOOT2 . Specifically, the drain of the transistor Mb is connected to the boot wiring W BOOT1 , and the source of the transistor Mb is connected to the boot wiring W BOOT2 .
  • the transistor Mc is provided between the boot wiring W BOOT2 and the boot wiring W BOOT3 . Specifically, the drain of the transistor Mc is connected to the boot wiring W BOOT2 , and the source of the transistor Mc is connected to the boot wiring W BOOT3 .
  • the controller 37 outputs control signals CNT1 to CNT4 to the level shifters 51_2 to 51_4, respectively.
  • the level shifter 51_2 is connected to wiring to which the voltages VDD, VSS, VBOOT1 , and VLX are applied, and receives the supply of these voltages.
  • the level shifter 51_2 shifts the level of the control signal CNT2 from the controller 37 using the voltages VDD, VSS, VBOOT1 , and VLX , and outputs the level-shifted control signal CNT2.
  • the output signal of the level shifter 51_2 is supplied to the switch driver 52_2.
  • the output signal of the level shifter 51_2 has a high level when the controller 37 outputs a high-level control signal CNT2, and has a low level when the controller 37 outputs a low-level control signal CNT2.
  • the high level of the output signal of the level shifter 51_2 has the level of the boot voltage VBOOT1
  • the low level of the output signal of the level shifter 51_2 has the level of the voltage VLX .
  • the switch driver 52_2 is connected to the gate of the transistor Ma.
  • the switch driver 52_2 drives the gate of the transistor Ma in response to the control signal CNT2 based on the voltages V BOOT1 and V LX (specifically, in response to the control signal CNT2 after level shifting from the level shifter 51_2), thereby turning the transistor Ma on or off.
  • the switch driver 52_2 sets the state of the transistor Ma to OFF by supplying a high level gate signal to the gate of the transistor Ma.
  • the switch driver 52_2 sets the state of the transistor Ma to ON by supplying a low level gate signal to the gate of the transistor Ma.
  • the high level gate signal for the transistor Ma has the level of the boot voltage V BOOT1
  • the low level gate signal for the transistor Ma has the level of the voltage V LX .
  • the difference voltage (V BOOT1 -V LX ) is greater than the absolute value of the gate threshold voltage of the transistor Ma.
  • the level shifter 51_3 is connected to wiring to which the voltages VDD, VSS, VBOOT2 , and VMID are applied, and receives the supply of these voltages.
  • the level shifter 51_3 shifts the level of the control signal CNT3 from the controller 37 using the voltages VDD, VSS, VBOOT2 , and VMID , and outputs the level-shifted control signal CNT3.
  • the output signal of the level shifter 51_3 is supplied to the switch driver 52_3.
  • the output signal of the level shifter 51_3 has a high level when the controller 37 outputs a high-level control signal CNT3, and has a low level when the controller 37 outputs a low-level control signal CNT3.
  • the high level of the output signal of the level shifter 51_3 has the level of the boot voltage VBOOT2
  • the low level of the output signal of the level shifter 51_3 has the level of the voltage VMID .
  • the switch driver 52_3 is connected to the gate of the transistor Mb.
  • the switch driver 52_3 drives the gate of the transistor Mb in response to the control signal CNT3 based on the voltages V BOOT2 and V MID (specifically, in response to the control signal CNT3 after level shifting from the level shifter 51_3), thereby turning the transistor Mb on or off.
  • the switch driver 52_3 sets the state of the transistor Mb to OFF by supplying a high level gate signal to the gate of the transistor Mb.
  • the switch driver 52_3 sets the state of the transistor Mb to ON by supplying a low level gate signal to the gate of the transistor Mb.
  • the high level gate signal for the transistor Mb has the level of the boot voltage V BOOT2
  • the low level gate signal for the transistor Mb has the level of the voltage V MID .
  • the difference voltage (V BOOT2 -V MID ) is greater than the absolute value of the gate threshold voltage of the transistor Mb.
  • the level shifter 51_4 is connected to wiring to which the voltages VDD, VSS, VBOOT3 , and VFLY are applied, and receives the supply of these voltages.
  • the level shifter 51_4 shifts the level of the control signal CNT4 from the controller 37 using the voltages VDD, VSS, VBOOT3 , and VFLY , and outputs the level-shifted control signal CNT4.
  • the output signal of the level shifter 51_4 is supplied to the switch driver 52_4.
  • the output signal of the level shifter 51_4 has a high level when the controller 37 outputs a high-level control signal CNT4, and has a low level when the controller 37 outputs a low-level control signal CNT4.
  • the high level of the output signal of the level shifter 51_4 has the level of the boot voltage VBOOT3
  • the low level of the output signal of the level shifter 51_4 has the level of the voltage VFLY .
  • the switch driver 52_4 is connected to the gate of the transistor Mc.
  • the switch driver 52_4 drives the gate of the transistor Mc in response to the control signal CNT4 based on the voltages V BOOT3 and V FLY (specifically, in response to the control signal CNT4 after level shifting from the level shifter 51_4), thereby turning the transistor Mc on or off.
  • the switch driver 52_4 sets the state of the transistor Mc to OFF by supplying a high level gate signal to the gate of the transistor Mc.
  • the switch driver 52_4 sets the state of the transistor Mc to ON by supplying a low level gate signal to the gate of the transistor Mc.
  • the high level gate signal for the transistor Mc has the level of the boot voltage V BOOT3
  • the low level gate signal for the transistor Mc has the level of the voltage V FLY .
  • the difference voltage (V BOOT3 -V FLY ) is greater than the absolute value of the gate threshold voltage of the transistor Mc.
  • the level shifters 41_2 to 41_4 and the gate drivers 42_2 to 42_4 may function as the level shifters 51_2 to 51_4 and the gate drivers 52_2 to 52_4.
  • the level shifters and switch drivers dedicated to driving the transistors Ma to Mc are not provided in the boost circuit 50A (i.e., the level shifters 51_2 to 51_4 and the gate drivers 52_2 to 52_4 are omitted from the boost circuit 50A).
  • the gate signal G2 output from the driver 42_2 is supplied to the gate of the transistor Ma
  • the gate signal G3 output from the driver 42_3 is supplied to the gate of the transistor Mb
  • the gate signal G4 output from the driver 42_4 is supplied to the gate of the transistor Mc.
  • FIG. 8 shows the internal configuration of the drive circuit 40A and the internal configuration of the boost circuit 50A.
  • the reference symbols "40A” and "50A” are omitted in FIG. 8 and in FIG. 9 and FIG. 10 described below.
  • the controller 37 outputs low-level control signals CNT1 and CNT3 and high-level control signals CNT2 and CNT4. Therefore, in state ST_A1, the drive circuit 40A sets transistors G1 and G3 off and transistors G2 and G4 on based on the control signals CNT1 to CNT4. Also, in state ST_A1, the boost circuit 50A sets transistors Ma and Mc off and transistor Mb on based on the control signals CNT2 to CNT4.
  • a current 821 is generated.
  • the current 821 is a current that charges the boot capacitor C BOOT2 , and is generated by discharging the boot capacitor C BOOT1 .
  • the current 821 flows in a current loop that runs from the boot wiring W BOOT1 through the transistor Mb, the boot wiring W BOOT2 , the boot capacitor C BOOT2 , the node ND2, the transistor M2, the node ND1, and the boot capacitor C BOOT1 , and returns to the boot wiring W BOOT1 .
  • the gate signal G2 is raised to a high level using the discharge current of the boot capacitor C BOOT1
  • the gate signal G4 is raised to a high level using the discharge current of the boot capacitor C BOOT3 .
  • the controller 37 outputs high-level control signals CNT1 and CNT3 and low-level control signals CNT2 and CNT4. Therefore, in state ST_A2, the drive circuit 40A sets transistors G1 and G3 on and transistors G2 and G4 off based on the control signals CNT1 to CNT4. Also, in state ST_A2, the boost circuit 50A sets transistors Ma and Mc on and transistor Mb off based on the control signals CNT2 to CNT4.
  • Current 822 is a current that charges boot capacitor C BOOT1 , and is generated by a voltage source (not shown) that generates drive voltage V DRV .
  • This voltage source is provided in power supply device 1A (power supply control device 10A described below; see FIG. 11), and is a DC voltage source that generates drive voltage V DRV based on input voltage V IN .
  • Current 822 flows in a current loop that runs from this voltage source through drive wiring W DRV , transistor Ma, boot wiring W BOOT1 , boot capacitor C BOOT1 , node ND1, transistor M1, and ground, and returns to this voltage source.
  • Current 823 is a current that charges boot capacitor C BOOT3 , and is generated by discharging boot capacitor C BOOT2 .
  • a current 823 flows in a current loop from boot wire W BOOT2 through transistor Mc, boot wire W BOOT3 , boot capacitor C BOOT3 , node ND3, transistor M3, node ND2, boot capacitor C BOOT2 , and back to boot wire W BOOT2 .
  • the gate signal G3 is pulled up to a high level using the discharge current of boot capacitor C BOOT2 .
  • FIG. 11 is an external perspective view of the power supply control device 10A included in the power supply unit 1A.
  • the power supply control device 10A is an electronic component that includes a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a number of external terminals that are exposed from the housing to the outside of the power supply control device 10A.
  • the power supply control device 10A is formed by sealing the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the power supply control device 10A and the type of housing for the power supply control device 10A shown in FIG. 2 are merely examples, and can be designed as desired.
  • the power supply 1A comprises a power supply control device 10A and a group of discrete components that are externally connected to the power supply control device 10A. Some of the components of the power supply 1A are provided in the power supply control device 10A, and the remaining parts are composed of the group of discrete components.
  • inductor L1 capacitors C OUT , C MID , C FLY , C BOOT1 , C BOOT2 , and C BOOT3 , and resistors R1 and R2 are provided in the group of discrete components. However, resistors R1 and R2 may be built into the power supply control device 10A. Transistors M1 to M4 are also provided in the group of discrete components. However, transistors M1 to M4 may be built into the power supply control device 10A. A control circuit 30A and a drive circuit 40A are provided in the power supply control device 10A. Of the components of boost circuit 50A, all except boot capacitors C BOOT1 to C BOOT3 are provided in the power supply control device 10A.
  • a reference power supply (not shown) that does not have the boost circuit 50A of this embodiment is also considered.
  • the reference power supply three bootstrap diodes are externally connected to the power supply control device. The number of parts in the reference power supply is greater than that of the power supply 1A by the amount of these diodes.
  • the bootstrap rectifying element can be built into the power supply control device 10. In other words, the number of parts can be reduced, and the power supply can be made smaller accordingly.
  • the level of the gate signal for turning on the transistors M2 to M4 is lowered by the forward voltage of the diode.
  • the power supply 1A there is no effect of the forward voltage of the diode, so the switching loss of the transistors M2 to M4 can be reduced, and it is also easy to ensure a driving margin when the voltage of each part is relatively low.
  • FIG. 13 is an overall configuration diagram of a power supply device 1B according to a second embodiment of the present disclosure.
  • the power supply device 1B is a type of multi-phase converter.
  • the power supply device 1B is configured by adding a switching element M5 and an inductor L2 to the power supply device 1A according to the first embodiment.
  • the description of "power supply device 1A" in the first embodiment is replaced with "power supply device 1B" in this embodiment.
  • the first end of the capacitor C FLY is connected to the node ND3, and the second end of the capacitor C FLY is connected to the node ND5.
  • the switching element M5 is configured by an N-channel MOSFET, similar to the switching elements M1 to M4. Therefore, hereinafter, the switching element M5 may be referred to as the transistor M5.
  • the drain of the transistor M5 and the first end of the inductor L2 are connected to the node ND5
  • the second end of the inductor L2 is connected to the output node ND OUT
  • the source of the transistor M5 is connected to ground.
  • the power supply device 1B includes a buck converter CNVa and a stacked converter CNVb.
  • the buck converter CNVa includes transistors M1 and M2, an inductor L1, and a capacitor COUT , and generates a desired output voltage VOUT by stepping down an intermediate voltage VMID .
  • the transistors M1 and M2 function as a low-side switching element and a high-side switching element in the buck converter CNVa.
  • the stacked converter CNVb includes transistors M3 to M5, a capacitor C FLY , and an inductor L2, and generates an intermediate voltage V MID from the input voltage V IN .
  • the capacitor C MID may be considered to be included in the components of the stacked converter CNVb.
  • the stacked converter CNVb also functions as a converter for one phase in the multiphase converter.
  • the transistor M3 functions as a control switching element for charging the capacitor C MID .
  • the transistor M4 functions as a switching element for generating the intermediate voltage V MID , and also functions as a high-side switching element for multiphase.
  • the transistor M5 functions as a low-side switching element for multiphase.
  • a control circuit 30B, a drive circuit 40B, and a boost circuit 50B are provided instead of the control circuit 30A, drive circuit 40A, and boost circuit 50A in FIG. 1.
  • the control circuit 30B uses the drive circuit 40B to control the switching of the transistors M1 to M5 based on the information on the output voltage V OUT and the current information of the inductor L1 so that the output voltage V OUT is stabilized at the target voltage V TG .
  • the information on the output voltage V OUT is information according to the output voltage V OUT , and may be, for example, the feedback voltage V FB described in the first embodiment.
  • the current information of the inductor L1 is information according to the inductor current I L , and may be, for example, a voltage signal (sense voltage V IL in FIG. 4) proportional to the value of the inductor current I L.
  • the control circuit 30B controls the transistors M1 to M5 to be on or off individually in the switching control.
  • the control circuit 30B generates the above-mentioned control signals CNT1 to CNT4 based on the information on the output voltage V OUT and the current information of the inductor L1, and also generates a control signal CNT5 that specifies the state (on or off state) of the transistor M5.
  • the drive circuit 40B has the same configuration as the drive circuit 40A of the first embodiment, and generates a gate signal G5 according to the control signal CNT5.
  • the boost circuit 50B has the same configuration as the boost circuit 50A of the first embodiment. Gate signals G1 to G5 are supplied from the drive circuit 40B to the gates of the transistors M1 to M5, respectively, to set the states of the transistors M1 to M5 individually to on or off.
  • the states of the transistors M1 to M5 are switched between states ST_B1 to ST_B4 shown in Figs. 14 to 17 by the switching control of the control circuit 30B.
  • the flow of current occurring in each state is indicated by a broken line with multiple arrows.
  • the power supply device 1B operates in a current continuous mode.
  • a current in a direction that increases the potential of the first end of the capacitor C i.e., the potential of the node ND3
  • the potential of the second end of the capacitor C i.e., the potential of the node ND5
  • a current in the opposite direction is the discharging current of the capacitor C.
  • a current in a direction that increases the intermediate voltage V MID is the charging current
  • a current in a direction that decreases the intermediate voltage V MID is the discharging current.
  • state ST_B1 the transistors M1 and M4 are in an ON state, and the transistors M2, M3, and M5 are in an OFF state.
  • currents 841 and 842 are generated.
  • the current 841 flows from the application terminal of the input voltage VIN through the transistor M4, the capacitor C FLY , and the inductor L2 to the output node ND OUT .
  • the current 841 corresponds to a charging current to the capacitor C FLY , and the capacitor C FLY is charged by the current 841.
  • the current 842 flows from the ground to the output node ND OUT through the transistor M1 and the inductor L1.
  • state ST_B1 no charging or discharging of the capacitor C MID occurs, and the accumulated charge of the capacitor C MID is kept unchanged.
  • a current 843 is generated together with the current 841.
  • the current 843 flows from the capacitor C MID through the transistor M2 and the inductor L1 toward the output node ND OUT , and is generated by discharging the capacitor C MID .
  • transistors M2, M3 and M5 are in an ON state, and transistors M1 and M4 are in an OFF state.
  • currents 844 and 845 are generated together with the current 843.
  • the current 844 flows from ground through transistor M5, capacitor C FLY and transistor M3 to the positive electrode of capacitor C MID , and returns to ground through capacitor C MID .
  • the current 844 discharges capacitor C FLY while charging capacitor C MID .
  • the current 845 flows from ground through transistor M5 and inductor L2 to the output node ND OUT .
  • transistors M1, M3, and M5 are on, and transistors M2 and M4 are off.
  • the above-mentioned currents 842, 844, and 845 are generated.
  • state ST_B1 the magnitudes of the currents 841 and 842 are approximately the same.
  • state ST_B2 the magnitudes of the currents 841 and 843 are approximately the same.
  • state ST_B2 the transistors M2 and M4 are on, so for the capacitors C FLY and C MID , state ST_B2 is equivalent to a state in which the capacitors C FLY and C MID are connected in series.
  • states ST_B3 and ST_B4 the capacitors C FLY and C MID are connected in parallel through the transistors M3 and M5.
  • a switched capacitor circuit is formed in the power supply device 1B by a circuit having the transistors M1 to M5 and the capacitors C FLY and C MID .
  • the control circuit 40B operates the circuit as a switched capacitor circuit, thereby generating an intermediate voltage V MID equivalent to a divided voltage of the input voltage V IN at the positive electrode of the capacitor C MID .
  • the intermediate voltage V MID is substantially equal to the voltage (V IN /2). Strictly speaking, the intermediate voltage V MID fluctuates somewhat around the voltage (V IN /2).
  • the output current (842, 843) from the buck converter CNVa to the output node ND OUT and the output current (841, 845) from the stacked converter CNVb to the output node ND OUT are pulsating currents, and the former output current and the latter output current have different phases. That is, the power supply device 1B is a multiphase converter (multiphase DC/DC converter) and has two phases.
  • the configuration and operation of the boost circuit 50B are the same as those of the boost circuit 50A of the first embodiment (see FIG. 7). Therefore, transistor Ma is off during the on period of transistor M2 and on during the off period of transistor M2. Transistor Mb is off during the on period of transistor M3 and on during the off period of transistor M3. Transistor Mc is off during the on period of transistor M4 and on during the off period of transistor M4. When only the states of transistors M1 to M4 and Ma to Mc are considered, state ST_B2 in FIG. 15 is equivalent to state ST_A1 in FIG. 9, and state ST_B4 in FIG. 17 is equivalent to state ST_A2 in FIG. 10.
  • Fig. 18 is an overall configuration diagram of a power supply device 1C according to the third embodiment of the present disclosure.
  • the description of the first embodiment can be applied to the third embodiment, and in this application, the description of "power supply device 1A" in the first embodiment can be read as “power supply device 1C" in this embodiment.
  • the power supply device 1C receives a positive input voltage V IN from a voltage source (not shown) and generates a positive output voltage V OUT by stepping down the input voltage V IN .
  • the power supply device 1C includes converters CNV1 and CNV2, a control circuit 30C, a drive circuit 40C, and a boost circuit 50C.
  • the power supply device 1C includes switching elements M1 to M8, capacitors C FLY1 , C FLY2 , C MID1 , C MID2 , and C OUT , and inductors L1 to L4.
  • the capacitors C FLY1 and C FLY2 can be referred to as flying capacitors.
  • the capacitors C MID1 and C MID2 can be referred to as intermediate capacitors.
  • the capacitor C OUT can be referred to as an output capacitor.
  • the converter CNV1 is a first channel converter.
  • the components of the converter CNV1 include switching elements M1 to M4, capacitors C FLY1 and C MID1 , and inductors L1 and L3.
  • the converter CNV2 is a second channel converter.
  • the components of the converter CNV2 include switching elements M5 to M8, capacitors C FLY2 and C MID2 , and inductors L2 and L4.
  • the capacitor C OUT is used in common by the converters CNV1 and CNV2. That is, the capacitor C OUT is a component of each of the converters CNV1 and CNV2, and is shared by the converters CNV1 and CNV2.
  • the converter CNV1 has a first channel buck converter and a first channel stacked converter.
  • the first channel buck converter includes switching elements M1 and M2 and an inductor L1, and generates an output voltage V OUT at an output node ND OUT by stepping down an intermediate voltage V MID1 in cooperation with a capacitor C OUT .
  • the switching elements M1 and M2 function as a low-side switching element and a high-side switching element in the first channel buck converter.
  • the first channel stacked converter includes switching elements M3 to M5, a capacitor C FLY1 , and an inductor L3, and generates an intermediate voltage V MID1 from an input voltage V IN .
  • the capacitor C MID1 may be understood to be included in the components of the first channel stacked converter.
  • the converter CNV1 itself is a two-phase multiphase converter.
  • the first channel stacked converter also functions as a converter for one phase in the converter CNV1.
  • the switching element M3 functions as a control switching element for charging the capacitor C MID1 .
  • the switching element M4 functions as a switching element for generating the intermediate voltage V MID1 , and also functions as a high-side switching element for multiphase.
  • the switching element M5 functions as a low-side switching element for multiphase.
  • the converter CNV2 has a second channel buck converter and a second channel stacked converter.
  • the second channel buck converter includes switching elements M5 and M6 and an inductor L2, and generates an output voltage V OUT at an output node ND OUT by stepping down an intermediate voltage V MID2 in cooperation with a capacitor C OUT .
  • the switching elements M5 and M6 function as a low-side switching element and a high-side switching element in the second channel buck converter.
  • the second channel stacked converter includes switching elements M7, M8, and M1, a capacitor C FLY2 , and an inductor L4, and generates an intermediate voltage V MID2 from an input voltage V IN .
  • the capacitor C MID2 may be considered to be included in the components of the second channel stacked converter.
  • the converter CNV2 itself is a two-phase multiphase converter.
  • the second channel stacked converter also functions as a converter for one phase in the converter CNV2.
  • the switching element M7 functions as a control switching element for charging the capacitor C MID2 .
  • the switching element M8 functions as a switching element for generating the intermediate voltage V MID2 , and also functions as a high-side switching element for multiphase.
  • the switching element M1 functions as a low-side switching element for multiphase.
  • the first channel buck converter, the first channel stacked converter, the second channel buck converter, and the second channel stacked converter each supply a current to the output node ND OUT , thereby generating an output voltage V OUT having a desired voltage value at the output node ND OUT .
  • switching element M1 is used both as a low-side switching element in the buck converter of the first channel and as a low-side switching element for multi-phase in the stacked converter of the second channel.
  • switching element M5 is used both as a low-side switching element in the buck converter of the second channel and as a low-side switching element for multi-phase in the stacked converter of the first channel.
  • converters CNV1 and CNV2 are each two-phase multiphase converters.
  • power supply device 1C converters CNV1 and CNV2 operate in parallel. If two power supply devices 1B as shown in FIG. 13 were provided, a total of 10 switching elements would be required, whereas power supply device 1C can achieve the same effect as two power supply devices 1B operating in parallel with a total of eight switching elements, resulting in a reduction in the number of parts.
  • the switching elements M1 to M8 are each configured with an N-channel MOSFET. For this reason, hereinafter, the switching elements M1 to M8 may be referred to as transistors M1 to M8.
  • Transistors M1 to M4 are connected in series between ground and node ND4.
  • Transistor M1 is provided between ground and node ND1
  • transistor M2 is provided between nodes ND1 and ND2
  • transistor M3 is provided between nodes ND2 and ND3
  • transistor M4 is provided between nodes ND3 and ND4. More specifically, the source of transistor M1 is connected to ground.
  • the drain of transistor M1 and the source of transistor M2 are connected to node ND1.
  • the drain of transistor M2 and the source of transistor M3 are connected to node ND2.
  • the drain of transistor M3 and the source of transistor M4 are connected to node ND3.
  • the drain of transistor M4 is connected to node ND4.
  • the signals supplied to the gates of transistors M1 to M4 are referred to as gate signals G1 to G4, respectively.
  • Transistors M5 to M8 are connected in series between ground and node ND8.
  • Transistor M5 is provided between ground and node ND5
  • transistor M6 is provided between nodes ND5 and ND6
  • transistor M7 is provided between nodes ND6 and ND7
  • transistor M8 is provided between nodes ND7 and ND8.
  • the source of transistor M5 is connected to ground.
  • the drain of transistor M5 and the source of transistor M6 are connected to node ND5.
  • the drain of transistor M6 and the source of transistor M7 are connected to node ND6.
  • the drain of transistor M7 and the source of transistor M8 are connected to node ND7.
  • the drain of transistor M8 is connected to node ND8.
  • the signals supplied to the gates of transistors M5 to M8 are referred to as gate signals G5 to G8, respectively.
  • the nodes ND4 and ND8 are power supply nodes that receive the input voltage VIN . That is, the input voltage VIN is supplied to the nodes ND4 and ND8.
  • different reference symbols ND4, ND8 are assigned to the power supply node to which the drain of the transistor M4 is connected and the power supply node to which the drain of the transistor M8 is connected, but the nodes ND4 and ND8 may be a single node, or may be two separate nodes that receive the input voltage VIN .
  • the capacitor C MID1 is provided between the node ND2 and the ground. That is, a first end of the capacitor C MID1 is connected to the node ND2, and a second end of the capacitor C MID1 is connected to the ground. The first end of the capacitor C MID1 corresponds to the positive electrode of the capacitor C MID1 .
  • the voltage at the node ND2 is the intermediate voltage V MID1 . That is, a charge equivalent to the intermediate voltage V MID1 is stored in the capacitor C MID1 .
  • the capacitor C MID2 is provided between the node ND6 and the ground. That is, a first end of the capacitor C MID2 is connected to the node ND6, and a second end of the capacitor C MID2 is connected to the ground. The first end of the capacitor C MID2 corresponds to the positive electrode of the capacitor C MID2 .
  • the voltage at the node ND6 is the intermediate voltage V MID2 . That is, a charge equivalent to the intermediate voltage V MID2 is stored in the capacitor C MID2 .
  • the inductor L1 is provided between the node ND1 and the output node ND OUT . That is, a first end of the inductor L1 is connected to the node ND1, and a second end of the inductor L1 is connected to the output node ND OUT .
  • the capacitor C FLY1 is provided between the nodes ND3 and ND5. That is, a first end of the capacitor C FLY1 is connected to the node ND3, and a second end of the capacitor C FLY1 is connected to the node ND5.
  • the inductor L3 is provided between the node ND5 and the output node ND OUT .
  • a first end of the inductor L3 is connected to the node ND5 (and therefore connected to the second end of the capacitor C FLY1 ), and a second end of the inductor L3 is connected to the output node ND OUT .
  • Inductor L2 is provided between node ND5 and output node ND OUT . That is, a first end of inductor L2 is connected to node ND5, and a second end of inductor L2 is connected to output node ND OUT .
  • Capacitor C FLY2 is provided between nodes ND7 and ND1. That is, a first end of capacitor C FLY2 is connected to node ND7, and a second end of capacitor C FLY2 is connected to node ND1.
  • Inductor L4 is provided between node ND1 and output node ND OUT . That is, a first end of inductor L4 is connected to node ND1 (and therefore connected to the second end of capacitor C FLY2 ), and a second end of inductor L4 is connected to output node ND OUT .
  • the capacitor COUT is provided between the output node NDOUT and the ground. That is, a first end of the capacitor COUT is connected to the output node NDOUT , and a second end of the capacitor COUT is connected to the ground. The first end of the capacitor COUT corresponds to the positive electrode of the capacitor COUT .
  • the voltage at the output node NDOUT is the output voltage VOUT . That is, a charge equivalent to the output voltage VOUT is stored in the capacitor COUT .
  • the control circuit 30C performs switching control of the transistors M1 to M8 based on the information of the output voltage V OUT , the current information of the inductor L1, and the current information of the inductor L2 so that the output voltage V OUT is stabilized at the target voltage V TG .
  • the switching control of the transistors M1 to M8 and the on/off control of the transistors M1 to M8 by the control circuit 30C are realized using the drive circuit 40C, but the description of the drive circuit 40C may be omitted.
  • the information of the output voltage V OUT is information according to the output voltage V OUT , and may be, for example, the feedback voltage V FB described in the first embodiment.
  • the current information of the inductor L1 is information according to the current flowing through the inductor L1, and may be, for example, a voltage signal proportional to the current flowing through the inductor L1.
  • the current information of the inductor L2 is information according to the current flowing through the inductor L2, and may be, for example, a voltage signal proportional to the current flowing through the inductor L2.
  • the control circuit 30C controls the transistors M1 to M8 individually to be on or off in the switching control.
  • the control circuit 30C generates control signals CNT1 to CNT8 that specify the states (on or off) of the transistors M1 to M8 based on information about the output voltage V OUT and information about the currents of the inductors L1 and L2.
  • the drive circuit 40C generates gate signals G1 to G4 in response to the control signals CNT1 to CNT4, similar to the drive circuit 40A of the first embodiment, and further generates gate signals G5 to G8 in response to the control signals CNT5 to CNT8.
  • the gate signals G1 to G8 from the drive circuit 40C are supplied to the gates of the transistors M1 to M8, respectively, to set the state of the transistors M1 to M8 individually to on or off.
  • the boost circuit 50C will be described later.
  • Gate signals G1 to G8 correspond to the control signals CNT1 to CNT8, respectively. Any of the control signals CNT1 to CNT8 is referred to as the control signal CNTx, and the gate signal corresponding to the control signal CNTx is referred to as the gate signal Gx. Of the transistors M1 to M8, the transistor that receives the gate signal Gx at its gate is referred to as the transistor Mx.
  • the drive circuit 40C causes the gate signal Gx to have a high level during the high level period of the control signal CNTx, and causes the gate signal Gx to have a low level during the low level period of the control signal CNTx.
  • the transistor Mx When the gate signal Gx has a high level, the transistor Mx is on, and when the gate signal Gx has a low level, the transistor Mx is off. Therefore, for example, during the high level period of the gate signal G1, the transistor M1 is on, and during the low level period of the gate signal G1, the transistor M1 is off. Similarly, transistor M2 is on during the high-level period of gate signal G2, and off during the low-level period of gate signal G2. The same is true for transistors M3 to M8.
  • a high-level gate signal Gx has a potential higher than the potential that is higher than the source potential of transistor Mx by the gate threshold voltage of transistor Mx.
  • a low-level gate signal Gx may have a potential equal to the source potential of transistor Mx.
  • a control circuit 30C controls the states of transistors M1-M8 to generate a desired output voltage V OUT at output node ND OUT , which is lower than the input voltage V IN .
  • the control circuit 30C sequentially switches the states of transistors M1-M8 between states ST_C1-ST_C4. States ST_C1-ST_C4 will be described with reference to FIGS. 19-22.
  • a current in a direction to increase the potential of the first end of the capacitor C FLY1 (i.e., the potential of the node ND3) based on the potential of the second end of the capacitor C FLY1 (i.e., the potential of the node ND5) is the charging current of the capacitor C FLY1
  • a current in the opposite direction is the discharging current of the capacitor C FLY1 .
  • a current in a direction to increase the potential of the first end of the capacitor C FLY2 i.e., the potential of the node ND7 based on the potential of the second end of the capacitor C FLY2 (i.e., the potential of the node ND1) is the charging current of the capacitor C FLY2
  • a current in the opposite direction is the discharging current of the capacitor C FLY2
  • a current in a direction to increase the intermediate voltage V MID1 is the charging current
  • a current in a direction to decrease the intermediate voltage V MID1 is the discharging current.
  • a current in a direction to increase the intermediate voltage V MID2 is the charging current
  • a current in a direction to decrease the intermediate voltage V MID2 is the discharging current.
  • the power supply device 1C operates in the continuous current mode.
  • a current always flows from the first end to the second end of each of the inductors L1 to L4, that is, a current always flows through the inductors L1 to L4 in a direction in which the capacitor C OUT is charged.
  • the current flowing through the inductor L1 is called the inductor current I L1 .
  • the currents flowing through the inductors L2, L3, and L4 are called the inductor currents I L2 , I L3 , and I L4 , respectively.
  • the output node ND OUT is connected to a load not shown.
  • the load is any load that is driven based on the output voltage V OUT .
  • the current supplied to the load from the output node ND OUT is called the load current I LD .
  • the load current I LD corresponds to the output current of the power supply device 1C.
  • FIG. 19 shows the on/off states of transistors M1 to M8 in state ST_C1 and the current flow that occurs in state ST_C1.
  • control circuit 30C uses drive circuit 40C to control transistors M2, M3, M5, and M8 to the on state, while controlling transistors M1, M4, M6, and M7 to the off state.
  • the state in state ST_C1 corresponds to state ST_B3 in FIG. 16 for converter CNV1, and to state ST_B1 in FIG. 14 for converter CNV2.
  • currents 911 to 913 are generated in the converter CNV1.
  • Current 911 flows from the capacitor C MID1 through the switching element M2 and the inductor L1 to the output node ND OUT , and is generated by discharging the capacitor C MID1 .
  • Current 912 flows from the ground through the switching element M5, the capacitor C FLY1 , and the switching element M3 to the first end of the capacitor C MID1 , and returns to the ground through the capacitor C MID1 .
  • the current 912 discharges the capacitor C FLY1 while charging the capacitor C MID1 .
  • Current 913 flows from the ground through the switching element M5 and the inductor L3 to the output node ND OUT .
  • state ST_C1 currents 914 and 915 are generated in the converter CNV2.
  • the current 914 flows from the node ND8 through the switching element M8, the capacitor C FLY2 , and the inductor L4 to the output node ND OUT .
  • the capacitor C FLY2 is charged by the current 914.
  • the current 915 flows from the ground through the switching element M5 and the inductor L2 to the output node ND OUT .
  • state ST_C1 no charging or discharging of the capacitor C MID2 occurs, and the accumulated charge of the capacitor C MID2 is kept unchanged.
  • FIG. 20 shows the on/off states of transistors M1 to M8 in state ST_C2 and the current flow that occurs in state ST_C2.
  • control circuit 30C uses drive circuit 40C to control transistors M2, M4, M6, and M8 to the on state, while controlling transistors M1, M3, M5, and M7 to the off state.
  • the state in state ST_C2 corresponds to state ST_B2 in FIG. 15 for converter CNV1, and also corresponds to state ST_B2 in FIG. 15 for converter CNV2.
  • the current 916 is generated in the converter CNV1 together with the current 911.
  • the current 911 is generated by discharging the capacitor C MID1 .
  • the current 916 flows from the node ND4 through the switching element M4, the capacitor C FLY1 , and the inductor L3 to the output node ND OUT .
  • the capacitor C FLY1 is charged by the current 916.
  • a current 917 is generated together with the current 914.
  • the capacitor C FLY2 is charged by the current 914.
  • the current 917 is a current flowing from the capacitor C MID1 through the switching element M6 and the inductor L2 toward the output node ND OUT , and is generated by discharging the capacitor C MID2 .
  • FIG. 21 shows the on/off states of transistors M1 to M8 in state ST_C3 and the current flow that occurs in state ST_C3.
  • control circuit 30C uses drive circuit 40C to control transistors M1, M4, M6, and M7 to the on state, while controlling transistors M2, M3, M5, and M8 to the off state.
  • the state in state ST_C3 corresponds to state ST_B1 in FIG. 14 for converter CNV1, and to state ST_B3 in FIG. 16 for converter CNV2.
  • a current 918 is generated in the converter CNV1 together with the current 916.
  • the capacitor C FLY1 is charged by the current 916.
  • the current 918 flows from the ground through the switching element M1 and the inductor L1 to the output node ND OUT .
  • no charging or discharging of the capacitor C MID1 occurs, and the accumulated charge of the capacitor C MID1 is kept unchanged.
  • currents 919 and 920 are generated in converter CNV2 together with the current 917.
  • current 917 is generated by discharging capacitor C MID2 .
  • Current 919 flows from ground through switching element M1, capacitor C FLY2 and switching element M7 to the first end of capacitor C MID2 and returns to ground through capacitor C MID2 .
  • Current 919 discharges capacitor C FLY2 while charging capacitor C MID2 .
  • Current 920 flows from ground through switching element M1 and inductor L4 to output node ND OUT .
  • FIG. 22 shows the on/off states of transistors M1 to M8 in state ST_C4 and the current flow that occurs in state ST_C4.
  • control circuit 30C uses drive circuit 40C to control transistors M1, M3, M5, and M7 to the on state, while controlling transistors M2, M4, M6, and M8 to the off state.
  • the state in state ST_C4 corresponds to state ST_B4 in FIG. 17 for converter CNV1, and also corresponds to state ST_B4 in FIG. 17 for converter CNV2.
  • converter CNV1 In state ST_C4, converter CNV1 generates the above-mentioned currents 912, 913 and 918. As described above, current 912 discharges capacitor C FLY1 while charging capacitor C MID1 .
  • converter CNV2 In state ST_C4, converter CNV2 generates the above-mentioned currents 919, 920 and 915. As described above, current 919 discharges capacitor C FLY2 while charging capacitor C MID2 .
  • the capacitors C FLY1 and C MID1 are connected in parallel through the transistors M3 and M5.
  • a switched capacitor circuit is formed by the circuit including the transistors M1 to M5 and the capacitors C FLY1 and C MID1 .
  • the control circuit 40C operates the circuit as a switched capacitor circuit, thereby generating an intermediate voltage V MID1 equivalent to a divided voltage of the input voltage V IN at the positive electrode of the capacitor C MID1 .
  • the intermediate voltage V MID1 is substantially equal to the voltage (V IN /2). Strictly speaking, the intermediate voltage V MID1 fluctuates somewhat around the voltage (V IN /2).
  • state ST_C1 the magnitudes of the currents 915 and 914 (i.e., the magnitudes of the inductor currents I L2 and I L4 ) are approximately equal.
  • state ST_C2 the magnitudes of the currents 917 and 914 (i.e., the magnitudes of the inductor currents I L2 and I L4 ) are approximately equal.
  • the transistors M6 and M8 are on, so that for the capacitors C FLY2 and C MID2 , the state of state ST_C2 is equivalent to a state in which the capacitors C FLY2 and C MID2 are connected in series.
  • the capacitors C FLY2 and C MID2 are connected in parallel through the transistors M7 and M1.
  • a switched capacitor circuit is formed by the circuit including the transistors M5 to M8 and M1 and the capacitors C FLY2 and C MID2 .
  • the control circuit 40C operates the circuit as a switched capacitor circuit, thereby generating an intermediate voltage V MID2 equivalent to a divided voltage of the input voltage V IN at the positive electrode of the capacitor C MID2 .
  • the intermediate voltage V MID2 is substantially equal to the voltage (V IN /2). Strictly speaking, the intermediate voltage V MID2 fluctuates somewhat around the voltage (V IN /2).
  • the boost circuit 50C has a boost circuit for converter CNV1 and a boost circuit for converter CNV2.
  • the boost circuit for converter CNV1 is the same as the boost circuit 50A of the first embodiment (see FIG. 7). Therefore, transistor Ma in the boost circuit for converter CNV1 is off during the on period of transistor M2 and on during the off period of transistor M2. Transistor Mb in the boost circuit for converter CNV1 is off during the on period of transistor M3 and on during the off period of transistor M3. Transistor Mc in the boost circuit for converter CNV1 is off during the on period of transistor M4 and on during the off period of transistor M4. When only the states of transistors M1 to M4 and Ma to Mc are considered, state ST_C2 in FIG. 20 is equivalent to state ST_A1 in FIG. 9, and state ST_C4 in FIG. 22 is equivalent to state ST_A2 in FIG. 10.
  • the boost circuit for converter CNV1 generates a boot voltage for turning on transistors M2 to M4
  • the boost circuit for converter CNV2 generates a boot voltage for turning on transistors M6 to M8.
  • the configuration and operation of the boost circuit for converter CNV2 may be the same as the configuration and operation of the boost circuit for converter CNV1.
  • FIG. 23 shows the internal configuration of control circuit 30C.
  • FIG. 24 shows a timing chart related to the operation of control circuit 30C. From top to bottom, FIG. 24 shows the waveforms of signals CLK1, CMPOUT1, CLK2, CMPOUT2, and CNT1 to CNT8.
  • the control circuit 30C includes an error amplifier 31, ramp circuits 32_1 and 32_2, current information acquisition circuits 33_1 and 33_2, adders 34_1 and 34_2, PWM comparators 35_1 and 35_2, a clock generation circuit 36C, and controllers 37_1 and 37_2.
  • the power supply device 1C includes resistors R1 and R2. The first end of the resistor R1 is connected to the output node ND OUT , the second end of the resistor R1 is connected to the first end of the resistor R2, and the second end of the resistor R2 is connected to the ground. A feedback voltage V FB corresponding to the output voltage V OUT is generated at the connection node between the resistors R1 and R2.
  • the feedback voltage V FB is a divided voltage of the output voltage V OUT , and is therefore proportional to the output voltage V OUT .
  • the resistors R1 and R2 form a feedback voltage generation circuit that generates a feedback voltage V FB .
  • the feedback voltage V FB is supplied to the control circuit 30C.
  • the feedback voltage generating circuit may be understood to be included in the components of the control circuit 30C.
  • the output voltage VOUT itself may be used as the feedback voltage VFB .
  • the feedback voltage VFB is information on the output voltage VOUT (more specifically, information indicating the value of the output voltage VOUT ).
  • the error amplifier 31 is a current output type transconductance amplifier.
  • the error amplifier 31 has an inverting input terminal, a non-inverting input terminal, and an output terminal.
  • a feedback voltage VFB is supplied to the inverting input terminal of the error amplifier 31.
  • a predetermined reference voltage VREF is supplied to the non-inverting input terminal of the error amplifier 31.
  • the reference voltage VREF is a DC voltage having a positive predetermined voltage value, and is generated by a reference voltage generating circuit (not shown) in the control circuit 30C.
  • the output terminal of the error amplifier 31 is connected to the wiring WR ERR .
  • a soft start control may be performed to gradually increase the value of the reference voltage VREF from 0V to a positive predetermined voltage value, but the existence of the soft start control will be ignored below.
  • the error amplifier 31 generates an error voltage V ERR corresponding to the difference between the feedback voltage V FB and the reference voltage V REF on the wiring WR ERR by outputting a current signal corresponding to the difference between the feedback voltage V FB and the reference voltage V REF from its output terminal. Specifically, when the feedback voltage V FB is lower than the reference voltage V REF , the error amplifier 31 outputs a current from its output terminal to the wiring WR ERR so that the error voltage V ERR increases, and when the feedback voltage V FB is higher than the reference voltage V REF , the error amplifier 31 draws a current from the wiring WR ERR to its output terminal so that the error voltage V ERR decreases.
  • a phase compensation circuit including a capacitor may be connected between the wiring WR ERR and ground.
  • the ramp circuit 32_1 generates a ramp voltage V RAMP1 that monotonically rises at a predetermined rate of change from a predetermined initial voltage V INT during an on-period of the transistor M2.
  • the initial voltage V INT is, for example, 0 V, but may be different from 0 V.
  • the ramp voltage V RAMP1 is fixed at the initial voltage V INT .
  • the current information acquisition circuit 33_1 acquires current information of the inductor L1, and generates a sense voltage V IL1 indicating the current information of the inductor L1.
  • the current information of the inductor L1 is information indicating the value of the inductor current IL1 .
  • the sense voltage V IL1 has a voltage value proportional to the value of the inductor current IL1 with a positive proportionality coefficient. Therefore, the sense voltage V IL1 increases as the inductor current IL1 increases, and the sense voltage V IL1 decreases as the inductor current IL1 decreases.
  • V IL1 k IV ⁇ IL1 ", where k IV is a predetermined positive coefficient.
  • the sense voltage VIL1 may be generated in any manner.
  • the sense voltage VIL1 may be generated by directly detecting the inductor current I L1 with a current sensor.
  • the current sensor here may be a shunt resistor (not shown) inserted in series between the inductor L1 and the node ND1.
  • the sense voltage VIL1 may be generated by detecting the current (hence the inductor current I L1 ) flowing through the transistor M2 during the on-period of the transistor M2, or by detecting the current (hence the inductor current I L1 ) flowing through the transistor M1 during the on-period of the transistor M1.
  • the sense voltage VIL1 may be generated by detecting the voltage at any point where a voltage corresponding to the inductor current I L1 is generated.
  • the PWM comparator 35_1 compares the error voltage VERR and the slope voltage VSLP1 , and generates and outputs a signal CMPOUT1 indicating the comparison result.
  • the error voltage VERR is input to the inverting input terminal of the PWM comparator 35_1, and the slope voltage VSLP1 is input to the non-inverting input terminal of the PWM comparator 35_1.
  • the PWM comparator 35_1 outputs a low-level signal CMPOUT1 when " VSLP1 ⁇ VERR " is satisfied, and outputs a high-level signal CMPOUT1 when " VSLP1 > VERR " is satisfied.
  • the signal CMPOUT1 has a low level or a high level.
  • a signal CMPOUT1 and a reference clock signal CLK1 are input to the controller 37_1.
  • the reference clock signal CLK1 is generated by a clock generation circuit 36C.
  • the reference clock signal CLK1 is a rectangular wave signal having a predetermined frequency f PWM , and alternates between high and low signal levels.
  • the duty of the reference clock signal CLK1 is arbitrary.
  • the reference clock signal CLK1 has a low level in principle, and has a high level for a very short time at intervals of the reciprocal of the frequency f PWM (see FIG. 24).
  • the controller 37_1 When a predetermined level change occurs in the reference clock signal CLK1, the controller 37_1 generates a falling edge in the control signals CNT1 and CNT7 to turn off the transistors M1 and M7, and generates a rising edge in the control signals CNT2 and CNT8 to turn on the transistors M2 and M8.
  • the predetermined level change (first predetermined level change) in the reference clock signal CLK1 is a change from a low level to a high level in the reference clock signal CLK1, but it may also be a change from a high level to a low level in the reference clock signal CLK1.
  • the slope voltage V SLP1 rises monotonically and transitions from a state where "V SLP1 ⁇ V ERR " is satisfied to a state where "V SLP1 > V ERR " is satisfied, causing a rising edge in the signal CMPOUT1.
  • the controller 37_1 turns on the transistors M1 and M7 by causing a rising edge in the control signals CNT1 and CNT7, and turns off the transistors M2 and M8 by causing a falling edge in the control signals CNT2 and CNT8.
  • the ramp voltage V RAMP1 drops to a sufficiently low initial voltage V INT , returning to a state where "V SLP1 ⁇ V ERR " is satisfied, and a falling edge occurs promptly in the signal CMPOUT1.
  • the time from when the transistors M1 and M7 are turned off and the transistors M2 and M8 are turned on to when the transistors M1 and M7 are turned on and the transistors M2 and M8 are turned off is referred to as time t ON1 .
  • the ramp circuit 32_2 generates a ramp voltage V RAMP2 that monotonically rises at a predetermined rate of change from a predetermined initial voltage V INT during the on-period of the transistor M6.
  • the initial voltage V INT is, for example, 0 V, but may be different from 0 V.
  • the ramp voltage V RAMP2 is fixed at the initial voltage V INT .
  • the ramp circuit 32_2 has the same configuration as the ramp circuit 32_1. Therefore, the rate of change of the ramp voltage V RAMP2 during the on-period of the transistor M6 is equal to the rate of change of the ramp voltage V RAMP1 during the on-period of the transistor M2.
  • the current information acquisition circuit 33_2 acquires current information of the inductor L2, and generates a sense voltage V IL2 indicating the current information of the inductor L2.
  • the current information of the inductor L2 is information indicating the value of the inductor current IL2 .
  • the sense voltage V IL2 has a voltage value proportional to the value of the inductor current IL2 with a positive proportionality coefficient. Therefore, the sense voltage V IL2 rises as the inductor current IL2 increases, and the sense voltage V IL2 falls as the inductor current IL2 decreases.
  • V IL2 k IV ⁇ IL2 ".
  • the method of generating the sense voltage V IL2 is arbitrary.
  • the sense voltage V IL2 may be generated by directly detecting the inductor current IL2 with a current sensor.
  • the current sensor here may be a shunt resistor (not shown) inserted in series between the inductor L2 and the node ND5.
  • the sense voltage V IL2 may be generated by detecting the current (hence the inductor current IL2 ) flowing through the transistor M6 during the on-period of the transistor M6, or the current (hence the inductor current IL2) flowing through the transistor M5 during the on-period of the transistor M5.
  • the sense voltage V IL2 may be generated by detecting the voltage at any point where a voltage corresponding to the inductor current IL2 is generated.
  • the PWM comparator 35_2 compares the error voltage VERR and the slope voltage VSLP2 , and generates and outputs a signal CMPOUT2 indicating the comparison result.
  • the error voltage VERR is input to the inverting input terminal of the PWM comparator 35_2, and the slope voltage VSLP2 is input to the non-inverting input terminal of the PWM comparator 35_2.
  • the PWM comparator 35_2 outputs a low-level signal CMPOUT2 when " VSLP2 ⁇ VERR " is satisfied, and outputs a high-level signal CMPOUT2 when " VSLP2 > VERR " is satisfied.
  • the signal CMPOUT2 has a low level or a high level.
  • a signal CMPOUT2 and a shift clock signal CLK2 are input to the controller 37_2.
  • the shift clock signal CLK2 is generated by the clock generation circuit 36C based on the reference clock CLK1.
  • the shift clock signal CLK2 is a signal obtained by shifting the phase of the reference clock CLK1. Therefore, the reference clock signal CLK1 and the shift clock signal CLK2 have the same frequency f PWM and different phases.
  • the shift clock signal CLK2 has a low level in principle and has a high level for a small period of time at an interval of the reciprocal of the frequency f PWM (see FIG. 24).
  • the shift clock signal CLK2 is assumed to be a signal whose phase is delayed by 180° from the reference clock signal CLK1.
  • the phase difference between the clock signals CLK1 and CLK2 is 180°.
  • Setting the delay amount to 180° is optimal for minimizing the ripple of the output voltage V OUT .
  • the amount of delay in phase of the shift clock signal CLK2 with respect to the phase of the reference clock signal CLK1 may be other than 180° (for example, it may be 170° or 190°).
  • the controller 37_2 When a predetermined level change occurs in the shift clock signal CLK2, the controller 37_2 generates a falling edge in the control signals CNT3 and CNT5 to turn off the transistors M3 and M5, and generates a rising edge in the control signals CNT4 and CNT6 to turn on the transistors M4 and M6.
  • the predetermined level change (second predetermined level change) in the shift clock signal CLK2 is a change from a low level to a high level in the shift clock signal CLK2, but it may also be a change from a high level to a low level in the shift clock signal CLK2.
  • the controller 37_2 turns on the transistors M3 and M5 by causing a rising edge in the control signals CNT3 and CNT5, and turns off the transistors M4 and M6 by causing a falling edge in the control signals CNT4 and CNT6.
  • the ramp voltage V RAMP2 drops to a sufficiently low initial voltage V INT , returning to a state where "V SLP2 ⁇ V ERR " is satisfied, and a falling edge occurs promptly in the signal CMPOUT2.
  • the time from when the transistors M3 and M5 are turned off and the transistors M4 and M6 are turned on to when the transistors M3 and M5 are turned on and the transistors M4 and M6 are turned off is referred to as time t ON2 .
  • the above switching control by the controllers 37_1 and 37_2 causes the states of the transistors M1 to M8 to switch sequentially between states ST_C1 to ST_C4, as shown in Fig. 24 (see also Figs. 19 to 22). That is, in the timing chart of Fig. 24, starting from state ST_C3, the states of the transistors M1 to M8 switch from state ST_C3 to state ST_C2 at the rising edge of the reference clock signal CLK1, then switch from state ST_C2 to state ST_C1 at the rising edge of the signal CMPOUT2, then switch from state ST_C1 to state ST_C4 at the rising edge of the signal CMPOUT1, and then return from state ST_C4 to state ST_C3 at the rising edge of the shift clock signal CLK2.
  • the length between the timing of the transition from state ST_C3 to state ST_C2 and the timing of the next transition from state ST_C3 to state ST_C2 matches the reciprocal of the frequency f PWM of the reference clock signal CLK1.
  • the above-mentioned time tON1 depends on the error voltage VERR (and therefore on the information of the output voltage VOUT ) and on the sense voltage VIL1 (and therefore on the current information of the inductor L1). That is, the controller 37_1 controls the switching of the transistors M1, M2, M7, and M8 in synchronization with the reference clock signal CLK1 based on the information of the output voltage VOUT and the current information of the inductor L1.
  • the controller 37_1 After turning off the transistors M1 and M7 and turning on the transistors M2 and M8 in response to a predetermined level change in the reference clock signal CLK1, the controller 37_1 turns on the transistors M1 and M7 and turns off the transistors M2 and M8 when the time tON1 according to the information of the output voltage VOUT and the current information of the inductor L1 has elapsed.
  • the above-mentioned time t ON2 depends on the error voltage V ERR (and therefore on the information of the output voltage V OUT ) and on the sense voltage V IL2 (and therefore on the current information of the inductor L2). That is, the controller 37_2 controls the switching of the transistors M3 to M6 in synchronization with the shift clock signal CLK2 based on the information of the output voltage V OUT and the current information of the inductor L2.
  • the controller 37_2 After turning off the transistors M3 and M5 and turning on the transistors M4 and M6 in response to a predetermined level change in the shift clock signal CLK2, the controller 37_2 turns on the transistors M3 and M5 and turns off the transistors M4 and M6 when the time t ON2 according to the information of the output voltage V OUT and the current information of the inductor L2 has elapsed.
  • Converters CNV1 and CNV2 have the same configuration.
  • the switching control of transistors M1, M2, M7, and M8 based on the current information of inductor L1 is equivalent to the switching control of transistors M3, M4, M5, and M6 based on the current information of inductor L2. Therefore, multiphase operation is achieved with a balance between the output current of converter CNV1 and the output current of converter CNV2.
  • the output current of the converter CNV1 is the sum of the inductor currents I L1 and I L3
  • the output current of the converter CNV2 is the sum of the inductor currents I L2 and I L4 .
  • the average of the output current of the buck converter of the first channel (i.e., the inductor current I L1 ) and the average of the output current of the stacked converter of the first channel (i.e., the inductor current I L3 ) are substantially the same.
  • the average of the output current of the buck converter of the second channel i.e., the inductor current I L2
  • the average of the output current of the stacked converter of the second channel i.e., the inductor current I L4
  • the average of the inductor currents I L1 to I L4 at each timing are different from each other, the average of the inductor current I L1 , the average of the inductor current I L2 , the average of the inductor current I L3 , and the average of the inductor current I L4 are substantially equal.
  • the output current of the first channel buck converter i.e., inductor current I L1
  • the output current of the second channel buck converter i.e., inductor current I L2
  • the output current of the first channel stacked converter i.e., inductor current I L3
  • the output current of the second channel stacked converter i.e., inductor current I L4
  • the output current of the first channel buck converter (i.e., inductor current I L1 ) and the output current of the first channel stacked converter (i.e., inductor current I L3 ) have different phases
  • the output current of the second channel buck converter (i.e., inductor current I L2 ) and the output current of the second channel stacked converter (i.e., inductor current I L4 ) have different phases.
  • power supply device 1C may be modified to power supply device 1C' in FIG. 25.
  • the only difference is that no current flows through inductors L3 and L4 as seen from power supply device 1C; otherwise, the configuration and operation of power supply device 1C' are the same as those of power supply device 1C.
  • the capacitor C MID2 may be omitted in the power supply device 1C or 1C', in which case the nodes ND2 and ND6 are shorted.
  • the capacitor C MID2 may be omitted in the power supply device 1C or 1C', and the capacitor C MID1 may be inserted between the nodes ND2 and ND6 (i.e., the first end of the capacitor C MID1 may be connected to the node ND2 and the second end of the capacitor C MID1 may be connected to the node ND6).
  • the power supply device 1 is referred to as the power supply device 1.
  • the power supply device 1 may be any of the power supply devices described in the first to third embodiments, and therefore may be any of the power supply devices 1A, 1B, 1C, and 1C'.
  • the power supply device 1 can be applied to any device or system that requires a stable DC voltage.
  • the power supply device 1 may be applied to a power supply system for a data center.
  • the output voltage V OUT in the power supply device 1 may be 48V, and the power supply device 1 supplies the output voltage V OUT to a 48V power bus.
  • the power supply device 1 may be applied to a primary power supply in a vehicle such as an automobile.
  • the power supply device 1 may directly receive an input voltage V IN from a battery mounted on the vehicle to generate an output voltage V OUT , and the output voltage V OUT may function as a driving voltage for any system (e.g., an autonomous driving system of level 3 or higher) mounted on the vehicle.
  • the power supply device 1 may be applied to a power supply for a charging system.
  • the charging system may charge a battery of an electric vehicle.
  • the power supply device 1 may be applied to a power supply for a base station.
  • the channel types of the FETs (field effect transistors) shown in each embodiment are examples.
  • the channel type of any FET can be changed between P-channel and N-channel without compromising the above-mentioned gist.
  • any of the transistors described above may be any type of transistor, provided that no disadvantage arises.
  • any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantage arises.
  • Any of the transistors has a first electrode, a second electrode, and a control electrode.
  • a FET one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate.
  • IGBT In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate.
  • a bipolar transistor that does not belong to the IGBT one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.
  • a power supply device (e.g., 1A; see FIG. 1 and FIG. 6 to FIG. 8) according to one aspect of the present disclosure includes a first switching element (M1) provided between a reference node having a potential lower than an input voltage (V IN ) and a first node (ND1), a second switching element (M2) provided between the first node and a second node (ND2), a third switching element (M3) provided between the second node and a third node (ND3), a fourth switching element (M4) provided between the third node and a fourth node (ND4) receiving the input voltage, and generates a first boot voltage (V BOOT1 ) on a first boot wiring (W BOOT1 ) that is supplied to a gate of the second switching element to turn on the second switching element, and generates a second boot voltage (V BOOT2 ) on a second boot wiring (W BOOT2 ) that is supplied to the gate of the third switching element to turn on the third switching element.
  • M1 first boot voltage
  • the boost circuit includes a first boot capacitor (C BOOT1 ) provided between the first node and the first boot wiring, and a second boot capacitor (C BOOT2 ) provided between the second node and the second boot wiring.
  • C BOOT3 a third boot capacitor (C BOOT3 ) provided between the third node and the third boot wiring, a first boot switch (Ma) provided between the first boot wiring and a drive wiring (W DRV ) to which the drive voltage is applied, a second boot switch (Mb) provided between the first boot wiring and the second boot wiring, and a third boot switch (Mc) provided between the second boot wiring and the third boot wiring, and the first boot voltage to the third boot voltage are generated by the control circuit controlling the states of each switching element and each boot switch (first configuration).
  • the control circuit may be configured to switch the states of the first switching element to the fourth switching element between a plurality of states including a first state (ST_A1) and a second state (ST_A2), in which in the first state, the second switching element and the fourth switching element are on and the first switching element and the third switching element are off, and in the second state, the second switching element and the fourth switching element are off and the first switching element and the third switching element are on (second configuration).
  • ST_A1 first state
  • ST_A2 second state
  • the boost circuit may be configured to set the first boot switch and the third boot switch to off and the second boot switch to on in the first state, and to set the first boot switch and the third boot switch to on and the second boot switch to off in the second state (third configuration).
  • the first boot switch to the third boot switch may each be configured with a P-channel field effect transistor (fourth configuration).
  • each boot switch By configuring each boot switch with a P-channel type field effect transistor, it is possible to obtain a high boot voltage. As a result, the switching loss of each switching element can be kept low. Furthermore, when configuring a power supply unit using a semiconductor device having a semiconductor integrated circuit and a group of disk lead components, a control circuit etc. can be provided in the semiconductor integrated circuit, and in this case, each boot switch can also be easily provided in the semiconductor integrated circuit. This makes it possible to reduce the number of components in the power supply unit, which in turn makes it possible to miniaturize the power supply unit.
  • the boost circuit may be configured to set the first boot switch on or off based on the voltage of the first node (V LX ) and the first boot voltage, set the second boot switch on or off based on the voltage of the second node (V MID ) and the second boot voltage, and set the third boot switch on or off based on the voltage of the third node (V FLY ) and the third boot voltage (fifth configuration).
  • the control circuit performs switching control to switch the states of the first to fourth switching elements between the plurality of states based on information about the output voltage and current information about an inductor (L1) provided between the first node and an output node to which the output voltage is applied, thereby dividing the input voltage and stepping down an intermediate voltage (V MID ) obtained by the voltage division to generate the output voltage, and the control circuit, in the switching control, operates a circuit having the first to fourth switching elements, an intermediate capacitor (C MID ) connected to the second node, and a flying capacitor (C FLY ) connected to the third node as a switched capacitor circuit, thereby generating the intermediate voltage at the second node (sixth configuration).
  • the control signal generated by the control circuit includes first to fourth control signals (CNT1 to CNT4)
  • the drive circuit includes a first gate driver (42_1) configured to drive the gate of the first switching element in response to the first control signal based on the drive voltage and a voltage of the reference node ( VSS ), thereby turning on or off the first switching element, a second gate driver (42_2) configured to drive the gate of the second switching element in response to the second control signal based on the first boot voltage and a voltage of the first node (V LX ), thereby turning on or off the second switching element, a third gate driver (42_3) configured to drive the gate of the third switching element in response to the third control signal based on the second boot voltage and a voltage of the second node (V MID ) , thereby turning on or off the third switching element, and and a fourth gate driver (42_4) configured to drive the gate of the fourth switching element in response to the fourth control signal based on the fourth

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PCT/JP2024/019747 2023-07-19 2024-05-29 電源装置 Pending WO2025018033A1 (ja)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020501488A (ja) * 2016-12-01 2020-01-16 インテグレーテッド・デバイス・テクノロジー・インコーポレーテッド バッテリ充電システム
JP2020156161A (ja) * 2019-03-19 2020-09-24 株式会社明電舎 Ｆｃ型３レベル電力変換装置
JP2021069160A (ja) * 2019-10-18 2021-04-30 ローム株式会社 スイッチング電源装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020501488A (ja) * 2016-12-01 2020-01-16 インテグレーテッド・デバイス・テクノロジー・インコーポレーテッド バッテリ充電システム
JP2020156161A (ja) * 2019-03-19 2020-09-24 株式会社明電舎 Ｆｃ型３レベル電力変換装置
JP2021069160A (ja) * 2019-10-18 2021-04-30 ローム株式会社 スイッチング電源装置

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