WO2025013769A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2025013769A1
WO2025013769A1 PCT/JP2024/024329 JP2024024329W WO2025013769A1 WO 2025013769 A1 WO2025013769 A1 WO 2025013769A1 JP 2024024329 W JP2024024329 W JP 2024024329W WO 2025013769 A1 WO2025013769 A1 WO 2025013769A1
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region
gate
source
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semiconductor
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French (fr)
Japanese (ja)
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誠悟 森
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/054—Forming charge compensation regions, e.g. superjunctions by high energy implantations in bulk semiconductor bodies, e.g. forming pillars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/058—Forming charge compensation regions, e.g. superjunctions by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H10D64/2527—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Definitions

  • Patent document 1 discloses a semiconductor device including a p-type doped region formed in an n-type epitaxial layer directly below a trench gate structure.
  • the present disclosure provides a semiconductor device capable of improving electrical characteristics.
  • the present disclosure provides a semiconductor device including a chip having a principal surface, a first conductivity type semiconductor region formed in a surface layer of the principal surface, a trench-type source structure formed in the principal surface and positioned within the semiconductor region, and a second conductivity type impurity region formed in a region directly below the source structure within the chip and forming a pn junction with the semiconductor region.
  • the present disclosure provides a semiconductor device including a chip having a main surface, a semiconductor region of a first conductivity type formed on a surface layer portion of the main surface, a trench-type gate structure formed on the main surface and positioned within the semiconductor region, a trench-type source structure formed on the main surface at a distance from the gate structure and positioned within the semiconductor region, a first impurity region of a second conductivity type formed in a region directly below the gate structure within the chip, and a second impurity region of a second conductivity type formed in a region directly below the source structure at a distance from the first impurity region within the chip.
  • the present disclosure provides a method for manufacturing a semiconductor device, including the steps of preparing a wafer having a semiconductor region of a first conductivity type in a surface layer of its main surface, forming a source trench in the main surface so as to be positioned within the semiconductor region, and introducing an impurity of a second conductivity type into the semiconductor region through a bottom wall of the source trench to form an impurity region of the second conductivity type that forms a pn junction with the semiconductor region in a region directly below the source trench.
  • FIG. 1 is a plan view showing a semiconductor device.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a perspective view showing the shape of the chip.
  • FIG. 4 is a plan view showing an example of the layout of the first main surface.
  • FIG. 5 is an enlarged plan view showing a main portion of the first main surface together with a contact region according to a first layout example.
  • FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG.
  • FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG.
  • FIG. 8 is an enlarged cross-sectional view showing a main portion of the region shown in FIG. FIG.
  • FIG. 9 is an enlarged cross-sectional view showing a main portion of the region shown in FIG.
  • FIG. 10 is a graph showing an example of the concentration gradient in the column region.
  • FIG. 11 is a graph showing another example of the concentration gradient in the column region.
  • FIG. 12A is an enlarged plan view showing a main portion of the first main surface together with a contact region according to a second layout example.
  • FIG. 12B is an enlarged plan view showing a main portion of the first main surface together with a contact region according to the third layout example.
  • FIG. 12C is an enlarged plan view showing a main portion of the first main surface together with a contact region according to the fourth layout example.
  • FIG. 12A is an enlarged plan view showing a main portion of the first main surface together with a contact region according to a second layout example.
  • FIG. 12B is an enlarged plan view showing a main portion of the first main surface together with a contact region according to the third layout example.
  • FIG. 12C is an enlarged plan
  • FIG. 12D is an enlarged plan view showing a main portion of the first main surface together with a contact region according to the fifth layout example.
  • FIG. 12E is an enlarged plan view showing a main portion of the first main surface together with a contact region according to the sixth layout example.
  • FIG. 12F is an enlarged plan view showing a main portion of the first main surface together with a contact region according to the seventh layout example.
  • FIG. 13 is a schematic diagram showing a wafer used in the manufacture of semiconductor devices.
  • FIG. 14A is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.
  • FIG. 14B is a cross-sectional view showing a step subsequent to FIG. 14A.
  • FIG. 14C is a cross-sectional view showing a step subsequent to FIG. 14B.
  • FIG. 14D is a cross-sectional view showing a step subsequent to FIG. 14C.
  • FIG. 14E is a cross-sectional view showing a step subsequent to FIG. 14D.
  • FIG. 14F is a cross-sectional view showing a step subsequent to FIG. 14E.
  • FIG. 14G is a cross-sectional view showing a step subsequent to FIG. 14F.
  • FIG. 14H is a cross-sectional view showing a step subsequent to FIG. 14G.
  • FIG. 14I is a cross-sectional view showing a step subsequent to FIG. 14H.
  • FIG. 14J is a cross-sectional view showing a step subsequent to FIG. 14I.
  • FIG. 14K is a cross-sectional view showing a step subsequent to FIG. 14J.
  • FIG. 14L is a cross-sectional view showing a step subsequent to FIG. 14K.
  • FIG. 14M is a cross-sectional view showing a step subsequent to FIG. 14L.
  • FIG. 14N is a cross-sectional view showing a step subsequent to FIG. 14M.
  • FIG. 15 is a cross-sectional view showing a semiconductor device according to a first modification.
  • FIG. 16 is a cross-sectional view showing a semiconductor device according to a second modification.
  • FIG. 17 is a cross-sectional view showing a semiconductor device according to a third modification.
  • FIG. 18 is a cross-sectional view showing a semiconductor device according to a fourth modification.
  • this term includes a numerical value (shape) that is equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • shape a numerical value that is equal to the numerical value (shape) of the comparison target
  • error a numerical error within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • the conductivity type of a semiconductor is indicated using “p-type” or “n-type”, but “p-type” may also be referred to as the “first conductivity type” and “n-type” as the “second conductivity type”. Of course, “n-type” may also be referred to as the "first conductivity type” and “p-type” as the “second conductivity type”.
  • P-type is a conductivity type resulting from a trivalent element
  • n-type is a conductivity type resulting from a pentavalent element.
  • the trivalent element is at least one of boron, aluminum, gallium, and indium.
  • the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • FIG. 1 is a plan view showing a semiconductor device 1.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1.
  • FIG. 3 is a perspective view showing the shape of a chip 2.
  • FIG. 4 is a plan view showing an example layout of a first main surface 3.
  • FIG. 5 is an enlarged plan view showing a main portion of the first main surface 3 together with the contact region 35 according to the first layout example.
  • FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 5.
  • FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 5.
  • FIG. 8 is an enlarged cross-sectional view showing a main portion of the region shown in FIG. 6.
  • FIG. 9 is an enlarged cross-sectional view showing a main portion of the region shown in FIG. 7.
  • the semiconductor device 1 is a semiconductor switching device including an insulated gate type transistor structure Tr.
  • the transistor structure Tr may be referred to as a MISFET structure (Metal Insulator Semiconductor Field Effect Transistor structure).
  • the transistor structure Tr has a vertical structure.
  • semiconductor device 1 includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape).
  • chip 2 includes a single crystal of a wide bandgap semiconductor.
  • semiconductor device 1 is a "wide bandgap semiconductor device.”
  • Chip 2 may also be referred to as a “semiconductor chip,” a “wide bandgap semiconductor chip,” etc.
  • a wide bandgap semiconductor is a semiconductor that has a bandgap that exceeds the bandgap of Si (silicon).
  • Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond).
  • chip 2 is a "SiC chip” that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor.
  • semiconductor device 1 is a "SiC semiconductor device.”
  • the semiconductor device 1 may be referred to as a "SiC-MISFET.”
  • the hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like.
  • the chip 2 includes a 4H-SiC single crystal, but the chip 2 may include other polytypes.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view").
  • the vertical direction Z is also the thickness direction of the chip 2.
  • the first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal.
  • the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal
  • the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.
  • the first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.
  • the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal
  • the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal.
  • the first direction X may be the a-axis direction of the SiC single crystal
  • the second direction Y may be the m-axis direction of the SiC single crystal.
  • the direction extending along the first main surface 3 may be referred to as the "horizontal direction.”
  • the horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.
  • the chip 2 (first main surface 3 and second main surface 4) has an off angle that is inclined at a predetermined angle in a predetermined off direction relative to the c-plane of the SiC single crystal.
  • the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical line toward the off direction by the off angle.
  • the c-plane of the SiC single crystal is inclined by the off angle relative to the horizontal plane.
  • the off-direction is preferably the a-axis direction of the SiC single crystal (the second direction Y in this embodiment).
  • the off-angle may be greater than 0° and less than or equal to 10°.
  • the off-angle may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.
  • the off angle is preferably 5° or less. It is particularly preferable that the off angle be 2° or more and 4.5° or less.
  • the off angle is typically set in the range of 4° ⁇ 0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane relative to the c-plane).
  • the semiconductor device 1 includes an n-type first semiconductor region 6 formed in a surface layer of the second main surface 4 of the chip 2.
  • a drain potential is applied to the first semiconductor region 6 as a first potential (high potential).
  • the first semiconductor region 6 may be referred to as a "semiconductor layer", a “first semiconductor layer”, a “drain region”, etc.
  • the first semiconductor region 6 is formed in a layer extending along the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the first semiconductor region 6 is made of an n-type semiconductor layer.
  • the first semiconductor region 6 is made of a substrate (SiC substrate) containing SiC single crystal (semiconductor single crystal), and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the first semiconductor region 6 (substrate) has the off direction and off angle described above.
  • the first semiconductor region 6 may have a thickness of 10 ⁇ m or more and 500 ⁇ m or less.
  • the thickness of the first semiconductor region 6 may have a value that belongs to at least one of the following ranges: 10 ⁇ m or more and 50 ⁇ m or less, 50 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 150 ⁇ m or less, 150 ⁇ m or more and 200 ⁇ m or less, 200 ⁇ m or more and 300 ⁇ m or less, 300 ⁇ m or more and 400 ⁇ m or less, and 400 ⁇ m or more and 500 ⁇ m or less.
  • the semiconductor device 1 includes an n-type second semiconductor region 7 formed in a surface layer of the first main surface 3 of the chip 2.
  • the second semiconductor region 7 may be referred to as a "semiconductor layer,” a “second semiconductor layer,” a “drift region,” or the like.
  • the second semiconductor region 7 has an n-type impurity concentration that is less than the n-type impurity concentration of the first semiconductor region 6.
  • the second semiconductor region 7 is formed in a layer extending along the first main surface 3 and is electrically connected to the first semiconductor region 6. The second semiconductor region 7 is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the second semiconductor region 7 is made of an n-type semiconductor layer.
  • the second semiconductor region 7 is made of an epitaxial layer (SiC epitaxial layer) containing SiC single crystal (semiconductor single crystal), and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the second semiconductor region 7 (epitaxial layer) has the off direction and off angle described above. It is preferable that the second semiconductor region 7 has a thickness less than that of the first semiconductor region 6. Of course, the thickness of the second semiconductor region 7 may be greater than the thickness of the first semiconductor region 6.
  • the thickness of the second semiconductor region 7 may be 5 ⁇ m or more and 50 ⁇ m or less.
  • the thickness of the second semiconductor region 7 may have a value that belongs to at least one of the following ranges: 5 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 15 ⁇ m or less, 15 ⁇ m or more and 20 ⁇ m or less, 20 ⁇ m or more and 25 ⁇ m or less, 25 ⁇ m or more and 30 ⁇ m or less, 30 ⁇ m or more and 35 ⁇ m or less, 35 ⁇ m or more and 40 ⁇ m or less, 40 ⁇ m or more and 45 ⁇ m, and 45 ⁇ m or more and 50 ⁇ m or less.
  • the second semiconductor region 7 has a concentration gradient in which the n-type impurity concentration changes in the thickness direction.
  • the second semiconductor region 7 includes a low concentration region 7a on the bottom side and a high concentration region 7b on the surface side, and has a concentration gradient in which the n-type impurity concentration increases from the bottom side to the surface side.
  • the boundary between the high concentration region 7b and the low concentration region 7a is defined by the bottom of the high concentration region 7b.
  • the bottom of the high concentration region 7b is the portion where the n-type impurity concentration gradually decreases toward the low concentration region 7a (from the first main surface 3 side to the second main surface 4 side).
  • the low concentration region 7a is formed in a layer extending along the first main surface 3 and is electrically connected to the first semiconductor region 6.
  • the low concentration region 7a is exposed from the first to fourth side surfaces 5A to 5D.
  • the thickness of the low concentration region 7a may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the low concentration region 7a may have a value belonging to any one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 4 ⁇ m or less, and 4 ⁇ m or more and 5 ⁇ m or less.
  • the high concentration region 7b is formed in a thickness range between the first main surface 3 and the low concentration region 7a, and is electrically connected to the first semiconductor region 6 via the low concentration region 7a.
  • the high concentration region 7b is formed in a layer extending along the first main surface 3, and faces the first semiconductor region 6 across the low concentration region 7a.
  • the high concentration region 7b is exposed from the first to fourth side surfaces 5A to 5D.
  • the high concentration region 7b may be exposed from the first main surface 3, or may be formed at a distance from the first main surface 3 towards the second main surface 4.
  • the high concentration region 7b may have a portion located in a region on the first major surface 3 side relative to the intermediate part of the thickness range of the second semiconductor region 7, and a portion located in a region on the bottom side of the second semiconductor region 7 relative to the intermediate part of the thickness range of the second semiconductor region 7.
  • the high concentration region 7b may be located only in the region on the first major surface 3 side relative to the intermediate part of the thickness range of the second semiconductor region 7.
  • the high concentration region 7b may be formed by introducing a pentavalent element (n-type impurity) into the n-type semiconductor layer.
  • the high concentration region 7b may be composed of an n-type channeling region extending along the axial channel of the chip 2 (second semiconductor region 7) in a cross-sectional view.
  • the axial channel is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the chip 2 (second semiconductor region 7), and is surrounded by atomic rows that form a crystal axis extending in the thickness direction (crystal growth direction).
  • the axial channel is a region in which the atomic rows are sparse extending in the thickness direction, and in which the atomic rows (atomic distance/atomic density) are sparse in the horizontal direction in a planar view.
  • the axial channel is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.
  • a low-index crystal axis is a crystal axis in which the absolute values of "a1", "a2", “a3” and "c" are all expressed as 2 or less (preferably 1 or less) with respect to the Miller indices (a1, a2, a3, c).
  • the axial channel consists of a region surrounded by atomic rows along the c-axis ((0001) axis) of the SiC single crystal.
  • the axial channel extends along the c-axis and has the off-direction and off-angle described above.
  • the axial channel is inclined from the vertical axis toward the off-direction by the off-angle.
  • the high concentration region 7b is an impurity region introduced parallel or nearly parallel to a region (axial channel) surrounded by atomic rows along a low index crystal axis in the chip 2, and may be inclined obliquely with respect to the first main surface 3.
  • the high concentration region 7b may have a thickness greater than that of the low concentration region 7a.
  • the thickness of the high concentration region 7b may be less than the thickness of the low concentration region 7a.
  • the semiconductor device 1 includes a first surface portion 8, a second surface portion 9, and first to fourth connection surface portions 10A to 10D formed on the first main surface 3.
  • the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D define a mesa on the first main surface 3.
  • the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D may be considered to be components of the chip 2 (first main surface 3).
  • the first surface portion 8 may be referred to as the "active surface”
  • the second surface portion 9 may be referred to as the “outer surface”
  • the first to fourth connecting surface portions 10A to 10D may be referred to as “connecting surfaces”
  • the mesa may be referred to as the "active mesa”.
  • the first surface portion 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3.
  • the first surface portion 8 has a flat surface extending horizontally, and is formed by a c-plane (Si-plane).
  • the first surface portion 8 is formed in a polygonal shape (specifically, a quadrilateral shape) having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.
  • the planar area of the first surface portion 8 is preferably 50% to 90% of the planar area of the first main surface 3.
  • the second surface portion 9 is located on the peripheral side of the first main surface 3 relative to the first surface portion 8, and is recessed from the height position of the first surface portion 8 in the thickness direction of the chip 2 (towards the second main surface 4).
  • the second surface portion 9 extends in a band shape along the first surface portion 8 in a plan view, and is formed in a ring shape (specifically, a square ring shape) surrounding the first surface portion 8.
  • the second surface portion 9 is connected to the first to fourth side surfaces 5A to 5D.
  • the second surface 9 is formed approximately parallel to the first surface 8, and has a flat surface extending horizontally.
  • the second surface 9 is formed by the c-plane (Si-plane).
  • the second surface 9 is formed in the second semiconductor region 7 with a space therebetween from the first semiconductor region 6. In other words, the second surface 9 is recessed to a depth less than the thickness of the second semiconductor region 7, exposing the second semiconductor region 7.
  • the second surface portion 9 is formed in the high concentration region 7b at a distance from the low concentration region 7a, exposing the high concentration region 7b.
  • the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D are formed by the high concentration region 7b.
  • the second surface portion 9 may have a depth of 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the second surface portion 9 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the second surface portion 9 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the first to fourth connection surface portions 10A to 10D extend in the vertical direction Z and are connected to the first surface portion 8 and the second surface portion 9.
  • the first connection surface portion 10A is located on the first side surface 5A side
  • the second connection surface portion 10B is located on the second side surface 5B side
  • the third connection surface portion 10C is located on the third side surface 5C side
  • the fourth connection surface portion 10D is located on the fourth side surface 5D side.
  • the first connection surface portion 10A and the second connection surface portion 10B extend in the first direction X and face the second direction Y.
  • the third connection surface portion 10C and the fourth connection surface portion 10D extend in the second direction Y and face the first direction X.
  • the mesa is defined in a protruding (convex) shape on the first main surface 3.
  • the mesa is formed only in the second semiconductor region 7, and not in the first semiconductor region 6.
  • the first to fourth connection surface portions 10A to 10D may extend substantially vertically between the first surface portion 8 and the second surface portion 9, defining a mesa in the shape of a quadrangular prism.
  • the first to fourth connection surface portions 10A to 10D may be inclined obliquely downward from the first surface portion 8 toward the second surface portion 9, defining a mesa in the shape of a truncated quadrangular pyramid.
  • the first to fourth connection surface portions 10A to 10D may be inclined at an angle of more than 90° and not more than 135° with respect to the first surface portion 8.
  • the semiconductor device 1 includes an active region 11 set in the chip 2.
  • the active region 11 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated.
  • the active region 11 is set in the inner part of the chip 2. Specifically, the active region 11 is set in the first surface portion 8.
  • the semiconductor device 1 includes a peripheral region 12 that is set outside the active region 11 in the chip 2.
  • the peripheral region 12 is a region that does not include a device structure (transistor structure Tr).
  • the peripheral region 12 is set on the periphery of the chip 2.
  • the peripheral region 12 is set on the second surface 9.
  • the peripheral region 12 is set in the region between the periphery of the first surface 8 and the periphery of the second surface 9 in a plan view.
  • the semiconductor device 1 includes a p-type body region 13 formed in a surface layer of the first surface portion 8 (first main surface 3) in the active region 11.
  • the body region 13 may be referred to as a "channel region", a "base region”, etc.
  • a source potential is applied to the body region 13 as a second potential (low potential) different from a first potential (high potential).
  • the source potential may be a reference potential that serves as a reference for circuit operation.
  • the reference potential may be a ground potential or a potential other than the ground potential.
  • the body region 13 is formed at a distance from the bottom of the second semiconductor region 7 toward the first surface portion 8, and faces the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the body region 13 is formed in a thickness range between the first main surface 3 and the high concentration region 7b in a cross-sectional view.
  • the body region 13 is formed in a region on the first main surface 3 side with respect to the depth position of the high concentration region 7b, and faces the low concentration region 7a across the high concentration region 7b. It is preferable that the body region 13 has a thickness less than the thickness of the high concentration region 7b. Of course, the thickness of the body region 13 may be greater than the thickness of the high concentration region 7b.
  • the body region 13 is formed at a distance from the depth position of the second surface portion 9 toward the first surface portion 8.
  • the body region 13 is formed in a layer extending along the first surface portion 8.
  • the body region 13 is formed over the entire first surface portion 8 and is exposed from the first to fourth connection surface portions 10A to 10D.
  • the body region 13 may also be formed at a distance inward from the periphery of the first surface portion 8.
  • the semiconductor device 1 includes an n-type source region 14 formed in the surface layer of the first surface portion 8 (first main surface 3) in the active region 11. A source potential is applied to the source region 14.
  • the source region 14 has an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7 (low concentration region 7a). It is preferable that the n-type impurity concentration of the source region 14 is higher than the n-type impurity concentration of the high concentration region 7b.
  • the source region 14 is formed in the surface layer of the body region 13. Specifically, the source region 14 is formed at a distance from the bottom of the body region 13 toward the first surface portion 8. In other words, the source region 14 is formed in a region on the first surface portion 8 side relative to the depth position of the body region 13 in a cross-sectional view.
  • the source region 14 forms a transistor channel together with the second semiconductor region 7 in the body region 13.
  • the source region 14 extends in a layered manner along the first surface portion 8.
  • the source region 14 is formed at a distance inward from the periphery of the first surface portion 8. Therefore, the source region 14 is not exposed from the first to fourth connection surface portions 10A to 10D.
  • the source region 14 may be formed on the entire surface of the first surface portion 8 and exposed from the first to fourth connection surface portions 10A to 10D.
  • the semiconductor device 1 includes a plurality of trench-type (trench electrode-type) gate structures 15 formed in the first surface portion 8 (first main surface 3) in the active region 11.
  • the gate structures 15 may be referred to as "first trench structures", “trench gate structures”, etc.
  • a gate potential is applied to the plurality of gate structures 15 as a control potential.
  • the plurality of gate structures 15 control the inversion and non-inversion of the channel in the body region 13 in response to the gate potential.
  • the multiple gate structures 15 are arranged on the first surface portion 8 with gaps between them inward from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D).
  • the extension direction of the multiple gate structures 15 coincides with the off-direction of the SiC single crystal.
  • the gate pitch may be 1 ⁇ m or more and 3 ⁇ m or less.
  • the gate pitch may have a value that belongs to at least one of the following ranges: 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, 1.75 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.25 ⁇ m or less, 2.25 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 2.75 ⁇ m or less, and 2.75 ⁇ m or more and 3 ⁇ m or less.
  • the gate pitch is preferably 1.5 ⁇ m or more and 2.5 ⁇ m or less.
  • the multiple gate structures 15 penetrate the body region 13 and the source region 14 to reach the second semiconductor region 7.
  • the body region 13 and the source region 14 are located on both sides of the multiple gate structures 15.
  • the multiple gate structures 15 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between.
  • the multiple gate structures 15 are formed at intervals from the bottom of the high concentration region 7b toward the first surface portion 8, and face a part of the low concentration region 7a across a part of the high concentration region 7b. In other words, the bottom walls of the multiple gate structures 15 are located within the high concentration region 7b (second semiconductor region 7).
  • the multiple gate structures 15 are formed substantially perpendicular to the first surface portion 8.
  • the multiple gate structures 15 may also be formed in a tapered shape toward the bottom of the second semiconductor region 7.
  • the side walls (long sides) of the multiple gate structures 15 are each formed by the m-plane ((1-100) plane) of the SiC single crystal.
  • the side walls (long sides) of the multiple gate structures 15 may each be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 15.
  • the side walls of the multiple gate structures 15 are formed approximately perpendicular to the first main surface 3.
  • the bottom walls of the multiple gate structures 15 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the multiple gate structures 15 extend almost flat along the horizontal direction. Of course, the bottom walls of the multiple gate structures 15 may be curved in an arc shape toward the second main surface 4.
  • the inclination angle (absolute value) of the sidewall of the gate structure 15 relative to the vertical line may be 85° or more and 95° or less.
  • the inclination angle may have a value that belongs to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less.
  • the inclination angle is preferably 87° or more and 93° or less.
  • the gate structure 15 may have a width of 0.1 ⁇ m or more and 1.5 ⁇ m or less.
  • the width of the gate structure 15 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, and 1.25 ⁇ m or more and 1.5 ⁇ m or less.
  • the width of the gate structure 15 is preferably 0.25 ⁇ m or more and 1.25 ⁇ m or less.
  • the gate structure 15 has a depth that is approximately equal to the depth of the second surface portion 9.
  • the depth of the gate structure 15 may be greater than the depth of the second surface portion 9, or may be less than the depth of the second surface portion 9.
  • the depth of the gate structure 15 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the gate structure 15 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the gate structure 15 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the gate structure 15 may have an aspect ratio of 1 to 3.
  • the aspect ratio of the gate structure 15 is the ratio of the depth of the gate structure 15 to the width of the gate structure 15.
  • the aspect ratio may have a value that falls within at least one of the following ranges: 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. It is preferable that the aspect ratio is 1.5 to 2.5.
  • the gate structure 15 includes a first trench 16, a first insulating film 17, and a first buried electrode 18.
  • the first trench 16 is formed in the first surface portion 8, and defines the walls (side walls and bottom wall) of the gate structure 15.
  • the first insulating film 17 covers the wall surface of the first trench 16.
  • the first insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the first insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 17 includes a silicon oxide film made of an oxide of the chip 2.
  • the first insulating film 17 includes a first film portion and a second film portion.
  • the first film portion covers the sidewall of the first trench 16 in a film-like manner.
  • the second film portion covers the bottom wall of the first trench 16 in a film-like manner and is connected to the first film portion.
  • the second film portion has a thickness greater than the thickness of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion.
  • the first insulating film 17 may have a thickness of 10 nm or more and 150 nm or less.
  • the thickness of the first insulating film 17 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the first buried electrode 18 has an electrode surface exposed from the first trench 16.
  • the electrode surface of the first buried electrode 18 is located on the bottom wall side of the first trench 16 with respect to the height position of the first surface portion 8.
  • the electrode surface of the first buried electrode 18 is located on the first main surface 3 with respect to the depth position of the bottom of the body region 13.
  • the electrode surface of the first buried electrode 18 has a recess in an inner portion that tapers toward the bottom wall side of the first trench 16.
  • the semiconductor device 1 includes a plurality of trench-type (trench electrode-type) source structures 20 formed in the first surface portion 8 (first main surface 3) in the active region 11.
  • the source structures 20 may be referred to as "second trench structures,” “trench source structures,” etc.
  • a source potential is applied to the plurality of source structures 20.
  • the multiple source structures 20 are arranged in regions between the multiple gate structures 15 at intervals in the first direction X from the multiple gate structures 15, and face the multiple gate structures 15 in the first direction X.
  • the extension direction of the multiple source structures 20 coincides with the off-direction of the SiC single crystal.
  • the multiple source structures 20 each extend in a band shape in the second direction Y in a plan view.
  • the multiple source structures 20 may penetrate either one or both of the first connection surface portion 10A and the second connection surface portion 10B.
  • the multiple source structures 20 may be formed at intervals in the second direction Y from both the first connection surface portion 10A and the second connection surface portion 10B.
  • the source pitch is approximately equal to the gate pitch of the multiple gate structures 15.
  • the source pitch may be greater than the gate pitch or less than the gate pitch.
  • the source pitch may be 1 ⁇ m or more and 3 ⁇ m or less.
  • the source pitch may have a value that belongs to at least one of the following ranges: 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, 1.75 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.25 ⁇ m or less, 2.25 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 2.75 ⁇ m or less, and 2.75 ⁇ m or more and 3 ⁇ m or less.
  • the source pitch is preferably 1.5 ⁇ m or more and 2.5 ⁇ m or less.
  • the trench pitch may be 0.25 ⁇ m or more and 2 ⁇ m or less.
  • the trench pitch may have a value that belongs to at least one of the following ranges: 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, and 1.75 ⁇ m or more and 2 ⁇ m or less.
  • the trench pitch is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the multiple source structures 20 penetrate the body region 13 and the source region 14 to reach the second semiconductor region 7.
  • the body region 13 and the source region 14 are located on both sides of the multiple source structures 20.
  • the multiple source structures 20 face the multiple gate structures 15 with the body region 13 and the source region 14 in between.
  • the multiple source structures 20 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the multiple source structures 20 are formed at intervals from the bottom of the high concentration region 7b toward the first surface portion 8, and face a portion of the low concentration region 7a across a portion of the high concentration region 7b.
  • the bottom walls of the multiple source structures 20 are located within the high concentration region 7b (second semiconductor region 7).
  • the source structures 20 are formed substantially perpendicular to the first surface 8.
  • the source structures 20 may also be formed in a tapered shape toward the bottom of the second semiconductor region 7.
  • the side walls (long sides) of the multiple source structures 20 are each formed by the m-plane ((1-100) plane) of the SiC single crystal.
  • the side walls (long sides) of the multiple source structures 20 may each be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the source structures 20.
  • the side walls of the multiple source structures 20 are formed approximately perpendicular to the first main surface 3.
  • the bottom walls of the multiple source structures 20 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the multiple source structures 20 extend almost flat along the horizontal direction. Of course, the bottom walls of the multiple source structures 20 may be curved in an arc shape toward the second main surface 4.
  • the inclination angle (absolute value) of the sidewall of the source structure 20 relative to the vertical line may be 85° or more and 95° or less.
  • the inclination angle may have a value that belongs to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less.
  • the inclination angle is preferably 87° or more and 93° or less.
  • the source structure 20 has a width that is approximately equal to the width of the gate structure 15. Of course, the width of the source structure 20 may be greater than the width of the gate structure 15 or less than the width of the gate structure 15.
  • the width of the source structure 20 may be 0.1 ⁇ m or more and 1.5 ⁇ m or less.
  • the width of the source structure 20 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, and 1.25 ⁇ m or more and 1.5 ⁇ m or less.
  • the width of the source structure 20 is preferably 0.25 ⁇ m or more and 1.25 ⁇ m or less.
  • the source structure 20 has a depth that is approximately equal to the depth of the second surface portion 9.
  • the depth of the source structure 20 may be greater than the depth of the second surface portion 9, or may be less than the depth of the second surface portion 9. It is preferable that the depth of the source structure 20 is approximately equal to the depth of the gate structure 15.
  • the depth of the source structure 20 may be greater than the depth of the gate structure 15, or may be less than the depth of the gate structure 15.
  • the ratio of the depth of the source structure 20 to the depth of the gate structure 15 is preferably 0.8 to 1.2.
  • the depth ratio may have a value that falls within at least one of the following ranges: 0.8 to 0.85, 0.85 to 0.9, 0.9 to 0.95, 0.95 to 1, 1 to 1.05, 1.05 to 1.1, 1.1 to 1.15, and 1.15 to 1.2.
  • the depth ratio is preferably 0.95 to 1.05.
  • the depth of the source structure 20 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the source structure 20 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the source structure 20 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the source structure 20 may have an aspect ratio of 1 to 3.
  • the aspect ratio of the source structure 20 is the ratio of the depth of the source structure 20 to the width of the source structure 20.
  • the aspect ratio may have a value that falls within at least one of the following ranges: 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3.
  • the aspect ratio is preferably 1.5 to 2.5.
  • the source structure 20 includes a second trench 21, a second insulating film 22, and a second buried electrode 23.
  • the second trench 21 is formed in the first surface portion 8, and defines the walls (side walls and bottom wall) of the source structure 20.
  • the second trench 21 is connected to either or both of the first connection surface portion 10A and the second connection surface portion 10B, the side walls of the second trench 21 are connected to either or both of the first connection surface portion 10A and the second connection surface portion 10B, and the bottom wall of the second trench 21 is connected to the second surface portion 9.
  • the second insulating film 22 covers the wall surface of the second trench 21.
  • the second insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the second insulating film 22 includes the same type of insulating material as the insulating material of the first insulating film 17. In this embodiment, the second insulating film 22 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 22 includes a silicon oxide film made of an oxide of the chip 2.
  • the second insulating film 22 includes a first film portion and a second film portion.
  • the first film portion covers the sidewall of the second trench 21 in a film-like manner.
  • the second film portion covers the bottom wall of the second trench 21 in a film-like manner and is connected to the first film portion.
  • the second film portion has a thickness greater than that of the first film portion.
  • the thickness of the second film portion may be approximately equal to the thickness of the first film portion.
  • the thickness of the first film portion of the second insulating film 22 may be approximately equal to the thickness of the first film portion of the first insulating film 17.
  • the thickness of the second film portion of the second insulating film 22 may be approximately equal to the thickness of the second film portion of the first insulating film 17.
  • the second insulating film 22 may have a thickness of 10 nm or more and 150 nm or less.
  • the thickness of the second insulating film 22 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the second buried electrode 23 is buried in the second trench 21 with the second insulating film 22 in between.
  • the second buried electrode 23 may contain either one or both of p-type conductive polysilicon and n-type conductive polysilicon. It is preferable that the second buried electrode 23 contains the same type of conductive material as the conductive material of the first buried electrode 18.
  • the second buried electrode 23 faces the second semiconductor region 7 (high concentration region 7b), the body region 13, and the source region 14 with the second insulating film 22 in between.
  • the second buried electrode 23 has an electrode surface exposed from the second trench 21.
  • the electrode surface of the second buried electrode 23 is located on the bottom wall side of the second trench 21 with respect to the height position of the first surface portion 8.
  • the electrode surface of the second buried electrode 23 is located on the second main surface 4 with respect to the depth position of the bottom of the body region 13.
  • the electrode surface of the second buried electrode 23 has a recess tapered toward the bottom wall side of the second trench 21 at the inner portion.
  • the semiconductor device 1 includes a plurality of p-type column regions 25 (impurity regions) formed at intervals in the horizontal direction in the second semiconductor region 7.
  • the plurality of column regions 25 include a plurality of gate column regions 25g (first impurity regions) and a plurality of source column regions 25s (second impurity regions).
  • the gate column regions 25g may be referred to as the "first impurity region", the "first column region”, etc.
  • the source column regions 25s may be referred to as the "second impurity region", the "second column region”, etc.
  • the multiple gate column regions 25g are formed by introducing a trivalent element (p-type impurity) into the second semiconductor region 7, and replace the conductivity type of the second semiconductor region 7 from n-type to p-type.
  • the gate column regions 25g have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7.
  • the p-type impurity concentration of the gate column regions 25g may be higher than the p-type impurity concentration of the body region 13.
  • the p-type impurity concentration of the gate column regions 25g may be lower than the p-type impurity concentration of the body region 13.
  • the multiple gate column regions 25g are formed in the chip 2 (second semiconductor region 7) in regions directly below the multiple gate structures 15, with gaps between each other in the first direction X. Specifically, the multiple gate column regions 25g are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the multiple gate structures 15, and overlap with the multiple gate structures 15 in a one-to-one correspondence in the thickness direction.
  • the extension direction of the multiple gate column regions 25g coincides with the off-direction of the SiC single crystal.
  • the multiple gate column regions 25g may also extend in the first direction X. In this case, the multiple gate column regions 25g intersect (specifically, perpendicular to) the off-direction.
  • the multiple gate column regions 25g are formed at intervals from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D) toward the inside of the first surface portion 8. Both ends of the multiple gate column regions 25g may be located on the inside side of the multiple gate structures 15 relative to both ends of the multiple gate structures 15. Both ends of the multiple gate column regions 25g may be located on the periphery side of the first surface portion 8 relative to both ends of the multiple gate structures 15.
  • the multiple gate column regions 25g are each formed in a columnar shape extending in the thickness direction of the chip 2 in a cross-sectional view.
  • the multiple gate column regions 25g may be made of p-type channeling regions extending along the axial channel of the chip 2 (second semiconductor region 7) in a cross-sectional view.
  • the multiple gate column regions 25g are formed by introducing a trivalent element (p-type impurity) into the second semiconductor region 7 through the bottom walls of the multiple gate structures 15 (first trenches 16).
  • the multiple gate column regions 25g are made of impurity regions introduced parallel or nearly parallel to a region (axial channel) surrounded by atomic rows along a low-index crystal axis (c-axis in this embodiment) in the chip 2 (second semiconductor region 7), and may be inclined obliquely with respect to the first main surface 3.
  • the gate column pitch is approximately equal to the gate pitch of the multiple gate structures 15.
  • the gate column pitch may be greater than the gate pitch or less than the gate pitch.
  • the gate column pitch may be 1 ⁇ m or more and 3 ⁇ m or less.
  • the gate column pitch may have a value that belongs to at least one of the following ranges: 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, 1.75 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.25 ⁇ m or less, 2.25 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 2.75 ⁇ m or less, and 2.75 ⁇ m or more and 3 ⁇ m or less.
  • the gate column pitch is preferably 1.5 ⁇ m or more and 2.5 ⁇ m or less.
  • the ratio of the gate column pitch to the gate pitch may be 0.8 or more and 1.2 or less.
  • the gate pitch ratio may have a value that belongs to any one of the following ranges: 0.8 or more and 0.85 or less, 0.85 or more and 0.9 or less, 0.9 or more and 0.95 or less, 0.95 or more and 1 or less, 1 or more and 1.05 or less, 1.05 or more and 1.1 or less, 1.1 or more and 1.15 or less, and 1.15 or more and 1.2 or less.
  • the gate pitch ratio is preferably 0.9 or more and 1.1 or less.
  • the configuration of one gate column region 25g is described below.
  • the gate column region 25g has an upper end located on the bottom wall side of the gate structure 15, and a lower end (bottom) located on the bottom side of the second semiconductor region 7.
  • the upper end of the gate column region 25g is located in the region on the bottom wall side of the gate structure 15 with respect to the intermediate portion between the bottom of the second semiconductor region 7 and the bottom wall of the gate structure 15.
  • the upper end of the gate column region 25g is formed at a distance from the bottom side of the second semiconductor region 7 relative to the depth position of the second surface portion 9.
  • the upper end of the gate column region 25g is formed at a distance from the bottom wall of the gate structure 15 to the bottom side of the second semiconductor region 7, and faces the multiple gate structures 15 with a portion of the second semiconductor region 7 in between.
  • the upper end of the gate column region 25g faces the gate structure 15 across a portion of the high concentration region 7b and is electrically connected to the high concentration region 7b.
  • the upper end of the gate column region 25g may also be connected to the bottom wall of the gate structure 15.
  • the upper end of the gate column region 25g may be formed with an upper end distance of 0 ⁇ m or more and 1 ⁇ m or less from the bottom wall of the gate structure 15.
  • the upper end distance of the gate column region 25g may have a value that belongs to at least one of the ranges of 0 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, and 0.75 ⁇ m or more and 1 ⁇ m or less.
  • the lower end of the gate column region 25g is located in a region on the bottom side of the second semiconductor region 7 with respect to the intermediate portion between the bottom of the second semiconductor region 7 and the bottom wall of the gate structure 15.
  • the lower end of the gate column region 25g is located within the low concentration region 7a across the bottom of the high concentration region 7b and is electrically connected to the low concentration region 7a.
  • the gate column region 25g has a portion (upper end) located in the high concentration region 7b and a portion (lower end) located in the low concentration region 7a. It is preferable that the cross-sectional area of the portion of the gate column region 25g located in the high concentration region 7b is larger than the cross-sectional area of the portion of the gate column region 25g located in the low concentration region 7a. Of course, the cross-sectional area of the portion of the gate column region 25g located in the high concentration region 7b may be smaller than the cross-sectional area of the portion of the gate column region 25g located in the low concentration region 7a.
  • the lower end of the gate column region 25g is formed at a distance from the bottom of the low concentration region 7a (first semiconductor region 6) to the bottom side of the high concentration region 7b, and faces the first semiconductor region 6 across a portion of the low concentration region 7a.
  • the lower end of the gate column region 25g may be formed with a lower end distance of 0 ⁇ m or more and 2 ⁇ m or less from the bottom of the second semiconductor region 7.
  • the lower end distance of the gate column region 25g may have a value that belongs to at least one of the following ranges: 0 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the lower end distance of the gate column region 25g may be greater than the upper end distance of the gate column region 25g or may be less than
  • the gate column region 25g has a width approximately equal to the width of the gate structure 15.
  • the width of the gate column region 25g may be greater than the width of the gate structure 15 or less than the width of the gate structure 15.
  • the width of the gate column region 25g may have a width approximately equal to the width of the source structure 20.
  • the width of the gate column region 25g may be greater than the width of the source structure 20 or less than the width of the source structure 20.
  • the width of the gate column region 25g may be 0.1 ⁇ m or more and 1.5 ⁇ m or less.
  • the width of the gate column region 25g may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, and 1.25 ⁇ m or more and 1.5 ⁇ m or less.
  • the width of the gate column region 25g is preferably 0.25 ⁇ m or more and 1.25 ⁇ m or less.
  • the ratio of the width of the gate column region 25g to the width of the gate structure 15 may be 0.8 or more and 1.2 or less.
  • the gate width ratio may have a value that belongs to any one of the following ranges: 0.8 or more and 0.85 or less, 0.85 or more and 0.9 or less, 0.9 or more and 0.95 or less, 0.95 or more and 1 or less, 1 or more and 1.05 or less, 1.05 or more and 1.1 or less, 1.1 or more and 1.15 or less, and 1.15 or more and 1.2 or less.
  • the gate width ratio is preferably 0.9 or more and 1.1 or less.
  • the gate column region 25g preferably has a depth greater than the depth of the second surface portion 9. Of course, the depth of the gate column region 25g may be less than the depth of the second surface portion 9. The depth of the gate column region 25g preferably has a depth greater than the depth of the gate structure 15. Of course, the depth of the gate column region 25g may be less than the depth of the gate structure 15.
  • the depth of the gate column region 25g is preferably greater than the depth of the source structure 20. Of course, the depth of the gate column region 25g may be less than the depth of the source structure 20. The depth of the gate column region 25g is preferably greater than the depth of the high concentration region 7b. Of course, the depth of the gate column region 25g may be less than the depth of the high concentration region 7b.
  • the ratio (gate depth ratio) of the depth of the gate column region 25g to the depth of the gate structure 15 (depth of the source structure 20) may be 1 or more and 5 or less.
  • the gate depth ratio may have a value that belongs to at least one of the following ranges: 1 or more and 1.5 or less, 1.5 or more and 2 or less, 2 or more and 2.5 or less, 2.5 or more and 3 or less, 3 or more and 3.5 or less, 3.5 or more and 4 or less, 4 or more and 4.5 or less, and 4.5 or more and 5 or less.
  • the depth of the gate column region 25g is preferably 1 ⁇ m or more and 5 ⁇ m or less.
  • the depth of the gate column region 25g may have a value that falls within at least one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the gate column region 25g may have an aspect ratio of 1 to 10.
  • the aspect ratio of the gate column region 25g is the ratio of the depth of the gate column region 25g to the width of the gate column region 25g.
  • the aspect ratio may have a value that falls within at least one of the following ranges: 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.
  • the source column region 25s is formed by introducing a trivalent element (p-type impurity) into the second semiconductor region 7, and replaces the conductivity type of the second semiconductor region 7 from n-type to p-type.
  • the source column region 25s has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7.
  • the p-type impurity concentration of the source column region 25s may be higher than the p-type impurity concentration of the body region 13.
  • the p-type impurity concentration of the source column region 25s may be lower than the p-type impurity concentration of the body region 13.
  • the p-type impurity concentration of the source column region 25s is preferably approximately equal to the p-type impurity concentration of the gate column region 25g.
  • the p-type impurity concentration of the source column region 25s may be higher than the p-type impurity concentration of the gate column region 25g, or may be lower than the p-type impurity concentration of the gate column region 25g.
  • the source column regions 25s are formed in the chip 2 (second semiconductor region 7) in regions directly below the source structures 20 at intervals in the first direction X. Specifically, the source column regions 25s are formed in the regions directly below the source structures 20 at intervals in the first direction X from the gate column regions 25g.
  • the multiple source column regions 25s are each formed in a thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the multiple source structures 20, and overlap with the multiple source structures 20 in a one-to-one correspondence in the thickness direction.
  • the extension direction of the multiple source column regions 25s coincides with the off-direction of the SiC single crystal.
  • the multiple source column regions 25s may also extend in the first direction X.
  • the multiple source column regions 25s intersect (specifically, are perpendicular to) the off-direction.
  • the ends of the source column regions 25s may be located on the inner side of the source structures 20 relative to the ends of the source structures 20.
  • the ends of the source column regions 25s may be located on the peripheral side of the first surface portion 8 relative to the ends of the source structures 20.
  • the multiple source column regions 25s may be exposed from either or both of the first connection surface portion 10A and the second connection surface portion 10B. Of course, the multiple source column regions 25s may be formed at intervals in the second direction Y from both the first connection surface portion 10A and the second connection surface portion 10B.
  • the multiple source column regions 25s face the multiple gate column regions 25g in the first direction X, sandwiching a portion of the second semiconductor region 7 therebetween.
  • the multiple source column regions 25s face the multiple gate column regions 25g, sandwiching a portion of the low concentration region 7a and a portion of the high concentration region 7b of the second semiconductor region 7 therebetween.
  • the multiple source column regions 25s are each formed in a columnar shape extending in the thickness direction of the chip 2 in a cross-sectional view.
  • the multiple source column regions 25s may be made of p-type channeling regions extending along the axial channel of the chip 2 (second semiconductor region 7) in a cross-sectional view.
  • the multiple source column regions 25s are formed by introducing a trivalent element (p-type impurity) into the second semiconductor region 7 through the bottom walls of the multiple source structures 20 (second trenches 21).
  • the multiple source column regions 25s are made of impurity regions introduced parallel or nearly parallel to a region (axial channel) surrounded by atomic rows along a low-index crystal axis (c-axis in this embodiment) in the chip 2 (second semiconductor region 7), and may be inclined obliquely with respect to the first main surface 3.
  • the source column pitch is approximately equal to the source pitch of the multiple source structures 20.
  • the source column pitch may be greater than the source pitch or less than the source pitch.
  • the source column pitch may be 1 ⁇ m or more and 3 ⁇ m or less.
  • the source column pitch may have a value that belongs to at least one of the following ranges: 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, 1.75 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.25 ⁇ m or less, 2.25 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 2.75 ⁇ m or less, and 2.75 ⁇ m or more and 3 ⁇ m or less.
  • the source column pitch is preferably 1.5 ⁇ m or more and 2.5 ⁇ m or less.
  • the ratio of source column pitch to source pitch may be 0.8 or more and 1.2 or less.
  • the source pitch ratio may have a value that belongs to any one of the following ranges: 0.8 or more and 0.85 or less, 0.85 or more and 0.9 or less, 0.9 or more and 0.95 or less, 0.95 or more and 1 or less, 1 or more and 1.05 or less, 1.05 or more and 1.1 or less, 1.1 or more and 1.15 or less, and 1.15 or more and 1.2 or less.
  • the source pitch ratio is preferably 0.9 or more and 1.1 or less.
  • the column pitch is approximately equal to the trench pitch between the gate structure 15 and the source structure 20.
  • the column pitch may be greater than the trench pitch or less than the trench pitch.
  • the column pitch may be 0.25 ⁇ m or more and 2 ⁇ m or less.
  • the column pitch may have a value that falls within at least one of the following ranges: 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, and 1.75 ⁇ m or more and 2 ⁇ m or less.
  • the column pitch is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the ratio of column pitch to trench pitch may be 0.8 or more and 1.2 or less.
  • the pitch ratio may have a value that belongs to any one of the following ranges: 0.8 or more and 0.85 or less, 0.85 or more and 0.9 or less, 0.9 or more and 0.95 or less, 0.95 or more and 1 or less, 1 or more and 1.05 or less, 1.05 or more and 1.1 or less, 1.1 or more and 1.15 or less, and 1.15 or more and 1.2 or less.
  • the pitch ratio is preferably 0.9 or more and 1.1 or less.
  • the configuration of one source column region 25s is described below.
  • the source column region 25s has an upper end located on the bottom wall side of the source structure 20, and a lower end (bottom) located on the bottom side of the second semiconductor region 7.
  • the upper end of the source column region 25s is located in the region on the bottom wall side of the source structure 20 with respect to the intermediate portion between the bottom of the second semiconductor region 7 and the bottom wall of the source structure 20.
  • the upper end of the source column region 25s is formed at a distance from the bottom side of the second semiconductor region 7 relative to the depth position of the second surface portion 9.
  • the upper end of the source column region 25s is formed at a distance from the bottom wall of the source structure 20 to the bottom side of the second semiconductor region 7, and faces multiple source structures 20 with a portion of the second semiconductor region 7 in between.
  • the upper end of the source column region 25s faces the source structure 20 across a portion of the high concentration region 7b and is electrically connected to the high concentration region 7b.
  • the upper end of the source column region 25s may also be connected to the bottom wall of the source structure 20.
  • the upper end of the source column region 25s is preferably located at a depth position that is approximately equal to the depth position of the upper end of the gate column region 25g.
  • the depth position of the upper end of the source column region 25s may be located closer to the bottom wall of the source structure 20 than the depth position of the upper end of the gate column region 25g, or it may be located closer to the bottom of the second semiconductor region 7 than the depth position of the upper end of the gate column region 25g.
  • the upper end of the source column region 25s may be formed with an upper end distance of 0 ⁇ m or more and 1 ⁇ m or less from the bottom wall of the source structure 20.
  • the upper end distance of the source column region 25s may have a value that belongs to at least one of the ranges of 0 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, and 0.75 ⁇ m or more and 1 ⁇ m or less.
  • the lower end of the source column region 25s is located in a region on the bottom side of the second semiconductor region 7 with respect to the intermediate portion between the bottom of the second semiconductor region 7 and the bottom wall of the source structure 20.
  • the lower end of the source column region 25s is located within the low concentration region 7a across the bottom of the high concentration region 7b and is electrically connected to the low concentration region 7a.
  • the source column region 25s has a portion (upper end) located in the high concentration region 7b, and a portion (lower end) located in the low concentration region 7a.
  • the cross-sectional area of the portion of the source column region 25s located in the high concentration region 7b is preferably larger than the cross-sectional area of the portion of the source column region 25s located in the low concentration region 7a.
  • the cross-sectional area of the portion of the source column region 25s located in the high concentration region 7b may be smaller than the cross-sectional area of the portion of the source column region 25s located in the low concentration region 7a.
  • the lower end of the source column region 25s is formed at a distance from the bottom of the low concentration region 7a (first semiconductor region 6) toward the bottom of the high concentration region 7b, and faces the first semiconductor region 6 across a portion of the low concentration region 7a.
  • the lower end of the source column region 25s is preferably located at a depth position that is approximately equal to the depth position of the lower end of the gate column region 25g.
  • the depth position of the lower end of the source column region 25s may be located closer to the bottom wall of the source structure 20 than the depth position of the lower end of the gate column region 25g, or it may be located closer to the bottom of the second semiconductor region 7 than the depth position of the lower end of the gate column region 25g.
  • the lower end of the source column region 25s may be formed with a lower end distance of 0 ⁇ m or more and 5 ⁇ m or less from the bottom of the second semiconductor region 7.
  • the lower end distance of the source column region 25s may have a value belonging to at least one of the ranges of 0 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the lower end distance of the source column region 25s may be greater than the upper end distance of the source column region 25s or may be less than the upper
  • the source column region 25s has a width approximately equal to the width of the source structure 20.
  • the width of the source column region 25s may be greater than the width of the source structure 20 or less than the width of the source structure 20.
  • the width of the source column region 25s may have a width approximately equal to the width of the gate structure 15.
  • the width of the source column region 25s may be greater than the width of the gate structure 15 or less than the width of the gate structure 15.
  • the width of the source column region 25s is preferably approximately equal to the width of the gate column region 25g.
  • the width of the source column region 25s may be greater than the width of the gate column region 25g, or may be less than the width of the gate column region 25g.
  • the width of the source column region 25s may be 0.1 ⁇ m or more and 1.5 ⁇ m or less.
  • the width of the source column region 25s may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, and 1.25 ⁇ m or more and 1.5 ⁇ m or less.
  • the width of the source column region 25s is preferably 0.25 ⁇ m or more and 1.25 ⁇ m or less.
  • the ratio of the width of the source column region 25s to the width of the source structure 20 may be 0.8 or more and 1.2 or less.
  • the source width ratio may have a value belonging to any one of the following ranges: 0.8 or more and 0.85 or less, 0.85 or more and 0.9 or less, 0.9 or more and 0.95 or less, 0.95 or more and 1 or less, 1 or more and 1.05 or less, 1.05 or more and 1.1 or less, 1.1 or more and 1.15 or less, and 1.15 or more and 1.2 or less.
  • the source width ratio is preferably 0.9 or more and 1.1 or less.
  • the source column region 25s preferably has a depth greater than the depth of the second surface portion 9. Of course, the depth of the source column region 25s may be less than the depth of the second surface portion 9.
  • the source column region 25s preferably has a depth greater than the depth of the source structure 20. Of course, the depth of the source column region 25s may be less than the depth of the source structure 20.
  • the depth of the source column region 25s is preferably greater than the depth of the gate structure 15. Of course, the depth of the source column region 25s may be less than the depth of the gate structure 15. The depth of the source column region 25s is preferably greater than the depth of the high concentration region 7b. Of course, the depth of the source column region 25s may be less than the depth of the high concentration region 7b.
  • the depth of the source column region 25s is preferably approximately equal to the depth of the gate column region 25g.
  • the depth of the source column region 25s may be greater than the depth of the gate column region 25g, or may be less than the depth of the gate column region 25g.
  • the ratio of the depth of the source column region 25s to the depth of the source structure 20 may be 1 or more and 5 or less.
  • the source depth ratio may have a value that belongs to at least one of the following ranges: 1 or more and 1.5 or less, 1.5 or more and 2 or less, 2 or more and 2.5 or less, 2.5 or more and 3 or less, 3 or more and 3.5 or less, 3.5 or more and 4 or less, 4 or more and 4.5 or less, and 4.5 or more and 5 or less.
  • the depth of the source column region 25s is preferably 1 ⁇ m or more and 5 ⁇ m or less.
  • the depth of the source column region 25s may have a value that belongs to at least one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the source column region 25s may have an aspect ratio of 1 to 10.
  • the aspect ratio of the source column region 25s is the ratio of the depth of the source column region 25s to the width of the source column region 25s.
  • the aspect ratio may have a value that falls within at least one of the following ranges: 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.
  • Figure 10 is a graph showing an example of the concentration gradient of the column region 25.
  • Figure 10 shows the concentration gradient when the column region 25 is formed by channeling injection.
  • the vertical axis shows the p-type impurity concentration of the column region 25, and the horizontal axis shows the depth of the column region 25 with the bottom wall of the gate structure 15 (bottom wall of the source structure 20) as the reference (zero point).
  • the values of the impurity concentration, thickness, etc. shown below are examples to explain the basic configuration of the column region 25 based on the concentration gradient, and are not intended to uniquely limit the configuration of the column region 25.
  • the impurity concentration, thickness, etc. are adjusted to various values depending on the injection conditions of the trivalent element (dose amount, injection temperature, injection energy, etc.).
  • FIG. 10 shows a first concentration gradient G1 and a second concentration gradient G2.
  • the first concentration gradient G1 shows the concentration gradient in the column region 25 when a trivalent element is introduced into the chip 2 (second semiconductor region 7) with an energy of 500 KeV or more and 800 KeV or less.
  • the second concentration gradient G2 shows the concentration gradient in the column region 25 when a trivalent element is introduced into the chip 2 (second semiconductor region 7) with an energy of 900 KeV or more and 1200 KeV or less.
  • a region having a p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more is defined as the column region 25.
  • the trivalent element is aluminum, and the dose amount of the trivalent element is 1 ⁇ 10 13 cm ⁇ 2 .
  • the thickness of the second semiconductor region 7 is about 5 ⁇ m, and the depth of the gate structure 15 (the depth of the source structure 20) is about 1 ⁇ m.
  • the column region 25 has a thickness of 2.5 ⁇ m or more and 2.8 ⁇ m or less, and has an upper end spaced from the bottom wall of the gate structure 15 (the bottom wall of the source structure 20) toward the bottom of the second semiconductor region 7, and a lower end spaced from the bottom of the second semiconductor region 7 toward the upper end.
  • the upper end of the column region 25 is formed with a distance of 0.2 ⁇ m or more and 0.3 ⁇ m or less from the bottom wall of the gate structure 15 (the bottom wall of the source structure 20).
  • the lower end of the column region 25 is formed with a distance of 1 ⁇ m or more and 1.2 ⁇ m or less from the bottom of the second semiconductor region 7.
  • the column region 25 has a concentration gradient from the upper end side to the lower end side, including a gradually increasing portion 26, a peak portion 27, a gradual portion 28, and a gradually decreasing portion 29.
  • the gradually increasing portion 26 is the portion that forms the upper end of the column region 25, and the p-type impurity concentration gradually increases from the upper end side to the lower end side at a relatively steep rate of increase up to the peak portion 27.
  • the gradually increasing portion 26 is located within the high concentration region 7b and is electrically connected to the high concentration region 7b.
  • Peak portion 27 is a portion having a peak value P (maximum value) of the p-type impurity concentration. Peak portion 27 is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the p-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend). Peak portion 27 is electrically connected to high concentration region 7b.
  • the gradual portion 28 is formed in a region closer to the lower end than the peak portion 27, and is a portion where the impurity concentration gradually decreases at a relatively gradual rate of decrease.
  • the gradual portion 28 is a portion that maintains a constant p-type impurity concentration in a certain depth range, and forms the main body of the gate column region 25g.
  • the p-type impurity concentration of the gradual portion 28 gradually decreases in a concentration range that is less than the p-type impurity concentration of the peak portion 27.
  • the slow portion 28 is defined by a portion having a concentration drop rate of 50% or less in a thickness range of at least 0.5 ⁇ m.
  • the slow portion 28 has a thickness of 1 ⁇ m or more and 1.3 ⁇ m or less, and has a concentration drop rate of 50% or less in that thickness range.
  • the slow portion 28 is located within the high concentration region 7b and is electrically connected to the high concentration region 7b.
  • the slow portion 28 may have a portion located within the low concentration region 7a and be electrically connected to the low concentration region 7a.
  • the sluggish portion 28 occupies a thickness range of 1/4 or more of the column region 25. Specifically, the proportion of the sluggish portion 28 in the column region 25 is 1/3 or more. The proportion of the sluggish portion 28 in the column region 25 is typically 1/2 or less (less than 1/2). Of course, the proportion of the sluggish portion 28 in the column region 25 may be 1/2 or more.
  • the gradually decreasing portion 29 is a portion that forms the lower end of the column region 25.
  • the gradually decreasing portion 29 has a concentration decrease rate that is greater than the concentration decrease rate of the gradual portion 28, and is a portion where the p-type impurity concentration gradually decreases from the gradual portion 28 toward the lower end.
  • the concentration decrease rate per unit thickness of the gradually decreasing portion 29 is greater than the concentration decrease rate per unit thickness of the gradual portion 28.
  • the gradually decreasing portion 29 is located within the low concentration region 7a and is electrically connected to the low concentration region 7a.
  • the column region 25 has a thickness of 3.1 ⁇ m or more and 3.2 ⁇ m or less, and has an upper end spaced from the bottom wall of the gate structure 15 (the bottom wall of the source structure 20) toward the bottom of the second semiconductor region 7, and a lower end spaced from the bottom of the second semiconductor region 7 toward the upper end.
  • the upper end of the column region 25 is formed with a distance of 0.4 ⁇ m or more and 0.5 ⁇ m or less from the bottom wall of the gate structure 15 (the bottom wall of the source structure 20).
  • the lower end of the column region 25 is formed with a distance of 0.4 ⁇ m or more and 0.6 ⁇ m or less from the bottom of the second semiconductor region 7.
  • the column region 25 has a concentration gradient that includes a gradually increasing portion 26, a peak portion 27, a gradual portion 28, and a gradually decreasing portion 29 from the upper end side to the lower end side, similar to the first concentration gradient G1.
  • the gradually increasing portion 26, the peak portion 27, the gradual portion 28, and the gradual decreasing portion 29 are all shifted toward the bottom side of the second semiconductor region 7 compared to the first concentration gradient G1.
  • the peak value P of the peak portion 27 is lower than in the first concentration gradient G1.
  • the thickness of the gradual portion 28 is 1.4 ⁇ m or more and 1.5 ⁇ m or less, which is greater than in the first concentration gradient G1.
  • the thickness (depth) of the column region 25 increases with increasing injection energy.
  • the depth position of the upper end of the gate column region 25g relative to the bottom wall of the gate structure 15 increases with increasing injection energy.
  • the thicknesses of the gradually increasing portion 26, the peak portion 27, the gradual portion 28, and the gradually decreasing portion 29 increase with increasing injection energy.
  • the peak value P of the peak portion 27 decreases with increasing injection energy. This is because the trivalent element is introduced into a relatively deep region with increasing injection energy, increasing the p-type impurity concentration in the deep region.
  • FIG. 11 is a graph showing another example of the concentration gradient in the column region 25.
  • FIG. 11 shows the concentration gradient when the column region 25 is formed by the random injection method.
  • the random injection method is a method of introducing a trivalent element into the chip 2 (second semiconductor region 7) in a random direction.
  • the random direction is a direction (for example, the vertical direction Z) that intersects with the axial channel of the chip 2 (second semiconductor region 7).
  • the vertical axis indicates the p-type impurity concentration in the column region 25, and the horizontal axis indicates the depth of the column region 25 with the bottom wall of the gate structure 15 (the bottom wall of the source structure 20) as the reference (zero point).
  • FIG. 11 shows the third concentration gradient G3 and the fourth concentration gradient G4.
  • the third concentration gradient G3 shows the concentration gradient in the column region 25 when a trivalent element is introduced into the chip 2 (second semiconductor region 7) with an energy of 500 KeV or more and 800 KeV or less.
  • the fourth concentration gradient G4 shows the concentration gradient in the column region 25 when a trivalent element is introduced into the chip 2 (second semiconductor region 7) with an energy of 900 KeV or more and 1200 KeV or less.
  • a region having a p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more is defined and illustrated as a column region 25.
  • the trivalent element is aluminum, and the dose amount of the trivalent element is 1 ⁇ 10 13 cm ⁇ 2 .
  • the thickness of the second semiconductor region 7 is about 5 ⁇ m, and the depth of the gate structure 15 (depth of the source structure 20) is about 1 ⁇ m.
  • the column region 25 has a gradually increasing portion 26, a peak portion 27 (peak value P), and a gradually decreasing portion 29 in a range of 0.5 ⁇ m, but does not have a gradual portion 28 having a thickness of 0.5 ⁇ m or more. Also, in the case of the random injection method, the formation location of the column region 25 shifted toward the bottom side of the second semiconductor region 7 as the injection energy increased, but the thickness of the column region 25 was less than 2 ⁇ m in all cases. In other words, the thickness of the column region 25 did not change significantly even when the injection energy was increased.
  • a process of introducing a trivalent element into an epitaxial layer having a relatively small thickness (for example, less than 1 ⁇ m) by random injection is repeated multiple times.
  • the number of epitaxial growth steps and the number of random injection steps increase, making the manufacturing process more complicated.
  • the multi-stage random injection method a process is carried out in which a trivalent element is introduced in multiple stages at different depth positions using multiple injection energies.
  • the trivalent element can be introduced to the desired depth position, but the depth position at which the trivalent element can be introduced is shallow. Therefore, the number of introduction stages (number of steps) using the random injection method must be increased, complicating the manufacturing process.
  • a column region 25 having a relatively thick gradual portion 28 is formed. Therefore, in the case of the channeling injection method, a column region 25 having charge balance is formed with fewer steps than when the random injection method is adopted.
  • the semiconductor device 1 preferably includes a column region 25 (gate column region 25g and source column region 25s) consisting of a channeling region.
  • the semiconductor device 1 may include a column region 25 (gate column region 25g and source column region 25s) consisting of a plurality of channeling regions (impurity regions) introduced in multiple stages in the thickness direction of the second semiconductor region 7.
  • the semiconductor device 1 may have a column region 25 (gate column region 25g and source column region 25s) that includes multiple random regions (impurity regions) that are introduced in multiple stages in the thickness direction of the second semiconductor region 7 by a random injection method.
  • the semiconductor device 1 includes a plurality of n-type intermediate drift regions 30 formed in the second semiconductor region 7.
  • Each of the plurality of intermediate drift regions 30 is composed of a region defined by a plurality of column regions 25 of the second semiconductor region 7.
  • the plurality of intermediate drift regions 30 are each defined into regions between a plurality of gate column regions 25g and a plurality of source column regions 25s.
  • the multiple intermediate drift regions 30 are partitioned at intervals in the first direction X (m-axis direction) within the second semiconductor region 7, and each extends in a strip shape in the second direction Y (a-axis direction). Each of the multiple intermediate drift regions 30 is formed by a part of the second semiconductor layer. In this embodiment, the multiple intermediate drift regions 30 are formed by a part of the low concentration region 7a and a part of the high concentration region 7b.
  • the intermediate drift regions 30 form a plurality of first pn junctions with the gate column regions 25g, and form a plurality of second pn junctions with the source column regions 25s.
  • the intermediate drift regions 30 form a charge balance together with the gate column regions 25g and the source column regions 25s.
  • Charge balance refers to a state in which, for a gate column region 25g and a source column region 25s adjacent to each other across one intermediate drift region 30, the depletion layer extending from the first pn junction and the depletion layer extending from the second pn junction are connected within the intermediate drift region 30 when a reverse bias voltage is applied.
  • the semiconductor device 1 includes a plurality of contact regions 35 formed in the chip 2 (second semiconductor region 7).
  • the plurality of contact regions 35 includes a plurality of gate contact regions 35g and a plurality of source contact regions 35s.
  • the multiple gate contact regions 35g are formed in regions along the multiple gate structures 15 within the chip 2 (second semiconductor region 7).
  • the gate contact regions 35g have a p-type impurity concentration higher than the p-type impurity concentration of the body region 13. It is preferable that the p-type impurity concentration of the gate contact regions 35g is higher than the p-type impurity concentration of the column region 25 (gate column region 25g).
  • the multiple gate contact regions 35g are formed in regions along the multiple gate structures 15 at intervals from the multiple source structures 20.
  • the multiple gate contact regions 35g are formed in a one-to-many correspondence with the multiple gate structures 15.
  • the multiple gate contact regions 35g are respectively interposed in regions between the bottom walls of the multiple gate structures 15 and the upper ends of the multiple gate column regions 25g, and are formed at intervals in the second direction Y.
  • the multiple gate contact regions 35g along one gate structure 15 face the multiple gate contact regions 35g along the other gate structure 15 in the first direction X in a planar view.
  • the multiple gate contact regions 35g are generally arranged in a matrix with gaps in the first direction X and the second direction Y in a planar view.
  • the multiple gate contact regions 35g extend in a band shape along the multiple gate structures 15 in a plan view.
  • the lengths of the multiple gate contact regions 35g in the second direction Y may be equal to each other or may be different from each other.
  • the lengths of the multiple gate contact regions 35g in the second direction Y are adjusted according to the channel area to be formed.
  • the channel area is the total area of the portions of the source region 14 exposed from the region between the multiple gate structures 15 and the multiple source structures 20. In other words, the channel area increases or decreases depending on the percentage of the total planar area of the multiple gate contact regions 35g. It is preferable that the total planar area of the multiple gate contact regions 35g is less than the channel area.
  • the total planar area of the multiple gate contact regions 35g is less than the planar area of the source region 14.
  • the length of the multiple gate contact regions 35g may be greater than the width of the gate structure 15, or may be smaller than the width of the gate structure 15.
  • the length of the multiple gate contact regions 35g may be greater than the gate pitch of the multiple gate structures 15, or may be smaller than the gate pitch.
  • the spacing between the multiple gate contact regions 35g in the second direction Y is preferably greater than the width of the gate structure 15.
  • the spacing between the multiple gate contact regions 35g in the second direction Y may be smaller than the width of the gate structure 15.
  • the spacing between the multiple gate contact regions 35g may be greater than the gate pitch or smaller than the gate pitch.
  • the configuration of one gate contact region 35g is described below.
  • the gate contact region 35g is connected to the bottom wall of the corresponding gate structure 15 and the upper end of the corresponding gate column region 25g.
  • the gate contact region 35g protrudes from the region directly below the gate structure 15 to both sides of the gate structure 15 and has an extension that extends in the vertical direction Z along the sidewall of the gate structure 15.
  • the thickness in the horizontal direction (first direction X) of the portion (extension) of the gate contact region 35g that runs along the side wall of the gate structure 15 is less than the thickness in the vertical direction Z of the portion of the gate contact region 35g that runs along the bottom wall of the gate structure 15.
  • the extension of the gate contact region 35g is electrically connected to the body region 13 at the surface portion of the first surface portion 8, and electrically connects the corresponding gate column region 25g to the body region 13. This prevents the gate column region 25g from becoming electrically floating, improving the electrical response characteristics of the gate column region 25g.
  • the gate contact region 35g has an upper end exposed from the first surface portion 8. In this embodiment, the upper end of the gate contact region 35g is exposed from the sidewall of the first trench 16 at the opening end of the first trench 16. The upper end of the gate contact region 35g may extend horizontally in the surface portion of the body region 13.
  • the multiple source contact regions 35s are formed in regions along the multiple source structures 20 within the chip 2 (second semiconductor region 7).
  • the source contact regions 35s have a p-type impurity concentration higher than the p-type impurity concentration of the body region 13. It is preferable that the p-type impurity concentration of the source contact regions 35s is higher than the p-type impurity concentration of the column region 25 (source column region 25s).
  • the p-type impurity concentration of the source contact region 35s is preferably approximately equal to the p-type impurity concentration of the gate contact region 35g.
  • the p-type impurity concentration of the source contact region 35s may be higher than the p-type impurity concentration of the gate contact region 35g, or may be lower than the p-type impurity concentration of the gate contact region 35g.
  • the multiple source contact regions 35s are formed in regions along the multiple source structures 20, spaced apart from the multiple gate structures 15.
  • the multiple source contact regions 35s have a planar layout that is different from the planar layout of the multiple gate contact regions 35g.
  • the multiple source contact regions 35s are formed in a one-to-one correspondence with the multiple source structures 20.
  • the multiple source contact regions 35s are respectively interposed in the regions between the bottom walls of the corresponding source structures 20 and the upper ends of the corresponding source column regions 25s, and extend in a strip-like shape in the second direction Y.
  • the multiple source contact regions 35s are formed in a stripe shape extending along the multiple source structures 20 in a plan view.
  • the multiple source contact regions 35s have a length greater than the length of the multiple gate contact regions 35g in the second direction Y, and cross the multiple gate structures 15 in the second direction Y. In the second direction Y, the multiple source contact regions 35s may have a length greater than the length of the multiple source structures 20, or may have a length less than the length of the multiple source structures 20.
  • the multiple source contact regions 35s preferably have a total planar area that is greater than the total planar area of the multiple gate contact regions 35g.
  • the total planar area of the multiple source contact regions 35s may be greater than the channel area or less than the channel area.
  • the configuration of one source contact region 35s is described below.
  • the source contact region 35s is connected to the bottom wall of the corresponding source structure 20 and the upper end of the corresponding source column region 25s.
  • the multiple source contact regions 35s protrude from the region directly below the source structure 20 to both sides of the source structure 20 and have extensions that extend along the side walls of the source structure 20.
  • the thickness in the horizontal direction (first direction X) of the portion (extension) of the source contact region 35s that runs along the side wall of the source structure 20 is preferably less than the thickness in the vertical direction Z of the portion of the source contact region 35s that runs along the bottom wall of the source structure 20.
  • the extension of the source contact region 35s is electrically connected to the body region 13 in the surface portion of the first surface portion 8 (first main surface 3), and electrically connects the corresponding source column region 25s to the body region 13. This prevents the source column region 25s from becoming electrically floating, improving the electrical response characteristics of the source column region 25s.
  • the source contact region 35s has an upper end exposed from the first surface portion 8.
  • the upper end of the source contact region 35s is exposed from the sidewall of the second trench 21 at the opening end of the second trench 21.
  • the upper end of the source contact region 35s may extend horizontally in the surface portion of the body region 13.
  • the upper end of the source contact region 35s is electrically connected to the upper end of the gate contact region 35g within the body region 13.
  • the upper end of the source contact region 35s is formed integrally with the upper end of the gate contact region 35g.
  • the semiconductor device 1 includes a main surface insulating film 40 that covers the first main surface 3.
  • the main surface insulating film 40 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the main surface insulating film 40 includes an insulating material of the same type as either or both of the insulating material of the first insulating film 17 and the insulating material of the second insulating film 22. In this embodiment, the main surface insulating film 40 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 40 includes a silicon oxide film made of an oxide of the chip 2.
  • the main surface insulating film 40 selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D.
  • the main surface insulating film 40 is selectively connected to the first insulating film 17 of the multiple gate structures 15 and the second insulating film 22 of the multiple source structures 20 on the first surface portion 8, exposing the first buried electrodes 18 of the multiple gate structures 15 and the second buried electrodes 23 of the multiple source structures 20.
  • the main surface insulating film 40 is continuous with the first to fourth side surfaces 5A to 5D at the periphery of the second surface 9.
  • the main surface insulating film 40 may be formed at a distance inward from the periphery of the second surface 9, exposing the second semiconductor region 7 from the periphery of the second surface 9.
  • the semiconductor device 1 includes an insulating interlayer film 41 that covers the main surface insulating film 40.
  • the interlayer film 41 may be called an "insulating film,” an "interlayer insulating film,” an “intermediate insulating film,” or the like.
  • the interlayer film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the interlayer film 41 include a silicon oxide film.
  • the interlayer film 41 selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D with the main surface insulating film 40 sandwiched therebetween.
  • the interlayer film 41 covers the multiple gate structures 15 (first buried electrodes 18) on the first surface portion 8, and selectively exposes the multiple source structures 20 (second buried electrodes 23).
  • the interlayer film 41 is continuous with the first to fourth side surfaces 5A to 5D at the periphery of the second surface portion 9.
  • the interlayer film 41 may be formed at a distance inward from the periphery of the second surface portion 9, exposing the second semiconductor region 7 from the periphery of the second surface portion 9.
  • the interlayer film 41 may have a thickness of 0.5 ⁇ m or more and 3 ⁇ m or less.
  • the thickness of the interlayer film 41 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the semiconductor device 1 includes a plurality of source openings 42 formed in an interlayer film 41.
  • the plurality of source openings 42 are each formed in a region between the plurality of gate structures 15, and each exposes a corresponding one of the source structures 20 in a one-to-one correspondence.
  • the plurality of source openings 42 each exposes a corresponding one of the source structures 20, the source region 14, and the plurality of source contact regions 35s.
  • the plurality of source openings 42 each extend in a band shape in the second direction Y along the corresponding source structure 20. It is preferable that each of the plurality of source openings 42 has an opening end curved in an arc shape.
  • multiple source openings 42 may be formed in a one-to-many correspondence with a corresponding source structure 20.
  • the multiple source openings 42 may be formed at intervals in the second direction Y along the corresponding source structure 20.
  • the multiple source openings 42 may be formed in a quadrangular shape, a rectangular shape (strip shape) extending in the first direction X, a rectangular shape (strip shape) extending in the second direction Y, a circular shape, etc. in a plan view.
  • the semiconductor device 1 includes a plurality of gate openings 43 formed in an interlayer film 41 (see FIG. 4).
  • the plurality of gate openings 43 are each formed in a region between a plurality of source structures 20, and each exposes one corresponding gate structure 15 in a one-to-many correspondence.
  • the plurality of gate openings 43 expose one end and the other end of the corresponding gate structure 15 (first buried electrode 18).
  • the multiple gate openings 43 preferably each have an opening end curved in an arc, similar to the source opening 42.
  • the multiple gate openings 43 may be formed in a quadrangular shape, a rectangular shape (strip shape) extending in the first direction X, a rectangular shape (strip shape) extending in the second direction Y, a circular shape, etc., in a plan view.
  • the semiconductor device 1 includes a source electrode 45 disposed on the first main surface 3.
  • the source electrode 45 is a terminal electrode to which a source potential is applied from the outside.
  • the source electrode 45 may also be referred to as a "source pad electrode,” a “first pad electrode,” a “first main surface electrode,” a “first terminal electrode,” etc.
  • the source electrode 45 is disposed on a portion of the interlayer film 41 that covers the first surface portion 8.
  • the source electrode 45 has a first pad portion 45a, a second pad portion 45b, and a third pad portion 45c.
  • the first pad portion 45a has a relatively large planar area and forms the main body of the source electrode 45.
  • the first pad portion 45a is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is biased toward the fourth side surface 5D relative to the center of the first surface portion 8.
  • the second pad portion 45b has a planar area less than that of the first pad portion 45a, and is drawn out in a strip (rectangular) shape from one end of the first pad portion 45a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C.
  • the third pad portion 45c has a planar area less than that of the first pad portion 45a, and is drawn out in a strip (rectangular) shape from the other end of the first pad portion 45a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 45b in the second direction Y.
  • the plane area of the third pad portion 45c may be approximately equal to the plane area of the second pad portion 45b. Of course, the plane area of the third pad portion 45c may be greater than the plane area of the second pad portion 45b, or may be less than the plane area of the second pad portion 45b. Either or both of the second pad portion 45b and the third pad portion 45c may be used as a terminal portion for monitoring a current.
  • the source electrode 45 does not necessarily have to have both the second pad portion 45b and the third pad portion 45c at the same time.
  • the source electrode 45 may have only one of the second pad portion 45b and the third pad portion 45c.
  • the source electrode 45 may be composed of only the first pad portion 45a and may not have both the second pad portion 45b and the third pad portion 45c.
  • the source electrode 45 extends from above the interlayer film 41 into the multiple source openings 42, and is electrically connected to the body region 13, the source region 14, the multiple source structures 20, and the multiple source contact regions 35s within the multiple source openings 42.
  • the source electrode 45 has a layered structure including a lower electrode film 46 and a main electrode film 47, which are layered in this order from the chip 2 side.
  • the lower electrode film 46 has a layered structure including a first electrode film 48 and a second electrode film 49.
  • the first electrode film 48 includes a Ti film
  • the second electrode film 49 includes a TiN film.
  • the lower electrode film 46 does not necessarily have to have a layered structure, and may have a single layer structure consisting of either the first electrode film 48 (Ti film) or the second electrode film 49 (TiN film).
  • the first electrode film 48 has a thickness less than the thickness of the interlayer film 41.
  • the thickness of the first electrode film 48 may be 10 nm or more and 100 nm or less.
  • the thickness of the first electrode film 48 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.
  • the second electrode film 49 has a thickness less than the thickness of the interlayer film 41.
  • the thickness of the second electrode film 49 is preferably greater than the thickness of the first electrode film 48.
  • the thickness of the second electrode film 49 may be 50 nm or more and 200 nm or less.
  • the thickness of the second electrode film 49 may have a value belonging to at least one of the following ranges: 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.
  • the first electrode film 48 collectively covers the region of the interlayer film 41 where the multiple source openings 42 are formed, and extends from above the interlayer film 41 into the multiple source openings 42.
  • the first electrode film 48 has a portion that covers the insulating main surface of the interlayer film 41 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 42 in a film-like manner, and a portion that covers the first main surface 3 within the multiple source openings 42 in a film-like manner.
  • the first electrode film 48 directly covers the insulating main surface of the interlayer film 41 and faces the gate structure 15 across the interlayer film 41.
  • the first electrode film 48 extends in an arc shape from above the insulating main surface of the interlayer film 41 following the opening edge of the source opening 42, and covers the wall surface of the source opening 42 in a film-like manner.
  • the first electrode film 48 covers the first main surface 3 (first surface portion 8) in the source opening 42 in a film-like manner, and is mechanically and electrically connected to the source region 14 and the multiple source contact regions 35s on the first main surface 3.
  • the first electrode film 48 penetrates into the second trench 21 from above the first main surface 3, and coats the sidewall of the second trench 21, the second insulating film 22, and the second buried electrode 23 in a film-like manner.
  • the first electrode film 48 is mechanically and electrically connected to the source region 14, the second buried electrode 23, and the multiple source contact regions 35s within the second trench 21.
  • the second electrode film 49 directly covers the first electrode film 48.
  • the second electrode film 49 collectively covers the region of the interlayer film 41 where the multiple source openings 42 are formed, sandwiching the first electrode film 48, and extends into the multiple source openings 42 from above the interlayer film 41.
  • the second electrode film 49 has a portion that sandwiches the first electrode film 48 and covers the insulating main surface of the interlayer film 41 in a film-like manner, a portion that sandwiches the first electrode film 48 and covers the wall surfaces of the multiple source openings 42 in a film-like manner, and a portion that sandwiches the first electrode film 48 within the multiple source openings 42 and covers the first main surface 3 in a film-like manner.
  • the second electrode film 49 covers the insulating main surface of the interlayer film 41 with the first electrode film 48 in between, and faces the gate structure 15 with the interlayer film 41 and the first electrode film 48 in between.
  • the second electrode film 49 covers the opening end of the source opening 42 in an arc shape with the first electrode film 48 in between, and covers the wall surface of the source opening 42 in a film shape with the first electrode film 48 in between.
  • the second electrode film 49 covers the first main surface 3 (first surface portion 8) in a film shape within the source opening 42 with the first electrode film 48 in between, and is electrically connected to the source region 14, the source structure 20, and the multiple source contact regions 35s via the first electrode film 48.
  • the second electrode film 49 enters the second trench 21 from above the first main surface 3 and covers the sidewall of the second trench 21, the second insulating film 22, and the second buried electrode 23 in a film-like manner, sandwiching the first electrode film 48 between them.
  • the second electrode film 49 is electrically connected to the source region 14, the second buried electrode 23, and the multiple source contact regions 35s within the second trench 21 via the first electrode film 48.
  • the main electrode film 47 contains a conductive material different from that of the lower electrode film 46 (the first electrode film 48 and the second electrode film 49).
  • the main electrode film 47 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the main electrode film 47 has a thickness greater than the thickness (total thickness) of the lower electrode film 46.
  • the thickness of the main electrode film 47 is preferably greater than the thickness of the interlayer film 41.
  • the thickness of the main electrode film 47 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the main electrode film 47 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the main electrode film 47 directly covers the lower electrode film 46 (second electrode film 49).
  • the main electrode film 47 backfills the second trenches 21 and the source openings 42, and collectively covers the region of the interlayer film 41 in which the source openings 42 are formed.
  • the main electrode film 47 has a portion that covers the insulating main surface of the interlayer film 41 with the lower electrode film 46 in between, a portion that covers the wall surfaces of the source openings 42 with the lower electrode film 46 in between, and a portion that covers the first main surface 3 with the lower electrode film 46 in between.
  • the main electrode film 47 covers the insulating main surface of the interlayer film 41 with the lower electrode film 46 in between, and faces the gate structure 15 with the interlayer film 41 and the lower electrode film 46 in between.
  • the main electrode film 47 covers the opening end of the source opening 42 with the lower electrode film 46 in between.
  • the main electrode film 47 covers the first main surface 3 (first surface portion 8) within the source opening 42 with the lower electrode film 46 in between, and is electrically connected to the source region 14 and the multiple source contact regions 35s via the lower electrode film 46.
  • the main electrode film 47 enters the second trench 21 from above the first main surface 3, and covers the sidewall of the second trench 21, the second insulating film 22, and the second buried electrode 23 with the lower electrode film 46 in between.
  • the main electrode film 47 is electrically connected to the source region 14, the second buried electrode 23, and the multiple source contact regions 35s via the lower electrode film 46 within the second trench 21.
  • the semiconductor device 1 includes a gate electrode 50 disposed on the first main surface 3.
  • the gate electrode 50 is a terminal electrode to which a gate potential is applied from the outside.
  • the gate electrode 50 may also be referred to as a "second pad electrode,” a “second main surface electrode,” a “second terminal electrode,” etc.
  • the gate electrode 50 includes a lower electrode film 46 and a main electrode film 47 that are laminated in this order from the chip 2 side, similar to the source electrode 45.
  • the gate electrode 50 is disposed on a portion of the interlayer film 41 that covers the first surface portion 8, spaced apart from the source electrode 45.
  • the gate electrode 50 is disposed in a region on the third side surface 5C side of the first pad portion 45a, and faces the first pad portion 45a in the first direction X.
  • the gate electrode 50 is also interposed in a region between the second pad portion 45b and the third pad portion 45c, and faces both the second pad portion 45b and the third pad portion 45c in the second direction Y.
  • the gate electrode 50 is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the gate electrode 50 has a planar area less than the planar area of the source electrode 45.
  • the gate electrode 50 has a planar area less than the planar area of the first pad portion 45a.
  • the gate electrode 50 may have a planar area less than the planar area of the second pad portion 45b (third pad portion 45c).
  • the gate electrode 50 partially faces the multiple gate structures 15 and multiple source structures 20 across the interlayer film 41. Specifically, the gate electrode 50 is disposed at a distance inward from both ends of the multiple gate structures 15 and both ends of the multiple source structures 20, and faces the inner parts of the multiple gate structures 15 and the inner parts of the multiple source structures 20 across the interlayer film 41.
  • the gate electrode 50 does not have a direct electrical connection to the multiple gate structures 15.
  • the gate electrode 50 may be electrically connected to the multiple gate structures 15 via the multiple gate openings 43.
  • the portion of the multiple gate structures 15 that is located at the gate electrode 50 may be removed.
  • the gate electrode 50 may face the body region 13 with the main surface insulating film 40 and the interlayer film 41 sandwiched therebetween.
  • the semiconductor device 1 includes a gate wiring 51 extending from the gate electrode 50 onto the first main surface 3.
  • the gate wiring 51 may also be referred to as a "gate finger” or “gate finger electrode.”
  • the gate wiring 51 transmits the gate potential applied to the gate electrode 50 to other regions.
  • the gate wiring 51 includes a lower electrode film 46 and a main electrode film 47, which are stacked in this order from the chip 2 side, similar to the source electrode 45 (gate electrode 50).
  • the gate wiring 51 is drawn out from the gate electrode 50 onto a portion of the interlayer film 41 that covers the first surface 8.
  • the gate wiring 51 is routed in a strip shape in the region between the periphery of the first surface 8 and the source electrode 45.
  • the gate wiring 51 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y.
  • the gate wiring 51 is formed in a strip shape with ends having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 45.
  • the gate wiring 51 intersects (specifically, perpendicular to) the ends (both ends in this embodiment) of the multiple gate structures 15.
  • the gate wiring 51 enters the multiple gate openings 43 from above the interlayer film 41, and is mechanically and electrically connected to the ends (both ends) of the multiple gate structures 15 (first buried electrodes 18) within the multiple gate openings 43.
  • the gate potential applied to the gate electrode 50 is applied to the multiple gate structures 15 via the gate wiring 51.
  • the semiconductor device 1 includes a drain electrode 52 covering the second main surface 4.
  • the drain electrode 52 is a terminal electrode to which a drain potential is applied from the outside.
  • the drain electrode 52 may be referred to as a "third pad electrode,” a “third main surface electrode,” a “third terminal electrode,” etc.
  • the drain electrode 52 is electrically connected to the first semiconductor region 6.
  • the drain electrode 52 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D).
  • the drain electrode 52 may partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.
  • the breakdown voltage that can be applied between the source electrode 45 and the drain electrode 52 (between the first major surface 3 and the second major surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that belongs to at least one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • FIGS 12A to 12F are enlarged plan views showing a main portion of the first main surface 3 together with the contact region 35 according to the second to seventh layout examples.
  • the semiconductor device 1 can include the features of any one of the contact regions 35 according to the first to seventh layout examples.
  • the features of the contact regions 35 according to the first to seventh layout examples can be combined as appropriate.
  • the semiconductor device 1 can include at least two of the features of the contact regions 35 according to the first to seventh layout examples simultaneously in the same or different regions.
  • the multiple contact regions 35 may include multiple gate contact regions 35g arranged in a staggered pattern with spaces in between in the first direction X and the second direction Y in a plan view. That is, with respect to one gate structure 15 and the other gate structure 15, the multiple gate contact regions 35g along one gate structure 15 may face in the first direction X a region between the multiple gate contact regions 35g along the other gate structure 15 in a plan view.
  • the contact regions 35 may include source contact regions 35s formed in a one-to-many correspondence with the source structures 20.
  • the source contact regions 35s are respectively interposed in regions between the bottom walls of the source structures 20 and the upper ends of the source column regions 25s, and are formed at intervals in the second direction Y.
  • the multiple source contact regions 35s along one source structure 20 may face the multiple source contact regions 35s along the other source structure 20 in the first direction X in a planar view.
  • the multiple source contact regions 35s may be generally arranged in a matrix with gaps in the first direction X and the second direction Y in a planar view.
  • the multiple source contact regions 35s extend in a band shape along the multiple source structures 20 in a planar view.
  • the lengths of the multiple source contact regions 35s in the second direction Y may be equal to each other or may be different from each other.
  • the length of the multiple source contact regions 35s may be greater than the width of the source structure 20 or may be less than the width of the source structure 20.
  • the length of the multiple source contact regions 35s may be greater than the source pitch of the multiple source structures 20 or may be less than the source pitch. In this embodiment, the length of the multiple source contact regions 35s is approximately equal to the length of the multiple gate contact regions 35g.
  • the length of the multiple source contact regions 35s may be greater than or less than the length of the multiple gate contact regions 35g.
  • the spacing between the multiple source contact regions 35s in the second direction Y may be greater than or less than the width of the source structure 20.
  • the spacing between the multiple source contact regions 35s may be greater than or less than the source pitch.
  • the multiple source contact regions 35s are arranged in regions adjacent to the multiple gate contact regions 35g on both sides in the first direction X.
  • the upper ends of the source contact regions 35s are integrally formed with the upper ends of the multiple gate contact regions 35g.
  • the multiple source contact regions 35s, together with the multiple gate contacts form multiple contact regions 35 extending in stripes in the first direction X.
  • the contact regions 35 have a layout obtained by modifying the layout of the source contact regions 35s in the third layout example (see FIG. 12B).
  • the source contact regions 35s may have a length greater than the length of the gate contact regions 35g in the second direction Y in a plan view.
  • the contact regions 35 have a layout obtained by modifying the layout of the source contact regions 35s in the third layout example (see FIG. 12B).
  • the source contact regions 35s may be formed offset in the second direction Y from the gate structures 15.
  • the source contact regions 35s may have portions that face the first direction X in the regions between the gate structures 15.
  • the multiple source contact regions 35s may face the multiple gate structures 15 in the first direction X across the source region 14 in a cross-sectional view.
  • the multiple source contact regions 35s may be formed spaced apart from the multiple gate contact regions 35g in the second direction Y, or may have portions connected to the multiple gate contact regions 35g.
  • the contact regions 35 have a layout obtained by modifying the layout of the source contact regions 35s in the fifth layout example (see FIG. 12D).
  • the source contact regions 35s may have a length in the second direction Y that is greater than the length of the gate contact regions 35g in a plan view.
  • the source contact regions 35s may be formed spaced apart from the gate contact regions 35g in the second direction Y, or may have a portion connected to the gate contact regions 35g.
  • the multiple column regions 25 may include multiple (at least two) source contact regions 35s arranged in the range between two gate contact regions 35g adjacent to each other in the second direction Y.
  • FIG. 12F shows an example in which three source contact regions 35s are formed in the range between two gate contact regions 35g adjacent to each other in the second direction Y.
  • the source contact region 35s adjacent to the gate contact region 35g may be formed at a distance from the gate contact region 35g in the second direction Y, or may have a portion connected to the gate contact region 35g.
  • the length of the multiple source contact regions 35s may be greater than the length of the multiple gate contact regions 35g, or may be smaller than the length of the multiple gate contact regions 35g.
  • the semiconductor device 1 includes the chip 2, the second semiconductor region 7 (semiconductor region) of n-type (first conductivity type), the trench-type source structure 20, and the source column region 25s (impurity region) of p-type (second conductivity type).
  • the chip 2 has a first main surface 3.
  • the second semiconductor region 7 is formed in a surface layer portion of the first main surface 3.
  • the source structure 20 is formed on the first main surface 3 and is located within the second semiconductor region 7.
  • the source column region 25s is formed in a region directly below the source structure 20 within the chip 2, and forms a pn junction with the second semiconductor region 7.
  • This configuration provides a semiconductor device 1 capable of improving electrical characteristics. Specifically, in this semiconductor device 1, a depletion layer spreads from the source column region 25s located directly below the source structure 20. This improves the breakdown voltage (e.g., breakdown voltage) by utilizing the region directly below the source structure 20.
  • the chip 2 preferably contains SiC. This configuration provides a SiC semiconductor device as the semiconductor device 1 capable of improving electrical characteristics.
  • the source column region 25s may be formed at a distance from the bottom wall of the source structure 20.
  • the bottom wall of the source structure 20 is preferably formed flat. With this configuration, for example, when a p-type impurity (trivalent element) is introduced into the chip 2 through the bottom wall of the source structure 20, the p-type impurity can be introduced into the chip 2 through the flat bottom wall. This allows the source column region 25s to be appropriately formed in the chip 2.
  • the source column region 25s is preferably formed in a columnar shape extending in the thickness direction of the chip 2 in a cross-sectional view. With this configuration, a pn junction is formed along the thickness direction of the chip 2 in a cross-sectional view. This expands the range of expansion of the depletion layer in the chip 2, thereby appropriately improving the breakdown voltage.
  • the source column region 25s preferably crosses the intermediate portion between the bottom of the second semiconductor region 7 and the bottom wall of the source structure 20.
  • the semiconductor device 1 may include a p-type body region 13 formed in a surface layer of the first main surface 3. In this case, the source structure 20 may penetrate the body region 13.
  • the semiconductor device 1 may include a p-type source contact region 35s formed in a region along the source structure 20 within the chip 2.
  • the source contact region 35s may have a p-type impurity concentration higher than the p-type impurity concentration of the body region 13.
  • the source contact region 35s may have a portion interposed between the source structure 20 and the source column region 25s.
  • the source contact region 35s may electrically connect the source column region 25s to the body region 13. With this configuration, the electrical response characteristics of the source column region 25s are improved by the source contact region 35s.
  • the semiconductor device 1 may include a trench-type gate structure 15.
  • the gate structure 15 may be formed on the first main surface 3 and located within the second semiconductor region 7.
  • the source structure 20 may be formed at a distance from the gate structure 15.
  • the source structure 20 may have a depth approximately equal to that of the gate structure 15.
  • the source structure 20 may have a width approximately equal to that of the gate structure 15.
  • the semiconductor device 1 may include a p-type gate column region 25g formed in the region directly below the gate structure 15 in the chip 2 and forming a pn junction with the second semiconductor region 7.
  • the source column region 25s may be formed at a distance from the gate column region 25g.
  • the location where the gate column region 25g is formed is limited to the region directly below the gate structure 15, and the location where the source column region 25s is formed is limited to the region directly below the source structure 20. Therefore, the distance between the gate column region 25g and the source column region 25s can be limited to the distance between the gate structure 15 and the source structure 20.
  • the pitch between the center of the gate column region 25g and the center of the source column region 25s is approximately equal to the pitch between the center of the gate structure 15 and the center of the source structure 20.
  • the semiconductor device 1 may include an n-type intermediate drift region 30 that is formed in a region between the source column region 25s and the gate column region 25g within the chip 2 and that forms a superjunction structure with the source column region 25s and the gate column region 25g.
  • This configuration provides a superjunction type semiconductor device 1 with an appropriate charge balance.
  • This configuration is preferably applied to a configuration in which the chip 2 includes SiC. In this case, a superjunction type SiC semiconductor device with an appropriate charge balance is provided.
  • a plurality of gate structures 15 may be formed on the first main surface 3 at intervals.
  • a plurality of source structures 20 may be formed in the first main surface 3 in regions between the plurality of gate structures 15.
  • a plurality of gate column regions 25g may be formed in regions directly below the plurality of gate structures 15.
  • a plurality of source column regions 25s may be formed in regions directly below the plurality of source structures 20 at intervals from the plurality of gate column regions 25g.
  • the multiple gate structures 15 may be arranged in a stripe pattern in a plan view.
  • the multiple source structures 20 may be arranged in a stripe pattern extending along the multiple gate structures 15 in a plan view.
  • the source column region 25s may have a depth approximately equal to that of the gate column region 25g.
  • the source column region 25s may have a width approximately equal to that of the gate column region 25g.
  • the chip 2 may have an off angle that is inclined toward the off direction.
  • the gate column region 25g may extend in a strip shape along the off direction in a plan view.
  • the source column region 25s may extend in a strip shape along the off direction in a plan view.
  • FIG. 13 is a schematic diagram showing a wafer 60 used in the manufacture of a semiconductor device 1.
  • the wafer 60 is the base material of the chip 2 and contains a SiC single crystal.
  • the wafer 60 is formed in a flat disk shape. Of course, the wafer 60 may also be formed in a flat rectangular parallelepiped shape.
  • the wafer 60 has a first wafer main surface 61 on one side, a second wafer main surface 62 on the other side, and a wafer side surface 63 connecting the first wafer main surface 61 and the second wafer main surface 62.
  • the first wafer main surface 61 corresponds to the first main surface 3 of the chip 2
  • the second wafer main surface 62 corresponds to the second main surface 4 of the chip 2.
  • the first wafer main surface 61 and the second wafer main surface 62 are formed by the c-plane of the SiC single crystal.
  • the first wafer main surface 61 is formed by the silicon surface of the SiC single crystal
  • the second wafer main surface 62 is formed by the carbon surface of the SiC single crystal.
  • the wafer 60 (the first wafer main surface 61 and the second wafer main surface 62) has the off-direction and off-angle described above.
  • the wafer 60 has a mark 64 on the wafer side surface 63 that indicates the crystal orientation of the SiC single crystal.
  • the mark 64 may include either or both of an orientation flat and an orientation notch.
  • the orientation flat consists of a cutout that is cut in a straight line in a plan view.
  • the orientation notch consists of a cutout that is cut in a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 61 in a plan view.
  • the mark 64 may include either or both of a first orientation flat extending in the a-axis direction and a second orientation flat extending in the m-axis direction.
  • the mark 64 may include either or both of an orientation notch recessed in the a-axis direction and an orientation notch recessed in the m-axis direction.
  • the wafer 60 includes an n-type first semiconductor region 6 formed in a surface layer of the second wafer main surface 62.
  • the first semiconductor region 6 is formed in a layer extending along the second wafer main surface 62, and is exposed from the second wafer main surface 62 and the wafer side surface 63.
  • the first semiconductor region 6 is made of an n-type semiconductor wafer (SiC wafer) containing SiC single crystal (semiconductor single crystal), and has the off direction and off angle described above.
  • the wafer 60 includes an n-type second semiconductor region 7 formed in the surface layer of the first wafer main surface 61.
  • the second semiconductor region 7 is formed in a layer extending along the first wafer main surface 61 and is exposed from the first wafer main surface 61 and the wafer side surface 63.
  • the second semiconductor region 7 is made of an n-type epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal) and is stacked on the first semiconductor region 6. That is, in this form, the wafer 60 is made of an epitaxial wafer (so-called epiwafer) having a stacked structure including a semiconductor wafer and an epitaxial layer.
  • the second semiconductor region 7 has the off direction and off angle described above.
  • the wafer 60 includes a plurality of device regions 65 and a plurality of cutting lines 66.
  • the plurality of device regions 65 and the plurality of cutting lines 66 are defined by alignment marks or the like formed on the first wafer main surface 61 side.
  • Each device region 65 is a region corresponding to a semiconductor device 1.
  • the plurality of device regions 65 are each set to have a rectangular shape in a plan view.
  • the multiple device regions 65 are set in a matrix along the first direction X and the second direction Y in a plan view.
  • the multiple device regions 65 are each set at intervals inward from the periphery of the first wafer main surface 61 in a plan view.
  • the multiple cutting lines 66 are set in a lattice extending along the first direction X and the second direction Y to partition the multiple device regions 65.
  • FIGS. 14A to 14N are cross-sectional views showing an example of a manufacturing method for semiconductor device 1.
  • FIG. 14A to FIG. 14N a cross section of a region corresponding to FIG. 6 is shown.
  • the aforementioned wafer 60 (see FIG. 13) is prepared.
  • FIG. 14B low concentration region 7a and high concentration region 7b of second semiconductor region 7 are formed.
  • n-type impurities are introduced into the second semiconductor region 7 by ion implantation.
  • the ion implantation may be either or both of channeling ion implantation and random ion implantation.
  • n-type impurities are introduced into the second semiconductor region 7 along the axial channel of the second semiconductor region 7 (wafer 60).
  • n-type impurities are implanted deep into the second semiconductor region 7 while repeatedly undergoing small-angle scattering due to the channeling effect.
  • the channeling implantation method reduces the probability of n-type impurities colliding with the atomic rows of the SiC single crystal. Therefore, the channeling ion implantation process is effective when forming a relatively deep high-concentration region 7b.
  • n-type impurities are introduced into the second semiconductor region 7 in a random direction.
  • the random direction is a direction other than the axial channel of the second semiconductor region 7 (i.e., a direction intersecting the axial channel).
  • the random direction is the vertical direction Z.
  • the collision probability of the n-type impurities with the atomic rows of the SiC single crystal is high, so the high concentration region 7b is formed in a relatively shallow region. Therefore, the random ion implantation process is effective when forming a relatively shallow high concentration region 7b.
  • n-type impurities are introduced into the surface region of the second semiconductor region 7 so that the bottom region of the second semiconductor region 7 remains as a low concentration region 7a.
  • the second semiconductor region 7 including the low concentration region 7a and the high concentration region 7b is formed in the surface region of the first wafer main surface 61.
  • the body region 13 is formed in the surface layer portion of the first wafer main surface 61 (specifically, the surface layer portion of the second semiconductor region 7).
  • the p-type impurity is introduced into the surface layer portion of the high concentration region 7b.
  • the body region 13 is formed in the surface layer portion of the first wafer main surface 61.
  • the source region 14 is formed in the surface portion of the first wafer main surface 61 (specifically, the surface portion of the body region 13).
  • a mask (not shown) having a predetermined layout is formed on the first wafer main surface 61.
  • the mask may be an inorganic mask or an organic mask (resist mask).
  • the mask (not shown) exposes the region where the source region 14 is to be formed and covers the other regions.
  • n-type impurities are introduced into the surface layer of the body region 13 by ion implantation through a mask (not shown). This forms a source region 14 in the surface layer of the body region 13.
  • the mask (not shown) is then removed.
  • the n-type impurities may be introduced into the entire area of the first wafer main surface 61 without using a mask (not shown).
  • a first mask 70 having a predetermined layout is formed on the first wafer main surface 61.
  • the first mask 70 may be an inorganic mask or an organic mask (resist mask).
  • the first mask 70 exposes the areas where the second surface portion 9, the multiple first trenches 16, and the multiple second trenches 21 are to be formed, and covers the other areas.
  • etching may be either wet etching or dry etching, or both. This results in the formation of the first surface 8, the second surface 9, a plurality of first trenches 16, and a plurality of second trenches 21.
  • first trenches 16 and the second trenches 21 are formed substantially perpendicular to the first wafer main surface 61. Furthermore, the bottom walls of the first trenches 16 and the bottom walls of the second trenches 21 are each formed flat.
  • a plurality of column regions 25 are formed inside the wafer 60 (specifically, the second semiconductor region 7). Specifically, this process includes forming a plurality of gate column regions 25g in the second semiconductor region 7 in regions aligned with the first trenches 16, and forming a plurality of source column regions 25s in the second semiconductor region 7 in regions aligned with the second trenches 21.
  • p-type impurities are introduced into the second semiconductor region 7 by ion implantation through the first mask 70 described above.
  • the p-type impurities are introduced into the second semiconductor region 7 through the bottom walls of the first trenches 16 and the bottom walls of the second trenches 21.
  • the ion implantation may be either or both of a channeling ion implantation method and a random ion implantation method. It is preferable that the ion implantation method is a channeling ion implantation method.
  • a plurality of relatively deep gate column regions 25g are formed with relatively high directivity in the region directly below the plurality of first trenches 16, and a plurality of relatively deep source column regions 25s are formed with relatively high directivity in the region directly below the plurality of second trenches 21.
  • a plurality of gate column regions 25g having a pitch approximately equal to the pitch of the plurality of first trenches 16 are formed, and a plurality of source column regions 25s having a pitch approximately equal to the pitch of the plurality of second trenches 21 are formed.
  • the first trenches 16 have flat bottom walls, the variation in the introduction depth of the p-type impurities caused by the variation in the depth of the bottom walls of the first trenches 16 is suppressed. This improves the accuracy of introducing the p-type impurities into the second semiconductor region 7.
  • the second trenches 21 have flat bottom walls, the variation in the introduction depth of the p-type impurities caused by the variation in the depth of the bottom walls of the second trenches 21 is suppressed. This improves the accuracy of introducing the p-type impurities into the second semiconductor region 7.
  • the first mask 70 is removed after this process.
  • the p-type impurity is introduced into the second semiconductor region 7 through the first mask 70.
  • the p-type impurity may be introduced into the second semiconductor region 7 by ion implantation through a mask different from the first mask 70.
  • a plurality of contact regions 35 are formed inside the wafer 60 (specifically, the second semiconductor region 7).
  • This process includes forming a plurality of gate contact regions 35g in the second semiconductor region 7 in regions aligned with the first trenches 16, and forming a plurality of source contact regions 35s in the second semiconductor region 7 in regions aligned with the second trenches 21.
  • a second mask 71 having a predetermined layout is formed on the first wafer main surface 61.
  • the second mask 71 may be an inorganic mask (e.g., a silicon oxide film) or an organic mask (resist mask).
  • the second mask 71 exposes the regions where the multiple gate contact regions 35g and the multiple source contact regions 35s are to be formed, and covers the other regions. In other words, the second mask 71 covers a portion of the first wafer main surface 61, and selectively exposes the wall surfaces of the multiple first trenches 16 and the wall surfaces of the multiple second trenches 21.
  • p-type impurities are introduced into the second semiconductor region 7 through a portion of the first wafer main surface 61, the walls of the first trenches 16, and the walls of the second trenches 21 by ion implantation through the second mask 71.
  • the ion implantation may be either or both of a channeling ion implantation method and a random ion implantation method.
  • the ion implantation method is a random ion implantation method.
  • the random ion implantation method may be a vertical ion implantation method.
  • the p-type impurity is introduced into the second semiconductor region 7 at an implantation angle that is approximately vertical to the first wafer main surface 61.
  • the random ion implantation method may be an oblique ion implantation method.
  • the p-type impurity is introduced into the second semiconductor region 7 at an implantation angle that is oblique to the first wafer main surface 61.
  • the implantation angle may be greater than 0° and less than or equal to 10°.
  • a base insulating film 72 is formed on the first wafer main surface 61.
  • the base insulating film 72 serves as a base for the multiple first insulating films 17, the multiple second insulating films 22, and the main surface insulating film 40.
  • the base insulating film 72 collectively covers the first surface portion 8, the second surface portion 9, the first to fourth connection surface portions 10A to 10D, the wall surfaces of the multiple first trenches 16, and the wall surfaces of the multiple second trenches 21 in a film-like manner.
  • the base insulating film 72 may be formed by either one or both of a CVD method and an oxidation method (for example, a thermal oxidation method).
  • a first base electrode film 73 is formed on the base insulating film 72.
  • the first base electrode film 73 serves as a base for the multiple first buried electrodes 18 and the multiple second buried electrodes 23.
  • the first base electrode film 73 has a portion that covers the first wafer main surface 61 with the base insulating film 72 in between, a portion that is embedded in the multiple first trenches 16 with the base insulating film 72 in between, and a portion that is embedded in the multiple second trenches 21 with the base insulating film 72 in between.
  • the base insulating film 72 may be formed by a CVD method.
  • the etching method may be either or both of a wet etching method and a dry etching method.
  • a plurality of first buried electrodes 18 and a plurality of second buried electrodes 23 are formed.
  • a plurality of gate structures 15 and a plurality of source structures 20 are formed.
  • an interlayer film 41 is formed on the first wafer main surface 61 (specifically, the first base electrode film 73).
  • the interlayer film 41 collectively covers the first surface portion 8, the second surface portion 9, the first to fourth connection surface portions 10A to 10D, the multiple gate structures 15, and the multiple source structures 20 in a film-like manner.
  • the interlayer film 41 may be formed by a CVD method.
  • a third mask 74 having a predetermined layout is formed on the interlayer film 41.
  • the third mask 74 may be an organic mask (resist mask).
  • the third mask 74 exposes the areas where the source openings 42 and the gate openings 43 are to be formed, and covers the other areas.
  • unnecessary portions of the interlayer film 41 are removed by an etching method via the third mask 74.
  • the etching method may be either or both of a wet etching method and a dry etching method.
  • the unnecessary portions of the base insulating film 72 are removed by etching through the third mask 74.
  • the etching method may be either wet etching or dry etching, or both.
  • the unnecessary portions of the base insulating film 72 may be removed simultaneously with the interlayer film 41.
  • a plurality of source openings 42 and a plurality of gate openings 43 are formed in the interlayer film 41.
  • the base insulating film 72 is also divided into a plurality of first insulating films 17, a plurality of second insulating films 22, and a main surface insulating film 40.
  • the third mask 74 is then removed.
  • a second base electrode film 75 is formed on the interlayer film 41.
  • the second base electrode film 75 is the base for the source electrode 45, the gate electrode 50, and the gate wiring 51.
  • the second base electrode film 75 has a layered structure including a lower electrode film 46 and a main electrode film 47.
  • the lower electrode film 46 has a layered structure including a first electrode film 48 and a second electrode film 49.
  • the first electrode film 48 may be formed by either one or both of a sputtering method and a vapor deposition method.
  • the first electrode film 48 is formed in a film shape along the first wafer main surface 61, the interlayer film 41, the wall surfaces of the multiple source openings 42, and the wall surfaces of the multiple gate openings 43.
  • the second electrode film 49 may be formed by either one or both of a sputtering method and a vapor deposition method.
  • the second electrode film 49 is laminated on the first electrode film 48 and formed in a film shape along the first wafer main surface 61, the interlayer film 41, the wall surfaces of the multiple source openings 42, and the wall surfaces of the multiple gate openings 43.
  • the main electrode film 47 is formed on the lower electrode film 46.
  • the main electrode film 47 may be formed by either or both of a sputtering method and a vapor deposition method.
  • the main electrode film 47 is laminated on the lower electrode film 46 and formed in the form of a film along the first wafer main surface 61, the interlayer film 41, the wall surfaces of the multiple source openings 42, and the wall surfaces of the multiple gate openings 43.
  • the second base electrode film 75 is divided into the source electrode 45, the gate electrode 50, and the gate wiring 51.
  • a mask (not shown) having a predetermined layout is formed on the main electrode film 47.
  • the mask (not shown) covers the areas where the source electrode 45, the gate electrode 50, and the gate wiring 51 are to be formed, and leaves the other areas exposed.
  • unnecessary portions of the main electrode film 47 are removed by an etching method through a mask (not shown).
  • the unnecessary portions of the main electrode film 47 are removed until the lower electrode film 46 is exposed.
  • the etching method may be either or both of a wet etching method and a dry etching method.
  • the mask (not shown) is removed after the etching process of the main electrode film 47.
  • unnecessary portions of the lower electrode film 46 are removed by an etching method using the main electrode film 47 as a mask.
  • the unnecessary portions of the lower electrode film 46 are removed until the interlayer film 41 is exposed.
  • the process of removing the lower electrode film 46 includes a process of removing the second electrode film 49 by an etching method, and a process of removing the first electrode film 48 by an etching method.
  • the etching method may be either or both of a wet etching method and a dry etching method.
  • unnecessary portions of the lower electrode film 46 may be removed by an etching method using a mask (not shown) in the etching process of the main electrode film 47.
  • a drain electrode 52 is formed on the second wafer main surface 62.
  • the drain electrode 52 may be formed by either or both of a sputtering method and a vapor deposition method. Thereafter, the wafer 60 is cut along the intended cutting lines 66 (see FIG. 13) to cut out a plurality of semiconductor devices 1. Through the steps including those described above, the semiconductor device 1 is manufactured.
  • Figure 15 is a cross-sectional view showing the semiconductor device 1 according to the first modified example.
  • Figure 16 is a cross-sectional view showing the semiconductor device 1 according to the second modified example.
  • Figure 17 is a cross-sectional view showing the semiconductor device 1 according to the third modified example.
  • Figure 18 is a cross-sectional view showing the semiconductor device 1 according to the fourth modified example.
  • the semiconductor device 1 can include the features of the fourth modification of any one of the first to fourth modifications.
  • the features of the first to fourth modifications can be combined as appropriate.
  • the semiconductor device 1 can include at least two of the features of the first to fourth modifications simultaneously in the same or different regions.
  • the semiconductor device 1 may include a gate column region 25g that crosses the bottom of the low concentration region 7a and has a bottom located within the first semiconductor region 6.
  • the semiconductor device 1 may include a source column region 25s that crosses the bottom of the low concentration region 7a and has a bottom located within the first semiconductor region 6.
  • the intermediate drift regions 30 may have portions interposed between the gate column regions 25g and the source column regions 25s within the first semiconductor region 6. In other words, the intermediate drift regions 30 may have portions formed by part of the first semiconductor region 6.
  • the semiconductor device 1 may include a gate column region 25g formed in the high concentration region 7b at a distance from the bottom of the high concentration region 7b toward the first main surface 3.
  • the semiconductor device 1 may include a source column region 25s formed in the high concentration region 7b at a distance from the bottom of the high concentration region 7b toward the first main surface 3.
  • the multiple intermediate drift regions 30 may have a portion formed by the high concentration region 7b.
  • the semiconductor device 1 does not necessarily have to simultaneously include both low concentration regions 7a and high concentration regions 7b in the second semiconductor region 7.
  • the second semiconductor region 7 may have a substantially constant n-type impurity concentration in the stacking direction (thickness direction).
  • the multiple gate column regions 25g and the multiple source column regions 25s are each formed inside the second semiconductor region 7, which has a constant n-type impurity concentration.
  • the multiple intermediate drift regions 30 are each formed by a part of the second semiconductor region 7, which has a constant n-type impurity concentration.
  • the semiconductor device 1 may include an n-type buffer region 80 interposed between the first semiconductor region 6 and the second semiconductor region 7.
  • the buffer region 80 may have an n-type impurity concentration that is lower than the n-type impurity concentration of the first semiconductor region 6 and higher than the n-type impurity concentration of the second semiconductor region 7 (low concentration region 7a).
  • the n-type impurity concentration of the buffer region 80 may be higher than the n-type impurity concentration of the high concentration region 7b, or may be lower than the n-type impurity concentration of the high concentration region 7b.
  • the buffer region 80 may extend in a layered manner in the horizontal direction, be interposed across the entire area of the first semiconductor region 6 and the second semiconductor region 7, and extend in a layered manner along the first main surface 3 (second main surface 4).
  • the buffer region 80 may be exposed from the first to fourth side surfaces 5A to 5D.
  • the buffer region 80 may be made of an n-type epitaxial layer (i.e., a SiC epitaxial layer).
  • the buffer region 80 may have a thickness equal to or less than the thickness of the second semiconductor region 7.
  • the thickness of the buffer region may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the buffer region 80 may have a value that falls within any one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the chip 2 including a SiC single crystal is used.
  • the chip 2 may include a silicon single crystal.
  • the first semiconductor region 6 may include a silicon single crystal.
  • the second semiconductor region 7 may include a silicon single crystal.
  • a p-type collector region may be formed in the surface layer of the second main surface 4 of the chip 2.
  • the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure.
  • IGBT Insulated Gate Bipolar Transistor
  • a specific configuration in this case is obtained by replacing the "source” of the MISFET structure with the "emitter” of the IGBT structure, and replacing the "drain” of the MISFET structure with the "collector” of the IGBT structure in the above description.
  • the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.
  • a semiconductor device (1) including: a chip (2) having a main surface (3); a first conductivity type (n-type) semiconductor region (7) formed on the surface of the main surface (3); a trench-type source structure (20) formed on the main surface (3) and positioned within the semiconductor region (7); and a second conductivity type (p-type) impurity region (25, 25s) formed in a region directly below the source structure (20) within the chip (2) and forming a pn junction with the semiconductor region (7).
  • a second conductivity type p-type
  • the semiconductor device (1) described in A7 further includes a contact region (35, 35s) of a second conductivity type (p-type) formed in a region along the source structure (20) within the chip (2) and having an impurity concentration higher than the impurity concentration of the body region (13).
  • a contact region (35, 35s) of a second conductivity type (p-type) formed in a region along the source structure (20) within the chip (2) and having an impurity concentration higher than the impurity concentration of the body region (13).
  • a semiconductor device (1) according to any one of A11 to A13, further comprising a gate impurity region (25, 25g) of a second conductivity type (p-type) that is formed in a region directly below the gate structure (15) in the chip (2) and forms a pn junction with the semiconductor region (7), and the impurity region (25, 25s) is formed at a distance from the gate impurity region (25, 25g).
  • a gate impurity region (25, 25g) of a second conductivity type (p-type) that is formed in a region directly below the gate structure (15) in the chip (2) and forms a pn junction with the semiconductor region (7), and the impurity region (25, 25s) is formed at a distance from the gate impurity region (25, 25g).
  • n-type first conductivity type
  • a semiconductor device (1) including: a chip (2) having a main surface (3); a semiconductor region (7) of a first conductivity type (n-type) formed on a surface layer of the main surface (3); a trench-type gate structure (15) formed on the main surface (3) and positioned within the semiconductor region (7); a trench-type source structure (20) formed on the main surface (3) at a distance from the gate structure (15) and positioned within the semiconductor region (7); a first impurity region (25, 25g) of a second conductivity type (p-type) formed in a region directly below the gate structure (15) in the chip (2); and a second impurity region (25, 25s) of a second conductivity type (p-type) formed in a region directly below the source structure (20) at a distance from the first impurity region (25, 25g) in the chip (2).
  • a method for manufacturing a semiconductor device (1) comprising the steps of: preparing a wafer (60) having a first conductivity type (n-type) semiconductor region (7) in the surface layer of a main surface (61); forming a source trench (21) in the main surface (61) so as to be positioned within the semiconductor region (7); and introducing a second conductivity type (p-type) impurity into the semiconductor region (7) through the bottom wall of the source trench (21) to form a second conductivity type (p-type) impurity region (25, 25s) that forms a pn junction with the semiconductor region (7) in the region directly below the source trench (21).
  • [B2] A method for manufacturing a semiconductor device (1) according to B1, in which the wafer (60) contains SiC.
  • [B3] A method for manufacturing a semiconductor device (1) according to B1 or B2, in which the impurity region (25, 25s) is formed at a distance from the bottom wall of the source trench (21).
  • [B4] A method for manufacturing a semiconductor device (1) according to any one of B1 to B3, in which the bottom wall of the source trench (21) is formed flat.
  • [B5] A method for manufacturing a semiconductor device (1) according to any one of B1 to B4, in which the impurity regions (25, 25s) are formed in a columnar shape extending in the thickness direction of the wafer (60) in a cross-sectional view.
  • [B6] A method for manufacturing a semiconductor device (1) according to any one of B1 to B5, in which the impurity region (25, 25s) is formed across the intermediate portion between the bottom of the semiconductor region (7) and the bottom wall of the source trench (21).
  • a second conductivity type (p-type) impurity into a surface layer of the main surface (61) to form a body region (13), and the source trench (21) is formed so as to penetrate the body region (13).
  • a second conductivity type (p-type) impurity into the semiconductor region (7) through the wall surface of the source trench (21) to form a second conductivity type (p-type) contact region (35, 35s) along the wall surface of the source trench (21) having an impurity concentration higher than the impurity concentration of the body region (13).
  • [B10] A method for manufacturing a semiconductor device (1) according to B8 or B9, in which the contact region (35, 35s) is formed to electrically connect the impurity region (25, 25s) to the body region (13).
  • a second conductivity type (p-type) impurity into the semiconductor region (7) through the bottom wall of the gate trench (16) to form a gate impurity region (25, 25g) of the second conductivity type (p-type) that forms a pn junction with the semiconductor region (7) in the region directly below the gate trench (16)
  • the impurity region (25, 25s) being formed at a distance from the gate impurity region (25, 25g).
  • [B15] A method for manufacturing a semiconductor device (1) according to B14, in which the impurity region (25, 25s) is formed to a depth equal to the depth of the gate impurity region (25, 25g).
  • [B16] A method for manufacturing a semiconductor device (1) according to B14 or B15, in which the impurity region (25, 25s) is formed with a width equal to the width of the gate impurity region (25, 25g).
  • [B18] A method for manufacturing a semiconductor device (1) according to B17, in which the gate trenches (16) are formed in a stripe pattern in a planar view, and the source trenches (21) are formed in a stripe pattern extending along the gate trenches (16) in a planar view.
  • the step of forming the impurity region (25, 25s) and the gate impurity region (25, 25s) includes a step of forming an intermediate drift region (30) of a first conductivity type (n-type) that constitutes a superjunction structure with the impurity region (25, 25s) and the gate impurity region (25, 25s) in the wafer (60).
  • Second semiconductor region First main surface 7 Second semiconductor region (semiconductor region) 13 Body region 15 Gate structure 20 Source structure 25 Column region (impurity region) 25g Gate column region (first impurity region) 25s Source column region (second impurity region) 30 intermediate drift region 35 contact region 35g gate contact region (first contact region) 35s Source contact region (second contact region) Z vertical direction (thickness direction)

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  • Insulated Gate Type Field-Effect Transistor (AREA)
PCT/JP2024/024329 2023-07-11 2024-07-04 半導体装置 Pending WO2025013769A1 (ja)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140124855A1 (en) * 2012-11-05 2014-05-08 François Hébert Charged balanced devices with shielded gate trench
JP2020136472A (ja) * 2019-02-19 2020-08-31 ローム株式会社 半導体装置
JP2021044517A (ja) * 2019-09-13 2021-03-18 株式会社東芝 半導体装置、半導体装置の製造方法、インバータ回路、駆動装置、車両、及び、昇降機
JP2021129020A (ja) * 2020-02-13 2021-09-02 株式会社デンソー 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140124855A1 (en) * 2012-11-05 2014-05-08 François Hébert Charged balanced devices with shielded gate trench
JP2020136472A (ja) * 2019-02-19 2020-08-31 ローム株式会社 半導体装置
JP2021044517A (ja) * 2019-09-13 2021-03-18 株式会社東芝 半導体装置、半導体装置の製造方法、インバータ回路、駆動装置、車両、及び、昇降機
JP2021129020A (ja) * 2020-02-13 2021-09-02 株式会社デンソー 半導体装置

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