WO2025010773A1 - 显示装置 - Google Patents

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Publication number
WO2025010773A1
WO2025010773A1 PCT/CN2023/110126 CN2023110126W WO2025010773A1 WO 2025010773 A1 WO2025010773 A1 WO 2025010773A1 CN 2023110126 W CN2023110126 W CN 2023110126W WO 2025010773 A1 WO2025010773 A1 WO 2025010773A1
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WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
gate driving
sub
pixels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2023/110126
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English (en)
French (fr)
Inventor
陈涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to DE112023000084.0T priority Critical patent/DE112023000084B4/de
Priority to US18/552,938 priority patent/US20250087164A1/en
Publication of WO2025010773A1 publication Critical patent/WO2025010773A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present application relates to the field of display technology, and in particular to a display device.
  • gate drive units with the same function and structure are arranged in series to achieve stage transmission, and gate drive units with different functions are arranged in parallel, such as EM(m) ⁇ EM(m+3) and Pscan(m) ⁇ Pscan(m+3) as shown in FIG1.
  • EM(m) ⁇ EM(m+3) and Pscan(m) ⁇ Pscan(m+3) as shown in FIG1.
  • the number of gate drive units that can achieve different functions required by pixel drive circuits has also begun to increase. If the gate drive units that achieve different functions continue to use the layout shown in FIG1, the border area of the display panel will become wider, which is not conducive to the display panel to achieve a narrow border design.
  • the embodiments of the present application provide a display device, which is conducive to realizing a narrow frame design for a display panel.
  • the embodiment of the present application provides a display device, including a display panel and a plurality of gate driving units.
  • the display panel includes a plurality of sub-pixels, each of which includes a light-emitting device and a pixel driving circuit electrically connected to the light-emitting device, and the pixel driving circuit includes a plurality of transistors.
  • the plurality of gate driving units at least include a first gate driving unit and a second gate driving unit electrically connected to the plurality of sub-pixels and sharing a clock signal and a power signal;
  • the first gate driving unit includes a plurality of cascaded first gate driving circuits, the first gate driving unit outputs a plurality of first scanning signals to the plurality of sub-pixels according to a first start signal, the clock signal and the power signal;
  • the second gate driving unit includes a plurality of cascaded second gate driving circuits, the second gate driving unit outputs a plurality of second scanning signals to the plurality of sub-pixels according to a second start signal, the clock signal and the power signal.
  • one of the transistors included in each of the sub-pixels is turned on according to the corresponding first scanning signal, and another of the transistors included in each of the sub-pixels is turned on according to the corresponding second scanning signal; the plurality of first gate driving circuits and the plurality of second gate driving circuits are arranged alternately in the first direction.
  • the embodiment of the present application provides a display device, including a display panel and a plurality of gate driving units, wherein the plurality of gate driving units at least include a first gate driving unit and a second gate driving unit electrically connected to a plurality of sub-pixels of the display panel and sharing a clock signal and a power signal; the first gate driving unit and the second gate driving unit respectively receive a first start signal and a second start signal and cooperate with the clock signal and the power signal to output a plurality of first scanning signals and a second scanning signal to a plurality of sub-pixels, so that a transistor included in each sub-pixel is turned on according to the corresponding first scanning signal, and another transistor included in each sub-pixel is turned on according to the corresponding second scanning signal; the first gate driving unit includes a plurality of cascaded first gate driving circuits, and the second gate driving unit includes a plurality of cascaded second gate driving circuits arranged alternately in the first direction.
  • FIG1 is a schematic diagram of a configuration structure of a gate driving unit in the prior art
  • FIGS. 2A to 2C are schematic diagrams of the structure of a display device provided in an embodiment of the present application.
  • 3A-3B are schematic diagrams of the structure of a gate driving circuit provided in an embodiment of the present application.
  • FIGS. 4A to 4C are schematic diagrams of the structure of a pixel driving circuit provided in an embodiment of the present application.
  • 5A to 5C are timing diagrams provided in embodiments of the present application.
  • FIG. 2A to FIG. 2C are schematic diagrams of the structure of a display device provided in an embodiment of the present application; an embodiment of the present application provides a display device, including a display panel and a plurality of gate driving units.
  • the display panel includes a plurality of sub-pixels Pi, each of which includes a light-emitting device L and a pixel driving circuit electrically connected to the light-emitting device L, and the pixel driving circuit is used to drive the corresponding light-emitting device L to emit light.
  • the display panel includes a self-luminous display panel.
  • the sub-pixels Pi include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B; and the light-emitting device L includes an organic light-emitting diode, a sub-millimeter light-emitting diode, a micro light-emitting diode, and the like.
  • the pixel driving circuit comprises a plurality of transistors.
  • the plurality of gate driving units at least include a first gate driving unit 10 and a second gate driving unit 20 which are electrically connected to the plurality of sub-pixels Pi and share a clock signal and a power signal.
  • the display device includes a first clock signal line CKL1, a second clock signal line CKL2, a first power line VL1, and a second power line VL2 electrically connected to the first gate driving unit 10 and the second gate driving unit 20.
  • the first clock signal line CKL1, the second clock signal line CKL2, the first power line VL1, and the second power line VL2 all extend along a first direction.
  • the first clock signal line CKL1 transmits a first clock signal CK
  • the second clock signal line CKL2 transmits a second clock signal XCK.
  • the clock signal includes a first clock signal CK and a second clock signal XCK.
  • the first power line VL1 transmits a first power signal VGH
  • the second power line VL2 transmits a second power signal VGL.
  • the power signal includes a first power signal VGH and a second power signal VGL.
  • the first clock signal CK and the second clock signal XCK are in opposite phases, and the voltage corresponding to the first power signal VGH is greater than the voltage corresponding to the second power signal VGL.
  • the first gate driving unit 10 includes a plurality of cascaded first gate driving circuits 101 .
  • the first gate driving unit 10 outputs a plurality of first scanning signals Scan1 to a plurality of sub-pixels Pi according to a first start signal STV1 , a clock signal, and a power signal.
  • the second gate driving unit 20 includes a plurality of cascaded second gate driving circuits 201 .
  • the second gate driving unit 20 outputs a plurality of second scanning signals Scan2 to a plurality of sub-pixels Pi according to a second start signal STV2 , a clock signal, and a power signal.
  • a transistor included in each sub-pixel Pi is turned on according to the corresponding first scanning signal Scan1, and another transistor included in each sub-pixel Pi is turned on according to the corresponding second scanning signal Scan2; a plurality of first gate driving circuits 101 and a plurality of second gate driving circuits 201 are arranged alternately in the first direction.
  • the first gate driving circuits 101 and the second gate driving circuits 201 electrically connected to transistors with different functions in the pixel driving circuits be arranged alternately in the first direction, the first gate driving unit 10 and the second gate driving unit 20 without cascade relationship exhibit series characteristics, so as to improve the problem that the cascaded gate driving circuits in the prior art are arranged in series, while the gate driving circuits without cascade relationship are arranged in parallel, resulting in a larger border width of the display panel, which is not conducive to the design of a narrow border for the display device.
  • the gate driving circuits alternately arranged in the first direction and not in cascade relationship have the same circuit topology structure, such as the first gate driving circuit 101 and the second gate driving circuit 201 have the same circuit topology structure.
  • the circuit topologies of the gate drive circuits that are alternately arranged in the first direction and have no cascade relationship may also be different.
  • the different circuit topologies include similar circuit topologies (e.g., the second gate drive circuit 201 is based on the first gate drive circuit 101, with at least one transistor or at least one capacitor reduced or increased) and dissimilar circuit topologies (i.e., the topology of the first gate drive circuit 101 is completely different from the topology of the second gate drive circuit 201).
  • FIG. 3A to FIG. 3B are schematic diagrams of the structure of a gate driving circuit provided in an embodiment of the present application, and the gate driving circuit includes a first transistor T1 to a tenth transistor T10 and a first capacitor C1 to a third capacitor C3.
  • the input end of the first transistor T1 is electrically connected to the second power line VL2, the output end of the first transistor T1 is electrically connected to the control end of the second transistor T2, the control end of the third transistor T3 and the output end of the fourth transistor T4, the output end of the second transistor T2 is electrically connected to the input end of the fifth transistor T5, the input end of the third transistor T3 is electrically connected to the first power line VL1, the output end of the third transistor T3 is electrically connected to the output end of the sixth transistor T6, the input end of the seventh transistor T7 receives a start signal (such as the first start signal STV1, the second start signal STV2 or the scan signal Scan(m-1) output by the upper gate driving circuit, where m ⁇ 1), and the seventh
  • the output end of the transistor T7 is electrically connected to the control end of the fourth transistor T4, the control end of the sixth transistor T6, the control end of the eighth transistor T8 and the control end of the ninth transistor T9, the input end of the eighth transistor T8 is electrically
  • the first capacitor C1 is connected in series between the output end of the sixth transistor T6 and the control end of the sixth transistor T6, the second capacitor C2 is connected in series between the output end of the second transistor T2 and the control end of the second transistor T2, and the third capacitor C3 is connected in series between the input end of the tenth transistor T10 and the control end of the tenth transistor T10.
  • the control end of the first transistor T1 is electrically connected to the first clock signal line CKL1
  • the input end of the second transistor T2 is electrically connected to the second clock signal line CKL2
  • the input end of the fourth transistor T4 is electrically connected to the first clock signal line CKL1
  • the control end of the fifth transistor T5 is electrically connected to the second clock signal line CKL2
  • the input end of the sixth transistor T6 is electrically connected to the second clock signal line CKL2.
  • the control end of the first transistor T1 is electrically connected to the second clock signal line CKL2
  • the input end of the second transistor T2 is electrically connected to the first clock signal line CKL1
  • the input end of the fourth transistor T4 is electrically connected to the second clock signal line CKL2
  • the control end of the fifth transistor T5 is electrically connected to the first clock signal line CKL1
  • the input end of the sixth transistor T6 is electrically connected to the first clock signal line CKL1.
  • the gate drive circuit also includes an eleventh transistor T11 and a twelfth transistor T12, the control end of the eleventh transistor and the control end of the twelfth transistor T12 are electrically connected to the second power line VL2, the input end and the output end of the eleventh transistor T11 are electrically connected between the output end of the first transistor T1 and the control end of the second transistor T2, the input end of the twelfth transistor T12 is electrically connected to the control end of the fourth transistor T4, the output end of the seventh transistor T7 and the control end of the eighth transistor T8, and the output end of the twelfth transistor T12 is electrically connected to the control end of the sixth transistor T6 and the control end of the ninth transistor T9.
  • the gate driving circuit also includes a thirteenth transistor T13, a control end of the thirteenth transistor T13 is electrically connected to the reset signal line CL, an input end of the thirteenth transistor T13 is electrically connected to the first power line VL1, and an output end of the thirteenth transistor T13 is electrically connected to the output end of the seventh transistor T7.
  • the gate driving circuit further includes fourteenth to sixteenth transistors T14 to T16.
  • the control end of the sixth transistor T6 is electrically connected to the control end of the sixteenth transistor T16
  • the input end of the fourteenth transistor T14 is electrically connected to the input end of the seventh transistor T7
  • the output end of the fourteenth transistor T14 is electrically connected to the input end of the fifteenth transistor T15
  • the control end of the fifteenth transistor T15 is electrically connected to the second power line VL2
  • the output end of the fifteenth transistor T15 is electrically connected to the control end of the sixteenth transistor T16
  • the input end of the sixteenth transistor T16 is electrically connected to the control end of the sixteenth transistor T16
  • the output end of the sixteenth transistor T16 is electrically connected to the control end of the ninth transistor T9.
  • the control end of the fourteenth transistor T14 is electrically connected to the first clock signal line CKL1; in the n+1th stage gate driving circuit, the control end of the fourteenth transistor T14 is electrically connected to the second clock signal line CKL2.
  • first gate driving circuit 101 and the second gate driving circuit 201 can be configured using the topological structure of the gate driving circuit shown in FIG. 3A to FIG. 3B , or other forms of circuit topological structures.
  • FIGS. 4A to 4C are schematic diagrams of the structure of a pixel driving circuit provided in an embodiment of the present application, wherein the plurality of transistors include a driving transistor Tdr, a data transistor Tda, a compensation transistor Tc, a first reset transistor Ti1, a second reset transistor Ti2 and a light emitting control transistor.
  • the plurality of transistors include a driving transistor Tdr, a data transistor Tda, a compensation transistor Tc, a first reset transistor Ti1, a second reset transistor Ti2 and a light emitting control transistor.
  • the control terminal of the driving transistor Tdr is electrically connected to the first node N1 , the input terminal of the driving transistor Tdr is electrically connected to the second node N2 , and the output terminal of the driving transistor Tdr is electrically connected to the third node N3 .
  • An input terminal of the data transistor Tda is electrically connected to the corresponding data line DL, and an output terminal of the data transistor Tda is electrically connected to the second node N2.
  • An input terminal of the compensation transistor Tc is electrically connected to the second node N2 , and an output terminal of the compensation transistor Tc is electrically connected to an output terminal of the driving transistor Tdr.
  • An input terminal of the first reset transistor Ti1 is electrically connected to the corresponding first reset line ViL1 , and an output terminal of the first reset transistor Ti1 is electrically connected to the first node N1 .
  • An input terminal of the second reset transistor Ti2 is electrically connected to the corresponding second reset line ViL2 , and an output terminal of the second reset transistor Ti2 is electrically connected to the third node N3 .
  • the input terminal and the output terminal of the light emitting control transistor are connected in series with the driving transistor Tdr between the first voltage terminal VDD and the light emitting device L.
  • the light emitting control transistor includes a first light emitting control transistor Te1 and a second light emitting control transistor Te2, the input terminal and the output terminal of the first light emitting control transistor Te1 are electrically connected between the first voltage terminal VDD and the second node N2, and the input terminal and the output terminal of the second light emitting control transistor Te1 are electrically connected between the output terminal of the driving transistor Tdr and the third node N3.
  • the cathode of the light emitting device L is electrically connected to the second voltage terminal VSS.
  • the compensation transistor Tc and the first reset transistor Ti1 may be silicon transistors or oxide transistors.
  • the gate driving circuit further includes a third reset transistor Ti3, an input end of the third reset transistor Ti3 is electrically connected to the corresponding third reset line ViL3, and an output end of the third reset transistor Ti3 is electrically connected to the second node N2.
  • control end of the third reset transistor Ti3 may be electrically connected to the control end of the second reset transistor Ti2, so that the second reset transistor Ti2 and the third reset transistor Ti3 are synchronously turned on or off, as shown in FIG. 4A to FIG. 4B .
  • control ends of the first reset transistor Ti1 and the data transistor Tda can be electrically connected to gate driving circuits of different levels of a gate driving unit, and the control ends of the compensation transistor Tc and the data transistor Tda can be electrically connected to gate driving circuits of the same level of a gate driving unit, as shown in Figures 4A and 4C.
  • the pixel driving circuit further includes a storage capacitor Cst, and the storage capacitor Cst is connected in series between the first voltage terminal VDD and the control terminal of the driving transistor Tdr.
  • the first gate driving unit 10 and the second gate driving unit 20 are electrically connected to the compensation transistors Tc, the first reset transistor Ti1 , the second reset transistor Ti2 , the third reset transistor Ti3 and two of the light emitting control transistors of the plurality of sub-pixels Pi.
  • one of the first gate driving unit 10 and the second gate driving unit 20 is electrically connected to the control end of the compensation transistor Tc of multiple sub-pixels Pi
  • the other of the first gate driving unit 10 and the second gate driving unit 20 is electrically connected to the control end of the first reset transistor Ti1 of multiple sub-pixels Pi
  • the other of the first gate driving unit 10 and the second gate driving unit 20 is electrically connected to the control end of the second reset transistor Ti2 of multiple sub-pixels Pi
  • the other of the first gate driving unit 10 and the second gate driving unit 20 is electrically connected to the control end of the third reset transistor Ti3 of multiple sub-pixels Pi
  • the other of the first gate driving unit 10 and the second gate driving unit 20 is electrically connected to the control end of the light emitting control transistor of multiple sub-pixels Pi.
  • one of the first gate driving unit 10 and the second gate driving unit 20 is electrically connected to the control end of the first reset transistor Ti1 of multiple sub-pixels Pi
  • the other of the first gate driving unit 10 and the second gate driving unit 20 is electrically connected to the control end of the second reset transistor Ti2 of multiple sub-pixels Pi
  • the other of the first gate driving unit 10 and the second gate driving unit 20 is electrically connected to the control end of the third reset transistor Ti3 of multiple sub-pixels Pi
  • the other of the first gate driving unit 10 and the second gate driving unit 20 is electrically connected to the control end of the light-emitting control transistor of multiple sub-pixels Pi.
  • one of the first gate driving unit 10 and the second gate driving unit 20 is electrically connected to the control end of the second reset transistor Ti2 of multiple sub-pixels Pi
  • the other of the first gate driving unit 10 and the second gate driving unit 20 is electrically connected to the control end of the third reset transistor Ti3 of multiple sub-pixels Pi
  • the other of the first gate driving unit 10 and the second gate driving unit 20 is electrically connected to the control end of the light emitting control transistor of multiple sub-pixels Pi.
  • one of the first gate driving unit 10 and the second gate driving unit 20 is electrically connected to the control end of the third reset transistor Ti3 of multiple sub-pixels Pi, and the other of the first gate driving unit 10 and the second gate driving unit 20 is electrically connected to the control end of the light emitting control transistor of multiple sub-pixels Pi.
  • each first gate driving circuit 101 is electrically connected to a plurality of sub-pixels Pi in n adjacent rows; each second gate driving circuit 201 is electrically connected to a plurality of sub-pixels Pi in n adjacent rows, so that the first gate driving circuit 101 and the second gate driving circuit 201 can be electrically connected to n rows of sub-pixels Pi at the same time, thereby reducing the number of first gate driving circuits 101 and second gate driving circuits 201 included in the display device to reduce power consumption.
  • n is greater than 1.
  • n is equal to 2, 3, 4, 5, 6, 7, 8, etc.
  • the first-level first gate driving circuit 101 and the first-level second gate driving circuit 201 are both electrically connected to a plurality of sub-pixels Pi located in the first to fourth rows
  • the second-level first gate driving circuit 101 and the second-level second gate driving circuit 201 are both electrically connected to a plurality of sub-pixels Pi located in the fifth to eighth rows, and so on, to obtain a corresponding relationship between the plurality of sub-pixels Pi located in other rows and the first gate driving circuit 101 and the second gate driving circuit 201.
  • a plurality of sub-pixels Pi located in the m+nth row to the m+n+3th row are electrically connected to a first gate driving circuit 101 and a second gate driving circuit 201 .
  • the first gate driving unit 10 is electrically connected to the control end of the light emitting control transistor of multiple sub-pixels Pi
  • the second gate driving unit 20 is electrically connected to the control end of the second reset transistor Ti2 of multiple sub-pixels Pi
  • the control end of the third reset transistor Ti3 is electrically connected to the control end of the second reset transistor Ti2, so as to control the light emitting control transistors of multiple sub-pixels Pi to be turned on or off through multiple first gate driving circuits 101, and control the second reset transistor Ti2 and the third reset transistor Ti3 to be turned on or off through multiple second gate driving circuits 201.
  • each first gate driving circuit 101 is electrically connected to the control end of the light-emitting control transistor of multiple sub-pixels Pi in four adjacent rows; each second gate driving circuit 201 is electrically connected to the control end of the second reset transistor Ti2 and the control end of the third reset transistor Ti3 of multiple sub-pixels Pi in four adjacent rows.
  • the multiple gate driving units also include a third gate driving unit 30 and a fourth gate driving unit 40 that share a common clock signal and a power signal.
  • the third gate driving unit 30 outputs multiple third scanning signals Nscan1 to multiple sub-pixels Pi according to the third start signal STV3, the clock signal and the power signal;
  • the fourth gate driving unit 40 outputs multiple fourth scanning signals Nscan2 to multiple sub-pixels Pi according to the fourth start signal STV4, the clock signal and the power signal.
  • the third gate driving unit 30 includes a plurality of cascaded third gate driving circuits 301
  • the fourth gate driving unit 40 includes a plurality of cascaded fourth gate driving circuits 401
  • the plurality of third gate driving circuits 301 and the plurality of fourth gate driving circuits 401 are alternately arranged in the first direction.
  • the first gate driving unit 10 is arranged in parallel with the third gate driving unit 30, and the second gate driving unit 20 is arranged in parallel with the fourth gate driving unit 40.
  • the compensation transistor Tc and the first reset transistor Ti1 include oxide transistors
  • the third gate driving unit 30 is electrically connected to the control end of the compensation transistor Tc of multiple sub-pixels Pi
  • the fourth gate driving unit 40 is electrically connected to the control end of the first reset transistor Ti1 of multiple sub-pixels Pi.
  • each third gate driving circuit 301 is electrically connected to the control end of the compensation transistor Tc of multiple sub-pixels Pi in four adjacent rows; each fourth gate driving circuit 401 is electrically connected to the control end of the first reset transistor Ti1 of multiple sub-pixels Pi in four adjacent rows.
  • the first gate driving unit 10 is electrically connected to the control end of the second reset transistor Ti2 of the plurality of sub-pixels Pi
  • the second gate driving unit 20 is electrically connected to the control end of the third reset transistor Ti3 of the plurality of sub-pixels Pi.
  • each first gate driving circuit 101 is electrically connected to the control end of the second reset transistor Ti2 of multiple sub-pixels Pi in four adjacent rows; each second gate driving circuit 201 is electrically connected to the control end of the third reset transistor Ti3 of multiple sub-pixels Pi in four adjacent rows.
  • the multiple gate driving units also include a fifth gate control unit.
  • the fifth gate control unit includes multiple fifth gate driving circuits.
  • Each fifth gate driving circuit 501 is electrically connected to the control end of the light-emitting control transistor of multiple sub-pixels Pi in two adjacent rows.
  • the multiple gate driving units also include a sixth gate driving unit 60, and the sixth gate driving unit 60 includes multiple cascaded sixth gate driving circuits 601; wherein each sixth gate driving circuit 601 is electrically connected to the control end of the data transistor Tda of multiple sub-pixels Pi located in the same row.
  • each sixth gate driving circuit 601 is electrically connected to the control end of the first reset transistor Ti1 of multiple sub-pixels Pi in the same row, and the control end of the compensation transistor Tc is electrically connected to the control end of the data transistor Tda, as shown in Figures 2A and 2C and Figures 4A and 4C.
  • the display panel includes a first sub-area A1 and a second sub-area A2 located on opposite sides of a plurality of sub-pixels Pi; wherein the first gate driving unit 10 and the second gate driving unit 20 are located in the first sub-area A1, and the sixth gate driving unit 60 is located in at least one of the first sub-area A1 and the second sub-area A2.
  • the first gate driving unit 10 and the second gate driving unit 20 are located in the first sub-area A1
  • the sixth gate driving unit 60 is located in the second sub-area A2 .
  • the first gate driving unit 10, the second gate driving unit 20, the third gate driving unit 30 and the fourth gate driving unit 40 are located in the first sub-area A1
  • the first gate driving unit 10 and the second gate driving unit 20 are located on the side of the third gate driving unit 30 and the fourth gate driving unit 40 close to the sixth gate driving unit 60
  • the sixth gate driving unit 60 is located in the second sub-area A2.
  • the first gate driving unit 10 and the second gate driving unit 20 are located in the first sub-area A1
  • the sixth gate driving unit 60 is located in the first sub-area A1 and the second sub-area A2
  • the fifth gate driving unit 50 is located in the second sub-area A2
  • the fifth gate driving unit 50 is located on the side of the sixth gate driving unit 60 away from the first gate driving unit 10 and the second gate driving unit 20
  • the first gate driving unit 10 and the second gate driving unit 20 are located on the side of the sixth gate driving unit 60 away from the fifth gate driving unit 50.
  • 5A to 5C are timing diagrams provided in the embodiment of the present application, taking the example that each first gate driving circuit 101 and each second gate driving circuit 201 are electrically connected to four adjacent rows of sub-pixels Pi as an example, the working principle of the display device is described.
  • the X-th level first scanning signal Scan1(X) output by the X-th level first gate driving circuit 101 is at a high level, so that the light-emitting control transistors of the sub-pixels Pi located in the m-th row to the m+3-th row are cut off, and the m-1-th level sixth gate driving circuit 601 outputs the m-1-th level scanning signal Pscan(m-1) is at a low level, so that the first reset transistor Ti1 of the sub-pixel Pi located in the m-th row is turned on, and the first reset signal transmitted by the first reset line ViL1 resets the gate of the driving transistor Tdr.
  • the m-th level scanning signal Pscan(m) output by the m-th level sixth gate driving circuit 601 is at a low level, so that the data transistor Tda and the compensation transistor Tc of the sub-pixel Pi located in the m-th row are turned on, and the data signal transmitted by the data line DL is written into the gate of the driving transistor Tdr and the storage capacitor Cst; the first reset transistor Ti1 of the sub-pixel Pi located in the m+1-th row is turned on, and the first reset signal transmitted by the first reset line ViL1 resets the gate of the driving transistor Tdr.
  • the m+1th level scanning signal Pscan(m+1) output by the m+1th level sixth gate driving circuit 601 is at a low level, so that the data transistor Tda and the compensation transistor Tc of the sub-pixel Pi located in the m+1th row are turned on, and the data signal transmitted by the data line DL is written into the gate of the driving transistor Tdr and the storage capacitor Cst; the first reset transistor Ti1 of the sub-pixel Pi located in the m+2th row is turned on, and the first reset signal transmitted by the first reset line ViL1 resets the gate of the driving transistor Tdr; afterward, the m+2th level scanning signal Pscan(m+2) output by the m+2th level sixth gate driving circuit 601 is at a low level, so that the data transistor Tda and the compensation transistor Tc of the sub-pixel Pi located in the m+2th row are turned on, and the data line DL transmits the data signal.
  • the data signal is written into the gate of the driving transistor Tdr and the storage capacitor Cst; the first reset transistor Ti1 of the sub-pixel Pi located in the m+3th row is turned on, and the first reset signal transmitted by the first reset line ViL1 resets the gate of the driving transistor Tdr; finally, the m+3th level scanning signal Pscan(m+3) output by the m+3th level sixth gate driving circuit 601 is low, so that the data transistor Tda and the compensation transistor Tc of the sub-pixel Pi located in the m+3th row are turned on, and the data signal transmitted by the data line DL is written into the gate of the driving transistor Tdr and the storage capacitor Cst; the first reset transistor Ti1 of the sub-pixel Pi located in the m+4th row is turned on, and the first reset signal transmitted by the first reset line ViL1 resets the gate of the driving transistor Tdr.
  • the second scanning signal Scan2(X) of the Xth stage output by the second gate driving circuit 201 of the Xth stage has a low level
  • the second reset transistor Ti2 and the third reset transistor Ti3 of the sub-pixels located in the mth row to the m+3th row are turned on
  • the second reset signal transmitted by the second reset line ViL2 resets the third node N3
  • the third reset signal transmitted by the third reset line ViL3 applies a bias voltage to the second node N2, thereby improving the hysteresis effect of the driving transistor Tdr and improving the flicker.
  • the sub-pixels Pi located in the m+4th row to the m+7th row perform the same operation as the sub-pixels Pi located in the mth row to the m+3th row in the second stage t2 in the third stage t3.
  • the Xth-stage first scanning signal Scan1(X) output by the Xth-stage first gate driving circuit 101 is at a low level, so that the light-emitting control transistors of the sub-pixels Pi located in the mth to m+3th rows are turned on, and the light-emitting devices L emit light.
  • the display device may be displayed using a variable refresh rate.
  • the display panel includes a write frame WF and a hold frame HF when displaying, wherein the write frame WF may include a first stage t1 to a fourth stage t4.
  • the hold frame HF the first scan signal Scan1 output by the first gate drive circuit 101 has a high level state and a low level state
  • the second scan signal Scan2 output by the second gate drive circuit 201 has a high level state and a low level state
  • the scan signal Pscan output by the sixth gate drive unit 60 has a low level state.
  • a fifth stage t5 in the hold frame HF to reset the third node N3 of the sub-pixel Pi of the corresponding row and apply a bias voltage to the second node N2.
  • the Xth-level first scanning signal Scan1(X) output by the Xth-level first gate driving circuit 101 is at a high level, so that the light-emitting control transistors of the sub-pixels Pi located in the mth row to the m+3th row are cut off, and the Xth-level second scanning signal Scan2(X) output by the Xth-level second gate driving circuit 201 has a low level, and the second reset transistor Ti2 and the third reset transistor Ti3 of the sub-pixels Pi located in the mth row to the m+3th row are turned on, and the second reset signal transmitted by the second reset line ViL2 resets the third node N3, and the third reset signal transmitted by the third reset line ViL3 applies a bias voltage to the second node N2,
  • the X-th level first scanning signal Scan1(X) output by the X-th level first gate driving circuit 101 is at a high level, so that the light-emitting control transistors of the sub-pixels Pi located in the m-th row to the m+3-th row are cut off;
  • the X-th level fourth scanning signal Nscan2(X) output by the X-th level fourth gate driving circuit 401 is at a low level, so that the first reset transistors Ti1 of the sub-pixels Pi located in the m-th row to the m+3-th row are turned on, and the first reset signal transmitted by the first reset line ViL1 resets the gates of the driving transistors Tdr of the sub-pixels Pi located in the m-th row to the m+3-th row.
  • the X-th level third scanning signal Nscan1(X) output by the X-th level third gate driving circuit 301 is at a high level, so that the compensation transistor Tc of the sub-pixel Pi located in the m-th row to the m+3-th row is turned on;
  • the m-th level sixth gate driving circuit 601 outputs the m-th level scanning signal Pscan(m) at a low level, so that the data transistor Tda of the sub-pixel Pi located in the m-th row is turned on, and the data signal transmitted by the data line DL is written into the gate of the driving transistor Tdr and the storage capacitor Cst.
  • the m+1th level scanning signal Pscan(m+1) output by the m+1th level sixth gate driving circuit 601 is at a low level, so that the data transistor Tda of the sub-pixel Pi located in the m+1th row is turned on, and the data signal transmitted by the data line DL is written into the gate of the driving transistor Tdr and the storage capacitor Cst;
  • the m+2th level scanning signal Pscan(m+2) output by the m+2th level sixth gate driving circuit 601 is at a low level, so that the data transistor Tda of the sub-pixel Pi located in the m+2th row is turned on, and the data signal transmitted by the data line DL is written into the gate of the driving transistor Tdr and the storage capacitor Cst;
  • the m+3th level scanning signal Pscan(m+3) output by the m+3th level sixth gate driving circuit 601 is at a low level, so that the data transistor Tda of the sub-pixel Pi located in the m+1th row is
  • the fourth scanning signal Nscan2(X+1) of the X+1th level output by the fourth gate driving circuit 401 of the X+1th level is at a low level, so that the first reset transistor Ti1 of the sub-pixel Pi located in the m+4th to m+7th rows is turned on, and the first reset signal transmitted by the first reset line ViL1 resets the gate of the driving transistor Tdr of the sub-pixel Pi located in the m+4th to m+7th rows.
  • the second scanning signal Scan2(X) of the Xth stage output by the second gate driving circuit 201 of the Xth stage has a low level
  • the second reset transistor Ti2 and the third reset transistor Ti3 of the sub-pixel Pi located in the mth row to the m+3th row are turned on
  • the second reset signal transmitted by the second reset line ViL2 resets the third node N3
  • the third reset signal transmitted by the third reset line ViL3 applies a bias voltage to the second node N2, thereby improving the hysteresis effect of the driving transistor Tdr and improving the flicker.
  • the sub-pixel Pi located in the m+4th row to the m+7th row performs the same operation as the sub-pixel Pi located in the mth row to the m+3th row in the second stage t2 in the third stage t3.
  • the Xth-stage first scanning signal Scan1(X) output by the Xth-stage first gate driving circuit 101 is at a low level, so that the light-emitting control transistors of the sub-pixels Pi located in the mth to m+3th rows are turned on, and the light-emitting devices L emit light.
  • the first scanning signal Scan1 output by the first gate driving circuit 101 has a high level state and a low level state
  • the second scanning signal Scan2 output by the second gate driving circuit 201 has a high level state and a low level state
  • the scanning signals output by the third gate driving unit 30 and the fourth gate driving unit 40 have a low level state
  • the scanning signal output by the sixth gate driving unit 60 has a low level state.
  • the holding frame HF also has a fifth stage t5 to reset the third node N3 of the sub-pixel Pi of the corresponding row and apply a bias voltage to the second node N2.
  • the Xth-level first scanning signal Scan1(X) output by the Xth-level first gate driving circuit 101 is at a high level, so that the light-emitting control transistors of the sub-pixels Pi located in the mth row to the m+3th row are cut off, and the Xth-level second scanning signal Scan2(X) output by the Xth-level second gate driving circuit 201 has a low level, and the second reset transistor Ti2 and the third reset transistor Ti3 of the sub-pixels Pi located in the mth row to the m+3th row are turned on, and the second reset signal transmitted by the second reset line ViL2 resets the third node N3, and the third reset signal transmitted by the third reset line ViL3 applies a bias voltage to the second node N2, thereby improving the hysteresis effect of the driving transistor Tdr and improving the flicker.
  • the Y-th level scanning signal EM(Y) output by the Y-th level fifth gate driving circuit 501 is at a high level, so that the light-emitting control transistors of the sub-pixels Pi located in the m-th row to the m+1-th row are cut off;
  • the m-1-th level scanning signal Pscan(m-1) output by the m-1-th level sixth gate driving circuit 601 is at a low level, so that the first reset transistor Ti1 of the sub-pixel Pi located in the m-th row is turned on, and the first reset signal transmitted by the first reset line ViL1 resets the gate of the driving transistor Tdr.
  • the Y+1th level scanning signal EM(Y+1) output by the fifth gate driving circuit 501 of the Y+1th level is at a high level, so that the light-emitting control transistors of the sub-pixels Pi located in the m+2th to m+3th rows are cut off;
  • the mth level scanning signal Pscan(m) output by the sixth gate driving circuit 601 of the mth level is at a low level, so that the data transistor Tda and the compensation transistor Tc of the sub-pixel Pi located in the mth row are turned on, and the data signal transmitted by the data line DL is written into the gate of the driving transistor Tdr and the storage capacitor Cst;
  • the first reset transistor Ti1 of the sub-pixel Pi located in the m+1th row is turned on, and the first reset signal transmitted by the first reset line ViL1 resets the gate of the driving transistor Tdr.
  • the m+1th level scanning signal Pscan(m+1) output by the m+1th level sixth gate driving circuit 601 is at a low level, so that the data transistor Tda and the compensation transistor Tc of the sub-pixel Pi located in the m+1th row are turned on, and the data signal transmitted by the data line DL is written into the gate of the driving transistor Tdr and the storage capacitor Cst; the first reset transistor Ti1 of the sub-pixel Pi located in the m+2th row is turned on, and the first reset signal transmitted by the first reset line ViL1 resets the gate of the driving transistor Tdr; afterwards, the m+2th level scanning signal Pscan(m+2) output by the m+2th level sixth gate driving circuit 601 is at a low level, so that the data transistor Tda and the compensation transistor Tc of the sub-pixel Pi located in the m+2th row are turned on, and the data signal transmitted by the data line DL is written into the gate of the driving transistor Tdr and the storage capacitor C
  • the first scanning signal Scan1(X) of the Xth stage outputted by the first gate driving circuit 101 of the Xth stage has a low level
  • the second reset transistor Ti2 of the sub-pixel Pi located in the m+2th row to the m+3th row is turned on
  • the second scanning signal Scan2(X) of the Xth stage outputted by the second gate driving circuit 201 of the Xth stage has a low level
  • the third reset transistor Ti3 of the sub-pixel Pi located in the m+2th row to the m+3th row is turned on
  • the second reset signal transmitted by the second reset line ViL2 resets the third node N3
  • the third reset signal transmitted by the third reset line ViL3 applies a bias voltage to the second node N2, thereby improving the hysteresis effect of the driving transistor Tdr and improving the flicker.
  • the sub-pixels Pi located in the m+4th row to the m+7th row perform the same operation in the third stage t3 as the sub-pixels Pi located in the mth row to the m+3th row in the second stage t2.
  • the Y-th level scanning signal EM(Y) output by the Y-th level fifth gate driving circuit 501 is at a low level, so that the light-emitting control transistors of the sub-pixels Pi located in the m-th row to the m+3-th row are turned on, and the light-emitting device L emits light.
  • the first scanning signal Scan1 output by the first gate driving circuit 101 has a high level state and a low level state
  • the second scanning signal Scan2 output by the second gate driving circuit 201 has a high level state and a low level state
  • the scanning signal EM output by the fifth gate driving unit 50 has a high level state and a low level state
  • the scanning signal Pscan output by the sixth gate driving unit 60 has a low level state.
  • the holding frame HF also has a fifth stage t5 to reset the third node N3 of the sub-pixel Pi of the corresponding row and apply a bias voltage to the second node N2.
  • the Y-th level scanning signal EM(Y) output by the Y-th level fifth gate driving circuit 501 is at a high level, so that the light-emitting control transistors of the sub-pixels Pi located in the m-th row to the m+3-th row are cut off, and the X-th level first scanning signal Scan1(X) output by the X-th level first gate driving circuit 101 has a low level, and/or the X-th level second scanning signal Scan2(X) output by the X-th level second gate driving circuit 201 has a low level, so that at least one of the second reset transistor Ti2 and the third reset transistor Ti3 of the sub-pixels Pi located in the m-th row to the m+3-th row is turned on to reset the third node N3, and/or, a bias voltage is applied to the second node N2 to improve the hysteresis effect of the driving transistor Tdr and improve the flicker.
  • the frequency of the second scanning signal Scan2 output by the second gate driving circuit 201 is greater than the frequency of the first scanning signal Scan1 output by the first gate driving circuit 101, so as to achieve both improved flicker and power saving.
  • the frequency of the second scanning signal Scan2 output by the second gate driving circuit 201 is 240 Hz
  • the frequency of the first scanning signal Scan1 output by the first gate driving circuit 101 is 120 Hz.

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Abstract

一种显示装置，包括显示面板及多个栅极驱动单元，多个栅极驱动单元至少包括与显示面板的多个子像素（Pi）电性连接且共用时钟信号及电源信号的第一栅极驱动单元（10）和第二栅极驱动单元（20）；第一栅极驱动单元（10）包括的多个级联的第一栅极驱动电路（101）和第二栅极驱动单元（20）包括的多个级联的第二栅极驱动电路（201）在第一方向上交替排布。

Description

显示装置
本申请要求于2023年07月12日提交中国专利局、申请号为202310856479.8、发明名称为“显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，具体涉及一种显示装置。
 背景技术
现有显示面板中，具有相同功能和结构的栅极驱动单元采用串联设置以实现级传，具有不同功能的栅极驱动单元采用并联设置，如图1所示的EM(m)~EM(m+3)和Pscan(m)~ Pscan(m+3)。但随着像素驱动电路结构不断发展的复杂化，像素驱动电路所需应用的可实现不同功能的栅极驱动单元的数量也开始增多。若实现不同功能的栅极驱动单元继续沿用图1所示的布局，会导致显示面板的边框区域变宽，不利于显示面板实现窄边框设计。
 发明概述
本申请实施例提供一种显示装置，有利于使显示面板实现窄边框设计。
本申请实施例提供一种显示装置，包括显示面板及多个栅极驱动单元。所述显示面板包括多个子像素，每一所述子像素包括发光器件和与所述发光器件电性连接的像素驱动电路，所述像素驱动电路包括多个晶体管。多个所述栅极驱动单元至少包括与多个所述子像素电性连接且共用时钟信号及电源信号的第一栅极驱动单元和第二栅极驱动单元；所述第一栅极驱动单元包括多个级联的第一栅极驱动电路，所述第一栅极驱动单元根据第一启动信号、所述时钟信号以及所述电源信号输出多个第一扫描信号至多个所述子像素；所述第二栅极驱动单元包括多个级联的第二栅极驱动电路，所述第二栅极驱动单元根据第二启动信号、所述时钟信号以及所述电源信号输出多个第二扫描信号至多个所述子像素。其中，每一所述子像素包括的一所述晶体管根据对应的所述第一扫描信号导通，每一所述子像素包括的另一所述晶体管根据对应的所述第二扫描信号导通；多个所述第一栅极驱动电路和多个所述第二栅极驱动电路在第一方向上交替排布。
有益效果
相较于现有技术，本申请实施例提供一种显示装置，包括显示面板及多个栅极驱动单元，多个栅极驱动单元至少包括与显示面板的多个子像素电性连接且共用时钟信号及电源信号的第一栅极驱动单元和第二栅极驱动单元；第一栅极驱动单元和第二栅极驱动单元分别接收第一启动信号和第二启动信号并配合时钟信号及电源信号输出多个第一扫描信号及第二扫描信号至多个子像素，以使每一子像素包括的一晶体管根据对应的第一扫描信号导通，每一子像素包括的另一晶体管根据对应的第二扫描信号导通；第一栅极驱动单元包括的多个级联的第一栅极驱动电路和第二栅极驱动单元包括多个级联的第二栅极驱动电路在第一方向上交替排布。通过使多个第一栅极驱动电路和多个第二栅极驱动电路在第一方向上交替排布，以减小面板边框宽度，以利于显示装置实现窄边框设计。
 附图说明
图1是现有技术中栅极驱动单元的设置结构示意图；
图2A~图2C是本申请实施例提供的显示装置的结构示意图；
图3A~图3B是本申请实施例提供的栅极驱动电路的结构示意图；
图4A~图4C是本申请实施例提供的像素驱动电路的结构示意图；
图5A~图5C是本申请实施例提供的时序图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
具体地，如图2A~图2C是本申请实施例提供的显示装置的结构示意图；本申请实施例提供一种显示装置，包括显示面板及多个栅极驱动单元。
显示面板包括多个子像素Pi，每一子像素Pi包括发光器件L和与发光器件L电性连接的像素驱动电路，像素驱动电路用于驱动对应的发光器件L发光。
可选地，显示面板包括自发光显示面板。子像素Pi包括红色子像素R、绿色子像素G及蓝色子像素B；发光器件L包括有机发光二极管、次毫米发光二极管、微型发光二极管等。
可选地，像素驱动电路包括多个晶体管。
多个栅极驱动单元至少包括与多个子像素Pi电性连接且共用时钟信号及电源信号的第一栅极驱动单元10和第二栅极驱动单元20。
可选地，显示装置包括与第一栅极驱动单元10和第二栅极驱动单元20电性连接的第一时钟信号线CKL1、第二时钟信号线CKL2、第一电源线VL1和第二电源线VL2，第一时钟信号线CKL1、第二时钟信号线CKL2、第一电源线VL1和第二电源线VL2均沿第一方向延伸，第一时钟信号线CKL1传输第一时钟信号CK，第二时钟信号线CKL2传输第二时钟信号XCK，时钟信号包括第一时钟信号CK和第二时钟信号XCK。第一电源线VL1传输第一电源信号VGH，第二电源线VL2传输第二电源信号VGL，电源信号包括第一电源信号VGH和第二电源信号VGL。第一时钟信号CK和第二时钟信号XCK反相，第一电源信号VGH对应的电压大于第二电源信号VGL对应的电压。
第一栅极驱动单元10包括多个级联的第一栅极驱动电路101，第一栅极驱动单元10根据第一启动信号STV1、时钟信号以及电源信号输出多个第一扫描信号Scan1至多个子像素Pi。
第二栅极驱动单元20包括多个级联的第二栅极驱动电路201，第二栅极驱动单元20根据第二启动信号STV2、时钟信号以及电源信号输出多个第二扫描信号Scan2至多个子像素Pi。
其中，每一子像素Pi包括的一晶体管根据对应的第一扫描信号Scan1导通，每一子像素Pi包括的另一晶体管根据对应的第二扫描信号Scan2导通；多个第一栅极驱动电路101和多个第二栅极驱动电路201在第一方向上交替排布。通过使分别与像素驱动电路中具有不同功能的晶体管实现电性连接的第一栅极驱动电路101和第二栅极驱动电路201于第一方向上交替排布，以使无级联关系的第一栅极驱动单元10和第二栅极驱动单元20表现出串联特性，以改善现有技术中级联的栅极驱动电路呈串联设置，而无级联关系的栅极驱动电路并联设置，导致显示面板的边框宽度较大，不利于使显示装置实现窄边框的设计的问题。
可选地，为降低布局设计复杂度及制程难度，在第一方向上交替排布且无级联关系的栅极驱动电路的电路拓扑结构相同。如第一栅极驱动电路101和第二栅极驱动电路201的电路拓扑结构相同。
可选地，在第一方向上交替排布且无级联关系的栅极驱动电路的电路拓扑结构也可不相同。其中，电路拓扑结构不相同包括电路拓扑结构相似（如第二栅极驱动电路201是在第一栅极驱动电路101的基础上，减小或增加至少一个晶体管或至少一个电容）及电路拓扑结构不相似（即第一栅极驱动电路101的拓扑结构和第二栅极驱动电路201的拓扑结构完全不相同）。
可选地，图3A~图3B是本申请实施例提供的栅极驱动电路的结构示意图，栅极驱动电路包括第一晶体管T1~第十晶体管T10及第一电容C1~第三电容C3。
第一晶体管T1的输入端与第二电源线VL2电性连接，第一晶体管T1的输出端与第二晶体管T2的控制端、第三晶体管T3的控制端及第四晶体管T4的输出端电性连接，第二晶体管T2的输出端与第五晶体管T5的输入端电性连接，第三晶体管T3的输入端与第一电源线VL1电性连接，第三晶体管T3的输出端与第六晶体管T6的输出端电性连接，第七晶体管T7的输入端接收启动信号（如第一启动信号STV1、第二启动信号STV2或上级栅极驱动电路输出的扫描信号Scan(m-1)，其中，m≥1），第七晶体管T7的输出端与第四晶体管T4的控制端、第六晶体管T6的控制端、第八晶体管T8及第九晶体管T9的控制端电性连接，第八晶体管T8的输入端与第一电源线VL1电性连接，第八晶体管T8的输出端与第五晶体管T5的输出端及第十晶体管T10的控制端电性连接，第九晶体管T9的输入端与第二电源线VL2电性连接，第十晶体管T10的输入端与第一电源线VL1电性连接，第九晶体管T9的输出端与第十晶体管T10的输出端均和栅极驱动电路输出扫描信号（如Scan(m)）的信号输出端电性连接。第一电容C1串联于第六晶体管T6的输出端与第六晶体管T6的控制端之间，第二电容C2串联于第二晶体管T2的输出端与第二晶体管T2的控制端之间，第三电容C3串联于第十晶体管T10的输入端与第十晶体管T10的控制端之间。
可选地，在第m级栅极驱动电路中，第一晶体管T1的控制端与第一时钟信号线CKL1电性连接，第二晶体管T2的输入端与第二时钟信号线CKL2电性连接，第四晶体管T4的输入端与第一时钟信号线CKL1电性连接，第五晶体管T5的控制端与第二时钟信号线CKL2电性连接，第六晶体管T6的输入端与第二时钟信号线CKL2电性连接。
可选地，在第m+1级栅极驱动电路中，第一晶体管T1的控制端与第二时钟信号线CKL2电性连接，第二晶体管T2的输入端与第一时钟信号线CKL1电性连接，第四晶体管T4的输入端与第二时钟信号线CKL2电性连接，第五晶体管T5的控制端与第一时钟信号线CKL1电性连接，第六晶体管T6的输入端与第一时钟信号线CKL1电性连接。
可选地，栅极驱动电路还包括第十一晶体管T11及第十二晶体管T12，十一晶体管的控制端及第十二晶体管T12的控制端与第二电源线VL2电性连接，第十一晶体管T11的输入端与输出端电性连接于第一晶体管T1的输出端和第二晶体管T2的控制端之间，第十二晶体管T12的输入端和第四晶体管T4的控制端、第七晶体管T7的输出端及第八晶体管T8的控制端电性连接，第十二晶体管T12的输出端与第六晶体管T6的控制端、第九晶体管T9的控制端电性连接。
可选地，栅极驱动电路还包括第十三晶体管T13，第十三晶体管T13的控制端与重置信号线CL电性连接，第十三晶体管T13的输入端第一电源线VL1电性连接，第十三晶体管T13的输出端与第七晶体管T7的输出端电性连接。
请继续参阅图3B，栅极驱动电路还包括第十四晶体管T14~第十六晶体管T16。在图3B所示的栅极驱动电路中，第六晶体管T6的控制端与第十六晶体管T16的控制端电性连接，第十四晶体管T14的输入端与第七晶体管T7的输入端电性连接，第十四晶体管T14的输出端与第十五晶体管T15的输入端电性连接，第十五晶体管T15的控制端与第二电源线VL2电性连接，第十五晶体管T15的输出端与第十六晶体管T16的控制端电性连接，第十六晶体管T16的输入端与第十六晶体管T16的控制端电性连接，第十六晶体管T16的输出端与第九晶体管T9的控制端电性连接。
可选地，在第n级栅极驱动电路中，第十四晶体管T14的控制端与第一时钟信号线CKL1电性连接；在第n+1级栅极驱动电路中，第十四晶体管T14的控制端与第二时钟信号线CKL2电性连接。
图3A~图3B的栅极驱动电路的工作原理可参阅现有技术得到，在此不再进行赘述。
可以理解的，第一栅极驱动电路101、第二栅极驱动电路201可采用图3A~图3B所示的栅极驱动电路的拓扑结构进行设置，也可采用其他形式的电路拓扑结构。
如图4A~图4C是本申请实施例提供的像素驱动电路的结构示意图，多个晶体管包括驱动晶体管Tdr、数据晶体管Tda、补偿晶体管Tc、第一复位晶体管Ti1、第二复位晶体管Ti2及发光控制晶体管。
驱动晶体管Tdr的控制端与第一节点N1电性连接，驱动晶体管Tdr的输入端与第二节点N2电性连接，驱动晶体管Tdr的输出端与第三节点N3电性连接。
数据晶体管Tda的输入端与对应的数据线DL电性连接，数据晶体管Tda的输出端与第二节点N2电性连接。
补偿晶体管Tc的输入端与第二节点N2电性连接，补偿晶体管Tc的输出端与驱动晶体管Tdr的输出端电性连接。
第一复位晶体管Ti1的输入端与对应的第一复位线ViL1电性连接，第一复位晶体管Ti1的输出端与第一节点N1电性连接。
第二复位晶体管Ti2的输入端与对应的第二复位线ViL2电性连接，第二复位晶体管Ti2的输出端与第三节点N3电性连接。
发光控制晶体管的输入端和输出端与驱动晶体管Tdr串联于第一电压端VDD和发光器件L之间。可选地，发光控制晶体管包括第一发光控制晶体管Te1和第二发光控制晶体管Te2，第一发光控制晶体管Te1的输入端和输出端电性连接于第一电压端VDD和第二节点N2之间，第二发光控制晶体管Te1的输入端和输出端电性连接于驱动晶体管Tdr的输出端和第三节点N3之间。发光器件L的阴极与第二电压端VSS电性连接。
可选地，补偿晶体管Tc及第一复位晶体管Ti1可为硅晶体管、氧化物晶体管。
可选地，栅极驱动电路还包括第三复位晶体管Ti3，第三复位晶体管Ti3的输入端与对应的第三复位线ViL3电性连接，第三复位晶体管Ti3的输出端与第二节点N2电性连接。
可选地，第三复位晶体管Ti3的控制端可与第二复位晶体管Ti2的控制端电性连接，以使第二复位晶体管Ti2与第三复位晶体管Ti3同步导通或截止，如图4A~图4B所示。
可选地，第一复位晶体管Ti1及数据晶体管Tda的控制端可与一栅极驱动单元的不同级的栅极驱动电路电性连接，补偿晶体管Tc及数据晶体管Tda的控制端可与一栅极驱动单元的同级的栅极驱动电路电性连接，如图4A和图4C所示。
请继续参阅图4A~图4C，像素驱动电路还包括存储电容Cst，存储电容Cst串联于第一电压端VDD和驱动晶体管Tdr的控制端之间。
其中，第一栅极驱动单元10及第二栅极驱动单元20与多个子像素Pi的补偿晶体管Tc、第一复位晶体管Ti1、第二复位晶体管Ti2、第三复位晶体管Ti3及发光控制晶体管的其中两个电性连接。
可选地，第一栅极驱动单元10和第二栅极驱动单元20中的一个与多个子像素Pi的补偿晶体管Tc的控制端电性连接，第一栅极驱动单元10和第二栅极驱动单元20中的另一个与多个子像素Pi的第一复位晶体管Ti1的控制端电性连接，或第一栅极驱动单元10和第二栅极驱动单元20中的另一个与多个子像素Pi的第二复位晶体管Ti2的控制端电性连接，或第一栅极驱动单元10和第二栅极驱动单元20中的另一个与多个子像素Pi的第三复位晶体管Ti3的控制端电性连接，或第一栅极驱动单元10和第二栅极驱动单元20中的另一个与多个子像素Pi的发光控制晶体管的控制端电性连接。
可选地，第一栅极驱动单元10和第二栅极驱动单元20中的一个与多个子像素Pi的第一复位晶体管Ti1的控制端电性连接，第一栅极驱动单元10和第二栅极驱动单元20中的另一个与多个子像素Pi的第二复位晶体管Ti2的控制端电性连接，或第一栅极驱动单元10和第二栅极驱动单元20中的另一个与多个子像素Pi的第三复位晶体管Ti3的控制端电性连接，或第一栅极驱动单元10和第二栅极驱动单元20中的另一个与多个子像素Pi的发光控制晶体管的控制端电性连接。
可选地，第一栅极驱动单元10和第二栅极驱动单元20中的一个与多个子像素Pi的第二复位晶体管Ti2的控制端电性连接，第一栅极驱动单元10和第二栅极驱动单元20中的另一个与多个子像素Pi的第三复位晶体管Ti3的控制端电性连接，或第一栅极驱动单元10和第二栅极驱动单元20中的另一个与多个子像素Pi的发光控制晶体管的控制端电性连接。
可选地，第一栅极驱动单元10和第二栅极驱动单元20中的一个与多个子像素Pi的第三复位晶体管Ti3的控制端电性连接，第一栅极驱动单元10和第二栅极驱动单元20中的另一个与多个子像素Pi的发光控制晶体管的控制端电性连接。
可选地，每一第一栅极驱动电路101与相邻n行的多个子像素Pi电性连接；每一第二栅极驱动电路201与相邻n行的多个子像素Pi电性连接，以使第一栅极驱动电路101和第二栅极驱动电路201可同时与n行子像素Pi电性连接，从而使显示装置包括的第一栅极驱动电路101及第二栅极驱动电路201的数量减少，以降低功耗。其中，n大于1。可选地，n等于2、3、4、5、6、7、8等。如n等于4，第一级第一栅极驱动电路101及第一级第二栅极驱动电路201均与位于第一行~第四行的多个子像素Pi电性连接，第二级第一栅极驱动电路101及第二级第二栅极驱动电路201均与位于第五行~第八行的多个子像素Pi电性连接，依次类推，得到位于其他行的多个子像素Pi与第一栅极驱动电路101及第二栅极驱动电路201的级数对应关系。
可选地，位于第m+n行~第m+n+3行的多个子像素Pi与一第一栅极驱动电路101和一第二栅极驱动电路201电性连接。
可选地，请继续参阅图2A及图4A，第一栅极驱动单元10与多个子像素Pi的发光控制晶体管的控制端电性连接，第二栅极驱动单元20与多个子像素Pi的第二复位晶体管Ti2的控制端电性连接，第三复位晶体管Ti3的控制端与第二复位晶体管Ti2的控制端电性连接，以通过多个第一栅极驱动电路101控制多个子像素Pi的发光控制晶体管导通或截止，通过多个第二栅极驱动电路201控制第二复位晶体管Ti2及第三复位晶体管Ti3的导通或截止。
可选地，每一第一栅极驱动电路101与相邻四行的多个子像素Pi的发光控制晶体管的控制端电性连接；每一第二栅极驱动电路201与相邻四行的多个子像素Pi的第二复位晶体管Ti2的控制端及第三复位晶体管Ti3的控制端电性连接。
可选地，请继续参阅图2B及图4B，多个栅极驱动单元还包括共用时钟信号及电源信号的第三栅极驱动单元30和第四栅极驱动单元40，第三栅极驱动单元30根据第三启动信号STV3、时钟信号以及电源信号输出多个第三扫描信号Nscan1至多个子像素Pi；第四栅极驱动单元40根据第四启动信号STV4、时钟信号以及电源信号输出多个第四扫描信号Nscan2至多个子像素Pi。
其中，第三栅极驱动单元30包括多个级联的第三栅极驱动电路301，第四栅极驱动单元40包括多个级联的第四栅极驱动电路401，多个第三栅极驱动电路301和多个第四栅极驱动电路401在第一方向上交替排布。可选地，第一栅极驱动单元10与第三栅极驱动单元30并联排布，第二栅极驱动单元20和第四栅极驱动单元40并联排布。
可选地，补偿晶体管Tc和第一复位晶体管Ti1包括氧化物晶体管，第三栅极驱动单元30与多个子像素Pi的补偿晶体管Tc的控制端电性连接，第四栅极驱动单元40与多个子像素Pi的第一复位晶体管Ti1的控制端电性连接。
可选地，每一第三栅极驱动电路301与相邻四行的多个子像素Pi的补偿晶体管Tc的控制端电性连接；每一第四栅极驱动电路401与相邻四行的多个子像素Pi的第一复位晶体管Ti1的控制端电性连接。
可选地，请继续参阅图2C及图4C，第一栅极驱动单元10与多个子像素Pi的第二复位晶体管Ti2的控制端电性连接，第二栅极驱动单元20与多个子像素Pi的第三复位晶体管Ti3的控制端电性连接。
可选地，每一第一栅极驱动电路101与相邻四行的多个子像素Pi的第二复位晶体管Ti2的控制端电性连接；每一第二栅极驱动电路201与相邻四行的多个子像素Pi的第三复位晶体管Ti3的控制端电性连接。
可选地，请继续参阅图2C和图4C，多个栅极驱动单元还包括第五栅极控制单元，第五栅极控制单元包括多个第五栅极驱动电路，每一第五栅极驱动电路501与相邻两行的多个子像素Pi的发光控制晶体管的控制端电性连接。
可选地，请继续参阅图2A~图2C，多个栅极驱动单元还包括第六栅极驱动单元60，第六栅极驱动单元60包括多个级联的第六栅极驱动电路601；其中，每一第六栅极驱动电路601与位于同行的多个子像素Pi的数据晶体管Tda的控制端电性连接。
可选地，每一第六栅极驱动电路601与位于同行的多个子像素Pi的第一复位晶体管Ti1的控制端电性连接，补偿晶体管Tc的控制端与数据晶体管Tda的控制端电性连接，如图2A和图2C及图4A和图4C所示。
可选地，显示面板包括位于多个子像素Pi相对两侧的第一子区A1和第二子区A2；其中，第一栅极驱动单元10和第二栅极驱动单元20位于第一子区A1内，第六栅极驱动单元60位于第一子区A1和第二子区A2的至少一个内。
可选地，请继续参阅图2A，第一栅极驱动单元10和第二栅极驱动单元20位于第一子区A1内，第六栅极驱动单元60位于第二子区A2内。
可选地，请继续参阅图2B，第一栅极驱动单元10、第二栅极驱动单元20、第三栅极驱动单元30和第四栅极驱动单元40位于第一子区A1内，且第一栅极驱动单元10和第二栅极驱动单元20位于第三栅极驱动单元30和第四栅极驱动单元40靠近第六栅极驱动单元60的一侧，第六栅极驱动单元60位于第二子区A2内。
可选地，请继续参阅图2C，第一栅极驱动单元10和第二栅极驱动单元20位于第一子区A1内，第六栅极驱动单元60位于第一子区A1和第二子区A2内，第五栅极驱动单元50位于第二子区A2内，且第五栅极驱动单元50位于第六栅极驱动单元60远离第一栅极驱动单元10和第二栅极驱动单元20的一侧，第一栅极驱动单元10和第二栅极驱动单元20位于第六栅极驱动单元60远离第五栅极驱动单元50的一侧。
如图5A~图5C是本申请实施例提供的时序图，以每一第一栅极驱动电路101及每一第二栅极驱动电路201均与相邻四行子像素Pi电性连接为例，对显示装置的工作原理进行说明。其中X≥1，Y≥1。
请继续参阅图2A、图4A和图5A，在第一阶段t1，第X级第一栅极驱动电路101输出的第X级第一扫描信号Scan1(X)为高电平，使得位于第m行~第m+3行的子像素Pi的发光控制晶体管截止，第m-1级第六栅极驱动电路601输出的第m-1级扫描信号Pscan(m-1)为低电平，使得位于第m行的子像素Pi的第一复位晶体管Ti1导通，第一复位线ViL1传输的第一复位信号对驱动晶体管Tdr的栅极进行复位。
第二阶段t2，第m级第六栅极驱动电路601输出的第m级扫描信号Pscan(m)为低电平，使得位于第m行的子像素Pi的数据晶体管Tda和补偿晶体管Tc导通，数据线DL传输的数据信号写入驱动晶体管Tdr的栅极及存储电容Cst；位于第m+1行的子像素Pi的第一复位晶体管Ti1导通，第一复位线ViL1传输的第一复位信号对驱动晶体管Tdr的栅极进行复位。之后，第m+1级第六栅极驱动电路601输出的第m+1级扫描信号Pscan(m+1)为低电平，使得位于第m+1行的子像素Pi的数据晶体管Tda和补偿晶体管Tc导通，数据线DL传输的数据信号写入驱动晶体管Tdr的栅极及存储电容Cst；位于第m+2行的子像素Pi的第一复位晶体管Ti1导通，第一复位线ViL1传输的第一复位信号对驱动晶体管Tdr的栅极进行复位；之后，第m+2级第六栅极驱动电路601输出的第m+2级扫描信号Pscan(m+2)为低电平,使得位于第m+2行的子像素Pi的数据晶体管Tda和补偿晶体管Tc导通，数据线DL传输的数据信号写入驱动晶体管Tdr的栅极及存储电容Cst；位于第m+3行的子像素Pi的第一复位晶体管Ti1导通，第一复位线ViL1传输的第一复位信号对驱动晶体管Tdr的栅极进行复位；最后，第m+3级第六栅极驱动电路601输出的第m+3级扫描信号Pscan(m+3)为低电平，使得位于第m+3行的子像素Pi的数据晶体管Tda和补偿晶体管Tc导通，数据线DL传输的数据信号写入驱动晶体管Tdr的栅极及存储电容Cst；位于第m+4行的子像素Pi的第一复位晶体管Ti1导通，第一复位线ViL1传输的第一复位信号对驱动晶体管Tdr的栅极进行复位。
第三阶段t3，第X级第二栅极驱动电路201输出的第X级第二扫描信号Scan2(X)具有低电平，位于第m行~第m+3行的子像素的第二复位晶体管Ti2和第三复位晶体管Ti3导通，第二复位线ViL2传输的第二复位信号对第三节点N3进行复位，第三复位线ViL3传输的第三复位信号对第二节点N2施加偏置电压，改善驱动晶体管Tdr的迟滞效应，改善闪烁。此外，位于第m+4行~第m+7行的子像素Pi于第三阶段t3执行与位于第m行~第m+3行的子像素Pi于第二阶段t2相同的操作。
第四阶段t4，第X级第一栅极驱动电路101输出的第X级第一扫描信号Scan1(X)为低电平，使得位于第m行~第m+3行的子像素Pi的发光控制晶体管导通，发光器件L发光。
可选地，显示装置可采用可变刷新频率显示。相应地，显示面板显示时包括写入帧WF和保持帧HF，其中，写入帧WF可包括第一阶段t1~第四阶段t4。而在保持帧HF内，第一栅极驱动电路101输出的第一扫描信号Scan1具有高电平状态和低电平状态，第二栅极驱动电路201输出的第二扫描信号Scan2具有高电平状态和低电平状态，第六栅极驱动单元60输出的扫描信号Pscan具有低电平状态。在保持帧HF内还具有第五阶段t5，以对对应行的子像素Pi的第三节点N3进行复位，并对第二节点N2施加偏置电压。如在第五阶段t5中，第X级第一栅极驱动电路101输出的第X级第一扫描信号Scan1(X)为高电平，使得位于第m行~第m+3行的子像素Pi的发光控制晶体管截止，第X级第二栅极驱动电路201输出的第X级第二扫描信号Scan2(X)具有低电平，位于第m行~第m+3行的子像素Pi的第二复位晶体管Ti2和第三复位晶体管Ti3导通，第二复位线ViL2传输的第二复位信号对第三节点N3进行复位，第三复位线ViL3传输的第三复位信号对第二节点N2施加偏置电压，改善驱动晶体管Tdr的迟滞效应，改善闪烁。
请继续参阅图4B和图5B，在第一阶段t1，第X级第一栅极驱动电路101输出的第X级第一扫描信号Scan1(X)为高电平，使得位于第m行~第m+3行的子像素Pi的发光控制晶体管截止；第X级第四栅极驱动电路401输出的第X级第四扫描信号Nscan2(X)为低电平，使得位于第m行~第m+3行的子像素Pi的第一复位晶体管Ti1导通，第一复位线ViL1传输的第一复位信号对位于第m行~第m+3行的子像素Pi的驱动晶体管Tdr的栅极进行复位。
第二阶段t2，第X级第三栅极驱动电路301输出的第X级第三扫描信号Nscan1(X)为高电平，使得位于第m行~第m+3行的子像素Pi的补偿晶体管Tc导通；第m级第六栅极驱动电路601输出的第m级扫描信号Pscan(m)为低电平，使得位于第m行的子像素Pi的数据晶体管Tda导通，数据线DL传输的数据信号写入驱动晶体管Tdr的栅极及存储电容Cst。之后，第m+1级第六栅极驱动电路601输出的第m+1级扫描信号Pscan(m+1)为低电平，使得位于第m+1行的子像素Pi的数据晶体管Tda导通，数据线DL传输的数据信号写入驱动晶体管Tdr的栅极及存储电容Cst；之后，第m+2级第六栅极驱动电路601输出的第m+2级扫描信号Pscan(m+2)为低电平，使得位于第m+2行的子像素Pi的数据晶体管Tda导通，数据线DL传输的数据信号写入驱动晶体管Tdr的栅极及存储电容Cst；最后，第m+3级第六栅极驱动电路601输出的第m+3级扫描信号Pscan(m+3)为低电平使得位于第m+3行的子像素Pi的数据晶体管Tda导通，数据线DL传输的数据信号写入驱动晶体管Tdr的栅极及存储电容Cst。第X+1级第四栅极驱动电路401输出的第X+1级第四扫描信号Nscan2(X+1)为低电平，使得位于第m+4行~第m+7行的子像素Pi的第一复位晶体管Ti1导通，第一复位线ViL1传输的第一复位信号对位于第m+4行~第m+7行的子像素Pi的驱动晶体管Tdr的栅极进行复位。
第三阶段t3，第X级第二栅极驱动电路201输出的第X级第二扫描信号Scan2(X)具有低电平，位于第m行~第m+3行的子像素Pi的第二复位晶体管Ti2和第三复位晶体管Ti3导通，第二复位线ViL2传输的第二复位信号对第三节点N3进行复位，第三复位线ViL3传输的第三复位信号对第二节点N2施加偏置电压，改善驱动晶体管Tdr的迟滞效应，改善闪烁。此外，位于第m+4行~第m+7行的子像素Pi于第三阶段t3执行与位于第m行~第m+3行的子像素Pi于第二阶段t2相同的操作。
第四阶段t4，第X级第一栅极驱动电路101输出的第X级第一扫描信号Scan1(X)为低电平，使得位于第m行~第m+3行的子像素Pi的发光控制晶体管导通，发光器件L发光。
可选地，在保持帧HF内，第一栅极驱动电路101输出的第一扫描信号Scan1具有高电平状态和低电平状态，第二栅极驱动电路201输出的第二扫描信号Scan2具有高电平状态和低电平状态，第三栅极驱动单元30和第四栅极驱动单元40输出的扫描信号具有低电平状态，第六栅极驱动单元60输出的扫描信号具有低电平状态。在保持帧HF内还具有第五阶段t5，以对对应行的子像素Pi的第三节点N3进行复位，并对第二节点N2施加偏置电压。如在第五阶段t5中，第X级第一栅极驱动电路101输出的第X级第一扫描信号Scan1(X)为高电平，使得位于第m行~第m+3行的子像素Pi的发光控制晶体管截止，第X级第二栅极驱动电路201输出的第X级第二扫描信号Scan2(X)具有低电平，位于第m行~第m+3行的子像素Pi的第二复位晶体管Ti2和第三复位晶体管Ti3导通，第二复位线ViL2传输的第二复位信号对第三节点N3进行复位，第三复位线ViL3传输的第三复位信号对第二节点N2施加偏置电压，改善驱动晶体管Tdr的迟滞效应，改善闪烁。
请继续参阅图4C和图5C，在第一阶段t1，第Y级第五栅极驱动电路501输出的第Y级扫描信号EM(Y)为高电平，使得位于第m行~第m+1行的子像素Pi的发光控制晶体管截止；第m-1级第六栅极驱动电路601输出的第m-1级扫描信号Pscan(m-1)为低电平，使得位于第m行的子像素Pi的第一复位晶体管Ti1导通，第一复位线ViL1传输的第一复位信号对驱动晶体管Tdr的栅极进行复位。
第二阶段t2，第Y+1级第五栅极驱动电路501输出的第Y+1级扫描信号EM(Y+1)为高电平，使得位于第m+2行~第m+3行的子像素Pi的发光控制晶体管截止；第m级第六栅极驱动电路601输出的第m级扫描信号Pscan(m)为低电平使得位于第m行的子像素Pi的数据晶体管Tda和补偿晶体管Tc导通，数据线DL传输的数据信号写入驱动晶体管Tdr的栅极及存储电容Cst；位于第m+1行的子像素Pi的第一复位晶体管Ti1导通，第一复位线ViL1传输的第一复位信号对驱动晶体管Tdr的栅极进行复位。之后，第m+1级第六栅极驱动电路601输出的第m+1级扫描信号Pscan(m+1)为低电平使得位于第m+1行的子像素Pi的数据晶体管Tda和补偿晶体管Tc导通，数据线DL传输的数据信号写入驱动晶体管Tdr的栅极及存储电容Cst；位于第m+2行的子像素Pi的第一复位晶体管Ti1导通，第一复位线ViL1传输的第一复位信号对驱动晶体管Tdr的栅极进行复位；之后，第m+2级第六栅极驱动电路601输出的第m+2级扫描信号Pscan(m+2)为低电平使得位于第m+2行的子像素Pi的数据晶体管Tda和补偿晶体管Tc导通，数据线DL传输的数据信号写入驱动晶体管Tdr的栅极及存储电容Cst；位于第m+3行的子像素Pi的第一复位晶体管Ti1导通，第一复位线ViL1传输的第一复位信号对驱动晶体管Tdr的栅极进行复位；最后，第m+3级第六栅极驱动电路601输出的第m+3级扫描信号Pscan(m+3)为低电平使得位于第m+3行的子像素Pi的数据晶体管Tda和补偿晶体管Tc导通，数据线DL传输的数据信号写入驱动晶体管Tdr的栅极及存储电容Cst；位于第m+4行的子像素Pi的第一复位晶体管Ti1导通，第一复位线ViL1传输的第一复位信号对驱动晶体管Tdr的栅极进行复位。
第三阶段t3，第X级第一栅极驱动电路101输出的第X级第一扫描信号Scan1(X)具有低电平，位于第m+2行~第m+3行的子像素Pi的第二复位晶体管Ti2导通，第X级第二栅极驱动电路201输出的第X级第二扫描信号Scan2(X)具有低电平，位于第m+2行~第m+3行的子像素Pi的第三复位晶体管Ti3导通，第二复位线ViL2传输的第二复位信号对第三节点N3进行复位，第三复位线ViL3传输的第三复位信号对第二节点N2施加偏置电压，改善驱动晶体管Tdr的迟滞效应，改善闪烁。此外，位于第m+4行~第m+7行的子像素Pi于第三阶段t3执行与位于第m行~第m+3行的子像素Pi于第二阶段t2相同的操作。
第四阶段t4，第Y级第五栅极驱动电路501输出的第Y级扫描信号EM(Y)为低电平，使得位于第m行~第m+3行的子像素Pi的发光控制晶体管导通，发光器件L发光。
可选地，在保持帧HF内，第一栅极驱动电路101输出的第一扫描信号Scan1具有高电平状态和低电平状态，第二栅极驱动电路201输出的第二扫描信号Scan2具有高电平状态和低电平状态，第五栅极驱动单元50输出的扫描信号EM具有高电平状态和低电平状态，第六栅极驱动单元60输出的扫描信号Pscan具有低电平状态。在保持帧HF内还具有第五阶段t5，以对对应行的子像素Pi的第三节点N3进行复位，并对第二节点N2施加偏置电压。如在第五阶段t5中，第Y级第五栅极驱动电路501输出的第Y级扫描信号EM(Y)为高电平，使得位于第m行~第m+3行的子像素Pi的发光控制晶体管截止，第X级第一栅极驱动电路101输出的第X级第一扫描信号Scan1(X)具有低电平，和/或，第X级第二栅极驱动电路201输出的第X级第二扫描信号Scan2(X)具有低电平，使得位于第m行~第m+3行的子像素Pi的第二复位晶体管Ti2和第三复位晶体管Ti3中的至少一个导通，以对第三节点N3进行复位，和/或，对第二节点N2施加偏置电压，改善驱动晶体管Tdr的迟滞效应，改善闪烁。
可选地，在保持帧HF对应的时长内，第二栅极驱动电路201输出的第二扫描信号Scan2的频率大于第一栅极驱动电路101输出的第一扫描信号Scan1的频率，以兼顾改善闪烁及节省功耗的目的。可选地，在保持帧HF对应的时长内，第二栅极驱动电路201输出的第二扫描信号Scan2的频率为240Hz，第一栅极驱动电路101输出的第一扫描信号Scan1的频率为120Hz。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (16)

  1. 一种显示装置，其中，包括：
    显示面板，包括多个子像素，每一所述子像素包括发光器件和与所述发光器件电性连接的像素驱动电路，所述像素驱动电路包括多个晶体管；
    多个栅极驱动单元，至少包括与多个所述子像素电性连接且共用时钟信号及电源信号的第一栅极驱动单元和第二栅极驱动单元；所述第一栅极驱动单元包括多个级联的第一栅极驱动电路，所述第一栅极驱动单元根据第一启动信号、所述时钟信号以及所述电源信号输出多个第一扫描信号至多个所述子像素；所述第二栅极驱动单元包括多个级联的第二栅极驱动电路，所述第二栅极驱动单元根据第二启动信号、所述时钟信号以及所述电源信号输出多个第二扫描信号至多个所述子像素；
    其中，每一所述子像素包括的一所述晶体管根据对应的所述第一扫描信号导通，每一所述子像素包括的另一所述晶体管根据对应的所述第二扫描信号导通；多个所述第一栅极驱动电路和多个所述第二栅极驱动电路在第一方向上交替排布。
  2. 根据权利要求1所述的显示装置，其中，所述第一栅极驱动电路和所述第二栅极驱动电路的电路拓扑结构相同。
  3. 根据权利要求1所述的显示装置，其中，多个所述晶体管包括：
    驱动晶体管，所述驱动晶体管的控制端与第一节点电性连接，所述驱动晶体管的输入端与第二节点电性连接，所述驱动晶体管的输出端与第三节点电性连接；
    数据晶体管，所述数据晶体管的输入端与对应的数据线电性连接，所述数据晶体管的输出度与所述第二节点电性连接；
    补偿晶体管，所述补偿晶体管的输入端与所述第二节点电性连接，所述补偿晶体管的输出端与所述驱动晶体管的输出端电性连接；
    第一复位晶体管，所述第一复位晶体管的输入端与对应的第一复位线电性连接，所述第一复位晶体管的输出端与所述第一节点电性连接；
    第二复位晶体管，所述第二复位晶体管的输入端与对应的第二复位线电性连接，所述第二复位晶体管的输出端与所述第三节点电性连接；
    第三复位晶体管，所述第三复位晶体管的输入端与对应的第三复位线电性连接，所述第三复位晶体管的输出端与所述第二节点电性连接；以及
    发光控制晶体管，所述发光控制晶体管的输入端和输出端与所述驱动晶体管串联于第一电压端和所述发光器件之间；
    其中，所述第一栅极驱动单元及所述第二栅极驱动单元与多个所述子像素的所述补偿晶体管、所述第一复位晶体管、所述第二复位晶体管、所述第三复位晶体管及所述发光控制晶体管的其中两个电性连接。
  4. 根据权利要求3所述的显示装置，其中，所述第一栅极驱动单元与多个所述子像素的所述发光控制晶体管的控制端电性连接，所述第二栅极驱动单元与多个所述子像素的所述第二复位晶体管的控制端与电性连接，所述第三复位晶体管的控制端与所述第二复位晶体管的控制端电性连接。
  5. 根据权利要求4所述的显示装置，其中，所述补偿晶体管和所述第一复位晶体管包括氧化物晶体管；
    多个栅极驱动单元还包括共用所述时钟信号及所述电源信号的第三栅极驱动单元和第四栅极驱动单元，所述第三栅极驱动单元与多个所述子像素的所述补偿晶体管的控制端电性连接，所述第四栅极驱动单元与多个所述子像素的所述第一复位晶体管的控制端电性连接；
    其中，所述第三栅极驱动单元包括多个级联的第三栅极驱动电路，所述第四栅极驱动单元包括多个级联的第四栅极驱动电路，多个所述第三栅极驱动电路和多个所述第四栅极驱动电路在所述第一方向上交替排布。
  6. 根据权利要求5所述的显示装置，其中，每一所述第一栅极驱动电路与相邻四行的多个所述子像素的所述发光控制晶体管的控制端电性连接；每一所述第二栅极驱动电路与相邻四行的多个所述子像素的所述第二复位晶体管的控制端及所述第三复位晶体管的控制端电性连接；每一所述第三栅极驱动电路与相邻四行的多个所述子像素的所述补偿晶体管的控制端电性连接；每一所述第四栅极驱动电路与相邻四行的多个所述子像素的所述第一复位晶体管的控制端电性连接。
  7. 根据权利要求3所述的显示装置，其中，所述第一栅极驱动单元与多个所述子像素的所述第二复位晶体管的控制端电性连接，所述第二栅极驱动单元与多个所述子像素的所述第三复位晶体管的控制端电性连接。
  8. 根据权利要求7所述的显示装置，其中，每一所述第一栅极驱动电路与相邻四行的多个所述子像素的所述第二复位晶体管的控制端电性连接；每一所述第二栅极驱动电路与相邻四行的多个所述子像素的所述第三复位晶体管的控制端电性连接。
  9. 根据权利要求7所述的显示装置，其中，多个所述栅极驱动单元还包括：
    第五栅极控制单元，包括多个第五栅极驱动电路，每一所述第五栅极驱动电路与相邻两行的多个所述子像素的发光控制晶体管的控制端电性连接。
  10. 根据权利要求3所述的显示装置，其中，多个栅极驱动单元还包括：
    第六栅极驱动单元，包括多个级联的第六栅极驱动电路；
    其中，每一所述第六栅极驱动电路与位于同行的多个所述子像素的数据晶体管的控制端电性连接。
  11. 根据权利要求10所述的显示装置，其中，每一所述第六栅极驱动电路与位于同行的多个所述子像素的第一复位晶体管的控制端电性连接，所述补偿晶体管的控制端与所述数据晶体管的控制端电性连接。
  12. 根据权利要求10所述的显示装置，其中，所述显示面板包括位于多个所述子像素相对两侧的第一子区和第二子区；
    其中，所述第一栅极驱动单元和所述第二栅极驱动单元位于所述第一子区内，所述第六栅极驱动单元位于所述第一子区和所述第二子区的至少一个内。
  13. 根据权利要求1所述的显示装置，其中，所述第一栅极驱动电路包括：
    第一晶体管，所述第一晶体管的控制端与第一时钟信号线和第二时钟信号线中的一个电性连接，所述第一晶体管的输入端与第二电源线电性连接；
    第二晶体管，所述第二晶体管的控制端与所述第一晶体管的输出端电性连接，所述第二晶体管的输入端与所述第一时钟信号线和所述第二时钟信号线中的另一个电性连接；
    第三晶体管，所述第三晶体管的控制端与所述第一晶体管的输出端电性连接，所述第三晶体管的输入端与第一电源线电性连接；
    第四晶体管，所述第四晶体管的输出端与所述第一晶体管的输出端电性连接，所述第四晶体管的输入端与所述第一时钟信号线和所述第二时钟信号线中的一个电性连接；
    第五晶体管，所述第五晶体管的控制端与所述第一时钟信号线和所述第二时钟信号线中的另一个电性连接，所述第五晶体管的输入端与所述第二晶体管的输出端电性连接；
    第六晶体管，所述第六晶体管的输入端与所述第一时钟信号线和所述第二时钟信号线中的一个电性连接电性连接，所述第六晶体管的输出端与所述第三晶体管的输出端与电性连接；
    第七晶体管，所述第七晶体管的输入端接收启动信号，所述第七晶体管的输出端与所述第四晶体管的控制端、所述第六晶体管的控制端电性连接；
    第八晶体管，所述第八晶体管的控制端与所述第七晶体管的输出端电性连接，所述第八晶体管的输入端与所述第一电源线电性连接，所述第八晶体管的输出端与所述第五晶体管的输出端电性连接；
    第九晶体管，所述第九晶体管的控制端与所述第七晶体管的输出端电性连接，所述第九晶体管的输入端与所述第二电源线电性连接；
    第十晶体管，所述第十晶体管的控制端与所述第五晶体管的输出端电性连接，所述第十晶体管的输入端与所述第一电源线电性连接，所述第九晶体管的输出端与所述第十晶体管的输出端均和所述第一栅极驱动电路输出扫描信号的信号输出端电性连接；
    第一电容，串联于所述第六晶体管的输出端与所述第六晶体管的控制端之间；
    第二电容，串联于所述第二晶体管的输出端与所述第二晶体管的控制端之间；以及
    第三电容，串联于所述第十晶体管的输入端与所述第十晶体管的控制端之间。
  14. 根据权利要求13所述的显示装置，其中，所述第一栅极驱动电路还包括：
    第十一晶体管，所述第十一晶体管的控制端与所述第二电源线电性连接，所述第十一晶体管的输入端与输出端电性连接于所述第一晶体管的输出端和所述第二晶体管的控制端之间；以及
    第十二晶体管，所述第十二晶体管的控制端与所述第二电源线电性连接，所述第十二晶体管的输入端和所述第四晶体管的控制端、所述第七晶体管的输出端及所述第八晶体管的控制端电性连接，所述第十二晶体管的输出端与所述第六晶体管的控制端、所述第九晶体管的控制端电性连接。
  15. 根据权利要求13所述的显示装置，其中，所述第一栅极驱动电路还包括：
    第十三晶体管，所述第十三晶体管的控制端与重置信号线电性连接，所述第十三晶体管的输入端所述第一电源线电性连接，所述第十三晶体管的输出端与所述第七晶体管的输出端电性连接。
  16. 根据权利要求13所述的显示装置，其中，所述第一栅极驱动电路还包括：
    第十四晶体管，所述第十四晶体管的输入端与所述第七晶体管的输入端电性连接，所述第十四晶体管的控制端与所述第一时钟信号线或所述第二时钟信号线电性连接；
    第十五晶体管，所述第十五晶体管的输入端与所述第十四晶体管的输出端电性连接，所述第十五晶体管的控制端与所述第二电源线电性连接；
    第十六晶体管，所述第十六晶体管的控制端与所述第六晶体管的控制端及所述第十五晶体管的输出端电性连接，所述第十六晶体管的输入端与所述第十六晶体管的控制端电性连接，所述第十六晶体管的输出端与所述第九晶体管的控制端电性连接。
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