WO2025007345A1 - 半导体器件及其制作方法、存储器和存储系统 - Google Patents

半导体器件及其制作方法、存储器和存储系统 Download PDF

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Publication number
WO2025007345A1
WO2025007345A1 PCT/CN2023/106137 CN2023106137W WO2025007345A1 WO 2025007345 A1 WO2025007345 A1 WO 2025007345A1 CN 2023106137 W CN2023106137 W CN 2023106137W WO 2025007345 A1 WO2025007345 A1 WO 2025007345A1
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WIPO (PCT)
Prior art keywords
gate
semiconductor
lead
semiconductor device
shielding
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Application number
PCT/CN2023/106137
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English (en)
French (fr)
Inventor
刘小欣
霍宗亮
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Filing date
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Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Priority to PCT/CN2023/106137 priority Critical patent/WO2025007345A1/zh
Priority to CN202380009712.7A priority patent/CN119586339A/zh
Priority to US18/399,558 priority patent/US20250016984A1/en
Publication of WO2025007345A1 publication Critical patent/WO2025007345A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a memory and a storage system.
  • the present application provides a semiconductor device and a manufacturing method thereof, a memory and a storage system, which can improve the yield and reliability of the memory.
  • the present application provides a semiconductor device, comprising:
  • a semiconductor column array comprising a plurality of semiconductor columns arranged in an array along a first direction and a second direction and extending in a third direction, wherein the first direction, the second direction, and the third direction intersect each other;
  • a gate bar and a shielding bar are provided between adjacent semiconductor columns along the second direction, the gate bar and the shielding bar extend along the first direction and are spaced apart in the second direction;
  • a barrier strip extending along the first direction, the barrier strip being connected to one end of the shielding strip in the third direction and being located between the shielding strip and the gate strip in the third direction on the same side.
  • the present application further provides a method for manufacturing a semiconductor device, comprising:
  • a gate bar and a shield bar are formed between the adjacent semiconductor columns of the first row and the semiconductor columns of the second row, and the gate bar and the shield bar are extended along the first direction and spaced apart in the second direction;
  • a blocking bar is formed at one end of the shielding bar along the third direction.
  • the blocking bar extends along the first direction and is located on the same side of the shielding bar and the gate bar in the third direction.
  • the present application further provides a memory, the memory comprising:
  • An array storage structure comprising the semiconductor device according to the first aspect
  • a peripheral circuit is connected to the array storage structure to control the bias voltage of the array storage structure.
  • the present application further provides a storage system, comprising: the memory as described in the third aspect; and a controller coupled to the memory, the controller being used to control the memory to perform data writing and reading operations.
  • the present application forms two electrodes, namely a first electrode and a second electrode, between adjacent semiconductor columns, and at the same end of the first electrode and the second electrode in the third direction, a barrier strip extending along the first direction and connected to the second electrode is formed, so that the first electrode can be used as a gate strip and the second electrode can be used as a shielding strip.
  • the shielding strip is formed while the gate strip is formed, so that interference between adjacent semiconductor columns can be prevented by the shielding strip, thereby reducing the coupling effect between adjacent semiconductor columns.
  • FIG1 is an equivalent circuit diagram of a memory cell in a semiconductor device provided in an embodiment of the present application.
  • FIG2 is a cross-sectional view of a semiconductor device provided in an embodiment of the present application.
  • FIG3 is a top view of a substrate provided in an embodiment of the present application.
  • FIG4 is a cross-sectional view of a substrate provided in an embodiment of the present application.
  • FIG5 is a top view of forming an isolation trench according to an embodiment of the present application.
  • FIG6 is a cross-sectional view of the AA' cutting line in FIG5 for forming an isolation trench provided in an embodiment of the present application;
  • FIG. 7 is a top view of a dielectric material deposited in an isolation trench according to an embodiment of the present application.
  • FIG8 is a cross-sectional view of the isolation trench at the BB' cutting line in FIG7 provided by an embodiment of the present application;
  • FIG9 is a top view of forming a gate trench according to an embodiment of the present application.
  • FIG10 is a cross-sectional view of the CC' cutting line in FIG9 for forming the gate trench according to an embodiment of the present application;
  • FIG. 11 is a top view of a first oxide layer formed on the sidewall of a gate trench according to an embodiment of the present application
  • FIG. 12 is a cross-sectional view of a first oxide layer formed on the sidewall of a gate trench at a cutting line DD' in FIG. 11 according to an embodiment of the present application;
  • FIG. 13 is a top view of forming a conductive layer on a first oxide layer according to an embodiment of the present application
  • FIG. 14 is a cross-sectional view of a conductive layer formed on a first oxide layer at a cutting line EE' in FIG. 13 provided by an embodiment of the present application;
  • FIG15 is a cross-sectional view of the semiconductor device provided by an embodiment of the present application taken along the BB' cutting line in FIG12;
  • FIG16 is a top view of an embodiment of the present application providing a method of filling an isolation material into an inner wall of a gate trench;
  • FIG17 is a cross-sectional view of the FF' cutting line in FIG16 in which an isolation material is filled into the inner wall of the gate trench according to an embodiment of the present application;
  • FIG. 18 is a diagram of an embodiment of the present application providing a method of filling the inner wall of the gate trench with an isolation material to cover the gate strip. and a cross-sectional view of a shielding strip;
  • FIG19 is a cross-sectional view of a capacitor array formed according to an embodiment of the present application.
  • 20 to 26 are multiple cross-sectional views of a manufacturing process for forming a barrier layer provided in an embodiment of the present application;
  • FIG. 27 is a top view of a structure for forming a barrier strip and a gate conductive connection provided by an embodiment of the present application;
  • FIG28 is a cross-sectional view of a barrier strip and a gate conductive structure formed along a GG' cutting line in FIG27 according to an embodiment of the present application;
  • 29 to 30 are multiple cross-sectional views of a manufacturing process for forming a gate lead-out contact provided by an embodiment of the present application
  • FIG31 is a top view of a method for forming a gate lead-out contact and a shield lead-out contact provided in an embodiment of the present application;
  • FIG32 is a cross-sectional view of forming a gate lead-out contact and a shield lead-out contact at the HH' cutting line in FIG31 provided in an embodiment of the present application;
  • 33 and 34 are multiple top views of another manufacturing process for forming gate lead-out contacts and shield lead-out contacts provided by an embodiment of the present application;
  • FIG35 is a top view of a semiconductor column lead-out contact formed according to an embodiment of the present application.
  • 36 is a cross-sectional view of forming a gate lead-out contact, a shield lead-out contact and a semiconductor column lead-out contact provided in an embodiment of the present application;
  • FIG37 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application.
  • Figure 38 is a schematic diagram of the structure of the storage system provided in an embodiment of the present application.
  • Transistors can be used in dynamic random access memory (DRAM) to control the capacitance in each storage unit.
  • DRAM dynamic random access memory
  • the basic storage unit structure of dynamic random access memory consists of a transistor and a storage capacitor. Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.
  • the size of storage cells is getting smaller and smaller, and its array architecture has changed from 8F 2 to 6F 2 and then to 4F 2.
  • the architecture of the memory has changed from planar array transistor to recessed gate array transistor, from recessed gate array transistor to buried saddle fin array transistor, and then from buried saddle fin array transistor to vertical gate transistor.
  • the dynamic random access memory is composed of multiple storage unit structures, each of which is mainly composed of a transistor and a storage capacitor controlled by the transistor, that is, the dynamic random access memory includes 1 transistor (T, Transistor) and 1 capacitor (C, Capacitance), that is, a 1T1C architecture; its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.
  • T Transistor
  • C Capacitance
  • Figure 1 is a circuit connection diagram of a 1T1C architecture provided in an embodiment of the present application.
  • the drain of the transistor T is electrically connected to the bit line (BL)
  • the source of the transistor T is electrically connected to one of the electrode plates of the capacitor C
  • the other electrode plate of the capacitor C is grounded through the ground terminal (GND)
  • the gate of the transistor T is connected to the word line (WL).
  • a voltage is applied through the word line WL to control the transistor T to be turned on or off, and the bit line BL is used to perform a read or write operation on the capacitor C when the transistor T is turned on.
  • FIG. 2 is a cross-sectional schematic diagram of a semiconductor structure 200 provided in an embodiment of the present application.
  • the semiconductor structure includes: a first transistor 210 and a second transistor 220 arranged in parallel along the Y-axis direction and separated by a first isolation structure 206, wherein the first isolation structure 206 includes an air gap 205 (Airgap);
  • the first transistor 210 and the second transistor 220 both include: a gate 201 extending along the Z-axis direction, a channel region 204 extending along the Z-axis direction, a gate oxide layer (Gate oxide layer) 202 located between the gate 201 and the channel region 204 and extending along the Z-axis direction, and a source (not shown in the figure) and a drain (not shown in the figure) located at opposite ends of the channel region 204 along the Z-direction.
  • GTE oxide layer Gate oxide layer
  • the gate 201 is located on one side of the channel region 204; wherein the gate 201 of the first transistor 210 is located on one side of the two sides of the channel region 204 away from the first isolation structure 206, and the gate 201 of the second transistor 220 is located on one side of the two sides of the channel region 204 away from the first isolation structure 206.
  • an air gap 205 is formed in the middle of the first isolation structure 206 to improve the problem of coupling effect between the adjacent first transistor 210 and the second transistor 220 in the semiconductor structure.
  • the semiconductor structure has high requirements for process control and is prone to dumping problems.
  • some embodiments of the present application provide a semiconductor device 100 and a manufacturing method thereof, a memory 320 and a storage system 300.
  • the present application forms two electrodes, namely a first electrode and a second electrode, between adjacent semiconductor pillars 10, and forms a barrier strip 90 extending along the first direction X and connected to the second electrode at the same end of the first electrode and the second electrode in the third direction Z, so that the first electrode can be used as a gate strip 30, and the second electrode can be used as a shielding strip 20.
  • the shielding strip 20 is formed at the same time as the gate strip 30, so that the interference between adjacent semiconductor pillars 10 can be prevented by the shielding strip 20, thereby reducing the coupling effect between adjacent semiconductor pillars 10.
  • FIGS. 3 to 36 are schematic diagrams of a manufacturing process of a semiconductor device 100 provided in some embodiments of the present application.
  • the semiconductor device 100 is described, wherein FIG. 27 is a top view of a semiconductor structure provided in an embodiment of the present application, FIG. 28 is a cross-sectional view of the semiconductor structure provided in an embodiment of the present application at the GG' cutting line in FIG. 27, and FIG. 30 is another cross-sectional view of the semiconductor structure provided in an embodiment of the present application at the GG' cutting line in FIG. 27.
  • the semiconductor The device 100 comprises:
  • a semiconductor pillar array comprising a plurality of semiconductor pillars 10 arranged in an array along a first direction and a third direction and extending in the third direction, wherein the first direction, the second direction, and the third direction intersect each other;
  • a gate bar 30 and a shield bar 20 are provided between the adjacent semiconductor pillars 10 along the second direction Y, the gate bar 30 and the shield bar 20 extend along the first direction X and are spaced apart in the third direction Y; and,
  • the barrier bar 90 extends along the first direction X, is connected to one end of the shielding bar 20 in the third direction Z, and is located on the same side of the shielding bar 20 and the gate bar 30 in the third direction Z.
  • the first direction and the third direction have an angle therebetween, and the third direction and the plane where the first direction and the third direction are located have an angle therebetween, and the angle range is: less than or equal to 90 degrees.
  • the first direction is set to the X direction
  • the second direction is set to the Y direction
  • the third direction is set to the Z direction.
  • the plurality of semiconductor pillars 10 include a first row of semiconductor pillars 10a and a second row of semiconductor pillars 10b arranged along the first direction X and adjacent to each other in the second direction Y.
  • the semiconductor pillars 10 are used to transfer charges or stop the transfer of charges under the action of an external electric field, so that the transistor is turned on or off.
  • the extension direction of each semiconductor pillar 10 is the current direction when the transistor is turned on.
  • the extension direction of the semiconductor pillar 10 is the third direction Z, and the plurality of semiconductor pillars 10 are distributed in an array along the first direction X and the third direction Y to form a semiconductor pillar array.
  • a gate bar 30 and a shield bar 20 are provided between two adjacent semiconductor columns 10 along the second direction Y.
  • the gate bar 30 between the adjacent semiconductor columns 10 along the second direction Y extends along the first direction X
  • the shield bar 20 between the adjacent semiconductor columns 10 along the second direction Y extends along the first direction X
  • the gate bar 30 and the shield bar 20 between every two adjacent semiconductor columns 10 along the second direction Y are spaced from each other, that is, the gate bar 30 and the shield bar 20 between the adjacent semiconductor columns 10 are not connected. touch or have a spacing.
  • the semiconductor structure is further provided with a barrier strip 90 extending along the first direction X, the barrier strip 90 contacts or is connected to one end of the shielding strip 20 in the third direction Z, and the barrier strip 90 is located on the same side as the shielding strip 20 and the gate strip 30 in the third direction Z, that is, the barrier strip 90, one end of the shielding strip 20 connected to the barrier strip 90 in the third direction Z, and one end of the gate strip 30 connected to the gate conductive structure 31 formed in the embodiment below in the third direction Z are located on the same side.
  • the gate strip 30 and the shielding strip 20 between the adjacent semiconductor pillars 10 in the second direction Y can be isolated by the barrier strip 90, and because the barrier strip 90 has an insulating function, the barrier strip 90 can better isolate the shielding strip 20 from the gate strip 30.
  • the barrier strip 90 is located between the shielding strip 20 and the gate strip 30 and is in contact with one end of the shielding strip 20 in the third direction Z (for example, one end of the semiconductor column 10 in the third direction Z away from the capacitor structure 70 in the embodiment below), and the barrier strip 90 and the gate strip 30 have a spacing in the second direction Y.
  • the blocking strip 90 may also be located at the same end of the shielding strip 20 and the semiconductor column 10 in the third direction Z.
  • the first blocking portion 90a of the blocking strip 90 is located at the same end of the shielding strip 20 and the gate strip 30 in the third direction Z between adjacent semiconductor columns 10, that is, the first blocking portion 90a connects one end of the shielding strip 20 in the third direction Z
  • the second blocking portion 90b of the blocking strip 90 is located at the same end of the adjacent semiconductor columns 10 in the third direction Z, that is, the second blocking portion 90b connects one end of the semiconductor column 10 in the third direction Z
  • the first blocking portion 90a connected to one end of the shielding strip 20 in the third direction Z and the second blocking portion 90b connected to one end of the semiconductor column 10 in the third direction Z are located on the same side in the third direction Z.
  • the first blocking portion 90a and the second blocking portion 90b can be a fan-shaped, and as shown in Figure 30, the cross-sectional shape of the second blocking portion 90b can be a rectangle.
  • the cross-sectional shape of the second blocking portion 90b can also be an inverted trapezoid, an arc, etc.
  • the first blocking portion 90a may be removed to connect the following embodiment as shown in FIG. The bit line BL in the embodiment.
  • the barrier strip 90 may be made of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, polysiloxane or polysilazane, etc.
  • Silicon oxide refers to silicon oxide compounds such as SixOy
  • silicon nitride refers to silicon nitrogen compounds such as SixNy.
  • the semiconductor device 100 further includes: a gate conductive structure 31, which extends along the first direction X and is located between the one end of the gate bar 30 in the third direction Z and the barrier bar 90, and is at least partially parallel to the barrier bar 90.
  • one end of the gate bar 30 in the third direction Z is connected to a gate conductive structure 31.
  • the gate conductive structure 31 is located between the gate bar 30 and the barrier bar 90, the gate conductive structure 31 is in contact with one end of the gate bar 30 in the third direction Z (for example, one end of the semiconductor column 10 in the third direction Z away from the capacitor structure 70 in the embodiment below), and the gate conductive structure 31 is adjacent to the barrier bar 90.
  • the gate conductive structure 31 connected to the gate bar 30 and the barrier bar 90 contacted by the shielding bar 20 are on the same side in the third direction Z, and the gate conductive structure 31 is adjacent to the barrier bar 90 along the second direction Y.
  • the constituent material of the gate conductive structure 31 may include a conductive material, and the conductive material includes but is not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof.
  • the semiconductor device 100 further includes: a gate lead contact 32 located at one end of the semiconductor pillar array in the third direction Z, and the gate lead contact 32 is connected to the gate conductive structure 31 .
  • each gate conductive structure 31 is connected to a gate lead-out contact 32 at one end away from the gate bar 30 in the third direction Z, that is, the gate lead-out structure is located between the gate lead-out contact 32 and the gate bar 30 in the third direction Z.
  • the constituent material of the gate lead contact 32 may include a conductive material, including but not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide or any combination thereof.
  • the gate lead contact 32 and the gate conductive structure 31 may be made of the same material or different materials. The present application uses the gate lead contact 32 and the gate conductive structure 31 to lead out the connection of the gate strip 30, which is beneficial to the process flow and Can improve reliability.
  • the semiconductor device 100 further includes: a shielding lead-out contact 21 located at the one end of the semiconductor pillar array in the third direction Z, and the shielding lead-out contact 21 is connected to the shielding bar 20 .
  • the shielding strip 20 is connected to a shielding lead-out contact 21 at one end in the third direction Z.
  • the shielding lead-out contact 21 passes through the barrier strip 90 along the third direction Z, and the shielding lead-out contact 21 is in contact and connected with one end of the shielding strip 20 in the third direction Z (for example, one end of the semiconductor column 10 in the third direction Z away from the capacitor structure 70 in the embodiment below) through the barrier strip 90.
  • the shielding lead-out contact 21 connected to the shielding strip 20 and the barrier strip 90 connected to the shielding strip 20 are on the same side in the third direction Z, and the shielding lead-out contact 21 and the shielding strip 20 are located on opposite sides of the barrier strip 90 along the third direction Z.
  • the component material of the shielding lead-out contact 21 may include a conductive material, and the conductive material includes but is not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide or any combination thereof.
  • the shielding lead-out contact 21 and the shielding bar 20 may be made of the same material or different materials.
  • the shielding lead-out contact 21 of the present application is electrically interconnected with the shielding bar 20, and a fixed voltage is applied to the shielding bar 20 through the shielding lead-out contact 21, that is, the shielding lead-out contact 21 can be connected to the common end so that the shielding bar 20 plays a shielding role.
  • the common terminal may include a low voltage terminal and a ground terminal, wherein the low voltage may include -0.5V, -1V, etc.
  • the shielding bar 20 is connected to the common terminal. In practical applications, the shielding bar 20 can be set to be powered separately without being connected to the common terminal according to needs. In some embodiments of the present application, a low voltage is applied to the shielding bar 20 or the shielding bar 20 is grounded so that the shielding bar 20 can shield the interference between adjacent semiconductor columns 10.
  • the semiconductor device 100 further includes: a semiconductor column lead-out contact 11 located at the one end of the semiconductor column array in the third direction Z, and the semiconductor column lead-out contact 11 is connected to the semiconductor column 10 .
  • one end of the semiconductor column 10 in the third direction Z is connected to a semiconductor column lead-out contact 11.
  • the semiconductor column lead-out contact 11 passes through the cover along the third direction Z.
  • the barrier strip 90 covering the semiconductor column 10 allows the semiconductor column lead-out contact 11 to pass through the barrier strip 90 and contact and connect with one end of the semiconductor column 10 in the third direction Z (for example, the end of the semiconductor column 10 away from the capacitor structure 70 in the following embodiment in the third direction Z).
  • the semiconductor column lead-out contact 11 connected to the semiconductor column 10 and the barrier strip 90 connected to the semiconductor column 10 are on the same side in the third direction Z, and the semiconductor column lead-out contact 11 is connected to one end of the shielding strip 20 along the third direction Z.
  • the first blocking portion 90 a connected to one end of the semiconductor pillar 10 along the third direction Z shown in FIG. 28 may be removed.
  • the constituent material of the semiconductor column lead-out contact 11 may include a conductive material, and the conductive material includes but is not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide or any combination thereof.
  • the material of the semiconductor column lead-out contact 11 and the semiconductor column 10 may be the same or different.
  • the semiconductor column lead-out contact 11 of the present application is electrically interconnected with the semiconductor column 10, and one end of multiple semiconductor columns 10 along the third direction Z can be connected to the same bit line BL through the semiconductor column lead-out contact 11.
  • the semiconductor column lead-out contact 11 can also be replaced to form a bit line BL, that is, the embodiment of the present application can lead out the connection of the bit line BL through the semiconductor column lead-out contact 11, or it can not lead out the connection of the bit line BL through the semiconductor column lead-out contact 11, that is, the bit line BL adjacent to it can be directly formed at one end of the multiple semiconductor columns 10 along the third direction Z.
  • a semiconductor column lead-out contact 11 is formed at the bottom of each of the plurality of semiconductor columns 10 arranged in an array, and the corresponding semiconductor column 10 can be led out through the plurality of semiconductor column lead-out contacts 11 arranged at intervals along the first direction X and the second direction Y as shown in FIG35, that is, eight columns of semiconductor column lead-out contacts 11 are respectively connected to the first bit line BL1 to the eighth word line BL8 in sequence.
  • the number of semiconductor column lead-out contacts 11 in the embodiment of the present application is only an example, and other numbers of semiconductor column lead-out contacts 11 are also within the protection scope of the present application.
  • the semiconductor device 100 may further include an insulating layer 91 extending along the second direction Y and located at the one end of the semiconductor pillar array in the third direction Z. As shown in FIG32 , in the third direction Z, the insulating layer 91 covers the barrier strip 90 , the gate conductive structure 31 , the gate lead contact 32 , the shield lead contact 21 and the semiconductor pillar lead contact 11 .
  • the semiconductor device 100 may further include an isolation layer 80 extending along the second direction Y and located at the one end of the semiconductor column array in the third direction Z.
  • the isolation layer 80 covers the end of the semiconductor column 10 in the third direction Z away from the capacitor structure 70 of the following embodiment, that is, as shown in FIG32 , the isolation layer 80 and the insulating layer 91 are respectively located on opposite sides of the barrier strip 90 in the third direction Z, and the isolation layer 80 covers each semiconductor column 10, and the insulating layer 91 covers the barrier strip 90, the gate conductive structure 31, the gate lead contact 32, the shield lead contact 21 and the semiconductor column lead contact 11 located on the same side in the third direction Z.
  • the constituent materials of the isolation layer 80 and the insulating layer 91 may both include any one or a combination of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, polysiloxane or polysilazane.
  • the materials of the isolation layer 80 and the insulating layer 91 may be the same or different.
  • the semiconductor device 100 further includes:
  • a plurality of gate bars 30 arranged at intervals between the rows of semiconductor pillars 10 along the third direction Y;
  • a plurality of the shielding bars 20 arranged at intervals between the rows of semiconductor pillars 10 along the third direction Y and arranged at intervals staggered with the plurality of gate bars 30;
  • the plurality of gate conductive structures 31 are arranged at intervals between the rows of semiconductor pillars 10 along the third direction Y.
  • a plurality of semiconductor columns 10 are arranged at intervals along the first direction X, and a plurality of semiconductor columns 10 are arranged at intervals along the second direction Y, that is, a plurality of semiconductor columns 10 are arranged in an array along the first direction X and the second direction Y.
  • a plurality of semiconductor columns 10 are arranged in an array along the first direction X and the second direction Y, and the gate bars 30 in the semiconductor columns 10 adjacent to each other in the second direction Y are located on one side of each semiconductor column 10, that is, a plurality of the gate bars 30 are arranged at intervals between each row of semiconductor columns 10 along the third direction Y, and a plurality of the gate bars 30 are located on one side of the semiconductor column 10 along the second direction Y.
  • the shield bars 20 in the semiconductor columns 10 adjacent to each other in the second direction Y are located on the other side of each semiconductor column 10.
  • the plurality of shielding bars 20 are arranged at intervals between the rows of semiconductor columns 10 along the third direction Y, and the plurality of shielding bars 20 are located on the other side of the semiconductor column 10 along the second direction Y.
  • the plurality of gate bars 30 and the plurality of shielding bars 20 are arranged alternately along the second direction Y, and there is a gap between the gate bars 30 and the shielding bars 20 in adjacent semiconductor columns 10 along the second direction Y.
  • the semiconductor structure is further provided with a plurality of barrier strips 90 extending along the first direction X, each shielding strip 20 is connected to its own barrier strip 90 at one end in the third direction Z, and the barrier strips 90 to which the plurality of shielding strips 20 are respectively connected are all located at the same end in the third direction Z.
  • the blocking strip 90 is in contact and connected with one end of the shielding strip 20 in the third direction Z (for example, one end of the semiconductor column 10 in the third direction Z away from the capacitor structure 70 in the following embodiment), the blocking strip 90 is located on the same side of the shielding strip 20 and the gate strip 30 in the third direction Z, and the blocking strip 90 and the gate strip 30 are spaced apart in the second direction Y.
  • the gate strip 30 and the shielding strip 20 between adjacent semiconductor columns 10 along the second direction Y can be isolated by the blocking strip 90, and because the blocking strip 90 has an insulating function, the shielding strip 20 in contact and connected with the blocking strip 90 can play a shielding role, thereby improving the coupling effect between adjacent transistors in the second direction Y, reducing interference between adjacent transistors, and improving the yield and reliability of the memory.
  • a plurality of barrier strips 90 may be located on one side of the semiconductor column 10 along the second direction Y.
  • a plurality of barrier strips 90 may be located on the other side of the semiconductor column 10 along the second direction Y. It should be noted that the constituent materials of the barrier strips 90 may refer to the above embodiments, and will not be described one by one here.
  • the first transistor T1 includes a gate bar 30a and a semiconductor column 10a
  • the second transistor T2 includes a gate bar 30b and a semiconductor column 10b.
  • a shielding bar 20 connected to the barrier bar 90 is provided between the semiconductor column 10a and the semiconductor column 10b.
  • the shielding bar 20 connected to the barrier bar 90 can improve the coupling effect between the first transistor T1 and the second transistor T2, that is, when the first transistor T1 is turned on, the semiconductor column 10a region of the first transistor T1 becomes a high voltage, and the shielding bar 20 located between the first transistor T1 and the second transistor T2 will shield the interference between the electrons in the semiconductor column 10a of the first transistor T1 and the electrons in the semiconductor column 10b of the second transistor T2, thereby reducing the first transistor T1 being turned on.
  • each gate bar 30 is connected to a gate conductive structure 31 at one end in the third direction Z, and the gate conductive structures 31 to which the multiple gate bars 30 are respectively connected are all located at the same end in the third direction Z, wherein the gate conductive structure 31 is located between the gate bar 30 and the barrier bar 90 along the third direction Z, the gate conductive structure 31 is in contact and connected with one end of the gate bar 30 in the third direction Z (for example, one end of the semiconductor column 10 in the third direction Z away from the capacitor structure 70 in the embodiment below), and the gate conductive structure 31 is adjacent to the barrier bar 90 along the second direction Y.
  • multiple gate conductive structures 31 along the second direction Y may be located on one side between adjacent semiconductor pillars 10, and multiple barrier strips 90 along the second direction Y are located on the other side between adjacent semiconductor pillars 10.
  • multiple gate conductive structures 31 along the second direction Y may be located on the other side of the semiconductor pillar 10, and multiple barrier strips 90 along the second direction Y are located on one side between adjacent semiconductor pillars 10.
  • the gate conductive structure 31 and the barrier strips 90 are located on the same side of the semiconductor pillar 10 along the third direction Z, and the gate conductive structure 31 and the barrier strips 90 are located on different sides of the adjacent semiconductor pillars 10 along the second direction Y.
  • the constituent materials of the gate conductive structure 31 can refer to the above embodiments, and will not be described one by one here.
  • the semiconductor device 100 further includes a plurality of gate lead contacts 32 , one gate lead contact 32 corresponds to one gate conductive structure 31 , and the plurality of gate lead contacts 32 are synchronously spaced and arranged along the first direction X and the second direction Y in a stepped distribution.
  • the semiconductor device 100 further includes a plurality of shielding lead-out contacts 21 , one shielding lead-out contact 21 corresponds to one shielding bar 20 , and the plurality of shielding lead-out contacts 21 are synchronously arranged and spaced along the first direction X and the second direction Y in a stepped distribution.
  • the semiconductor device 100 includes gate lead contacts 32a, gate lead contacts 32b, gate lead contacts 32c and gate lead contacts 32d arranged simultaneously or synchronously in the order of arrangement of the four gate bars 30 in the examples shown in FIG. 30 and FIG. 32, so as to be arranged in a stepped manner.
  • the semiconductor device 100 includes the gate lead contacts 32a, gate lead contacts 32b, gate lead contacts 32c and gate lead contacts 32d in the first direction X and the second direction Y as shown in FIG. 32 and FIG. 34.
  • the arrangement order of the four shielding strips 20 is the shielding lead-out contact 21a, shielding lead-out contact 21b, shielding lead-out contact 21c and shielding lead-out contact 21d arranged simultaneously or synchronously at intervals, so as to be arranged in a stepped manner, and the gate lead-out contact 32 is located at one end of a gate strip 30 between adjacent semiconductor pillars 10 along the third direction Z away from the capacitor structure 70 in the following embodiment, and the shielding lead-out contact 21 is located at one end of a shielding strip 20 between adjacent semiconductor pillars 10 along the third direction Z away from the capacitor structure 70 in the following embodiment.
  • the constituent materials of the gate lead-out contact 32 and the shielding lead-out contact 21 can refer to the above embodiments, and will not be repeated here one by one.
  • the semiconductor device 100 also includes a plurality of gate lead-out contacts 32 and a plurality of shield lead-out contacts 21, one of the gate lead-out contacts 32 corresponds to one of the gate conducting structures 31, one of the shield lead-out contacts 21 corresponds to one of the shielding strips 20, and the plurality of gate lead-out contacts 32 and the plurality of shield lead-out contacts 21 are arranged in an alternating manner along the second direction Y.
  • each gate bar 30 is connected to a gate conducting structure 31 on a side of the second direction Y close to the isolation structure 50 in the following embodiment, and one of the gate conducting structures 31 is correspondingly connected to one of the gate lead-out contacts 32.
  • Four gate bars 30 are led out through four spaced-apart gate lead-out contacts 32 and their respectively connected gate conducting structures 31, that is, the four gate bars 30 are respectively connected to the first word line WL1, the second word line WL2, the third word line WL3 and the fourth word line WL4 in sequence.
  • each shielding bar 20 is connected to a barrier bar 90 on one side of the isolation structure 50 in the following embodiment along the second direction, and one shielding bar is correspondingly connected to one shielding lead-out contact 21, and four shielding bars 20 are led out through four shielding lead-out contacts 21 arranged at intervals, that is, the four shielding bars 20 are respectively connected to the first plate line PL1, the second plate line PL2, the third plate line PL2 and the fourth plate line PL4.
  • a certain fixed voltage can be applied to the shielding bar 20 connected to it through the plate line PL (Plate Line) so that the shielding bar 20 can shield the interference between adjacent semiconductor columns 10.
  • the number of gate lead-out contacts 32 and shielding lead-out contacts 21 in the diagram of the embodiment of the present application is only an example, and other numbers of semiconductor column lead-out contacts 11 are also within the protection scope of the present application.
  • the semiconductor device 100 also includes a plurality of gate lead-out contacts 32 and a plurality of shield lead-out contacts 21, one gate lead-out contact 32 corresponds to one gate conductive structure 31, one shield lead-out contact 21 corresponds to one shielding bar 20, and the plurality of gate lead-out contacts 32 and the plurality of shield lead-out contacts 21 are synchronously staggered and arranged along the first direction X and the second direction Y in a stepped distribution.
  • FIG34 Exemplarily, as shown in FIG34 , four gate bars 30 and four shield bars 20 can also be led out with reference to FIG31 .
  • the difference between FIG34 and FIG31 is that the multiple gate lead contacts 32 and the multiple shield lead contacts 21 in FIG34 are staggered and arranged in a stepped manner along the second direction Y.
  • a cross-sectional dimension of the semiconductor pillar 10 in the second direction Y is equal to a spacing dimension between two adjacent semiconductor pillars 10 .
  • the cross-sectional dimension L2 of each semiconductor column 10 in the second direction Y is equal to the spacing dimension L1 between adjacent semiconductor columns 10. Due to the process precision control, the equal in this embodiment includes approximately equal to or approximately equal to.
  • two electrodes namely a first electrode and a second electrode, are formed between adjacent semiconductor columns 10, and a barrier strip 90 extending along the first direction X and connected to the second electrode is formed at the same end of the first electrode and the second electrode in the third direction Z, so that the first electrode can be used as a gate strip 30, and the second electrode can be used as a shielding strip 20, and there is no need to directly form an air gap or other shielding isolation structure 50 between adjacent semiconductor columns 10.
  • the shielding strip 20 can be formed at the same time as the gate strip 30 through the barrier strip 90, so that the interference of the gate strip 30 on the adjacent semiconductor columns 10 can be shielded, thereby reducing the coupling effect between adjacent semiconductor columns 10.
  • the cross-sectional dimension L2 of each semiconductor column 10 in the second direction Y is equal to the spacing dimension L1 between adjacent semiconductor columns 10, which reduces the load effect and reduces the difficulty of process control.
  • a difference between a cross-sectional dimension of the semiconductor pillar 10 in the second direction Y and a spacing dimension between two adjacent semiconductor pillars 10 is smaller than a preset value.
  • the cross-sectional dimension L2 of each semiconductor pillar 10 along the second direction Y is equal to the dimension L1 of the interval between adjacent semiconductor pillars 10.
  • the difference is smaller than the set value based on the accuracy requirement of the process or equipment, or the product requirement.
  • the absolute value of the difference between the interval dimension L1 and the cross-sectional dimension L2 is smaller than and other feasible values, that is,
  • the semiconductor device 100 further includes:
  • a first oxide layer 41 located between the semiconductor column 10 and the gate bar 30 and between the semiconductor column 10 and the shield bar 20;
  • An isolation structure 50 is located between the gate bar 30 and the shield bar 20 .
  • the semiconductor device 100 further includes a first oxide layer 41 and an isolation structure 50.
  • a first oxide layer 41 is provided between the semiconductor column 10 and the gate bar 30 along the second direction Y
  • a first oxide layer 41 is provided between the semiconductor column 10 and the shielding bar 20 along the second direction Y
  • an isolation structure 50 is provided between the gate bar 30 and the shielding bar 20 along the second direction Y.
  • the semiconductor column 10, the first oxide layer 41, the gate bar 30, the isolation structure 50, the shielding bar 20, the first oxide layer 41 and the semiconductor column 10 are arranged in sequence along the second direction Y.
  • a gate bar 30 and a shield bar 20 are disposed between adjacent semiconductor columns 10 in the second direction Y, and the spacing distance between the semiconductor column 10 and the shield bar 20 is the same as the spacing distance between the adjacent semiconductor column 10 and the gate bar 30. That is, in the second direction Y, a gate bar 30 and a shield bar 20 are respectively located on different side walls of adjacent semiconductor columns 10, and the positions of the shield bar 20 and the gate bar 30 are mirror-symmetrical.
  • the first isolation structure 206 is located in the middle position between two adjacent gates 201 along the second direction Y, and a first isolation structure 206 is provided in the middle position of adjacent channel regions 204 in the second direction Y, that is, the first isolation structure 206 is at the same distance from the adjacent channel regions 204 in the second direction Y, and the first isolation structure 206 is at the same distance from the adjacent gates 201 in the second direction Y.
  • the present application forms a gate trench K2 synchronously as shown in FIGS.
  • 11 to 28 deposits a first electrode and a second electrode on different sidewalls of the gate trench along the second direction Y, and forms a barrier strip 90 on one side of the second electrode located on one sidewall along the third direction Z, so that the second electrode connected to the barrier strip 90 is A shielding strip 20 having a shielding effect is formed, so that the first electrode not connected to the barrier strip 90 forms a gate strip.
  • an additional groove is dug between adjacent transistors to obtain an isolation groove for forming a first isolation structure 206.
  • the present application directly utilizes a plurality of equally spaced gate grooves to form a mirror-symmetrically arranged conductive layer to cooperate with the barrier strip to form the gate strip 30 and the shielding strip 20, thereby reducing the difficulty of process control, and can also enhance the strength of the semiconductor column 10 and improve the anti-dumping ability of the semiconductor device 100.
  • the constituent material of the first oxide layer 41 may include silicon oxide, silicon oxynitride, and the like.
  • the constituent material of the isolation structure 50 may include any one or a combination of multiple insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, polysiloxane or polysilazane.
  • the semiconductor device 100 further includes: a capacitor array 71 located at the other end of the semiconductor column array in the third direction Z, the capacitor array 71 including a plurality of capacitor structures 70 arranged in an array along the first direction X and the second direction Y and extending in the third direction Z, the capacitor structure 70 including a first electrode layer (not shown in the figure) connected to the other end of the semiconductor column 10 in the third direction Z, and a capacitor dielectric layer (not shown in the figure) and a second electrode layer (not shown in the figure) located in the first electrode layer.
  • the semiconductor device 100 further includes a capacitor array 71, the capacitor array 71 includes a plurality of capacitor structures 70 extending in the third direction Z, the plurality of capacitor structures 70 are arrayed along the first direction X and the second direction Y, and the other end of each semiconductor column 10 along the third direction Z (i.e., the ends of the semiconductor column 10 connected to the barrier strip 90 and the gate conductive structure 31 in the above embodiment are opposite ends along the third direction Z) is connected to a capacitor structure 70. Furthermore, each capacitor structure 70 includes a first electrode layer connected to the source of the semiconductor column 10.
  • the sidewalls of the semiconductor columns 10 of the semiconductor array are formed with gate bars 30, and the gate bars 30 of the semiconductor columns 10 in the same row (i.e., the semiconductor columns 10 arranged at intervals along the second direction Y) are connected to form a word line, and the semiconductor columns 10 of the transistor array form a source (not shown in the figure) at one end along the third direction Z, and the source is connected to the first electrode layer of the capacitor structure 70, and the semiconductor columns 10 of the transistor array are connected along the third direction Z.
  • the other end in the third direction Z forms a drain (not shown in the figure), and the drains of the semiconductor pillars 10 in the same row (i.e., the semiconductor pillars 10 arranged at intervals along the first direction X) are connected to form a bit line BL (not shown in the figure).
  • the semiconductor pillars 10 extend along the third direction Z, and the source and the drain are respectively formed at the opposite ends of the semiconductor pillars 10 along the third direction Z.
  • the capacitor structure 70 and the bit line BL are respectively located on the opposite sides of the semiconductor pillars 10 along the third direction Z, so that they can be manufactured on both sides of the substrate 1, thereby improving the process manufacturing efficiency.
  • the source and the drain of the semiconductor column 10 are relative concepts, and the source and the drain can be any surface of the semiconductor column 10 along the third direction Z.
  • a capacitor structure 70 and a transistor constitute a DRAM storage unit, and the selection and non-selection of the connected capacitor structure 70 are realized by turning the transistor on and off, thereby realizing the read, write or erase operation of the selected storage unit.
  • the embodiment of the present application does not limit the number of capacitor structures 70 and transistors, and the capacitor array 71 can be coupled with a transistor array (including a plurality of transistors arranged in an array along a first direction X and a second direction Y) to form a DRAM array storage structure.
  • the source and drain of a transistor are relative concepts, which are related to the way the transistor is actually connected to the circuit, and have nothing to do with the physical position of the source and drain in the transistor.
  • the input end of the transistor connected to the circuit can be used as the source, and the output end can be used as the drain, and the carriers flow from the source to the drain.
  • one end of the transistor coupled to the capacitor structure 70 is used as the drain, and the source of the transistor can be coupled to the bit line BL to which the operating voltage is applied.
  • the present application also provides a method for manufacturing a semiconductor device 100.
  • the semiconductor device 100 in the above embodiment can be manufactured by the following method for manufacturing a semiconductor device 100.
  • FIG37 is a flow chart of the method for manufacturing a semiconductor device 100 in the present application, as shown in FIG37, including:
  • the step of forming a plurality of semiconductor pillars 10 includes:
  • the substrate 1 is a material used to make the semiconductor device 100, and the material of the substrate 1 may include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI) or any suitable combination thereof.
  • the substrate 1 may include a wafer formed by grinding, polishing, and slicing cylindrical single crystal silicon.
  • a first dielectric layer 14 covering the substrate 1 is first deposited along a third direction Z, and then a second oxide layer (liner oxide) 13 covering the first dielectric layer 14 is deposited along the third direction Z under high temperature conditions to repair the surface of the substrate 1, so as to form a structure in which the substrate 1, the first dielectric layer 14, and the second oxide layer 13 are stacked in sequence along the third direction Z as shown in FIGS. 3 and 4.
  • the constituent materials of the second oxide layer 13 and the first dielectric layer 14 may include any one or more of silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride.
  • a plurality of isolation trenches K1 may be formed in the substrate 1, or a plurality of isolation trenches K1 may be formed in the structure shown in FIGS. 3 and 4 as shown in FIGS. 5 and 6. As shown in FIGS. 5 and 6, a plurality of isolation trenches K1 extend along the second direction Y and are arranged at intervals along the first direction X, and the isolation trenches K1 extend along the third direction Z but do not penetrate the substrate 1.
  • the step of forming the isolation trench K1 includes: etching from the surface of the second oxide layer 13 as shown in FIG. 4 to form the isolation trenches K1 extending along the third direction Y and arranged at intervals along the first direction X, and the isolation trenches K1 can extend along the third direction Z to the substrate 1 but do not penetrate the substrate 1.
  • a mask (not shown in the figure) can be used to cover part of the surface of the substrate 1 or the second oxide layer 13, that is, the areas where the isolation trench K1 needs to be formed. Then, the surface of the substrate 1 is etched along the thickness direction of the substrate 1 (that is, the third direction Z).
  • the substrate 1, the first dielectric layer 14 and the second dielectric layer 13 are A portion of the oxide layer 13 is etched away to form a groove of a certain depth, namely the isolation groove K1. It should be noted that the etching depth of the isolation groove K1 is less than the initial thickness of the substrate 1, that is, the etching process will not etch through the substrate 1.
  • etching can be performed using processes such as photolithography (PH) or dry etching (ET), for example, electron beam lithography, plasma etching or reactive ion etching, which are not limited in some embodiments of the present application.
  • PH photolithography
  • ET dry etching
  • the manufacturing process can be simplified and the efficiency can be improved.
  • FIG7 is a top view of depositing a dielectric material 42 in an isolation trench K1 provided in some embodiments of the present application
  • FIG8 is a cross-sectional view of depositing a dielectric material 42 in an isolation trench K1 provided in some embodiments of the present application.
  • dielectric material 42 includes but is not limited to any one or a combination of silicon nitride, silicon oxide or silicon oxynitride.
  • Silicon oxide here refers to silicon oxide compounds, such as SixOy
  • silicon nitride refers to silicon nitrogen compounds, such as SixNy.
  • the isolation trenches K1 are formed as shown in FIG5 and FIG6, and the plurality of isolation trenches K1 are arranged at intervals along the first direction X, there will be a protruding structure 211 for spacing two adjacent isolation trenches K1 between the isolation trenches K1 formed by removing part of the semiconductor material in the substrate 1. It should be noted that in the actual process of depositing the dielectric material 42, the dielectric material 42 will cover the surface of the protruding structure 211. As shown in FIG7, the dielectric material 42 is filled around each protruding structure 211. In addition, after the deposition is completed, a chemical mechanical polishing (CMP) process can be used to polish and remove the excess dielectric material 42 to achieve planarization.
  • CMP chemical mechanical polishing
  • the deposition method of the dielectric material 42, the first dielectric layer 14, and the second oxide layer 13 can be, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, organic metal chemical vapor deposition, etc. (Metal-organic emical vapor deposition, MOCVD) and atomic layer deposition (Atomic layer deposition, ALD), etc.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • PECVD plasma-enhanced chemical vapor deposition
  • sputtering organic metal chemical vapor deposition, etc.
  • MOCVD Metal-organic emical vapor deposition
  • ALD atomic layer deposition
  • a plurality of gate trenches K2 extending along the first direction X and arranged at intervals along the third direction Y are formed, and a plurality of semiconductor pillars 10 extending along the first direction X and arranged at intervals along the third direction Y and extending in the third direction Z are formed.
  • gate trenches K2 extending along the first direction X and arranged at intervals along the second direction Y are formed in the substrate 1, and the semiconductor pillars 10 along the second direction Y are located between adjacent gate trenches K2.
  • the isolation trench K1 filled with the dielectric material 42 extends along the second direction Y and is arranged at intervals along the first direction X, and the gate trenches K2 extend along the first direction X and are arranged at intervals in the second direction Y, the isolation trench K1 filled with the dielectric material 42 can be divided into a plurality of semiconductor pillars 10 arranged in an array in the first direction X and the third direction Y and extending in the third direction Z through the gate trenches K2.
  • the sizes of the plurality of gate trenches K2 arranged at intervals in the second direction Y along the first direction X may be the same or different.
  • the gate trenches K2a and the gate trenches K2b are arranged alternately at intervals along the third direction Y, and the size of the gate trenches K2a along the first direction X is greater than the size of the gate trenches K2b along the first direction X.
  • the size of the gate trench K2 formed by etching along the second direction Y is equal to the size of the semiconductor pillar 10 along the third direction Y.
  • the step of forming a gate strip 30 and a shield strip 20 includes:
  • a first oxide layer 41 may be formed in the sidewall of the gate trench K2 as shown in FIGS. 11 and 12 .
  • the first oxide layer 41 may be formed by a thermal oxidation method (RTO, Rapid Thermal Oxidation) or an in-situ steam generation method.
  • RTO Rapid Thermal Oxidation
  • the exposed sidewalls of the semiconductor column 10 are oxidized through the gate trench K2, and a first oxide layer 41 is formed on the sidewalls of the semiconductor column 10, i.e., the sidewalls of the gate trench K2.
  • the process of oxidizing the sidewalls of the semiconductor column 10 exposed in the gate trench K2 includes, but is not limited to, direct oxidation, alkaline oxidation, or acidic oxidation.
  • direct oxidation is performed by heating, so that the silicon on the sidewall of the semiconductor pillar 10 reacts chemically with the gas containing the oxidizing substance at high temperature, thereby generating a dense silicon dioxide film on the silicon surface, forming a first oxide layer 41 located on the sidewall of the semiconductor pillar 10.
  • the first oxide layer 41 includes insulating materials such as silicon oxide and silicon oxynitride.
  • a conductive layer 66 is deposited on the sidewall of the first oxide layer 41 , and the material of the conductive layer includes but is not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide or any combination thereof.
  • the deposition method of the conductive material may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD), etc.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • PECVD plasma-enhanced chemical vapor deposition
  • MOCVD metal-organic chemical vapor deposition
  • ALD atomic layer deposition
  • barrier bar 90 at one end of the shielding bar 20 along the third direction Z, wherein the barrier bar 90 extends along the first direction X and is located on the same side of the shielding bar 20 and the gate bar 30 in the third direction Z.
  • the gate strip 30 and the shield strip 20 formed in the gate trench K2 are adjacent to each other in the third direction Y, and the gate bar 30 and the shield bar 20 are respectively located on one side of the semiconductor column 10 adjacent thereto.
  • the semiconductor column 10a and the semiconductor column 10b are adjacent to each other in the third direction Y
  • a gate bar 30 and a shield bar 20 are provided between the semiconductor column 10a and the semiconductor column 10b
  • the gate bar 30 is located on one side close to the semiconductor column 10b along the third direction Y
  • the shield bar 20 in the gate bar 30 is located on one side close to the semiconductor column 10a along the third direction Y.
  • the steps of forming the barrier strip 90 specifically include: as shown in FIG. 23 , depositing an isolation layer 80 along the third direction Z at one end of the semiconductor column 10 away from the capacitor array 71; as shown in FIG. 24 , doping the exposed gate strip 30 and the shield strip 20 by processes such as ion implantation (IMP Process), such as N-type doping, and the N-type doping may include any suitable N-type dopant (e.g., phosphorus (P), arsenic (Ar) or antimony (Sb)) to contribute free electrons and increase the conductivity of the gate strip 30 and the shield strip 20.
  • IMP Process ion implantation
  • N-type doping may include any suitable N-type dopant (e.g., phosphorus (P), arsenic (Ar) or antimony (Sb)) to contribute free electrons and increase the conductivity of the gate strip 30 and the shield strip 20.
  • a barrier layer 92 covering the semiconductor column 10, the gate bar 30 and the shielding bar 20 is formed based on a deposition process, and the barrier layer 92 extends along the second direction Y.
  • the portion of the barrier layer 92 connected to the shielding bar 20 in Figure 25 is removed to form a groove K3 as shown in Figure 26, so that the remaining barrier layer 92 after removing the portion connected to the shielding bar 20 forms a barrier bar 90 extending along the first direction X as shown in Figure 26, and the barrier bar 90 is connected to one end of the shielding bar 20 in the third direction Z, and the barrier bar 90 is at the same end of the shielding bar 20 and the gate bar 30 in the third direction Z.
  • two electrodes namely a first electrode and a second electrode
  • a barrier strip 90 extending along the first direction X and connected to the second electrode is formed at the same end of the first electrode and the second electrode in the third direction Z, so that the first electrode can be used as a gate strip 30, and the second electrode can be used as a shielding strip 20.
  • the shielding strip 20 can be formed at the same time as the gate strip 30 through the barrier strip 90, so that the interference of the gate strip 30 on the adjacent semiconductor pillars 10 can be shielded, thereby reducing the coupling effect between the adjacent semiconductor pillars 10.
  • the manufacturing method further includes: as shown in FIG. 15 , FIG. 17 and FIG. 18 , filling the gate trench K2 with an isolation material 55 , and making the isolation material 55 cover the gate bar 30 and the shielding bar 20 to form an isolation structure 50 .
  • the material of the isolation material 55 includes but is not limited to any one of silicon nitride, silicon oxide or silicon oxynitride or any combination of multiple thereof.
  • the deposition method of the isolation material 55 may be but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD).
  • the manufacturing method further comprises:
  • a capacitor array 71 is formed at the other end of the semiconductor column array in the third direction Z, and the capacitor array 71 includes a plurality of capacitor structures 70 arranged in an array along the first direction X and the second direction Y and extending in the third direction Z.
  • the capacitor structure 70 includes a first electrode layer (not shown in the figure) connected to the other end of the semiconductor column 10 in the third direction Z, and a capacitor dielectric layer (not shown in the figure) and a second electrode layer (not shown in the figure) located in the first electrode layer.
  • a capacitor array 71 is formed at the other end of the semiconductor pillar array in the third direction Z, and as shown in FIG. 20 , a portion of the substrate 1 away from the capacitor array 71 along the third direction Z is removed.
  • the manufacturing method further comprises:
  • one end of the substrate 1 in the third direction Z away from the capacitor array 71 and the isolation structure 50 located at the bottom of the gate trench K2 are removed, and one end of the gate bar 30 in the third direction Z and one end of the shielding bar 20 in the third direction Z are exposed.
  • a process such as photolithography (PH) or dry etching (ET) can be used to remove one end of the substrate 1 away from the capacitor array 71 in the third direction Z.
  • PH photolithography
  • ET dry etching
  • a part of the isolation material 55 in the isolation structure 50 away from the capacitor array 71 along the third direction Z, that is, a bottom portion 56 of the isolation structure 50 can be removed by dry etching or wet etching.
  • the bottom portion 56 of the isolation structure 50 covers the gate strip 30 away from the capacitor in the third direction Z.
  • the manufacturing method further comprises:
  • a gate conductive structure 31 is formed at the bottom of the gate trench K2 .
  • the gate conductive structure 31 extends along the first direction X and is located at one end of the gate bar 30 and the isolation structure 50 in the third direction Z and is spaced apart from the one end of the shielding bar 20 in the third direction Z.
  • the groove K3 is located at one end of the gate bar 30 and the isolation structure 50 away from the capacitor structure 70 in the third direction Z, and the groove K3 is spaced from one end of the shielding bar 20 away from the capacitor structure 70 in the third direction Z, so that a gate conductive structure 31 is formed in the groove K3 as shown in FIG26, and a gate conductive structure 31 as shown in FIG28 can be formed.
  • the material of the gate conductive structure 31 can refer to the above embodiments, and will not be repeated here.
  • the manufacturing method further comprises:
  • a gate lead contact 32 is formed at one end of the semiconductor pillar array in the third direction Z, and the gate lead contact 32 is connected to the gate conductive structure 31 .
  • an insulating layer 91 is deposited at one end of the semiconductor pillar array away from the capacitor array 71 in the third direction Z, and the insulating layer 91 covers the barrier strip 90 and the gate conductive structure 31. A portion of the insulating layer 91 is removed to form a first trench K4, and a gate lead contact 32 is formed in the first trench K4.
  • the material of the gate lead contact 32 can refer to the above embodiment, and will not be described one by one here.
  • the manufacturing method further comprises:
  • a shielding lead-out contact 21 is formed at the one end of the semiconductor pillar array in the third direction Z, and the shielding lead-out contact 21 is connected to the shielding bar 20.
  • a portion of the insulating layer 91 is removed to form a second groove K5, and a shielding lead-out contact 21 is formed in the second groove K5.
  • the material of the shielding lead-out contact 21 can refer to the above embodiment, and will not be repeated here.
  • the manufacturing method further comprises:
  • a semiconductor column lead-out contact 11 is formed at the one end of the semiconductor column array in the third direction Z, and the semiconductor column lead-out contact 11 is connected to the semiconductor column 10.
  • a portion of the insulating layer 91 is removed to form a third trench K6, and a semiconductor column lead-out contact 11 is formed in the third trench K6.
  • the material of the semiconductor column lead-out contact 11 can refer to the above embodiment, and will not be described one by one here.
  • the step of forming a gate lead contact 32 at one end of the semiconductor pillar array in the third direction Z includes:
  • a plurality of gate lead-out contacts 32 are formed, one gate lead-out contact 32 corresponds to one gate conductive structure 31, and the plurality of gate lead-out contacts 32 are synchronously arranged and spaced along the first direction X and the second direction Y in a stepped distribution.
  • the step of forming the shielding lead-out contact 21 at the one end of the semiconductor pillar array in the third direction Z includes:
  • a plurality of shielding lead-out contacts 21 are formed, one shielding lead-out contact 21 corresponds to one shielding bar 20, and the plurality of shielding lead-out contacts 21 are synchronously arranged and spaced along the first direction X and the second direction Y in a stepped distribution.
  • the manufacturing method also includes forming a plurality of gate lead-out contacts 32 and a plurality of shield lead-out contacts 21, one gate lead-out contact 32 corresponds to one gate conductive structure 31, one shield lead-out contact 21 corresponds to one shielding strip 20, and the plurality of gate lead-out contacts 32 and the plurality of shield lead-out contacts 21 are synchronously and staggeredly arranged along the first direction X and the second direction Y to form a stepped distribution.
  • the manufacturing method also includes forming a plurality of gate lead-out contacts and a plurality of shield lead-out contacts, one gate lead-out contact corresponds to one gate conductive structure, one shield lead-out contact corresponds to one shield strip, and the plurality of gate lead-out contacts and the plurality of shield lead-out contacts are synchronously and staggeredly arranged along the first direction and the second direction.
  • the step of forming a plurality of semiconductor pillars 10 includes making the cross-sectional dimensions of the semiconductor pillars 10 in the second direction Y equal to the cross-sectional dimensions between two adjacent semiconductor pillars 10. The difference in interval size is smaller than the preset value.
  • a patterned first mask layer (not shown) is formed on the surface of the insulating layer 91 away from the capacitor array 71 along the third direction Z, and the first mask layer has a plurality of first openings (not shown) and second openings (not shown), the first openings are used to form the first groove K4, and the second openings are used to form the second groove K5.
  • Openings corresponding to the first groove K4 and the second groove K5 are formed in the patterned first mask layer, and the openings expose the positions of the first groove K4 and the second groove K5 to be etched in the subsequent etching process, that is, the vertical projection of the first opening on the surface of the insulating layer 91 away from the capacitor array 71 along the third direction Z can at least substantially overlap with the position of the first groove K4, and the vertical projection of the second opening on the surface of the insulating layer 91 away from the capacitor array 71 along the third direction Z can at least substantially overlap with the position of the second groove K5.
  • the etching positions of the first trench K4 and the second trench K5 can be quickly and accurately determined, which facilitates etching of the insulating layer 91, thereby forming a gate lead contact 32 in the first trench K4 and a shield lead contact 21 in the second trench K5.
  • a patterned second mask layer (not shown) is formed on the surface of the insulating layer 91 away from the capacitor array 71 along the third direction Z, and the second mask layer has a plurality of third openings (not shown), and the third openings are used to form the third trench K6.
  • An opening corresponding to the second trench K5 is formed in the patterned second mask layer, and the opening exposes the position of the third trench K6 to be etched in the subsequent etching process, that is, the vertical projection of the first opening on the surface of the insulating layer 91 away from the capacitor array 71 along the third direction Z can at least substantially overlap with the position of the third trench K6, and the vertical projection of the third opening on the surface of the insulating layer 91 away from the capacitor array 71 along the third direction Z can at least substantially overlap with the position of the third trench K6.
  • the etching position of the third trench K6 can be determined quickly and accurately, so as to facilitate etching the insulating layer 91 to form the third trench K6 and further form the semiconductor column lead contact 11 in the third trench K6.
  • Some embodiments of the present application provide a semiconductor device 100 and a manufacturing method thereof.
  • a shielding strip 20 is formed between adjacent semiconductor pillars 10 in the semiconductor device 100 formed by the manufacturing method.
  • the shielding strip 20 can prevent interference between adjacent semiconductor pillars 10, thereby reducing the 10 coupling effect.
  • the embodiment of the present application further provides a memory 320, and the memory 320 includes:
  • An array storage structure 321 includes the semiconductor device 100 of the embodiment shown in FIGS. 3 to 36 ; and a peripheral circuit 322 connected to the array storage structure 321 to control the bias voltage of the array storage structure 321 .
  • an embodiment of the present application also provides a storage system 300, the storage system 300 includes a memory 320 as shown in Figure 38, and a controller coupled to the memory 320, the controller is used to control the memory to perform data writing and reading operations.
  • the storage system 300 includes a controller 310 and one or more memories 320, wherein the memory 320 (3D NAND Flash) includes an array storage structure 321 (Array) and a peripheral circuit 322 (Periphery Circuit), wherein the array storage structure 321 includes any of the semiconductor devices 100 described above.
  • the storage system 300 can communicate with the host 400 through the controller 310, wherein the controller 310 can be connected to the one or more memories 320 via channels in the one or more memories 320.
  • Each memory 320 can be managed by the controller 310 via channels in the memory 320.
  • the array storage structure 321 is used to store information
  • the peripheral circuit 322 can be located above or below the array storage structure 321, or can be located around the array storage structure 321, and the peripheral circuit 322 is used to control the corresponding array storage structure 321.
  • the semiconductor device 100 can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), etc., without specific limitation.
  • the semiconductor device 100 of the embodiment of the present application can be a memory 320, and can be a part of a peripheral memory, without special limitation.
  • the semiconductor device 100 and its manufacturing method, memory and storage system 300 provided in the embodiment of the present application are described in detail above.
  • the principle and implementation method of the present application are described in detail using specific examples.
  • the description of the above embodiments is only used to help understand the method and its core idea of the present application.
  • the content of this specification should not be construed as limiting the present application.

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Abstract

本申请公开一种半导体器件及其制作方法、存储器和存储系统；半导体器件包括多个半导体柱；沿第二方向上相邻半导体柱之间设有一栅极条和一屏蔽条；阻隔条沿第一方向延伸，阻隔条与屏蔽条在第三方向上的一端连接，且位于屏蔽条与栅极条在第三方向上的同一侧。本申请可提高良率和可靠性。

Description

半导体器件及其制作方法、存储器和存储系统 技术领域
本申请涉及半导体技术领域，具体涉及一种半导体器件及其制作方法、存储器和存储系统。
背景技术
随着存储单元的特征尺寸接近工艺下限，平面工艺和制造技术变得具有挑战性且成本高昂，这造成2D结构的存储器的存储密度接近上限。
为克服2D结构的存储器带来的限制，业界已经研发了具有三维结构的存储器以提高存储密度。
然而，随着存储器的集成度要求增高，如何妥善安排各种栅极的排布，以减少栅极间的相互干扰，仍是目前有待克服的问题。
发明内容
本申请提供一种半导体器件及其制作方法、存储器和存储系统，可以提高存储器的良率和可靠性。
第一方面，本申请提供一种半导体器件，包括：
半导体柱阵列，所述半导体柱阵列包括沿第一方向与第二方向阵列排布且在第三方向上延伸的多个半导体柱，所述第一方向、所述第二方向、以及所述第三方向彼此相交叉；
沿所述第二方向上相邻所述半导体柱之间设有一栅极条和一屏蔽条，所述栅极条与所述屏蔽条沿所述第一方向延伸并在第二方向上相间隔；以及，
阻隔条，所述阻隔条沿所述第一方向延伸，所述阻隔条与所述屏蔽条在所述第三方向上的一端连接，且位于所述屏蔽条与所述栅极条在所述第三方向上 的同一侧。
第二方面，本申请还提供一种半导体器件的制作方法，包括：
形成多个半导体柱，并使所述多个半导体柱在第一方向与第二方向阵列排布且在第三方向上延伸，且所述第一方向、所述第二方向、以及所述第三方向彼此相交叉；
在相邻的所述第一行半导体柱与所述第二行半导体柱之间，形成一个栅极条与一个屏蔽条，并使所述栅极条与所述屏蔽条沿所述第一方向延伸并在第二方向上相间隔；以及，
在所述屏蔽条沿所述第三方向上的一端形成阻隔条，所述阻隔条沿第一方向延伸，且位于所述屏蔽条与所述栅极条在所述第三方向上的同一侧。
第三方面，本申请还提供一种存储器，所述存储器包括：
阵列存储结构，所述阵列存储结构包括如第一方面所述的半导体器件；以及
外围电路，所述外围电路与所述阵列存储结构相接，以控制所述阵列存储结构的偏压。
第四方面，本申请还提供一种存储系统，包括：如第三方面所述的存储器；以及与所述存储器耦合的控制器，所述控制器用于控制所述存储器执行数据写入和读取操作。
本申请有益效果：本申请在相邻半导体柱之间形成两个电极即第一电极和第二电极，于所述第一电极和第二电极在所述第三方向上的同一端，形成沿所述第一方向延伸且与第二电极连接的阻隔条，这样第一电极可以作为栅极条，第二电极可以作为屏蔽条，在形成栅极条的同时形成屏蔽条，从而可以通过屏蔽条来防止相邻半导体柱之间的干扰，进而降低了相邻半导体柱之间的耦合效应。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的半导体器件中一个存储单元的等效电路图；
图2是本申请实施例提供的半导体器件的一种剖视图；
图3是本申请实施例提供的衬底的俯视图；
图4是本申请实施例提供的衬底的剖视图；
图5是本申请实施例提供的形成隔离沟槽的俯视图；
图6是本申请实施例提供的形成隔离沟槽在图5中AA＇切割线的剖视图；
图7是本申请实施例提供的在隔离沟槽中沉积介质材料的俯视图；
图8是本申请实施例提供的在隔离沟槽在图7中BB＇切割线的剖视图；
图9是本申请实施例提供的形成栅极沟槽的俯视图；
图10是本申请实施例提供的形成栅极沟槽图9中CC＇切割线的剖视图；
图11是本申请实施例提供的在栅极沟槽的侧壁形成第一氧化层的俯视图；
图12是本申请实施例提供的在栅极沟槽的侧壁形成第一氧化层在图11中DD＇切割线的剖视图；
图13是本申请实施例提供的在第一氧化层形成导电层的俯视图；
图14是本申请实施例提供的在第一氧化层形成导电层在图13中EE＇切割线的剖视图；
图15是本申请实施例提供的半导体器件在图12中BB＇切割线的剖视图；
图16是本申请实施例提供的在栅极沟槽的内壁填入隔离材料的一种俯视图；
图17是本申请实施例提供的在栅极沟槽的内壁填入隔离材料在图16中FF＇切割线的剖视图；
图18是本申请实施例提供的在栅极沟槽的内壁填入隔离材料以覆盖栅极条 和屏蔽条的一种剖视图；
图19是本申请实施例提供的形成电容阵列的一种剖视图；
图20至图26是本申请实施例提供的形成阻隔层的制作流程的多个剖视图；
图27是本申请实施例提供的形成阻隔条和栅极导接结构的一种俯视图；
图28是本申请实施例提供的形成阻隔条和栅极导接结构在图27中GG＇切割线的剖视图；
图29至图30是本申请实施例提供的形成栅极引出触点的制作流程的多个剖视图；
图31是本申请实施例提供的一种形成栅极引出触点、屏蔽引出触点的俯视图；
图32是本申请实施例提供的形成栅极引出触点、屏蔽引出触点在图31中HH＇切割线的一种剖视图；
图33和图34是本申请实施例提供的另一种形成栅极引出触点、屏蔽引出触点的制作流程的多个俯视图；
图35是本申请实施例提供的形成半导体柱引出触点的一种俯视图；
图36是本申请实施例提供的形成栅极引出触点、屏蔽引出触点和半导体柱引出触点的剖视图；
图37是本申请实施例提供的半导体器件的制作方法的一种流程图；
图38是本申请实施例提供的存储系统的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本 申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
晶体管可以用于动态随机存储器(DRAM，Dynamic Random Access Memory)中，用于控制每一存储单元中的电容。动态随机存取存储器的基本存储单元结构由一个晶体管和一个存储电容组成，其主要的作用原理是利用电容内存储电荷的多寡来代表一个二进制比特(bit)是l还是0。
随着动态随机存取存储器技术的发展，存储单元的尺寸越来越小，其阵列架构由8F2到6F2再到4F2；另外，基于动态随机存取存储器中对离子和漏电流的需求，存储器的架构从平面阵列晶体管(Planar array transistor)到凹栅阵列晶体管(Recess gate arraytransistor)，又从凹栅阵列晶体管到掩埋式阵列晶体管(Buried saddle Fin arraytransistor)，再从掩埋式阵列晶体管到垂直栅极晶体管(Vertical gate transistor)。
实际应用中，不论是平面晶体管、凹栅阵列晶体管、掩埋式晶体管还是垂直栅极晶体管，动态随机存取存储器均由多个存储单元结构构成，每一个存储单元结构主要是由一个晶体管与一个由晶体管所操控的存储电容构成，即动态随机存取存储器包括1个晶体管(T，Transistor)和1个电容(C，Capacitance)即1T1C的架构；其主要的作用原理是利用电容内存储电荷的多寡来代表一个二进制比特(bit)是l还是0。
图1为本申请实施例中提供的一种采用1T1C的架构的电路连接示意图，如图1所示，晶体管T的漏极与位线(BL，Bite Line)电连接，晶体管T的源极与电容C的其中一个电极板电连接，电容C的另外一个电极板通过接地端(GND，Ground)接地，晶体管T的栅极与字线(WL，Word Line)连接；通过字线WL施加电压控制晶体管T导通或截止，位线BL用于在晶体管T导通时，对所述电容C执行读取或写入操作。
图2为本申请实施例中提供的一种半导体结构200的剖面示意图，本申请实 施例提供了一种半导体结构，如图2所示，所述半导体结构包括：沿Y轴方向并列设置且被第一隔离结构206间隔分开的第一晶体管210和第二晶体管220，所述第一隔离结构206中包括有气隙205(Airgap)；所述第一晶体管210、第二晶体管220均包括：沿Z轴方向延伸的栅极201、沿Z轴方向延伸的沟道区204、位于栅极201与沟道区204之间且沿Z轴方向延伸的的栅氧化层(Gate oxide layer)202、分别位于所述沟道区204沿Z方向相对的两端的源极(图中未示出)和漏极(图中未示出)。栅极201位于所述沟道区204的一侧；其中，所述第一晶体管210的栅极201位于所述沟道区204的两侧中远离所述第一隔离结构206的一侧，所述第二晶体管220的栅极201位于所述沟道区204的两侧中远离所述第一隔离结构206的一侧。
在采用如图2所示的栅极垂直晶体管结构时，由于第一隔离结构206的中间形成气隙205，以改善半导体结构中相邻的第一晶体管210和第二晶体管220容易发生耦合效应的问题，但是该半导体结构对于工艺控制要求高，且容易发生倾倒问题。
为了改善上述问题，参考图3至图38所示，本申请一些实施例提供了一种半导体器件100及其制作方法、存储器320和存储系统300。本申请在相邻半导体柱10之间形成两个电极即第一电极和第二电极，于所述第一电极和第二电极在所述第三方向Z上的同一端，形成沿所述第一方向X延伸且与第二电极连接的阻隔条90，这样第一电极可以作为栅极条30，第二电极可以作为屏蔽条20，在形成栅极条30的同时形成屏蔽条20，从而可以通过屏蔽条20来防止相邻半导体柱10之间的干扰，进而降低了相邻半导体柱10之间的耦合效应。
请参阅图3至图36所示，为本申请一些实施例提供的一种半导体器件100的制作工艺过程示意图，首先就所述半导体器件100作说明，其中，图27为本申请实施例提供的一种半导体结构的一种俯视图，图28为本申请实施例提供的半导体结构在图27中GG＇切割线的一种剖视图，图30为本申请实施例提供的半导体结构在图27中GG＇切割线的另一种剖视图，如图27、图28和图30所示，半导体 器件100包括：
半导体柱阵列，所述半导体柱阵列包括沿第一方向与第三方向阵列排布且在第三方向上延伸的多个半导体柱10，所述第一方向、所述第二方向、以及所述第三方向彼此相交叉；
沿所述第二方向Y上相邻所述半导体柱10之间设有一栅极条30和一屏蔽条20，所述栅极条30与所述屏蔽条20沿所述第一方向X延伸并在第三方向Y上相间隔；以及，
阻隔条90，所述阻隔条90沿所述第一方向X延伸，所述阻隔条90与所述屏蔽条20在所述第三方向Z上的一端连接，且位于所述屏蔽条20与所述栅极条30在所述第三方向Z上的同一侧。
在一些具体示例中，所述第一方向和第三方向之间具有夹角，第三方向与第一方向和第三方向所在平面之间具有夹角，所述夹角范围为：小于或等于90度。例如，本申请的一些实施例中设定第一方向为X方向，第二方向为Y方向，第三方向为Z方向。
如图27所示，多个半导体柱10包括沿第一方向X排布且在所述第二方向Y相邻的第一行半导体柱10a与第二行半导体柱10b。半导体柱10用于在外加电场的作用下传递电荷或者停止电荷的传递，使得晶体管导通或者截止，每一半导体柱10的延伸方向是晶体管导通时的电流方向，示例性的，如图28和图30所示，半导体柱10的延伸方向为第三方向Z，并且多个半导体柱10沿第一方向X和第三方向Y阵列分布以形成半导体柱阵列。
在一些具体示例中，如图27、图28和图30所示，沿第二方向Y上相邻的两个半导体柱10之间设有一个栅极条30和一个屏蔽条20。另外，如图27所示，沿所述第二方向Y上位于相邻所述半导体柱10之间的栅极条30沿第一方向X延伸，沿所述第二方向Y上位于相邻所述半导体柱10之间的屏蔽条20沿第一方向X延伸，并且，沿第二方向Y上每相邻的两个半导体柱10之间的一个栅极条30和一个屏蔽条20相互之间间隔，即相邻的半导体柱10之间栅极条30和屏蔽条20不接 触或具有间距。
在一些具体示例中，如图28和图30所示，半导体结构还设有沿第一方向X延伸的阻隔条90，阻隔条90与屏蔽条20在第三方向Z上的一端接触或连接，并且，阻隔条90与位于所述屏蔽条20与所述栅极条30在所述第三方向Z上的同一侧，即阻隔条90、屏蔽条20中在所述第三方向Z上与阻隔条90连接的一端，以及栅极条30中在第三方向Z上与后文实施例形成的栅极导接结构31连接的一端位于同一侧。这样，就可以通过阻隔条90将沿第二方向Y上相邻半导体柱10之间的栅极条30和屏蔽条20隔离开，并且由于阻隔条90具有绝缘功能，这样，阻隔条90可以更好的隔离屏蔽条20与栅极条30。
在一些具体示例中，如图28和图30所示，阻隔条90位于屏蔽条20与栅极条30之间且与屏蔽条20在第三方向Z上的一端(例如，半导体柱10在第三方向Z上远离下文实施例中的电容结构70的一端)接触连接，并且阻隔条90与栅极条30在第二方向Y上具有间距。
在一些具体示例中，阻隔条90还可以位于所述屏蔽条20与半导体柱10在所述第三方向Z上的同一端，例如，如图28和图30所示，阻隔条90的第一阻隔部分90a位于相邻半导体柱10之间的屏蔽条20和栅极条30在第三方向Z上的同一端，即第一阻隔部分90a连接屏蔽条20在第三方向Z上的一端，阻隔条90的第二阻隔部分90b位于相邻半导体柱10在第三方向Z上的同一端，即第二阻隔部分90b连接半导体柱10在第三方向Z上的一端，并且屏蔽条20在第三方向Z上的一端连接的第一阻隔部分90a和半导体柱10在第三方向Z上的一端连接的第二阻隔部分90b位于第三方向Z上的同一侧。
在一些示例中，如图28和图30所示，第一阻隔部分90a和第二阻隔部分90b。如图28所示第二阻隔部分90b的横截面形状可以是扇形，如图30所示，第二阻隔部分90b的横截面形状可以是矩形。当然，第二阻隔部分90b的横截面形状还可以是倒梯形、弧形等。
在一些实施例中，如图28所示第一阻隔部分90a可以被去除以连接下文实 施例中的位线BL。
在一些具体示例中，阻隔条90的组成材料可以包括氧化硅、氮化硅、氮氧化硅、氧化铝、聚硅氧烷或者聚硅氮烷等绝缘材料。此处氧化硅是指硅氧化合物，如SixOy，氮化硅是指氮硅化合物，如SixNy。
在一些实施例中，所述半导体器件100还包括：栅极导接结构31，所述栅极导接结构31沿所述第一方向X延伸，且位于所述栅极条30在所述第三方向Z上的所述一端与所述阻隔条90之间，并与所述阻隔条90至少部分并列。
在一些具体示例中，如图28至图30所示，栅极条30在第三方向Z上的一端连接有栅极导接结构31。其中，在第三方向Z上栅极导接结构31位于栅极条30与阻隔条90之间，栅极导接结构31与栅极条30在第三方向Z上的一端(例如，半导体柱10在第三方向Z上远离下文实施例中的电容结构70的一端)接触连接，且栅极导接结构31与阻隔条90相邻。也就是说，栅极条30所连接的栅极导接结构31与屏蔽条20所接触的阻隔条90在第三方向Z上的同一侧，且沿第二方向Y上栅极导接结构31与阻隔条90相邻。
在一些具体示例中，栅极导接结构31的组成材料可以包括导电材料，导电材料包括但不限于：钨(W)、钴(Co)、铜(Cu)、铝(Al)、硅化物或者其任何组合。
在一些实施例中，所述半导体器件100还包括：位于所述半导体柱阵列在所述第三方向Z上的一端的栅极引出触点32，所述栅极引出触点32与所述栅极导接结构31连接。
在一些具体示例中，如图30和图32所示，每个栅极导接结构31在第三方向Z上远离栅极条30的一端连接有栅极引出触点32，即在第三方向Z上栅极导出结构位于栅极引出触点32和栅极条30之间。
在一些具体示例中，栅极引出触点32的组成材料可以包括导电材料，导电材料包括但不限于：钨(W)、钴(Co)、铜(Cu)、铝(Al)、硅化物或者其任何组合。栅极引出触点32与栅极导接结构31的材料可以相同也可以不同。本申请通过栅极引出触点32和栅极导接结构31来引出栅极条30的连接，有利于工艺流程，并 可以提高可靠性。
在一些实施例中，所述半导体器件100还包括：位于所述半导体柱阵列在所述第三方向Z上的所述一端的屏蔽引出触点21，所述屏蔽引出触点21与所述屏蔽条20连接。
在一些具体示例中，如图31、图32和图34所示，屏蔽条20在第三方向Z上的一端连接有屏蔽引出触点21。在一些示例中，例如位于屏蔽条20的非端部部位时，屏蔽引出触点21沿第三方向Z穿过阻隔条90，并且屏蔽引出触点21通过阻隔条90与屏蔽条20在第三方向Z上的一端(例如，半导体柱10在第三方向Z上远离下文实施例中的电容结构70的一端)接触连接。也就是说，屏蔽条20所连接的屏蔽引出触点21与屏蔽条20所连接的阻隔条90在第三方向Z上的同一侧，且沿第三方向Z上屏蔽引出触点21和屏蔽条20位于阻隔条90的相对两侧。
在一些具体示例中，屏蔽引出触点21的组成材料可以包括导电材料，导电材料包括但不限于：钨(W)、钴(Co)、铜(Cu)、铝(Al)、硅化物或者其任何组合。屏蔽引出触点21与屏蔽条20的材料可以相同也可以不同。本申请屏蔽引出触点21与屏蔽条20电互连，通过屏蔽引出触点21对屏蔽条20施加固定的电压，即屏蔽引出触点21可以与公共端连接以使所述屏蔽条20起到屏蔽作用。
在一些具体示例中，公共端可以包括接低电压端、接地端，其中，低电压可以包括-0.5V、-1V等。在一些实施例中，屏蔽条20与公共端相连。在实际应用时，可以根据需求将屏蔽条20设置为单独供电而不与公共端相连。本申请的一些实施例中通过对屏蔽条20施加低电压或将屏蔽条20接地，以使屏蔽条20可以屏蔽相邻半导体柱10之间的干扰。
在一些实施例中，所述半导体器件100还包括：位于所述半导体柱阵列在所述第三方向Z上的所述一端的半导体柱引出触点11，所述半导体柱引出触点11与所述半导体柱10连接。
在一些具体示例中，如图35和图36所示，半导体柱10在第三方向Z上的一端连接有半导体柱引出触点11。其中，半导体柱引出触点11沿第三方向Z穿过覆 盖半导体柱10的阻隔条90，使得半导体柱引出触点11穿过阻隔条90与半导体柱10在第三方向Z上的一端(例如，半导体柱10在第三方向Z上远离下文实施例中的电容结构70的一端)接触连接。也就是说，半导体柱10所连接的半导体柱引出触点11与半导体柱10所连接的阻隔条90在第三方向Z上的同一侧，且沿第三方向Z上半导体柱引出触点11与屏蔽条20的一端连接。
在一些实施例中，可以将图28所示的与半导体柱10沿第三方向Z上的一端连接的第一阻隔部分90a去除。
在一些具体示例中，半导体柱引出触点11的组成材料可以包括导电材料，导电材料包括但不限于：钨(W)、钴(Co)、铜(Cu)、铝(Al)、硅化物或者其任何组合。半导体柱引出触点11与半导体柱10的材料可以相同也可以不同。本申请半导体柱引出触点11与半导体柱10电互连，通过半导体柱引出触点11可以将多个半导体柱10沿第三方向Z的一端与同一条位线BL连接。当然，在一些实施例中，半导体柱引出触点11也可以替换形成位线BL，即本申请实施例可以通过半导体柱引出触点11引出位线BL的连接，也可以不通过半导体柱引出触点11引出位线BL的连接，即可以直接在多个半导体柱10沿第三方向Z的一端形成与之邻接的位线BL。
示例性的，如图35所示，在阵列排布的多个半导体柱10的底部各自形成有一半导体柱引出触点11，可通过如图35所示的沿第一方向X和第二方向Y间隔排布的多个半导体柱引出触点11引出对应的半导体柱10，即八列半导体柱引出触点11分别依次与第一位线BL1至第八字线BL8连接。需要说明的是，本申请实施例图示中半导体柱引出触点11的数量只是示例，其他数量的半导体柱引出触点11亦在本申请保护范围内。
在一些具体示例中，半导体器件100还可以包括沿第二方向Y延伸且位于所述半导体柱阵列在所述第三方向Z上的所述一端的绝缘层91。如图32所示，在第三方向Z上绝缘层91覆盖所述阻隔条90、所述栅极导接结构31、栅极引出触点32、屏蔽引出触点21和半导体柱引出触点11。
在一些具体示例中，半导体器件100还可以包括沿第二方向Y延伸且位于所述半导体柱阵列在所述第三方向Z上的所述一端的隔离层80。如图32所示，在第三方向Z上隔离层80覆盖半导体柱10沿第三方向Z上远离下文实施例的电容结构70的一端，即如图32所示，沿第三方向Z上隔离层80和绝缘层91分别位于所述阻隔条90的相对两侧，并且隔离层80覆盖各半导体柱10，绝缘层91覆盖沿第三方向Z上位于同一侧的阻隔条90、所述栅极导接结构31、栅极引出触点32、屏蔽引出触点21和半导体柱引出触点11。
在一些具体示例中，隔离层80和绝缘层91的组成材料可以均包括氧化硅、氮化硅、氮氧化硅、氧化铝、聚硅氧烷或者聚硅氮烷等绝缘材料中的任意一种或者多种组合，在本申请实施例中，隔离层80和绝缘层91的材料可以相同也可以不同。
在一些实施例中，所述半导体器件100还包括：
沿所述第三方向Y间隔排布于各行半导体柱10之间的多个所述栅极条30；
沿所述第三方向Y间隔排布于所述各行半导体柱10之间，且与所述多个栅极条30交错间隔排布的多个所述屏蔽条20；
沿所述第三方向Y间隔排布于所述各行半导体柱10之间的多个所述阻隔条90；以及，
沿所述第三方向Y间隔排布于所述各行半导体柱10之间的多个所述栅极导接结构31。
在一些具体示例中，如图27所示，沿第一方向X上多个半导体柱10间隔排布，且沿第二方向Y上多个半导体柱10间隔排布，即多个半导体柱10沿第一方向X和第二方向Y阵列排布。如图27、图28和图31所示，多个半导体柱10沿第一方向X和第二方向Y阵列排布，沿第二方向Y上相邻的半导体柱10中的栅极条30位于各半导体柱10的一侧，即多个所述栅极条30沿所述第三方向Y间隔排布于各行半导体柱10之间，并且多个栅极条30沿第二方向Y上位于半导体柱10的一侧。沿第二方向Y上相邻的半导体柱10中的屏蔽条20位于各半导体柱10的另一 侧，即多个所述屏蔽条20沿所述第三方向Y间隔排布于各行半导体柱10之间，并且多个屏蔽条20沿第二方向Y上位于半导体柱10的另一侧。另外，沿第二方向Y上多个栅极条30与多个所述屏蔽条20交错排布，且沿第二方向Y上相邻半导体柱10中的栅极条30与屏蔽条20之间有间距。
在一些具体示例中，如图28和图30所示，半导体结构还设有沿第一方向X延伸的多个阻隔条90，每个屏蔽条20在第三方向Z上的一端连接有各自的阻隔条90，并且，多个屏蔽条20各自连接的阻隔条90均位于第三方向Z上的同一端。其中，阻隔条90与屏蔽条20在第三方向Z上的一端(例如，半导体柱10在第三方向Z上远离下文实施例中的电容结构70的一端)接触连接，阻隔条90位于所述屏蔽条20与所述栅极条30在所述第三方向Z上的同一侧，并且阻隔条90与栅极条30在第二方向Y上具有间距，这样，就可以通过阻隔条90将沿第二方向Y上相邻半导体柱10之间的栅极条30和屏蔽条20隔离开，并且由于阻隔条90具有绝缘功能，这样，与阻隔条90接触连接的屏蔽条20就能够起到屏蔽作用，从而实现改善第二方向Y上相邻晶体管之间的耦合效应，降低相邻晶体管之间的干扰，提升提高存储器的良率和可靠性。
在一些具体示例中，如图30所示沿第二方向Y上多个阻隔条90可以位于半导体柱10的一侧。当然，如图28所示沿第二方向Y上多个阻隔条90可以位于半导体柱10的另一侧。需要说明的是，阻隔条90的组成材料可参考上文实施例，在此不再一一赘述。
示例性的，如图28所示，第一晶体管T1包括栅极条30a和半导体柱10a，第二晶体管T2包括栅极条30b和半导体柱10b，半导体柱10a和半导体柱10b之间设有与阻隔条90接触连接的屏蔽条20，这样，可以通过与阻隔条90接触连接的屏蔽条20改善第一晶体管T1和第二晶体管T2之间的耦合效应，即当第一晶体管T1被导通时，第一晶体管T1的半导体柱10a区域变成高压，位于第一晶体管T1和第二晶体管T2之间的屏蔽条20会屏蔽第一晶体管T1的半导体柱10a中的电子与第二晶体管T2的半导体柱10b中的电子之间的干扰，从而降低导通的第一晶体 管T1对第二晶体管T2的干扰问题。
在一些具体示例中，如图28至图30、图32至图33所示，每个栅极条30在第三方向Z上的一端连接有栅极导接结构31，并且，多个栅极条30各自连接的栅极导接结构31均位于第三方向Z上的同一端，其中，沿第三方向Z上栅极导接结构31位于栅极条30与阻隔条90之间，栅极导接结构31与栅极条30在第三方向Z上的一端(例如，半导体柱10在第三方向Z上远离下文实施例中的电容结构70的一端)接触连接，且沿第二方向Y上栅极导接结构31与阻隔条90相邻。
在一些具体示例中，如图28所示沿第二方向Y上多个栅极导接结构31可以位于相邻半导体柱10之间的一侧，此时第二方向Y上多个阻隔条90位于相邻半导体柱10之间的另一侧。当然，如图30所示沿第二方向Y上多个栅极导接结构31可以位于半导体柱10的另一侧，此时第二方向Y上多个阻隔条90位于相邻半导体柱10之间的一侧。总之，栅极导接结构31和阻隔条90位于半导体柱10沿第三方向Z上的同一侧，且栅极导接结构31和阻隔条90位于相邻半导体柱10沿第二方向Y上的不同侧。需要说明的是，栅极导接结构31的组成材料可参考上文实施例，在此不再一一赘述。
在一些实施例中，所述半导体器件100还包括多个栅极引出触点32，一个所述栅极引出触点32对应于一个所述栅极导接结构31，且所述多个栅极引出触点32沿所述第一方向X与所述第二方向Y同步间隔排列呈阶梯状分布。
在一些实施例中，所述半导体器件100还包括多个屏蔽引出触点21，一个所述屏蔽引出触点21对应于一个所述屏蔽条20，且所述多个屏蔽引出触点21沿所述第一方向X与所述第二方向Y同步间隔排列呈阶梯状分布。
在具体的示例中，如图30、图34和图32所示，半导体器件100包括沿第一方向X上以及第二方向Y上依图30和图32所示示例的四个栅极条30的排列顺序同时或同步间隔排布的栅极引出触点32a、栅极引出触点32b、栅极引出触点32c和栅极引出触点32d，从而呈阶梯状排列，半导体器件100包括沿第一方向X上以及第二方向Y上如图32和图34所示，半导体器件100所示示例 的四个屏蔽条20的排列顺序同时或同步间隔排布的屏蔽引出触点21a、屏蔽引出触点21b、屏蔽引出触点21c和屏蔽引出触点21d，从而呈阶梯状排列，并且，栅极引出触点32位于相邻半导体柱10之间的一栅极条30沿第三方向Z上远离下文实施例中电容结构70的一端，屏蔽引出触点21位于相邻半导体柱10之间的一屏蔽条20沿第三方向Z上远离下文实施例中电容结构70的一端。需要说明的是，栅极引出触点32、屏蔽引出触点21的组成材料可参考上文实施例，在此不再一一赘述。
在一些实施例中，如图31和图32所示，所述半导体器件100还包括多个栅极引出触点32与多个屏蔽引出触点21，一个所述栅极引出触点32对应于一个所述栅极导接结构31，一个所述屏蔽引出触点21对应于一个所述屏蔽条20，且所述多个栅极引出触点32与所述多个屏蔽引出触点21沿所述第二方向Y交错间隔排列。
示例性的，如图31所示，沿第二方向Y上间隔排列设置有四个沿第一方向延伸X的四个栅极条30，每个栅极条30沿第二方向Y上靠近下文实施例中隔离结构50的一侧连接有一个栅极导接结构31，一个所述栅极导接结构31对应连接有一个所述栅极引出触点32，通过四个间隔排列的栅极引出触点32及其各自连接的栅极导接结构31引出四个栅极条30，即四个栅极条30分别依次与第一字线WL1、第二字线WL2、第三字线WL3和第四字线WL4连接。同理，沿第二方向Y上间隔排列设置有四个沿第一方向延伸X的四个屏蔽条20，每个屏蔽条20沿第二方向上靠近下文实施例中隔离结构50的一侧连接有一个阻隔条90，一个屏蔽条对应连接有一个所述屏蔽引出触点21，通过四个间隔排列的屏蔽引出触点21来引出四个屏蔽条20，即四个屏蔽条20分别依次与第一盘线PL1、第二盘线PL2、第三盘线PL2和第四盘线PL4连接。可以通过盘线PL(Plate Line)对其连接的屏蔽条20施加一定的固定电压，以使屏蔽条20可以屏蔽相邻半导体柱10之间的干扰。需要说明的是，本申请实施例图示中栅极引出触点32与屏蔽引出触点21的数量只是示例，其他数量的半导体柱引出触点11亦在本申请保护范围内。
在一些实施例中，如图32和图34所示，所述半导体器件100还包括多个栅极引出触点32与多个屏蔽引出触点21，一个所述栅极引出触点32对应于一个所述栅极导接结构31，一个所述屏蔽引出触点21对应于一个所述屏蔽条20，且所述多个栅极引出触点32与所述多个屏蔽引出触点21沿所述第一方向X与所述第二方向Y同步交错间隔排列而呈阶梯状分布。
示例性的，如图34所示，同样可以参照图31所示引出四个栅极条30和四个屏蔽条20，图34与图31的不同在于图34的多个栅极引出触点32与多个屏蔽引出触点21沿所述第二方向Y交错间隔排列呈阶梯状分布。
在一些实施例中，所述半导体柱10在所述第二方向Y上的横截面尺寸，与两相邻所述半导体柱10之间的间隔尺寸相等。
在一些具体示例中，如图32所示，沿第二方向Y上各半导体柱10在所述第二方向Y上的横截面尺寸L2等于相邻所述半导体柱10之间的间隔尺寸L1。由于工艺精度控制的原因，本实施例中的等于包括近似等于或者约等于。本申请的一些实施例中在相邻半导体柱10之间形成两个电极即第一电极和第二电极，于所述第一电极和第二电极在所述第三方向Z上的同一端，形成沿所述第一方向X延伸且与第二电极连接的阻隔条90，这样第一电极可以作为栅极条30，第二电极可以作为屏蔽条20，不需要在相邻半导体柱10直接形成气隙或者其他屏蔽隔离结构50，通过阻隔条90可以在形成栅极条30的同时形成屏蔽条20，这样可以屏蔽栅极条30对相邻半导体柱10的干扰，进而降低了相邻半导体柱10之间的耦合效应。而且，沿第二方向Y上各半导体柱10在所述第二方向Y上的横截面尺寸L2等于相邻所述半导体柱10之间的间隔尺寸L1，降低负载效应，工艺控制难度降低。
在一些实施例中，所述半导体柱10在所述第二方向Y上的横截面尺寸，与两相邻所述半导体柱10之间的间隔尺寸的差异小于预设值。
在一些具体示例中，如图32所示，沿第二方向Y上各半导体柱10在所述第二方向Y上的横截面尺寸L2等于相邻所述半导体柱10之间的间隔尺寸L1的尺寸 差异小于基于工艺或者设备的精度要求、或者产品要求的设定数值，例如，间隔尺寸L1和横截面尺寸L2的差值的绝对值小于及其他可行数值，即|L1－L2|＜△L，△L指代预设值。
在一些实施例中，所述半导体器件100还包括：
位于所述半导体柱10与所述栅极条30之间以及所述半导体柱10与所述屏蔽条20之间的第一氧化层41；
位于所述栅极条30和所述屏蔽条20之间的隔离结构50。
在一些具体示例中，如图18至图26、图28至图30和图32所示，半导体器件100还包括第一氧化层41和隔离结构50。其中，沿第二方向Y上半导体柱10与所述栅极条30之间设有第一氧化层41，并且沿第二方向Y上所述半导体柱10与所述屏蔽条20之间设有第一氧化层41。另外，沿第二方向Y上所述栅极条30和所述屏蔽条20之间设有隔离结构50。如图18至图26、图28至图30和图32所示，沿第二方向Y上半导体柱10、第一氧化层41、栅极条30、隔离结构50、屏蔽条20、第一氧化层41、半导体柱10依次排布。
在一些实施例中，在第二方向Y上相邻半导体柱10之间设有一栅极条30和一屏蔽条20，并且半导体柱10与屏蔽条20之间的间隔距离与相邻半导体柱10与栅极条30之间的间隔距离相同。也就是说，在第二方向Y上一个栅极条30和一个屏蔽条20分别位于相邻半导体柱10的不同侧壁，并且屏蔽条20与栅极条30之间的位置镜像对称。
如图2所示的第一隔离结构206沿第二方向Y上位于相邻两个栅极201之间的中间位置，在第二方向Y上相邻沟道区204的中间位置设有一个第一隔离结构206，也就是说，在第二方向Y上第一隔离结构206与相邻沟道区204的距离相同，且在第二方向Y上第一隔离结构206与相邻栅极201的距离相同。不同于图2所示，本申请由于如图11至图28所示，同步形成栅极沟槽K2，沿第二方向Y在栅极沟槽的不同侧壁沉积形成第一电极和第二电极，在位于一侧壁的第二电极沿所述第三方向Z上的一侧形成阻隔条90，从而使得与阻隔条90连接的第二电极 形成具有屏蔽作用的屏蔽条20，使得未与阻隔条90连接的第一电极形成栅极条，相对于图2而言额外在相邻晶体管之间挖槽得到用于形成第一隔离结构206的隔离凹槽，本申请直接利用多个等间矩排布的多个栅极凹槽形成镜像对称设置的导电层配合阻隔条形成栅极条30和屏蔽条20，降低工艺控制难度，还可以增强半导体柱10的强度，提升半导体器件100的抗倾倒能力。
在一些具体示例中，第一氧化层41的组成材料可以包括氧化硅、氮氧化硅等。
在一些具体示例中，隔离结构50的组成材料可以包括氧化硅、氮化硅、氮氧化硅、氧化铝、聚硅氧烷或者聚硅氮烷等绝缘材料中的任意一种或者多种组合。
在一些实施例中，所述半导体器件100还包括：位于所述半导体柱阵列在所述第三方向Z上的另一端的电容阵列71，所述电容阵列71包括多个沿所述第一方向X与所述第二方向Y阵列排布且在所述第三方向Z上延伸的多个电容结构70，所述电容结构70包括与所述半导体柱10在所述第三方向Z上的另一端连接的第一电极层(图中未示出)，以及位于所述第一电极层内的电容介质层(图中未示出)和第二电极层(图中未示出)。
在一些具体示例中，如图28、图30和图32所示，半导体器件100还包括电容阵列71，电容阵列71包括多个在所述第三方向Z上延伸的电容结构70，多个电容结构70沿所述第一方向X与所述第二方向Y阵列排布，并且沿第三方向Z上各半导体柱10的另一端(即与上文实施例中与阻隔条90、栅极导接结构31连接的与半导体柱10的一端沿第三方向Z上是相对两端)连接有一个电容结构70。并且，每个电容结构70包括与所述半导体柱10的源极连接的第一电极层。
半导体阵列的各半导体柱10侧壁形成有栅极条30，位于同一列的各半导体柱10(即沿第二方向Y间隔排布的各半导体柱10)的栅极条30相连接以形成字线，晶体管阵列的各半导体柱10沿第三方向Z上的一端形成源极(图中未示出)，源极与电容结构70的第一电极层连接，晶体管阵列的各半导体柱10沿第 三方向Z上的另一端形成漏极(图中未示出)，位于同一行的各半导体柱10(即沿第一方向X间隔排布的各半导体柱10)的漏极相连接以形成位线BL(图中未示出)。在上述半导体器件100中半导体柱10沿第三方向Z延伸，源极和漏极分别形成在半导体柱10沿第三方向Z的相对两端，沿第三方向Z上电容结构70和位线BL分别位于半导体柱10的相对两侧，这样可以在衬底1的两侧分别制作，提高工艺制造效率。
可以理解的是，半导体柱10的源极与漏极是一种相对的概念，源极和漏极可以是半导体柱10的沿第三方向Z上的任意一个表面。
其中，一个电容结构70与一个晶体管构成一个DRAM存储单元，通过晶体管的导通与关闭，实现对所连接电容结构70的选定与非选定，进而可实现对选中的存储单元进行读、写或者擦除操作。本申请实施例对电容结构70和晶体管的数量不作限制，可以是电容阵列71与晶体管阵列(包括多个沿第一方向X和第二方向Y阵列排布的晶体管)耦接，构成DRAM阵列存储结构。
可以理解的是，晶体管的源极与漏极是一种相对的概念，跟晶体管实际接入电路的方式相关，而与源极与漏极处于晶体管的物理位置无关。在一些示例中，当晶体管接入电路后，可将晶体管接入电路的输入端作为源极，输出端作为漏极，载流子从源极流入漏极。为了更好的解释说明本申请实施例中电容结构70与晶体管的耦接关系，将晶体管与电容结构70耦接的一端作为漏极，而晶体管的源极则可以与施加操作电压的位线BL耦接。
本申请实施例还提供一种半导体器件100的制作方法，可以通过下述半导体器件100的制作方法制造得到上述实施例中的半导体器件100。图37是本申请实施例中半导体器件100的制作方法的流程示意图，如图37所示，包括：
S100、形成多个半导体柱10，并使所述多个半导体柱10在第一方向X与第三方向Y阵列排布且在第三方向Z上延伸，所述第一方向X、所述第二方向Y、以及所述第三方向Z彼此相交叉。
在一些实施例中，所述形成多个半导体柱10的步骤包括：
S110、提供一衬底1。
在一些具体的示例中，衬底1是用于制作半导体器件100的材料，衬底1的材料可以包括硅(例如，单晶硅、多晶硅)、硅锗(SiGe)、碳化硅(SiC)、氮化镓(GaN)、磷化铟(InP)、砷化镓(GaAs)、锗(Ge)、绝缘体上硅(SOI)、绝缘体上锗(GOI)或其任何合适的组合。衬底1可以包括由圆柱形的单晶硅经过研磨、抛光以及切片等步骤后形成的晶圆。
在一些具体的示例中，在形成步骤S120的隔离沟槽K1之前，先沿第三方向Z沉积形成覆盖衬底1的第一介质层14，然后高温条件下沿第三方向Z沉积覆盖第一介质层14的第二氧化层(liner oxide)13以修复衬底1表面，以形成如图3和图4所示沿第三方向Z上衬底1、第一介质层14和第二氧化层13依次层叠的结构。
在一些具体的示例中，第二氧化层13和第一介质层14的组成材料可以包括氧化硅、氮化硅、氧化铝或氮氧化硅中的任意一种或多种。
S120、如图5和图6所示在所述衬底1中形成多个沿所述第三方向Y延伸且沿第一方向X间隔排布的隔离沟槽K1，如图7和图8所示，并于所述隔离沟槽K1的内壁填入介质材料42；
在一些具体的示例中，可以在衬底1中形成多个隔离沟槽K1，也可以如图5和图6所示在如图3和图4所示的结构中形成多个隔离沟槽K1。如图5和图6所示，多个隔离沟槽K1沿所述第二方向Y延伸且沿第一方向X间隔排布，并且隔离沟槽K1沿第三方向Z延伸但不穿透衬底1。
形成隔离沟槽K1的步骤包括：从如图4所示的第二氧化层13表面刻蚀，形成沿第三方向Y延伸且沿第一方向X间隔排布的隔离沟槽K1，并且隔离沟槽K1可以沿第三方向Z延伸至衬底1但不穿透衬底1。如5和图6所示，在进行刻蚀的过程中，可以通过掩模(图中未示出)遮盖衬底1或第二氧化层13表面的部分区域，即需要形成隔离沟槽K1的各区域。然后对衬底1表面沿衬底1的厚度方向(即第三方向Z)进行刻蚀，在掩模遮盖的区域以外，衬底1、第一介质层14和第二 氧化层13均被刻蚀掉一部分，形成一定深度的凹槽，即上述隔离沟槽K1。需要注意的是，形成隔离沟槽K1的刻蚀深度小于衬底1的初始厚度，即刻蚀过程不会将衬底1刻穿。
在一些具体的示例中，可以采用光刻(Photolithography，PH)或者干法刻蚀(Etching，ET)等工艺进行刻蚀，例如，电子束光刻工艺、等离子体刻蚀工艺或者反应离子刻蚀工艺等，本申请的一些实施例不做限定。
本申请一些实施例中，通过对整个衬底1表面进行刻蚀，同步地形成多个具有相同深度的隔离沟槽K1，可以简化制造工艺，提高效率。
在一些具体的示例中，图7为本申请的一些实施例提供的在隔离沟槽K1中沉积介质材料42的俯视图，图8为本申请的一些实施例提供的在隔离沟槽K1中沉积介质材料42的剖视图。形成如图5和图6所示的隔离沟槽K1后，如图7和图8所示，利用沉积工艺在隔离沟槽K1中沉积介质材料42。
在一些实施例中，介质材料42包括但不限于氮化硅、氧化硅或氮氧化硅中任一种或任意多种的组合。此处氧化硅是指硅氧化合物，如SixOy，氮化硅是指氮硅化合物，如SixNy。
由于如图5和图6所示形成隔离沟槽K1，多个隔离沟槽K1沿第一方向X间隔排布，因此，衬底1中形成去除部分半导体材料形成的隔离沟槽K1与隔离沟槽K1之间会有用于间隔相邻两个隔离沟槽K1的凸起结构211。需要说明的是，在实际沉积介质材料42的过程中，介质材料42会覆盖在凸起结构211的表面，如图7所示，每一凸起结构211的周围填充有介质材料42。另外，在沉积完成后，可以采用化学机械研磨(Chemical Mechanical Polishing，CMP)工艺，打磨去除多余的介质材料42以实现平坦化。
本申请一些实施例中，介质材料42、第一介质层14、第二氧化层13的沉积方法可以采用但不限于化学气相沉积(800emical vapor deposition，CVD)、物理气象沉积(Physicalvapor deposition，PVD)、等离子体增强化学气象沉积(Plasma-enhanced CVD，PECVD)、溅镀(Sputtering)、有机金属化学气象沉积 (Metal-organic emical vapor deposition，MOCVD)及原子层沉积(Atomic layer deposition，ALD)等。
S130、如图9、图10所示，形成多个沿所述第一方向X延伸且沿第三方向Y间隔排布的栅极沟槽K2，而形成沿所述第一方向X延伸且沿第三方向Y间隔排布且在第三方向Z上延伸的所述多个半导体柱10。
在一些具体示例中，在隔离沟槽K1内填充介质材料42后，如图9、图10所示，在所述衬底1中形成沿所述第一方向X延伸且沿第二方向Y间隔排布的栅极沟槽K2，且沿第二方向Y上所述半导体柱10位于相邻的所述栅极沟槽K2之间，由于填充有介质材料42的隔离沟槽K1沿第二方向Y延伸且沿第一方向X间隔排布，而栅极沟槽K2沿第一方向X延伸且第二方向Y间隔排布，因此通过栅极沟槽K2可以将填充有介质材料42的隔离沟槽K1划分为在第一方向X与第三方向Y阵列排布且在第三方向Z上延伸的多个半导体柱10。
在一些具体示例中，在第二方向Y间隔排布的多个栅极沟槽K2沿第一方向X上的尺寸可以相同也可以不同。例如，如图9、图10所示，所述栅极沟槽K2a和所述栅极沟槽K2b沿所述第三方向Y间隔交错排布，且所述栅极沟槽K2a沿所述第一方向X的尺寸大于所述栅极沟槽K2b沿所述第一方向X的尺寸。
在一些具体示例中，刻蚀形成的栅极沟槽K2沿所述第二方向Y的尺寸等于半导体柱10沿所述第三方向Y的尺寸。
S200、在相邻的所述半导体柱10之间形成一个栅极条30与一个屏蔽条20，并使所述栅极条30与所述屏蔽条20沿所述第一方向X延伸并在第三方向Y上相间隔；以及，
在一些实施例中，所述形成一个栅极条30与一个屏蔽条20的步骤，包括：
S210、如图11和图12所示，在所述栅极沟槽K2的侧壁内形成第一氧化层41。
在一些具体示例中，如图9和图10所示，形成栅极沟槽K2后，可以如图11和图12所示，在所述栅极沟槽K2的侧壁内形成第一氧化层41，第一氧化层41可以是利用热氧化法(RTO，Rapid Thermal Oxidation)或原位蒸汽生成法 (ISSG，In-situ Stream Generation)形成的氧化硅层。如图11和图12所示，通过所述栅极沟槽K2对所述半导体柱10裸露的侧壁进行氧化处理，在所述半导体柱10的所述侧壁即所述栅极沟槽K2的侧壁内形成第一氧化层41。对上述半导体柱10裸露在栅极沟槽K2内的侧壁进行氧化处理的工艺包括但不限于：直接氧化，碱性氧化或者酸性氧化。
本申请的一些实施例中，通过加热的方式直接氧化，使半导体柱10侧壁上的硅与含有氧化物质的气体在高温下进行化学反应，从而在硅表面产生一层致密的二氧化硅薄膜，形成位于半导体柱10侧壁上的第一氧化层41。第一氧化层41包括例如氧化硅、氮氧化硅等绝缘材料。
S220、如图13和图14所示，在所述第一氧化层41的侧壁内形成导电层66。
在一些具体示例中，在所述第一氧化层41的侧壁内沉积形成导电层66，导电层的材料包括但是不限于：钨(W)、钴(Co)、铜(Cu)、铝(Al)、硅化物或者其任何组合的导电材料。
在一些实施例中，导电材料的沉积方法可以采用但不限于化学气相沉积(800emical vapor deposition，CVD)、物理气象沉积(Physicalvapor deposition，PVD)、等离子体增强化学气象沉积(Plasma-enhanced CVD，PECVD)、溅镀(Sputtering)、有机金属化学气象沉积(Metal-organic emical vapor deposition，MOCVD)及原子层沉积(Atomic layer deposition，ALD)等。
S230、如图15和图16所示，去除位于所述第一氧化层41的侧壁上且沿所述第三方向Z上靠近所述衬底1的部分所述导电层66，以及位于所述栅极沟槽K2在所述第一方向X的两端部的连接部分，而形成分开的所述栅极条30与所述屏蔽条20。
S300、在所述屏蔽条20沿所述第三方向Z上的一端形成阻隔条90，所述阻隔条90沿第一方向X延伸，且位于所述屏蔽条20与所述栅极条30在所述第三方向Z上的同一侧。
在一些具体示例中，在栅极沟槽K2内形成的所述栅极条30和所述屏蔽条20 在所述第三方向Y上相邻，并且，栅极条30和所述屏蔽条20分别位于与之相邻的所述半导体柱10的一侧。例如，如图28所示，半导体柱10a与半导体柱10b在所述第三方向Y上相邻，位于半导体柱10a与半导体柱10b之间设有一栅极条30和一屏蔽条20，且栅极条30沿第三方向Y位于靠近半导体柱10b的一侧，该栅极条30中所述屏蔽条20沿第三方向Y位于靠近半导体柱10a的一侧。
形成阻隔条90的步骤具体包括：如图23所示，沿第三方向Z在半导体柱10背离电容阵列71的一端沉积隔离层80，如图24所示，通过例如离子注入(IMP Process)等工艺对暴露的栅极条30和屏蔽条20进行掺杂，例如N型掺杂，上述N型掺杂可包括任何合适的例如N型掺杂剂(例如，磷(P)、砷(Ar)或锑(Sb))，以贡献自由电子并且增加栅极条30和屏蔽条20的导电性。如图25所示，基于沉积工艺形成覆盖半导体柱10、栅极条30和屏蔽条20的阻隔层92，阻隔层92沿第二方向Y延伸，去除如图25阻隔层92中与屏蔽条20连接的部分以形成如图26所示的凹槽K3，从而去除与屏蔽条20连接的部分后剩余的阻隔层92形成如图26所示的沿第一方向X延伸的阻隔条90，在第三方向Z上阻隔条90与屏蔽条20的一端连接，并且阻隔条90在所述屏蔽条20与所述栅极条30在所述第三方向Z上的同一端。
本申请的一些实施例中在相邻半导体柱10之间形成两个电极即第一电极和第二电极，于所述第一电极和第二电极在所述第三方向Z上的同一端，形成沿所述第一方向X延伸且与第二电极连接的阻隔条90，这样第一电极可以作为栅极条30，第二电极可以作为屏蔽条20，通过阻隔条90可以在形成栅极条30的同时形成屏蔽条20，这样可以屏蔽栅极条30对相邻半导体柱10的干扰，进而降低了相邻半导体柱10之间的耦合效应。
在一些实施例中，所述制作方法还包括：如图15、图17和图18所示，在所述栅极沟槽K2中填入隔离材料55，并使所述隔离材料55覆盖所述栅极条30与所述屏蔽条20而形成隔离结构50。
在一些具体示例中，隔离材料55的材料包括但是不限于氮化硅、氧化硅或氮氧化硅中任一种或任意多种的组合。隔离材料55的沉积方法可以采用但不限于化学气相沉积(800emical vapor deposition，CVD)、物理气象沉积(Physicalvapor deposition，PVD)、等离子体增强化学气象沉积(Plasma-enhanced CVD，PECVD)、溅镀(Sputtering)、有机金属化学气象沉积(Metal-organic emical vapor deposition，MOCVD)及原子层沉积(Atomic layer deposition，ALD)等。
在一些实施例中，所述制作方法还包括：
如图19所示，于所述半导体柱阵列在所述第三方向Z上的另一端形成电容阵列71，并使所述电容阵列71包括多个沿所述第一方向X与所述第二方向Y阵列排布且在所述第三方向Z上延伸的多个电容结构70，所述电容结构70包括与所述半导体柱10在所述第三方向Z上的另一端连接的第一电极层(图中未示出)，以及位于所述第一电极层内的电容介质层(图中未示出)和第二电极层(图中未示出)。
在一些具体示例中，如图19所示，于所述半导体柱阵列在所述第三方向Z上的另一端形成电容阵列71，如图20所示，去除沿第三方向Z上远离电容阵列71的衬底1的一部分。
在一些实施例中，所述制作方法还包括：
如图21和图22所示，去除所述衬底1在所述第三方向Z上远离所述电容阵列71的一端，以及位于所述栅极沟槽K2的底部的所述隔离结构50，而露出所述栅极条30在所述第三方向Z上的一端，以及所述屏蔽条20在所述第三方向Z上的一端。
在一些具体示例中，如图21所示，可以采用光刻(Photolithography，PH)或者干法刻蚀(Etching，ET)等工艺去除衬底1在所述第三方向Z上远离所述电容阵列71的一端。然后，如图22所示，可以采用干法刻蚀或者湿法刻蚀去除所述隔离结构50中沿第三方向Z上远离电容阵列71的部分隔离材料55即隔离结构50的底端部分56，隔离结构50的底端部分56在第三方向Z上覆盖栅极条30远离电容 阵列71的一端，以及在第三方向Z上覆盖屏蔽条20远离电容阵列71的一端，因此，去除隔离结构50的底端部分56可以露出所述栅极条30在所述第三方向Z上的一端，以及所述屏蔽条20在所述第三方向Z上的一端。
在一些实施例中，所述制作方法还包括：
于所述栅极沟槽K2的底部形成栅极导接结构31，所述栅极导接结构31沿所述第一方向X延伸，且位于所述栅极条30以及所述隔离结构50在所述第三方向Z上的所述一端，并与所述屏蔽条20在所述第三方向Z上的所述一端相间隔。
在一些具体示例中，凹槽K3位于所述栅极条30以及所述隔离结构50在所述第三方向Z上远离电容结构70的一端，并且凹槽K3与所述屏蔽条20在所述第三方向Z上远离电容结构70的一端相间隔，这样在如图26所示的凹槽K3内形成栅极导接结构31，可以形成如图28所示的栅极导接结构31。栅极导接结构31的材料可参见上述实施例，在此不再一一赘述。
在一些实施例中，所述制作方法还包括：
如图26至图28所示，于所述半导体柱阵列在所述第三方向Z上的一端形成栅极引出触点32，所述栅极引出触点32与所述栅极导接结构31连接。
在一些具体示例中，如图29所示，于所述半导体柱阵列在所述第三方向Z上远离电容阵列71的一端沉积形成绝缘层91，绝缘层91覆盖阻隔条90和栅极导接结构31。去除绝缘层91的一部分形成第一沟槽K4，并于第一沟槽K4中形成栅极引出触点32，栅极引出触点32的材料可参见上述实施例，在此不再一一赘述。
在一些实施例中，所述制作方法还包括：
如图31至图32所示，或如图33、图34和图36所示，于所述半导体柱阵列在所述第三方向Z上的所述一端形成屏蔽引出触点21，所述屏蔽引出触点21与所述屏蔽条20连接。去除绝缘层91的一部分形成第二沟槽K5，并于第二沟槽K5中形成屏蔽引出触点21，屏蔽引出触点21的材料可参见上述实施例，在此不再一一赘述。
在一些实施例中，所述制作方法还包括：
如图35和图36所示，于所述半导体柱阵列在所述第三方向Z上的所述一端形成半导体柱引出触点11，所述半导体柱引出触点11与所述半导体柱10连接。去除绝缘层91的一部分形成第三沟槽K6，并于第三沟槽K6中形成半导体柱引出触点11，半导体柱引出触点11的材料可参见上述实施例，在此不再一一赘述。
如图26至图29和图33至图34所示，在一些实施例中，所述于所述半导体柱阵列在所述第三方向Z上的一端形成栅极引出触点32的步骤包括：
形成多个所述栅极引出触点32，一个所述栅极引出触点32对应于一个所述栅极导接结构31，并使所述多个栅极引出触点32沿所述第一方向X与所述第二方向Y同步间隔排列呈阶梯状分布。
如图26至图29和图33至图34所示，在一些实施例中，所述于所述半导体柱阵列在所述第三方向Z上的所述一端形成屏蔽引出触点21的步骤包括：
形成多个屏蔽引出触点21，一个所述屏蔽引出触点21对应于一个所述屏蔽条20，并使所述多个屏蔽引出触点21沿所述第一方向X与所述第二方向Y同步间隔排列呈阶梯状分布。
如图26至图29和图33至图34所示，在一些实施例中，所述制作方法还包括形成多个栅极引出触点32与多个屏蔽引出触点21，一个所述栅极引出触点32对应于一个所述栅极导接结构31，一个所述屏蔽引出触点21对应于一个所述屏蔽条20，并使所述多个栅极引出触点32与所述多个屏蔽引出触点21沿所述第一方向X与所述第二方向Y同步交错间隔排列而呈阶梯状分布。
如图31至图32所示，在一些实施例中，所述制作方法还包括形成多个栅极引出触点与多个屏蔽引出触点，一个所述栅极引出触点对应于一个所述栅极导接结构，一个所述屏蔽引出触点对应于一个所述屏蔽条，并使所述多个栅极引出触点与所述多个屏蔽引出触点沿所述第一方向与所述第二方向同步交错间隔排列。
在一些实施例中，如图32所示，所述形成多个半导体柱10的步骤包括使半导体柱10在所述第二方向Y上的横截面尺寸，与两相邻所述半导体柱10之间的 间隔尺寸的差异小于预设值。
在一些具体示例中，在形成如图33所示用于形成栅极引出触点32的第一沟槽K4，用于形成屏蔽引出触点21的第二沟槽K5之前，沿第三方向Z上在绝缘层91背离电容阵列71的表面形成图案化的第一掩膜层(图未示)，第一掩膜层具有多个第一开口(图未示)和第二开口(图未示)，第一开口用来形成第一沟槽K4，第二开口用来形成第二沟槽K5。以在经图案化的第一掩膜层中形成对应于第一沟槽K4和第二沟槽K5的开口，开口暴露出后续进行刻蚀工艺需刻蚀出的第一沟槽K4和第二沟槽K5的位置，即，沿第三方向Z上第一开口在绝缘层91的背离电容阵列71的表面的垂直投影可至少大体上与第一沟槽K4的位置重叠，沿第三方向Z上第二开口在绝缘层91的背离电容阵列71的表面的垂直投影可至少大体上与第二沟槽K5的位置重叠。通过设置第一掩膜层，能够快速准确的确定第一沟槽K4和第二沟槽K5的刻蚀位置，便于对绝缘层91进行刻蚀处理，进而在第一沟槽K4内形成栅极引出触点32，在第二沟槽K5内形成屏蔽引出触点21。
在一些具体示例中，在形成如图34所示用于形成半导体柱引出触点11的第三沟槽K6之前，沿第三方向Z上在绝缘层91背离电容阵列71的表面形成图案化的第二掩膜层(图未示)，第二掩膜层具有多个第三开口(图未示)，第三开口用来形成第三沟槽K6。以在经图案化的第二掩膜层中形成对应于第二沟槽K5的开口，开口暴露出后续进行刻蚀工艺需刻蚀出的第三沟槽K6的位置，即，沿第三方向Z上第一开口在绝缘层91的背离电容阵列71的表面的垂直投影可至少大体上与第三沟槽K6的位置重叠，沿第三方向Z上第三开口在绝缘层91的背离电容阵列71的表面的垂直投影可至少大体上与第三沟槽K6的位置重叠。通过设置第二掩膜层，能够快速准确的确定第三沟槽K6的刻蚀位置，便于对绝缘层91进行刻蚀处理形成第三沟槽K6，进而在第三沟槽K6内形成半导体柱引出触点11。
通过本申请的一些实施例提供了一种半导体器件100及其制造方法，该制造方法形成的半导体器件100中的相邻半导体柱10之间还形成有屏蔽条20，该屏蔽条20能够防止相邻半导体柱10之间的干扰，进而降低了相邻半导体柱 10之间的耦合效应。
基于上述的半导体器件100及其制作方法，参考图38所示，本申请实施例还提供了一种存储器320，所述存储器320包括：
阵列存储结构321，所述阵列存储结构321包括如图3至图36所示实施例的半导体器件100；以及外围电路322，所述外围电路322与所述阵列存储结构321相接，以控制所述阵列存储结构321的偏压。
基于上述的半导体器件100及其制作方法，参考图38所示，本申请实施例还提供了一种存储系统300，存储系统300包括如图38所示的存储器320，以及与所述存储器320耦合的控制器，所述控制器用于控制所述存储器执行数据写入和读取操作。
具体地，如图38所示，存储系统300包括控制器310和一个或多个存储器320，其中，存储器320(3D NAND Flash)包括阵列存储结构321(Array)和外围电路322(Periphery Circuit)，其中，阵列存储结构321包括上述任一项的半导体器件100。存储系统300可通过控制器310与主机400通信，其中，控制器310可经由一个或多个存储器320中的通道连接到一个或多个存储器320。每个存储器320可以由控制器310经由存储器320中的通道来管理。
具体地，其中，阵列存储结构321用于存储信息，而外围电路322可以位于阵列存储结构321的上方或者下方，也可以位于阵列存储结构321的四周，外围电路322用于控制对应的阵列存储结构321。另外，该半导体器件100还可以应用于其它的微电子器件中，比如，非易失闪存(Nor Flash)等，具体不作限制。此外，本申请实施例的半导体器件100可以是存储器320，可以是外围存储器中的一部分，不作特别地限定。
以上对本申请实施例所提供的一种半导体器件100及其制作方法、存储器和存储系统300进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应 用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (30)

  1. 一种半导体器件，其中，包括：
    半导体柱阵列，所述半导体柱阵列包括沿第一方向与第二方向阵列排布且在第三方向上延伸的多个半导体柱，所述第一方向、所述第二方向、以及所述第三方向彼此相交叉；
    沿所述第二方向上相邻所述半导体柱之间设有一栅极条和一屏蔽条，所述栅极条与所述屏蔽条沿所述第一方向延伸并在第二方向上相间隔；以及，
    阻隔条，所述阻隔条沿所述第一方向延伸，所述阻隔条与所述屏蔽条在所述第三方向上的一端连接，且位于所述屏蔽条与所述栅极条在所述第三方向上的同一侧。
  2. 根据权利要求1所述的半导体器件，其中，所述半导体器件还包括：栅极导接结构，所述栅极导接结构沿所述第一方向延伸，且位于所述栅极条在所述第三方向上的所述一端与所述阻隔条之间，并与所述阻隔条至少部分并列。
  3. 根据权利要求2所述的半导体器件，其中，所述半导体器件还包括：位于所述半导体柱阵列在所述第三方向上的一端的栅极引出触点，所述栅极引出触点与所述栅极导接结构连接。
  4. 根据权利要求3所述的半导体器件，其中，所述半导体器件还包括：位于所述半导体柱阵列在所述第三方向上的所述一端的屏蔽引出触点，所述屏蔽引出触点与所述屏蔽条连接。
  5. 根据权利要求1所述的半导体器件，其中，所述半导体器件还包括：位于所述半导体柱阵列在所述第三方向上的所述一端的半导体柱引出触点，所述半导体柱引出触点与所述半导体柱连接。
  6. 根据权利要求2所述的半导体器件，其中，所述半导体器件还包括：
    沿所述第二方向间隔排布于各行半导体柱之间的多个所述栅极条；
    沿所述第二方向间隔排布于所述各行半导体柱之间，且与所述多个栅极条 交错间隔排布的多个所述屏蔽条；
    沿所述第二方向间隔排布于所述各行半导体柱之间的多个所述阻隔条；以及，
    沿所述第二方向间隔排布于所述各行半导体柱之间的多个所述栅极导接结构。
  7. 根据权利要求6所述的半导体器件，其中，所述半导体器件还包括多个栅极引出触点，一个所述栅极引出触点对应于一个所述栅极导接结构，且所述多个栅极引出触点沿所述第一方向与所述第二方向同步间隔排列呈阶梯状分布。
  8. 根据权利要求6所述的半导体器件，其中，所述半导体器件还包括多个屏蔽引出触点，一个所述屏蔽引出触点对应于一个所述屏蔽条，且所述多个屏蔽引出触点沿所述第一方向与所述第二方向同步间隔排列呈阶梯状分布。
  9. 根据权利要求6所述的半导体器件，其中，所述半导体器件还包括多个栅极引出触点与多个屏蔽引出触点，一个所述栅极引出触点对应于一个所述栅极导接结构，一个所述屏蔽引出触点对应于一个所述屏蔽条，且所述多个栅极引出触点与所述多个屏蔽引出触点沿所述第一方向与所述第二方向同步交错间隔排列而呈阶梯状分布。
  10. 根据权利要求6所述的半导体器件，其中，所述半导体器件还包括多个栅极引出触点与多个屏蔽引出触点，一个所述栅极引出触点对应于一个所述栅极导接结构，一个所述屏蔽引出触点对应于一个所述屏蔽条，且所述多个栅极引出触点与所述多个屏蔽引出触点沿所述第二方向交错间隔排列。
  11. 根据权利要求1所述的半导体器件，其中，所述半导体柱在所述第二方向上的横截面尺寸，与两相邻所述半导体柱之间的间隔尺寸相等。
  12. 根据权利要求1所述的半导体器件，其中，所述半导体柱在所述第二方向上的横截面尺寸，与两相邻所述半导体柱之间的间隔尺寸的差异小于预设值。
  13. 根据权利要求1所述的半导体器件，其中，所述半导体器件还包括：
    位于所述半导体柱与所述栅极条之间以及所述半导体柱与所述屏蔽条之间的第一氧化层；
    位于所述栅极条和所述屏蔽条之间的隔离结构。
  14. 根据权利要求1所述的半导体器件，其中，所述半导体器件还包括：位于所述半导体柱阵列在所述第三方向上的另一端的电容阵列，所述电容阵列包括多个沿所述第一方向与所述第二方向阵列排布且在所述第三方向上延伸的多个电容结构，所述电容结构包括与所述半导体柱在所述第三方向上的另一端连接的第一电极层，以及位于所述第一电极层内的电容介质层和第二电极层。
  15. 一种半导体器件的制作方法，其中，包括：
    形成多个半导体柱，并使所述多个半导体柱在第一方向与第二方向阵列排布且在第三方向上延伸，所述第一方向、所述第二方向、以及所述第三方向彼此相交叉；
    在相邻的所述半导体柱之间形成一个栅极条与一个屏蔽条，并使所述栅极条与所述屏蔽条沿所述第一方向延伸并在第二方向上相间隔；以及，
    在所述屏蔽条沿所述第三方向上的一端形成阻隔条，所述阻隔条沿第一方向延伸，且位于所述屏蔽条与所述栅极条在所述第三方向上的同一侧。
  16. 根据权利要求15所述的半导体器件的制作方法，其中，所述形成多个半导体柱的步骤包括：
    提供一衬底；
    在所述衬底中形成多个沿所述第二方向延伸且沿第一方向间隔排布的隔离沟槽，并于所述隔离沟槽的内壁填入介质材料；
    形成多个沿所述第一方向延伸且沿第二方向间隔排布的栅极沟槽，而形成沿所述第一方向延伸且沿第二方向间隔排布且在第三方向上延伸的所述多个半导体柱。
  17. 根据权利要求16所述的半导体器件的制作方法，其中，所述形成一个 栅极条与一个屏蔽条的步骤，包括：
    在所述栅极沟槽的侧壁内形成第一氧化层；
    在所述第一氧化层的侧壁内形成导电层；
    去除位于所述第一氧化层的侧壁上且沿所述第三方向上靠近所述衬底的部分所述导电层，以及位于所述栅极沟槽在所述第一方向的两端部的连接部分，而形成分开的所述栅极条与所述屏蔽条。
  18. 根据权利要求17所述的半导体器件的制作方法，其中，所述制作方法还包括：在所述栅极沟槽中填入隔离材料，并使所述隔离材料覆盖所述栅极条与所述屏蔽条而形成隔离结构。
  19. 根据权利要求18所述的半导体器件的制作方法，其中，所述制作方法还包括：
    于所述半导体柱阵列在所述第三方向上的另一端形成电容阵列，并使所述电容阵列包括多个沿所述第一方向与所述第二方向阵列排布且在所述第三方向上延伸的多个电容结构，所述电容结构包括连接所述半导体柱在所述第三方向上的另一端的第一电极层，以及位于所述第一电极内的电容介质层和第二电极层。
  20. 根据权利要求19所述的半导体器件的制作方法，其中，所述制作方法还包括：
    去除所述衬底在所述第三方向上远离所述电容阵列的一端，以及位于所述栅极沟槽的底部的所述隔离结构，而露出所述栅极条在所述第三方向上的一端，以及所述屏蔽条在所述第三方向上的一端。
  21. 根据权利要求20所述的半导体器件的制作方法，其中，所述制作方法还包括：
    于所述栅极沟槽的底部形成栅极导接结构，所述栅极导接结构沿所述第一方向延伸，且位于所述栅极条以及所述隔离结构在所述第三方向上的一端，并与所述屏蔽条在所述第三方向上的所述一端相间隔。
  22. 根据权利要求21所述的半导体器件的制作方法，其中，所述制作方法还包括：
    于所述半导体柱阵列在所述第三方向上的一端形成栅极引出触点，所述栅极引出触点与所述栅极导接结构连接。
  23. 根据权利要求17所述的半导体器件的制作方法，其中，所述制作方法还包括：
    于所述半导体柱阵列在所述第三方向上的所述一端形成屏蔽引出触点，所述屏蔽引出触点与所述屏蔽条连接。
  24. 根据权利要求15所述的半导体器件的制作方法，其中，所述制作方法还包括：
    于所述半导体柱阵列在所述第三方向上的所述一端形成半导体柱引出触点，所述半导体柱引出触点与所述半导体柱连接。
  25. 根据权利要求22所述的半导体器件的制作方法，其中，所述于所述半导体柱阵列在所述第三方向上的一端形成栅极引出触点的步骤包括：
    形成多个所述栅极引出触点，一个所述栅极引出触点对应于一个所述栅极导接结构，并使所述多个栅极引出触点沿所述第一方向与所述第二方向同步间隔排列呈阶梯状分布。
  26. 根据权利要求23所述的半导体器件的制作方法，其中，所述于所述半导体柱阵列在所述第三方向上的所述一端形成屏蔽引出触点的步骤包括：
    形成多个屏蔽引出触点，一个所述屏蔽引出触点对应于一个所述屏蔽条，并使所述多个屏蔽引出触点沿所述第一方向与所述第二方向同步间隔排列呈阶梯状分布。
  27. 根据权利要求21所述的半导体器件的制作方法，其中，所述制作方法还包括形成多个栅极引出触点与多个屏蔽引出触点，一个所述栅极引出触点对应于一个所述栅极导接结构，一个所述屏蔽引出触点对应于一个所述屏蔽条，并使所述多个栅极引出触点与所述多个屏蔽引出触点沿所述第一方向与所述第 二方向同步交错间隔排列而呈阶梯状分布。
  28. 根据权利要求15所述的半导体器件的制作方法，其中，所述形成多个半导体柱的步骤包括使半导体柱在所述第二方向上的横截面尺寸，与两相邻所述半导体柱之间的间隔尺寸的差异小于预设值。
  29. 一种存储器，其中，所述存储器包括：
    阵列存储结构，所述阵列存储结构包括如权利要求1至14所述的半导体器件；以及
    外围电路，所述外围电路与所述阵列存储结构相接，以控制所述阵列存储结构的偏压。
  30. 一种存储系统，其中，包括：
    如权利要求29所述的存储器；以及
    与所述存储器耦合的控制器，所述控制器用于控制所述存储器执行数据写入和读取操作。
PCT/CN2023/106137 2023-07-06 2023-07-06 半导体器件及其制作方法、存储器和存储系统 Ceased WO2025007345A1 (zh)

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