WO2025001638A1 - 一种像素驱动电路、显示装置及驱动方法 - Google Patents

一种像素驱动电路、显示装置及驱动方法 Download PDF

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Publication number
WO2025001638A1
WO2025001638A1 PCT/CN2024/094512 CN2024094512W WO2025001638A1 WO 2025001638 A1 WO2025001638 A1 WO 2025001638A1 CN 2024094512 W CN2024094512 W CN 2024094512W WO 2025001638 A1 WO2025001638 A1 WO 2025001638A1
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Prior art keywords
transistor
coupled
driving
terminal
driving transistor
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PCT/CN2024/094512
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English (en)
French (fr)
Inventor
曹席磊
邱远游
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US18/992,953 priority Critical patent/US20260100155A1/en
Publication of WO2025001638A1 publication Critical patent/WO2025001638A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0469—Details of the physics of pixel operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present disclosure relates to the field of display technology and provides a pixel driving circuit, a display device and a driving method.
  • the driving transistor is sensitive to the oxide characteristics (light, water, oxygen, etc.), which will cause its threshold voltage to change.
  • the change in threshold voltage will cause the current of the driving transistor to be unstable during the light-emitting process, and the light-emitting device in the pixel circuit will flicker.
  • Embodiments of the present disclosure provide a pixel driving circuit, a display device, and a driving method, which are used to reduce the influence of unstable light emission of a light-emitting device caused by a change in threshold voltage.
  • a pixel driving circuit includes: a driving transistor, a light emitting device, a data writing subcircuit, a threshold compensation subcircuit and a first light emitting control subcircuit;
  • a driving transistor configured to generate a driving current according to the data voltage and a threshold voltage of the driving transistor
  • the data writing sub-circuit is coupled to the gate of the driving transistor and is configured to input the data voltage of the data signal terminal into the gate of the driving transistor in response to the signal of the scanning signal terminal;
  • the threshold compensation subcircuit is coupled to the driving transistor and is configured to provide a threshold voltage of the driving transistor to a gate of the driving transistor in response to a signal at the compensation signal terminal;
  • the first light emitting control subcircuit is coupled to the driving transistor and is configured to provide the driving current generated by the driving transistor to the light emitting device in response to a signal at the control signal terminal.
  • the threshold compensation subcircuit includes a first switch transistor and a first capacitor
  • the control terminal of the first switch transistor is coupled to the compensation signal terminal, the first terminal of the first switch transistor is coupled to the gate of the driving transistor, and the second terminal of the first switch transistor is coupled to the second electrode of the driving transistor;
  • a first terminal of the first capacitor is coupled to the gate electrode of the driving transistor, and a second terminal of the first capacitor is coupled to the second electrode of the driving transistor.
  • the data writing subcircuit includes a second switching transistor
  • the control end of the second switch transistor is coupled to the scan signal end, the first end of the second switch transistor is coupled to the data signal end, and the second end of the second switch transistor is coupled to the gate of the driving transistor.
  • the first light emitting control subcircuit includes a third switching transistor
  • the control end of the third switch transistor is coupled to the control signal end, the first end of the third switch transistor is coupled to the first power supply end, and the second end of the third switch transistor is coupled to the first electrode of the driving transistor.
  • a first reset subcircuit is further included, which is coupled to the first electrode of the driving transistor and provides a signal from the reference signal terminal to the first electrode of the driving transistor in response to a signal from the first reset signal terminal.
  • the first reset subcircuit includes a fourth switch transistor
  • the control terminal of the fourth switch transistor is coupled to the first reset signal terminal, the first terminal of the fourth switch transistor is coupled to the reference signal terminal, and the second terminal of the fourth switch transistor is coupled to the first electrode of the driving transistor.
  • a second reset circuit is further included, the second reset circuit is coupled to the gate of the driving transistor, and the second reset circuit is configured to provide an initialization signal at an initialization signal terminal to the gate of the driving transistor in response to a signal at a second reset signal terminal.
  • the second reset circuit includes a fifth switch transistor
  • the control terminal of the fifth switch transistor is coupled to the second reset signal terminal, the first terminal of the fifth switch transistor is coupled to the initialization signal terminal, and the second terminal of the fifth switch transistor is coupled to the gate of the driving transistor.
  • the second electrode of the driving transistor is coupled to the light emitting device and the threshold compensation sub-circuit.
  • it further includes a second light emitting control subcircuit, and the second electrode of the driving transistor is coupled to the light emitting device and the threshold compensation subcircuit through the second light emitting control subcircuit;
  • the second light emitting control subcircuit is configured to connect the second electrode of the driving transistor to the light emitting device in response to a signal at the control signal terminal.
  • the second light emitting control subcircuit includes a sixth switching transistor
  • the control end of the sixth switch transistor is coupled to the control signal end, the first end of the sixth switch transistor is coupled to the second electrode of the driving transistor, and the second end of the sixth switch transistor is coupled to the light emitting device.
  • a second capacitor is further included, wherein a first electrode of the second capacitor is coupled to a second electrode of the driving transistor, and a second electrode of the second capacitor is coupled to a fixed voltage signal terminal, and the fixed voltage signal terminal is the first power supply terminal or the second power supply terminal.
  • the driving transistor is a single-gate transistor or a double-gate transistor
  • the driving transistor is a dual-gate transistor
  • the first gate of the driving transistor is coupled to the data writing sub-circuit
  • the second gate of the driving transistor is coupled to the second power supply terminal.
  • the polarity of the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor and the fifth switch transistor is N-type.
  • a display device comprises any one of the above pixel driving circuits.
  • a driving method of a pixel driving circuit as described in any one of the above items comprises:
  • the second reset subcircuit resets the anode of the light emitting device via the fifth switch transistor and the first switch transistor;
  • the data writing sub-circuit inputs the data voltage of the data signal terminal into the gate of the driving transistor in response to the signal of the scanning signal terminal;
  • the threshold compensation subcircuit provides the threshold voltage of the driving transistor to the gate of the driving transistor in response to the signal at the compensation signal terminal;
  • the driving transistor generates a driving current according to the data voltage and a threshold voltage of the driving transistor
  • the first light emitting control subcircuit provides the driving current generated by the driving transistor to the light emitting device in response to the signal at the control signal terminal.
  • the threshold compensation sub-circuit is coupled to the driving transistor and is configured to provide the threshold voltage of the driving transistor to the gate of the driving transistor in response to a signal at a compensation signal end.
  • the first light-emitting control sub-circuit is coupled to the driving transistor and is configured to provide the driving current generated by the driving transistor to the light-emitting device in response to a signal at a control signal end.
  • FIG1 is a connection diagram of a pixel driving circuit in an embodiment of the present disclosure
  • FIG2 is a circuit connection diagram of a first pixel driving circuit in an embodiment of the present disclosure
  • FIG3 is a connection diagram of another pixel driving circuit in an embodiment of the present disclosure.
  • FIG4 is a circuit connection diagram of a second pixel driving circuit in an embodiment of the present disclosure.
  • FIG5 is a circuit connection diagram of a third pixel driving circuit in an embodiment of the present disclosure.
  • FIG6 is a circuit connection diagram of a fourth pixel driving circuit in an embodiment of the present disclosure.
  • FIG7 is a circuit connection diagram of a fifth pixel driving circuit in an embodiment of the present disclosure.
  • FIG8 is a circuit connection diagram of a sixth pixel driving circuit in an embodiment of the present disclosure.
  • FIG9 is a timing diagram corresponding to the second pixel driving circuit in the embodiment of the present disclosure.
  • FIG. 10 is a flow chart of a driving method of a pixel driving circuit in an embodiment of the present disclosure.
  • the driving transistor is sensitive to the characteristics of oxides (light, water, oxygen, etc.), which will cause its threshold voltage to change.
  • oxides light, water, oxygen, etc.
  • the change in threshold voltage will cause the current of the driving transistor to be unstable during the light-emitting process, and the light-emitting device in the pixel circuit will flicker.
  • a pixel driving circuit provided in an embodiment of the present disclosure includes: a driving transistor DT, a light emitting device LED, a data writing subcircuit 001 , a threshold compensation subcircuit 002 and a first light emitting control subcircuit 003 .
  • the driving transistor DT is configured to generate a driving current according to the data voltage and a threshold voltage of the driving transistor DT.
  • the data writing sub-circuit 001 is coupled to the gate of the driving transistor DT, and is configured to input the data voltage of the data signal terminal Vdata into the gate of the driving transistor DT in response to the signal of the scanning signal terminal Gate.
  • the threshold compensation sub-circuit 002 is coupled to the driving transistor DT, and is configured to provide the threshold voltage of the driving transistor DT to the gate of the driving transistor DT in response to the signal of the compensation signal terminal CM.
  • the first light emitting control sub-circuit 003 is coupled to the driving transistor DT, and is configured to provide the driving current generated by the driving transistor DT to the light emitting device LED in response to the signal of the control signal terminal EM.
  • the threshold compensation sub-circuit 002 includes a first switch transistor T1 and a first capacitor C1 .
  • connection relationship between the first switch transistor T1 and other components in Figure 2 is: the control end of the first switch transistor T1 is coupled to the compensation signal end CM, the first end of the first switch transistor T1 is coupled to the gate of the driving transistor DT, and the second end of the first switch transistor T1 is coupled to the second electrode of the driving transistor DT.
  • the first switch transistor T1 is turned on.
  • connection relationship between the first capacitor C1 and other components in FIG. 2 is as follows: a first end of the first capacitor C1 is coupled to the gate of the driving transistor DT, and a second end of the first capacitor C1 is coupled to the second electrode of the driving transistor DT.
  • the first capacitor C1 is used to store the threshold voltage of the driving transistor DT.
  • the data writing sub-circuit 001 includes a second switch transistor T2 .
  • connection relationship between the second switch transistor T2 and other components in Figure 2 is: the control end of the second switch transistor T2 is coupled to the scan signal end Gate, the first end of the second switch transistor T2 is coupled to the data signal end Vdata, and the second end of the second switch transistor T2 is coupled to the gate of the driving transistor DT.
  • the second switch transistor T2 when the signal at the scan signal terminal Gate is at a high voltage, the second switch transistor T2 is turned on, and the signal at the data signal terminal Vdata reaches the first node via the turned-on second switch transistor T2.
  • the first light emitting control sub-circuit 003 includes a third switch transistor T3 .
  • connection relationship between the third switch transistor T3 and other components in Figure 2 is: the control end of the third switch transistor T3 is coupled to the control signal end EM, the first end of the third switch transistor T3 is coupled to the first power supply end Vdd, and the second end of the third switch transistor T3 is coupled to the first electrode of the driving transistor DT.
  • the third switch transistor T3 is turned on, and the signal at the first power supply terminal Vdd reaches the driving transistor DT via the turned-on third switch transistor T3.
  • the pixel driving circuit further comprises a first reset subcircuit 004 , which is coupled to the first electrode of the driving transistor DT and provides a signal from the reference signal terminal Vref to the first electrode of the driving transistor DT in response to a signal from the first reset signal terminal Re_1 .
  • the first resetting sub-circuit 004 is mainly used to reset the third node of the driving transistor DT.
  • the first reset sub-circuit 004 includes a fourth switch transistor T4 .
  • connection relationship between the fourth switch transistor T4 and other components in Figure 4 is: the control end of the fourth switch transistor T4 is coupled to the first reset signal end Re_1, the first end of the fourth switch transistor T4 is coupled to the reference signal end Vref, and the second end of the fourth switch transistor T4 is coupled to the first electrode of the driving transistor DT.
  • the fourth switch transistor T4 is turned on, and the signal at the reference signal terminal Vref reaches the third node via the turned-on fourth switch transistor T4.
  • the pixel driving circuit further includes a second reset circuit coupled to the gate of the driving transistor DT.
  • the second reset circuit is configured to respond to a signal at the second reset signal terminal Re_2 and provide an initialization signal at the initialization signal terminal Vinit to the gate of the driving transistor DT.
  • the second reset sub-circuit 005 is mainly used to reset the first node of the driving transistor DT.
  • the second reset circuit includes a fifth switch transistor T5 .
  • the connection relationship between the fifth switch transistor T5 and other components in FIG. 4 is as follows: The control terminal of the transistor T5 is coupled to the second reset signal terminal Re_2, the first terminal of the fifth switch transistor T5 is coupled to the initialization signal terminal Vinit, and the second terminal of the fifth switch transistor T5 is coupled to the gate of the driving transistor DT.
  • the fifth switch transistor T5 is turned on, and the signal at the initialization signal terminal Vinit reaches the first node via the turned-on fifth switch transistor T5.
  • the second electrode of the driving transistor DT is coupled to the light emitting device LED and the threshold compensation sub-circuit 002 .
  • the pixel driving circuit further includes a second light emitting control sub-circuit 006 , and the second electrode of the driving transistor DT is coupled to the light emitting device LED and the threshold compensation sub-circuit 002 via the second light emitting control sub-circuit 006 .
  • the second light emitting control sub-circuit 006 is configured to connect the second electrode of the driving transistor DT and the light emitting device LED in response to a signal at the control signal terminal EM.
  • the second light emitting control sub-circuit 006 includes a sixth switch transistor T6 .
  • connection relationship between the sixth switch transistor T6 and other components in Figure 5 is: the control end of the sixth switch transistor T6 is coupled to the control signal end EM, the first end of the sixth switch transistor T6 is coupled to the second electrode of the driving transistor DT, and the second end of the sixth switch transistor T6 is coupled to the light emitting device LED.
  • the sixth switch transistor T6 when the signal at the control signal terminal EM is a high voltage, the sixth switch transistor T6 is turned on, and the signal at the first power supply terminal Vdd reaches the light emitting device LED via the driving transistor DT and the turned-on sixth switch transistor T6.
  • the sixth switch transistor T6 can be turned on and off according to a preset PWM waveform, so that the turning on and off of the light emitting device LED can be further controlled by the sixth switch transistor T6. That is, in order to make the light emitting current of the light emitting device LED more delicate, the sixth switch transistor T6 can be set to a PWM waveform.
  • the pixel driving circuit further includes a second capacitor C2, a first electrode of the second capacitor C2 is coupled to the second electrode of the driving transistor DT, a second electrode of the second capacitor C2 is coupled to a fixed voltage signal terminal, and the fixed voltage signal terminal is the first power terminal Vdd or the second power terminal Vss.
  • the original luminous current of the light-emitting device LED is generated by the data voltage of the data signal terminal Vdata through the first capacitor C1 and the driving transistor DT.
  • the luminous current of the light-emitting device LED is generated by the data voltage of the data signal terminal Vdata through the first capacitor C1, the second capacitor C2 and the driving transistor DT. This can make the luminous current of the light-emitting device LED more delicate in the light-emitting stage.
  • the driving transistor DT is a single-gate transistor or a double-gate transistor.
  • the driving transistor DT is a single-gate transistor
  • its connection mode in the above pixel driving circuit is as shown in any one of FIG. 2 , FIG. 4 , FIG. 5 , FIG. 6 or FIG. 7 .
  • a first gate of the driving transistor DT is coupled to the data writing sub-circuit 001
  • a second gate of the driving transistor DT is coupled to the second power supply terminal Vss.
  • the driving transistor DT When the second gate of the driving transistor DT is coupled to the second power supply terminal Vss, the driving transistor DT can be shielded from light.
  • the polarities of the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor and the fifth switch transistor are N-type.
  • the fourth switch transistor When the first reset signal terminal Re_1 is a high voltage, the fourth switch transistor is turned on, and the signal of the reference signal terminal Vref reaches the third node N3 through the turned-on fourth switch transistor, and the voltage of the third node N3 is Vref.
  • the fifth switch transistor When the second reset signal terminal Re_2 is a high voltage, the fifth switch transistor is turned on, and the Vinit signal of the initialization signal terminal reaches the first node N1 through the turned-on fifth switch transistor.
  • the fourth switch transistor When the first reset signal terminal Re_1 is a high voltage, the fourth switch transistor is turned on, and the signal of the reference signal terminal reaches the third node N3 through the turned-on fourth switch transistor, and the voltage of the third node N3 is Vref.
  • the fifth switch transistor When the second reset signal terminal Re_2 is a high voltage, the fifth switch transistor is turned on, and the Vinit signal of the initialization signal terminal reaches the first node N1 through the turned-on fifth switch transistor.
  • the signal of the compensation signal terminal CM is a low voltage, and the first switch transistor is turned off.
  • the signal of the reference signal terminal Vref reaches the second node N2 through the turned-on fourth switch transistor and the turned-on driving transistor, and the voltage of the second node N2 is Vref.
  • the fourth switch transistor When the first reset signal terminal Re_1 is a low voltage, the fourth switch transistor is turned off, and when the second reset signal terminal Re_2 is a high voltage, the fifth switch transistor is turned on, the signal at the compensation signal terminal CM is a low voltage, the first switch transistor is turned off, the signal at the control signal terminal EM is a high voltage, the third switch transistor is turned on, and the signal at the first power supply terminal Vdd reaches the second node N2 via the turned-on third switch transistor and the driving transistor.
  • the driving transistor is turned off, the gate-source voltage of the driving transistor is reset, and the threshold voltage Vth of the driving transistor is written into the first node N1.
  • the fourth switch transistor When the first reset signal terminal Re_1 is a low voltage, the fourth switch transistor is turned off, when the second reset signal terminal Re_2 is a low voltage, the fifth switch transistor is turned off, the signal at the compensation signal terminal CM is a low voltage, the first switch transistor is turned off, when the signal at the control signal terminal EM is a low voltage, the third switch transistor is turned off, when the signal at the scan signal terminal Gate is a high voltage, the second switch transistor is turned on, and the data voltage of the data signal terminal Vdata is input to the gate of the driving transistor.
  • the fourth switch transistor When the first reset signal terminal Re_1 is at a low voltage, the fourth switch transistor is turned off. When the second reset signal terminal Re_2 is at a low voltage, the fifth switch transistor is turned off. The signal at the compensation signal terminal CM is at a low voltage, the first switch transistor is turned off. When the signal at the control signal terminal EM is at a high voltage, the third switch transistor is turned on. The driving transistor is turned on under the action of the first power supply terminal Vdd. The gate of the driving transistor The data voltage of the first electrode makes the light emitting device LED emit light through the turned-on driving transistor, and when the signal of the scanning signal terminal Gate is a low voltage, the second switching transistor is turned off.
  • k is a constant
  • Vgs is the gate-source voltage of the driving transistor
  • Vth is the threshold voltage of the driving transistor
  • the gate-source voltage of the driving transistor Vgs (Vdata-Vinit)*(Coled/C1+Coled)+Vth Formula (2)
  • Vdata is the data voltage of the data signal terminal
  • Vinit is the initialization signal of the initialization signal terminal
  • Coled is the capacitance value of the light emitting device
  • C1 is the capacitance value of the first capacitor
  • Vth is the threshold voltage of the driving transistor.
  • the light-emitting current of the light-emitting device is independent of the threshold voltage Vth of the driving transistor.
  • k is a constant
  • Vdata is the data voltage of the data signal terminal
  • Vinit is the initialization signal of the initialization signal terminal
  • Coled is the capacitance value of the light emitting device
  • C1 is the capacitance value of the first capacitor.
  • k is a constant
  • Vdata is the data voltage of the data signal terminal
  • Vinit is the initialization signal of the initialization signal terminal
  • Coled is the capacitance value of the light emitting device
  • C1 is the capacitance value of the first capacitor
  • C2 is the capacitance value of the second capacitor.
  • an embodiment of the present disclosure provides a display device, comprising any one of the above-mentioned pixel driving circuits.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • Other essential components of the display device are well understood by those skilled in the art, and are not described in detail herein, nor should they be used as limitations on the present invention.
  • an embodiment of the present disclosure provides a driving method for a pixel driving circuit, as shown in FIG10 , including:
  • Step 200 The second resetting sub-circuit resets the anode of the light-emitting device via the fifth switching transistor and the first switching transistor.
  • Step 201 the data writing sub-circuit inputs the data voltage at the data signal terminal into the gate of the driving transistor in response to the signal at the scanning signal terminal.
  • the second switch transistor when the signal at the scan signal end is at a high level, the second switch transistor is turned on, and the data voltage at the data signal end is input to the gate of the driving transistor through the second switch transistor and the first node.
  • Step 202 the threshold compensation sub-circuit provides the threshold voltage of the driving transistor to the gate of the driving transistor in response to the signal at the compensation signal terminal.
  • the first switch transistor when the signal at the compensation signal end is at a high level, the first switch transistor is turned on, and the threshold voltage of the driving transistor is provided to the gate of the driving transistor via the turned-on first switch transistor.
  • Step 203 the driving transistor generates a driving current according to the data voltage and the threshold voltage of the driving transistor.
  • the driving transistor in the light emitting stage, the driving transistor generates a driving current according to a predetermined current formula data voltage and a threshold voltage of the driving transistor.
  • Step 204 the first light-emitting control subcircuit provides the driving current generated by the driving transistor to the light-emitting device in response to the signal at the control signal terminal.
  • the third switch transistor is turned on, and the driving current generated by the driving transistor is provided to the light-emitting device.
  • the pixel driving circuit includes: a driving transistor, a light-emitting device, a data writing sub-circuit, a threshold compensation sub-circuit and a first light-emitting control sub-circuit.
  • the driving transistor is configured to generate a driving current according to a data voltage and a threshold voltage of the driving transistor.
  • the data writing sub-circuit is coupled to the gate of the driving transistor and is configured to input the data voltage of the data signal end into the gate of the driving transistor in response to a signal at a scanning signal end.
  • the threshold compensation sub-circuit is coupled to the driving transistor and is configured to provide the threshold voltage of the driving transistor to the gate of the driving transistor in response to a signal at a compensation signal end.
  • the first light-emitting control sub-circuit is coupled to the driving transistor and is configured to provide the driving current generated by the driving transistor to the light-emitting device in response to a signal at a control signal end.
  • the embodiments of the present disclosure may be provided as methods, systems, or computer program product systems. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present disclosure may take the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
  • a computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory
  • the instructions in the method generate a product including an instruction device, which implements the functions specified in one or more processes in the flowchart and/or one or more blocks in the block diagram.

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Abstract

一种像素驱动电路、显示装置及驱动方法，像素驱动电路包括：驱动晶体管（DT），被配置为根据数据电压和驱动晶体管（DT）的阈值电压产生驱动电流，数据写入子电路（001）与驱动晶体管（DT）的栅极耦接，被配置为响应于扫描信号端（Gate）的信号，将数据信号端（Vdata）的数据电压输入驱动晶体管（DT）的栅极，阈值补偿子电路（002）与驱动晶体管（DT）耦接，被配置为响应于补偿信号端（CM）的信号，将驱动晶体管（DT）的阈值电压提供给驱动晶体管（DT）的栅极，第一发光控制子电路（003）与驱动晶体管（DT）耦接，被配置为响应于控制信号端（EM）的信号，将驱动晶体管（DT）产生的驱动电流提供给发光器件（LED），像素驱动电路的设置能够消除氧化物特性对像素电路的电流的影响，提升了像素电路中发光器件（LED）的发光稳定性。

Description

一种像素驱动电路、显示装置及驱动方法
相关申请的交叉引用
本申请要求2023年06月25日提交中国国家知识产权局、申请号为202310747576.3、申请名称为“一种像素驱动电路、显示装置及驱动方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，提供了一种像素驱动电路、显示装置及驱动方法。
背景技术
对于全氧化物类型的驱动晶体管组成的像素电路而言，驱动晶体管对氧化物特性(光照、水、氧气等)敏感，会导致其阈值电压发生变化，阈值电压的变化会导致驱动晶体管在发光过程中的电流不稳定，像素电路中的发光器件会出现闪烁等的现象。
发明内容
本公开实施例提供一种像素驱动电路、显示装置及驱动方法，用以降低阈值电压变化导致的发光器件发光不稳定的影响。
本公开提供的具体技术方案如下：
第一方面，一种像素驱动电路，包括：驱动晶体管、发光器件、数据写入子电路、阈值补偿子电路和第一发光控制子电路；
驱动晶体管，被配置为根据数据电压和驱动晶体管的阈值电压产生驱动电流；
数据写入子电路与驱动晶体管的栅极耦接，被配置为响应于扫描信号端的信号，将数据信号端的数据电压输入驱动晶体管的栅极；
阈值补偿子电路与驱动晶体管耦接，被配置为响应于补偿信号端的信号，将驱动晶体管的阈值电压提供给驱动晶体管的栅极；
第一发光控制子电路与驱动晶体管耦接，被配置为响应于控制信号端的信号，将驱动晶体管产生的驱动电流提供给发光器件。
可选地，阈值补偿子电路包括第一开关晶体管和第一电容；
第一开关晶体管的控制端与补偿信号端耦接，第一开关晶体管的第一端与驱动晶体管的栅极耦接，第一开关晶体管的第二端与驱动晶体管的第二极耦接；
第一电容的第一端与驱动晶体管的栅极耦接，第一电容的第二端与驱动晶体管的第二极耦接。
可选地，数据写入子电路包括第二开关晶体管；
第二开关晶体管的控制端与扫描信号端耦接，第二开关晶体管的第一端与数据信号端耦接，第二开关晶体管的第二端与驱动晶体管的栅极耦接。
可选地，第一发光控制子电路包括第三开关晶体管；
第三开关晶体管的控制端与控制信号端耦接，第三开关晶体管的第一端与第一电源端耦接，第三开关晶体管的第二端与驱动晶体管的第一极耦接。
可选地，还包括第一复位子电路，第一复位子电路与驱动晶体管的第一极耦接，响应于第一复位信号端的信号，将参考信号端的信号提供给驱动晶体管的第一极。
可选地，第一复位子电路包括第四开关晶体管；
第四开关晶体管的控制端与第一复位信号端耦接，第四开关晶体管的第一端与参考信号端耦接，第四开关晶体管的第二端与驱动晶体管的第一极耦接。
可选地，还包括第二复位电路，第二复位电路与驱动晶体管的栅极耦接，第二复位电路被配置为响应于第二复位信号端的信号，将初始化信号端的初始化信号提供给驱动晶体管的栅极。
可选地，第二复位电路包括第五开关晶体管；
第五开关晶体管的控制端与第二复位信号端耦接，第五开关晶体管的第一端与初始化信号端耦接，第五开关晶体管的第二端与驱动晶体管的栅极耦接。
可选地，驱动晶体管的第二极与发光器件以及阈值补偿子电路耦接。
可选地，还包括第二发光控制子电路，驱动晶体管的第二极通过第二发光控制子电路与发光器件以及阈值补偿子电路耦接；
第二发光控制子电路，被配置为响应于控制信号端的信号，将驱动晶体管的第二极与发光器件导通。
可选地，第二发光控制子电路包括第六开关晶体管；
第六开关晶体管的控制端与控制信号端耦接，第六开关晶体管的第一端与驱动晶体管的第二极耦接，第六开关晶体管的第二端与发光器件耦接。
可选地，还包括第二电容，第二电容的第一极与驱动晶体管的第二极耦接，第二电容的第二极与固定电压信号端耦接，固定电压信号端为第一电源端或者第二电源端。
可选地，驱动晶体管为单栅型晶体管或者双栅型晶体管；
当驱动晶体管为双栅型晶体管时，驱动晶体管的第一栅极与数据写入子电路耦接，驱动晶体管的第二栅极与第二电源端耦接。
可选地，第一开关晶体管、第二开关晶体管、第三开关晶体管、第四开关晶体管和第五开关晶体管的极性为N型。
第二方面，一种显示装置，包括上述任一项的像素驱动电路。
第三方面，一种如上述任一项的像素驱动电路的驱动方法，包括：
第二复位子电路经第五开关晶体管和第一开关晶体管对发光器件的阳极进行复位；
数据写入子电路响应于扫描信号端的信号，将数据信号端的数据电压输入驱动晶体管的栅极；
阈值补偿子电路响应于补偿信号端的信号，将驱动晶体管的阈值电压提供给驱动晶体管的栅极；
驱动晶体管根据数据电压和驱动晶体管的阈值电压产生驱动电流；
第一发光控制子电路响应于控制信号端的信号，将驱动晶体管产生的驱动电流提供给发光器件。
本公开有益效果如下：
综上所述，本公开实施例中提供了一种像素驱动电路、显示装置及驱动方法，该像素驱动电路包括：驱动晶体管、发光器件、数据写入子电路、阈值补偿子电路和第一发光控制子电路，实施过程中，驱动晶体管，被配置为根据数据电压和驱动晶体管的阈值电压产生驱动电流，数据写入子电路与驱动晶体管的栅极耦接，被配置为响应于扫描信号端的信号，将数据信号端的数据电压输入驱动晶体管的栅极，阈值补偿子电路与驱动晶体管耦接，被配置为响应于补偿信号端的信号，将驱动晶体管的阈值电压提供给驱动晶体管的栅极，第一发光控制子电路与驱动晶体管耦接，被配置为响应于控制信号端的信号，将驱动晶体管产生的驱动电流提供给发光器件，上述像素驱动电路的设置能够消除氧化物特性对像素电路的电流的影响，提升了像素电路中发光器件的发光稳定性。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的目的和其他优点可通过在所写的说明书、权利要求书、以及附图中所特别指出的结构来实现和获得。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例中的一种像素驱动电路的连接示意图；
图2为本公开实施例中的第一种像素驱动电路的电路连接图；
图3为本公开实施例中的另一种像素驱动电路的连接示意图；
图4为本公开实施例中的第二种像素驱动电路的电路连接图；
图5为本公开实施例中的第三种像素驱动电路的电路连接图；
图6为本公开实施例中的第四种像素驱动电路的电路连接图；
图7为本公开实施例中的第五种像素驱动电路的电路连接图；
图8为本公开实施例中的第六种像素驱动电路的电路连接图；
图9为本公开实施例中的第二种像素驱动电路对应的时序图；
图10为本公开实施例中一种像素驱动电路的驱动方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开技术方案的一部分实施例，而不是全部的实施例。基于本公开文件中记载的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开技术方案保护的范围。
本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例能够使用除了在这里图示或描述的那些以外的顺序实施。
相关技术中，驱动晶体管对氧化物特性(光照、水、氧气等)敏感，会导致其阈值电压发生变化，阈值电压的变化会导致驱动晶体管在发光过程中的电流不稳定，像素电路中的发光器件会出现闪烁等的现象。
下面结合附图对本公开优选的实施方式进行详细说明。
参阅图1所示，本公开实施例中提供的一种像素驱动电路，包括：驱动晶体管DT、发光器件LED、数据写入子电路001、阈值补偿子电路002和第一发光控制子电路003。
实施过程中，上述驱动晶体管DT，被配置为根据数据电压和驱动晶体管DT的阈值电压产生驱动电流。
上述数据写入子电路001与驱动晶体管DT的栅极耦接，被配置为响应于扫描信号端Gate的信号，将数据信号端Vdata的数据电压输入驱动晶体管DT的栅极。
上述阈值补偿子电路002与驱动晶体管DT耦接，被配置为响应于补偿信号端CM的信号，将驱动晶体管DT的阈值电压提供给驱动晶体管DT的栅极。
上述第一发光控制子电路003与驱动晶体管DT耦接，被配置为响应于控制信号端EM的信号，将驱动晶体管DT产生的驱动电流提供给发光器件LED。
参阅图2所示，上述阈值补偿子电路002包括第一开关晶体管T1和第一电容C1。
第一开关晶体管T1与图2中其他元器件之间的连接关系为：第一开关晶体管T1的控制端与补偿信号端CM耦接，第一开关晶体管T1的第一端与驱动晶体管DT的栅极耦接，第一开关晶体管T1的第二端与驱动晶体管DT的第二极耦接。
实施过程中，当补偿信号端CM的信号为高电压时，第一开关晶体管T1导通。
第一电容C1与图2中其他元器件之间的连接关系为：第一电容C1的第一端与驱动晶体管DT的栅极耦接，第一电容C1的第二端与驱动晶体管DT的第二极耦接。
实施过程中，第一电容C1用于存储驱动晶体管DT的阈值电压。
参阅图2所示，数据写入子电路001包括第二开关晶体管T2。
第二开关晶体管T2与图2中其他元器件之间的连接关系为：第二开关晶体管T2的控制端与扫描信号端Gate耦接，第二开关晶体管T2的第一端与数据信号端Vdata耦接，第二开关晶体管T2的第二端与驱动晶体管DT的栅极耦接。
实施过程中，当扫描信号端Gate的信号为高电压时，第二开关晶体管T2导通，数据信号端Vdata的信号经导通的第二开关晶体管T2到达第一节点。
参阅图2所示，第一发光控制子电路003包括第三开关晶体管T3。
第三开关晶体管T3与图2中其他元器件之间的连接关系为：第三开关晶体管T3的控制端与控制信号端EM耦接，第三开关晶体管T3的第一端与第一电源端Vdd耦接，第三开关晶体管T3的第二端与驱动晶体管DT的第一极耦接。
实施过程中，当控制信号端EM的信号为高电压时，第三开关晶体管T3导通，第一电源端Vdd的信号经导通的第三开关晶体管T3到达驱动晶体管DT。
参阅图3所示，上述像素驱动电路还包括第一复位子电路004，第一复位子电路004与驱动晶体管DT的第一极耦接，响应于第一复位信号端Re_1的信号，将参考信号端Vref的信号提供给驱动晶体管DT的第一极。
实施过程中，上述第一复位子电路004主要用于为驱动晶体管DT的第三节点进行复位。
参阅图4所示，上述第一复位子电路004包括第四开关晶体管T4。
第四开关晶体管T4与图4中其他元器件之间的连接关系为：第四开关晶体管T4的控制端与第一复位信号端Re_1耦接，第四开关晶体管T4的第一端与参考信号端Vref耦接，第四开关晶体管T4的第二端与驱动晶体管DT的第一极耦接。
实施过程中，第一复位信号端Re_1的信号为高电压时，第四开关晶体管T4导通，参考信号端Vref的信号经导通的第四开关晶体管T4到达第三节点。
参阅图4所示，上述像素驱动电路还包括第二复位电路，第二复位电路与驱动晶体管DT的栅极耦接，第二复位电路被配置为响应于第二复位信号端Re_2的信号，将初始化信号端Vinit的初始化信号提供给驱动晶体管DT的栅极。
实施过程中，上述第二复位子电路005主要用于为驱动晶体管DT的第一节点进行复位。
参阅图4所示，第二复位电路包括第五开关晶体管T5。
第五开关晶体管T5与图4中其他元器件之间的连接关系为：第五开关晶 体管T5的控制端与第二复位信号端Re_2耦接，第五开关晶体管T5的第一端与初始化信号端Vinit耦接，第五开关晶体管T5的第二端与驱动晶体管DT的栅极耦接。
实施过程中，当第二复位信号端Re_2的信号为高电压时，第五开关晶体管T5导通，初始化信号端Vinit的信号经导通的第五开关晶体管T5到达第一节点。
参阅图4所示，驱动晶体管DT的第二极与发光器件LED以及阈值补偿子电路002耦接。
参阅图4所示，上述像素驱动电路还包括第二发光控制子电路006，驱动晶体管DT的第二极通过第二发光控制子电路006与发光器件LED以及阈值补偿子电路002耦接。
实施过程中，第二发光控制子电路006，被配置为响应于控制信号端EM的信号，将驱动晶体管DT的第二极与发光器件LED导通。
参阅图5所示，第二发光控制子电路006包括第六开关晶体管T6。
第六开关晶体管T6与图5中其他元器件之间的连接关系为：第六开关晶体管T6的控制端与控制信号端EM耦接，第六开关晶体管T6的第一端与驱动晶体管DT的第二极耦接，第六开关晶体管T6的第二端与发光器件LED耦接。
实施过程中，在控制信号端EM的信号为高电压时，第六开关晶体管T6导通，第一电源端Vdd的信号经驱动晶体管DT、导通的第六开关晶体管T6到达发光器件LED。上述第六开关晶体管T6可按照预设的PWM波形进行打开和关闭，从而通过第六开关晶体管T6来进一步控制发光器件LED的打开和关闭。即为了使发光器件LED的发光电流更加细腻，可将上述第六开关晶体管T6设置为PWM波形。
参阅图6和图7所示，上述像素驱动电路还包括第二电容C2，第二电容C2的第一极与驱动晶体管DT的第二极耦接，第二电容C2的第二极与固定电压信号端耦接，固定电压信号端为第一电源端Vdd或者第二电源端Vss。
发光器件LED原有的发光电流是数据信号端Vdata的数据电压经第一电容C1和驱动晶体管DT产生的，设置了上述第二电容C2后，发光器件LED的发光电流是数据信号端Vdata的数据电压经第一电容C1、第二电容C2和驱动晶体管DT产生的，这样能使发光器件LED在发光阶段的发光电流更加细腻。
为了使电路的连接更加灵活，在另一些实施例中，上述驱动晶体管DT为单栅型晶体管或者双栅型晶体管。
当驱动晶体管DT为单栅型晶体管时，其在上述像素驱动电路中的连接方式如图2、图4、图5、图6或者图7中的任意一个图所示。
当驱动晶体管DT为双栅型晶体管时，参阅图8所示，驱动晶体管DT的第一栅极与数据写入子电路001耦接，驱动晶体管DT的第二栅极与第二电源端Vss耦接。
当驱动晶体管DT的第二栅极与第二电源端Vss耦接后，能对驱动晶体管DT起到挡光的作用。
需要补充说明的是，上述第一开关晶体管、第二开关晶体管、第三开关晶体管、第四开关晶体管和第五开关晶体管的极性为N型。
参阅图9所示，在介绍完上述像素驱动电路的电路连接情况后，下面结合时序图详细介绍下上述像素驱动电路的工作过程。
时序t1阶段：Re_1＝1，Re_2＝1，CM＝1，EM＝0，Gate＝0
当第一复位信号端Re_1为高电压时，第四开关晶体管导通，参考信号端Vref的信号经导通的第四开关晶体管到达第三节点N3，第三节点N3的电压为Vref，当第二复位信号端Re_2为高电压时，第五开关晶体管导通，初始化信号端的Vinit信号经导通的第五开关晶体管到达第一节点N1，同时，补偿信号端CM的信号为高电压，第一开关晶体管导通，初始化信号端的Vinit信号经第一节点N1和导通的第一开关晶体管到达第二节点N2。由于，Vinit大于Vref，驱动晶体管DT的栅源电压为Vgs＝Vinit-Vref，并且，Vgs大于Vth，驱动晶体管DT导通。
时序t2阶段：Re_1＝1，Re_2＝1，CM＝0，EM＝0，Gate＝0
当第一复位信号端Re_1为高电压时，第四开关晶体管导通，参考信号端的信号经导通的第四开关晶体管到达第三节点N3，第三节点N3的电压为Vref，当第二复位信号端Re_2为高电压时，第五开关晶体管导通，初始化信号端的Vinit信号经导通的第五开关晶体管到达第一节点N1，同时，补偿信号端CM的信号为低电压，第一开关晶体管截止。参考信号端Vref的信号经导通的第四开关晶体管、导通的驱动晶体管到达第二节点N2，第二节点N2的电压为Vref。
时序t3阶段：Re_1＝0，Re_2＝1，CM＝0，EM＝1，Gate＝0
当第一复位信号端Re_1为低电压时，第四开关晶体管截止，当第二复位信号端Re_2为高电压时，第五开关晶体管导通，补偿信号端CM的信号为低电压，第一开关晶体管截止，控制信号端EM的信号为高电压，第三开关晶体管导通，第一电源端Vdd的信号经导通的第三开关晶体管和驱动晶体管到达第二节点N2，在第二节点N2的电压变化到VDD的过程中，具体的，第二节点N2的电压变化到Vinit-Vth时，驱动晶体管截止，驱动晶体管的栅源电压重置，驱动晶体管的阈值电压Vth写入到第一节点N1中。
时序t4阶段：Re_1＝0，Re_2＝0，CM＝0，EM＝0，Gate＝1
当第一复位信号端Re_1为低电压时，第四开关晶体管截止，当第二复位信号端Re_2为低电压时，第五开关晶体管截止，补偿信号端CM的信号为低电压，第一开关晶体管截止，控制信号端EM的信号为低电压时，第三开关晶体管截止，扫描信号端Gate的信号为高电压时，第二开关晶体管导通，数据信号端Vdata的数据电压输入驱动晶体管的栅极。
时序t5阶段：Re_1＝0，Re_2＝0，CM＝0，EM＝1，Gate＝0
当第一复位信号端Re_1为低电压时，第四开关晶体管截止，当第二复位信号端Re_2为低电压时，第五开关晶体管截止，补偿信号端CM的信号为低电压，第一开关晶体管截止，控制信号端EM的信号为高电压时，第三开关晶体管导通，驱动晶体管在第一电源端Vdd的作用下导通，驱动晶体管的栅 极的数据电压经导通的驱动晶体管使发光器件LED发光，扫描信号端Gate的信号为低电压时，第二开关晶体管截止。
上述发光器件LED的发光电流I＝1/2k(Vgs-Vth)2公式(1)
上述公式(1)中，k为常数，Vgs为驱动晶体管的栅源电压，Vth为驱动晶体管的阈值电压。
驱动晶体管的栅源电压Vgs＝(Vdata-Vinit)*(Coled/C1+Coled)+Vth    公式(2)
上述公式(2)中，Vdata为数据信号端的数据电压，Vinit为初始化信号端的初始化信号，Coled为发光器件的电容值，C1为第一电容的电容值，Vth为驱动晶体管的阈值电压。
将公式(2)代入到公式(1)中，简化发光电流的公式I＝1/2k[(Vdata-Vinit)*(Coled/C1+Coled)+Vth-Vth]2＝1/2k[(Vdata-Vinit)*(Coled/C1+Coled)]2
即得到发光电流的公式(3)I＝1/2k[(Vdata-Vinit)*(Coled/C1+Coled)]2   公式(3)
由上述公式(3)可知，通过上述像素驱动电路的设置，发光器件的发光电流与驱动晶体管的阈值电压Vth无关。
上述公式(3)中，k为常数，Vdata为数据信号端的数据电压，Vinit为初始化信号端的初始化信号，Coled为发光器件的电容值，C1为第一电容的电容值。
进一步的，在加入上述第二电容后，发光器件的发光电流为I＝1/2k[(Vdata-Vinit)*(Coled+C2/C1+Coled+C2)]2公式(4)。
上述公式(4)中，k为常数，Vdata为数据信号端的数据电压，Vinit为初始化信号端的初始化信号，Coled为发光器件的电容值，C1为第一电容的电容值，C2为第二电容的电容值。
基于同一发明构思，本公开实施例中提供了一种显示装置，包括上述任一项的像素驱动电路。
在本发明实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
基于同一发明构思，本公开实施例中提供了一种像素驱动电路的驱动方法，参阅图10所示，包括：
步骤200：第二复位子电路经第五开关晶体管和第一开关晶体管对发光器件的阳极进行复位。
步骤201：数据写入子电路响应于扫描信号端的信号，将数据信号端的数据电压输入驱动晶体管的栅极。
实施过程中，在扫描信号端的信号为高电平时，第二开关晶体管导通，数据信号端的数据电压经过第二开关晶体管和第一节点输入到驱动晶体管的栅极。
步骤202：阈值补偿子电路响应于补偿信号端的信号，将驱动晶体管的阈值电压提供给驱动晶体管的栅极。
实施过程中，在补偿信号端的信号为高电平时，第一开关晶体管导通，驱动晶体管的阈值电压经导通的第一开关晶体管提供给驱动晶体管的栅极。
步骤203：驱动晶体管根据数据电压和驱动晶体管的阈值电压产生驱动电流。
实施过程中，在发光阶段，驱动晶体管根据既定的电流公式数据电压和驱动晶体管的阈值电压产生驱动电流。
步骤204：第一发光控制子电路响应于控制信号端的信号，将驱动晶体管产生的驱动电流提供给发光器件。
在发光阶段，控制信号端的信号为高电平时，第三开关晶体管导通，驱动晶体管产生的驱动电流提供给发光器件。
综上所述，本公开实施例中提供的一种像素驱动电路、显示装置及驱动方法，该像素驱动电路包括：驱动晶体管、发光器件、数据写入子电路、阈值补偿子电路和第一发光控制子电路，实施过程中，驱动晶体管，被配置为根据数据电压和驱动晶体管的阈值电压产生驱动电流，数据写入子电路与驱动晶体管的栅极耦接，被配置为响应于扫描信号端的信号，将数据信号端的数据电压输入驱动晶体管的栅极，阈值补偿子电路与驱动晶体管耦接，被配置为响应于补偿信号端的信号，将驱动晶体管的阈值电压提供给驱动晶体管的栅极，第一发光控制子电路与驱动晶体管耦接，被配置为响应于控制信号端的信号，将驱动晶体管产生的驱动电流提供给发光器件，上述像素驱动电路的设置能够消除氧化物特性对像素电路的电流的影响，提升了像素电路中发光器件的发光稳定性。
本领域内的技术人员应明白，本公开的实施例可提供为方法、系统、或计算机程序产品系统。因此，本公开可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本公开可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品系统的形式。
本公开是参照根据本公开的方法、设备(系统)、和计算机程序产品系统的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器 中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (16)

  1. 一种像素驱动电路，其中，包括：驱动晶体管、发光器件、数据写入子电路、阈值补偿子电路和第一发光控制子电路；
    所述驱动晶体管，被配置为根据数据电压和所述驱动晶体管的阈值电压产生驱动电流；
    所述数据写入子电路与所述驱动晶体管的栅极耦接，被配置为响应于扫描信号端的信号，将数据信号端的数据电压输入所述驱动晶体管的栅极；
    所述阈值补偿子电路与所述驱动晶体管耦接，被配置为响应于补偿信号端的信号，将所述驱动晶体管的所述阈值电压提供给所述驱动晶体管的栅极；
    所述第一发光控制子电路与所述驱动晶体管耦接，被配置为响应于控制信号端的信号，将所述驱动晶体管产生的所述驱动电流提供给所述发光器件。
  2. 如权利要求1所述的像素驱动电路，其中，所述阈值补偿子电路包括第一开关晶体管和第一电容；
    所述第一开关晶体管的控制端与所述补偿信号端耦接，所述第一开关晶体管的第一端与所述驱动晶体管的栅极耦接，所述第一开关晶体管的第二端与所述驱动晶体管的第二极耦接；
    所述第一电容的第一端与所述驱动晶体管的栅极耦接，所述第一电容的第二端与所述驱动晶体管的第二极耦接。
  3. 如权利要求1所述的像素驱动电路，其中，所述数据写入子电路包括第二开关晶体管；
    所述第二开关晶体管的控制端与所述扫描信号端耦接，所述第二开关晶体管的第一端与所述数据信号端耦接，所述第二开关晶体管的第二端与所述驱动晶体管的栅极耦接。
  4. 如权利要求1所述的像素驱动电路，其中，所述第一发光控制子电路包括第三开关晶体管；
    所述第三开关晶体管的控制端与所述控制信号端耦接，所述第三开关晶 体管的第一端与第一电源端耦接，所述第三开关晶体管的第二端与所述驱动晶体管的第一极耦接。
  5. 如权利要求1-4任一项所述的像素驱动电路，其中，还包括第一复位子电路，所述第一复位子电路与所述驱动晶体管的第一极耦接，响应于第一复位信号端的信号，将参考信号端的信号提供给所述驱动晶体管的第一极。
  6. 如权利要求5所述的像素驱动电路，其中，所述第一复位子电路包括第四开关晶体管；
    所述第四开关晶体管的控制端与所述第一复位信号端耦接，所述第四开关晶体管的第一端与所述参考信号端耦接，所述第四开关晶体管的第二端与所述驱动晶体管的第一极耦接。
  7. 如权利要求1-4任一项所述的像素驱动电路，其中，还包括第二复位子电路，所述第二复位子电路与所述驱动晶体管的栅极耦接，所述第二复位子电路被配置为响应于第二复位信号端的信号，将初始化信号端的初始化信号提供给所述驱动晶体管的栅极。
  8. 如权利要求7所述的像素驱动电路，其中，所述第二复位子电路包括第五开关晶体管；
    所述第五开关晶体管的控制端与所述第二复位信号端耦接，所述第五开关晶体管的第一端与所述初始化信号端耦接，所述第五开关晶体管的第二端与所述驱动晶体管的栅极耦接。
  9. 如权利要求1-4任一项所述的像素驱动电路，其中，所述驱动晶体管的第二极与所述发光器件以及所述阈值补偿子电路耦接。
  10. 如权利要求1-4任一项所述的像素驱动电路，其中，还包括第二发光控制子电路，所述驱动晶体管的第二极通过所述第二发光控制子电路与所述发光器件以及所述阈值补偿子电路耦接；
    所述第二发光控制子电路，被配置为响应于所述控制信号端的信号，将所述驱动晶体管的第二极与所述发光器件导通。
  11. 如权利要求9所述的像素驱动电路，其中，所述第二发光控制子电 路包括第六开关晶体管；
    所述第六开关晶体管的控制端与所述控制信号端耦接，所述第六开关晶体管的第一端与所述驱动晶体管的第二极耦接，所述第六开关晶体管的第二端与所述发光器件耦接。
  12. 如权利要求1-4任一项所述的像素驱动电路，其中，还包括第二电容，所述第二电容的第一极与所述驱动晶体管的第二极耦接，所述第二电容的第二极与固定电压信号端耦接，所述固定电压信号端为所述第一电源端或者所述第二电源端。
  13. 如权利要求1-11任一项所述的像素驱动电路，其中，所述驱动晶体管为单栅型晶体管或者双栅型晶体管；
    当所述驱动晶体管为双栅型晶体管时，所述驱动晶体管的第一栅极与所述数据写入子电路耦接，所述驱动晶体管的第二栅极与所述第二电源端耦接。
  14. 如权利要求1-11任一项所述的像素驱动电路，其中，所述第一开关晶体管、所述第二开关晶体管、所述第三开关晶体管、所述第四开关晶体管和所述第五开关晶体管的极性为N型。
  15. 一种显示装置，其中，包括如权利要求1-14任一项所述的像素驱动电路。
  16. 一种如权利要求1-14任一项所述的像素驱动电路的驱动方法，其中，包括：
    第二复位子电路经第五开关晶体管和第一开关晶体管对发光器件的阳极进行复位；
    数据写入子电路响应于扫描信号端的信号，将数据信号端的数据电压输入所述驱动晶体管的栅极；
    阈值补偿子电路响应于补偿信号端的信号，将所述驱动晶体管的所述阈值电压提供给所述驱动晶体管的栅极；
    驱动晶体管根据数据电压和所述驱动晶体管的阈值电压产生驱动电流；
    第一发光控制子电路响应于控制信号端的信号，将所述驱动晶体管产生 的所述驱动电流提供给所述发光器件。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116665585B (zh) * 2023-06-25 2026-01-13 京东方科技集团股份有限公司 一种像素驱动电路、显示装置及驱动方法
CN117275408B (zh) * 2023-10-30 2026-05-01 昆山国显光电有限公司 像素电路及其驱动方法、显示面板
TWI883932B (zh) * 2024-04-24 2025-05-11 友達光電股份有限公司 畫素電路
CN121191452A (zh) * 2024-06-20 2025-12-23 京东方科技集团股份有限公司 一种像素驱动电路、显示装置及驱动方法
CN118553193A (zh) * 2024-06-24 2024-08-27 京东方科技集团股份有限公司 一种像素驱动电路、显示装置及驱动方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105427792A (zh) * 2016-01-05 2016-03-23 京东方科技集团股份有限公司 像素补偿电路及驱动方法、显示面板和显示装置
CN108597450A (zh) * 2018-04-26 2018-09-28 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN111462698A (zh) * 2020-04-28 2020-07-28 合肥京东方光电科技有限公司 一种像素驱动电路、显示面板及显示装置
US20210035502A1 (en) * 2019-07-29 2021-02-04 Lg Display Co., Ltd. Display device
CN112509518A (zh) * 2020-11-27 2021-03-16 合肥维信诺科技有限公司 像素电路及其驱动方法、显示面板
CN115188333A (zh) * 2022-07-15 2022-10-14 京东方科技集团股份有限公司 一种像素电路、其驱动方法及显示装置
CN116665585A (zh) * 2023-06-25 2023-08-29 京东方科技集团股份有限公司 一种像素驱动电路、显示装置及驱动方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101058108B1 (ko) * 2009-09-14 2011-08-24 삼성모바일디스플레이주식회사 화소 회로 및 이를 이용한 유기 발광 표시장치
CN106531074B (zh) * 2017-01-10 2019-02-05 上海天马有机发光显示技术有限公司 有机发光像素驱动电路、驱动方法以及有机发光显示面板
KR102555805B1 (ko) * 2018-10-01 2023-07-17 삼성디스플레이 주식회사 표시 패널의 화소 및 표시 장치
KR102866119B1 (ko) * 2020-06-10 2025-10-01 엘지디스플레이 주식회사 화소 구동 회로를 포함한 전계발광 표시패널
CN111696473B (zh) * 2020-06-17 2022-07-15 昆山国显光电有限公司 像素驱动电路、像素驱动电路的驱动方法和显示面板
KR102819031B1 (ko) * 2021-07-30 2025-06-12 보에 테크놀로지 그룹 컴퍼니 리미티드 화소 구동 회로, 그 구동 방법 및 표시 패널
CN115294940A (zh) * 2022-08-30 2022-11-04 云谷（固安）科技有限公司 像素电路及其驱动方法和显示面板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105427792A (zh) * 2016-01-05 2016-03-23 京东方科技集团股份有限公司 像素补偿电路及驱动方法、显示面板和显示装置
CN108597450A (zh) * 2018-04-26 2018-09-28 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
US20210035502A1 (en) * 2019-07-29 2021-02-04 Lg Display Co., Ltd. Display device
CN111462698A (zh) * 2020-04-28 2020-07-28 合肥京东方光电科技有限公司 一种像素驱动电路、显示面板及显示装置
CN112509518A (zh) * 2020-11-27 2021-03-16 合肥维信诺科技有限公司 像素电路及其驱动方法、显示面板
CN115188333A (zh) * 2022-07-15 2022-10-14 京东方科技集团股份有限公司 一种像素电路、其驱动方法及显示装置
CN116665585A (zh) * 2023-06-25 2023-08-29 京东方科技集团股份有限公司 一种像素驱动电路、显示装置及驱动方法

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