WO2025001392A1 - 一种多路错相功率因数校正电路、电源电路和显示设备 - Google Patents

一种多路错相功率因数校正电路、电源电路和显示设备 Download PDF

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Publication number
WO2025001392A1
WO2025001392A1 PCT/CN2024/085362 CN2024085362W WO2025001392A1 WO 2025001392 A1 WO2025001392 A1 WO 2025001392A1 CN 2024085362 W CN2024085362 W CN 2024085362W WO 2025001392 A1 WO2025001392 A1 WO 2025001392A1
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Prior art keywords
factor correction
power factor
output
driving
current source
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PCT/CN2024/085362
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English (en)
French (fr)
Inventor
李锦乐
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Shenzhen TCL New Technology Co Ltd
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Shenzhen TCL New Technology Co Ltd
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Publication of WO2025001392A1 publication Critical patent/WO2025001392A1/zh
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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0043—Converters switched with a phase shift, i.e. interleaved
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from AC input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters

Definitions

  • the present application relates to the technical field of power factor correction, and in particular to a multi-path out-of-phase power factor correction circuit, a power supply circuit and a display device.
  • PFC power factor correction
  • a single driver chip outputs two drive signals to drive two power switch tubes to work alternately, so as to form two power factor correction channels.
  • Two interlaced driving signals are formed by a single driving chip, which requires a complex circuit structure of the single driving chip and is costly.
  • the purpose of the present application is to provide a multi-path out-of-phase power factor correction circuit, a power supply circuit and a display device, which can reduce the structural requirements for a single driving part to reduce costs.
  • the multi-path phase-shifted power factor correction circuit comprises at least two power factor correction modules connected in parallel, each power factor correction module is connected to a corresponding driving module, and the driving modules are connected in series step by step;
  • the first stage driving module is used to output a driving signal to the corresponding power factor correction module; the second stage driving module is used to delay the driving signal output by the previous stage driving module and then output it to the corresponding power factor correction module.
  • the power factor correction module is used to correct the power factor of the input power according to the corresponding drive signal.
  • the latter stage driving module includes a driving control unit and a delay unit, and the driving control unit is connected to the delay unit;
  • the drive control unit is used to output a control signal to the delay unit according to the drive signal output by the previous stage drive module; the delay unit is used to output a trigger signal to the drive control unit after timing the first time according to the control signal; the drive control unit is also used to output the drive signal output by the previous stage drive module to the corresponding power factor correction module according to the trigger signal.
  • the delay unit includes a delay timing subunit and a pulse width timing subunit, and both the delay timing subunit and the pulse width timing subunit are connected to the driving control unit;
  • the driving control unit is used to output a first control signal when detecting a rising edge of a driving signal output by a previous stage driving module, and output a second control signal when detecting a first falling edge after the rising edge;
  • the delay timing subunit is used to start timing according to the first control signal and output a first trigger signal after timing the first time;
  • the pulse width timing subunit is used to start timing according to the first control signal, and output the second timing time according to the second control signal, and output the second trigger signal after restarting the timing of the second time when the delay timing subunit outputs the first trigger signal;
  • the driving control unit is further configured to output a high-level driving signal according to the first trigger signal, and output a low-level driving signal according to the second trigger signal.
  • the delay timing subunit includes a first current source, a first switch and a first capacitor, the input end of the first current source is connected to electricity, the output end of the first current source is connected to one end of the first switch, one end of the first capacitor and the driving control unit, the other end of the first switch is grounded, and the other end of the first capacitor is grounded;
  • the first current source is used to charge the first capacitor to a first voltage according to the first control signal; the driving control unit is also used to control the first current source to be disconnected when the first capacitor is charged to the first voltage.
  • the first switch is turned on, so that the first capacitor is discharged.
  • the pulse width timing subunit includes a second current source, a third current source and a second capacitor, the input end of the second current source is connected to electricity, the output end of the second current source is connected to one end of the second capacitor, the input end of the third current source and the driving control unit, and the output end of the third current source and the other end of the second capacitor are grounded;
  • the second current source is used to be turned on according to the first control signal to charge the second capacitor, and to be turned off according to the second control signal to stop charging the second capacitor;
  • the drive control unit is also used to control the third current source to be turned on to discharge the second capacitor when the delay timing subunit outputs the first trigger signal, and to control the third current source to be turned off after the second capacitor is discharged to the second voltage.
  • the duration of the first time is related to the charging current of the first current source.
  • the charging current of the second current source is the same as the discharging current of the third current source.
  • the duration of the first time is not less than the duration of the second time.
  • the power factor correction module includes an inductor, a diode and a power switch tube, one end of the inductor is connected to the input end, the other end of the inductor is connected to the first end of the power switch tube and the positive electrode of the diode, the negative electrode of the diode is connected to the output end, the second end of the power switch tube is grounded, and the third end of the power switch tube is connected to the drive module.
  • the multi-path staggered-phase power factor correction circuit also includes a rectifier bridge, wherein the first pin of the rectifier bridge is connected to the L line of the AC power supply, the second pin of the rectifier bridge is connected to the power factor correction module, the third pin of the rectifier bridge is connected to the N line of the AC power supply, and the fourth pin of the rectifier bridge is grounded.
  • the embodiment of the present application further provides a power supply circuit, which includes the above-mentioned multi-channel staggered phase power factor correction circuit;
  • the multi-channel staggered phase power factor correction circuit includes at least two power factor correction modules connected in parallel, each power factor correction module is correspondingly connected to a driving module, and the driving modules are connected in series step by step;
  • the first-stage driving module is used to output a driving signal to the corresponding power factor correction module;
  • the latter stage driving module is used to delay the driving signal output by the former stage driving module and then output it to the corresponding power factor correction module;
  • the power factor correction module is used to perform power factor correction on the input power supply according to the corresponding driving signal.
  • the latter stage driving module includes a driving control unit and a delay unit, and the driving control unit is connected to the delay unit;
  • the drive control unit is used to output a control signal to the delay unit according to the drive signal output by the previous stage drive module; the delay unit is used to output a trigger signal to the drive control unit after timing the first time according to the control signal; the drive control unit is also used to output the drive signal output by the previous stage drive module to the corresponding power factor correction module according to the trigger signal.
  • the delay unit includes a delay timing subunit and a pulse width timing subunit, and both the delay timing subunit and the pulse width timing subunit are connected to the driving control unit;
  • the driving control unit is used to output a first control signal when detecting a rising edge of a driving signal output by a previous stage driving module, and output a second control signal when detecting a first falling edge after the rising edge;
  • the delay timing subunit is used to start timing according to the first control signal and output a first trigger signal after timing the first time;
  • the pulse width timing subunit is used to start timing according to the first control signal, and output the second timing time according to the second control signal, and output the second trigger signal after restarting the timing of the second time when the delay timing subunit outputs the first trigger signal;
  • the driving control unit is further configured to output a high-level driving signal according to the first trigger signal, and output a low-level driving signal according to the second trigger signal.
  • the delay timing subunit includes a first current source, a first switch and a first capacitor, the input end of the first current source is connected to electricity, the output end of the first current source is connected to one end of the first switch, one end of the first capacitor and the driving control unit, the other end of the first switch is grounded, and the other end of the first capacitor is grounded;
  • the first current source is used to charge the first capacitor to a first voltage according to the first control signal; the driving control unit is also used to control the first current source to be disconnected when the first capacitor is charged to the first voltage.
  • the first switch is turned on, so that the first capacitor is discharged.
  • the pulse width timing subunit includes a second current source, a third current source and a second capacitor, the input end of the second current source is connected to electricity, the output end of the second current source is connected to one end of the second capacitor, the input end of the third current source and the driving control unit, and the output end of the third current source and the other end of the second capacitor are grounded;
  • the second current source is used to be turned on according to the first control signal to charge the second capacitor, and to be turned off according to the second control signal to stop charging the second capacitor;
  • the drive control unit is also used to control the third current source to be turned on to discharge the second capacitor when the delay timing subunit outputs the first trigger signal, and to control the third current source to be turned off after the second capacitor is discharged to the second voltage.
  • the duration of the first time is related to the charging current of the first current source.
  • the charging current of the second current source is the same as the discharging current of the third current source.
  • the duration of the first time is not less than the duration of the second time.
  • the power factor correction module includes an inductor, a diode and a power switch tube, one end of the inductor is connected to the input end, the other end of the inductor is connected to the first end of the power switch tube and the positive electrode of the diode, the negative electrode of the diode is connected to the output end, the second end of the power switch tube is grounded, and the third end of the power switch tube is connected to the driving module.
  • the embodiment of the present application provides a display device, the display device includes a power supply circuit, the power supply circuit includes a multi-channel staggered phase power factor correction circuit, the multi-channel staggered phase power factor correction circuit includes at least two power factor correction modules connected in parallel, each power factor correction module is connected to a corresponding driving module, and the driving modules are connected in series step by step;
  • the first-stage driving module is used to output a driving signal to the corresponding power factor correction module;
  • the next-stage driving module is used to delay the driving signal output by the previous-stage driving module and output it to the corresponding power factor correction module;
  • the power factor correction module is used to perform power factor correction on the input power supply according to the corresponding driving signal.
  • the present application provides a multi-channel staggered-phase power factor correction circuit, a power supply circuit and a display device, wherein a power factor correction module in the multi-channel staggered-phase power factor correction circuit corresponds to a driving module to form a power factor correction channel, that is, each power factor correction module corresponds to a driving module, and the driving module only needs to provide a driving signal for a power factor correction module connected thereto, thereby normalizing the driving module, and does not require a driving module to simultaneously drive two or more power factor correction modules to work in staggered rows, thereby simplifying the structure of the driving module to achieve the effect of reducing costs.
  • the latter driving module directly drives the corresponding power factor correction module after delay processing according to the driving signal output by the former driving module, so that each power factor correction path works in staggered phases, which can also effectively reduce the ripple current of each power factor correction path and the electromagnetic radiation interference between each power factor correction path.
  • FIG1 is a schematic diagram of the structure of a multi-path out-of-phase power factor correction circuit provided in an embodiment of the present application.
  • FIG2 is a schematic diagram of the structure of a driving module in a multi-path out-of-phase power factor correction circuit provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of the structure of a delay unit in a multi-path out-of-phase power factor correction circuit provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of the structure of a delay subunit in a multi-path out-of-phase power factor correction circuit provided in an embodiment of the present application.
  • FIG5 is a timing diagram of input drive signals and output drive signals in a multi-path out-of-phase power factor correction circuit provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of the structure of a pulse width subunit in a multi-path out-of-phase power factor correction circuit provided in an embodiment of the present application.
  • FIG. 7 is a circuit structure diagram of a power factor correction module in a multi-path out-of-phase power factor correction circuit provided in an embodiment of the present application.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated.
  • the features specified as “first” and “second” may explicitly or implicitly include one or more features.
  • “multiple” means two or more, unless otherwise clearly and specifically defined.
  • This embodiment provides a multi-path out-of-phase power factor correction circuit, which includes at least two power factor correction modules 11 connected in parallel, each power factor correction module 11 is correspondingly connected to a drive module 12, and each drive module 12 is connected in series step by step.
  • the first-stage driving module 12 is used to output a driving signal to the corresponding power factor correction module 11; the next-stage driving module 12 is used to delay the driving signal output by the previous-stage driving module 12 and output it to the corresponding power factor correction module 11; the power factor correction module 11 is used to perform power factor correction on the input power supply according to the corresponding driving signal.
  • a driving module 12 is correspondingly arranged for one power factor correction module 11 to form a power factor correction channel, that is, each power factor correction module 11 corresponds to one driving module 12, and the driving module 12 only needs to provide a driving signal for one power factor correction module 11 connected thereto, thereby normalizing the driving module 12, and it is not necessary for one driving module 12 to simultaneously drive two or more power factor correction modules 11 to work in staggered rows, thereby simplifying the driving
  • the latter driving module 12 directly drives the corresponding power factor correction module 11 after delay processing according to the driving signal output by the former driving module 12, so that each power factor correction path works in a staggered phase, which can also effectively reduce the ripple current of each power factor correction path and the electromagnetic radiation interference between each power factor correction path.
  • each driving module 12 in the present application corresponds to driving one power factor correction module 11, and each driving module 12 is connected in series to facilitate the duplication and utilization of the driving signal.
  • the setting of the driving module 12 and the power factor correction module 11 in the present application is more conducive to forming a multi-path out-of-phase power factor correction path, and as the power factor correction paths increase, it is more conducive to dispersing the heat of a single power factor correction path, thereby reducing the temperature and heat dissipation requirements of the power factor correction module 11.
  • the first-stage driving module 12 is used to output a driving signal to the corresponding power factor correction module 11.
  • the first-stage driving module 12 does not need to perform delay processing on the driving signal.
  • the first-stage driving module 12 can be used as the main driving module 12, and the power factor correction module 11 connected to the main driving module 12 can be used as the main power factor correction module 11; the other subsequent-stage driving modules 12 can be used as slave driving modules 12, and the power factor correction modules 11 connected to the slave driving modules 12 can be used as slave power factor correction modules 11.
  • the first slave driving module 12 drives the first slave power factor correction module 11 after delaying the driving signal output by the main driving module 12, and outputs the delayed driving signal to the second slave driving module 12; the second slave driving module 12 drives the second slave power factor correction module after delaying the driving signal output by the first slave driving module 12 again, and outputs the delayed driving signal to the third driving module 12, and so on, until the last slave driving module 12 receives the driving signal output by the previous slave driving module 12 and drives the last slave power factor correction module 11 to work after delaying, thereby forming a multi-path out-of-phase power factor correction path, thereby reducing the peak current of a single power factor correction path. This reduces electromagnetic radiation interference between power factor correction paths.
  • the latter driving module 12 includes a driving control unit 121 and a delay unit 122, and the driving control unit 121 is connected to the delay unit 122. It is understandable that the master driving module 12 may not need to process the driving signal, and each slave driving module 12 needs to delay the input driving signal, and each slave driving module 12 includes a driving control unit 121 and a delay unit 122.
  • the drive control unit 121 is used to output a control signal to the delay unit 122 according to the drive signal output by the previous-stage drive module 12; the delay unit 122 is used to output a trigger signal to the drive control unit 121 after timing the first time according to the control signal; the drive control unit 121 is also used to output the drive signal output by the previous-stage drive module 12 to the corresponding power factor correction module 11 according to the trigger signal, that is, after the drive control unit 121 receives the drive signal output by the previous-stage drive module 12, it will control the delay unit 122 to start timing, and when the delay unit 122 times the first time, it will output a trigger signal to the drive control unit 121, and the drive control unit 121 outputs the received drive signal to the next-stage drive module 12 according to the feedback trigger signal, and at the same time drives the corresponding power factor correction module 11 according to the drive signal to perform power factor correction on the input power supply, thereby facilitating the staggered operation of multiple power factor correction paths.
  • the delay unit 122 includes a delay timing subunit 1221 and a pulse width timing subunit 1222.
  • the delay timing subunit 1221 and the pulse width timing subunit 1222 are both connected to the driving control unit 121.
  • the driving control unit 121 is used to output a first control signal to the delay timing subunit 1221 and the pulse width timing subunit 1222 when the rising edge of the driving signal output by the previous stage driving module 12 is detected, and output a second control signal to the pulse width timing subunit 1222 when the first falling edge after the rising edge is detected.
  • the delay timing subunit 1221 is used to start timing according to the first control signal, and output a first trigger signal after timing the first time; the pulse width timing subunit 1222 is used to start timing according to the first control signal, and output a second timing time according to the second control signal, and output a second trigger signal after restarting the timing of the second time when the delay timing subunit 1221 outputs the first trigger signal.
  • the duration of the first time is greater than the duration of the second time.
  • the driving control unit 121 is also used to output a high-level driving signal according to the first trigger signal. signal, and outputs a low-level driving signal according to the second trigger signal.
  • the rising edge of the input driving signal is used as a control signal for the delay timing subunit 1221 and the pulse width timing subunit 1222 to start working; when the rising edge of the input driving signal is detected, the delay timing subunit 1221 and the pulse width timing subunit 1222 are controlled to start timing; after the delay timing subunit 1221 has timed for a first time, it outputs a first trigger signal to the driving control unit 121, and at this time, the driving control unit 121 starts to output a high-level signal of the driving signal to the next-level driving module 12 according to the first trigger signal.
  • the pulse width timing subunit 1222 In order to completely copy the input drive signal, the pulse width timing subunit 1222 is required to time the pulse width of the drive signal. Therefore, when the first falling edge after the rising edge is detected, the pulse width timing subunit 1222 is controlled to output the second time. At this time, the second time period corresponds to the high level duration of the drive signal, that is, the pulse width of the drive signal; and when the first time period is delayed, the drive signal needs to be output. In order to ensure that the drive signal is copied when the drive signal is output, the first time needs to be not less than the second time.
  • the drive control unit 121 When the first time is delayed, the drive control unit 121 starts to output the high level drive signal according to the first trigger signal; at the same time, when the pulse width timing subunit 1222 restarts to time the second time, it outputs the second trigger signal to the drive control unit 121, so that the drive control unit 121 jumps to output the low level drive signal according to the second trigger signal; when the drive control unit 121 detects the next rising edge, the above process is repeated, thereby completing the copy and delayed output process of the input drive signal.
  • the delay timing subunit 1221 includes a first current source 1201, a first switch 1202 and a first capacitor 1203.
  • the input end of the first current source 1201 is connected to electricity, the output end of the first current source 1201 is connected to one end of the first switch 1202, one end of the first capacitor 1203 and the driving control unit 121, the other end of the first switch 1202 is grounded, and the other end of the first capacitor 1203 is grounded.
  • the voltage of the first capacitor 1203 is a first voltage signal.
  • the first current source 1201 is used to charge the first capacitor 1203 to the first voltage V1 according to the first control signal.
  • the driving control unit 121 is also used to control the first current source 1201 to be disconnected and the first switch 1202 to be turned on when the first capacitor 1203 is charged to the first voltage V1, so that the first capacitor 1203 discharges. That is, in this embodiment, the first capacitor 1203 is charged and discharged by the first current source 1201 to achieve delay timing.
  • the time from the start of charging of the first capacitor 1203 to charging to the first voltage is recorded as the first time t1.
  • the driving control unit 121 detects that the first capacitor 1203 is charged to the first voltage V1, it controls the first current source 1201 to be disconnected and the first switch 1202 to be turned on, so that the first capacitor 1203 is discharged. At this time, the voltage signal of the first capacitor 1203 will produce a falling edge.
  • the driving control unit 121 starts to output a high-level driving signal; accordingly, in this embodiment, the first voltage V1 can be used as the first trigger signal of the driving control unit 121, or the falling edge of the voltage signal of the first capacitor 1203 can be used as the first trigger signal of the driving control unit 121.
  • the duration of the first time t1 depends on the charging speed of the first capacitor 1203, that is, the duration of the first time t1 is related to the charging current of the first current source 1201.
  • the driving control unit 121 can control the duration of the first time t1 by controlling the charging current of the first current source 1201, thereby realizing flexible control of the delay duration.
  • the pulse width timing subunit 1222 includes a second current source 1204, a third current source 1205 and a second capacitor 1206.
  • the input end of the second current source 1204 is connected to electricity
  • the output end of the second current source 1204 is connected to one end of the second capacitor 1206, the input end of the third current source 1205 and the driving control unit 121, and the output end of the third current source 1205 and the other end of the second capacitor 1206 are grounded.
  • the voltage of the second capacitor 1206 is a second voltage signal
  • the second current source 1204 is used to charge the second capacitor 1206 according to the first control signal, and to stop charging the second capacitor 1206 according to the second control signal; that is, the driving control unit 121 controls the second current source 1204 to charge the second capacitor 1206 when detecting the rising edge of the input driving signal, and controls the second current source 1204 to stop charging the second capacitor 1206 when detecting the first falling edge after the rising edge.
  • the time from the start of charging to the stop of charging of the second capacitor 1206 in this embodiment is the second time t2, that is, the high level duration of the driving signal corresponding to the second time t2. Therefore, in this embodiment, the input driving signal pulse can be realized by charging the second capacitor 1206. Wide timing function.
  • the driving control unit 121 is also used to control the third current source 1205 to be turned on to discharge the second capacitor 1206 when the delay timing sub-unit 1221 outputs the first trigger signal, and to control the third current source 1205 to be disconnected after the second capacitor 1206 is discharged to the second voltage V2, so that the second capacitor 1206 stops discharging; that is, the driving control unit 121 is also used to monitor the voltage signal of the second capacitor 1206, and when the second capacitor 1206 is discharged to the second voltage V2, the third current source 1205 is controlled to be disconnected, so that the second capacitor 1206 stops discharging, thereby in this embodiment, the discharge of the second capacitor 1206 is controlled to achieve pulse width timing of the output driving signal; accordingly, the second voltage V2 in this embodiment can be used as the second trigger signal of the driving control unit 121.
  • the second voltage V2 is the voltage when the second capacitor 1206 starts to charge; the voltage of the second capacitor 1206 after charging for the second time t2 is recorded as the third voltage V3, then in this embodiment, the driving control unit 121 controls the second capacitor 1206 to charge from the second voltage V2 to the third voltage V3 in the charging stage, and discharges from the third voltage V3 to the second voltage V2 in the discharging stage, thereby making the time of the charging stage consistent with the time of the discharging stage, so as to ensure that the pulse width of the driving signal output by the driving control unit 121 is consistent with the pulse width of the driving signal input.
  • the charging current of the second current source 1204 is the same as the discharging current of the third current source 1205.
  • the charging current of the second current source 1204 can control the charging speed of the second capacitor 1206; similarly, the discharging current of the third current source 1205 can control the discharging speed of the second capacitor 1206.
  • the charging current of the second current source 1204 is equal to the discharging current of the third current source 1205, it can ensure that the discharging speed and charging speed of the second capacitor 1206 are consistent, so that the time for the second capacitor 1206 to discharge from the third voltage to the second voltage is consistent with the time for the second capacitor 1206 to charge from the second voltage to the third voltage, thereby ensuring that the input drive signal pulse width is consistent with the output drive signal pulse width, and realizing the replication of the input drive signal.
  • each power factor correction module 11 includes an inductor L1, a diode D1, and a power switch tube Q1.
  • One end of the inductor L1 is connected to the input terminal A, the other end of the inductor L1 is connected to the first end of the power switch tube Q1 and the positive electrode of the diode D1, the negative electrode of the diode D1 is connected to the output terminal B, the second end of the power switch tube Q1 is grounded, and the power switch tube Q1 is grounded.
  • the third end is connected to the driving module 12; wherein the power switch tube Q1 is a MOS tube, the first end of the power switch tube Q1 is the drain of the MOS tube, the second end of the power switch tube Q1 is the source of the MOS tube, and the third end of the power switch tube Q1 is the gate of the MOS tube.
  • the gate of the power switch tube Q1 receives the driving signal output by the corresponding driving module 12, and the driving signal controls the conduction or disconnection of the power switch tube Q1 to realize the power factor correction function of the input power supply. It should be noted that the power factor correction of the power factor correction module 11 in this embodiment is a prior art and will not be repeated here.
  • the multi-channel staggered phase power factor correction circuit further includes a rectifier bridge 13, wherein the first pin of the rectifier bridge 13 is connected to the L line of the AC power supply, the second pin of the rectifier bridge 13 is connected to the power factor correction module 11, the third pin of the rectifier bridge 13 is connected to the N line of the AC power supply, and the fourth pin of the rectifier bridge 13 is grounded.
  • the rectifier bridge 13 in this embodiment is used to rectify the AC power supply and output direct current to each power factor correction module 11 as the input power of the power factor correction module 11.
  • one power factor correction module 11 corresponds to one driving module 12 to form a power factor correction path.
  • Each power factor correction module 11 is driven to work independently.
  • the corresponding power factor correction path can be cut off directly by controlling the power supply of the driving module 12, thereby reducing the standby power consumption.
  • An embodiment of the present application also provides a power supply circuit, which includes the above-mentioned multi-path out-of-phase power factor correction circuit. Since the power factor correction circuit is described in detail above, it will not be repeated here.
  • a display device is also provided in an embodiment of the present application, wherein the display device can be a television, and the display device includes the above-mentioned power supply circuit; the power supply circuit is provided with the above-mentioned multi-path phase-shifted power factor correction circuit. Since the power factor correction circuit is described in detail above, it will not be repeated here.

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Abstract

本申请公开了一种多路错相功率因数校正电路、电源电路和显示设备，其中，多路错相功率因数校正电路包括至少两个并联连接的功率因数校正模块，每个功率因数校正模块对应连接一个驱动模块，且各个驱动模块之间逐级串联连接；第一级驱动模块用于输出驱动信号至对应的功率因数校正模块；后一级驱动模块用于将前一级驱动模块输出的驱动信号进行延时处理后输出至对应的功率因数校正模块；功率因数校正模块用于根据对应的驱动信号将输入电源进行功率因数校正。

Description

一种多路错相功率因数校正电路、电源电路和显示设备
本申请要求于2023年06月28日提交中国专利局、申请号为202310778045.0、申请名称为“一种多路错相功率因数校正电路、电源电路和显示设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及功率因数校正技术领域，具体涉及一种多路错相功率因数校正电路、电源电路和显示设备。
背景技术
为了提高功率因数、降低输入电流谐波含量，在电力电子设备中大多采用PFC(功率因数校正)电路进行调节。
目前的功率因数校正电路中通过单个驱动芯片输出两路驱动信号驱动两个功率开关管交替工作，以形成两路功率因数校正通道。
技术问题
由单个驱动芯片形成两路交错的驱动信号，对单个驱动芯片的电路结构要求复杂，成本高。
技术解决方案
本申请的目的在于提供一种多路错相功率因数校正电路、电源电路和显示设备，能够降低对单个驱动部分的结构要求，以降低成本。
本申请提供的多路错相功率因数校正电路包括至少两个并联连接的功率因数校正模块，每个功率因数校正模块对应连接一个驱动模块，且各个驱动模块之间逐级串联连接；
其中，第一级驱动模块用于输出驱动信号至对应的功率因数校正模块；后一级驱动模块用于将前一级驱动模块输出的驱动信号进行延时处理后输 出至对应的功率因数校正模块；功率因数校正模块用于根据对应的驱动信号将输入电源进行功率因数校正。
在一些实施例中的多路错相功率因数校正电路，后一级驱动模块包括驱动控制单元和延时单元，驱动控制单元与延时单元连接；
驱动控制单元用于根据前一级驱动模块输出的驱动信号输出控制信号至延时单元；延时单元用于根据控制信号计时第一时间后输出触发信号至驱动控制单元；驱动控制单元还用于根据触发信号将前一级驱动模块输出的驱动信号输出至对应的功率因数校正模块。
在一些实施例中的多路错相功率因数校正电路，延时单元包括延时计时子单元和脉宽计时子单元，延时计时子单元和脉宽计时子单元均与驱动控制单元连接；
驱动控制单元用于在检测到前一级驱动模块输出的驱动信号的上升沿时输出第一控制信号，并在检测到上升沿之后的第一个下降沿时输出第二控制信号；
延时计时子单元用于根据第一控制信号开始计时，并在计时第一时间后输出第一触发信号；
脉宽计时子单元用于根据第一控制信号开始计时，并根据第二控制信号输出计时的第二时间，且在延时计时子单元输出第一触发信号时重新开始计时第二时间后输出第二触发信号；
驱动控制单元还用于根据第一触发信号输出高电平的驱动信号，并根据第二触发信号输出低电平的驱动信号。
在一些实施例中的多路错相功率因数校正电路，延时计时子单元包括第一电流源、第一开关和第一电容，第一电流源的输入端接电，第一电流源的输出端与第一开关的一端、第一电容的一端和驱动控制单元连接，第一开关的另一端接地，第一电容的另一端接地；
第一电流源用于根据第一控制信号导通为第一电容充电至第一电压；驱动控制单元还用于在第一电容充电至第一电压时控制第一电流源断开且 第一开关导通，使得第一电容放电。
在一些实施例中的多路错相功率因数校正电路，脉宽计时子单元包括第二电流源、第三电流源和第二电容，第二电流源的输入端接电，第二电流源的输出端与第二电容的一端、第三电流源的输入端和驱动控制单元连接，第三电流源的输出端和第二电容的另一端接地；
第二电流源用于根据第一控制信号导通为第二电容充电，并根据第二控制信号断开停止为第二电容充电；驱动控制单元还用于在延时计时子单元输出第一触发信号时，控制第三电流源导通为第二电容放电，并在第二电容放电至第二电压后控制第三电流源断开。
在一些实施例中的多路错相功率因数校正电路，第一时间的时长与第一电流源的充电电流有关。
在一些实施例中的多路错相功率因数校正电路，第二电流源的充电电流与第三电流源的放电电流相同。
在一些实施例中的多路错相功率因数校正电路，第一时间的时长不小于第二时间的时长。
在一些实施例中的多路错相功率因数校正电路，功率因数校正模块包括电感、二极管和功率开关管，电感的一端与输入端连接，电感的另一端与功率开关管的第一端和二极管的正极连接，二极管的负极与输出端连接，功率开关管的第二端接地，功率开关管的第三端与驱动模块连接。
在一些实施例中的多路错相功率因数校正电路，还包括整流桥，整流桥的第1脚与交流电源的L线连接，整流桥的第2脚与功率因数校正模块连接，整流桥的第3脚与交流电源的N线连接，整流桥的第4脚接地。
本申请实施例还提供了一种电源电路，该电源电路包括上述的多路错相功率因数校正电路；多路错相功率因数校正电路包括至少两个并联连接的功率因数校正模块，每个功率因数校正模块对应连接一个驱动模块，且各个驱动模块之间逐级串联连接；
其中，第一级驱动模块用于输出驱动信号至对应的功率因数校正模块； 后一级驱动模块用于将前一级驱动模块输出的驱动信号进行延时处理后输出至对应的功率因数校正模块；功率因数校正模块用于根据对应的驱动信号将输入电源进行功率因数校正。
在一些实施例中的电源电路，后一级驱动模块包括驱动控制单元和延时单元，驱动控制单元与延时单元连接；
驱动控制单元用于根据前一级驱动模块输出的驱动信号输出控制信号至延时单元；延时单元用于根据控制信号计时第一时间后输出触发信号至驱动控制单元；驱动控制单元还用于根据触发信号将前一级驱动模块输出的驱动信号输出至对应的功率因数校正模块。
在一些实施例中的电源电路，延时单元包括延时计时子单元和脉宽计时子单元，延时计时子单元和脉宽计时子单元均与驱动控制单元连接；
驱动控制单元用于在检测到前一级驱动模块输出的驱动信号的上升沿时输出第一控制信号，并在检测到上升沿之后的第一个下降沿时输出第二控制信号；
延时计时子单元用于根据第一控制信号开始计时，并在计时第一时间后输出第一触发信号；
脉宽计时子单元用于根据第一控制信号开始计时，并根据第二控制信号输出计时的第二时间，且在延时计时子单元输出第一触发信号时重新开始计时第二时间后输出第二触发信号；
驱动控制单元还用于根据第一触发信号输出高电平的驱动信号，并根据第二触发信号输出低电平的驱动信号。
在一些实施例中的电源电路，延时计时子单元包括第一电流源、第一开关和第一电容，第一电流源的输入端接电，第一电流源的输出端与第一开关的一端、第一电容的一端和驱动控制单元连接，第一开关的另一端接地，第一电容的另一端接地；
第一电流源用于根据第一控制信号导通为第一电容充电至第一电压；驱动控制单元还用于在第一电容充电至第一电压时控制第一电流源断开且 第一开关导通，使得第一电容放电。
在一些实施例中的电源电路，脉宽计时子单元包括第二电流源、第三电流源和第二电容，第二电流源的输入端接电，第二电流源的输出端与第二电容的一端、第三电流源的输入端和驱动控制单元连接，第三电流源的输出端和第二电容的另一端接地；
第二电流源用于根据第一控制信号导通为第二电容充电，并根据第二控制信号断开停止为第二电容充电；驱动控制单元还用于在延时计时子单元输出第一触发信号时，控制第三电流源导通为第二电容放电，并在第二电容放电至第二电压后控制第三电流源断开。
在一些实施例中的电源电路，第一时间的时长与第一电流源的充电电流有关。
在一些实施例中的电源电路，第二电流源的充电电流与第三电流源的放电电流相同。
在一些实施例中的电源电路，第一时间的时长不小于第二时间的时长。
在一些实施例中的电源电路，功率因数校正模块包括电感、二极管和功率开关管，电感的一端与输入端连接，电感的另一端与功率开关管的第一端和二极管的正极连接，二极管的负极与输出端连接，功率开关管的第二端接地，功率开关管的第三端与驱动模块连接。
本申请实施例一种显示设备，该显示设备包括电源电路，电源电路包括多路错相功率因数校正电路，多路错相功率因数校正电路包括至少两个并联连接的功率因数校正模块，每个功率因数校正模块对应连接一个驱动模块，且各个驱动模块之间逐级串联连接；
其中，第一级驱动模块用于输出驱动信号至对应的功率因数校正模块；后一级驱动模块用于将前一级驱动模块输出的驱动信号进行延时处理后输出至对应的功率因数校正模块；功率因数校正模块用于根据对应的驱动信号将输入电源进行功率因数校正。
有益效果
本申请提供的多路错相功率因数校正电路、电源电路和显示设备，其中，多路错相功率因数校正电路中一个功率因数校正模块对应设置一个驱动模块形成一路功率因数校正通道，即每个功率因数校正模块对应一个驱动模块，驱动模块仅需要为与之连接的一个功率因数校正模块提供驱动信号，由此可将驱动模块进行常规化，并不需要一个驱动模块同时驱动两个或两个以上数目的功率因数校正模块错行工作，进而简化驱动模块的结构，以达到降低成本的效果。而本申请中的至少两个驱动模块形成串联结构之后，后一个驱动模块直接根据前一个驱动模块输出的驱动信号进行延时处理后驱动相应的功率因数校正模块，使得各路功率因数校正通路错相工作，同样能够有效降低各个功率因数校正通路的纹波电流以及各路功率因数校正通路之间的电磁辐射干扰。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的多路错相功率因数校正电路的结构示意图。
图2为本申请实施例提供的多路错相功率因数校正电路中驱动模块的结构示意图。
图3为本申请实施例提供的多路错相功率因数校正电路中延时单元的结构示意图。
图4为本申请实施例提供的多路错相功率因数校正电路中延时子单元的结构示意图。
图5为本申请实施例提供的多路错相功率因数校正电路中输入的驱动信号和输出的驱动信号的时序图。
图6为本申请实施例提供的多路错相功率因数校正电路中脉宽子单元的结构示意图。
图7为本申请实施例提供的多路错相功率因数校正电路中功率因数校正模块的电路结构图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量，由此限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个特征，在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
请参阅图1，本实施例提供了一种多路错相功率因数校正电路，该功率因数校正电路包括至少两个并联连接的功率因数校正模块11连接，每个功率因数校正模块11对应连接一个驱动模块12，且各个驱动模块12之间逐级串联连接。
其中，第一级驱动模块12用于输出驱动信号至对应的功率因数校正模块11；后一级驱动模块12用于将前一级驱动模块12输出的驱动信号进行延时处理后输出至对应的功率因数校正模块11；功率因数校正模块11用于根据对应的驱动信号将输入电源进行功率因数校正。
本申请中针对一个功率因数校正模块11对应设置一个驱动模块12形成一路功率因数校正通道，即每个功率因数校正模块11对应一个驱动模块12，驱动模块12仅需要为与之连接的一个功率因数校正模块11提供驱动信号，由此可将驱动模块12进行常规化，并不需要一个驱动模块12同时驱动两个或两个以上数目的功率因数校正模块11错行工作，进而简化驱动 模块12的结构，以达到降低成本的效果。而本申请中的至少两个驱动模块12形成串联结构之后，后一个驱动模块12直接根据前一个驱动模块12输出的驱动信号进行延时处理后驱动相应的功率因数校正模块11，使得各路功率因数校正通路错相工作，同样能够有效降低各个功率因数校正通路的纹波电流以及各路功率因数校正通路之间的电磁辐射干扰。
其中，并联设置的功率因数校正模块11越多，与对应的驱动模块12形成的功率因数校正通路越多，各个功率因数校正通路之间的电磁辐射干扰越低，各个功率因数校正通路的纹波电流越小。与此同时，本申请中的每个驱动模块12对应驱动一个功率因数校正模块11，各个驱动模块12串联连接以便于形成驱动信号的复制利用，在设置两个以上的功率因数校正通路时，并不需要考虑会设置驱动模块12的结构；反之，本申请中驱动模块12和功率因数校正模块11的设置更加有利于形成多路错相的功率因数校正通路，而随着功率因数校正通路的增多，更加有利于分散单路功率因数校正通路的热量，进而降低了功率因数校正模块11对温度和散热的要求。
其中，本申请中第一级驱动模块12用于输出驱动信号至对应的功率因数校正模块11，第一级驱动模块12可以不需要对驱动信号进行延时处理，可以将第一级驱动模块12作为主驱动模块12，与主驱动模块12连接的功率因数校正模块11作为主功率因数校正模块11；其他的后一级驱动模块12作为从驱动模块12，与从驱动模块12连接的功率因数校正模块11作为从功率因数校正模块11。第一个从驱动模块12将主驱动模块12输出的驱动信号进行延时处理后驱动第一个从功率因数校正模块11，并将延时后的驱动信号输出至第二个从驱动模块12；第二从驱动模块12则将第一个从驱动模块12输出的驱动信号再次进行延时处理后驱动第二个从功率因数模块，并将再次延时处理后的驱动信号输出至第三个驱动模块12，依次类推，直到最后一个从驱动模块12接收到上一个从驱动模块12输出的驱动信号进行延时处理后驱动最后从功率因数校正模块11工作，由此形成多路错相的功率因数校正通路，以此降低单路功率因数校正通路的峰值电流， 进而降低功率因数校正通路之间的电磁辐射干扰。
请参阅图2，在一些实施例中，后一级驱动模块12包括驱动控制单元121和延时单元122，驱动控制单元121与延时单元122连接。可以理解的是，主驱动模块12可以不需要对驱动信号进行处理，每个从驱动模块12需要对输入的驱动信号进行延时处理，每个从驱动模块12均包括驱动控制单元121和延时单元122。
其中，驱动控制单元121用于根据前一级驱动模块12输出的驱动信号输出控制信号至延时单元122；延时单元122用于根据控制信号计时第一时间后输出触发信号至驱动控制单元121；驱动控制单元121还用于根据触发信号将前一级驱动模块12输出的驱动信号输出至对应的功率因数校正模块11，即驱动控制单元121接收到前一级驱动模块12输出的驱动信号后，会控制延时单元122开始计时，当延时单元122计时第一时间后会输出触发信号至驱动控制单元121，驱动控制单元121根据该反馈回来的触发信号将接收的驱动信号输出至后一级驱动模块12，同时根据该驱动信号驱动相应的功率因数校正模块11对输入电源进行功率因数校正，由此以便于实现多路功率因数校正通路的错相工作。
请参阅图3，在一些实施例中，延时单元122包括延时计时子单元1221和脉宽计时子单元1222，延时计时子单元1221和脉宽计时子单元1222均与驱动控制单元121连接；驱动控制单元121用于在检测到前一级驱动模块12输出的驱动信号的上升沿时输出第一控制信号至延时计时子单元1221和脉宽计时子单元1222，并在检测到上升沿之后的第一个下降沿时输出第二控制信号至脉宽计时子单元1222。延时计时子单元1221用于根据第一控制信号开始计时，并在计时第一时间后输出第一触发信号；脉宽计时子单元1222用于根据第一控制信号开始计时，并根据第二控制信号输出计时的第二时间，且在延时计时子单元1221输出第一触发信号时重新开始计时第二时间后输出第二触发信号。其中，第一时间的时长大于第二时间的时长。驱动控制单元121还用于根据第一触发信号输出高电平的驱动信 号，并根据第二触发信号输出低电平的驱动信号。
本申请中的将输入的驱动信号的上升沿作为延时计时子单元1221和脉宽计时子单元1222开始工作的控制信号；当检测到输入的驱动信号的上升沿时，控制延时计时子单元1221和脉宽计时子单元1222开始计时；当延时计时子单元1221计时了第一时间之后就输出第一触发信号至驱动控制单元121，此时驱动控制单元121根据该第一触发信号开始向后一级驱动模块12输出驱动信号的高电平信号。
为了完全复制输入的驱动信号，此时需要脉宽计时子单元1222计时驱动信号的脉宽，因此在检测到上升沿后的第一个下降沿时控制脉宽计时子单元1222输出第二时间，此时第二时间段对应驱动信号的高电平持续时间即驱动信号的脉宽；而在延时第一时间段时需要开始输出该驱动信号，为了确保在输出该驱动信号时完成该驱动信号的复制，那么需要第一时间不小于第二时间。等到延时第一时间时，驱动控制单元121根据第一触发信号开始输出高电平驱动信号；同时，脉宽计时子单元1222重新开始计时第二时间时则输出第二触发信号至驱动控制单元121，使得驱动控制单元121根据第二触发信号跳转输出低电平驱动信号；当驱动控制单元121检测到下一个上升沿时重复以上的过程，进而完成对输入的驱动信号的复制与延时输出过程。
请参阅图4，作为一种实施例，延时计时子单元1221包括第一电流源1201、第一开关1202和第一电容1203，第一电流源1201的输入端接电，第一电流源1201的输出端与第一开关1202的一端、第一电容1203的一端和驱动控制单元121连接，第一开关1202的另一端接地，第一电容1203的另一端接地。
请一并参阅图5，本实施例中，第一电容1203的电压为第一电压信号，第一电流源1201用于根据第一控制信号导通为第一电容1203充电至第一电压V1；驱动控制单元121还用于在第一电容1203充电至第一电压V1时控制第一电流源1201断开且第一开关1202导通，使得第一电容1203放 电；即本实施例中通过第一电流源1201为第一电容1203充放电以实现延时计时。
记第一电容1203从开始充电到充电至第一电压的时长为第一时间t1，驱动控制单元121在监测到第一电容1203充电至第一电压V1时，则控制第一电流源1201断开且第一开关1202导通，使得第一电容1203放电，此时第一电容1203的电压信号会产生一下降沿。而当延时计时子单元1221计时至第一时间时，驱动控制单元121开始输出高电平驱动信号；相应的，本实施例中可以是第一电压V1作为驱动控制单元121的第一触发信号，也可以是第一电容1203的电压信号的下降沿作为驱动控制单元121的第一触发信号。
其中，第一时间t1的时长取决于第一电容1203的充电快慢，即第一时间t1的时长与第一电流源1201的充电电流大小有关，相应的，驱动控制单元121可通过控制第一电流源1201的充电电流大小以控制第一时间t1的时长，由此实现对延时时长的灵活控制。
请参阅图6，作为一种实施例，脉宽计时子单元1222包括第二电流源1204、第三电流源1205和第二电容1206，第二电流源1204的输入端接电，第二电流源1204的输出端与第二电容1206的一端、第三电流源1205的输入端和驱动控制单元121连接，第三电流源1205的输出端和第二电容1206的另一端接地。
请继续参阅图5，本实施例中，第二电容1206的电压为第二电压信号，第二电流源1204用于根据第一控制信号导通为第二电容1206充电，并根据第二控制信号断开停止为第二电容1206充电；即驱动控制单元121在检测到输入的驱动信号的上升沿时控制第二电流源1204为第二电容1206充电，在检测到该上升沿后的第一个下降沿时控制第二电流源1204停止为第二电容1206充电。那么本实施例中的第二电容1206开始充电至停止充电的时长为第二时间t2，也即第二时间t2段对应驱动信号的高电平持续时间，因此，本实施例中通过对第二电容1206的充电可实现对输入的驱动信号脉 宽的计时功能。
进一步地，驱动控制单元121还用于在延时计时子单元1221输出第一触发信号时，控制第三电流源1205导通为第二电容1206放电，并在第二电容1206放电至第二电压V2后控制第三电流源1205断开，使得第二电容1206停止放电；即驱动控制单元121还用于对第二电容1206的电压信号进行监测，当第二电容1206放电至第二电压V2时即控制第三电流源1205断开，使得第二电容1206停止放电，由此本实施例中通过控制第二电容1206的放电以实现对输出的驱动信号的脉宽计时；相应的，本实施例中的第二电压V2可以作为驱动控制单元121的第二触发信号。
其中，第二电压V2为第二电容1206开始充电时的电压；记第二电容1206充电第二时间t2后的电压为第三电压V3，那么本实施例中由驱动控制单元121控制第二电容1206在充电阶段由第二电压V2充电至第三电压V3，在放电阶段则由第三电压V3放电至第二电压V2，由此使得充电阶段的时间与放电阶段的时间一致，以便于确保驱动控制单元121输出的驱动信号脉宽与输入的驱动信号脉宽一致。
作为一种实施例，第二电流源1204的充电电流与第三电流源1205的放电电流相同。第二电流源1204的充电电流可控制第二电容1206的充电快慢；同样，第三电流源1205的放电电流可控制第二电容1206的放电快慢，若第二电流源1204的充电电流与第三电流源1205的放电电流相等，可确保第二电容1206的放电速度和充电速度一致，以便于使得第二电容1206由第三电压放电至第二电压的时间与第二电容1206由第二电压充电至第三电压的时间一致，进而确保输入的驱动信号脉宽与输出的驱动信号脉宽一致，实现对输入的驱动信号的复制。
请参阅图7，在一些实施例中，每个功率因数校正模块11包括电感L1、二极管D1和功率开关管Q1，电感L1的一端与输入端A连接，电感L1的另一端与功率开关管Q1的第一端和二极管D1的正极连接，二极管D1的负极与输出端B连接，功率开关管Q1的第二端接地，功率开关管Q1 的第三端与驱动模块12连接；其中，功率开关管Q1为MOS管，功率开关管Q1的第一端为MOS管的漏极，功率开关管Q1的第二端为MOS管的源极，功率开关管Q1的第三端为MOS管的栅极。本实施例中功率开关管Q1的栅极接收对应驱动模块12输出的驱动信号，由驱动信号控制功率开关管Q1的导通或断开以实现对输入电源的功率因数校正功能。需要说明的是的本实施例中功率因数校正模块11的功率因数校正为现有技术，在此不再赘述。
在一些实施例中，多路错相功率因数校正电路还包括整流桥13，整流桥13的第1脚与交流电源的L线连接，整流桥13的第2脚与功率因数校正模块11连接，整流桥13的第3脚与交流电源的N线连接，整流桥13的第4脚接地。本实施例中的整流桥13用于对交流电源进行整流处理后输出直流电至各个功率因数校正模块11，作为功率因数校正模块11输入电源。
本申请中一个功率因数校正模块11对应一个驱动模块12形成一功率因数校正通路，每个功率因数校正模块11独立驱动工作，当进入待机状态时可直接通过控制驱动模块12的供电电能即可切断相应功率因数校正通路，从而降低待机功耗。
本申请实施例还提供了一种电源电路，该电源电路包括上述的多路错相功率因数校正电路，由于上文对该功率因数校正电路进行了详细的描述，在此不再赘述。
本申请实施例中还提供了一种显示设备，其中，该显示设备可以是电视机，该显示设备包括上述的电源电路；该电源电路中设置有上述的多路错相位功率因数校正电路，由于上文对该功率因数校正电路进行了详细的描述，在此不再赘述。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的多路错相功率因数校正电路进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以 上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种多路错相功率因数校正电路，其中，包括至少两个并联连接的功率因数校正模块，每个所述功率因数校正模块对应连接一个驱动模块，且各个所述驱动模块之间逐级串联连接；
    其中，第一级所述驱动模块用于输出驱动信号至对应的所述功率因数校正模块；后一级所述驱动模块用于将前一级所述驱动模块输出的驱动信号进行延时处理后输出至对应的所述功率因数校正模块；所述功率因数校正模块用于根据对应的驱动信号将输入电源进行功率因数校正。
  2. 根据权利要求1所述的多路错相功率因数校正电路，其中，后一级所述驱动模块包括驱动控制单元和延时单元，所述驱动控制单元与所述延时单元连接；
    所述驱动控制单元用于根据前一级所述驱动模块输出的驱动信号输出控制信号至延时单元；所述延时单元用于根据所述控制信号计时第一时间后输出触发信号至所述驱动控制单元；所述驱动控制单元还用于根据所述触发信号将前一级所述驱动模块输出的驱动信号输出至对应的所述功率因数校正模块。
  3. 根据权利要求2所述的多路错相功率因数校正电路，其中，所述延时单元包括延时计时子单元和脉宽计时子单元，所述延时计时子单元和所述脉宽计时子单元均与所述驱动控制单元连接；
    所述驱动控制单元用于在检测到前一级所述驱动模块输出的驱动信号的上升沿时输出第一控制信号，并在检测到所述上升沿之后的第一个下降沿时输出第二控制信号；
    所述延时计时子单元用于根据所述第一控制信号开始计时，并在计时第一时间后输出第一触发信号；
    所述脉宽计时子单元用于根据所述第一控制信号开始计时，并根据所述第二控制信号输出计时的第二时间，且在所述延时计时子单元输出所述第一触发信号时重新开始计时所述第二时间后输出第二触发信号；
    所述驱动控制单元还用于根据所述第一触发信号输出高电平的所述驱动信号，并根据所述第二触发信号输出低电平的所述驱动信号。
  4. 根据权利要求3所述的多路错相功率因数校正电路，其中，所述延时计时子单元包括第一电流源、第一开关和第一电容，所述第一电流源的输入端接电，所述第一电流源的输出端与所述第一开关的一端、所述第一电容的一端和所述驱动控制单元连接，所述第一开关的另一端接地，所述第一电容的另一端接地；
    所述第一电流源用于根据所述第一控制信号导通为所述第一电容充电至第一电压；所述驱动控制单元还用于在所述第一电容充电至所述第一电压时控制所述第一电流源断开且所述第一开关导通，使得所述第一电容放电。
  5. 根据权利要求3所述的多路错相功率因数校正电路，其中，所述脉宽计时子单元包括第二电流源、第三电流源和第二电容，所述第二电流源的输入端接电，所述第二电流源的输出端与所述第二电容的一端、所述第三电流源的输入端和所述驱动控制单元连接，所述第三电流源的输出端和所述第二电容的另一端接地；
    所述第二电流源用于根据所述第一控制信号导通为所述第二电容充电，并根据所述第二控制信号断开停止为所述第二电容充电；所述驱动控制单元还用于在所述延时计时子单元输出所述第一触发信号时，控制所述第三电流源导通为所述第二电容放电，并在所述第二电容放电至第二电压后控制所述第三电流源断开。
  6. 根据权利要求4所述的多路错相功率因数校正电路，其中，所述第一时间的时长与所述第一电流源的充电电流有关。
  7. 根据权利要求5所述的多路错相功率因数校正电路，其中，所述第二电流源的充电电流与所述第三电流源的放电电流相同。
  8. 根据权利要求5或6所述的多路错相功率因数校正电路，其中，所述第一时间的时长不小于所述第二时间的时长。
  9. 根据权利要求1-7任一项所述的多路错相功率因数校正电路，其中，所述功率因数校正模块包括电感、二极管和功率开关管，所述电感的一端与输入端连接，所述电感的另一端与所述功率开关管的第一端和所述二极管的正极连接，所述二极管的负极与输出端连接，所述功率开关管的第二端接地，所述功率开关管的第三端与所述驱动模块连接。
  10. 根据权利要求9所述的多路错相功率因数校正电路，其中，还包括整流桥，所述整流桥的第1脚与交流电源的L线连接，所述整流桥的第2脚与所述功率因数校正模块连接，所述整流桥的第3脚与所述交流电源的N线连接，所述整流桥的第4脚接地。
  11. 一种电源电路，其中，包括多路错相功率因数校正电路；所述多路错相功率因数校正电路包括至少两个并联连接的功率因数校正模块，每个所述功率因数校正模块对应连接一个驱动模块，且各个所述驱动模块之间逐级串联连接；
    其中，第一级所述驱动模块用于输出驱动信号至对应的所述功率因数校正模块；后一级所述驱动模块用于将前一级所述驱动模块输出的驱动信号进行延时处理后输出至对应的所述功率因数校正模块；所述功率因数校正模块用于根据对应的驱动信号将输入电源进行功率因数校正。
  12. 根据权利要求11所述的电源电路，其中，后一级所述驱动模块包括驱动控制单元和延时单元，所述驱动控制单元与所述延时单元连接；
    所述驱动控制单元用于根据前一级所述驱动模块输出的驱动信号输出控制信号至延时单元；所述延时单元用于根据所述控制信号计时第一时间后输出触发信号至所述驱动控制单元；所述驱动控制单元还用于根据所述触发信号将前一级所述驱动模块输出的驱动信号输出至对应的所述功率因数校正模块。
  13. 根据权利要求12所述的电源电路，其中，所述延时单元包括延时计时子单元和脉宽计时子单元，所述延时计时子单元和所述脉宽计时子单元均与所述驱动控制单元连接；
    所述驱动控制单元用于在检测到前一级所述驱动模块输出的驱动信号的上升沿时输出第一控制信号，并在检测到所述上升沿之后的第一个下降沿时输出第二控制信号；
    所述延时计时子单元用于根据所述第一控制信号开始计时，并在计时第一时间后输出第一触发信号；
    所述脉宽计时子单元用于根据所述第一控制信号开始计时，并根据所述第二控制信号输出计时的第二时间，且在所述延时计时子单元输出所述第一触发信号时重新开始计时所述第二时间后输出第二触发信号；
    所述驱动控制单元还用于根据所述第一触发信号输出高电平的所述驱动信号，并根据所述第二触发信号输出低电平的所述驱动信号。
  14. 根据权利要求13所述的电源电路，其中，所述延时计时子单元包括第一电流源、第一开关和第一电容，所述第一电流源的输入端接电，所述第一电流源的输出端与所述第一开关的一端、所述第一电容的一端和所述驱动控制单元连接，所述第一开关的另一端接地，所述第一电容的另一端接地；
    所述第一电流源用于根据所述第一控制信号导通为所述第一电容充电至第一电压；所述驱动控制单元还用于在所述第一电容充电至所述第一电压时控制所述第一电流源断开且所述第一开关导通，使得所述第一电容放电。
  15. 根据权利要求13所述的电源电路，其中，所述脉宽计时子单元包括第二电流源、第三电流源和第二电容，所述第二电流源的输入端接电，所述第二电流源的输出端与所述第二电容的一端、所述第三电流源的输入端和所述驱动控制单元连接，所述第三电流源的输出端和所述第二电容的另一端接地；
    所述第二电流源用于根据所述第一控制信号导通为所述第二电容充电，并根据所述第二控制信号断开停止为所述第二电容充电；所述驱动控制单元还用于在所述延时计时子单元输出所述第一触发信号时，控制所述第三 电流源导通为所述第二电容放电，并在所述第二电容放电至第二电压后控制所述第三电流源断开。
  16. 根据权利要求14所述的电源电路，其中，所述第一时间的时长与所述第一电流源的充电电流有关。
  17. 根据权利要求15所述的电源电路，其中，所述第二电流源的充电电流与所述第三电流源的放电电流相同。
  18. 根据权利要求15或16所述的电源电路，其中，所述第一时间的时长不小于所述第二时间的时长。
  19. 根据权利要求11-17任一项所述的电源电路，其中，所述功率因数校正模块包括电感、二极管和功率开关管，所述电感的一端与输入端连接，所述电感的另一端与所述功率开关管的第一端和所述二极管的正极连接，所述二极管的负极与输出端连接，所述功率开关管的第二端接地，所述功率开关管的第三端与所述驱动模块连接。
  20. 一种显示设备，其中，包括电源电路，所述电源电路包括多路错相功率因数校正电路，所述多路错相功率因数校正电路包括至少两个并联连接的功率因数校正模块，每个所述功率因数校正模块对应连接一个驱动模块，且各个所述驱动模块之间逐级串联连接；
    其中，第一级所述驱动模块用于输出驱动信号至对应的所述功率因数校正模块；后一级所述驱动模块用于将前一级所述驱动模块输出的驱动信号进行延时处理后输出至对应的所述功率因数校正模块；所述功率因数校正模块用于根据对应的驱动信号将输入电源进行功率因数校正。
PCT/CN2024/085362 2023-06-28 2024-04-01 一种多路错相功率因数校正电路、电源电路和显示设备 Ceased WO2025001392A1 (zh)

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