WO2024255545A1 - 移位寄存器单元及其驱动方法、显示基板、显示装置 - Google Patents

移位寄存器单元及其驱动方法、显示基板、显示装置 Download PDF

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Publication number
WO2024255545A1
WO2024255545A1 PCT/CN2024/094416 CN2024094416W WO2024255545A1 WO 2024255545 A1 WO2024255545 A1 WO 2024255545A1 CN 2024094416 W CN2024094416 W CN 2024094416W WO 2024255545 A1 WO2024255545 A1 WO 2024255545A1
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WIPO (PCT)
Prior art keywords
transistor
electrode
node
signal
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/094416
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English (en)
French (fr)
Other versions
WO2024255545A9 (zh
Inventor
黄耀
王蓉
都蒙蒙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
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Filing date
Publication date
Priority to GB2520746.5A priority Critical patent/GB2644956A/en
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to DE112024002518.8T priority patent/DE112024002518T5/de
Publication of WO2024255545A1 publication Critical patent/WO2024255545A1/zh
Publication of WO2024255545A9 publication Critical patent/WO2024255545A9/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and specifically to a shift register unit and a driving method thereof, a display substrate, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node, and the second node, respectively, and is configured to provide a signal from the signal input terminal or the first power supply terminal to the first node, and provide a signal from the second power supply terminal or the first clock signal terminal to the second node under the control of the signal from the first clock signal terminal and the second clock signal terminal;
  • the pull-down sub-circuit is electrically connected to the first node and the third power supply terminal, respectively, and is configured to provide a signal of the third power supply terminal to the first node;
  • An absolute value of a voltage value of a signal at the third power supply terminal is smaller than an absolute value of a voltage value of a signal at the second power supply terminal.
  • a first electrode of the eleventh transistor is electrically connected to the third power supply terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.
  • a control electrode of the eleventh transistor is electrically connected to the first node.
  • the node control subcircuit includes: a first transistor, a second transistor, a third transistor, a sixth transistor, and a seventh transistor;
  • the control electrode of the first transistor is electrically connected to the first clock signal terminal, and the first electrode of the first transistor is electrically connected to the signal input terminal.
  • the second electrode of the first transistor is electrically connected to the first node;
  • a control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the second node;
  • the control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the fourth node;
  • the control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first node.
  • the output subcircuit includes: a fourth transistor, a fifth transistor, and an eighth transistor;
  • the control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first signal output terminal;
  • the control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first signal output terminal;
  • the control electrode of the eighth transistor is electrically connected to the second power supply terminal, the first electrode of the eighth transistor is connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node.
  • the pull-down sub-circuit includes: an eleventh transistor
  • the eleventh transistor control electrode is electrically connected to the third node.
  • the output subcircuit further includes: at least one of a first capacitor and a second capacitor;
  • the first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power supply terminal;
  • the first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the first signal output terminal.
  • the output subcircuit is also electrically connected to the third clock signal terminal and the second signal output terminal, respectively, and is configured to provide a signal from the second power supply terminal or the third clock signal terminal to the second signal output terminal under the control of the signals of the first node and the second node.
  • the output subcircuit includes: a fourth transistor, a fifth transistor, an eighth transistor, a ninth transistor, and a tenth transistor;
  • the control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first signal output terminal;
  • the control electrode of the eighth transistor is electrically connected to the second power supply terminal, the first electrode of the eighth transistor is connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node;
  • the control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is connected to the third clock signal terminal, and the second electrode of the ninth transistor is electrically connected to the second signal output terminal;
  • the control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the second signal output terminal.
  • the output sub-circuit further includes: a twelfth transistor; the control electrode of the ninth transistor is electrically connected to the first node through the twelfth transistor;
  • the first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power supply terminal;
  • the first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the first signal output terminal;
  • a first electrode plate of the third capacitor is electrically connected to the control electrode of the ninth transistor, and a second electrode plate of the third capacitor is connected to the second signal output terminal;
  • the first plate of the fourth capacitor is electrically connected to the second node, and the second plate of the fourth capacitor is connected to the second power supply terminal.
  • the signal at the third clock signal terminal and the signal at the second clock signal terminal are inverted signals.
  • it further includes: an output control subcircuit
  • the output control subcircuit includes: a fifth capacitor
  • the first electrode of the fifth capacitor is electrically connected to the first power supply terminal, and the second electrode of the fifth capacitor is electrically connected to the first signal output terminal.
  • the signal at the first clock signal terminal and the signal at the second clock signal terminal are not active level signals at the same time.
  • the present disclosure further provides a display substrate, comprising: a substrate, and sub-pixels, gate lines, and a gate driving circuit arranged on the substrate, wherein the substrate is provided with a display area and a non-display area, the gate driving circuit is located in the non-display area, the sub-pixels and the gate lines are located in the display area, and the gate lines are electrically connected to the sub-pixels and the gate driving circuit, respectively;
  • the gate driving circuit comprises: a plurality of cascaded shift register units, wherein the first signal output end of the i-th shift register unit is connected to the signal input end of the i+1-th shift register unit, 1 ⁇ i ⁇ N, N being the total number of shift register units.
  • the first signal output terminal of the shift register unit is electrically connected to the gate line.
  • it further includes: an initial signal line, a first clock signal line, a second clock signal line, a first power line, a second power line, and a third power line disposed on the substrate and located in the non-display area;
  • any one of the initial signal line, the first clock signal line, the second clock signal line, the first power line, the second power line and the third power line extends along a first direction
  • the gate line extends along a second direction
  • the first direction intersects the second direction
  • the initial signal line, the first clock signal line, the second clock signal line and the first power line are sequentially arranged in a direction close to the display area and are located on a side of the shift register unit away from the display area.
  • the shift register unit includes: a plurality of transistors, and the second power line is located on a side of the first power line close to the display area and is located between the plurality of transistors of the shift register unit.
  • the third power line is located on a side of the second power line close to the display area.
  • the orthographic projection on the substrate partially overlaps with the orthographic projection of the shift register unit on the substrate.
  • the shift register unit includes: a first transistor, a second transistor, a third transistor, a sixth transistor, and a seventh transistor;
  • the shift register unit includes: a fourth transistor, a fifth transistor, an eighth transistor, an eleventh transistor, and a twelfth transistor, and the number of the second power supply line is at least one;
  • the second capacitor is located on a side of the third power line close to the display area.
  • the second power line close to the display area is located on a side of any one of the third clock signal line and the fourth clock signal line close to the display area, and the second power line far from the display area is located between the first power line and the third power line.
  • the shift register unit includes: a fourth transistor, a fifth transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor and a fourth capacitor;
  • the first clock signal terminal of the i-th stage shift register unit is electrically connected to one of the first clock signal line and the second clock signal line
  • the second clock signal terminal of the i-th stage shift register unit is electrically connected to the other of the first clock signal line and the second clock signal line
  • the first clock signal terminals of adjacent shift register units are connected to different signal lines, and the second clock signal terminals of adjacent shift register units are connected to different signal lines.
  • the shift register unit includes: a fourth transistor and a fifth transistor;
  • An orthographic projection of the third power line on the substrate partially overlaps with orthographic projections of the fourth transistor and the fifth transistor on the substrate.
  • the active layer of the eighth transistor extends along the second direction
  • any one of the first electrode and the second electrode of the eighth transistor extends along the first direction
  • the gate electrode of the eighth transistor at least partially extends along the first direction.
  • the gate electrode of the eleventh transistor is an integral structure with the gate electrode of the fifth transistor
  • the orthographic projection of the first electrode of the eleventh transistor on the substrate partially overlaps with the orthographic projection of the third power line on the substrate, and is electrically connected to the third power line
  • the second electrode of the eleventh transistor is an integral structure with the first electrode of the eighth transistor and the first electrode of the twelfth transistor.
  • a width of any one of the first power line, the second power line, and the third power line along the second direction is smaller than a width of any one of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line along the second direction.
  • the third clock signal terminal of the i-th stage shift register unit is electrically connected to one of the third clock signal line and the fourth clock signal line
  • the third clock signal terminal of the i+1-th stage shift register unit is electrically connected to the other of the third clock signal line and the fourth clock signal line.
  • a channel width of an active layer of the tenth transistor and the ninth transistor is greater than a channel width of an active layer of the fourth transistor.
  • a channel width of an active layer of the tenth transistor or the ninth transistor is not less than 90 micrometers.
  • a channel width of an active layer of the fourth transistor is no greater than 50 micrometers.
  • a channel width of an active layer of the ninth transistor and the tenth transistor is greater than a channel width of an active layer of the fifth transistor.
  • a channel width of an active layer of the ninth transistor or the tenth transistor is not less than 90 micrometers.
  • a channel width of an active layer of the fifth transistor is no greater than 50 micrometers.
  • the second signal output terminal of the shift register unit is electrically connected to the gate line.
  • the present disclosure further provides a display device, comprising: the above-mentioned display substrate.
  • the present disclosure further provides a driving method of a shift register unit, which is configured to drive the above-mentioned shift register unit, and the method includes:
  • the node control subcircuit provides a signal from the signal input terminal or the first power supply terminal to the first node and provides a signal from the second power supply terminal or the first clock signal terminal to the second node under the control of the signals from the first clock signal terminal and the second clock signal terminal;
  • the pull-down sub-circuit provides a signal of the third power supply terminal to the first node
  • the output subcircuit provides a signal from the first power supply terminal or the second clock signal terminal to the first signal output terminal under the control of the signals from the first node and the second node.
  • the shift register unit further includes: an output control subcircuit
  • the method further comprises: the output subcircuit provides a signal from a second power supply terminal or a third clock signal terminal to a second signal output terminal under the control of the signals from the first node and the second node;
  • the output control subcircuit stores a voltage difference between the signal at the first signal output terminal and the signal at the first power supply terminal.
  • FIG1 is a structural schematic diagram 1 of a shift register unit provided in an embodiment of the present disclosure
  • FIG2 is an equivalent circuit diagram of a pull-down subcircuit
  • FIG3 is an equivalent circuit diagram of another pull-down subcircuit
  • FIG4 is an equivalent circuit diagram of a node control subcircuit
  • FIG5 is an equivalent circuit diagram 1 of the output subcircuit
  • FIG6 is an equivalent circuit diagram of the output subcircuit
  • FIG7 is a second structural diagram of a shift register unit provided in an embodiment of the present disclosure.
  • FIG8 is an equivalent circuit diagram 3 of the output subcircuit
  • FIG9 is an equivalent circuit diagram 4 of the output subcircuit
  • FIG10 is a third structural diagram of a shift register unit provided in an embodiment of the present disclosure.
  • FIG11 is an equivalent circuit diagram of an output control subcircuit
  • FIG12 is an equivalent circuit diagram 1 of a shift register unit
  • FIG13 is a second equivalent circuit diagram of a shift register unit
  • FIG14 is a third equivalent circuit diagram of a shift register unit
  • FIG16 is a fifth equivalent circuit diagram of a shift register unit
  • FIG17 is an equivalent circuit diagram of a shift register unit VI
  • FIG19 is a signal timing simulation diagram of the shift register unit provided in FIG12 and FIG13;
  • FIG20 is a signal timing simulation diagram of the shift register provided by FIGS. 14 to 18 ;
  • FIG21 is a comparison diagram of signals at the first node and the second signal output terminal of different shift register units
  • FIG22 is a schematic structural diagram of a display device
  • FIG23 is a schematic diagram of a planar structure of a display substrate
  • FIG25 is a third schematic plan view of a display substrate
  • FIG26A is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG26B is a working timing diagram of the pixel driving circuit provided in FIG26A;
  • FIG28 is a cascade schematic diagram 1 of a gate drive circuit
  • FIG29 is a second cascade schematic diagram of a gate drive circuit
  • FIG31 is a second structural schematic diagram of a display substrate
  • FIG32 is a schematic diagram of FIG30 after a semiconductor layer pattern is formed
  • FIG33 is a schematic diagram of FIG31 after a semiconductor layer pattern is formed
  • FIG34 is a schematic diagram of a first conductive layer pattern in FIG30 ;
  • FIG35 is a schematic diagram of FIG30 after forming a first conductive layer pattern
  • FIG36 is a schematic diagram of a first conductive layer pattern in FIG31 ;
  • FIG37 is a schematic diagram of FIG31 after forming a first conductive layer pattern
  • FIG38 is a schematic diagram of a second conductive layer pattern in FIG30 ;
  • FIG39 is a schematic diagram of FIG30 after forming a second conductive layer pattern
  • FIG40 is a schematic diagram of a second conductive layer pattern in FIG31 ;
  • FIG41 is a schematic diagram of FIG31 after forming a second conductive layer pattern
  • FIG42 is a schematic diagram of FIG30 after forming a third insulating layer pattern
  • FIG43 is a schematic diagram of FIG31 after forming a third insulating layer pattern
  • FIG44 is a schematic diagram of a third conductive layer pattern in FIG30 ;
  • FIG45 is a schematic diagram of FIG30 after forming a third conductive layer pattern
  • FIG46 is a schematic diagram of a third conductive layer pattern in FIG31 ;
  • FIG47 is a schematic diagram of FIG31 after forming a third conductive layer pattern
  • FIG48 is a schematic diagram of FIG30 after forming a fourth insulating layer pattern
  • FIG49 is a schematic diagram of FIG31 after forming a fourth insulating layer pattern
  • FIG50 is a schematic diagram of a fourth conductive layer pattern in FIGS. 30 and 31 ;
  • FIG51 is a schematic diagram of FIG30 after forming a fourth conductive layer pattern
  • FIG. 52 is a schematic diagram of FIG. 31 after forming a fourth conductive layer pattern.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different.
  • the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • the display substrate includes: a pixel driving circuit, a light-emitting element and a gate driving circuit, wherein the gate driving circuit is configured to provide a gate signal to the transistor in the pixel driving circuit so that the pixel driving circuit can drive the light-emitting element to emit light.
  • the display substrate uses low-temperature polysilicon (LTPS) technology, which has the advantages of high resolution, high response speed, high brightness, and high aperture ratio. Although it is popular in the market, LTPS technology also has some defects, such as high production cost and high power consumption. At this time, the low-temperature polycrystalline oxide (LTPO) technology solution came into being. Compared with LTPS technology, the pixel driving circuit includes low-temperature polysilicon transistors.
  • LTPS low-temperature polysilicon
  • the pixel driving circuit in LTPO technology includes low-temperature polysilicon transistors and metal oxide transistors.
  • the metal oxide transistor has a smaller leakage current, which makes the pixel point respond faster.
  • the display substrate adds an extra layer of oxide, which can reduce the energy consumption required to excite the pixel point, thereby reducing the power consumption when the screen is displayed.
  • the display product using LTPO technology includes a set of driving circuits to control the metal oxide transistors in the display product. As the size, resolution and refresh rate of display substrates increase, the compensation time of pixel driving circuits in one frame is getting shorter and shorter.
  • the driving circuit for controlling metal oxide transistors in the display substrate usually has a voltage at some nodes that is not low enough, so that the voltage of the output signal of the driving circuit for controlling the metal oxide transistor cannot reach the predetermined voltage, that is, the driving ability of the driving circuit for controlling the metal oxide transistor is weak, which leads to the metal oxide transistor being damaged.
  • the conduction degree of the body tube is low, which affects the performance of the pixel driving circuit, thereby reducing the display effect of the display substrate.
  • Fig. 1 is a structural schematic diagram 1 of a shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit provided by an embodiment of the present disclosure may include: a node control subcircuit, an output subcircuit and a pull-down subcircuit.
  • the node control subcircuit is electrically connected to the signal input terminal IN, the first clock signal terminal CK1, the second clock signal terminal CK2, the first power supply terminal V1, the second power supply terminal V2, the first node N1 and the second node N2, respectively, and is configured to provide the signal of the signal input terminal IN or the first power supply terminal V1 to the first node N1 and provide the signal of the second power supply terminal V2 or the first clock signal terminal CK1 to the second node N2 under the control of the signal of the first clock signal terminal CK1 and the second clock signal terminal CK2;
  • the pull-down subcircuit is electrically connected to the first node N1 and the third power supply terminal V3, respectively, and is configured to provide the signal of the third power supply terminal V3 to the first node N1;
  • the output subcircuit is electrically connected to the second clock signal terminal CK2, the first power supply terminal V1, the second power supply terminal V2, the first signal output terminal OUT1, the first node N1 and the second node N2,
  • the first power terminal V1 continuously provides a high level signal
  • the second power terminal V2 and the third power terminal V3 continuously provide a low level signal
  • the absolute value of the voltage value of the signal at the third power supply terminal V3 is smaller than the absolute value of the voltage value of the signal at the second power supply terminal V2.
  • the width of the signal line connected to the second power supply terminal V2 is different from the width of the signal line connected to the third power supply terminal V3.
  • a signal at any one of the first clock signal terminal CK1 and the second clock signal terminal CK2 may be a periodic pulse signal.
  • the signal at the signal output terminal IN is a single pulse signal.
  • the shift register unit includes: a node control subcircuit, an output subcircuit and a pull-down subcircuit, wherein the node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node and the second node, respectively, and is configured to provide the signal of the signal input terminal or the first power supply terminal to the first node, and provide the signal of the second power supply terminal or the first clock signal terminal to the second node under the control of the signal of the first clock signal terminal and the second clock signal terminal; the pull-down subcircuit is electrically connected to the first node and the third power supply terminal, respectively, and is configured to provide the signal of the third power supply terminal to the first node; the output subcircuit is electrically connected to the second clock signal terminal, the first power supply terminal, the first signal output terminal, the first node and the second node, respectively, and is configured to provide the signal of the first power supply terminal or
  • the shift register unit provided in the present disclosure can pull down the signal of the first node to a low-level signal with a lower voltage value by setting a pull-down sub-circuit, so that some transistors in the shift register unit can be fully turned on, and then the voltage of the output signal of the shift register unit can reach a predetermined voltage, thereby improving the driving capability of the shift register unit, and can ensure the conduction capability of the transistors in the pixel driving circuit, thereby improving the performance of the pixel driving circuit and the display effect of the display substrate.
  • Fig. 2 is an equivalent circuit diagram of a pull-down sub-circuit
  • Fig. 3 is an equivalent circuit diagram of another pull-down sub-circuit.
  • the pull-down sub-circuit may include: an eleventh transistor T11.
  • the first electrode of the eleventh transistor T11 is electrically connected to the third power supply terminal V3, and the second electrode of the eleventh transistor T11 is electrically connected to the first node N1.
  • FIG4 is an equivalent circuit diagram of a node control subcircuit.
  • the node control subcircuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6, and a seventh transistor T7.
  • the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1;
  • the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the second node N2;
  • the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the second node N2;
  • the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the first power supply terminal V1, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node;
  • FIG5 is an equivalent circuit diagram of an output subcircuit.
  • the output subcircuit may include: a fourth transistor T4, a fifth transistor T5, and an eighth transistor T8.
  • the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected to the first signal output terminal OUT1;
  • the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the first signal output terminal OUT1;
  • the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3.
  • a control electrode of the eleventh transistor T11 may be electrically connected to the first node N1 .
  • control of the eleventh transistor may be electrically connected to the third node N3 .
  • FIG6 is an equivalent circuit diagram of the output subcircuit.
  • the output subcircuit may include: at least one of a first capacitor C1 and a second capacitor C2.
  • the first plate of the first capacitor C1 is electrically connected to the second node N2, and the second plate of the first capacitor C1 is electrically connected to the first power supply terminal V1; the first plate of the second capacitor C2 is electrically connected to the third node, and the second plate of the second capacitor C2 is electrically connected to the first signal output terminal OUT1.
  • FIG6 is illustrated by taking the output subcircuit also including the first capacitor C1 and the second capacitor C2 as an example.
  • Fig. 7 is a second structural schematic diagram of a shift register unit provided in an embodiment of the present disclosure.
  • the output subcircuit is electrically connected to the second clock signal terminal CK2, the first power supply terminal V1, the first signal output terminal OUT1, the first node N1, the second node N2, the third clock signal terminal CK3, the second power supply terminal V2, and the second signal output terminal OUT2, respectively, and is configured to provide a signal of the first power supply terminal V1 or the second clock signal terminal CK2 to the first signal output terminal OUT1 and provide a signal of the second power supply terminal V2 or the third clock signal terminal CK3 to the second signal output terminal OUT2 under the control of the signal of the first node N1 and the second node N2.
  • the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are single pulse signals, and the signal at the first signal output terminal OUT1 and the signal at the second signal output terminal OUT2 are inverted signals to each other, that is, when the signal at the first signal output terminal OUT1 is a high-level signal, the signal at the second signal output terminal OUT2 is a low-level signal, and when the signal at the first signal output terminal OUT1 is a low-level signal, the signal at the second signal output terminal OUT2 is a high-level signal.
  • the first signal output terminal OUT1 is configured to output a cascade signal, which is a low level signal
  • the second signal output terminal OUT2 is configured to output a gate scan signal.
  • the gate scan signal is a high level signal or a low level signal.
  • FIG8 is an equivalent circuit diagram of the output subcircuit.
  • the output subcircuit may include: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10.
  • the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected to the first signal output terminal OUT1;
  • the control electrode of the fifth transistor T5 is electrically connected to the third node N3, and the first electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CK2, the second electrode of the fifth transistor T5 is electrically connected to the first signal output terminal OUT1;
  • the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3;
  • the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is connected to the third clock signal terminal CK3, and the second electrode of the ninth transistor T9 is electrically connected to the second signal
  • FIG9 is an equivalent circuit diagram of an output subcircuit.
  • the output subcircuit may include: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a twelfth transistor T12, wherein the control electrode of the ninth transistor T9 is electrically connected to the first node N1 through the twelfth transistor T12.
  • the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected to the first signal output terminal OUT1;
  • the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the first signal output terminal OUT1;
  • the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3;
  • the ninth transistor T 9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is connected to the third clock signal terminal CK3, and the second electrode of the ninth transistor T9 is electrically connected to the second signal output terminal OUT2;
  • the twelfth transistor T12 is a continuously turned-on transistor, which can ensure the stability of the signal at the control electrode of the ninth transistor T9, avoid large deviation of the output signal of the shift register unit, and ensure the stability of the output signal of the shift register unit.
  • the output sub-circuit may further include: at least one of a first capacitor C1 , a second capacitor C2 , a third capacitor C3 , and a fourth capacitor C4 .
  • the first plate of the first capacitor C1 is electrically connected to the second node N2, and the second plate of the first capacitor C1 is electrically connected to the first power supply terminal V1; the first plate of the second capacitor C2 is electrically connected to the third node N3, and the second plate of the second capacitor C2 is connected to the first signal output terminal OUT1; the first plate of the third capacitor C3 is electrically connected to the control electrode of the ninth transistor T9, and the second plate of the third capacitor C3 is connected to the second signal output terminal OUT2; the first plate of the fourth capacitor C4 is electrically connected to the second node N2, and the second plate of the fourth capacitor C4 is connected to the second power supply terminal V2.
  • the output subcircuit may include: a second capacitor C2 and a fourth capacitor C4, or may include: a second capacitor C2, or may include: a first capacitor C1 and a third capacitor C3, or may include: a third capacitor C3, or may include: a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4.
  • Figures 8 and 9 are illustrated by taking the output subcircuit including: a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4 as an example.
  • the first capacitor C1 can ensure the stability of the second node N2
  • the second capacitor C2 can ensure the voltage difference between the signal of the third node N3 and the first signal output terminal OUT1
  • the third capacitor can ensure the voltage difference between the signal of the first node N1 and the second signal output terminal OUT2
  • the fourth capacitor C4 can ensure the stability of the signal of the second node N2.
  • FIG10 is a schematic diagram of the structure of the shift register unit provided in the embodiment of the present disclosure.
  • the shift register unit may further include: an output control subcircuit.
  • the output control subcircuit is electrically connected to the first power supply terminal V1 and the first signal output terminal OUT1, respectively, and is configured to store the first signal output terminal
  • the output subcircuit of the shift register unit in FIG10 may be electrically connected to the second clock signal terminal CK2, the first power supply terminal V1, the first node N1, the second node N2, and the first signal output terminal OUT1, or may be electrically connected to the second clock signal terminal CK2, the third clock signal line CK3, the first power supply terminal V1, the second power supply terminal V2, the first node N1, the second node N2, the first signal output terminal OUT1, and the second signal output terminal OUT2.
  • the signal outputted by the first signal output terminal OUT1 is a cascade signal, that is, the signal line connected to the first signal output terminal OUT1 will not flow through the display area where the pixel driving circuit is located, that is, the load of the signal line connected to the first signal output terminal OUT1 is small, and it is easily affected by the parasitic capacitance of some transistors in the output subcircuit, thereby causing the signal of the first signal output terminal OUT1 to fluctuate.
  • the present disclosure can make the signal outputted by the first signal output terminal OUT1 more stable by setting the output control subcircuit, thereby improving the performance of the shift register unit.
  • FIG11 is an equivalent circuit diagram of the output control subcircuit.
  • the output control subcircuit includes: a fifth capacitor C5.
  • the first electrode of the fifth capacitor C5 is electrically connected to the first power supply terminal V1, and the second electrode of the fifth capacitor C5 is electrically connected to the first signal output terminal OUT1.
  • the dotted lines in FIGS. 10 and 11 indicate that they may be connected or may not be connected.
  • FIG. 12 is an equivalent circuit diagram 1 of a shift register unit
  • FIG. 13 is an equivalent circuit diagram 2 of a shift register unit.
  • the shift register unit may further output a control subcircuit, wherein the node control subcircuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6, and a seventh transistor T7, the output subcircuit includes: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, and at least one of a first capacitor C1 and a second capacitor C2, the pull-down subcircuit includes: an eleventh transistor T11, and the output control subcircuit includes: a fifth capacitor C5.
  • FIG. 12 is an equivalent circuit diagram 1 of a shift register unit
  • FIG. 13 is an equivalent circuit diagram 2 of a shift register unit.
  • the shift register unit may further output a control subcircuit, wherein the node control subcircuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6, and a
  • FIG. 12 is illustrated by taking the shift register unit including: a second capacitor C2
  • FIG. 13 is illustrated by taking the shift register unit including: a first capacitor C1 and a second capacitor C2 as an example.
  • FIG. 12 is illustrated by taking the control electrode of the eleventh transistor being electrically connected to the third node N3 as an example
  • FIG. 13 is illustrated by taking the control electrode of the eleventh transistor being electrically connected to the first node N1 as an example.
  • a control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, a first electrode of the first transistor T1 is connected to the signal input terminal IN, and a second electrode of the first transistor T1 is electrically connected to the first node N1;
  • a control electrode of the second transistor T2 is electrically connected to the first node N1, a first electrode of the second transistor T2 is connected to the first clock signal terminal CK1, and a second electrode of the second transistor T2 is electrically connected to the second node N2;
  • a control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, a first electrode of the third transistor T3 is connected to the second power supply terminal V2, and a second electrode of the third transistor T3 is electrically connected to the second node N2;
  • a control electrode of the fourth transistor T4 is electrically connected to the second node N2, a first electrode of the fourth transistor T4 is connected to the first power supply terminal V1, and
  • FIG. 12 The description is made by taking the control electrode of the eleventh transistor T11 being electrically connected to the third node N3 as an example, and FIG. 13 is made by taking the control electrode of the eleventh transistor T11 being electrically connected to the first node N1 as an example.
  • the transistors can be divided into N-type transistors and P-type transistors according to the characteristics of the transistors.
  • the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages).
  • the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).
  • the first to eighth transistors T1 to T8 and the eleventh transistor T11 may all be P-type transistors.
  • FIG. 14 is an equivalent circuit diagram of a shift register unit in FIG. 3
  • FIG. 15 is an equivalent circuit diagram of a shift register unit in FIG. 4.
  • the shift register unit further includes: an output control subcircuit
  • a node control subcircuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6, and a seventh transistor T7
  • an output subcircuit includes: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10, and at least one of a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4,
  • a pull-down subcircuit includes: an eleventh transistor T11
  • an output control subcircuit includes: a fifth capacitor C5.
  • FIG. 14 and FIG. 15 are explained by taking the shift register unit including: a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4 as an example.
  • FIG. 14 is explained by taking the control electrode of the eleventh transistor being electrically connected to the third node N3 as an example
  • FIG. 15 is explained by taking the control electrode of the eleventh transistor being electrically connected to the first node N1 as an example.
  • a control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, a first electrode of the first transistor T1 is connected to the signal input terminal IN, and a second electrode of the first transistor T1 is electrically connected to the first node N1;
  • a control electrode of the second transistor T2 is electrically connected to the first node N1, a first electrode of the second transistor T2 is connected to the first clock signal terminal CK1, and a second electrode of the second transistor T2 is electrically connected to the second node N2;
  • a control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, a first electrode of the third transistor T3 is connected to the second power supply terminal V2, and a second electrode of the third transistor T3 is electrically connected to the second node N2;
  • a control electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal CK1, a first electrode of the third transistor T3 is connected to the second power supply terminal V
  • the first to eleventh transistors T1 to T11 may all be P-type transistors.
  • FIG. 16 is an equivalent circuit diagram 5 of a shift register unit
  • FIG. 17 is an equivalent circuit diagram 6 of a shift register unit
  • FIG. 18 is an equivalent circuit diagram 7 of a shift register unit. As shown in FIG. 16 to FIG.
  • a node control subcircuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6, and a seventh transistor T7
  • an output subcircuit includes: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a twelfth transistor T12, and at least one of a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4,
  • a pull-down subcircuit includes: an eleventh transistor T11
  • an output control subcircuit includes: a fifth capacitor C5.
  • FIG. 17 are described by taking the shift register unit including: a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4 as an example
  • FIG. 18 is described by taking the shift register unit including: a second capacitor C2 and a fourth capacitor C4 as an example.
  • 16 and 18 are described by taking the example that the control electrode of the eleventh transistor T11 is electrically connected to the third node N3, and FIG. 17 is described by taking the example that the control electrode of the eleventh transistor T11 is electrically connected to the first node N1.
  • a control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, a first electrode of the first transistor T1 is connected to the signal input terminal IN, and a second electrode of the first transistor T1 is electrically connected to the first node N1;
  • a control electrode of the second transistor T2 is electrically connected to the first node N1, a first electrode of the second transistor T2 is connected to the first clock signal terminal CK1, and a second electrode of the second transistor T2 is electrically connected to the second node N2;
  • a control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, a first electrode of the third transistor T3 is connected to the second power supply terminal V2, and a second electrode of the third transistor T3 is electrically connected to the second node N2;
  • a control electrode of the fourth transistor T4 is electrically connected to the second node N2, and a first electrode of the fourth transistor T4 is connected to the first power supply terminal V1
  • the first to eleventh transistors T1 to T11 may all be P-type transistors.
  • the signal of the first clock signal terminal CK1 and the signal of the second clock signal terminal CK2 are not valid level signals at the same time.
  • the signal of the first clock signal terminal CK1 is at a valid level signal
  • the signal of the second clock signal terminal CK2 is an invalid level signal
  • the signal of the first clock signal terminal CK1 is an invalid level signal.
  • the signal of the third clock signal terminal CK3 and the signal of the second clock signal terminal CK2 may be inverted signals or may not be inverted signals.
  • the signal of the third clock signal terminal CK3 and the signal of the second clock signal terminal CK2 are inverted signals, when the signal of the third clock signal terminal CK3 is a valid level signal, the signal of the second clock signal terminal CK2 is an invalid level signal, and when the signal of the third clock signal terminal CK3 is an invalid level signal, the signal of the second clock signal terminal CK2 is a valid level signal.
  • the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are inverted signals to each other.
  • Fig. 19 is a signal timing simulation diagram of the shift register unit provided by Fig. 12 and Fig. 13. Fig. 19 is explained by taking the example that all transistors in the shift register unit are P-type transistors.
  • the eighth transistor T8 is continuously turned on.
  • the working process of the control shift register unit provided in FIG. 12 includes the following stages:
  • the signals of the signal input terminal IN and the first clock signal terminal CK1 are low-level signals
  • the signal of the second clock signal terminal GCK2 is a high-level signal.
  • the signal of the first clock signal terminal CK1 is a low-level signal
  • the first transistor T1 and the third transistor T3 are turned on
  • the low-level signal of the signal input terminal IN is written into the first node N1
  • the low-level signal of the second power supply terminal V2 is written into the second node N2. Since the eighth transistor T8 is continuously turned on, the signal of the third node N3 and the signal of the first node N1 are both low-level signals.
  • the signal of the first node N1 is a low-level signal
  • the second transistor T2 is turned on
  • the low-level signal of the first clock signal terminal CK1 is written into the second node N2, ensuring that the signal of the second node N2 continues to be a low-level signal.
  • the signal of the second node N2 is a low-level signal
  • the fourth transistor T4 and the sixth transistor T6 are turned on, the high-level signal of the first power supply terminal V1 is written into the first signal output terminal OUT1 and the fourth node N4, and the low-level signal of the second power supply terminal V2 is written into the second signal output terminal OUT2.
  • the signal of the third node N3 is a low-level signal
  • the fifth transistor T5 and the eleventh transistor T11 are turned on, and the signal of the third power supply terminal V3 is written to the first node N1, further pulling down the level signal of the first node N1, so that the signal of the first node N1 continues to be a low-level signal.
  • the seventh transistor T7 is turned off, the high-level signal of the fourth node N4 will not be written to the first node N1, and the signal of the first node N1 will not be pulled high.
  • the signals of the first node N1, the second node N2 and the third node N3 are low-level signals
  • the signal of the fourth node N4 is a high-level signal
  • the signal of the first power supply terminal V1 is written to the first signal output terminal OUT1
  • the output signal of the first signal output terminal OUT1 is a high-level signal.
  • the signals at the signal input terminal IN and the first clock signal terminal CK1 are high-level signals, and the signal at the second clock signal terminal GCK2 is a low-level signal.
  • the signal at the first clock signal terminal CK1 is a high-level signal, the first transistor T1 and the third transistor T3 are disconnected, and the signal at the first node N1 remains a low-level signal. Since the eighth transistor T8 is continuously turned on, the signal at the third node N3 and the signal at the first node N1 are both low-level signals.
  • the signal at the first node N1 is a low-level signal
  • the second transistor T2 is turned on, the high-level signal at the first clock signal terminal CK1 is written to the second node N2
  • the signal at the second node N2 is a high-level signal
  • the signal at the second node N2 is a high-level signal
  • the fourth transistor T4 and the sixth transistor T6 are disconnected, and the high-level signal at the first power supply terminal V1 cannot be written to the first signal output terminal OUT1.
  • the signal at the third node N3 is a low-level signal
  • the fifth transistor T5 and the eleventh transistor T11 are turned on, the signal at the third power supply terminal V3 is written to the first node N1, and the signal at the first node N1 is kept continuously low.
  • the low level signal of the second clock signal terminal CK2 is written into the first signal output terminal OUT1. Since the signal of the second clock signal terminal CK2 is a low level signal, the seventh transistor T7 is turned on, the signal of the fourth node N4 is pulled down by the signal of the first node N1, and the signal of the fourth node N4 is a low level signal. In this stage, the signals of the first node N1, the third node N3 and the fourth node N4 are low level signals, the signal of the second node N2 is a high level signal, the low level signal of the second clock signal terminal CK2 is written into the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a low level signal.
  • the signals of the signal input terminal IN and the second clock signal terminal GCK2 are high-level signals, and the signal of the first clock signal terminal CK1 is a low-level signal.
  • the signal of the first clock signal terminal CK1 is a low-level signal
  • the first transistor T1 and the third transistor T3 are turned on
  • the high-level signal of the signal input terminal IN is written into the first node N1
  • the low-level signal of the second power supply terminal V2 is written into the second node N2.
  • the eighth transistor T8 is continuously turned on
  • the signal of the third node N3 and the signal of the first node N1 are both high-level signals.
  • the signal of the first node N1 is a high-level signal
  • the second transistor T2 is turned off.
  • the signal of the second node N2 is a low-level signal
  • the fourth transistor T4 and the sixth transistor T6 are turned on, and the high-level signal of the first power supply terminal V1 is written into the first signal output terminal OUT1 and the fourth node N4.
  • the signal of the third node N3 is a high-level signal
  • the fifth transistor T5 and the eleventh transistor T11 are turned off, the signal of the third power supply terminal V3 cannot be written into the first node N1, the signal of the first node N1 is kept as a high-level signal
  • the high-level signal of the second clock signal terminal CK2 cannot be written into the first signal output terminal OUT1. Since the signal of the second clock signal terminal CK2 is a high level signal, the seventh transistor T7 is turned off.
  • the signal of the second node N2 is a low level signal
  • the signals of the first node N1, the third node N3 and the fourth node N4 are high level signals
  • the signal of the first power supply terminal V1 is written to the first signal output terminal OUT1
  • the output signal of the first signal output terminal OUT1 is a high level signal.
  • the signal input terminal IN and the first clock signal terminal CK1 are high-level signals, and the signal of the second clock signal terminal CK2 is a low-level signal.
  • the signal of the first clock signal terminal CK1 is a high-level signal
  • the first transistor T1 and the third transistor T3 are disconnected, and the signal of the first node N1 remains a high-level signal.
  • the eighth transistor T8 is continuously turned on, the signal of the third node N3 and the signal of the first node N1 are both high-level signals.
  • the signal of the first node N1 is a high-level signal, and the second transistor T2 is disconnected.
  • the signal of the second node N2 continues to be a low-level signal, the fourth transistor T4 and the sixth transistor T6 are turned on, and the high-level signal of the first power supply terminal V1 is written to the first signal output terminal OUT1 and the fourth node N4.
  • the signal of the third node N3 is a high-level signal, the fifth transistor T5 and the eleventh transistor T11 are disconnected, the signal of the third power supply terminal V3 cannot be written to the first node N1, the signal of the first node N1 is kept as a high-level signal, and the high-level signal of the second clock signal terminal CK2 cannot be written to the first signal output terminal OUT1. Since the signal of the second clock signal terminal CK2 is a high-level signal, the seventh transistor T7 is disconnected.
  • the signal of the second node N2 is a low level signal
  • the signals of the first node N1, the third node N3 and the fourth node N4 are high level signals
  • the signal of the first power supply terminal V1 is written into the first signal output terminal OUT1
  • the output signal of the first signal output terminal OUT1 is a high level signal.
  • the working process of the shift register unit further includes: a plurality of third stages S3 and fourth stages S4, and the third stage S3 and the fourth stage S4 work alternately.
  • the shift register unit provided in Figure 13 is different from the shift register unit provided in Figure 12 in that the node to which the control electrode of the eleventh transistor is connected is different.
  • Figure 12 is illustrated by taking the control electrode of the eleventh transistor being connected to the third node as an example
  • Figure 13 is illustrated by taking the control electrode of the eleventh transistor being connected to the first node. Since the signals of the first node N1 and the third node N3 are both high-level signals or both low-level signals, that is, the eleventh transistor in the shift register units provided in Figures 12 and 13 is turned on or turned off at the same time, the working process of the shift register unit provided in Figure 13 is the same as that of the shift register unit provided in Figure 12.
  • Fig. 20 is a signal timing simulation diagram of the shift register provided by Fig. 14 to Fig. 18.
  • Fig. 20 is explained by taking the example that all transistors in the shift register are P-type transistors.
  • the eighth transistor since the eighth transistor The control electrode of T8 is electrically connected to the second power supply terminal V2, and the eighth transistor T8 is continuously turned on.
  • the control electrodes of the eighth transistor T8 and the twelfth transistor T12 are both electrically connected to the second power supply terminal V2, and the eighth transistor T8 and the twelfth transistor T12 are continuously turned on.
  • the working process of the control shift register unit provided in FIG. 14 includes the following stages:
  • the signals of the signal input terminal IN, the first clock signal terminal CK1, and the third clock signal terminal CK3 are low-level signals
  • the signal of the second clock signal terminal GCK2 is a high-level signal.
  • the signal of the first clock signal terminal CK1 is a low-level signal
  • the first transistor T1 and the third transistor T3 are turned on
  • the low-level signal of the signal input terminal IN is written into the first node N1
  • the low-level signal of the second power supply terminal V2 is written into the second node N2. Since the eighth transistor T8 is continuously turned on, the signal of the third node N3 and the signal of the first node N1 are both low-level signals.
  • the signal of the first node N1 is a low-level signal
  • the second transistor T2 and the ninth transistor T9 are turned on, the low-level signal of the first clock signal terminal CK1 is written into the second node N2, ensuring that the signal of the second node N2 continues to be a low-level signal, and the low-level signal of the third clock signal terminal CK3 is written into the second signal output terminal OUT2.
  • the signal of the second node N2 is a low-level signal
  • the fourth transistor T4, the sixth transistor T6 and the tenth transistor T10 are turned on, the high-level signal of the first power supply terminal V1 is written into the first signal output terminal OUT1 and the fourth node N4, and the low-level signal of the second power supply terminal V2 is written into the second signal output terminal OUT2.
  • the signal of the third node N3 is a low-level signal
  • the fifth transistor T5 and the eleventh transistor T11 are turned on, and the signal of the third power supply terminal V3 is written into the first node N1, further pulling down the level signal of the first node N1, so that the signal of the first node N1 continues to be a low-level signal.
  • the seventh transistor T7 Since the signal of the second clock signal terminal CK2 is a high-level signal, the seventh transistor T7 is turned off, the high-level signal of the fourth node N4 will not be written into the first node N1, and the signal of the first node N1 will not be pulled high.
  • the signals of the first node N1, the second node N2 and the third node N3 are low-level signals
  • the signal of the fourth node N4 is a high-level signal
  • the signal of the first power supply terminal V1 is written into the first signal output terminal OUT1
  • the output signal of the first signal output terminal OUT1 is a high-level signal
  • the signal of the third clock signal terminal CK3 and the signal of the second power supply terminal V2 are written into the second signal output terminal OUT2
  • the output signal of the second signal output terminal OUT2 is a low-level signal.
  • the signals of the signal input terminal IN, the first clock signal terminal CK1 and the third clock signal terminal CK3 are high-level signals, and the signal of the second clock signal terminal GCK2 is a low-level signal.
  • the signal of the first clock signal terminal CK1 is a high-level signal
  • the first transistor T1 and the third transistor T3 are disconnected, and the signal of the first node N1 remains a low-level signal. Since the eighth transistor T8 is continuously turned on, the signal of the third node N3 and the signal of the first node N1 are both low-level signals.
  • the signal of the first node N1 is a low-level signal
  • the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal of the first clock signal terminal CK1 is written into the second node N2, the signal of the second node N2 is a high-level signal, the high-level signal of the third clock signal terminal CK3 is written into the second signal output terminal OUT2, the signal of the second node N2 is a high-level signal, the fourth transistor T4, the sixth transistor T6 and the tenth transistor T10 are disconnected, the high-level signal of the first power supply terminal V1 cannot be written into the first signal output terminal OUT1, and the low-level signal of the first low-level signal terminal VGL1 cannot be written into the second signal output terminal OUT2.
  • the signal of the third node N3 is a low-level signal
  • the fifth transistor T5 and the eleventh transistor T11 are turned on, the signal of the third power supply terminal V3 is written to the first node N1, the signal of the first node N1 is kept as a low-level signal, and the low-level signal of the second clock signal terminal CK2 is written to the first signal output terminal OUT1. Since the signal of the second clock signal terminal CK2 is a low-level signal, the seventh transistor T7 is turned on, the signal of the fourth node N4 is pulled down by the signal of the first node N1, and the signal of the fourth node N4 is a low-level signal.
  • the signals of the first node N1, the third node N3 and the fourth node N4 are low-level signals
  • the signal of the second node N2 is a high-level signal
  • the low-level signal of the second clock signal terminal CK2 is written to the first signal output terminal OUT1
  • the output signal of the first signal output terminal OUT1 is a low-level signal
  • the signal of the third clock signal terminal CK3 is written to the second signal output terminal OUT2
  • the output signal of the second signal output terminal OUT2 is a high-level signal.
  • the signals at the signal input terminal IN and the second clock signal terminal GCK2 are high level signals, and the signals at the first clock signal terminal CK1 and the third clock signal terminal CK3 are low level signals.
  • the signal is a low-level signal
  • the first transistor T1 and the third transistor T3 are turned on
  • the high-level signal of the signal input terminal IN is written to the first node N1
  • the low-level signal of the second power supply terminal V2 is written to the second node N2.
  • the eighth transistor T8 is continuously turned on
  • the signal of the third node N3 and the signal of the first node N1 are both high-level signals.
  • the signal of the first node N1 is a high-level signal
  • the second transistor T2 and the ninth transistor T9 are turned off.
  • the signal of the second node N2 is a low-level signal
  • the fourth transistor T4, the sixth transistor T6 and the tenth transistor T10 are turned on, the high-level signal of the first power supply terminal V1 is written to the first signal output terminal OUT1 and the fourth node N4, and the low-level signal of the second power supply terminal V2 is written to the second signal output terminal OUT2.
  • the signal of the third node N3 is a high-level signal
  • the fifth transistor T5 and the eleventh transistor T11 are turned off, the signal of the third power supply terminal V3 cannot be written to the first node N1, the signal of the first node N1 is kept as a high-level signal, and the high-level signal of the second clock signal terminal CK2 cannot be written to the first signal output terminal OUT1. Since the signal of the second clock signal terminal CK2 is a high-level signal, the seventh transistor T7 is turned off.
  • the signal of the second node N2 is a low level signal
  • the signals of the first node N1, the third node N3 and the fourth node N4 are high level signals
  • the signal of the first power supply terminal V1 is written to the first signal output terminal OUT1
  • the output signal of the first signal output terminal OUT1 is a high level signal
  • the signal of the second power supply terminal V2 is written to the second signal output terminal OUT2
  • the output signal of the second signal output terminal OUT2 is a low level signal.
  • the signals of the signal input terminal IN, the first clock signal terminal CK1 and the third clock signal terminal CK3 are high-level signals, and the signal of the second clock signal terminal CK2 is a low-level signal.
  • the signal of the first clock signal terminal CK1 is a high-level signal
  • the first transistor T1 and the third transistor T3 are disconnected, and the signal of the first node N1 remains a high-level signal. Since the eighth transistor T8 is continuously turned on, the signal of the third node N3 and the signal of the first node N1 are both high-level signals.
  • the signal of the first node N1 is a high-level signal
  • the second transistor T2 and the ninth transistor T9 are disconnected, and the high-level signal of the third clock signal terminal CK3 cannot be written into the second output signal terminal.
  • the signal of the second node N2 continues to be a low-level signal
  • the fourth transistor T4, the sixth transistor T6 and the tenth transistor T10 are turned on, the high-level signal of the first power supply terminal V1 is written into the first signal output terminal OUT1 and the fourth node N4, and the low-level signal of the second power supply terminal V2 is written into the second signal output terminal OUT2.
  • the signal of the third node N3 is a high-level signal
  • the fifth transistor T5 and the eleventh transistor T11 are disconnected, the signal of the third power supply terminal V3 cannot be written to the first node N1, the signal of the first node N1 is kept as a high-level signal, and the high-level signal of the second clock signal terminal CK2 cannot be written to the first signal output terminal OUT1. Since the signal of the second clock signal terminal CK2 is a high-level signal, the seventh transistor T7 is disconnected.
  • the signal of the second node N2 is a low-level signal
  • the signals of the first node N1, the third node N3 and the fourth node N4 are high-level signals
  • the signal of the first power supply terminal V1 is written to the first signal output terminal OUT1
  • the output signal of the first signal output terminal OUT1 is a high-level signal
  • the signal of the second power supply terminal V2 is written to the second signal output terminal OUT2
  • the output signal of the second signal output terminal OUT2 is a low-level signal.
  • the working process of the shift register unit includes: a plurality of third stages S3 and fourth stages S4, and the third stage S3 and the fourth stage S4 work alternately.
  • the shift register unit provided by Figure 15 is different from the shift register unit provided by Figure 14 in that the node to which the control electrode of the eleventh transistor is connected is different.
  • Figure 14 is illustrated by taking the control electrode of the eleventh transistor being connected to the third node as an example
  • Figure 15 is illustrated by taking the control electrode of the eleventh transistor being connected to the first node. Since the signals of the first node N1 and the third node N3 are both high-level signals or both low-level signals, that is, the eleventh transistor in the shift register units provided by Figures 14 and 15 is turned on or turned off at the same time, the working process of the shift register unit provided by Figure 15 is the same as that of the shift register unit provided by Figure 14.
  • the shift register unit provided by Figure 16 also includes: a twelfth transistor T12. Since the twelfth transistor T12 is turned on, the second transistor T12 can be equivalent to a section of wire and will not affect the working process of other transistors of the shift register unit. Therefore, the working process of the shift register unit provided by Figure 16 is the same as that of the shift register unit provided by Figure 14.
  • the shift register unit provided in FIG. 17 and FIG. 18 is different from the shift register unit provided in FIG. 15 in that
  • the shift register unit provided in Figures 17 and 18 also includes: a twelfth transistor T12. Since the twelfth transistor T12 is turned on, the second transistor T12 can be equivalent to a section of conductive wire and will not affect the working process of other transistors of the shift register unit. Therefore, the working process of the shift register unit provided in Figures 17 and 18 is the same as the working process of the shift register unit provided in Figure 15.
  • the setting of the eleventh transistor T11 in the present disclosure can pull the first node N1 down to the signal of the third power supply terminal V3 with a lower voltage value, thereby improving the conduction degree of the ninth transistor T9, so that the fifth transistor T5 and the ninth transistor T9 can be fully turned on.
  • FIG21 is a comparison diagram of the signals of the first node and the second signal output terminal of different shift register units.
  • N1-1 and OUT2-1 refer to the first node and the second signal output terminal in any one of the shift register units in FIG14 to FIG18 provided in the present application, respectively
  • N1-2 and OUT2-2 refer to the first node and the second signal output terminal in the shift register unit whose transistors only include the first transistor to the tenth transistor, respectively.
  • the shift register unit provided by the present disclosure can increase the voltage value of the output signal of the second signal output terminal, thereby improving the performance of the shift register unit.
  • the embodiment of the present disclosure further provides a driving method of a shift register unit, which is configured to drive the shift register unit.
  • the driving method of the shift register unit may include the following steps:
  • Step 100 Under the control of the first clock signal terminal and the second clock signal terminal, the node control subcircuit provides a signal from the signal input terminal or the first power terminal to the first node, and provides a signal from the second power terminal or the first clock signal terminal to the second node.
  • Step 200 The pull-down sub-circuit provides a signal of the third power terminal to the first node.
  • Step 300 The output sub-circuit provides a first power supply terminal or a second clock signal terminal to a first signal output terminal under the control of signals at a first node and a second node.
  • the shift register unit is the shift register unit provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.
  • the driving method of the shift register unit may further include: the output subcircuit provides a signal from the second power supply terminal or the third clock signal terminal to the second signal output terminal under the control of the signals from the first node and the second node.
  • the shift register unit may further include: an output control subcircuit; and the driving method of the shift register unit may further include: the output control subcircuit storing a voltage difference between a signal at the first signal output terminal and a signal at the first power supply terminal.
  • FIG22 is a schematic diagram of the structure of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a display substrate.
  • the display substrate includes: a pixel array, a timing controller is respectively connected to a data driver, a scan driver and a light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo).
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the scan signal line, the light emitting signal line and the data signal line.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc.
  • the data driver may generate data to be provided to the data signal lines D1, D2, D3, . . . and Dn using the grayscale value and the control signal received from the timing controller. Voltage.
  • the data driver can sample the grayscale value using a clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, and n can be a natural number.
  • the scan driver can generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller.
  • the scan driver can sequentially provide a scan signal with a conduction level pulse to the scan signal lines S1 to Sm.
  • the scan driver can be constructed in the form of a shift register unit, and can sequentially transmit the scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of the clock signal to generate a scan signal, and m can be a natural number.
  • the light-emitting driver can generate an emission signal to be provided to the light-emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller.
  • the light-emitting driver can sequentially provide an emission signal with a cut-off level pulse to the light-emitting signal lines E1 to Eo.
  • the light emitting driver may be constructed in the form of a shift register unit and may generate an emission signal in such a manner that an emission stop signal provided in the form of a cutoff level pulse is sequentially transmitted to a next stage circuit under the control of a clock signal, and o may be a natural number.
  • the display device may be a liquid crystal display (LCD) or an organic light emitting diode (OLED) display device.
  • the display device may be a liquid crystal panel, electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigation device, or any other product or component with a display function.
  • LCD liquid crystal display
  • OLED organic light emitting diode
  • AMOLED active-matrix organic light emitting diode
  • FIG23 is a schematic diagram of a planar structure of a display substrate
  • FIG24 is a schematic diagram of a planar structure of a display substrate
  • FIG25 is a schematic diagram of a planar structure of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, the plurality of pixel units P include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and at least one third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light emitting device.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line, and the light emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light emitting signal line, and output the corresponding current to the light emitting device.
  • the light emitting devices in the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the sub-pixels, and the light emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuits of the sub-pixels.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel P3 may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in horizontal parallel, vertical parallel or in a herringbone manner, which is not limited in the present disclosure.
  • a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a herringbone arrangement, etc., which is not limited in the present disclosure.
  • FIG23 is illustrated by taking the horizontal parallel arrangement as an example
  • FIG25 is illustrated by taking the herringbone arrangement as an example.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be a first sub-pixel, a second sub-pixel, and two third sub-pixels.
  • the four sub-pixels may be arranged in a horizontal parallel, a vertical parallel, or a square manner, which is not limited in the present disclosure.
  • FIG24 is illustrated by taking the arrangement of four sub-pixels in a square manner as an example.
  • the organic light emitting layer may include a stacked hole injection layer (Hole Injection Layer,
  • HIL light emitting layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • EML emitting layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the electron injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be a common layer connected together
  • the electron transport layers of all sub-pixels may be a common layer connected together
  • the hole blocking layers of all sub-pixels may be a common layer connected together
  • the emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated
  • the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • the display substrate is a LTPO display substrate.
  • the gate electrode of the first transistor M1 is electrically connected to the reset signal line Reset, the first electrode of the first transistor M1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor M1 is electrically connected to the first node N1;
  • the gate electrode of the second transistor M2 is electrically connected to the second scan signal line Gate2, the first electrode of the second transistor M2 is electrically connected to the first node N1, and the second electrode of the second transistor M2 is electrically connected to the third node N3;
  • the gate electrode of the third transistor M3 is electrically connected to the first node N1, the first electrode of the third transistor M3 is electrically connected to the second node N2, and the second electrode of the third transistor M3 is electrically connected to the third node N3;
  • the gate electrode of the fourth transistor M4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor M4 is electrically connected to the data signal line Data, and the The second electrode of the fourth transistor M4 is electrically connected to the
  • the first transistor M1 to the seventh transistor M7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS for short), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide oxide semiconductor
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • the low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form an LTPO display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.
  • the first transistor M1 and the second transistor M2 are opposite to the third transistor M3 to the seventh transistor M7 in transistor type.
  • the first transistor M1 and the second transistor M2 may be N-type transistors
  • the third transistor M3 to the seventh transistor M7 may be P-type transistors.
  • the first transistor M1 and the second transistor M2 may be oxide transistors, and the third to seventh transistors M3 to M7 may be low temperature polysilicon transistors.
  • the voltage value of the signal of the first initial signal line INIT1 is constant and is a DC signal.
  • the voltage value of the signal of the first initial signal line INIT1 may be -3V.
  • the voltage value of the signal of the second initial signal line INIT2 is constant and is a DC signal.
  • the voltage value of the signal of the second initial signal line INIT2 may be 0V.
  • the light emitting device L′ may be electrically connected to the fourth node N4 and the low-level power line VSS, respectively.
  • the high-level power line VDD continuously provides a high-level signal
  • the low-level power line VSS continuously provides a low-level signal
  • FIG26B is a working timing diagram of the pixel driving circuit provided in FIG26A. The following is an explanation of an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit illustrated in FIG26A during the display phase.
  • FIG26B is explained by taking the first transistor M1 and the second transistor M2 as N-type transistors, and the third transistor M3 to the seventh transistor M7 as P-type transistors as an example.
  • the pixel driving circuit in FIG26B includes the first transistor M1 to the seventh transistor M7, a capacitor C and 8 signal lines (data signal line Data, a first scanning signal line Gate1, a second scanning signal line Gate2, a reset signal line Reset, a first initial signal line INIT1, a second initial signal line INIT2, a light emitting signal line EM and a high-level power line VDD).
  • the operation process of the pixel driving circuit may include:
  • the first stage P1 is called the initialization stage.
  • the signal of the reset signal line Reset is a high-level signal
  • the first transistor M1 is turned on, and the signal of the first initial signal line INIT1 is written into the first node N1 through the turned-on first transistor M1, and the first node N1 is initialized (resettled), and the pre-stored voltage inside it is cleared to complete the initialization.
  • the second stage P2 is called the data writing stage or the threshold compensation stage, the first scanning signal line Gate1 is a low level signal, the second scanning signal line Gate2 is a low level signal, and the data signal line Data outputs a data voltage.
  • the third transistor M3 is turned on.
  • the signal of the first scanning signal line Gate1 is a low-level signal
  • the fourth transistor M4 is turned on and the seventh transistor M7 is turned on
  • the signal of the second scanning signal line Gate2 is a high-level signal
  • the second transistor M2 is turned on
  • the data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor M4, the second node N2, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 is Vd-
  • the third stage P3 is called the light-emitting stage.
  • the signal of the light-emitting signal line EM is a low-level signal.
  • the fifth transistor M5 and the sixth transistor M6 are turned on.
  • the power supply voltage output by the high-level power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3 and the sixth transistor M6, thereby driving the light-emitting device L to emit light.
  • the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-
  • )-Vth]2 K*(Vdd-Vd)2
  • I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3
  • Vth is the threshold voltage of the third transistor M3
  • Vd is the data voltage output by the data signal line Data
  • Vdd is the power supply voltage output by the high-level power supply line VDD.
  • FIG27A is a schematic diagram of an equivalent circuit of another pixel driving circuit.
  • the pixel driving circuit may include 8 transistors (first transistor M1 to eighth transistor M8), 1 capacitor C and 9 signal lines (data signal line Data, control signal line Scan, scan signal line Gate, reset signal line Reset, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, high level power line VDD and low level power line VSS).
  • a first electrode of the capacitor C is connected to a high-level power supply line VDD, and a second electrode of the capacitor C is connected to a first node N1.
  • a control electrode of the first transistor M1 is connected to a reset signal line Reset, a first electrode of the first transistor M1 is connected to a first initial signal line INIT1, and a second electrode of the first transistor is connected to a fourth node N4.
  • a control electrode of the second transistor M2 is connected to a scan signal line Gate, a first electrode of the second transistor M2 is connected to a fourth node N4, and a second electrode of the second transistor M2 is connected to a second node N2.
  • a control electrode of the third transistor M3 is connected to the first node N1, a first electrode of the third transistor M3 is connected to a second node N2, and a second electrode of the third transistor M3 is connected to a third node N3.
  • a control electrode of the fourth transistor M4 is connected to a scan signal line Gate, a first electrode of the fourth transistor M4 is connected to a data signal line Data, and a second electrode of the fourth transistor M4 is connected to a third node N3.
  • a control electrode of the fifth transistor M5 is connected to a light-emitting signal line EM, a first electrode of the fifth transistor M5 is connected to a high-level power supply line VDD, and a second electrode of the fifth transistor M5 is connected to a third node N3.
  • the control electrode of the sixth transistor M6 is connected to the light emitting signal line EM, the first electrode of the sixth transistor M6 is connected to the second node N2, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light emitting device L.
  • the control electrode of the seventh transistor M7 is connected to the reset signal line Reset, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light emitting device L, and the second electrode of the light emitting device L is connected to the low level power line VSS.
  • the control electrode of the eighth transistor M8 is connected to the control signal line Scan, the first electrode of the eighth transistor M8 is connected to the first node N1, and the second electrode of the eighth transistor M8 is connected to the fourth node N4.
  • control electrode of the seventh transistor M7 can also be connected to the scan signal line Gate, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light emitting device L, and the second electrode of the light emitting device L is connected to the low level power line VSS.
  • the signal of the high-level power line VDD is a continuously provided high-level signal
  • the signal of the low-level power line VSS is a low-level signal
  • the eighth transistor M8 is a metal oxide transistor and is an N-type transistor
  • the first to seventh transistors M1 to M7 are low temperature polysilicon transistors and are P-type transistors.
  • the eighth transistor M8 is an oxide transistor, which can reduce leakage current, improve the performance of the pixel driving circuit, and reduce the power consumption of the pixel driving circuit.
  • FIG27B is a timing diagram of the operation of the pixel driving circuit provided in FIG27A.
  • the following describes an exemplary embodiment of the present disclosure through the operation process of the pixel driving circuit illustrated in FIG27B.
  • the operation process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage.
  • the signals of the control signal line Scan, the light emitting signal line EM and the scanning signal line Gate are all high-level signals, and the signal of the reset signal line Reset is a low-level signal.
  • the signal of the reset signal line Reset is a low-level signal, the first transistor M1 is turned on, the signal of the first initial signal line INIT1 is provided to the fourth node N4, the seventh transistor M7 is turned on, and the initial voltage of the second initial signal line INIT2 is provided to the first electrode of the light emitting device L, and the first electrode of the light emitting device L is initialized (reset), for example: the pre-stored voltage inside it is cleared, the initialization is completed, and the light emitting device L is ensured not to emit light.
  • the signal of the control signal line Scan is a high-level signal
  • the eighth transistor M8 is turned on
  • the signal of the fourth node N4 is provided to the first node N1
  • the capacitor C is initialized
  • the original data voltage in the capacitor C is cleared.
  • the signals of the scanning signal line Gate and the light emitting signal line EM are high-level signals
  • the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are turned off, and in this stage, the light emitting device L does not emit light.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the scanning signal line Gate is a low level signal, and the signals of the reset signal line Reset, the luminous signal line EM and the control signal line Scan are high level signals.
  • the data signal line Data outputs a data voltage.
  • the third transistor M3 is turned on.
  • the signal of the scan signal line Gate is a low-level signal, the second transistor M2 and the fourth transistor M4 are turned on, the signal of the control signal line Scan is a high-level signal, and the eighth transistor M8 is turned on.
  • the second transistor M2, the fourth transistor M4 and the eighth transistor M8 are turned on so that the data voltage output by the data signal line Data is provided to the first node N1 through the third node N3, the turned-on third transistor M3, the second node N2, the turned-on second transistor M2, the fourth node N4 and the turned-on eighth transistor M8, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 is Vd-
  • the signal of the reset signal line Reset is a low-level signal, and the first transistor M1 and the seventh transistor M7 are turned off.
  • the signal of the light emitting signal line EM is a high level signal, and the fifth transistor M5 and the sixth transistor M6 are turned off.
  • the third stage A3 is called the light-emitting stage.
  • the signals of the control signal line Scan and the light-emitting signal line EM are both low-level signals, and the signals of the scanning signal line Gate and the reset signal line Reset are high-level signals.
  • the signal of the reset signal line Reset is a low-level signal, and the first transistor M1 and the seventh transistor M7 are turned off.
  • the control signal line Scan is a low-level signal, the signals of the scanning signal line Gate and the reset signal line Reset are high-level signals, and the second transistor M2, the fourth transistor M4 and the eighth transistor M8 are turned off.
  • the signal of the light-emitting signal line EM is a low-level signal
  • the fifth transistor M5 and the sixth transistor M6 are turned on
  • the power supply voltage output by the high-level power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3 and the sixth transistor M6, driving the light-emitting device L to emit light.
  • the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-
  • )-Vth]2 K*(Vdd-Vd)2
  • I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the third transistor M3
  • Vth is the threshold voltage of the third transistor M3
  • Vd is the data voltage output by the data signal line Data
  • Vdd is the power supply voltage output by the high-level power supply line VDD.
  • the display substrate provided by the embodiment of the present disclosure may include: a substrate and sub-pixels, gate lines and a gate driving circuit arranged on the substrate, the substrate is provided with a display area and a non-display area, the gate driving circuit is located in the non-display area, the sub-pixels and the gate lines are located in the display area, and the gate lines are electrically connected to the sub-pixels and the gate driving circuit, respectively.
  • the subpixel includes: a pixel driving circuit and a light emitting device.
  • the gate line may include: at least one of a reset signal line, a first scan signal line, a second scan signal line, and a light emitting signal line.
  • the subpixel includes: a pixel driving circuit and a light emitting device.
  • the gate line may include: at least one of a reset signal line, a first scan signal line, a second scan signal line, a control signal line, and a light emitting signal line.
  • the shift register unit is the shift register unit provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.
  • FIG28 is a cascade schematic diagram of a gate drive circuit 1
  • FIG29 is a cascade schematic diagram of a gate drive circuit 2.
  • the first signal output terminal OUT1 of the i-th shift register unit GOA(i) is connected to the signal input terminal IN of the i+1-th shift register unit GOA(i+1), 1 ⁇ i ⁇ N, and N is the total number of shift register units.
  • FIG28 is illustrated by taking the shift register units provided in FIG12 and FIG13 as an example
  • FIG29 is illustrated by taking the shift register units provided in FIG14 to FIG18 as an example.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and a conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked.
  • the materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc.
  • the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, the first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).
  • its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.
  • PI1 first flexible
  • a-si amorphous silicon
  • the first signal output terminal OUT1 of the shift register unit may be electrically connected to the gate line.
  • the second signal output terminal OUT2 of the shift register unit may be electrically connected to the gate line.
  • FIG. 30 is a schematic diagram of the structure of the display substrate 1
  • FIG. 31 is a schematic diagram of the structure of the display substrate 2.
  • FIG. 30 is illustrated by taking the shift register unit provided in FIG. 12 as an example
  • FIG. 31 is illustrated by taking the shift register unit provided in FIG. 18 as an example.
  • the display substrate may further include: an initial signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a first power line VGH, a second power line VGL1, and a third power line VGL2, which are disposed on the substrate and located in the non-display area.
  • the signal input terminal IN of the first-stage shift register unit GOA(1) is electrically connected to the initial signal line STV
  • the first power terminal of the i-th stage shift register unit is electrically connected to the first power line VGH
  • the second power terminal of the i-th stage shift register unit is electrically connected to the second power line VGL1
  • the third power terminal of the i-th stage shift register unit is electrically connected to the third power line VGL2.
  • any one of the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, the second power line VGL1 and the third power line VGL2 extends along the first direction D1
  • the gate line extends along the second direction D2
  • the first direction D1 intersects the second direction D2.
  • the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2 and the first power line VGH are sequentially arranged in a direction close to the display area and are located on a side of the shift register unit away from the display area.
  • the shift register unit includes a plurality of transistors, and the second power line VGL1 is located on a side of the first power line VGH close to the display area and between the plurality of transistors of the shift register unit.
  • the third power line VGL2 is located on a side of the second power line VGL1 close to the display area, and its orthographic projection on the substrate partially overlaps with the orthographic projection of the shift register unit on the substrate.
  • the shift register unit includes: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, an eleventh transistor T11 and a twelfth transistor T12, and the number of the second power line VGL1 is at least one, wherein at least a portion of any one of the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the eleventh transistor T11 and the twelfth transistor T12 is located on a side of the second power line VGL1 close to the display area.
  • the shift register unit includes: a second capacitor C2 ; the second capacitor C2 is located at a side of the third power line VGL2 close to the display area.
  • the display substrate may further include: a third clock signal line CLK3 and a fourth clock signal line CLK4 disposed on the base and located in the non-display area, and either one of the third clock signal line CLK3 and the fourth clock signal line CLK4 extends along the first direction D1.
  • the number of the second power lines VGL1 is two, the second power line VGL1 close to the display area is located on a side of any one of the third clock signal line CLK3 and the fourth clock signal line CLK4 close to the display area, and the second power line VGL1 away from the display area is located between the first power line VGH and the third power line VGL2.
  • the shift register unit includes: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12 and a fourth capacitor C4.
  • the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the eleventh transistor T11 and the twelfth transistor T12 are located between the second power line VGL1 and any one of the third clock signal line CLK3 and the fourth clock signal line CLK4 away from the display area, and the ninth transistor T9 and the tenth transistor T10 are located on the side of the second power line VGL1 close to the display area close to the display area.
  • the orthographic projection of the second power line VGL1 near the display area on the substrate partially overlaps with the orthographic projection of the fourth capacitor C 4 on the substrate.
  • the first clock signal terminal CK1 of the i-th stage shift register unit is electrically connected to one of the first clock signal line CLK1 and the second clock signal line CLK2, and the second clock signal terminal CK2 of the i-th stage shift register unit is electrically connected to the other of the first clock signal line CLK1 and the second clock signal line CLK2; the first clock signal terminals of adjacent shift register units are connected to different signal lines, and the second clock signal terminals of adjacent shift register units are connected to different signal lines.
  • the first clock signal terminal CK1 of the odd-numbered shift register unit can be electrically connected to the first clock signal line CLK1
  • the second clock signal terminal CK2 of the odd-numbered shift register unit can be electrically connected to the second clock signal line CLK2
  • the first clock signal terminal CK1 of the even-numbered shift register unit can be electrically connected to the second clock signal line CLK2
  • the second clock signal terminal CK2 of the even-numbered shift register unit can be electrically connected to the first clock signal line CLK1
  • the first clock signal terminal CK1 of the odd-numbered shift register unit can be electrically connected to the second clock signal line CLK2
  • the second clock signal terminal CK2 of the odd-numbered shift register unit can be electrically connected to the first clock signal line CLK1
  • the The first clock signal terminal CK1 of the even-numbered shift register unit can be electrically connected to the first clock signal line CLK1, and the second clock signal terminal CK2 of the even-numbered shift register unit can be electrically connected to the second clock signal line CLK2.
  • Figures 28 and 29 are explained by taking the example that the first clock signal terminal CK1 of the odd-numbered shift register unit can be electrically connected to the first clock signal line CLK1, the second clock signal terminal CK2 of the odd-numbered shift register unit can be electrically connected to the second clock signal line CLK2, the first clock signal terminal CK1 of the even-numbered shift register unit can be electrically connected to the second clock signal line CLK2, and the second clock signal terminal CK2 of the even-numbered shift register unit can be electrically connected to the first clock signal line CLK1.
  • the third clock signal terminal CK3 of the i-th shift register unit is electrically connected to one of the third clock signal line CLK3 and the fourth clock signal line CLK4, and the third clock signal terminal CK3 of the i+1-th shift register unit is electrically connected to the other of the third clock signal line CLK3 and the fourth clock signal line CLK4.
  • the third clock signal terminal CK3 of the odd-numbered shift register unit is electrically connected to the third clock signal line CLK3, and the third clock signal terminal CK3 of the even-numbered shift register unit is electrically connected to the fourth clock signal line CLK4, or the third clock signal terminal CK3 of the odd-numbered shift register unit is electrically connected to the fourth clock signal line CLK4, and the third clock signal terminal CK3 of the even-numbered shift register unit is electrically connected to the third clock signal line CLK3.
  • 29 is an example in which the third clock signal terminal CK3 of the odd-numbered shift register unit is electrically connected to the third clock signal line CLK3, and the third clock signal terminal CK3 of the even-numbered shift register unit is electrically connected to the fourth clock signal line CLK4.
  • an orthographic projection of the third power line VGL2 on the substrate partially overlaps with an orthographic projection of the fourth transistor T4 and the fifth transistor T5 on the substrate.
  • the active layer T81 of the eighth transistor T8 extends along the second direction D2
  • any one of the first electrode T83 and the second electrode T84 of the eighth transistor T8 extends along the first direction D1
  • the gate electrode T82 of the eighth transistor T8 at least partially extends along the first direction D1.
  • the gate electrode T112 of the eleventh transistor is an integral structure with the gate electrode T52 of the fifth transistor
  • the orthographic projection of the first electrode T113 of the eleventh transistor on the substrate partially overlaps with the orthographic projection of the third power line VGL2 on the substrate, and is electrically connected to the third power line VGL2
  • the second electrode T114 of the eleventh transistor is an integral structure with the first electrode T83 of the eighth transistor and the first electrode T123 of the twelfth transistor.
  • the width of any one of the first power line VGH, the second power line VGL1, and the third power line VGL2 along the second direction D2 is smaller than the width of any one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 along the second direction D2.
  • the width of any one of the first clock signal line CLK1 , the second clock signal line CLK2 , the third clock signal line CLK3 and the fourth clock signal line CLK4 along the second direction D2 is wider to reduce the load of the clock signal lines.
  • a channel width of an active layer of the tenth transistor is greater than a channel width of an active layer of the fourth transistor.
  • the channel width of the active layer of the tenth transistor is not less than 90 micrometers.
  • the channel width of the active layer of the tenth transistor may be about 100 micrometers.
  • a channel length of the active layer of the tenth transistor may be approximately 3.5 micrometers, and a channel width-to-length ratio of the active layer of the tenth transistor may be approximately 100/3.5.
  • the channel width of the active layer of the fourth transistor is no greater than 50 micrometers.
  • the channel width of the active layer of the fourth transistor may be approximately 25 micrometers.
  • a channel length of the active layer of the fourth transistor may be approximately 3.5 micrometers, and a channel width-to-length ratio of the active layer of the fourth transistor may be approximately 25/3.5.
  • a channel width of an active layer of the ninth transistor is greater than a channel width of an active layer of the fifth transistor.
  • the channel width of the active layer of the ninth transistor is not less than 90 micrometers.
  • the channel width of the active layer of the ninth transistor may be about 100 micrometers.
  • the channel length of the active layer of the ninth transistor may be about 3.5 micrometers.
  • the channel width-to-length ratio of the active layer of the tube may be about 100/3.5.
  • the channel width of the active layer of the fifth transistor is no greater than 50 micrometers.
  • the channel width of the active layer of the fifth transistor may be approximately 25 micrometers.
  • a channel length of the active layer of the fifth transistor may be approximately 3.5 micrometers, and a channel width-to-length ratio of the active layer of the fifth transistor may be approximately 25/3.5.
  • the display substrate may further include: a driving structure layer disposed on the substrate;
  • the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate;
  • the shift register unit includes: a plurality of transistors and a plurality of capacitors, any one of the capacitors includes: a first plate and a second plate;
  • the semiconductor layer includes at least: an active layer of a plurality of transistors located in at least one shift register unit;
  • the first conductive layer at least includes: control electrodes of a plurality of transistors located in at least one shift register unit and first plates of a plurality of capacitors;
  • the third conductive layer at least includes: an initial signal line, a first clock signal line, a second clock signal line, a first power line, a second power line, a third clock signal line, a fourth clock signal line, and first and second electrodes of a plurality of transistors located in at least one shift register unit;
  • the fourth conductive layer at least includes: a third power line.
  • the driving structure layer may further include: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer and a flat layer, wherein the first insulating layer is located between the semiconductor layer and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, the third insulating layer is located between the second conductive layer and the third conductive layer, the fourth insulating layer is located between the third conductive layer and the fourth conductive layer, the fifth insulating layer is located on a side of the fourth conductive layer away from the substrate, and the flat layer is located on a side of the fifth insulating layer away from the substrate.
  • the following is an exemplary explanation through the preparation process of the display substrate.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • FIG. 32 is a schematic diagram of FIG. 30 after forming a semiconductor layer pattern
  • FIG. 33 is a schematic diagram of FIG. 31 after forming a semiconductor layer pattern.
  • the semiconductor layer pattern may include active layers T11 to T81 of first to eighth transistors and T111 of eleventh transistors of at least one shift register unit, and an active connection block AL.
  • the semiconductor layer pattern may include an active layer T11 of a first transistor to an active layer T121 of a twelfth transistor located in at least one shift register unit and an active connection block AL.
  • the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor are an integrated structure
  • the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor are an integrated structure.
  • the active layer T11 of the first transistor, the active layer T21 of the second transistor, the active layer T31 of the third transistor, the active layer T81 of the eighth transistor, the active layer T111 of the eleventh transistor, and the active connection block AL may be provided separately.
  • the active layer T91 of the ninth transistor and the active layer T101 of the fourth transistor are an integral structure, and the active layer T121 of the twelfth transistor may be provided separately.
  • the active layer T11 of the first transistor and the active layer T61 of the sixth transistor are arranged along the second direction D2, and the active layer T11 of the first transistor of the shift register unit of this stage is located on the side of the active layer T61 of the sixth transistor (also the active layer T71 of the seventh transistor) of the shift register unit of this stage close to the shift register unit of the previous stage.
  • the active layer T21 of the second transistor is located on the side of the active layer T11 of the first transistor close to the display area.
  • the active layer T31 of the third transistor and the active connection block AL are arranged along the second direction D2 and are located on the side of the active layer T21 of the second transistor close to the display area.
  • the active layer T81 of the eighth transistor, the active layer T111 of the eleventh transistor and the active layer T41 of the fourth transistor (also the active layer T51 of the fifth transistor) are arranged in sequence along the second direction D2, and are located on the side of the active layer T31 of the third transistor close to the display area, wherein the active layer T111 of the eleventh transistor of the shift register unit at this level is located on the side of the active layer T81 of the eighth transistor of the shift register unit at this level close to the shift register unit of the next level, and the active layer T41 of the fourth transistor of the shift register unit at this level (also the active layer T51 of the fifth transistor) is located on the side of the active layer T111 of the eleventh transistor of the shift register unit at this level close to the shift register unit of the next level.
  • the active layer T121 of the twelfth transistor of the shift register unit at this level is located on the side of the active layer T81 of the eighth transistor of the shift register unit at this level close to the shift register unit at the previous level, and the active layer of the ninth transistor of the shift register unit at this level (also the active layer of the fourth transistor) is located on the side of the active layer T41 of the fourth transistor (also the active layer T51 of the fifth transistor) close to the display area.
  • the active layers T11 of the first transistor to T71 of the seventh transistor are strip-shaped and extend in the first direction D1.
  • the active layers T81 of the eighth transistor and T11 of the eleventh transistor are strip-shaped and extend in the second direction D2.
  • the active connection block AL may be block-shaped.
  • the active layer of the ninth transistor (also the active layer of the fourth transistor) is strip-shaped and extends along the first direction D1.
  • the active layer T121 of the twelfth transistor is strip-shaped and extends along the second direction D2.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the first region and the second region will be conductorized after the subsequent first conductive layer is formed, and therefore may also be referred to as a conductive region.
  • a first region T11-1 and a second region T11-2 of an active layer T11 of a first transistor a first region T21-1 and a second region T21-2 of an active layer T21 of a second transistor, a first region T31-1 and a second region T31-2 of an active layer T31 of a third transistor, a first region T41-1 of an active layer T41 of a fourth transistor, a first region T51-1 of an active layer T51 of a fifth transistor, a first region T61-1 of an active layer T61 of a sixth transistor, a second region T71-2 of an active layer T71 of a seventh transistor, a first region T81-1 and a second region T81-2 of an active layer T81 of an eighth transistor, a first region T91-1 of an active layer T91 of a ninth transistor, and a second region T91-2 of an active layer T91 of a ninth transistor.
  • the first region T101-1 of the active layer T101 of the fourth transistor, the first region T111-1 and the second region T111-2 of the active layer T111 of the eleventh transistor, and the first region T121-1 and the second region T121-2 of the active layer T121 of the twelfth transistor may be separately provided.
  • FIGS. 34 to 37 (2) forming a first conductive layer pattern, comprising: depositing a first insulating film and a first conductive film on the substrate having the aforementioned pattern, patterning the first insulating film and the first conductive film by a patterning process, forming a first insulating layer pattern and a first conductive layer pattern disposed on the first insulating layer pattern, as shown in FIGS. 34 to 37, wherein FIG. 34 is a schematic diagram of the first conductive layer pattern in FIG. 30, FIG. 35 is a schematic diagram of FIG. 30 after the first conductive layer pattern is formed, FIG. 36 is a schematic diagram of the first conductive layer pattern in FIG. 31, and FIG. 37 is a schematic diagram of FIG. 31 after the first conductive layer pattern is formed.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern may include: a control electrode T12 of a first transistor to a control electrode T82 of an eighth transistor located in at least one shift register unit, a control electrode T112 of an eleventh transistor, a first electrode plate C21 of a second capacitor, and a first connecting line L1.
  • the first conductive layer pattern may include: a control electrode T12 of a first transistor to a control electrode T122 of a twelfth transistor located in at least one shift register unit, a first plate C21 of a second capacitor, a first plate C41 of a fourth capacitor, and a first connecting line L1.
  • the control electrode T12 of the first transistor and the control electrode T32 of the third transistor are an integrated structure.
  • the control electrode T52 of the fifth transistor, the control electrode T112 of the eleventh transistor and the first electrode plate C21 of the second capacitor are an integrated structure.
  • the control electrode T42 of the fourth transistor and the control electrode T62 of the sixth transistor are an integrated structure.
  • the control electrode T22 of the second transistor, the control electrode T72 of the seventh transistor, the control electrode T82 of the eighth transistor and the first connection line L1 may be separately provided.
  • control electrode T42 of the fourth transistor, the control electrode T62 of the sixth transistor, the control electrode T102 of the fourth transistor, and the first electrode plate C41 of the fourth capacitor are an integrated structure.
  • the control electrode T82 of the eighth transistor and the control electrode T122 of the twelfth transistor are an integrated structure.
  • the control electrode T92 of the ninth transistor can be provided separately.
  • the control electrode T12 of the first transistor includes: a first connection portion T12A and a second connection portion T12B, the first connection portion T12A extends along the first direction D1, the second connection portion T12B is in a “ ⁇ ” shape, and the second connection portion T12B is connected to the middle of the first connection portion T12A.
  • the control electrode T32 of the third transistor may be in a strip shape and extends along the second direction D2. The control electrode T32 of the third transistor is connected to the end of the second connection portion T12B.
  • the shape of the first electrode C21 of the second capacitor may be square
  • the shape of the control electrode T52 of the fifth transistor is strip-shaped and extends along the second direction D2
  • the shape of the control electrode T112 of the eleventh transistor is “ ⁇ ”
  • the control electrode T52 of the fifth transistor and the control electrode T112 of the eleventh transistor are located on the side of the first electrode C21 of the second capacitor away from the display area.
  • control electrode T42 of the fourth transistor (also the control electrode T62 of the sixth transistor) is in the shape of a strip and extends along the second direction D2 .
  • the shape of the first electrode plate C41 of the fourth capacitor may be a square
  • the control electrode T102 of the fourth transistor includes: a plurality of first branch segments T102A, the first branch segments T102A extend along the second direction D2, and the plurality of first branch segments T102A are arranged along the first direction D1.
  • the control electrode T62 of the sixth transistor and the control electrode T42 of the fourth transistor are located on the side of the first electrode plate C41 of the fourth capacitor away from the display area, and the control electrode T102 of the fourth transistor is located on the side of the first electrode plate C41 of the fourth capacitor close to the display area.
  • FIGS. 36 and 37 are described by taking two first branch segments T102A as an example.
  • the shape of the control electrode T82 of the eighth transistor may be It is in the shape of a groove with an opening facing upward.
  • control electrode T122 of the twelfth transistor is in a strip shape and extends along the first direction D1 .
  • the control electrode T92 of the ninth transistor includes: a second connection segment T92A and a plurality of second branch segments T92B.
  • the second connection segment T92A is in the shape of a “ ⁇ ”, the second branch segment T92B extends along the second direction D2, and the plurality of second branch segments T92B are arranged along the first direction D1.
  • the second connection segment T92A is equivalent to a “comb back”, and the plurality of second branch segments T92B are equivalent to “comb teeth”.
  • control electrode T22 of the second transistor, the control electrode T72 of the seventh transistor, and the first connection line L1 may be strip-shaped and at least partially extend along the second direction D2 .
  • the first connection segment T12A and the second connection segment T12B of the control electrode T12 of the first transistor are respectively arranged across the active layer of the first transistor
  • the control electrode T22 of the second transistor is arranged across the active layer of the second transistor
  • the control electrode T32 of the third transistor is arranged across the active layer of the third transistor
  • the control electrode T42 of the fourth transistor is arranged across the active layer of the fourth transistor
  • the control electrode T52 of the fifth transistor is arranged across the active layer of the fifth transistor
  • the control electrode T62 of the sixth transistor is arranged across the active layer of the sixth transistor
  • the control electrode T72 of the seventh transistor is arranged across the active layer of the seventh transistor.
  • this process also includes a conductorization process.
  • the conductorization process is to use the semiconductor layer of the control electrode shielding area of multiple transistors (i.e., the area where the semiconductor layer and the control electrode overlap) as the channel area of the transistor after forming the first conductive layer, and the semiconductor layer in the area not shielded by the first conductive layer is processed into a conductorization layer to form an electrode connection portion of the transistor. As shown in FIG.
  • the active connection line AL in the present disclosure is processed into a conductorization layer to form a conductorized active connection line AL, and the second area of the active layer of the sixth transistor after conductorization (also the first area of the active layer of the seventh transistor) can be reused as the second electrode T64 of the sixth transistor and the first electrode T73 of the seventh transistor.
  • FIGS. 38 to 41 wherein FIG. 38 is a schematic diagram of the second conductive layer pattern in FIG. 30, FIG. 39 is a schematic diagram of FIG. 30 after the second conductive layer pattern is formed, FIG. 40 is a schematic diagram of the second conductive layer pattern in FIG. 31, and FIG. 41 is a schematic diagram of FIG. 31 after the second conductive layer pattern is formed.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern may include a second plate C22 of a second capacitor located in at least one shift register unit and a second connection line L2 .
  • the second conductive layer pattern may include: a second plate C22 of a second capacitor located in at least one shift register unit, a second plate C42 of a fourth capacitor, a second connection line L2, a third connection line L3, and a fourth connection line L4.
  • the second plate C22 of the second capacitor is square in shape, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first plate of the second capacitor on the substrate.
  • the second plate C42 of the fourth capacitor is square in shape, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first plate of the fourth capacitor on the substrate.
  • the second connection lines L2 may be in a bar shape and at least partially extend along the second direction D2 .
  • the third connection line L3 may be shaped like a bar and extend at least partially in the second direction D2.
  • the fourth connection line L4 may be shaped like a bar and extend at least partially in the first direction D1.
  • FIGS. 42 and 43 (4) forming a third insulating layer pattern, including: depositing a third insulating film on the substrate having the aforementioned pattern, and composing the third insulating film through a patterning process to form a third insulating layer pattern covering the aforementioned structure, wherein the third insulating layer is provided with a plurality of via patterns, as shown in FIGS. 42 and 43 , wherein FIG. 42 is a schematic diagram of FIG. 30 after the third insulating layer pattern is formed, and FIG. 43 is a schematic diagram of FIG. 31 after the third insulating layer pattern is formed.
  • the plurality of via patterns may include first to thirteenth vias V13 , seventeenth to eighteenth vias V17 , twenty-first to twenty-seventh vias V21 to V27 , twenty-ninth to thirty-second vias V29 , thirty-second to thirty-second vias V32 .
  • the plurality of via hole patterns may include first to thirty-fourth via holes V1 to V34 .
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first transistor on the substrate, the first insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the active layer of the first transistor, and the first via hole V1 is configured to connect the first electrode of the subsequently formed first transistor to the first region of the active layer of the first transistor through the via hole.
  • the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the first transistor on the substrate, the first insulating layer and the second insulating layer in the second via V2 are etched away to expose the surface of the second region of the active layer of the first transistor, and the second via V2 is configured to connect the second electrode of the subsequently formed first transistor (also the second electrode of the seventh transistor) to the second region of the active layer of the first transistor through the via.
  • the orthographic projection of the third via V3 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the second transistor on the substrate, the first insulating layer and the second insulating layer in the third via V3 are etched away to expose the surface of the first area of the active layer of the second transistor, and the third via V3 is configured to connect the first electrode of the subsequently formed second transistor to the first area of the active layer of the second transistor through the via.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the second transistor on the substrate, the first insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the active layer of the second transistor, and the fourth via hole V4 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the third transistor) to the second region of the active layer of the second transistor through the via hole.
  • the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the third transistor on the substrate, the first insulating layer and the second insulating layer in the fifth via V5 are etched away to expose the surface of the first area of the active layer of the third transistor, and the fifth via V5 is configured to connect the first electrode of the subsequently formed third transistor to the first area of the active layer of the third transistor through the via.
  • the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the third transistor on the substrate, the first insulating layer and the second insulating layer in the sixth via V6 are etched away to expose the surface of the second region of the active layer of the third transistor, and the sixth via V6 is configured to connect the second electrode of the subsequently formed third transistor (also the second electrode of the second transistor) to the second region of the active layer of the third transistor through the via.
  • the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fourth transistor on the substrate, the first insulating layer and the second insulating layer in the seventh via V7 are etched away to expose the surface of the first area of the active layer of the fourth transistor, and the seventh via V7 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of the active layer of the fourth transistor through the via.
  • the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the fourth transistor (also the second area of the active layer of the fifth transistor) on the substrate, the first insulating layer and the second insulating layer in the eighth via V8 are etched away to expose the surface of the second area of the active layer of the fourth transistor (also the second area of the active layer of the fifth transistor), and the eighth via V8 is configured to connect the second electrode of the subsequently formed fourth transistor (also the second electrode of the fifth transistor) to the second area of the active layer of the fourth transistor (also the second area of the active layer of the fifth transistor) through the via.
  • the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fifth transistor on the substrate, the first insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the first area of the active layer of the fifth transistor, and the ninth via V9 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of the active layer of the fifth transistor through the via.
  • the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the sixth transistor on the substrate, the first insulating layer and the second insulating layer in the tenth via V10 are etched away to expose the surface of the first area of the active layer of the sixth transistor, and the tenth via V10 is configured to connect the first electrode of the subsequently formed sixth transistor to the first area of the active layer of the sixth transistor through the via.
  • the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the seventh transistor on the substrate, the first insulating layer and the second insulating layer in the eleventh via V11 are etched away to expose the surface of the second region of the active layer of the seventh transistor, and the eleventh via V11 is configured to connect the second electrode of the subsequently formed seventh transistor (which is also the second electrode of the first transistor) to the second region of the active layer of the seventh transistor through the via.
  • the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the eighth transistor on the substrate, the first insulating layer and the second insulating layer in the twelfth via V12 are etched away to expose the surface of the first area of the active layer of the eighth transistor, and the twelfth via V12 is configured to connect the first electrode of the subsequently formed eighth transistor (which is also the second electrode of the eleventh transistor and the first electrode of the twelfth transistor) to the first area of the active layer of the eighth transistor through the via.
  • the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the eighth transistor on the substrate, the first insulating layer and the second insulating layer in the thirteenth via V13 are etched away to expose the surface of the first region of the active layer of the eighth transistor, and the thirteenth via V13 is configured to connect the second electrode of the subsequently formed eighth transistor to the second region of the active layer of the eighth transistor through the via.
  • the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the ninth transistor on the substrate, the first insulating layer and the second insulating layer in the fourteenth via V14 are etched away to expose the surface of the first area of the active layer of the ninth transistor, and the fourteenth via V14 is configured to connect the first electrode of the subsequently formed ninth transistor to the first area of the active layer of the ninth transistor through the via.
  • the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the ninth transistor (also the second area of the active layer of the fourth transistor) on the substrate, the first insulating layer and the second insulating layer in the fifteenth via V15 are etched away to expose the surface of the second area of the active layer of the ninth transistor (also the second area of the active layer of the fourth transistor), and the fifteenth via V15 is configured to connect the second electrode of the subsequently formed ninth transistor (also the second electrode of the fourth transistor) to the second area of the active layer of the ninth transistor (also the second area of the active layer of the fourth transistor) through the via.
  • the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fourth transistor on the substrate, the first insulating layer and the second insulating layer in the sixteenth via V16 are etched away to expose the surface of the first area of the active layer of the fourth transistor, and the sixteenth via V16 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of the active layer of the fourth transistor through the via.
  • the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the eleventh transistor on the substrate, the first insulating layer and the second insulating layer in the seventeenth via V17 are etched away to expose the surface of the first area of the active layer of the eleventh transistor, and the seventeenth via V17 is configured to connect the first electrode of the subsequently formed eleventh transistor to the first area of the active layer of the eleventh transistor through the via.
  • the orthographic projection of the eighteenth via V18 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the eleventh transistor on the substrate, the first insulating layer and the second insulating layer in the eighteenth via V18 are etched away to expose the surface of the first region of the active layer of the eleventh transistor, and the eighteenth via V18 is configured to connect the second electrode of the subsequently formed eleventh transistor (which is also the first electrode of the eighth transistor and the first electrode of the twelfth transistor) to the second region of the active layer of the eleventh transistor through the via.
  • the orthographic projection of the nineteenth via V19 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the twelfth transistor on the substrate, the first insulating layer and the second insulating layer in the nineteenth via V19 are etched away to expose the surface of the first area of the active layer of the twelfth transistor, and the nineteenth via V19 is configured to connect the first electrode of the subsequently formed twelfth transistor (which is also the second electrode of the eleventh transistor and the first electrode of the eighth transistor) to the first area of the active layer of the twelfth transistor through the via.
  • the orthographic projection of the twentieth via V20 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the twelfth transistor on the substrate, the first insulating layer and the second insulating layer in the twentieth via V20 are etched away to expose the surface of the first region of the active layer of the twelfth transistor, and the twentieth via V20 is configured to connect the second electrode of the subsequently formed twelfth transistor to the second region of the active layer of the twelfth transistor through the via.
  • the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the active connection portion on the substrate, the first insulating layer and the second insulating layer in the twenty-first via V21 are etched away to expose the surface of the active connection portion, and the twenty-first via V21 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the third transistor) to the active connection portion through the via.
  • the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the control electrode of the first transistor (also the control electrode of the third transistor) on the substrate, the second insulating layer in the twenty-second via V22 is etched away to expose the surface of the control electrode of the first transistor (also the control electrode of the third transistor), and the twenty-second via V22 is configured to connect one of the subsequently formed first clock signal line and the second clock signal line and the first electrode of the second transistor to the control electrode of the first transistor (also the control electrode of the third transistor) through the via.
  • the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the control electrode of the second transistor on the substrate, the second insulating layer in the twenty-third via V23 is etched away to expose the surface of the control electrode of the second transistor, and the twenty-third via V23 is configured to connect the second electrode of the first transistor (also the first electrode of the seventh transistor) and the first electrode of the eighth transistor (also the second electrode of the eleventh transistor and the first electrode of the twelfth transistor) formed subsequently to the control electrode of the second transistor through the via.
  • the orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the control electrode of the fourth transistor (also the control electrode of the sixth transistor, the control electrode of the fourth transistor, and the first electrode plate of the fourth capacitor) on the substrate, the second insulating layer in the twenty-fourth via hole V24 is etched away to expose the surface of the control electrode of the fourth transistor (also the control electrode of the sixth transistor, the control electrode of the fourth transistor, and the first electrode plate of the fourth capacitor), and the twenty-fourth via hole V24 is configured to allow the second electrode of the second transistor (also the second electrode of the third transistor) to be formed subsequently to be
  • the control electrode of the fourth transistor (which is also the control electrode of the sixth transistor, the control electrode of the fourth transistor and the first plate of the fourth capacitor) is connected through the via.
  • the orthographic projection of the twenty-fifth via V25 on the substrate is located within the range of the orthographic projection of the control electrode of the fifth transistor (also the control electrode of the eleventh transistor and the first plate of the second capacitor) on the substrate, the second insulating layer in the twenty-fifth via V25 is etched away to expose the surface of the control electrode of the fifth transistor (also the control electrode of the eleventh transistor and the first plate of the second capacitor), and the twenty-fifth via V25 is configured to connect the second electrode of the subsequently formed eighth transistor to the control electrode of the fifth transistor (also the control electrode of the eleventh transistor and the first plate of the second capacitor) through the via.
  • the orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the control electrode of the seventh transistor on the substrate, the second insulating layer in the twenty-sixth via V26 is etched away to expose the surface of the control electrode of the seventh transistor, and the twenty-sixth via V26 is configured to connect the subsequently formed first clock signal line and another of the second clock signal lines and the first electrode of the fifth transistor to the control electrode of the seventh transistor through the via.
  • the orthographic projection of the twenty-seventh via V27 on the substrate is located within the range of the orthographic projection of the control electrode of the eighth transistor (also the control electrode of the twelfth transistor) on the substrate, the second insulating layer in the twenty-seventh via V27 is etched away to expose the surface of the control electrode of the eighth transistor (also the control electrode of the twelfth transistor), and the twenty-seventh via V27 is configured to connect a subsequently formed first second power line to the control electrode of the eighth transistor (also the control electrode of the twelfth transistor) through the via.
  • the orthographic projection of the twenty-eighth via V28 on the substrate is located within the range of the orthographic projection of the control electrode of the ninth transistor on the substrate, the second insulating layer in the twenty-eighth via V28 is etched away to expose the surface of the control electrode of the ninth transistor, and the twenty-eighth via V28 is configured to connect the second electrode of the subsequently formed twelfth transistor to the control electrode of the ninth transistor through the via.
  • the orthographic projection of the twenty-ninth via V29 on the substrate is within the range of the orthographic projection of the first connecting line on the substrate, the second insulating layer in the twenty-ninth via V29 is etched away to expose the surface of the first connecting line, and the twenty-ninth via V29 is configured to connect the second electrode of the fourth transistor of the shift register unit of the current level (also the second electrode of the fifth transistor) and the first electrode of the first transistor of the shift register unit of the next level to the first connecting line through the via.
  • the orthographic projection of the thirtieth via V30 on the substrate is located within the range of the orthographic projection of the second plate of the second capacitor on the substrate, the thirtieth via V30 exposes the surface of the second plate of the second capacitor, and the thirtieth via V30 is configured to connect the second electrode of the subsequently formed fourth transistor (also the second electrode of the fifth transistor) to the second plate of the second capacitor through the via.
  • the orthographic projection of the thirty-first via V31 on the substrate is located within the range of the orthographic projection of the second plate of the fourth capacitor on the substrate, the thirty-first via V31 exposes the surface of the second plate of the fourth capacitor, and the thirty-first via V31 is configured to connect a subsequently formed second second power line to the second plate of the fourth capacitor through the via.
  • the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the second connecting line on the substrate, the thirty-second via V32 exposes the surface of the second connecting line, and the thirty-second via V32 is configured to connect the first electrode of the subsequently formed sixth transistor and the first electrode of the fourth transistor to the second connecting line through the via.
  • the orthographic projection of the thirty-third via hole V33 on the substrate is located within the range of the orthographic projection of the third connection line on the substrate, the thirty-third via hole V33 exposes the surface of the third connection line, and the thirty-third via hole V33 is configured to allow the first electrode of the subsequently formed ninth transistor and the third clock signal line and the fourth clock signal line to be connected to each other. One of them is connected to the third connection line through the via hole.
  • the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the fourth connecting line on the substrate, the thirty-fourth via V34 exposes the surface of the fourth connecting line, and the thirty-fourth via V34 is configured to connect the second electrode of the subsequently formed ninth transistor (which is also the second electrode of the fourth transistor) to the fourth connecting line through the via.
  • FIGS. 44 to 47 forming a third conductive layer pattern, comprising: depositing a third metal film on the substrate on which the aforementioned pattern is formed, and patterning the third metal film by a patterning process to form a third metal layer pattern, as shown in FIGS. 44 to 47, wherein FIG. 44 is a schematic diagram of the third conductive layer pattern in FIG. 30, FIG. 45 is a schematic diagram of FIG. 30 after the third conductive layer pattern is formed, FIG. 46 is a schematic diagram of the third conductive layer pattern in FIG. 31, and FIG. 47 is a schematic diagram of FIG. 31 after the third conductive layer pattern is formed.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer pattern may include: an initial signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a first power line VGH, a second power line VGL1, and a first electrode T13 and a second electrode T14 of a first transistor located in at least one shift register unit to a first electrode T83 and a second electrode T83 of an eighth transistor, and a first electrode T113 and a second electrode 114 of an eleventh transistor.
  • the third conductive layer pattern may include: an initial signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a first power line VGH, two second power lines VGL1, and a first electrode T13 and a second electrode T14 of a first transistor to a first electrode T123 and a second electrode 124 of a twelfth transistor located in at least one shift register unit.
  • the second electrode T14 of the first transistor and the second electrode T74 of the seventh transistor are an integral structure.
  • the second electrode T24 of the second transistor and the second electrode T34 of the third transistor are an integral structure.
  • the second electrode T44 of the fourth transistor and the second electrode T54 of the fifth transistor are an integral structure.
  • the first power line VGH and the first electrode T63 of the sixth transistor are an integral structure.
  • the first second power line VGL1 and the first electrode T33 of the third transistor are an integral structure.
  • the second second power line VGL1 and the first electrode T103 of the fourth transistor are an integral structure.
  • the first electrode T83 of the eighth transistor and the second electrode T114 of the eleventh transistor are integrally structured.
  • the second power line VGL1 and the first electrode T33 of the third transistor are integrally structured.
  • the first electrode T83 of the eighth transistor, the second electrode T114 of the eleventh transistor, and the first electrode T123 of the twelfth transistor are an integrated structure.
  • the second electrode T94 of the ninth transistor and the second electrode T104 of the fourth transistor are an integrated structure.
  • the first second power line VGL1 and the first electrode T33 of the third transistor are an integrated structure.
  • the second second power line VGL1 and the first electrode T103 of the fourth transistor are an integrated structure.
  • the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, and the second power line VGL1 are sequentially arranged along a side close to the display area. Any one of the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, and the second power line VGL1 extends along the first direction D1.
  • the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, the first second power line VGL1, the third clock signal line CLK3, the fourth clock signal line CLK4, and the second second power line VGL1 are sequentially arranged along a side close to the display area. Any one of the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, the first second power line VGL1, the third clock signal line CLK3, the fourth clock signal line CLK4, and the second second power line VGL1 extends along the first direction D1.
  • the first electrode T13 of the first transistor may be in a square shape and extend in the first direction D1.
  • the first electrode T13 of the first transistor is connected to the first region of the active layer of the first transistor through a first via hole, and is connected to the first connection line of the shift register unit of the previous stage through the twenty-ninth via hole of the shift register unit of the previous stage.
  • the first electrode T13 of the first transistor is located between the first power line VGH and the second power line VGL1, and as shown in FIGS. 46 and 47 , the first electrode T13 of the first transistor is located between the first power line VGH and the first second power line VGL1.
  • the second electrode T14 of the first transistor may be in the shape of a “ ⁇ ” type.
  • the second electrode T14 of the first transistor (also the second electrode T74 of the seventh transistor) is connected to the second region of the active layer of the first transistor through the second via hole, to the second region of the active layer of the seventh transistor through the eleventh via hole V11, and to the control electrode of the second transistor through the twenty-third via hole.
  • the second electrode T14 of the first transistor (also the second electrode T74 of the seventh transistor) is located between the first power line VGH and the second power line VGL1.
  • the second electrode T14 of the first transistor (also the second electrode T74 of the seventh transistor) is located between the first power line VGH and the first second power line VGL1.
  • the first electrode T23 of the second transistor may be in the shape of a strip and extend along the first direction D1.
  • the first electrode T23 of the second transistor is connected to the first region of the active layer of the second transistor through the third via hole, and is connected to the control electrode of the first transistor (also the control electrode of the third transistor) through the twenty-second via hole.
  • the first electrode T23 of the second transistor is located between the first power line VGH and the second power line VGL1, and as shown in FIGS. 46 and 47 , the first electrode T23 of the second transistor is located between the first power line VGH and the first second power line VGL1.
  • the second electrode T24 of the second transistor (also the second electrode T34 of the third transistor) may be in the shape of a zigzag line and at least partially extend along the first direction D1. As shown in FIGS. 44 and 45, the second electrode T24 of the second transistor (also the second electrode T34 of the third transistor) is located between the first power line VGH and the second power line VGL1.
  • the second electrode T24 of the second transistor (also the second electrode T34 of the third transistor) is connected to the second region of the active layer of the second transistor through the fourth via hole, connected to the second region of the active layer of the third transistor through the sixth via hole, connected to the active connection portion through the twenty-first via hole, and connected to the control electrode of the fourth transistor (also the control electrode of the sixth transistor) through the twenty-fourth via hole.
  • the second electrode T24 of the second transistor (also the second electrode T34 of the third transistor) is located between the first power line VGH and the first second power line VGL1.
  • the second electrode T24 of the second transistor (which is also the second electrode T34 of the third transistor) is connected to the second area of the active layer of the second transistor through the fourth via, is connected to the second area of the active layer of the third transistor through the sixth via, is connected to the active connection part through the twenty-first via, and is connected to the control electrode of the fourth transistor (which is also the control electrode of the sixth transistor, the control electrode of the fourth transistor and the first electrode plate of the fourth capacitor) through the twenty-fourth via.
  • the first electrode T33 of the third transistor may be in the shape of a strip and extend along the second direction D2.
  • the first electrode T33 of the third transistor is connected to the first region of the active layer of the third transistor through a fifth via.
  • the first electrode T33 of the third transistor is located between the first power line VGH and the second power line VGL1.
  • the first electrode T33 of the third transistor is located between the first power line VGH and the first second power line VGL1.
  • the first electrode T43 of the fourth transistor may be in the shape of a strip and extend along the second direction D2.
  • the first electrode T43 of the fourth transistor is connected to the first region of the active layer of the fourth transistor through the seventh via hole, and is connected to the second connection line through the thirty-second via hole.
  • the first electrode T43 of the fourth transistor is located on the side of the second power line VGL1 close to the display area.
  • the first electrode T43 of the fourth transistor is located between the first second power line VGL1 and the third clock signal line CLK3.
  • the shape of the second electrode T44 of the fourth transistor may be The second electrode T44 of the fourth transistor (also the fifth transistor).
  • the second electrode T54 of the fourth transistor is connected to the second area of the active layer of the fourth transistor (also the second area of the active layer of the fifth transistor) through the eighth via hole, connected to the first connecting line through the twenty-ninth via hole, and connected to the second electrode plate of the second capacitor through the thirtieth via hole.
  • the second electrode T44 of the fourth transistor (also the second electrode T54 of the fifth transistor) is located on the side of the second power line VGL1 close to the display area. As shown in Figures 46 and 47, the second electrode T44 of the fourth transistor (also the second electrode T54 of the fifth transistor) is located between the first second power line VGL1 and the third clock signal line CLK3.
  • the first electrode T53 of the fifth transistor may be in the shape of a strip and extend along the second direction D2.
  • the first electrode T53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor through the ninth via hole, and is connected to the control electrode of the seventh transistor through the twenty-sixth via hole.
  • the first electrode T53 of the fifth transistor is located on the side of the second power line VGL1 close to the display area.
  • the first electrode T53 of the fifth transistor is located between the first second power line VGL1 and the third clock signal line CLK3.
  • the first electrode T63 of the sixth transistor may be in the shape of a strip and extend along the second direction D2.
  • the first electrode T63 of the sixth transistor is connected to the first region of the active layer of the sixth transistor through the tenth via hole and is connected to the second connection line through the thirty-second via hole.
  • the first electrode T63 of the sixth transistor is located between the first power line VGH and the second power line VGL1.
  • the first electrode T63 of the sixth transistor is located between the first power line VGH and the first second power line VGL1.
  • the first electrode T83 of the eighth transistor may be in an “L” shape.
  • the first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor) is located on a side of the second power line VGL1 close to the display area.
  • the first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor) is connected to the first region of the active layer of the eighth transistor through the twelfth via hole, and is connected to the second region of the active layer of the eleventh transistor through the eighteenth via hole, and is connected to the control electrode of the second transistor through the twenty-third via hole.
  • the first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor and the first electrode T123 of the twelfth transistor) may be in an "L" shape.
  • the first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor and the first electrode T123 of the twelfth transistor) is located between the first second power line VGL1 and the third clock signal line CLK3.
  • the first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor and the first electrode T123 of the twelfth transistor) is connected to the first region of the active layer of the eighth transistor through the twelfth via, and is connected to the second region of the active layer of the eleventh transistor through the eighteenth via, is connected to the first region of the active layer of the twelfth transistor through the nineteenth via, and is connected to the control electrode of the second transistor through the twenty-third via.
  • the second pole T84 of the eighth transistor may be in the shape of a strip and extend along the first direction D1.
  • the second pole T84 of the eighth transistor is connected to the second region of the active layer of the eighth transistor through the thirteenth via hole, and is connected to the control pole of the fifth transistor (also the control pole of the eleventh transistor and the first plate of the second capacitor) through the twenty-fifth via hole.
  • the second pole T84 of the eighth transistor is located on the side of the second power line VGL1 close to the display area.
  • the second pole T84 of the eighth transistor is located between the first second power line VGL1 and the third clock signal line CLK3.
  • the first electrode T93 of the ninth transistor may be in the shape of a “[”.
  • the first electrode T93 of the ninth transistor is located on a side of the second second power line VGL1 close to the display area.
  • the first electrode T93 of the ninth transistor is connected to the first region of the active layer of the ninth transistor through a fourteenth via hole, and is connected to the third connection line through a thirty-third via hole.
  • the shape of the first electrode T103 of the fourth transistor may be The first electrode T103 of the fourth transistor is located on the side of the second power line VGL1 close to the display area. The first electrode T103 of the fourth transistor is connected to the first area of the active layer of the fourth transistor through the sixteenth via hole.
  • the first electrode 94 of the ninth transistor may be in the shape of a comb, wherein the teeth of the comb are located on the side of the comb back away from the display area.
  • the first electrode 94 of the ninth transistor (also the second electrode T104 of the fourth transistor) is located on the side of the second second power line VGL1 close to the display area.
  • the first electrode 94 of the ninth transistor (also the second electrode T104 of the fourth transistor) is connected to the second region of the active layer of the ninth transistor (also the second region of the active layer of the fourth transistor) through the fifteenth via hole, and is connected to the fourth connection line through the thirty-fourth via hole.
  • the first electrode T113 of the eleventh transistor may be in the shape of a strip and extend along the first direction D1.
  • the first electrode T113 of the eleventh transistor is connected to the first region of the active layer of the eleventh transistor through the seventeenth via hole.
  • the first electrode T113 of the eleventh transistor is located on a side of the second power line VGL1 close to the display area.
  • the first electrode T113 of the eleventh transistor is located between the first second power line VGL1 and the third clock signal line CLK3.
  • the second electrode T124 of the twelfth transistor may be in a strip shape and extend along the second direction D2.
  • the second electrode T124 of the twelfth transistor is located between the first second power line VGL1 and the third clock signal line CLK3.
  • the second electrode T124 of the twelfth transistor is connected to the second region of the active layer of the twelfth transistor through the twentieth via hole, and is connected to the control electrode of the ninth transistor through the twenty-eighth via hole.
  • the control electrode of the first transistor (also the control electrode of the third transistor) is connected to one of the first clock signal line CLK1 and the second clock signal line CLK2 through the 22nd via hole.
  • FIG. 45 and FIG. 47 are described by taking the example that the control electrode of the first transistor (also the control electrode of the third transistor) is connected to the first clock signal line CLK1 through the 22nd via hole.
  • control electrode of the seventh transistor is connected to the first clock signal line CLK1 and the other of the second clock signal lines CLK2 through the 26th via hole.
  • Figures 45 and 47 are described by taking the example that the control electrode of the seventh transistor is connected to the second clock signal line CLK2 through the 26th via hole.
  • control electrode of the eighth transistor (also the control electrode of the twelfth transistor) is connected to the second power line VGL1 through the twenty-seventh via hole.
  • the control electrode of the eighth transistor (also the control electrode of the twelfth transistor) is connected to the first second power line VGL1 through a twenty-seventh via hole.
  • the second plate of the fourth capacitor is connected to the second second power line VGL1 through a thirty-first via hole.
  • the third connection line is connected to one of the third clock signal line CLK3 and the fourth clock signal line CLK4 through the 33rd via hole.
  • Figure 47 is an example of the third connection line being connected to the third clock signal line CLK3 through the 33rd via hole.
  • an orthographic projection of the second power line VGL1 on the substrate partially overlaps an orthographic projection of the fourth capacitor on the substrate.
  • FIGS. 48 and 49 a schematic diagram of the fourth insulating layer pattern after being formed in FIG. 30
  • FIG. 49 is a schematic diagram of the fourth insulating layer pattern after being formed in FIG. 31 .
  • the via hole pattern may include a thirty-fifth via hole V35 .
  • the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the first electrode of the eleventh transistor on the substrate, the thirty-fifth via V35 exposes the surface of the first electrode of the eleventh transistor, and the thirty-fifth via V35 is configured to connect a subsequently formed third power line to the first electrode of the eleventh transistor through the via.
  • FIGS. 50 to 52 forming a fourth conductive layer pattern, comprising: depositing a fourth metal film on the substrate on which the aforementioned pattern is formed, and patterning the fourth metal film by a patterning process to form a fourth metal layer pattern, as shown in FIGS. 50 to 52, wherein FIG. 50 is a schematic diagram of the fourth conductive layer pattern in FIGS. 30 and 31, FIG. 51 is a schematic diagram of FIG. 30 after the fourth conductive layer pattern is formed, and FIG. 52 is a schematic diagram of FIG. 31 after the fourth conductive layer pattern is formed.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer pattern may include a third power line VGL2 .
  • the third power line VGL2 may be in a linear shape and extend in the first direction D1.
  • the third power line VGL2 is connected to the first electrode of the eleventh transistor through the thirty-fifth via hole.
  • the orthographic projection of the third power line VGL2 on the substrate partially overlaps the orthographic projections of the fourth transistor and the fifth transistor on the substrate.
  • the orthographic projection of the third power line VGL2 on the substrate is located on a side of the orthographic projection of the second power line on the substrate close to the display area.
  • the orthographic projection of the third power line VGL2 on the substrate is located between the orthographic projection of the first second power line on the substrate and the orthographic projection of the third clock signal line on the substrate.
  • (8) forming a planar layer pattern comprising: depositing a fifth insulating film on a substrate having the aforementioned pattern, coating a second planar film, and patterning the fifth insulating film and the second planar film through a patterning process to form a fifth insulating layer pattern and a planar layer pattern covering the aforementioned pattern.
  • the drive structure layer is prepared on the substrate.
  • the drive structure layer may include a plurality of shift register units, and the drive structure layer may be arranged on the substrate.
  • the drive structure layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a flat layer sequentially arranged on the substrate.
  • the semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer, or may be a metal oxide layer.
  • the metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc.
  • the metal oxide layer may be a single layer, a double layer, or a multilayer.
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.
  • the planar layer may employ an organic material such as resin or the like.
  • a light emitting structure layer is prepared on the driving structure layer.
  • the preparation process of the light emitting structure layer may include the following operations.
  • an anode conductive film is deposited, and the anode conductive film is patterned by a patterning process to form an anode conductive layer pattern arranged on the flat layer; on the substrate formed with the aforementioned pattern, a pixel definition film is deposited, and the pixel definition film is patterned by a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern; on the substrate formed with the pixel definition layer pattern, an organic light-emitting material is coated, and the organic light-emitting material is patterned by a patterning process to form an organic structure layer pattern; on the substrate formed with the organic material layer pattern, a cathode conductive film is deposited, and the cathode conductive film is patterned by a patterning process to form a cathode conductive layer.
  • the subsequent preparation process may include: forming a packaging structure layer on the cathode conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.
  • the anode conductive layer includes at least a plurality of anode patterns.
  • the anode conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO/Ag/ITO.
  • the organic structure layer may include at least: an organic light emitting layer of a light emitting device.
  • the cathode conductive layer may include at least: cathodes of a plurality of light emitting devices.
  • the cathode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the above conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum and titanium.
  • the display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.
  • the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element may be “directly” “on” or “under” the other element, or there may be intermediate elements.

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Abstract

一种移位寄存器单元及其驱动方法、显示基板、显示装置，其中，移位寄存器单元包括：节点控制子电路被配置为在第一时钟信号端和第二时钟信号端的信号控制下，向第一节点提供信号输入端或者第一电源端的信号，向第二节点提供第二电源端或者第一时钟信号端的信号；下拉子电路被配置为向第一节点提供第三电源端的信号；输出子电路被配置为在第一节点、第二节点和第二电源端的信号的控制下，向第一信号输出端提供第一电源端或者第二时钟信号端的信号，第三电源端的信号的电压值的绝对值小于第二电源端的信号的电压值的绝对值。

Description

移位寄存器单元及其驱动方法、显示基板、显示装置
本申请要求于2023年6月13日提交中国专利局、申请号为202310701919.2、发明名称为“移位寄存器单元及其驱动方法、显示基板、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开涉及但不限于显示技术领域，具体涉及一种移位寄存器单元及其驱动方法、显示基板、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光元件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种移位寄存器单元，包括：节点控制子电路、输出子电路和下拉子电路；
所述节点控制子电路，分别与信号输入端、第一时钟信号端、第二时钟信号端、第一电源端、第二电源端、第一节点和第二节点电连接，被配置为在第一时钟信号端和第二时钟信号端的信号控制下，向第一节点提供信号输入端或者第一电源端的信号，向第二节点提供第二电源端或者第一时钟信号端的信号；
所述下拉子电路，分别与第一节点和第三电源端电连接，被配置为向第一节点提供第三电源端的信号；
所述输出子电路，分别与第二时钟信号端、第一电源端、第二电源端、第一信号输出端、第一节点和第二节点电连接，被配置为在第一节点、第二节点和第二电源端的信号的控制下，向第一信号输出端提供第一电源端或者第二时钟信号端的信号；
所述第三电源端的信号的电压值的绝对值小于所述第二电源端的信号的电压值的绝对值。
在示例性实施方式中，所述下拉子电路包括：第十一晶体管；
第十一晶体管的第一极与第三电源端电连接，第十一晶体管的第二极与第一节点电连接。
在示例性实施方式中，第十一晶体管的控制极与第一节点电连接。
在示例性实施方式中，所述节点控制子电路包括：第一晶体管、第二晶体管、第三晶体管、第六晶体管和第七晶体管；
第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端连 接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第一节点电连接，第二晶体管的第一极与第一时钟信号端连接，第二晶体管的第二极与第二节点电连接；
第三晶体管的控制极与第一时钟信号端电连接，第三晶体管的第一极与第二电源端连接，第三晶体管的第二极与第二节点电连接；
第六晶体管的控制极与第二节点电连接，第六晶体管的第一极与第一电源端连接，第六晶体管的第二极与第四节点电连接；
第七晶体管的控制极与第二时钟信号端电连接，第七晶体管的第一极与第四节点连接，第七晶体管的第二极与第一节点电连接。
在示例性实施方式中，所述输出子电路包括：第四晶体管、第五晶体管和第八晶体管；
第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第一电源端连接，第四晶体管的第二极与第一信号输出端电连接；
第五晶体管的控制极与第三节点电连接，第五晶体管的第一极与第二时钟信号端连接，第五晶体管的第二极与第一信号输出端电连接；
第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点连接，第八晶体管的第二极与第三节点电连接。
在示例性实施方式中，所述下拉子电路包括：第十一晶体管；
第十一晶体管控制极与第三节点电连接。
在示例性实施方式中，所述输出子电路还包括：第一电容和第二电容中的至少一个；
第一电容的第一极板与第二节点电连接，第一电容的第二极板与第一电源端电连接；
第二电容的第一极板与第三节点电连接，第二电容的第二极板与第一信号输出端电连接。
在示例性实施方式中，所述输出子电路，还分别与第三时钟信号端和第二信号输出端电连接，被配置为在第一节点和第二节点的信号的控制下，向第二信号输出端提供第二电源端或者第三时钟信号端的信号。
在示例性实施方式中，所述输出子电路包括：第四晶体管、第五晶体管、第八晶体管、第九晶体管和第十晶体管；
第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第一电源端连接，第四晶体管的第二极与第一信号输出端电连接；
第五晶体管的控制极与第三节点电连接，第五晶体管的第一极与第二时钟信号端连接，第五晶体管的第二极与第一信号输出端电连接；
第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点连接，第八晶体管的第二极与第三节点电连接；
第九晶体管的控制极与第一节点电连接，第九晶体管的第一极与第三时钟信号端连接，第九晶体管的第二极与第二信号输出端电连接；
第十晶体管的控制极与第二节点电连接，第十晶体管的第一极与第二电源端连接，第十晶体管的第二极与第二信号输出端电连接。
在示例性实施方式中，所述输出子电路还包括：第十二晶体管；所述第九晶体管的控制极通过第十二晶体管与第一节点电连接；
第十二晶体管的控制极与第二电源端电连接，第十二晶体管的第一极与第一节点电连接，第十二晶体管的第二极与第九晶体管的控制极电连接。
在示例性实施方式中，所述输出子电路还包括：第一电容、第二电容、第三电容和第四电容中的至少一个；
第一电容的第一极板与第二节点电连接，第一电容的第二极板与第一电源端电连接；
第二电容的第一极板与第三节点电连接，第二电容的第二极板与第一信号输出端电连接；
第三电容的第一极板与第九晶体管的控制极电连接，第三电容的第二极板与第二信号输出端连接；
第四电容的第一极板与第二节点电连接，第四电容的第二极板与第二电源端连接。
在示例性实施方式中，所述第三时钟信号端的信号与所述第二时钟信号端的信号互为反相信号。
在示例性实施方式中，还包括：输出控制子电路；
所述输出控制子电路，分别与第一电源端和第一信号输出端电连接，被配置为存储第一信号输出端和第一电源端的信号之间的电压差。
在示例性实施方式中，所述输出控制子电路包括：第五电容；
第五电容的第一极板与第一电源端电连接，第五电容的第二极与第一信号输出端电连接。
在示例性实施方式中，所述第一时钟信号端的信号和所述第二时钟信号端的信号不同时为有效电平信号。
第二方面，本公开还提供了一种显示基板，包括：基底以及设置在所述基底上的子像素、栅线和栅极驱动电路，所述基底设置有显示区和非显示区，所述栅极驱动电路位于所述非显示区，所述子像素和所述栅线位于所述显示区，所述栅线分别与所述子像素和所述栅极驱动电路电连接；
所述栅极驱动电路包括：多个级联的上述移位寄存器单元，其中，第i级移位寄存器单元的第一信号输出端与第i+1级移位寄存器单元的信号输入端连接，1≤i<N，N为移位寄存器单元的总级数。
在示例性实施方式中，所述移位寄存器单元的第一信号输出端与栅线电连接。
在示例性实施方式中，还包括：设置在基底上，且位于所述非显示区的初始信号线、第一时钟信号线、第二时钟信号线、第一电源线、第二电源线和第三电源线；
所述初始信号线、所述第一时钟信号线、所述第二时钟信号线、所述第一电源线、所述第二电源线和所述第三电源线中的任一条沿第一方向延伸，所述栅线沿第二方向延伸，所述第一方向与所述第二方向相交。
在示例性实施方式中，所述初始信号线、所述第一时钟信号线、所述第二时钟信号线和所述第一电源线沿靠近所述显示区的方向依次排布，且位于所述移位寄存器单元远离所述显示区的一侧。
在示例性实施方式中，所述移位寄存器单元包括：多个晶体管，所述第二电源线位于所述第一电源线靠近显示区的一侧，且位于移位寄存器单元的多个晶体管之间。
在示例性实施方式中，所述第三电源线位于所述第二电源线靠近所述显示区的一侧， 且在基底上的正投影与所述移位寄存器单元在基底上的正投影部分交叠。
在示例性实施方式中，所述移位寄存器单元包括：第一晶体管、第二晶体管、第三晶体管、第六晶体管和第七晶体管；
所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第六晶体管和所述第七晶体管中的任一个晶体管的至少部分位于所述第一电源线和所述第二电源线之间。
在示例性实施方式中，所述移位寄存器单元包括：第四晶体管、第五晶体管、第八晶体管、第十一晶体管和第十二晶体管，所述第二电源线的数量为至少一条；
所述第四晶体管、所述第五晶体管、所述第八晶体管、所述第十一晶体管和所述第十二晶体管中的任一晶体管的至少部分位于所述第二电源线靠近所述显示区的一侧。
在示例性实施方式中，所述移位寄存器单元包括：第二电容；
所述第二电容位于所述第三电源线靠近显示区的一侧。
在示例性实施方式中，还包括：设置在所述基底，且位于所述非显示区的第三时钟信号线和第四时钟信号线，所述第三时钟信号线和所述第四时钟信号线中的任一条沿第一方向延伸；
所述第二电源线的数量为两条，靠近所述显示区的所述第二电源线位于所述第三时钟信号线和所述第四时钟信号线中任一条靠近所述显示区的一侧，远离所述显示区的所述第二电源线位于所述第一电源线和所述第三电源线之间。
在示例性实施方式中，所述移位寄存器单元包括：第四晶体管、第五晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管和第四电容；
所述第四晶体管、所述第五晶体管、所述第八晶体管、第十一晶体管和第十二晶体管位于远离所述显示区的所述第二电源线和所述第三时钟信号线和所述第四时钟信号线中任一条之间，所述第九晶体管和所述第十晶体管位于靠近所述显示区的所述第二电源线靠近所述显示区的一侧；
靠近所述显示区的所述第二电源线在基底上的正投影与所述第四电容在基底上的正投影部分交叠。
在示例性实施方式中，第i级移位寄存器单元的第一时钟信号端与所述第一时钟信号线和所述第二时钟信号线中的其中一条电连接，第i级移位寄存器单元的第二时钟信号端与所述第一时钟信号线和所述第二时钟信号线中的另一条电连接；
相邻移位寄存器单元的第一时钟信号端连接的信号线不同，相邻移位寄存器单元的第二时钟信号端连接的信号线不同。
在示例性实施方式中，所述移位寄存器单元包括：第四晶体管和第五晶体管；
所述第三电源线在基底上的正投影与所述第四晶体管和所述第五晶体管在基底上的正投影部分交叠。
在示例性实施方式中，所述第八晶体管的有源层沿第二方向延伸，所述第八晶体管的第一极和第二极中的任一电极沿第一方向延伸，所述第八晶体管的栅电极至少部分沿第一方向延伸。
在示例性实施方式中，第十一晶体管的栅电极与第五晶体管的栅电极为一体结构，第十一晶体管的第一极在基底上的正投影与第三电源线在基底上的正投影部分交叠，且与第三电源线电连接，第十一晶体管的第二极与第八晶体管的第一极、第十二晶体管的第一极为一体结构。
在示例性实施方式中，所述第一电源线、所述第二电源线和所述第三电源线中的任一条沿第二方向的宽度小于所述第一时钟信号线、所述第二时钟信号线、所述第三时钟信号线和所述第四时钟信号线中任一条沿第二方向的宽度。
在示例性实施方式中，第i级移位寄存器单元的第三时钟信号端与所述第三时钟信号线和所述第四时钟信号线中的其中一条电连接，第i+1级移位寄存器单元的第三时钟信号端与所述第三时钟信号线和所述第四时钟信号线中的另一条电连接。
在示例性实施方式中，所述第十晶体管第九晶体管的有源层的沟道宽度大于所述第四晶体管的有源层的沟道宽度。
在示例性实施方式中，所述第十晶体管第九晶体管的有源层的沟道宽度不小于90微米。
在示例性实施方式中，所述第四晶体管的有源层的沟道宽度不大于50微米。
在示例性实施方式中，所述第九晶体管第十晶体管的有源层的沟道宽度大于所述第五晶体管的有源层的沟道宽度。
在示例性实施方式中，所述第九晶体管第十晶体管的有源层的沟道宽度不小于90微米。
在示例性实施方式中，所述第五晶体管的有源层的沟道宽度不大于50微米。
在示例性实施方式中，所述移位寄存器单元的第二信号输出端与栅线电连接。
第三方面，本公开还提供了一种显示装置，包括：上述显示基板。
第四方面，本公开还提供了一种移位寄存器单元的驱动方法，被配置为驱动上述移位寄存器单元，所述方法包括：
节点控制子电路在第一时钟信号端和第二时钟信号端的信号控制下，向第一节点提供信号输入端或者第一电源端的信号，向第二节点提供第二电源端或者第一时钟信号端的信号；
下拉子电路向第一节点提供第三电源端的信号；
输出子电路在第一节点和第二节点的信号的控制下，向第一信号输出端提供第一电源端或者第二时钟信号端的信号。
在示例性实施方式中，所述移位寄存器单元还包括：输出控制子电路；
所述方法还包括：输出子电路在第一节点和第二节点的信号的控制下，向第二信号输出端提供第二电源端或者第三时钟信号端的信号；
输出控制子电路存储第一信号输出端和第一电源端的信号之间的电压差。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为本公开实施例提供的移位寄存器单元的结构示意图一；
图2为一种下拉子电路的等效电路图；
图3为另一下拉子电路的等效电路图；
图4为节点控制子电路的等效电路图；
图5为输出子电路的等效电路图一；
图6为输出子电路的等效电路图；
图7为本公开实施例提供的移位寄存器单元的结构示意图二；
图8为输出子电路的等效电路图三；
图9为输出子电路的等效电路图四；
图10为本公开实施例提供的移位寄存器单元的结构示意图三；
图11为输出控制子电路的等效电路图；
图12为移位寄存器单元的等效电路图一；
图13为移位寄存器单元的等效电路图二；
图14为移位寄存器单元的等效电路图三；
图15为移位寄存器单元的等效电路图四；
图16为移位寄存器单元的等效电路图五；
图17为移位寄存器单元的等效电路图六；
图18为移位寄存器单元的等效电路图七；
图19为图12和图13提供的移位寄存器单元的信号时序仿真图；
图20为图14至图18提供的移位寄存器的信号时序仿真图；
图21为不同移位寄存器单元的第一节点和第二信号输出端的信号的对比图；
图22为一种显示装置的结构示意图；
图23为一种显示基板的平面结构示意图一；
图24为一种显示基板的平面结构示意图二；
图25为一种显示基板的平面示意图三；
图26A为一种像素驱动电路的等效电路示意图；
图26B为图26A提供的像素驱动电路的工作时序图；
图27A为另一像素驱动电路的等效电路示意图；
图27B为图27A提供的像素驱动电路的工作时序图；
图28为栅极驱动电路的级联示意图一；
图29为栅极驱动电路的级联示意图二；
图30为显示基板的结构示意图一；
图31为显示基板的结构示意图二；
图32为图30形成半导体层图案后的示意图；
图33为图31形成半导体层图案后的示意图；
图34为图30中的第一导电层图案的示意图；
图35为图30形成第一导电层图案后的示意图；
图36为图31中的第一导电层图案的示意图；
图37为图31形成第一导电层图案后的示意图；
图38为图30中的第二导电层图案的示意图；
图39为图30形成第二导电层图案后的示意图；
图40为图31中的第二导电层图案的示意图；
图41为图31形成第二导电层图案后的示意图；
图42为图30形成第三绝缘层图案后的示意图；
图43为图31形成第三绝缘层图案后的示意图；
图44为图30中的第三导电层图案的示意图；
图45为图30形成第三导电层图案后的示意图；
图46为图31中的第三导电层图案的示意图；
图47为图31形成第三导电层图案后的示意图；
图48为图30形成第四绝缘层图案后的示意图；
图49为图31形成第四绝缘层图案后的示意图；
图50为图30和图31中的第四导电层图案的示意图；
图51为图30形成第四导电层图案后的示意图；
图52为图31形成第四导电层图案后的示意图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
显示基板包括：像素驱动电路、发光元件和栅极驱动电路，其中，栅极驱动电路设置为向像素驱动电路中的晶体管提供栅极信号，以使得像素驱动电路可以驱动发光元件发光。显示基板中所用的是低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)技术，LTPS技术拥有高分辨率、高反应速度、高亮度、高开口率等优势。尽管受到了市场欢迎，但LTPS技术也存在一些缺陷，如生产成本较高，所需功耗较大等，此时，低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)技术方案应运而生。相比于LTPS技术，像素驱动电路中包括低温多晶硅晶体管，LTPO技术中像素驱动电路包括低温多晶硅晶体管和金属氧化物晶体管，金属氧化物晶体管漏电流更小，使得像素点反应更快，而显示基板多加了一层氧化物，可以降低激发像素点所需的能耗，从而降低屏幕显示时的功耗。采用LTPO技术的显示产品中包括一组驱动电路以对显示产品中的金属氧化物晶体管进行控制。随着显示基板的尺寸、分辨率和刷新频率的提升，像素驱动电路在一帧的补偿时间越来越短。更为甚者，显示基板中用于控制金属氧化物晶体管的驱动电路通常会由于部分节点电压不够低，使得控制金属氧化物晶体管的驱动电路的输出信号的电压无法达到预定电压，即控制金属氧化物晶体管的驱动电路的驱动能力较弱，进而导致金属氧化物晶 体管的导通程度较低，影响了像素驱动电路的性能，从而降低了显示基板的显示效果。
图1为本公开实施例提供的移位寄存器单元的结构示意图一。如图1所示，本公开实施例提供的移位寄存器单元可以包括：节点控制子电路、输出子电路和下拉子电路。
如图1所示，节点控制子电路，分别与信号输入端IN、第一时钟信号端CK1、第二时钟信号端CK2、第一电源端V1、第二电源端V2、第一节点N1和第二节点N2电连接，被配置为在第一时钟信号端CK1和第二时钟信号端CK2的信号控制下，向第一节点N1提供信号输入端IN或者第一电源端V1的信号，向第二节点N2提供第二电源端V2或者第一时钟信号端CK1的信号；下拉子电路，分别与第一节点N1和第三电源端V3电连接，被配置为向第一节点N1提供第三电源端V3的信号；输出子电路，分别与第二时钟信号端CK2、第一电源端V1、第二电源端V2、第一信号输出端OUT1、第一节点N1和第二节点N2电连接，被配置为在第二电源端V2、第一节点N1和第二节点N2的信号的控制下，向第一信号输出端OUT1提供第一电源端V1或者第二时钟信号端CK2的信号。
在示例性实施方式中，第一电源端V1持续提供高电平信号，第二电源端V2和第三电源端V3持续地提供低电平信号。
在示例性实施方式中，第三电源端V3的信号的电压值的绝对值小于第二电源端V2的信号的电压值的绝对值。示例性地，第二电源端V2所连接的信号线的宽度不同于第三电源端V3所连接的信号线的宽度。
在示例性实施方式中，第一时钟信号端CK1和第二时钟信号端CK2中的任一个信号端的信号可以为周期性脉冲信号。
在示例性实施方式中，信号输出端IN的信号为单次脉冲信号。
本公开实施例提供的移位寄存器单元包括：节点控制子电路、输出子电路和下拉子电路，其中，节点控制子电路，分别与信号输入端、第一时钟信号端、第二时钟信号端、第一电源端、第二电源端、第一节点和第二节点电连接，被配置为在第一时钟信号端和第二时钟信号端的信号控制下，向第一节点提供信号输入端或者第一电源端的信号，向第二节点提供第二电源端或者第一时钟信号端的信号；下拉子电路，分别与第一节点和第三电源端电连接，被配置为向第一节点提供第三电源端的信号；输出子电路，分别与第二时钟信号端、第一电源端、第一信号输出端、第一节点和第二节点电连接，被配置为在第一节点和第二节点的信号的控制下，向第一信号输出端提供第一电源端或者第二时钟信号端的信号，第三电源端的信号的电压值的绝对值小于第二电源端的信号的电压值的绝对值。本公开提供的移位寄存器单元通过设置下拉子电路，可以将第一节点的信号拉低至电压值较低的低电平信号，使得移位寄存器单元中的部分晶体管可以完全开启，进而使得移位寄存器单元的输出信号的电压可以达到预定电压，提升了移位寄存器单元的的驱动能力，可以保证像素驱动电路中的晶体管的导通能力，进而提升了像素驱动电路的性能和显示基板的显示效果。
在示例性实施方式中，图2为一种下拉子电路的等效电路图，图3为另一下拉子电路的等效电路图。如图2和图3所示，下拉子电路可以包括：第十一晶体管T11。其中，第十一晶体管T11的第一极与第三电源端V3电连接，第十一晶体管T11的第二极与第一节点N1电连接。
在示例性实施方式中，图4为节点控制子电路的等效电路图。如图4所示，节点控制子电路可以包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第六晶体管T6和第七晶体管T7。其中，第一晶体管T1的控制极与第一时钟信号端CK1电连接，第一晶体管T1的第一极与信号输入端IN连接，第一晶体管T1的第二极与第一节点N1电连接； 第二晶体管T2的控制极与第一节点N1电连接，第二晶体管T2的第一极与第一时钟信号端CK1连接，第二晶体管T2的第二极与第二节点N2电连接；第三晶体管T3的控制极与第一时钟信号端CK1电连接，第三晶体管T3的第一极与第二电源端V2连接，第三晶体管T3的第二极与第二节点N2电连接；第六晶体管T6的控制极与第二节点N2电连接，第六晶体管T6的第一极与第一电源端V1连接，第六晶体管T6的第二极与第四节点电连接；第七晶体管T7的控制极与第二时钟信号端CK2电连接，第七晶体管T7的第一极与第四节点连接，第七晶体管T7的第二极与第一节点N1电连接。
在示例性实施方式中，图5为输出子电路的等效电路图一。如图5所示，输出子电路可以包括：第四晶体管T4、第五晶体管T5和第八晶体管T8。其中，第四晶体管T4的控制极与第二节点N2电连接，第四晶体管T4的第一极与第一电源端V1连接，第四晶体管T4的第二极与第一信号输出端OUT1电连接；第五晶体管T5的控制极与第三节点N3电连接，第五晶体管T5的第一极与第二时钟信号端CK2连接，第五晶体管T5的第二极与第一信号输出端OUT1电连接；第八晶体管T8的控制极与第二电源端V2电连接，第八晶体管T8的第一极与第一节点N1连接，第八晶体管T8的第二极与第三节点N3电连接。
在示例性实施方式中，如图2所示，第十一晶体管T11的控制极可以与第一节点N1电连接。
在示例性实施方式中，如图3所示，第十一晶体管的控制可以与第三节点N3电连接。
在示例性实施方式中，图6为输出子电路的等效电路图二。如图6所示，输出子电路嗨可以包括：第一电容C1和第二电容C2中的至少一个。其中，第一电容C1的第一极板与第二节点N2电连接，第一电容C1的第二极板与第一电源端V1电连接；第二电容C2的第一极板与第三节点电连接，第二电容C2的第二极板与第一信号输出端OUT1电连接。图6是以输出子电路还包括第一电容C1和第二电容C2为例进行说明的。
在示例性实施方式中，图7为本公开实施例提供的移位寄存器单元的结构示意图二。如图7所示，输出子电路，分别与第二时钟信号端CK2、第一电源端V1、第一信号输出端OUT1、第一节点N1、第二节点N2、第三时钟信号端CK3、第二电源端V2和第二信号输出端OUT2电连接，被配置为在第一节点N1和第二节点N2的信号的控制下，向第一信号输出端OUT1提供第一电源端V1或者第二时钟信号端CK2的信号，向第二信号输出端OUT2提供第二电源端V2或者第三时钟信号端CK3的信号。
在示例性实施方式中，第一信号输出端OUT1和第二信号输出端OUT2的信号为单次脉冲信号，且第一信号输出端OUT1的信号和第二信号输出端OUT2的信号互为反相信号，即第一信号输出端OUT1的信号为高电平信号时，第二信号输出端OUT2的信号为低电平信号，第一信号输出端OUT1的信号为低电平信号时，第二信号输出端OUT2的信号为高电平信号。
在示例性实施方式中，第一信号输出端OUT1被配置为输出级联信号，级联信号为低电平信号，第二信号输出端OUT2被配置为输出栅极扫描信号。示例性地，栅极扫描信号为高电平信号，或者为低电平信号。
在示例性实施方式中，图8为输出子电路的等效电路图三。如图8所示，输出子电路可以包括：第四晶体管T4、第五晶体管T5、第八晶体管T8、第九晶体管T9和第十晶体管T10。其中，第四晶体管T4的控制极与第二节点N2电连接，第四晶体管T4的第一极与第一电源端V1连接，第四晶体管T4的第二极与第一信号输出端OUT1电连接；第五晶体管T5的控制极与第三节点N3电连接，第五晶体管T5的第一极与第二时钟信号端 CK2连接，第五晶体管T5的第二极与第一信号输出端OUT1电连接；第八晶体管T8的控制极与第二电源端V2电连接，第八晶体管T8的第一极与第一节点N1连接，第八晶体管T8的第二极与第三节点N3电连接；第九晶体管T9的控制极与第一节点N1电连接，第九晶体管T9的第一极与第三时钟信号端CK3连接，第九晶体管T9的第二极与第二信号输出端OUT2电连接；第十晶体管T10的控制极与第二节点N2电连接，第十晶体管T10的第一极与第二电源端V2连接，第十晶体管T10的第二极与第二信号输出端OUT2电连接。
在示例性实施方式中，图9为输出子电路的等效电路图四。如图9所示，输出子电路可以包括：第四晶体管T4、第五晶体管T5、第八晶体管T8、第九晶体管T9、第十晶体管T10和第十二晶体管T12，第九晶体管T9的控制极通过第十二晶体管T12与第一节点N1电连接。其中，第四晶体管T4的控制极与第二节点N2电连接，第四晶体管T4的第一极与第一电源端V1连接，第四晶体管T4的第二极与第一信号输出端OUT1电连接；第五晶体管T5的控制极与第三节点N3电连接，第五晶体管T5的第一极与第二时钟信号端CK2连接，第五晶体管T5的第二极与第一信号输出端OUT1电连接；第八晶体管T8的控制极与第二电源端V2电连接，第八晶体管T8的第一极与第一节点N1连接，第八晶体管T8的第二极与第三节点N3电连接；第九晶体管T9的控制极与第一节点N1电连接，第九晶体管T9的第一极与第三时钟信号端CK3连接，第九晶体管T9的第二极与第二信号输出端OUT2电连接；第十晶体管T10的控制极与第二节点N2电连接，第十晶体管T10的第一极与第二电源端V2连接，第十晶体管T10的第二极与第二信号输出端OUT2电连接，第十二晶体管T12的控制极与第二电源端V2电连接，第十二晶体管T12的第一极与第一节点N1电连接，第十二晶体管T12的第二极与第九晶体管T9的控制极电连接。
在示例性实施方式中，第十二晶体管T12为持续导通的晶体管，可以保证第九晶体管T9的控制极的信号稳定，避免移位寄存器单元输出信号出现较大的偏离，可以保证移位寄存器单元的输出信号的稳定性。
在示例性实施方式中，如图8和图9所示，输出子电路还可以包括：第一电容C1、第二电容C2、第三电容C3和第四电容C4中的至少一个。
在示例性实施方式中，如图8和图9所示，第一电容C1的第一极板与第二节点N2电连接，第一电容C1的第二极板与第一电源端V1电连接；第二电容C2的第一极板与第三节点N3电连接，第二电容C2的第二极板与第一信号输出端OUT1连接；第三电容C3的第一极板与第九晶体管T9的控制极电连接，第三电容C3的第二极板与第二信号输出端OUT2连接；第四电容C4的第一极板与第二节点N2电连接，第四电容C4的第二极板与第二电源端V2连接。
在示例性实施方式中，输出子电路可以包括：第二电容C2和第四电容C4，或者可以包括：第二电容C2，或者可以包括：第一电容C1和第三电容C3，或者可以包括：第三电容C3，或者可以包括：第一电容C1、第二电容C2、第三电容C3和第四电容C4。图8和图9是以输出子电路包括：第一电容C1、第二电容C2、第三电容C3和第四电容C4为例进行说明的。其中，第一电容C1可以保证第二节点N2的稳定性，第二电容C2可保证第三节点N3和第一信号输出端OUT1的信号之间的压差，第三电容可以保证第一节点N1和第二信号输出端OUT2的信号之间的压差，第四电容C4可以保证第二节点N2的信号的稳定性。
在示例性实施方式中，图10为本公开实施例提供的移位寄存器单元的结构示意图三。如图10所示，移位寄存器单元还可以包括：输出控制子电路。其中，输出控制子电路，分别与第一电源端V1和第一信号输出端OUT1电连接，被配置为存储第一信号输出端 OUT1和第一电源端V1的信号之间的电压差。图10中的移位寄存器单元的输出子电路可以与第二时钟信号端CK2、第一电源端V1、第一节点N1、第二节点N2和第一信号输出端OUT1电连接，或者可以与第二时钟信号端CK2、第三时钟信号线CK3、第一电源端V1、第二电源端V2、第一节点N1、第二节点N2、第一信号输出端OUT1和第二信号输出端OUT2电连接。
本公开中，由于第一信号输出端OUT1输出的信号为级联信号，即第一信号输出端OUT1所连接的信号线不会流经像素驱动电路所在的显示区域，即第一信号输出端OUT1所连接的信号线的负载较小，容易受到输出子电路中的部分晶体管的寄生电容的影响，从而导致第一信号输出端OUT1的信号存在波动。而本公开通过设置输出控制子电路可以使得第一信号输出端OUT1输出的信号比较稳定，提升了移位寄存器单元的性能。
在示例性实施方式中，图11为输出控制子电路的等效电路图。如图11所示，在示例性实施方式中，输出控制子电路包括：第五电容C5。其中，第五电容C5的第一极板与第一电源端V1电连接，第五电容C5的第二极与第一信号输出端OUT1电连接。
在示例性实施方式中，图10和图11中的虚线表示可以连接，或者可以不连接。
在示例性实施方式中，图12为移位寄存器单元的等效电路图一，图13为移位寄存器单元的等效电路图二。如图12和图13所示，移位寄存器单元还可以输出控制子电路，其中，节点控制子电路包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第六晶体管T6和第七晶体管T7，输出子电路包括：第四晶体管T4、第五晶体管T5、第八晶体管T8、以及第一电容C1和第二电容C2中的至少一个，下拉子电路包括：第十一晶体管T11，输出控制子电路包括：第五电容C5。其中，图12是以移位寄存器单元包括：第二电容C2，图13是以移位寄存器单元包括：第一电容C1和第二电容C2为例进行说明的。图12是以第十一晶体管的控制极与第三节点N3电连接为例进行说明的，图13是以第十一晶体管的控制极与第一节点N1电连接为例进行说明的。
在示例性实施方式中，如图12和图13所示，第一晶体管T1的控制极与第一时钟信号端CK1电连接，第一晶体管T1的第一极与信号输入端IN连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第一节点N1电连接，第二晶体管T2的第一极与第一时钟信号端CK1连接，第二晶体管T2的第二极与第二节点N2电连接；第三晶体管T3的控制极与第一时钟信号端CK1电连接，第三晶体管T3的第一极与第二电源端V2连接，第三晶体管T3的第二极与第二节点N2电连接；第四晶体管T4的控制极与第二节点N2电连接，第四晶体管T4的第一极与第一电源端V1连接，第四晶体管T4的第二极与第一信号输出端OUT1电连接；第五晶体管T5的控制极与第三节点N3电连接，第五晶体管T5的第一极与第二时钟信号端CK2连接，第五晶体管T5的第二极与第一信号输出端OUT1电连接；第六晶体管T6的控制极与第二节点N2电连接，第六晶体管T6的第一极与第一电源端V1连接，第六晶体管T6的第二极与第四节点电连接；第七晶体管T7的控制极与第二时钟信号端CK2电连接，第七晶体管T7的第一极与第四节点连接，第七晶体管T7的第二极与第一节点N1电连接；第八晶体管T8的控制极与第二电源端V2电连接，第八晶体管T8的第一极与第一节点N1连接，第八晶体管T8的第二极与第三节点N3电连接；第十一晶体管T11的控制极与第一节点N1或者第三节点N3电连接，第十一晶体管T11的第一极与第三电源端V3电连接，第十一晶体管T11的第二极与第一节点N1电连接；第一电容C1的第一极板与第二节点N2电连接，第一电容C1的第二极板与第一电源端V1电连接；第二电容C2的第一极板与第三节点N3电连接，第二电容C2的第二极板与第一信号输出端OUT1连接；第五电容C5的第一极板与第一电源端V1电连接，第五电容C5的第二极与第一信号输出端OUT1电连接。图12 是以第十一晶体管T11的控制极与第三节点N3电连接为例进行说明，图13是以第十一晶体管T11的控制极与第一节点N1电连接为例进行说明。
在示例性实施方式中，按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
在示例性实施方式中，第一晶体管T1至第八晶体管T8以及第十一晶体管T11可以均为P型晶体管。
在示例性实施方式中，图14为移位寄存器单元的等效电路图三，图15为移位寄存器单元的等效电路图四。如图14和图15所示，移位寄存器单元还包括：输出控制子电路，节点控制子电路包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第六晶体管T6和第七晶体管T7，输出子电路包括：第四晶体管T4、第五晶体管T5、第八晶体管T8、第九晶体管T9和第十晶体管T10以及第一电容C1、第二电容C2、第三电容C3、第四电容C4中的至少一个，下拉子电路包括：第十一晶体管T11，输出控制子电路包括：第五电容C5。图14和图15是以移位寄存器单元包括：第一电容C1、第二电容C2、第三电容C3和第四电容C4为例进行说明的。图14是以第十一晶体管的控制极与第三节点N3电连接为例进行说明的，图15是以第十一晶体管的控制极与第一节点N1电连接为例进行说明的。
在示例性实施方式中，如图14和图15所示，第一晶体管T1的控制极与第一时钟信号端CK1电连接，第一晶体管T1的第一极与信号输入端IN连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第一节点N1电连接，第二晶体管T2的第一极与第一时钟信号端CK1连接，第二晶体管T2的第二极与第二节点N2电连接；第三晶体管T3的控制极与第一时钟信号端CK1电连接，第三晶体管T3的第一极与第二电源端V2连接，第三晶体管T3的第二极与第二节点N2电连接；第四晶体管T4的控制极与第二节点N2电连接，第四晶体管T4的第一极与第一电源端V1连接，第四晶体管T4的第二极与第一信号输出端OUT1电连接；第五晶体管T5的控制极与第三节点N3电连接，第五晶体管T5的第一极与第二时钟信号端CK2连接，第五晶体管T5的第二极与第一信号输出端OUT1电连接；第六晶体管T6的控制极与第二节点N2电连接，第六晶体管T6的第一极与第一电源端V1连接，第六晶体管T6的第二极与第四节点电连接；第七晶体管T7的控制极与第二时钟信号端CK2电连接，第七晶体管T7的第一极与第四节点连接，第七晶体管T7的第二极与第一节点N1电连接；第八晶体管T8的控制极与第二电源端V2电连接，第八晶体管T8的第一极与第一节点N1连接，第八晶体管T8的第二极与第三节点N3电连接；第九晶体管T9的控制极与第一节点N1电连接，第九晶体管T9的第一极与第三时钟信号端CK3连接，第九晶体管T9的第二极与第二信号输出端OUT2电连接；第十晶体管T10的控制极与第二节点N2电连接，第十晶体管T10的第一极与第二电源端V2连接，第十晶体管T10的第二极与第二信号输出端OUT2电连接；第十一晶体管T11的控制极与第一节点N1或者第三节点N3电连接，第十一晶体管T11的第一极与第三电源端V3电连接，第十一晶体管T11的第二极与第一节点N1电连接；第一电容C1的第一极板与第二节点N2电连接，第一电容C1的第二极板与第一电源端V1电连接；第二电容C2的第一极板与第三节点N3电连接，第二电容C2的第二极板与第一信号输出端OUT1连接；第三电容C3的第一极板与第九晶体管T9的控制极电连接，第三电容C3的第二极板与第二信号输出端OUT2连接；第四电容C4的第一极板 与第二节点N2电连接，第四电容C4的第二极板与第二电源端V2连接；第五电容C5的第一极板与第一电源端V1电连接，第五电容C5的第二极与第一信号输出端OUT1电连接。图14是以第十一晶体管T11的控制极与第三节点N3电连接为例进行说明，图15是以第十一晶体管T11的控制极与第一节点N1电连接为例进行说明。
在示例性实施方式中，第一晶体管T1至第十一晶体管T11可以均为P型晶体管。
在示例性实施方式中，图16为移位寄存器单元的等效电路图五，图17为移位寄存器单元的等效电路图六，图18为移位寄存器单元的等效电路图七。如图16至图18所示，还包括：输出控制子电路，节点控制子电路包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第六晶体管T6和第七晶体管T7，输出子电路包括：第四晶体管T4、第五晶体管T5、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十二晶体管T12以及第一电容C1、第二电容C2、第三电容C3、第四电容C4中的至少一个，下拉子电路包括：第十一晶体管T11，输出控制子电路包括：第五电容C5。图16和图17是以移位寄存器单元包括：第一电容C1、第二电容C2、第三电容C3和第四电容C4为例进行说明的，图18是以移位寄存器单元包括：第二电容C2和第四电容C4为例进行说明的。图16和图18是以第十一晶体管T11的控制极与第三节点N3电连接为例进行说明的，图17是以第十一晶体管T11的控制极与第一节点N1电连接为例进行说明的。
在示例性实施方式中，如图16至图18所示，第一晶体管T1的控制极与第一时钟信号端CK1电连接，第一晶体管T1的第一极与信号输入端IN连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第一节点N1电连接，第二晶体管T2的第一极与第一时钟信号端CK1连接，第二晶体管T2的第二极与第二节点N2电连接；第三晶体管T3的控制极与第一时钟信号端CK1电连接，第三晶体管T3的第一极与第二电源端V2连接，第三晶体管T3的第二极与第二节点N2电连接；第四晶体管T4的控制极与第二节点N2电连接，第四晶体管T4的第一极与第一电源端V1连接，第四晶体管T4的第二极与第一信号输出端OUT1电连接；第五晶体管T5的控制极与第三节点N3电连接，第五晶体管T5的第一极与第二时钟信号端CK2连接，第五晶体管T5的第二极与第一信号输出端OUT1电连接；第六晶体管T6的控制极与第二节点N2电连接，第六晶体管T6的第一极与第一电源端V1连接，第六晶体管T6的第二极与第四节点电连接；第七晶体管T7的控制极与第二时钟信号端CK2电连接，第七晶体管T7的第一极与第四节点连接，第七晶体管T7的第二极与第一节点N1电连接；第八晶体管T8的控制极与第二电源端V2电连接，第八晶体管T8的第一极与第一节点N1连接，第八晶体管T8的第二极与第三节点N3电连接；第九晶体管T9的控制极与第十二晶体管T12的第二极电连接，第九晶体管T9的第一极与第三时钟信号端CK3连接，第九晶体管T9的第二极与第二信号输出端OUT2电连接；第十晶体管T10的控制极与第二节点N2电连接，第十晶体管T10的第一极与第二电源端V2连接，第十晶体管T10的第二极与第二信号输出端OUT2电连接；第十一晶体管T11的控制极与第一节点N1或者第三节点N3电连接，第十一晶体管T11的第一极与第三电源端V3电连接，第十一晶体管T11的第二极与第一节点N1电连接；第十二晶体管T12的控制极与第二电源线电连接，第十二晶体管T12的第一级与第一节点N1电连接；第一电容C1的第一极板与第二节点N2电连接，第一电容C1的第二极板与第一电源端VGH电连接；第二电容C2的第一极板与第三节点N3电连接，第二电容C2的第二极板与第一信号输出端OUT1连接；第三电容C3的第一极板与第九晶体管T9的控制极电连接，第三电容C3的第二极板与第二信号输出端OUT2连接；第四电容C4的第一极板与第二节点N2电连接，第四电容C4的第二极板与第二电源端V2连接；第五电容C5的第一极板与第一电源端V1电连接，第五电容C5的第二极与第一信号输出端OUT1电连接。
在示例性实施方式中，第一晶体管T1至第十一晶体管T11可以均为P型晶体管。
在示例性实施方式中，第一时钟信号端CK1的信号和第二时钟信号端CK2的信号不同时为有效电平信号。示例性地，第一时钟信号端CK1的信号位于有效电平信号时，第二时钟信号端CK2的信号为无效电平信号，第二时钟信号端CK2的信号位于有效电平信号时，第一时钟信号端CK1的信号为无效电平信号。
在示例性实施方式中，第三时钟信号端CK3的信号与第二时钟信号端CK2的信号可以互为反相信号，或者可以不互为反相信号。当第三时钟信号端CK3的信号与第二时钟信号端CK2的信号互为反相信号时，第三时钟信号端CK3的信号为有效电平信号时，第二时钟信号端CK2的信号为无效电平信号，第三时钟信号端CK3的信号为无效电平信号时，第二时钟信号端CK2的信号为有效电平信号。
在示例性实施方式中，第一信号输出端OUT1和第二信号输出端OUT2的信号互为反相信号。
图19为图12和图13提供的移位寄存器单元的信号时序仿真图。图19是以移位寄存器单元中的所有晶体管均为P型晶体管为例进行说明的。
在示例性实施方式中，对于图12和图13提供的移位寄存器单元，由于第八晶体管T8的控制极与第二电源端V2电连接，第八晶体管T8持续导通。
结合图12和图19所示，图12提供的控制移位寄存器单元的工作过程包括以下阶段：
在第一阶段S1，即输入阶段，信号输入端IN、第一时钟信号端CK1的信号为低电平信号，第二时钟信号端GCK2的信号为高电平信号。第一时钟信号端CK1的信号为低电平信号，第一晶体管T1和第三晶体管T3导通，信号输入端IN的低电平信号写入第一节点N1，第二电源端V2的低电平信号写入第二节点N2。由于第八晶体管T8持续导通，第三节点N3的信号与第一节点N1的信号均为低电平信号。第一节点N1的信号为低电平信号，第二晶体管T2导通，第一时钟信号端CK1的低电平信号写入第二节点N2，保证第二节点N2的信号持续为低电平信号。第二节点N2的信号为低电平信号，第四晶体管T4和第六晶体管T6导通，第一电源端V1的高电平信号写入第一信号输出端OUT1和第四节点N4，第二电源端V2的低电平信号写入第二信号输出端OUT2。第三节点N3的信号为低电平信号，第五晶体管T5和第十一晶体管T11导通，第三电源端V3的信号写入至第一节点N1，进一步拉低了第一节点N1的电平信号，使得第一节点N1的信号持续为低电平信号。由于第二时钟信号端CK2的信号为高电平信号，第七晶体管T7断开，第四节点N4的高电平信号不会写入至第一节点N1，第一节点N1的信号不会被拉高。本阶段，第一节点N1、第二节点N2和第三节点N3的信号为低电平信号，第四节点N4的信号为高电平信号，第一信号输出端OUT1写入第一电源端V1的信号，第一信号输出端OUT1的输出信号为高电平信号。
在第二阶段S2，即输出阶段，信号输入端IN、第一时钟信号端CK1的信号为高电平信号，第二时钟信号端GCK2的信号为低电平信号。第一时钟信号端CK1的信号为高电平信号，第一晶体管T1和第三晶体管T3断开，第一节点N1的信号保持低电平信号。由于第八晶体管T8持续导通，第三节点N3的信号与第一节点N1的信号均为低电平信号。第一节点N1的信号为低电平信号，第二晶体管T2导通，第一时钟信号端CK1的高电平信号写入第二节点N2，第二节点N2的信号为高电平信号，第二节点N2的信号为高电平信号，第四晶体管T4和第六晶体管T6断开，第一电源端V1的高电平信号无法写入第一信号输出端OUT1。第三节点N3的信号为低电平信号，第五晶体管T5和第十一晶体管T11导通，第三电源端V3的信号写入至第一节点N1，保持第一节点N1的信号持续为低 电平信号，第二时钟信号端CK2的低电平信号写入第一信号输出端OUT1。由于第二时钟信号端CK2的信号为低电平信号，第七晶体管T7导通，第四节点N4的信号被第一节点N1的信号被拉低，第四节点N4的信号为低电平信号。本阶段，第一节点N1、第三节点N3和第四节点N4的信号为低电平信号，第二节点N2的信号为高电平信号，第一信号输出端OUT1写入第二时钟信号端CK2的低电平信号，第一信号输出端OUT1的输出信号为低电平信号。
在第三阶段S3，信号输入端IN和第二时钟信号端GCK2信号为高电平信号，第一时钟信号端CK1的信号为低电平信号。第一时钟信号端CK1的信号为低电平信号，第一晶体管T1和第三晶体管T3导通，信号输入端IN的高电平信号写入第一节点N1，第二电源端V2的低电平信号写入第二节点N2。由于第八晶体管T8持续导通，第三节点N3的信号与第一节点N1的信号均为高电平信号。第一节点N1的信号为高电平信号，第二晶体管T2断开。第二节点N2的信号为低电平信号，第四晶体管T4和第六晶体管T6导通，第一电源端V1的高电平信号写入第一信号输出端OUT1和第四节点N4。第三节点N3的信号为高电平信号，第五晶体管T5和第十一晶体管T11断开，第三电源端V3的信号无法写入至第一节点N1，保持第一节点N1的信号为高电平信号，第二时钟信号端CK2的高电平信号无法写入第一信号输出端OUT1。由于第二时钟信号端CK2的信号为高电平信号，第七晶体管T7断开。本阶段，第二节点N2的信号为低电平信号，第一节点N1、第三节点N3和第四节点N4的信号为高电平信号，第一信号输出端OUT1写入第一电源端V1的信号，第一信号输出端OUT1的输出信号为高电平信号。
在第四阶段S4，信号输入端IN和第一时钟信号端CK1信号为高电平信号，第二时钟信号端CK2的信号为低电平信号。第一时钟信号端CK1的信号为高电平信号，第一晶体管T1和第三晶体管T3断开，第一节点N1的信号保持高电平信号。由于第八晶体管T8持续导通，第三节点N3的信号与第一节点N1的信号均为高电平信号。第一节点N1的信号为高电平信号，第二晶体管T2断开。第二节点N2的信号持续为低电平信号，第四晶体管T4和第六晶体管T6导通，第一电源端V1的高电平信号写入第一信号输出端OUT1和第四节点N4。第三节点N3的信号为高电平信号，第五晶体管T5和第十一晶体管T11断开，第三电源端V3的信号无法写入至第一节点N1，保持第一节点N1的信号为高电平信号，第二时钟信号端CK2的高电平信号无法写入第一信号输出端OUT1。由于第二时钟信号端CK2的信号为高电平信号，第七晶体管T7断开。本阶段，第二节点N2的信号为低电平信号，第一节点N1、第三节点N3和第四节点N4的信号为高电平信号，第一信号输出端OUT1写入第一电源端V1的信号，第一信号输出端OUT1的输出信号为高电平信号。
移位寄存器单元的工作过程还包括：多个第三阶段S3和第四阶段S4，第三阶段S3和第四阶段S4交替工作。
图13提供的移位寄存器单元与图12提供的移位寄存器单元不同之处在于第十一晶体管的控制极所连接的节点不同，图12是以第十一晶体管的控制极与第三节点连接为例进行说明，图13是以十一晶体管的控制极与第一节点连接，由于第一节点N1和第三节点N3的信号同时为高电平信号，或者同时为低电平信号，即图12和图13提供的移位寄存器单元中第十一晶体管同时导通，或者同时断开，因此，图13提供的移位寄存器单元的工作过程与图12提供的移位寄存器单元的工作相同。
图20为图14至图18提供的移位寄存器的信号时序仿真图。图20是以移位寄存器中的所有晶体管均为P型晶体管为例进行说明的。
在示例性实施方式中，对于图14和图15提供的移位寄存器单元，由于第八晶体管 T8的控制极与第二电源端V2电连接，第八晶体管T8持续导通。对于图16至图18提供的移位寄存器单元，第八晶体管T8和十二晶体管T12的控制极均与第二电源端V2电连接，第八晶体管T8和十二晶体管T12持续导通。
结合图14和图20所示，图14提供的控制移位寄存器单元的工作过程包括以下阶段：
在第一阶段S1，即输入阶段，信号输入端IN、第一时钟信号端CK1和第三时钟信号端CK3的信号为低电平信号，第二时钟信号端GCK2的信号为高电平信号。第一时钟信号端CK1的信号为低电平信号，第一晶体管T1和第三晶体管T3导通，信号输入端IN的低电平信号写入第一节点N1，第二电源端V2的低电平信号写入第二节点N2。由于第八晶体管T8持续导通，第三节点N3的信号与第一节点N1的信号均为低电平信号。第一节点N1的信号为低电平信号，第二晶体管T2和第九晶体管T9导通，第一时钟信号端CK1的低电平信号写入第二节点N2，保证第二节点N2的信号持续为低电平信号，第三时钟信号端CK3的低电平信号写入第二信号输出端OUT2。第二节点N2的信号为低电平信号，第四晶体管T4、第六晶体管T6和第十晶体管T10导通，第一电源端V1的高电平信号写入第一信号输出端OUT1和第四节点N4，第二电源端V2的低电平信号写入第二信号输出端OUT2。第三节点N3的信号为低电平信号，第五晶体管T5和第十一晶体管T11导通，第三电源端V3的信号写入至第一节点N1，进一步拉低了第一节点N1的电平信号，使得第一节点N1的信号持续为低电平信号。由于第二时钟信号端CK2的信号为高电平信号，第七晶体管T7断开，第四节点N4的高电平信号不会写入至第一节点N1，第一节点N1的信号不会被拉高。本阶段，第一节点N1、第二节点N2和第三节点N3的信号为低电平信号，第四节点N4的信号为高电平信号，第一信号输出端OUT1写入第一电源端V1的信号，第一信号输出端OUT1的输出信号为高电平信号，第二信号输出端OUT2写入第三时钟信号端CK3的信号和第二电源端V2的信号，第二信号输出端OUT2的输出信号为低电平信号。
在第二阶段S2，即输出阶段，信号输入端IN、第一时钟信号端CK1和第三时钟信号端CK3的信号为高电平信号，第二时钟信号端GCK2的信号为低电平信号。第一时钟信号端CK1的信号为高电平信号，第一晶体管T1和第三晶体管T3断开，第一节点N1的信号保持低电平信号。由于第八晶体管T8持续导通，第三节点N3的信号与第一节点N1的信号均为低电平信号。第一节点N1的信号为低电平信号，第二晶体管T2和第九晶体管T9导通，第一时钟信号端CK1的高电平信号写入第二节点N2，第二节点N2的信号为高电平信号，第三时钟信号端CK3的高电平信号写入第二信号输出端OUT2，第二节点N2的信号为高电平信号，第四晶体管T4、第六晶体管T6和第十晶体管T10断开，第一电源端V1的高电平信号无法写入第一信号输出端OUT1，第一低电平信号端VGL1的低电平信号无法写入第二信号输出端OUT2。第三节点N3的信号为低电平信号，第五晶体管T5和第十一晶体管T11导通，第三电源端V3的信号写入至第一节点N1，保持第一节点N1的信号持续为低电平信号，第二时钟信号端CK2的低电平信号写入第一信号输出端OUT1。由于第二时钟信号端CK2的信号为低电平信号，第七晶体管T7导通，第四节点N4的信号被第一节点N1的信号被拉低，第四节点N4的信号为低电平信号。本阶段，第一节点N1、第三节点N3和第四节点N4的信号为低电平信号，第二节点N2的信号为高电平信号，第一信号输出端OUT1写入第二时钟信号端CK2的低电平信号，第一信号输出端OUT1的输出信号为低电平信号，第二信号输出端OUT2写入第三时钟信号端CK3的信号，第二信号输出端OUT2的输出信号为高电平信号。
在第三阶段S3，信号输入端IN和第二时钟信号端GCK2信号为高电平信号，第一时钟信号端CK1和第三时钟信号端CK3的信号为低电平信号。第一时钟信号端CK1的信 号为低电平信号，第一晶体管T1和第三晶体管T3导通，信号输入端IN的高电平信号写入第一节点N1，第二电源端V2的低电平信号写入第二节点N2。由于第八晶体管T8持续导通，第三节点N3的信号与第一节点N1的信号均为高电平信号。第一节点N1的信号为高电平信号，第二晶体管T2和第九晶体管T9断开。第二节点N2的信号为低电平信号，第四晶体管T4、第六晶体管T6和第十晶体管T10导通，第一电源端V1的高电平信号写入第一信号输出端OUT1和第四节点N4，第二电源端V2的低电平信号写入第二信号输出端OUT2。第三节点N3的信号为高电平信号，第五晶体管T5和第十一晶体管T11断开，第三电源端V3的信号无法写入至第一节点N1，保持第一节点N1的信号为高电平信号，第二时钟信号端CK2的高电平信号无法写入第一信号输出端OUT1。由于第二时钟信号端CK2的信号为高电平信号，第七晶体管T7断开。本阶段，第二节点N2的信号为低电平信号，第一节点N1、第三节点N3和第四节点N4的信号为高电平信号，第一信号输出端OUT1写入第一电源端V1的信号，第一信号输出端OUT1的输出信号为高电平信号，第二信号输出端OUT2写入第二电源端V2的信号，第二信号输出端OUT2的输出信号为低电平信号。
在第四阶段S4，信号输入端IN、第一时钟信号端CK1和第三时钟信号端CK3的信号为高电平信号，第二时钟信号端CK2的信号为低电平信号。第一时钟信号端CK1的信号为高电平信号，第一晶体管T1和第三晶体管T3断开，第一节点N1的信号保持高电平信号。由于第八晶体管T8持续导通，第三节点N3的信号与第一节点N1的信号均为高电平信号。第一节点N1的信号为高电平信号，第二晶体管T2和第九晶体管T9断开，第三时钟信号端CK3的高电平信号无法写入第二输出信号端。第二节点N2的信号持续为低电平信号，第四晶体管T4、第六晶体管T6和第十晶体管T10导通，第一电源端V1的高电平信号写入第一信号输出端OUT1和第四节点N4，第二电源端V2的低电平信号写入第二信号输出端OUT2。第三节点N3的信号为高电平信号，第五晶体管T5和第十一晶体管T11断开，第三电源端V3的信号无法写入至第一节点N1，保持第一节点N1的信号为高电平信号，第二时钟信号端CK2的高电平信号无法写入第一信号输出端OUT1。由于第二时钟信号端CK2的信号为高电平信号，第七晶体管T7断开。本阶段，第二节点N2的信号为低电平信号，第一节点N1、第三节点N3和第四节点N4的信号为高电平信号，第一信号输出端OUT1写入第一电源端V1的信号，第一信号输出端OUT1的输出信号为高电平信号，第二信号输出端OUT2写入第二电源端V2的信号，第二信号输出端OUT2的输出信号为低电平信号。
移位寄存器单元的工作过程包括：多个第三阶段S3和第四阶段S4，第三阶段S3和第四阶段S4交替工作。
图15提供的移位寄存器单元与图14提供的移位寄存器单元不同之处在于第十一晶体管的控制极所连接的节点不同，图14是以第十一晶体管的控制极与第三节点连接为例进行说明，图15是以十一晶体管的控制极与第一节点连接，由于第一节点N1和第三节点N3的信号同时为高电平信号，或者同时为低电平信号，即图14和图15提供的移位寄存器单元中第十一晶体管同时导通，或者同时断开，因此，图15提供的移位寄存器单元的工作过程与图14提供的移位寄存器单元的工作相同。
图16提供的移位寄存器单元与图14提供的移位寄存器单元不同之处在于图16提供的移位寄存器单元还包括：第十二晶体管T12，由于第十二晶体管T12导通，因此，第二晶体管T12可以相当于一段导线，不会影响移位寄存器单元的其他晶体管的工作过程，因此，图16提供的移位寄存器单元的工作过程与图14提供的移位寄存器单元的工作相同。
图17和图18提供的移位寄存器单元与图15提供的移位寄存器单元不同之处在于图 17和图18提供的移位寄存器单元还包括：第十二晶体管T12，由于第十二晶体管T12导通，因此，第二晶体管T12可以相当于一段导线，不会影响移位寄存器单元的其他晶体管的工作过程，因此，图17和图18提供的移位寄存器单元的工作过程与图15提供的移位寄存器单元的工作相同。
本公开中的第十一晶体管T11的设置可以使得第一节点N1可以被拉低至电压值较低的第三电源端V3的信号，从而提升了第九晶体管T9的导通程度，使得第五晶体管T5和第九晶体管T9可以完全导通。
图21为不同移位寄存器单元的第一节点和第二信号输出端的信号的对比图。图21中N1-1和OUT2-1分别指的是本申请提供的图14至图18中任一个移位寄存器单元中的第一节点和第二信号输出端，N1-2和OUT2-2分别指的是晶体管仅包括第一晶体管至第十晶体管的移位寄存器单元中的第一节点和第二信号输出端。如图21所示，在输出阶段以及输出阶段的部分时间，N1-1的信号的电压值小于N1-2的信号的电压值，且OUT2-1的信号的上升沿持续时间小于OUT2-2的信号的上升沿持续时间，即本公开提供的移位寄存器单元可以提升第二信号输出端输出信号的电压值，提升了移位寄存器单元的性能。
本公开实施例还提供了一种移位寄存器单元的驱动方法，被配置为驱动移位寄存器单元，移位寄存器单元的驱动方法可以包括以下步骤：
步骤100、节点控制子电路在第一时钟信号端和第二时钟信号端的信号控制下，向第一节点提供信号输入端或者第一电源端的信号，向第二节点提供第二电源端或者第一时钟信号端的信号。
步骤200、下拉子电路向第一节点提供第三电源端的信号。
步骤300、输出子电路在第一节点和第二节点的信号的控制下，向第一信号输出端提供第一电源端或者第二时钟信号端的。
移位寄存器单元为前述任一个实施例提供的移位寄存器单元，实现原理和实现效果类似，在此不再赘述。
在示例性实施方式中，移位寄存器单元的驱动方法还可以包括：输出子电路在第一节点和第二节点的信号的控制下，向第二信号输出端提供第二电源端或者第三时钟信号端的信号。
在示例性实施方式中，移位寄存器单元还可以包括：输出控制子电路；移位寄存器单元的驱动方法还可以包括：输出控制子电路存储第一信号输出端和第一电源端的信号之间的电压差。
本公开实施例还提供了一种显示装置。图22为一种显示装置的结构示意图。如图22所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和显示基板。其中，显示基板包括：像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括像素驱动电路，像素驱动电路可以分别与扫描信号线、发光信号线和数据信号线连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据 电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器单元的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器单元的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
在示例性实施方式中，显示装置可以为液晶显示装置(Liquid Crystal Display，简称LCD)或有机发光二极管(Organic Light Emitting Diode，简称OLED)显示装置。该显示装置可以为：液晶面板、电子纸、OLED面板、有源矩阵有机发光二极管(active-matrix organic light emitting diode，简称AMOLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
图23为一种显示基板的平面结构示意图一，图24为一种显示基板的平面结构示意图二，图25为一种显示基板的平面结构示意图三。如图23至图25所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和至少一个出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，三个子像素可以采用水平并列、竖直并列或品字方式排列，本公开在此不做限定。
在示例性实施方式中，如图23和图25所示，一个像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字方式等排列，本公开在此不做限定。图23是以水平并列方式排列为例进行说明的，图25是以品字形排列为例进行说明的。
在示例性实施方式中，如图24所示，一个像素单元可以包括四个子像素，四个子像素可以为一个第一子像素、一个第二子像素和两个第三子像素。四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。图24是以四个子像素正方形方式排列为例进行说明的。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的一电极(阳极)、有机发光层和第二电极(阴极)。
在示例性实施方式中，有机发光层可以包括叠设的空穴注入层(Hole Injection Layer， 简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，显示基板为LTPO显示基板。
图26A为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图26A所示，像素驱动电路可以包括7个晶体管(第一晶体管M1到第七晶体管M7)和1个电容C。
如图26A所示，第一晶体管M1的栅电极与复位信号线Reset电连接，第一晶体管M1的第一极与第一初始信号线INIT1电连接，第一晶体管M1的第二极与第一节点N1电连接；第二晶体管M2的栅电极与第二扫描信号线Gate2电连接，第二晶体管M2的第一极与第一节点N1电连接，第二晶体管M2的第二极与第三节点N3电连接；第三晶体管M3的栅电极与第一节点N1电连接，第三晶体管M3的第一极与第二节点N2电连接，第三晶体管M3的第二极与第三节点N3电连接；第四晶体管M4的栅电极与第一扫描信号线Gate1电连接，第四晶体管M4的第一极与数据信号线Data电连接，第四晶体管M4的第二极与第二节点N2电连接；第五晶体管M5的栅电极与发光信号线EM电连接，第五晶体管M5的第一极与高电平电源线VDD电连接，第五晶体管M5的第二极与第二节点N2电连接；第六晶体管M6的栅电极与发光信号线EM电连接，第六晶体管M6的第一极与第三节点N3电连接，第六晶体管M6的第二极与第四节点N4电连接；第七晶体管M7的栅电极与第一扫描信号线Gate1电连接，第七晶体管M7的第一极与第二初始信号线INIT2电连接，第七晶体管M7的第二极与第四节点N4电连接；电容C的第一极板与第一节点N1电连接，电容C的第二极板与高电平电源线VDD电连接。
在示例性实施方式中，第一晶体管M1到第七晶体管M7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成LTPO显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，第一晶体管M1和第二晶体管M2与第三晶体管M3至第七晶体管M7的晶体管类型相反。示例性地，第一晶体管M1和第二晶体管M2可以为N型晶体管，第三晶体管M3至第七晶体管M7可以为P型晶体管。
在示例性实施方式中，第一晶体管M1和第二晶体管M2可以为氧化物晶体管，第三晶体管M3至第七晶体管M7可以为低温多晶硅晶体管。
在示例性实施方式中，第一初始信号线INIT1的信号的电压值恒定，且为直流信号，第一初始信号线INIT1的信号的电压值可以为-3V。
在示例性实施方式中，第二初始信号线INIT2的信号的电压值恒定，且为直流信号， 第二初始信号线INIT2的信号的电压值可以为0V。
在示例性实施方式中，发光器件L，可以分别与第四节点N4和低电平电源线VSS电连接。
在示例性实施方式中，高电平电源线VDD持续提供高电平信号，低电平电源线VSS持续提供低电平信号。
图26B为图26A提供的像素驱动电路的工作时序图。下面通过图26A示例的像素驱动电路在显示阶段的工作过程说明本公开示例性实施例。图26B是以第一晶体管M1和第二晶体管M2为N型晶体管，第三晶体管M3至第七晶体管M7为P型晶体管为例进行说明的，图26B中的像素驱动电路包括第一晶体管M1到第七晶体管M7、1个电容C和8个信号线(数据信号线Data、第一扫描信号线Gate1、第二扫描信号线Gate2、复位信号线Reset、第一初始信号线INIT1、第二初始信号线INIT2、发光信号线EM和高电平电源线VDD)。
结合图26A和图26B，像素驱动电路的工作过程可以包括：
第一阶段P1，称为初始化阶段，复位信号线Reset的信号为高电平信号，第一晶体管M1导通，第一初始信号线INIT1的信号通过导通的第一晶体管M1写入第一节点N1，对第一节点N1进行初始化(复位)，清空其内部的预存电压，完成初始化。
第二阶段P2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线Gate1为低电平信号，第二扫描信号线Gate2为低电平信号，数据信号线Data输出数据电压。此阶段由于第一节点N1为低电平信号，因此第三晶体管M3导通。第一扫描信号线Gate1的信号为低电平信号，第四晶体管M4导通和第七晶体管M7导通，第二扫描信号线Gate2的信号为高电平信号，第二晶体管M2导通，数据信号线Data输出的数据电压经过导通的第四晶体管M4、第二节点N2、导通的第三晶体管M3、第三节点N3、导通的第二晶体管M2提供至第一节点N1，并将数据信号线Data输出的数据电压与第三晶体管M3的阈值电压之差充入电容C，直至第一节点N1的电压为Vd-|Vth|，Vd为数据信号线Data输出的数据电压，Vth为第三晶体管M3的阈值电压，第七晶体管M7导通，第二初始信号线INIT2的信号通过导通的第七晶体管M7写入第四节点N4，对发光器件L的第一电极进行初始化(复位)，清空其内部的预存电压，完成初始化。
第三阶段P3，称为发光阶段，发光信号线EM的信号为低电平信号，第五晶体管M5和第六晶体管M6导通，高电平电源线VDD输出的电源电压通过导通的第五晶体管M5、第三晶体管M3和第六晶体管M6向发光器件L的第一极提供驱动电压，驱动发光器件L发光。
在像素驱动电路驱动过程中，流过第三晶体管M3(驱动晶体管)的驱动电流由栅电极和第一极之间的电压差决定。由于第一节点N1的电压为Vd-|Vth|，因而第三晶体管M3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*(Vdd-Vd)2
其中，I为流过第三晶体管M3的驱动电流，也就是驱动发光器件L的驱动电流，K为常数，Vgs为第三晶体管M3的栅电极和第一极之间的电压差，Vth为第三晶体管M3的阈值电压，Vd为数据信号线Data输出的数据电压，Vdd为高电平电源线VDD输出的电源电压。
在示例性实施方式中，图27A为另一像素驱动电路的等效电路示意图。如图27A所示，像素驱动电路可以包括8个晶体管(第一晶体管M1到第八晶体管M8)、1个电容 C和9个信号线(数据信号线Data、控制信号线Scan、扫描信号线Gate、复位信号线Reset、发光信号线EM、第一初始信号线INIT1、第二初始信号线INIT2、高电平电源线VDD和低电平电源线VSS)。
在示例性实施方式中，电容C的第一极板与高电平电源线VDD连接，电容C的第二极板与第一节点N1连接。第一晶体管M1的控制极与复位信号线Reset连接，第一晶体管M1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第四节点N4连接。第二晶体管M2的控制极与扫描信号线Gate连接，第二晶体管M2的第一极与第四节点N4连接，第二晶体管M2的第二极与第二节点N2连接。第三晶体管M3的控制极与第一节点N1连接，第三晶体管M3的第一极与第二节点N2连接，第三晶体管M3的第二极与第三节点N3连接。第四晶体管M4的控制极与扫描信号线Gate连接，第四晶体管M4的第一极与数据信号线Data连接，第四晶体管M4的第二极与第三节点N3连接。第五晶体管M5的控制极与发光信号线EM连接，第五晶体管M5的第一极与高电平电源线VDD连接，第五晶体管M5的第二极与第三节点N3连接。第六晶体管M6的控制极与发光信号线EM连接，第六晶体管M6的第一极与第二节点N2连接，第六晶体管M6的第二极与发光器件L的第一极连接。第七晶体管M7的控制极与复位信号线Reset连接，第七晶体管M7的第一极与第二初始信号线INIT2连接，第七晶体管M7的第二极与发光器件L的第一极连接，发光器件L的第二极与低电平电源线VSS连接。第八晶体管M8的控制极与控制信号线Scan连接，第八晶体管M8的第一极与第一节点N1连接，第八晶体管M8的第二极与第四节点N4连接。
在示例性实施方式中，第七晶体管M7的控制极还可以与扫描信号线Gate连接，第七晶体管M7的第一极与第二初始信号线INIT2连接，第七晶体管M7的第二极与发光器件L的第一极连接，发光器件L的第二极与低电平电源线VSS连接。
在示例性实施方式中，高电平电源线VDD的信号为持续提供高电平信号，低电平电源线VSS的信号为低电平信号。
在示例性实施方式中，第八晶体管M8为金属氧化物晶体管，且为N型晶体管，第一晶体管M1至第七晶体管M7为低温多晶硅晶体管，且为P型晶体管。
在示例性实施方式中，第八晶体管M8为氧化物晶体管可以减少漏电流，提升像素驱动电路的性能，可以降低像素驱动电路的功耗。
图27B为图27A提供的像素驱动电路的工作时序图。下面通过图27B示例的像素驱动电路的工作过程说明本公开示例性实施例。像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，控制信号线Scan、发光信号线EM和扫描信号线Gate的信号均为高电平信号，复位信号线Reset的信号为低电平信号。复位信号线Reset的信号为低电平信号，第一晶体管M1导通，第一初始信号线INIT1的信号提供至第四节点N4，第七晶体管M7导通，第二初始信号线INIT2的初始电压提供至发光器件L的第一极，对发光器件L的第一极进行初始化(复位)，例如：清空其内部的预存电压，完成初始化，确保发光器件L不发光。控制信号线Scan的信号为高电平信号，第八晶体管M8导通，第四节点N4的信号提供至第一节点N1，对电容C进行初始化，清除电容C中原有数据电压。扫描信号线Gate和发光信号线EM的信号为高电平信号，第二晶体管M2、第四晶体管M4、第五晶体管M5和第六晶体管M6第七晶体管M7截止，此阶段，发光器件L不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，扫描信号线Gate的信号为低电平信号，复位信号线Reset、发光信号线EM和控制信号线Scan的信号为高电平信号， 数据信号线Data输出数据电压。此阶段由于第一节点N1为低电平信号，因此第三晶体管M3导通。扫描信号线Gate的信号为低电平信号，第二晶体管M2和第四晶体管M4导通，控制信号线Scan的信号为高电平信号，第八晶体管M8导通。第二晶体管M2、第四晶体管M4和第八晶体管M8导通使得数据信号线Data输出的数据电压经过第三节点N3、导通的第三晶体管M3、第二节点N2、导通的第二晶体管M2、第四节点N4和导通的第八晶体管M8提供至第一节点N1，并将数据信号线Data输出的数据电压与第三晶体管M3的阈值电压之差充入电容C，直至第一节点N1的电压为Vd-|Vth|，Vd为数据信号线Data输出的数据电压，Vth为第三晶体管M3的阈值电压。复位信号线Reset的信号为低电平信号，第一晶体管M1和第七晶体管M7断开。发光信号线EM的信号为高电平信号，第五晶体管M5和第六晶体管M6断开。
第三阶段A3、称为发光阶段，控制信号线Scan和发光信号线EM的信号均为低电平信号，扫描信号线Gate和复位信号线Reset的信号为高电平信号。复位信号线Reset的信号为低电平信号，第一晶体管M1和第七晶体管M7截止。控制信号线Scan为低电平信号、扫描信号线Gate和复位信号线Reset的信号为高电平信号，第二晶体管M2、第四晶体管M4和第八晶体管M8截止。发光信号线EM的信号为低电平信号，第五晶体管M5和第六晶体管M6导通，高电平电源线VDD输出的电源电压通过导通的第五晶体管M5、第三晶体管M3和第六晶体管M6向发光器件L的第一极提供驱动电压，驱动发光器件L发光。
在像素驱动电路驱动过程中，流过第三晶体管M3(驱动晶体管)的驱动电流由控制极和第一极之间的电压差决定。由于第一节点N1的电压为Vd-|Vth|，因而第三晶体管M3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*(Vdd-Vd)2
其中，I为流过第三晶体管M3的驱动电流，也就是驱动发光器件L的驱动电流，K为常数，Vgs为第三晶体管M3的控制极和第一极之间的电压差，Vth为第三晶体管M3的阈值电压，Vd为数据信号线Data输出的数据电压，Vdd为高电平电源线VDD输出的电源电压。
本公开实施例提供的显示基板可以包括：基底以及设置在基底上的子像素、栅线和栅极驱动电路，基底设置有显示区和非显示区，栅极驱动电路位于非显示区，子像素和栅线位于显示区，栅线分别与子像素和栅极驱动电路电连接。
在示例性实施方式中，子像素包括：像素驱动电路和发光器件。当像素驱动电路为图26A提供的像素驱动电路时，栅线可以包括：复位信号线、第一扫描信号线、第二扫描信号线和发光信号线中的至少一种。
在示例性实施方式中，子像素包括：像素驱动电路和发光器件。当像素驱动电路为图27A提供的像素驱动电路时，栅线可以包括：复位信号线、第一扫描信号线、第二扫描信号线、控制信号线和发光信号线中的至少一种。
移位寄存器单元为前述任一个实施例提供的移位寄存器单元，实现原理和实现效果类似，在此不再赘述。
图28为栅极驱动电路的级联示意图一，图29为栅极驱动电路的级联示意图二。如图28和图29所示，第i级移位寄存器单元GOA(i)的第一信号输出端OUT1与第i+1级移位寄存器单元GOA(i+1)的信号输入端IN连接，1≤i<N，N为移位寄存器单元的总级数。其中，图28是以图12和图13提供的移位寄存器单元为例进行说明的，图29是以图14至图18提供的移位寄存器单元为例进行说明的。
在示例性实施方式中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、导电箔片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底的制备。
在示例性实施方式中，如图28所示，移位寄存器单元的第一信号输出端OUT1可以与栅线电连接。
在示例性实施方式中，如图29所示，移位寄存器单元的第二信号输出端OUT2可以与栅线电连接。
在示例性实施方式中，图30为显示基板的结构示意图一，图31为显示基板的结构示意图二。图30是以图12提供的移位寄存器单元为例进行说明的，图31是以图18提供的移位寄存器单元为例进行说明的。如图28至图31所示，显示基板还可以包括：设置在基底上，且位于非显示区的初始信号线STV、第一时钟信号线CLK1、第二时钟信号线CLK2、第一电源线VGH、第二电源线VGL1和第三电源线VGL2。
在示例性实施方式中，第一级移位寄存器单元GOA(1)的信号输入端IN与初始信号线STV电连接，第i级移位寄存器单元的第一电源端与第一电源线VGH电连接，第i级移位寄存器单元的第二电源端与第二电源线VGL1电连接，第i级移位寄存器单元的第三电源端与第三电源线VGL2电连接。
在示例性实施方式中，初始信号线STV、第一时钟信号线CLK1、第二时钟信号线CLK2、第一电源线VGH、第二电源线VGL1和第三电源线VGL2中的任一条沿第一方向D1延伸，栅线沿第二方向D2延伸，第一方向D1与第二方向D2相交。
在示例性实施方式中，如图30和图31所示，初始信号线STV、第一时钟信号线CLK1、第二时钟信号线CLK2和第一电源线VGH沿靠近显示区的方向依次排布，且位于移位寄存器单元远离显示区的一侧。
在示例性实施方式中，如图30和图31所示，移位寄存器单元包括：多个晶体管，第二电源线VGL1位于第一电源线VGH靠近显示区的一侧，且位于移位寄存器单元的多个晶体管之间。
在示例性实施方式中，如图30和图31所示，第三电源线VGL2位于第二电源线VGL1靠近显示区的一侧，且在基底上的正投影与移位寄存器单元在基底上的正投影部分交叠。
在示例性实施方式中，如图30和图31所示，移位寄存器单元包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第六晶体管T6和第七晶体管T7。其中，第一晶体管 T1、第二晶体管T2、第三晶体管T3、第六晶体管T6和第七晶体管T7中的任一个晶体管的至少部分位于第一电源线VGH和第二电源线VGL1之间。
在示例性实施方式中，如图31所示，移位寄存器单元包括：第四晶体管T4、第五晶体管T5、第八晶体管T8、第十一晶体管T11和第十二晶体管T12，第二电源线VGL1的数量为至少一条，其中，第四晶体管T4、第五晶体管T5、第八晶体管T8、第十一晶体管T11和第十二晶体管T12中的任一晶体管的至少部分位于第二电源线VGL1靠近显示区的一侧。
在示例性实施方式中，如图30和图31所示，移位寄存器单元包括：第二电容C2；第二电容C2位于第三电源线VGL2靠近显示区的一侧。
在示例性实施方式中，如图31所示，显示基板还可以包括：设置在基底，且位于非显示区的第三时钟信号线CLK3和第四时钟信号线CLK4，第三时钟信号线CLK3和第四时钟信号线CLK4中的任一条沿第一方向D1延伸。
在示例性实施方式中，如图31所示，第二电源线VGL1的数量为两条，靠近显示区的第二电源线VGL1位于第三时钟信号线CLK3和第四时钟信号线CLK4中任一条靠近显示区的一侧，远离显示区的第二电源线VGL1位于第一电源线VGH和第三电源线VGL2之间。
在示例性实施方式中，如图31所示，移位寄存器单元包括：第四晶体管T4、第五晶体管T5、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12和第四电容C4。其中，第四晶体管T4、第五晶体管T5、第八晶体管T8、第十一晶体管T11和第十二晶体管T12位于远离显示区的第二电源线VGL1和第三时钟信号线CLK3和第四时钟信号线CLK4中任一条之间，第九晶体管T9和第十晶体管T10位于靠近显示区的第二电源线VGL1靠近显示区的一侧。
在示例性实施方式中，如图31所示，靠近显示区的第二电源线VGL1在基底上的正投影与第四电容C 4在基底上的正投影部分交叠。
在示例性实施方式中，如图28至图31所示，第i级移位寄存器单元的第一时钟信号端CK1与第一时钟信号线CLK1和第二时钟信号线CLK2中的其中一条电连接，第i级移位寄存器单元的第二时钟信号端CK2与第一时钟信号线CLK1和第二时钟信号线CLK2中的另一条电连接；相邻移位寄存器单元的第一时钟信号端连接的信号线不同，相邻移位寄存器单元的第二时钟信号端连接的信号线不同。示例性地，示例性地，第奇数级移位寄存器单元的第一时钟信号端CK1可以与第一时钟信号线CLK1电连接，第奇数级移位寄存器单元的第二时钟信号端CK2可以与第二时钟信号线CLK2电连接，第偶数级移位寄存器单元的第一时钟信号端CK1可以与第二时钟信号线CLK2电连接，第偶数级移位寄存器单元的第二时钟信号端CK2可以与第一时钟信号线CLK1电连接，或者，第奇数级移位寄存器单元的第一时钟信号端CK1可以与第二时钟信号线CLK2电连接，第奇数级移位寄存器单元的第二时钟信号端CK2可以与第一时钟信号线CLK1电连接，第偶数级移位寄存器单元的第一时钟信号端CK1可以与第一时钟信号线CLK1电连接，第偶数级移位寄存器单元的第二时钟信号端CK2可以与第二时钟信号线CLK2电连接，图28和图29是以第奇数级移位寄存器单元的第一时钟信号端CK1可以与第一时钟信号线CLK1电连接，第奇数级移位寄存器单元的第二时钟信号端CK2可以与第二时钟信号线CLK2电连接，第偶数级移位寄存器单元的第一时钟信号端CK1可以与第二时钟信号线CLK2电连接，第偶数级移位寄存器单元的第二时钟信号端CK2可以与第一时钟信号线CLK1电连接为例进行说明的。
在示例性实施方式中，如图29和图31所示，第i级移位寄存器单元的第三时钟信号端CK3与第三时钟信号线CLK3和第四时钟信号线CLK4中的其中一条电连接，第i+1级移位寄存器单元的第三时钟信号端CK3与第三时钟信号线CLK3和第四时钟信号线CLK4中的另一条电连接。示例性地，第奇数级移位寄存器单元的第三时钟信号端CK3与第三时钟信号线CLK3电连接，第偶数级移位寄存器单元的第三时钟信号端CK3与第四时钟信号线CLK4电连接，或者，第奇数级移位寄存器单元的第三时钟信号端CK3与第四时钟信号线CLK4电连接，第偶数级移位寄存器单元的第三时钟信号端CK3与第三时钟信号线CLK3电连接。图29是以第奇数级移位寄存器单元的第三时钟信号端CK3与第三时钟信号线CLK3电连接，第偶数级移位寄存器单元的第三时钟信号端CK3与第四时钟信号线CLK4电连接为例进行说明的。
在示例性实施方式中，如图30和图31所示，第三电源线VGL2在基底上的正投影与第四晶体管T4和第五晶体管T5在基底上的正投影部分交叠。
在示例性实施方式中，如图30和图31所示，第八晶体管T8的有源层T81沿第二方向D2延伸，第八晶体管T8的第一极T83和第二极T84中的任一电极沿第一方向D1延伸，第八晶体管T8的栅电极T82至少部分沿第一方向D1延伸。
在示例性实施方式中，如图30和图31所示，第十一晶体管的栅电极T112与第五晶体管的栅电极T52为一体结构，第十一晶体管的第一极T113在基底上的正投影与第三电源线VGL2在基底上的正投影部分交叠，且与第三电源线VGL2电连接，第十一晶体管的第二极T114与第八晶体管的第一极T83、第十二晶体管的第一极T123为一体结构。
在示例性实施方式中，如图31所示，第一电源线VGH、第二电源线VGL1和第三电源线VGL2中的任一条沿第二方向D2的宽度小于第一时钟信号线CLK1、第二时钟信号线CLK2、第三时钟信号线CLK3和第四时钟信号线CLK4中任一条沿第二方向D2的宽度。
在示例性实施方式中，由于时钟信号线的信号为交流信号，第一时钟信号线CLK1、第二时钟信号线CLK2、第三时钟信号线CLK3和第四时钟信号线CLK4中任一条沿第二方向D2的宽度较宽可以降低时钟信号线的负载。
在示例性实施方式中，第十晶体管的有源层的沟道宽度大于第四晶体管的有源层的沟道宽度。
在示例性实施方式中，第十晶体管的有源层的沟道宽度不小于90微米。示例性地，第十晶体管的有源层的沟道宽度可以约为100微米。
在示例性实施方式中，第十晶体管的有源层的沟道长度可以约为3.5微米，第十晶体管的有源层的沟道宽长比可以约为100/3.5。
在示例性实施方式中，第四晶体管的有源层的沟道宽度不大于50微米。示例性地，第四晶体管的有源层的沟道宽度可以约为25微米。
在示例性实施方式中，第四晶体管的有源层的沟道长度可以约为3.5微米，第四晶体管的有源层的沟道宽长比可以约为25/3.5。
在示例性实施方式中，第九晶体管的有源层的沟道宽度大于第五晶体管的有源层的沟道宽度。
在示例性实施方式中，第九晶体管的有源层的沟道宽度不小于90微米。示例性地，第九晶体管的有源层的沟道宽度可以约为100微米。
在示例性实施方式中，第九晶体管的有源层的沟道长度可以约为3.5微米，第九晶体 管的有源层的沟道宽长比可以约为100/3.5。
在示例性实施方式中，第五晶体管的有源层的沟道宽度不大于50微米。示例性地，第五晶体管的有源层的沟道宽度可以约为25微米。
在示例性实施方式中，第五晶体管的有源层的沟道长度可以约为3.5微米，第五晶体管的有源层的沟道宽长比可以约为25/3.5。
在示例性实施方式中，显示基板还可以包括：设置在基底上的驱动结构层；驱动结构层包括：依次叠设在基底上的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；移位寄存器单元包括：多个晶体管和多个电容，任一个电容包括：第一极板和第二极板；
半导体层至少包括：位于至少一个移位寄存器单元的多个晶体管的有源层；
第一导电层至少包括：位于至少一个移位寄存器单元的多个晶体管的控制极以及多个电容的第一极板；
第二导电层至少包括：位于至少一个移位寄存器单元的多个电容的第二极板；
第三导电层至少包括：初始信号线、第一时钟信号线、第二时钟信号线、第一电源线、第二电源线、第三时钟信号线、第四时钟信号线以及位于至少一个移位寄存器单元的多个晶体管的第一极和第二极；
第四导电层至少包括：第三电源线。
在示例性实施方式中，驱动结构层还可以包括：第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层和平坦层，其中，第一绝缘层位于半导体层和第一导电层之间，第二绝缘层位于第一导电层和第二导电层之间，第三绝缘层位于第二导电层和第三导电层之间，第四绝缘层位于第三导电层和第四导电层之间，第五绝缘层位于第四导电层远离基底的一侧，平坦层位于第五绝缘层远离基底的一侧。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
(1)在基底上形成半导体层图案，包括：在基底上沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层图案。如图32和图33所示，图32为图30形成半导体层图案后的示意图，图33为图31形成半导体层图案后的示意图。
在示例性实施方式中，如图32所示，半导体层图案可以包括：位于至少一个移位寄存器单元的第一晶体管的有源层T11至第八晶体管的有源层T81、第十一晶体管的有源层T111以及有源连接块AL。
在示例性实施方式中，如图33所示，半导体层图案可以包括：位于至少一个移位寄存器单元的第一晶体管的有源层T11至第十二晶体管的有源层T121以及有源连接块AL。
在示例性实施方式中，如图32和图33所示，第四晶体管的有源层T41和第五晶体管的有源层T51为一体结构，第六晶体管的有源层T61和第七晶体管的有源层T71为一体结构。第一晶体管的有源层T11、第二晶体管的有源层T21、第三晶体管的有源层T31、第八晶体管的有源层T81、第十一晶体管的有源层T111和有源连接块AL可以单独设置。
在示例性实施方式中，如图33所示，第九晶体管的有源层T91和第四晶体管的有源层T101为一体结构，第十二晶体管的有源层T121可以单独设置。
在示例性实施方式中，如图32和图33所示，第一晶体管的有源层T11和第六晶体管的有源层T61(也是第七晶体管的有源层T71)沿第二方向D2排布，且本级移位寄存器单元的第一晶体管的有源层T11位于本级移位寄存器单元的第六晶体管的有源层T61(也是第七晶体管的有源层T71)靠近上一级移位寄存器单元的一侧。第二晶体管的有源层T21位于第一晶体管的有源层T11靠近靠近显示区的一侧。第三晶体管的有源层T31和有源连接块AL沿第二方向D2排布，且位于第二晶体管的有源层T21靠近显示区的一侧。第八晶体管的有源层T81、第十一晶体管的有源层T111和第四晶体管的有源层T41(也是第五晶体管有源层T51)沿第二方向D2依次排布，且位于第三晶体管的有源层T31靠近显示区的一侧，其中，本级移位寄存器单元的第十一晶体管的有源层T111位于本级移位寄存器单元的第八晶体管的有源层T81靠近下一级移位寄存器单元的一侧，本级移位寄存器单元的第四晶体管的有源层T41(也是第五晶体管有源层T51)位于本级移位寄存器单元的第十一晶体管的有源层T111靠近下一级移位寄存器单元的一侧。
在示例性实施方式中，如图33所示，本级移位寄存器单元的第十二晶体管的有源层T121位于本级移位寄存器单元的第八晶体管的有源层T81靠近上一级移位寄存器单元的一侧，本级移位寄存器单元的第九晶体管的有源层(也是第四晶体管的有源层)位于第四晶体管的有源层T41(也是第五晶体管有源层T51)靠近显示区的一侧。
在示例性实施方式中，如图32和图33所示，第一晶体管的有源层T11至第七晶体管的有源层T71的形状为条状，且沿第一方向D1延伸。第八晶体管的有源层T81和第十一晶体管的有源层T11的形状为条状，且沿第二方向D2延伸。有源连接块AL的形状可以为块状。
在示例性实施方式中，如图32和图33所示，第九晶体管的有源层(也是第四晶体管的有源层)的形状为条状，且沿第一方向D1延伸。第十二晶体管的有源层T121的形状为条状，且沿第二方向D2延伸。
在示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。其中，第一区和第二区在后续第一导电层形成后会被导体化，因此还可以被称为导电区。在示例性实施方式中，第六晶体管的有源层T61的第二区T61-2可以同时作为第七晶体管的有源层T31的第一区T71-2，第四晶体管的有源层T41的第二区T41-2可以同时作为第五晶体管的有源层T51的第二区T51-2，第九晶体管的有源层T91的第二区T91-2可以同时作为第四晶体管的有源层T101的第二区T101-2。第一晶体管的有源层T11的第一区T11-1和第二区T11-2、第二晶体管的有源层T21的第一区T21-1和第二区T21-2、第三晶体管的有源层T31的第一区T31-1和第二区T31-2、第四晶体管的有源层T41的第一区T41-1、第五晶体管的有源层T51的第一区T51-1、第六晶体管的有源层T61的第一区T61-1、第七晶体管的有源层T71的第二区T71-2、第八晶体管的有源层T81的第一区T81-1和第二区T81-2、第九晶体管的有源层T91的第一区T91-1、第 四晶体管的有源层T101的第一区T101-1、第十一晶体管的有源层T111的第一区T111-1和第二区T111-2和第十二晶体管的有源层T121的第一区T121-1和第二区T121-2可以单独设置。
(2)形成第一导电层图案，包括：在形成有前述图案的基底上沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一绝缘薄膜和第一导电薄膜进行图案化，形成第一绝缘层图案以及设置在第一绝缘层图案上的第一导电层图案，如图34至图37所示，图34为图30中的第一导电层图案的示意图，图35为图30形成第一导电层图案后的示意图，图36为图31中的第一导电层图案的示意图，图37为图31形成第一导电层图案后的示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，如图34和图35所示，第一导电层图案可以包括：位于至少一个移位寄存器单元的第一晶体管的控制极T12至第八晶体管的控制极T82、第十一晶体管的控制极T112、第二电容的第一极板C21以及第一连接线L1。
在示例性实施方式中，如图36和图37所示，第一导电层图案可以包括：位于至少一个移位寄存器单元的第一晶体管的控制极T12至第十二晶体管的控制极T122、第二电容的第一极板C21、第四电容的第一极板C41以及第一连接线L1。
在示例性实施方式中，如图34至图37所示，第一晶体管的控制极T12和第三晶体管的控制极T32为一体结构。第五晶体管的控制极T52、第十一晶体管的控制极T112和第二电容的第一极板C21为一体结构。第四晶体管的控制极T42、第六晶体管的控制极T62为一体结构。第二晶体管的控制极T22、第七晶体管的控制极T72、第八晶体管的控制极T82和第一连接线L1可以单独设置
在示例性实施方式中，如图36和图37所示，第四晶体管的控制极T42、第六晶体管的控制极T62、第四晶体管的控制极T102和第四电容的第一极板C41为一体结构。第八晶体管的控制极T82和第十二晶体管的控制极T122为一体结构。第九晶体管的控制极T92可以单独设置。
在示例性实施方式中，如图34至图37所示，第一晶体管的控制极T12包括：第一连接部T12A和第二连接部T12B，第一连接部T12A沿第一方向D1延伸，第二连接部T12B呈“┐”字型，第二连接部T12B与第一连接部T12A的中部连接。第三晶体管的控制极T32的形状可以为条状，且沿第二方向D2延伸。第三晶体管的控制极T32与第二连接部T12B的端部连接。
在示例性实施方式中，如图34至图37所示，第二电容的第一极板C21的形状可以为方形，第五晶体管的控制极T52的形状为条状，且沿第二方向D2延伸，第十一晶体管的控制极T112的形状为“┌”，第五晶体管的控制极T52和第十一晶体管的控制极T112位于第二电容的第一极板C21远离显示区的一侧。
在示例性实施方式中，如图34和图35所示，第四晶体管的控制极T42(也是第六晶体管的控制极T62)的形状为条状，且沿第二方向D2延伸。
在示例性实施方式中，如图36和图37所示，第四电容的第一极板C41的形状可以为方形，第四晶体管的控制极T102包括：多个第一分支段T102A，第一分支段T102A沿第二方向D2延伸，多个第一分支段T102A沿第一方向D1排布。第六晶体管的控制极T62和第四晶体管的控制极T42位于第四电容的第一极板C41远离显示区的一侧，第四晶体管的控制极T102位于第四电容的第一极板C41靠近显示区的一侧。图36和图37是以2个第一分支段T102A为例进行说明的。
在示例性实施方式中，如图34至图37所示，第八晶体管的控制极T82的形状可以 为开口向上的凹槽状。
在示例性实施方式中，如图36和图37所示，第十二晶体管的控制极T122的形状为条状，且沿第一方向D1延伸。
在示例性实施方式中，如图36和图37所示，第九晶体管的控制极T92包括：第二连接段T92A和多个第二分支段T92B。第二连接段T92A的形状呈“┐”字型，第二分支段T92B沿第二方向D2延伸，多个第二分支段T92B沿第一方向D1排布。第二连接段T92A相当于“梳背”，多个第二分支段T92B相当于“梳齿”。
在示例性实施方式中，如图34至图37所示，第二晶体管的控制极T22、第七晶体管的控制极T72和第一连接线L1的形状可以为条状，且至少部分沿第二方向D2延伸。
在示例性实施方式中，第一晶体管的控制极T12的第一连接段T12A和第二连接段T12B分别跨设在第一晶体管的有源层上，第二晶体管的控制极T22跨设在第二晶体管的有源层上，第三晶体管的控制极T32跨设在第三晶体管的有源层上，第四晶体管的控制极T42跨设在第四晶体管的有源层上，第五晶体管的控制极T52跨设在第五晶体管的有源层上，第六晶体管的控制极T62跨设在第六晶体管的有源层上，第七晶体管的控制极T72跨设在第七晶体管的有源层上，第八晶体管的控制极T82跨设在第八晶体管的有源层上，第九晶体管的控制极T92的多个第二分支段T92B跨设在第九晶体管的有源层上，第四晶体管的控制极T102的多个第一分支段T102A跨设在第四晶体管的有源层上，第十一晶体管的控制极T112跨设在第十一晶体管的有源层上，第十二晶体管的控制极T122跨设在第十二晶体管的有源层上，也就是说，至少一个晶体管的控制极的延伸方向与有源层的延伸方向相互垂直。
在示例性实施方式中，本次工艺还包括导体化处理。导体化处理是在形成第一导电层后，利用多个晶体管的控制极遮挡区域的半导体层(即半导体层与控制极交叠的区域)作为晶体管的沟道区域，未被第一导电层遮挡区域的半导体层被处理成导体化层，形成晶体管的电极连接部。如图24所示，本公开中的有源连接线AL被处理成导体化层，形成导体化的有源连接线AL，导体化后的第六晶体管的有源层的第二区(也是第七晶体管的有源层的第一区)可以复用为第六晶体管的第二极T64和第七晶体管的第一极T73。
(3)形成第二导电层图案，包括：在形成有前述图案的基底上，沉积第二绝缘薄膜和第二导电薄膜，通过图案化工艺对第二绝缘薄膜和第二导电薄膜进行图案化，形成第二绝缘层图案和位于第二绝缘层图案上的第二导电层图案，如图38至图41所示，图38为图30中的第二导电层图案的示意图，图39为图30形成第二导电层图案后的示意图，图40为图31中的第二导电层图案的示意图，图41为图31形成第二导电层图案后的示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，如图38和图39所示，第二导电层图案可以包括：位于至少一个移位寄存器单元的第二电容的第二极板C22和第二连接线L2。
在示例性实施方式中，如图40和图41所示，第二导电层图案可以包括：位于至少一个移位寄存器单元的第二电容的第二极板C22、第四电容的第二极板C42、第二连接线L2、第三连接线L3和第四连接线L4。
在示例性实施方式中，如图38至图41所示，第二电容的第二极板C22的形状为方形，且在基底上的正投影与第二电容的第一极板在基底上的正投影至少部分交叠。
在示例性实施方式中，如图40和图41所示，第四电容的第二极板C42的形状为方形，且在基底上的正投影与第四电容的的第一极板在基底上的正投影至少部分交叠。
在示例性实施方式中，如图38至图41所示，第二连接线L2的形状可以为条状，且至少部分沿第二方向D2延伸。
在示例性实施方式中，如图40和图41所示，第三连接线L3的形状可以为条状，且至少部分沿第二方向D2延伸。第四连接线L4的形状可以为条状，且至少部分沿第一方向D1延伸。
(4)形成第三绝缘层图案，包括：在形成有前述图案的基底上，沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜进行构图，形成覆盖前述结构的第三绝缘层图案，第三绝缘层开设有多个过孔图案，如图42和图43所示，图42为图30形成第三绝缘层图案后的示意图，图43为图31形成第三绝缘层图案后的示意图。
在示例性实施方式中，如图42所示，多个过孔图案可以包括：第一过孔V1至第十三过孔V13、第十七过孔V17、第十八过孔V18、第二十一过孔V21至第二十七过孔V27、第二十九过孔V29、第三十过孔V30和第三十二过孔V32。
在示例性实施方式中，如图43所示，多个过孔图案可以包括：第一过孔V1至第三十四过孔V34。
在示例性实施方式中，第一过孔V1在基底上的正投影位于第一晶体管的有源层的第一区在基底上的正投影的范围之内，第一过孔V1内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一晶体管的有源层的第一区的表面，第一过孔V1被配置为使后续形成的第一晶体管的第一极通过该过孔与第一晶体管的有源层的第一区连接。
在示例性实施方式中，第二过孔V2在基底上的正投影位于第一晶体管的有源层的第二区在基底上的正投影的范围之内，第二过孔V2内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一晶体管的有源层的第二区的表面，第二过孔V2被配置为使后续形成的第一晶体管的第二极(也是第七晶体管的第二极)通过该过孔与第一晶体管的有源层的第二区连接。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第二晶体管的有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第二晶体管的有源层的第一区的表面，第三过孔V3被配置为使后续形成的第二晶体管的第一极通过该过孔与第二晶体管的有源层的第一区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第二晶体管的有源层的第二区在基底上的正投影的范围之内，第四过孔V4内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第二晶体管的有源层的第二区的表面，第四过孔V4被配置为使后续形成的第二晶体管的第二极(也是第三晶体管的第二极)通过该过孔与第二晶体管的有源层的第二区连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第三晶体管的有源层的第一区在基底上的正投影的范围之内，第五过孔V5内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第三晶体管的有源层的第一区的表面，第五过孔V5被配置为使后续形成的第三晶体管的第一极通过该过孔与第三晶体管的有源层的第一区连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于第三晶体管的有源层的第二区在基底上的正投影的范围之内，第六过孔V6内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第三晶体管的有源层的第二区的表面，第六过孔V6被配置为使后续形成的第三晶体管的第二极(也是第二晶体管的第二极)通过该过孔与第三晶体管的有源层的第二区连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于第四晶体管的有源层的第一区在基底上的正投影的范围之内，第七过孔V7内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第四晶体管的有源层的第一区的表面，第七过孔V7被配置为使后续形成的第四晶体管的第一极通过该过孔与第四晶体管的有源层的第一区连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于第四晶体管的有源层的第二区(也是第五晶体管的有源层的第二区)在基底上的正投影的范围之内，第八过孔V8内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第四晶体管的有源层的第二区(也是第五晶体管的有源层的第二区)的表面，第八过孔V8被配置为使后续形成的第四晶体管的第二极(也是第五晶体管的第二极)通过该过孔与第四晶体管的有源层的第二区(也是第五晶体管的有源层的第二区)连接。
在示例性实施方式中，第九过孔V9在基底上的正投影位于第五晶体管的有源层的第一区在基底上的正投影的范围之内，第九过孔V9内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第五晶体管的有源层的第一区的表面，第九过孔V9被配置为使后续形成的第五晶体管的第一极通过该过孔与第五晶体管的有源层的第一区连接。
在示例性实施方式中，第十过孔V10在基底上的正投影位于第六晶体管的有源层的第一区在基底上的正投影的范围之内，第十过孔V10内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第六晶体管的有源层的第一区的表面，第十过孔V10被配置为使后续形成的第六晶体管的第一极通过该过孔与第六晶体管的有源层的第一区连接。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于第七晶体管的有源层的第二区在基底上的正投影的范围之内，第十一过孔V11内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第七晶体管的有源层的第二区的表面，第十一过孔V11被配置为使后续形成的第七晶体管的第二极(也是第一晶体管的第二极)通过该过孔与第七晶体管的有源层的第二区连接。
在示例性实施方式中，第十二过孔V12在基底上的正投影位于第八晶体管的有源层的第一区在基底上的正投影的范围之内，第十二过孔V12内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第八晶体管的有源层的第一区的表面，第十二过孔V12被配置为使后续形成的第八晶体管的第一极(也是第十一晶体管的第二极和第十二晶体管的第一极)通过该过孔与第八晶体管的有源层的第一区连接。
在示例性实施方式中，第十三过孔V13在基底上的正投影位于第八晶体管的有源层的第二区在基底上的正投影的范围之内，第十三过孔V13内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第八晶体管的有源层的第一区的表面，第十三过孔V13被配置为使后续形成的第八晶体管的第二极通过该过孔与第八晶体管的有源层的第二区连接。
在示例性实施方式中，第十四过孔V14在基底上的正投影位于第九晶体管的有源层的第一区在基底上的正投影的范围之内，第十四过孔V14内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第九晶体管的有源层的第一区的表面，第十四过孔V14被配置为使后续形成的第九晶体管的第一极通过该过孔与第九晶体管的有源层的第一区连接。
在示例性实施方式中，第十五过孔V15在基底上的正投影位于第九晶体管的有源层的第二区(也是第四晶体管的有源层的第二区)在基底上的正投影的范围之内，第十五过孔V15内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第九晶体管的有源层的第二区(也是第四晶体管的有源层的第二区)的表面，第十五过孔V15被配置为使后续形成的第九晶体管的第二极(也是第四晶体管的第二极)通过该过孔与第九晶体管的有源层的第二区(也是第四晶体管的有源层的第二区)连接。
在示例性实施方式中，第十六过孔V16在基底上的正投影位于第四晶体管的有源层的第一区在基底上的正投影的范围之内，第十六过孔V16内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第四晶体管的有源层的第一区的表面，第十六过孔V16被配置为使后续形成的第四晶体管的第一极通过该过孔与第四晶体管的有源层的第一区连接。
在示例性实施方式中，第十七过孔V17在基底上的正投影位于第十一晶体管的有源层的第一区在基底上的正投影的范围之内，第十七过孔V17内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第十一晶体管的有源层的第一区的表面，第十七过孔V17被配置为使后续形成的第十一晶体管的第一极通过该过孔与第十一晶体管的有源层的第一区连接。
在示例性实施方式中，第十八过孔V18在基底上的正投影位于第十一晶体管的有源层的第二区在基底上的正投影的范围之内，第第十八过孔V18内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第十一晶体管的有源层的第一区的表面，第十八过孔V18被配置为使后续形成的第十一晶体管的第二极(也是第八晶体管的第一极和第十二晶体管的第一极)通过该过孔与第十一晶体管的有源层的第二区连接。
在示例性实施方式中，第十九过孔V19在基底上的正投影位于第十二晶体管的有源层的第一区在基底上的正投影的范围之内，第十九过孔V19内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第十二晶体管的有源层的第一区的表面，第十九过孔V19被配置为使后续形成的第十二晶体管的第一极(也是第十一晶体管的第二极和第八晶体管的第一极)通过该过孔与第十二晶体管的有源层的第一区连接。
在示例性实施方式中，第二十过孔V20在基底上的正投影位于第十二晶体管的有源层的第二区在基底上的正投影的范围之内，第二十过孔V20内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第十二晶体管的有源层的第一区的表面，第二十过孔V20被配置为使后续形成的第十二晶体管的第二极通过该过孔与第十二晶体管的有源层的第二区连接。
在示例性实施方式中，第二十一过孔V21在基底上的正投影位于有源连接部在基底上的正投影的范围之内，第二十一过孔V21内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出有源连接部的表面，第二十一过孔V21被配置为使后续形成的第二晶体管的第二极(也是第三晶体管的第二极)通过该过孔与有源连接部连接。
在示例性实施方式中，第二十二过孔V22在基底上的正投影位于第一晶体管的控制极(也是第三晶体管的控制极)在基底上的正投影的范围之内，第二十二过孔V22内的第二绝缘层被刻蚀掉，暴露出第一晶体管的控制极(也是第三晶体管的控制极)的表面，第二十二过孔V22被配置为使后续形成的第一时钟信号线和第二时钟信号线中的其中一条和第二晶体管的第一极通过该过孔与第一晶体管的控制极(也是第三晶体管的控制极)连接。
在示例性实施方式中，第二十三过孔V23在基底上的正投影位于第二晶体管的控制极在基底上的正投影的范围之内，第二十三过孔V23内的第二绝缘层被刻蚀掉，暴露出第二晶体管的控制极的表面，第二十三过孔V23被配置为使后续形成的第一晶体管的第二极(也是第七晶体管的第一极)和第八晶体管的第一极(也是第十一晶体管的第二极和第十二晶体管的第一极)通过该过孔与第二晶体管的控制极连接。
在示例性实施方式中，第二十四过孔V24在基底上的正投影位于第四晶体管的控制极(也是第六晶体管的控制极、第四晶体管的控制极和第四电容的第一极板)在基底上的正投影的范围之内，第二十四过孔V24内的第二绝缘层被刻蚀掉，暴露出第四晶体管的控制极(也是第六晶体管的控制极、第四晶体管的控制极和第四电容的第一极板)的表面，第二十四过孔V24被配置为使后续形成的第二晶体管的第二极(也是第三晶体管的第二 极)通过该过孔与第四晶体管的控制极(也是第六晶体管的控制极、第四晶体管的控制极和第四电容的第一极板)连接。
在示例性实施方式中，第二十五过孔V25在基底上的正投影位于第五晶体管的控制极(也是第十一晶体管的控制极和第二电容的第一极板)在基底上的正投影的范围之内，第二十五过孔V25内的第二绝缘层被刻蚀掉，暴露出第五晶体管的控制极(也是第十一晶体管的控制极和第二电容的第一极板)的表面，第二十五过孔V25被配置为使后续形成的第八晶体管的第二极通过该过孔与第五晶体管的控制极(也是第十一晶体管的控制极和第二电容的第一极板)连接。
在示例性实施方式中，第二十六过孔V26在基底上的正投影位于第七晶体管的控制极在基底上的正投影的范围之内，第二十六过孔V26内的第二绝缘层被刻蚀掉，暴露出第七晶体管的控制极的表面，第二十六过孔V26被配置为使后续形成的第一时钟信号线和第二时钟信号线的另一条和第五晶体管的第一极通过该过孔与第七晶体管的控制极连接。
在示例性实施方式中，第二十七过孔V27在基底上的正投影位于第八晶体管的控制极(也是第十二晶体管的控制极)在基底上的正投影的范围之内，第二十七过孔V27内的第二绝缘层被刻蚀掉，暴露出第八晶体管的控制极(也是第十二晶体管的控制极)的表面，第二十七过孔V27被配置为使后续形成的第一条第二电源线通过该过孔与第八晶体管的控制极(也是第十二晶体管的控制极)连接。
在示例性实施方式中，第二十八过孔V28在基底上的正投影位于第九晶体管的控制极在基底上的正投影的范围之内，第二十八过孔V28内的第二绝缘层被刻蚀掉，暴露出第九晶体管的控制极的表面，第二十八过孔V28被配置为使后续形成的第十二晶体管的第二极通过该过孔与第九晶体管的控制极连接。
在示例性实施方式中，第二十九过孔V29在基底上的正投影位于第一连接线在基底上的正投影的范围之内，第二十九过孔V29内的第二绝缘层被刻蚀掉，暴露出第一连接线的表面，第二十九过孔V29被配置为使后续形成的本级移位寄存器单元的第四晶体管的第二极(也是第五晶体管的第二极)和下一级移位寄存器单元的第一晶体管的第一极通过该过孔与第一连接线连接。
在示例性实施方式中，第三十过孔V30在基底上的正投影位于第二电容的第二极板在基底上的正投影的范围之内，第三十过孔V30暴露出第二电容的第二极板的表面，第三十过孔V30被配置为使后续形成的第四晶体管的第二极(也是第五晶体管的第二极)通过该过孔与第二电容的第二极板连接。
在示例性实施方式中，第三十一过孔V31在基底上的正投影位于第四电容的第二极板在基底上的正投影的范围之内，第三十一过孔V31暴露出第四电容的第二极板的表面，第三十一过孔V31被配置为使后续形成的第二条第二电源线通过该过孔与第四电容的第二极板连接。
在示例性实施方式中，第三十二过孔V32在基底上的正投影位于第二连接线在基底上的正投影的范围之内，第三十二过孔V32暴露出第二连接线的表面，第三十二过孔V32被配置为使后续形成的第六晶体管的第一极和第四晶体管的第一极通过该过孔与第二连接线连接。
在示例性实施方式中，第三十三过孔V33在基底上的正投影位于第三连接线在基底上的正投影的范围之内，第三十三过孔V33暴露出第三连接线的表面，第三十三过孔V33被配置为使后续形成的第九晶体管的第一极以及第三时钟信号线和第四时钟信号线中的 其中一条通过该过孔与第三连接线连接。
在示例性实施方式中，第三十四过孔V34在基底上的正投影位于第四连接线在基底上的正投影的范围之内，第三十四过孔V34暴露出第四连接线的表面，第三十四过孔V34被配置为使后续形成的第九晶体管的第二极(也是第四晶体管的第二极)通过该过孔与第四连接线连接。
(5)形成第三导电层图案，包括：在形成前述图案的基底上，沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行构图，形成第三金属层图案，如图44至图47所示，图44为图30中的第三导电层图案的示意图，图45为图30形成第三导电层图案后的示意图，图46为图31中的第三导电层图案的示意图，图47为图31形成第三导电层图案后的示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，如图44和图45所示，第三导电层图案可以包括：初始信号线STV、第一时钟信号线CLK1、第二时钟信号线CLK2、第一电源线VGH、第二电源线VGL1以及位于至少一个移位寄存器单元的第一晶体管的第一极T13和第二极T14至第八晶体管的第一极T83和第二极T83、第十一晶体管的第一极T113和第二极114。
在示例性实施方式中，如图46和图47所示，第三导电层图案可以包括：初始信号线STV、第一时钟信号线CLK1、第二时钟信号线CLK2、第三时钟信号线CLK3、第四时钟信号线CLK4、第一电源线VGH、两条第二电源线VGL1以及位于至少一个移位寄存器单元的第一晶体管的第一极T13和第二极T14至第十二晶体管的第一极T123和第二极124。
在示例性实施方式中，如图44至图47所示，第一晶体管的第二极T14和第七晶体管的第二极T74为一体结构。第二晶体管的第二极T24和第三晶体管的第二极T34为一体结构。第四晶体管的第二极T44和第五晶体管的第二极T54为一体结构。第一电源线VGH与第六晶体管的第一极T63为一体结构。第一条第二电源线VGL1与第三晶体管的第一极T33为一体结构。第二条第二电源线VGL1与第四晶体管的第一极T103为一体结构。
在示例性实施方式中，如图44和图45所示，第八晶体管的第一极T83和第十一晶体管的第二极T114为一体结构。第二电源线VGL1与第三晶体管的第一极T33为一体结构。
在示例性实施方式中，如图46和图47所示，第八晶体管的第一极T83、第十一晶体管的第二极T114和第十二晶体管的第一极T123为一体结构。第九晶体管的第二极T94和第四晶体管的第二极T104为一体结构。第一条第二电源线VGL1与第三晶体管的第一极T33为一体结构。第二条第二电源线VGL1与第四晶体管的第一极T103为一体结构。
在示例性实施方式中，如图44和图45所示，初始信号线STV、第一时钟信号线CLK1、第二时钟信号线CLK2、第一电源线VGH和第二电源线VGL1沿靠近显示区的一侧依次排布。初始信号线STV、第一时钟信号线CLK1、第二时钟信号线CLK2、第一电源线VGH和第二电源线VGL1中的任一条沿第一方向D1延伸。
在示例性实施方式中，如图46和图47所示，初始信号线STV、第一时钟信号线CLK1、第二时钟信号线CLK2、第一电源线VGH、第一条第二电源线VGL1、第三时钟信号线CLK3、第四时钟信号线CLK4和第二条第二电源线VGL1沿靠近显示区的一侧依次排布。初始信号线STV、第一时钟信号线CLK1、第二时钟信号线CLK2、第一电源线VGH、第一条第二电源线VGL1、第三时钟信号线CLK3、第四时钟信号线CLK4和第二条第二电源线VGL1中的任一条沿第一方向D1延伸。
在示例性实施方式中，如图44至图47所示，第一晶体管的第一极T13的形状可以为方形，且沿第一方向D1延伸。第一晶体管的第一极T13通过第一过孔与第一晶体管的有源层的第一区连接，且通过上一级移位移位寄存器单元的第二十九过孔与位于上一级移位寄存器单元的第一连接线连接。如图44和图45所示，第一晶体管的第一极T13位于第一电源线VGH和第二电源线VGL1之间，如图46和图47所示，第一晶体管的第一极T13位于第一电源线VGH和第一条第二电源线VGL1之间。
在示例性实施方式中，如图44至47所示，第一晶体管的第二极T14(也是第七晶体管的第二极T74)的形状可以为“┌”型。第一晶体管的第二极T14(也是第七晶体管的第二极T74)通过第二过孔与第一晶体管的有源层的第二区、通过第十一过孔V11第七晶体管的有源层的第二区，且通过第二十三过孔与第二晶体管的控制极连接。如图44和图45所示，第一晶体管的第二极T14(也是第七晶体管的第二极T74)位于第一电源线VGH和第二电源线VGL1之间。如图46和图47所示，第一晶体管的第二极T14(也是第七晶体管的第二极T74)位于第一电源线VGH和第一条第二电源线VGL1之间。
在示例性实施方式中，如图44至图47所示，第二晶体管的第一极T23的形状可以为条状，且沿第一方向D1延伸。第二晶体管的第一极T23通过第三过孔与第二晶体管的有源层的第一区连接，且通过第二十二过孔与第一晶体管的控制极(也是第三晶体管的控制极)连接。如图44和图45所示，第二晶体管的第一极T23位于第一电源线VGH和第二电源线VGL1之间，如图46和图47所示，第二晶体管的第一极T23位于第一电源线VGH和第一条第二电源线VGL1之间。
在示例性实施方式中，如图44至图47所示，第二晶体管的第二极T24(也是第三晶体管的第二极T34)的形状可以为折线状，且至少部分沿第一方向D1延伸。如图44和图45所示，第二晶体管的第二极T24(也是第三晶体管的第二极T34)位于第一电源线VGH和第二电源线VGL1之间。第二晶体管的第二极T24(也是第三晶体管的第二极T34)通过第四过孔与第二晶体管的有源层的第二区连接，通过第六过孔与第三晶体管的有源层的第二区连接，通过第二十一过孔与有源连接部连接，且通过第二十四过孔与第四晶体管的控制极(也是第六晶体管的控制极)连接。如图46和图47所示，第二晶体管的第二极T24(也是第三晶体管的第二极T34)位于第一电源线VGH和第一条第二电源线VGL1之间。第二晶体管的第二极T24(也是第三晶体管的第二极T34)通过第四过孔与第二晶体管的有源层的第二区连接，通过第六过孔与第三晶体管的有源层的第二区连接，通过第二十一过孔与有源连接部连接，且通过第二十四过孔与第四晶体管的控制极(也是第六晶体管的控制极、第四晶体管的控制极和第四电容的第一极板)连接。
在示例性实施方式中，如图44至图47所示，第三晶体管的第一极T33的形状可以为条状，且沿第二方向D2延伸。第三晶体管的第一极T33通过第五过孔与第三晶体管的有源层的第一区连接。如图44和图45所示，第三晶体管的第一极T33位于第一电源线VGH和第二电源线VGL1之间。如图46和图47所示，第三晶体管的第一极T33位于第一电源线VGH和第一条第二电源线VGL1之间。
在示例性实施方式中，如图44至图47所示，第四晶体管的第一极T43的形状可以为条状，且沿第二方向D2延伸。第四晶体管的第一极T43通过第七过孔与第四晶体管的有源层的第一区连接，且通过第三十二过孔与第二连接线连接。如图44和图45所示，第四晶体管的第一极T43位于第二电源线VGL1靠近显示区的一侧。如图46和图47所示，第四晶体管的第一极T43位于第一条第二电源线VGL1和第三时钟信号线CLK3之间。
在示例性实施方式中，如图44至图47所示，第四晶体管的第二极T44(也是第五晶体管的第二极T54)的形状可以为字型。第四晶体管的第二极T44(也是第五晶体 管的第二极T54)通过第八过孔与第四晶体管的有源层的第二区(也是第五晶体管的有源层的第二区)连接，通过第二十九过孔与第一连接线连接，且通过第三十过孔与第二电容的第二极板连接。如图44和图45所示，第四晶体管的第二极T44(也是第五晶体管的第二极T54)位于第二电源线VGL1靠近显示区的一侧。如图46和图47所示，第四晶体管的第二极T44(也是第五晶体管的第二极T54)位于第一条第二电源线VGL1和第三时钟信号线CLK3之间。
在示例性实施方式中，如图44至图47所示，第五晶体管的第一极T53的形状可以为条状，且沿第二方向D2延伸。第五晶体管的第一极T53通过第九过孔与第五晶体管的有源层的第一区连接，且通过第二十六过孔与第七晶体管的控制极连接。如图44和图45所示，第五晶体管的第一极T53位于第二电源线VGL1靠近显示区的一侧。如图46和图47所示，第五晶体管的第一极T53位于第一条第二电源线VGL1和第三时钟信号线CLK3之间。
在示例性实施方式中，如图44至图47所示，第六晶体管的第一极T63的形状可以为条状，且沿第二方向D2延伸。第六晶体管的第一极T63通过第十过孔与第六晶体管的有源层的第一区连接，且通过第三十二过孔与第二连接线连接。如图44和图45所示，第六晶体管的第一极T63位于第一电源线VGH和第二电源线VGL1之间。如图46和图47所示，第六晶体管的第一极T63位于第一电源线VGH和第一条第二电源线VGL1之间。
在示例性实施方式中，如图44和图45所示，第八晶体管的第一极T83(也是第十一晶体管的第二极T114)的形状可以呈“L”字型。第八晶体管的第一极T83(也是第十一晶体管的第二极T114)位于第二电源线VGL1靠近显示区的一侧。第八晶体管的第一极T83(也是第十一晶体管的第二极T114)通过第十二过孔与第八晶体管的有源层的第一区连接，且通过第十八过孔与第十一晶体管的有源层的第二区连接，且通过第二十三过孔与第二晶体管的控制极连接。
在示例性实施方式中，如图46和图47所示，第八晶体管的第一极T83(也是第十一晶体管的第二极T114和第十二晶体管的第一极T123)的形状可以呈“L”字型。第八晶体管的第一极T83(也是第十一晶体管的第二极T114和第十二晶体管的第一极T123)位于第一条第二电源线VGL1和第三时钟信号线CLK3之间。第八晶体管的第一极T83(也是第十一晶体管的第二极T114和第十二晶体管的第一极T123)通过第十二过孔与第八晶体管的有源层的第一区连接，且通过第十八过孔与第十一晶体管的有源层的第二区连接，通过第十九过孔与第十二晶体管的有源层的第一区连接，且通过第二十三过孔与第二晶体管的控制极连接。
在示例性实施方式中，如图44至图47所示，第八晶体管的第二极T84的形状可以为条状，且沿第一方向D1延伸。第八晶体管的第二极T84通过第十三过孔与第八晶体管的有源层的第二区连接，且通过第二十五过孔与第五晶体管的控制极(也是第十一晶体管的控制极和第二电容的第一极板)连接。如图44和图45所示，第八晶体管的第二极T84位于第二电源线VGL1靠近显示区的一侧。如图46和图47所示，第八晶体管的第二极T84位于第一条第二电源线VGL1和第三时钟信号线CLK3之间。
在示例性实施方式中，如图46和图47所示，第九晶体管的第一极T93的形状可以呈“[”字型。第九晶体管的第一极T93位于第二条第二电源线VGL1靠近显示区的一侧。第九晶体管的第一极T93通过第十四过孔与第九晶体管的有源层的第一区连接，且通过第三十三过孔与第三连接线连接。
在示例性实施方式中，如图46和图47所示，第四晶体管的第一极T103的形状可以 为条状，且沿第一方向D1延伸。第四晶体管的第一极T103位于第二条第二电源线VGL1靠近显示区的一侧。第四晶体管的第一极T103通过第十六过孔与第四晶体管的有源层的第一区连接。
在示例性实施方式中，如图46和图47所示，第九晶体管的第一极94(也是第四晶体管的第二极T104)的形状可以为梳状，其中梳齿位于梳背远离显示区的一侧。第九晶体管的第一极94(也是第四晶体管的第二极T104)位于第二条第二电源线VGL1靠近显示区的一侧。第九晶体管的第一极94(也是第四晶体管的第二极T104)通过第十五过孔与第九晶体管的有源层的第二区(也是第四晶体管的有源层的第二区)连接，且通过第三十四过孔与第四连接线连接。
在示例性实施方式中，如图44至图47所示，第十一晶体管的第一极T113的形状可以为条状，且沿第一方向D1延伸。第十一晶体管的第一极T113通过第十七过孔与第十一晶体管的有源层的第一区连接。如图44和图45所示，第十一晶体管的第一极T113位于第二电源线VGL1靠近显示区的一侧。如图46和图47所示，第十一晶体管的第一极T113位于第一条第二电源线VGL1和第三时钟信号线CLK3之间。
在示例性实施方式中，如图44至图47所示，第十二晶体管的第二极T124的形状可以为条状，且沿第二方向D2延伸。第十二晶体管的第二极T124位于第一条第二电源线VGL1和第三时钟信号线CLK3之间。第十二晶体管的第二极T124通过第二十过孔与第十二晶体管的有源层的第二区连接，且通过第二十八过孔与第九晶体管的控制极连接。
在示例性实施方式中，如44至图47所示，第一晶体管的控制极(也是第三晶体管的控制极)通过第二十二过孔与第一时钟信号线CLK1和第二时钟信号线CLK2中的其中一条连接。图45和图47是以第一晶体管的控制极(也是第三晶体管的控制极)通过第二十二过孔与第一时钟信号线CLK1连接为例进行说明的。
在示例性实施方式中，如图44至图47所示，第七晶体管的控制极通过第二十六过孔与第一时钟信号线CLK1和第二时钟信号线CLK2的另一条连接。图45和图47是以第七晶体管的控制极通过第二十六过孔与第二时钟信号线CLK2连接为例进行说明的。
在示例性实施方式中，如图44和图45所示，第八晶体管的控制极(也是第十二晶体管的控制极)通过第二十七过孔与第二电源线VGL1连接。
在示例性实施方式中，如图46和图47所示，第八晶体管的控制极(也是第十二晶体管的控制极)通过第二十七过孔与第一条第二电源线VGL1连接。
在示例性实施方式中，如图46和图47所示，第四电容的第二极板通过第三十一过孔与第二条第二电源线VGL1连接。
在示例性实施方式中，如图46和图47所示，第三连接线通过第三十三过孔与第三时钟信号线CLK3和第四时钟信号线CLK4中的其中一条连接。图47是以第三连接线通过第三十三过孔与第三时钟信号线CLK3连接为例进行说明的。
在示例性实施方式中，如图47所示，第二条第二电源线VGL1在基底上的正投影与第四电容在基底上的正投影部分交叠。
(6)形成第四绝缘层图案，包括：在形成有前述图案的基底上，沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行构图，形成覆盖前述结构的第四绝缘层图案，第四绝缘层开设有过孔图案，如图48和图49所示，图48为图30形成第四绝缘层图案后的示意图，图49为图31形成第四绝缘层图案后的示意图。
在示例性实施方式中，如图48和图49所示，过孔图案可以包括：第三十五过孔V35。
在示例性实施方式中，第三十五过孔V35在基底上的正投影位于第十一晶体管的第一极在基底上的正投影的范围之内，第三十五过孔V35暴露出第十一晶体管的第一极的表面，第三十五过孔V35被配置为使后续形成的第三电源线通过该过孔与第十一晶体管的第一极连接。
(7)形成第四导电层图案，包括：在形成前述图案的基底上，沉积第四金属薄膜，通过图案化工艺对第四金属薄膜进行构图，形成第四金属层图案，如图50至图52所示，图50为图30和图31中的第四导电层图案的示意图，图51为图30形成第四导电层图案后的示意图，图52为图31形成第四导电层图案后的示意图。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，如图50至图52所示，第四导电层图案可以包括：第三电源线VGL2。
在示例性实施方式中，如图50至图52所示，第三电源线VGL2的形状可以为线形状，且沿第一方向D1延伸。第三电源线VGL2通过第三十五过孔与第十一晶体管的第一极连接。第三电源线VGL2在基底上的正投影与第四晶体管和第五晶体管在基底上的正投影部分交叠。
在示例性实施方式中，如图51所示，第三电源线VGL2在基底上的正投影位于第二电源线在基底上的正投影靠近显示区的一侧。如图52所示，第三电源线VGL2在基底上的正投影位于第一条第二电源线在基底上的正投影和第三时钟信号线在基底上的正投影之间。
(8)形成平坦层图案，包括：在形成有前述图案的基底上，沉积第五绝缘薄膜，涂覆第二平坦薄膜，通过图案化工艺对第五绝缘薄膜和第二平坦薄膜进行图案化，形成覆盖前述图案的第五绝缘层图案和平坦层图案。
至此，在基底上制备完成驱动结构层。在平行于显示基板的平面内，驱动结构层可以包括多个移位寄存器单元，驱动结构层可以设置在基底上。驱动结构层可以包括在基底上依次设置的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、第四导电层、第五绝缘层和平坦层。
在示例性实施方式中，半导体层可以为非晶硅层或者多晶硅层，或者可以为金属氧化物层。其中，金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物或者包含铟或镓和锌的氧化物。金属氧化物层可以单层，或者可以是双层，或者可以是多层。
在示例性实施方式中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
在示例性实施方式中，平坦层可以采用有机材料，如树脂等。
在示例性实施方式中，制备完成驱动结构层后，在驱动结构层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在平坦层上的阳极导电层图案，在形成前述图案的基底上，沉积像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成暴露出阳极导电层图案的像素定义层图案，在形成有像素定义层图案的基底上，涂覆有机发光材料，通过图案化工艺对有机发光材料进行图案化，形成有机结构层图案，在形成有机材料层图案的基底上，沉积阴极导电薄膜，通过图案化工艺对阴极导电薄膜进行图案化，形成阴极导电层。
至此，在基底上制备完成发光结构层。
在示例性实施方式中，后续制备流程可以包括：在阴极导电层上形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，阳极导电层至少包括多个阳极图案。
在示例性实施方式中，阳极导电层采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，有机结构层至少可以包括：发光器件的有机发光层。
在示例性实施方式中，阴极导电层至少可以包括：多个发光器件的阴极。
在示例性实施方式中，阴极层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述导电的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。示例性地，第四导电层可以为钛、铝和钛形成的三层堆叠结构。
本公开实施例通过的显示基板可以适用于任何分辨率的显示产品中。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (42)

  1. 一种移位寄存器单元，包括：节点控制子电路、输出子电路和下拉子电路；
    所述节点控制子电路，分别与信号输入端、第一时钟信号端、第二时钟信号端、第一电源端、第二电源端、第一节点和第二节点电连接，被配置为在第一时钟信号端和第二时钟信号端的信号控制下，向第一节点提供信号输入端或者第一电源端的信号，向第二节点提供第二电源端或者第一时钟信号端的信号；
    所述下拉子电路，分别与第一节点和第三电源端电连接，被配置为向第一节点提供第三电源端的信号；
    所述输出子电路，分别与第二时钟信号端、第一电源端、第二电源端、第一信号输出端、第一节点和第二节点电连接，被配置为在第一节点、第二节点和第二电源端的信号的控制下，向第一信号输出端提供第一电源端或者第二时钟信号端的信号；
    所述第三电源端的信号的电压值的绝对值小于所述第二电源端的信号的电压值的绝对值。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述下拉子电路包括：第十一晶体管；
    第十一晶体管的第一极与第三电源端电连接，第十一晶体管的第二极与第一节点电连接。
  3. 根据权利要求2所述的移位寄存器单元，其中，第十一晶体管的控制极与第一节点电连接。
  4. 根据权利要求1所述的移位寄存器单元，其中，所述节点控制子电路包括：第一晶体管、第二晶体管、第三晶体管、第六晶体管和第七晶体管；
    第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第一节点电连接，第二晶体管的第一极与第一时钟信号端连接，第二晶体管的第二极与第二节点电连接；
    第三晶体管的控制极与第一时钟信号端电连接，第三晶体管的第一极与第二电源端连接，第三晶体管的第二极与第二节点电连接；
    第六晶体管的控制极与第二节点电连接，第六晶体管的第一极与第一电源端连接，第六晶体管的第二极与第四节点电连接；
    第七晶体管的控制极与第二时钟信号端电连接，第七晶体管的第一极与第四节点连接，第七晶体管的第二极与第一节点电连接。
  5. 根据权利要求1所述的移位寄存器单元，其中，所述输出子电路包括：第四晶体管、第五晶体管和第八晶体管；
    第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第一电源端连接，第四晶体管的第二极与第一信号输出端电连接；
    第五晶体管的控制极与第三节点电连接，第五晶体管的第一极与第二时钟信号端连接，第五晶体管的第二极与第一信号输出端电连接；
    第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点连接，第八晶体管的第二极与第三节点电连接。
  6. 根据权利要求5所述的移位寄存器单元，其中，所述下拉子电路包括：第十一晶体管；
    第十一晶体管控制极与第三节点电连接。
  7. 根据权利要求5所述的移位寄存器单元，其中，所述输出子电路还包括：第一电容和第二电容中的至少一个；
    第一电容的第一极板与第二节点电连接，第一电容的第二极板与第一电源端电连接；
    第二电容的第一极板与第三节点电连接，第二电容的第二极板与第一信号输出端电连接。
  8. 根据权利要求1所述的移位寄存器单元，其中，所述输出子电路，还分别与第三时钟信号端和第二信号输出端电连接，被配置为在第一节点和第二节点的信号的控制下，向第二信号输出端提供第二电源端或者第三时钟信号端的信号。
  9. 根据权利要求8所述的移位寄存器单元，其中，所述输出子电路包括：第四晶体管、第五晶体管、第八晶体管、第九晶体管和第十晶体管；
    第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第一电源端连接，第四晶体管的第二极与第一信号输出端电连接；
    第五晶体管的控制极与第三节点电连接，第五晶体管的第一极与第二时钟信号端连接，第五晶体管的第二极与第一信号输出端电连接；
    第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点连接，第八晶体管的第二极与第三节点电连接；
    第九晶体管的控制极与第一节点电连接，第九晶体管的第一极与第三时钟信号端连接，第九晶体管的第二极与第二信号输出端电连接；
    第十晶体管的控制极与第二节点电连接，第十晶体管的第一极与第二电源端连接，第十晶体管的第二极与第二信号输出端电连接。
  10. 根据权利要求9所述的移位寄存器单元，其中，所述输出子电路还包括：第十二晶体管；所述第九晶体管的控制极通过第十二晶体管与第一节点电连接；
    第十二晶体管的控制极与第二电源端电连接，第十二晶体管的第一极与第一节点电连接，第十二晶体管的第二极与第九晶体管的控制极电连接。
  11. 根据权利要求9或10所述的移位寄存器单元，其中，所述输出子电路还包括：第一电容、第二电容、第三电容和第四电容中的至少一个；
    第一电容的第一极板与第二节点电连接，第一电容的第二极板与第一电源端电连接；
    第二电容的第一极板与第三节点电连接，第二电容的第二极板与第一信号输出端电连接；
    第三电容的第一极板与第九晶体管的控制极电连接，第三电容的第二极板与第二信号输出端连接；
    第四电容的第一极板与第二节点电连接，第四电容的第二极板与第二电源端连接。
  12. 根据权利要求8所述的移位寄存器单元，其中，所述第三时钟信号端的信号与所述第二时钟信号端的信号互为反相信号。
  13. 根据权利要求1所述的移位寄存器单元，还包括：输出控制子电路；
    所述输出控制子电路，分别与第一电源端和第一信号输出端电连接，被配置为存储第 一信号输出端和第一电源端的信号之间的电压差。
  14. 根据权利要求13所述的移位寄存器单元，其中，所述输出控制子电路包括：第五电容；
    第五电容的第一极板与第一电源端电连接，第五电容的第二极与第一信号输出端电连接。
  15. 根据权利要求1所述的移位寄存器单元，其中，所述第一时钟信号端的信号和所述第二时钟信号端的信号不同时为有效电平信号。
  16. 一种显示基板，包括：基底以及设置在所述基底上的子像素、栅线和栅极驱动电路，所述基底设置有显示区和非显示区，所述栅极驱动电路位于所述非显示区，所述子像素和所述栅线位于所述显示区，所述栅线分别与所述子像素和所述栅极驱动电路电连接；
    所述栅极驱动电路包括：多个级联的如权利要求1至15任一项所述的移位寄存器单元，其中，第i级移位寄存器单元的第一信号输出端与第i+1级移位寄存器单元的信号输入端连接，1≤i<N，N为移位寄存器单元的总级数。
  17. 根据权利要求16所述的显示基板，其中，所述移位寄存器单元的第一信号输出端与栅线电连接。
  18. 根据权利要求16所述的显示基板，还包括：设置在基底上，且位于所述非显示区的初始信号线、第一时钟信号线、第二时钟信号线、第一电源线、第二电源线和第三电源线；
    所述初始信号线、所述第一时钟信号线、所述第二时钟信号线、所述第一电源线、所述第二电源线和所述第三电源线中的任一条沿第一方向延伸，所述栅线沿第二方向延伸，所述第一方向与所述第二方向相交。
  19. 根据权利要求18所述的显示基板，其中，所述初始信号线、所述第一时钟信号线、所述第二时钟信号线和所述第一电源线沿靠近所述显示区的方向依次排布，且位于所述移位寄存器单元远离所述显示区的一侧。
  20. 根据权利要求18所述的显示基板，其中，所述移位寄存器单元包括：多个晶体管，所述第二电源线位于所述第一电源线靠近显示区的一侧，且位于移位寄存器单元的多个晶体管之间。
  21. 根据权利要求18所述的显示基板，其中，所述第三电源线位于所述第二电源线靠近所述显示区的一侧，且在基底上的正投影与所述移位寄存器单元在基底上的正投影部分交叠。
  22. 根据权利要求18所述的显示基板，其中，所述移位寄存器单元包括：第一晶体管、第二晶体管、第三晶体管、第六晶体管和第七晶体管；
    所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第六晶体管和所述第七晶体管中的任一个晶体管的至少部分位于所述第一电源线和所述第二电源线之间。
  23. 根据权利要求18所述的显示基板，其中，所述移位寄存器单元包括：第四晶体管、第五晶体管、第八晶体管、第十一晶体管和第十二晶体管，所述第二电源线的数量为至少一条；
    所述第四晶体管、所述第五晶体管、所述第八晶体管、所述第十一晶体管和所述第十二晶体管中的任一晶体管的至少部分位于所述第二电源线靠近所述显示区的一侧。
  24. 根据权利要求18所述的显示基板，其中，所述移位寄存器单元包括：第二电容；
    所述第二电容位于所述第三电源线靠近显示区的一侧。
  25. 根据权利要求18或19所述的显示基板，还包括：设置在所述基底，且位于所述非显示区的第三时钟信号线和第四时钟信号线，所述第三时钟信号线和所述第四时钟信号线中的任一条沿第一方向延伸；
    所述第二电源线的数量为两条，靠近所述显示区的所述第二电源线位于所述第三时钟信号线和所述第四时钟信号线中任一条靠近所述显示区的一侧，远离所述显示区的所述第二电源线位于所述第一电源线和所述第三电源线之间。
  26. 根据权利要求25所述的显示基板，其中，所述移位寄存器单元包括：第四晶体管、第五晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管和第四电容；
    所述第四晶体管、所述第五晶体管、所述第八晶体管、第十一晶体管和第十二晶体管位于远离所述显示区的所述第二电源线和所述第三时钟信号线和所述第四时钟信号线中任一条之间，所述第九晶体管和所述第十晶体管位于靠近所述显示区的所述第二电源线靠近所述显示区的一侧；
    靠近所述显示区的所述第二电源线在基底上的正投影与所述第四电容在基底上的正投影部分交叠。
  27. 根据权利要求18所述的显示基板，其中，第i级移位寄存器单元的第一时钟信号端与所述第一时钟信号线和所述第二时钟信号线中的其中一条电连接，第i级移位寄存器单元的第二时钟信号端与所述第一时钟信号线和所述第二时钟信号线中的另一条电连接；
    相邻移位寄存器单元的第一时钟信号端连接的信号线不同，相邻移位寄存器单元的第二时钟信号端连接的信号线不同。
  28. 根据权利要求21所述的显示基板，其中，所述移位寄存器单元包括：第四晶体管和第五晶体管；
    所述第三电源线在基底上的正投影与所述第四晶体管和所述第五晶体管在基底上的正投影部分交叠。
  29. 根据权利要求23所述的显示基板，其中，所述第八晶体管的有源层沿第二方向延伸，所述第八晶体管的第一极和第二极中的任一电极沿第一方向延伸，所述第八晶体管的栅电极至少部分沿第一方向延伸。
  30. 根据权利要求23所述的显示基板，其中，第十一晶体管的栅电极与第五晶体管的栅电极为一体结构，第十一晶体管的第一极在基底上的正投影与第三电源线在基底上的正投影部分交叠，且与第三电源线电连接，第十一晶体管的第二极与第八晶体管的第一极、第十二晶体管的第一极为一体结构。
  31. 根据权利要求25所述的显示基板，其中，所述第一电源线、所述第二电源线和所述第三电源线中的任一条沿第二方向的宽度小于所述第一时钟信号线、所述第二时钟信号线、所述第三时钟信号线和所述第四时钟信号线中任一条沿第二方向的宽度。
  32. 根据权利要求25所述的显示基板，其中，第i级移位寄存器单元的第三时钟信号端与所述第三时钟信号线和所述第四时钟信号线中的其中一条电连接，第i+1级移位寄存器单元的第三时钟信号端与所述第三时钟信号线和所述第四时钟信号线中的另一条电连接。
  33. 根据权利要求26所述的显示基板，其中，所述第九晶体管第十晶体管的有源层 的沟道宽度大于所述第四晶体管的有源层的沟道宽度。
  34. 根据权利要求33所述的显示基板，其中，所述第十晶体管第九晶体管的有源层的沟道宽度不小于90微米。
  35. 根据权利要求33所述的显示基板，其中，所述第四晶体管的有源层的沟道宽度不大于50微米。
  36. 根据权利要求26所述的显示基板，其中，所述第十第九晶体管的有源层的沟道宽度大于所述第五晶体管的有源层的沟道宽度。
  37. 根据权利要求36所述的显示基板，其中，所述第九晶体管第十晶体管的有源层的沟道宽度不小于90微米。
  38. 根据权利要求36所述的显示基板，其中，所述第五晶体管的有源层的沟道宽度不大于50微米。
  39. 根据权利要求26所述的显示基板，其中，所述移位寄存器单元的第二信号输出端与栅线电连接。
  40. 一种显示装置，包括：如权利要求16至39任一项所述的显示基板。
  41. 一种移位寄存器单元的驱动方法，被配置为驱动如权利要求1至15任一项所述的移位寄存器单元，所述方法包括：
    节点控制子电路在第一时钟信号端和第二时钟信号端的信号控制下，向第一节点提供信号输入端或者第一电源端的信号，向第二节点提供第二电源端或者第一时钟信号端的信号；
    下拉子电路向第一节点提供第三电源端的信号；
    输出子电路在第一节点和第二节点的信号的控制下，向第一信号输出端提供第一电源端或者第二时钟信号端的信号。
  42. 根据权利要求41所述的方法，其中，所述移位寄存器单元还包括：输出控制子电路；
    所述方法还包括：输出子电路在第一节点和第二节点的信号的控制下，向第二信号输出端提供第二电源端或者第三时钟信号端的信号；
    输出控制子电路存储第一信号输出端和第一电源端的信号之间的电压差。
PCT/CN2024/094416 2023-06-13 2024-05-21 移位寄存器单元及其驱动方法、显示基板、显示装置 Ceased WO2024255545A1 (zh)

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