WO2024241741A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2024241741A1
WO2024241741A1 PCT/JP2024/014534 JP2024014534W WO2024241741A1 WO 2024241741 A1 WO2024241741 A1 WO 2024241741A1 JP 2024014534 W JP2024014534 W JP 2024014534W WO 2024241741 A1 WO2024241741 A1 WO 2024241741A1
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Prior art keywords
region
trench
conductivity type
semiconductor device
contact
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French (fr)
Japanese (ja)
Inventor
功 吉川
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Priority to CN202480004519.9A priority Critical patent/CN120153772A/zh
Priority to JP2025521859A priority patent/JPWO2024241741A1/ja
Publication of WO2024241741A1 publication Critical patent/WO2024241741A1/ja
Priority to US19/185,148 priority patent/US20250254983A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/415—Insulated-gate bipolar transistors [IGBT] having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/417—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the collector side relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/418—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the emitter side relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/128—Anode regions of diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/129—Cathode regions of diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/232—Emitter electrodes for IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/422—PN diodes having the PN junctions in mesas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.
  • Patent Document 1 JP 2022-67972 A
  • a semiconductor device in a first aspect of the present invention, includes a transistor portion and a diode portion, the semiconductor device including a plurality of trench portions provided on the front surface of a semiconductor substrate, a drift region of a first conductivity type provided in the semiconductor substrate, a base region of a second conductivity type provided above the drift region, an emitter region of the first conductivity type provided above the base region and having a higher doping concentration than the drift region, a first contact region of the second conductivity type provided in a mesa portion of the transistor portion and having a higher doping concentration than the base region, an anode region of the second conductivity type provided above the drift region in the diode portion, and a second contact region of the second conductivity type provided in the mesa portion of the diode portion and having a higher doping concentration than the anode region.
  • the amount of the second conductivity type dopant per unit volume in the mesa portion of the diode portion may be equal to or greater than the amount of the second conductivity type do
  • the transistor portion and the diode portion may be provided with trench contact portions.
  • the depth of the lower end of the trench contact portion may be deeper than the depth of the lower end of the emitter region in the depth direction of the semiconductor substrate.
  • the first contact region may be provided at the lower end of the trench contact portion.
  • the second contact region may be provided at the lower end of the trench contact portion.
  • the width of the trench contact portion in the diode portion in the arrangement direction of the multiple trench portions may be the same as the width of the trench contact portion in the transistor portion.
  • the width of the trench contact portion in the diode portion may be greater than the width of the trench contact portion in the transistor portion in the arrangement direction of the plurality of trench portions.
  • the multiple trench portions may have a gate trench portion to which a gate potential is applied, and a dummy trench portion to which a potential different from the gate potential is applied.
  • the trench contact portion may be provided in a mesa portion provided between the gate trench portion and the dummy trench portion, closer to the dummy trench portion than to the gate trench portion.
  • a doping concentration of the first contact region in the transistor portion may be not less than 1E19 cm ⁇ 3 and not more than 1E21 cm ⁇ 3 .
  • the first contact region may be provided in the transistor portion, extending in the extension direction of the plurality of trench portions.
  • the first contact region may be provided in the transistor portion and spaced apart from the emitter region.
  • the plurality of trench portions may include a gate trench portion to which a gate potential is applied, and a dummy trench portion to which a potential different from the gate potential is applied.
  • the first contact region may be provided in the transistor portion, spaced apart from the gate trench portion.
  • a doping concentration of the second contact region in the diode portion may be not less than 1E19 cm ⁇ 3 and not more than 1E21 cm ⁇ 3 .
  • the second contact region may be provided in the diode portion, extending in the extension direction of the plurality of trench portions.
  • the multiple trenches may have a gate trench to which a gate potential is applied and a dummy trench to which a potential different from the gate potential is applied.
  • the second contact region may be provided in a mesa portion sandwiched between the two dummy trenches of the diode portion, extending from a sidewall of one of the dummy trenches to a sidewall of the other dummy trench.
  • the emitter regions and the base regions may be provided alternately in the extension direction of the multiple trench portions on the front surface of the semiconductor substrate.
  • the emitter region may be provided on the front surface of the semiconductor substrate, extending in the extension direction of the multiple trench portions.
  • the doping concentration of the base region may be the same as the doping concentration of the anode region.
  • a cathode region of the first conductivity type is provided on a rear surface of the semiconductor substrate, the cathode region having a doping concentration higher than that of the drift region.
  • the doping concentration of the cathode region may be 1E18 cm ⁇ 3 or more and 1E21 cm ⁇ 3 or less.
  • the transistor portion may include an accumulation region of the first conductivity type having a doping concentration higher than that of the drift region.
  • the semiconductor substrate may not have a lifetime control region.
  • the transistor portion may have a main region that operates as a transistor.
  • the main region of the transistor portion may be provided adjacent to the diode portion.
  • the amount of the second conductivity type dopant per unit volume in the mesa portion of the diode portion may be equal to or greater than the amount of the second conductivity type dopant per unit volume in the mesa portion of the main region.
  • a semiconductor device having a transistor portion comprising: a drift region of a first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided above the drift region; a first contact region of the second conductivity type provided in a mesa portion of the transistor portion and having a doping concentration higher than that of the base region; and a trench contact portion provided on the front surface of the semiconductor substrate.
  • the first contact region does not have to be provided on the front surface of the semiconductor substrate.
  • a method for manufacturing a semiconductor device having a transistor portion and a diode portion comprising the steps of: providing a plurality of trench portions on the front surface of a semiconductor substrate; providing a drift region of a first conductivity type in the semiconductor substrate; providing a base region of a second conductivity type above the drift region; providing an emitter region of a first conductivity type having a higher doping concentration than the drift region above the base region; providing an anode region of a second conductivity type above the drift region in the diode portion; a first ion implantation step of providing a first contact region of a second conductivity type having a higher doping concentration than the base region in the mesa portion of the transistor portion; and a second ion implantation step of providing a second contact region of a second conductivity type having a higher doping concentration than the anode region above the drift region in the diode portion.
  • the first ion implantation step and the second ion implantation step may be the same ion implantation step.
  • the dose of ions implanted in the first ion implantation step may be different from the dose of ions implanted in the second ion implantation step.
  • FIG. 2 is a diagram showing an example of the top surface of the semiconductor device 100.
  • 1 is a diagram showing an example of aa' cross section of a semiconductor device 100.
  • FIG. 2 is a diagram showing an example of a bb' cross section of the semiconductor device 100.
  • FIG. 1 is a diagram showing an example of a cc' cross section of the semiconductor device 100.
  • FIG. 1A and 1B are diagrams illustrating modified examples of the upper surface of the semiconductor device 100.
  • 1A and 1B are diagrams illustrating modified examples of the upper surface of the semiconductor device 100.
  • 1 is a diagram showing an example of a dd′ cross section of the semiconductor device 100.
  • FIG. 1A and 1B are diagrams illustrating modified examples of the upper surface of the semiconductor device 100.
  • FIG. 13 is a diagram showing the relationship between the doping concentration of the cathode region 82 and the forward voltage Vf of the diode section 80.
  • FIG. 11 is a diagram showing the relationship between the forward voltage Vf and the reverse recovery loss Err of the diode section 80.
  • FIG. 4 is a flowchart showing an example of a method for manufacturing the semiconductor device 100.
  • top one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "top” and the other side as “bottom.”
  • bottom one side in a direction parallel to the depth direction of the semiconductor substrate
  • top surface one surface is referred to as the top surface and the other surface is referred to as the bottom surface.
  • the directions of "top,” “bottom,” “front,” and “back” are not limited to the direction of gravity or the direction in which the semiconductor device is attached to a substrate or the like when mounted.
  • the orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction.
  • the Z-axis does not limit the height direction relative to the ground.
  • the +Z-axis direction and the -Z-axis direction are opposite directions.
  • the Z-axis direction is described without indicating positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.
  • the plane parallel to the top surface of the semiconductor substrate is referred to as the XY plane, and the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis.
  • the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis.
  • the depth direction of the semiconductor substrate may be referred to as the Z-axis.
  • the case where the semiconductor substrate is viewed in the Z-axis direction is referred to as a planar view.
  • the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis may be referred to as the horizontal direction.
  • the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type.
  • the conductivity types of the substrate, layer, region, etc. in each embodiment will be of opposite polarity.
  • the conductivity type of a doped region doped with impurities is described as P type or N type.
  • impurities may specifically mean either N type donors or P type acceptors, and may be described as dopants.
  • doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor that exhibits N type conductivity or a semiconductor that exhibits P type conductivity.
  • doping concentration refers to the donor concentration or acceptor concentration in thermal equilibrium.
  • FIG. 1A shows an example of the top surface of a semiconductor device 100.
  • the semiconductor device 100 of this example is a semiconductor chip including a transistor section 70 and a diode section 80.
  • the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT).
  • the transistor section 70 may include a boundary region in a portion adjacent to the diode section 80.
  • the transistor section 70 of this example does not include a boundary region.
  • the front surface 21 of the semiconductor substrate 10 is provided with a plurality of trench portions extending in a predetermined direction (in this example, the Y-axis direction) and arranged in a predetermined direction (in this example, the X-axis direction).
  • the front surface 21 will be described later.
  • the plurality of trench portions include a gate trench portion 40 to which a gate potential is applied, and a dummy trench portion 30 to which a potential different from the gate potential is applied.
  • the transistor section 70 is a region obtained by projecting the collector region 22 provided on the back side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10.
  • the collector region 22 has a second conductivity type.
  • the collector region 22 is a P+ type, for example.
  • the transistor section 70 includes a transistor such as an IGBT.
  • the transistor section 70 includes a main region 75.
  • the main region 75 is a region in which a channel region is formed during operation of the semiconductor device 100 and which operates as a transistor.
  • the main region 75 may be a region of the transistor section 70 other than the boundary region. Since the transistor section 70 in this example does not have a boundary region, the transistor section 70 and the main region 75 coincide with each other. In other words, the main region 75 of the transistor section 70 is provided adjacent to the diode section 80.
  • the diode section 80 is a region obtained by projecting a cathode region 82 provided on the back surface of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10.
  • the cathode region 82 has a first conductivity type.
  • the cathode region 82 is an N+ type, for example.
  • the diode section 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.
  • FWD free wheel diode
  • an anode region 19 may be formed on the front surface, and in the diode section 80, an emitter region 12 and a base region 14 may be formed on the front surface.
  • the distance between the boundary between the region in which the emitter region 12 or the base region 14 is provided and the region in which the anode region 19 is provided, and the boundary between the collector region 22 and the cathode region 82 may be 0 ⁇ m or more and 10 ⁇ m or less. In this example, the distance is 0 ⁇ m.
  • an edge termination structure may be provided in the region on the negative side in the Y-axis direction of the semiconductor device 100 in this example.
  • the edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate 10.
  • the edge termination structure has, for example, a guard ring, a field plate, a resurf, or a structure combining these. Note that, for convenience, in this example, the edge on the negative side in the Y-axis direction is described, but the same applies to the other edges of the semiconductor device 100.
  • the edge termination structure may be provided to surround an active region including a transistor portion 70 and a diode portion 80.
  • the semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc.
  • the semiconductor substrate 10 in this example is a silicon substrate.
  • the semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a well region 17, and an anode region 19 on the front surface 21 of the semiconductor substrate 10.
  • the semiconductor device 100 of this example includes a first contact region 73 provided in the mesa portion 71 of the transistor portion 70 and a second contact region 83 provided in the mesa portion 81 of the diode portion 80.
  • the semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.
  • the emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the well region 17, and the anode region 19.
  • the gate metal layer 50 is provided above the gate trench portion 40 and the well region 17.
  • the emitter electrode 52 and the gate metal layer 50 are formed of a material containing a metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al) or an alloy containing aluminum, such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al) or an alloy containing aluminum, such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal made of titanium or a titanium compound under the region made of aluminum or an alloy containing aluminum. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.
  • the emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with the interlayer insulating film 38 in between.
  • the interlayer insulating film 38 is omitted in FIG. 1A.
  • the interlayer insulating film 38 has contact holes 54, 55, and 56 penetrating therethrough.
  • the contact holes 54 are provided extending from the upper surface of the interlayer insulating film 38 in the depth direction of the semiconductor substrate 10.
  • the contact holes 54 have a bottom and sides.
  • the contact holes 54 electrically connect the emitter electrode 52 and the semiconductor substrate 10.
  • the contact holes 54 are provided extending in the trench extension direction.
  • the contact holes 54 are arranged in a stripe pattern along the gate trench portion 40 and the dummy trench portion 30.
  • the contact hole 54 is provided in both the transistor section 70 and the diode section 80.
  • the contact hole 54 is formed in the upper surface of each of the emitter region 12 and the base region 14.
  • the contact hole 54 is provided above the anode region 19.
  • the contact hole 54 is not provided above the well regions 17 provided at both ends in the Y-axis direction.
  • one or more contact holes 54 are formed in the interlayer insulating film.
  • the one or more contact holes 54 may be provided extending in the extension direction.
  • the contact hole 54 may be provided with a trench contact section 60. That is, the trench contact section 60 may be provided in both the transistor section 70 and the diode section 80. The trench contact section 60 will be described later.
  • the contact hole 55 connects the gate metal layer 50 to the gate conductive portion in the transistor portion 70. Inside the contact hole 55, a plug made of tungsten or the like may be formed via a barrier metal.
  • the contact hole 56 connects the emitter electrode 52 to the dummy conductive portion in the dummy trench portion 30. Inside the contact hole 56, a plug made of tungsten or the like may be formed via a barrier metal.
  • connection portion 25 electrically connects the front surface electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10.
  • the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion.
  • the connection portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion.
  • the connection portion 25 is a conductive material, such as polysilicon doped with impurities.
  • the connection portion 25 is polysilicon (N+) doped with N-type impurities.
  • the connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film, such as an oxide film.
  • the gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example).
  • the gate trench portions 40 in this example may have two extension portions 41 that extend parallel to the front surface 21 of the semiconductor substrate 10 and along an extension direction perpendicular to the arrangement direction (the Y-axis direction in this example), and a connection portion 43 that connects the two extension portions 41.
  • connection portion 43 may be formed at least partially in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, electric field concentration at the ends of the extension portions 41 can be alleviated.
  • the gate metal layer 50 may be connected to the gate conductive portion.
  • the dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. Like the gate trench portion 40, the dummy trench portion 30 is arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). Like the gate trench portion 40, the dummy trench portion 30 in this example may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connection portion 33 connecting the two extension portions 31.
  • the main region 75 has a structure in which one gate trench section 40 and one dummy trench section 30 are repeatedly arranged. That is, the transistor section 70 of this example has gate trench sections 40 and dummy trench sections 30 in a 1:1 ratio.
  • the transistor section 70 has one extension section 31 between two extension sections 41.
  • the transistor section 70 also has one extension section 41 between two extension sections 31.
  • the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example.
  • the ratio of the gate trench portions 40 to the dummy trench portions 30 may be 2:3 or 2:4.
  • the transistor portion 70 may have all trench portions as gate trench portions 40 and may not have dummy trench portions 30.
  • Mesa portion 71 is a mesa portion provided adjacent to a trench portion in a plane parallel to front surface 21 of semiconductor substrate 10.
  • a mesa portion is a portion of semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion from front surface 21 of semiconductor substrate 10 to the deepest bottom of each trench portion.
  • the extension portion of each trench portion may be considered as one trench portion. In other words, the area sandwiched between two extension portions may be considered as a mesa portion.
  • the mesa portion 71 is provided adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40 in the transistor portion 70.
  • the mesa portion 71 has a well region 17, an emitter region 12, and a base region 14 on the front surface 21 of the semiconductor substrate 10.
  • the emitter regions 12 and the base regions 14 are provided alternately in the extension direction of the trench portion (the Y-axis direction in this example) on the front surface 21 of the semiconductor substrate 10.
  • the base region 14 is a region of a second conductivity type provided above the drift region 18 described below.
  • the base region 14 is P-type.
  • the base region 14 may be provided on both ends of the mesa portion 71 in the Y-axis direction on the front surface 21 of the semiconductor substrate 10. In FIG. 1A, only one end of the base region 14 in the Y-axis direction is shown.
  • the emitter region 12 is a first conductivity type region that is provided above the base region 14 and has a higher doping concentration than the drift region 18.
  • the emitter region 12 is an N+ type, for example.
  • An example of a dopant for the emitter region 12 is arsenic (As).
  • the emitter region 12 is provided in contact with the gate trench portion 40 on the front surface 21 of the mesa portion 71.
  • the emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions that sandwich the mesa portion 71 to the other.
  • the emitter region 12 may or may not be in contact with the dummy trench portion 30.
  • the emitter region 12 is in contact with the dummy trench portion 30.
  • the mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30.
  • the mesa portion 81 has an anode region 19 on the front surface 21 of the semiconductor substrate 10.
  • the mesa portion 81 has an anode region 19, a base region 14, and a well region 17 on the negative side in the Y-axis direction.
  • the anode region 19 is a region of the second conductivity type provided above the drift region 18.
  • the doping concentration of the anode region 19 may be the same as the doping concentration of the base region 14, or may be greater than the doping concentration of the base region 14. In this example, the doping concentration of the anode region 19 is the same as the doping concentration of the base region 14. In this example, the anode region 19 is, as an example, P-type.
  • the anode region 19 in this example is provided on the front surface 21 of the mesa portion 81.
  • the anode region 19 may be provided in the X-axis direction from one of the two dummy trench portions 30 that sandwich the mesa portion 81 to the other.
  • the anode region 19 may or may not be in contact with the dummy trench portion 30.
  • the anode region 19 in this example is in contact with the dummy trench portion 30.
  • the doping concentration of the anode region 19 in this example may be 1E16 cm ⁇ 3 or more, and may be 1E18 cm ⁇ 3 or less.
  • E means a power of 10
  • 1E18 cm ⁇ 3 means 1 ⁇ 10 18 cm ⁇ 3 .
  • the anode region 19 may have a peak of doping concentration in the depth direction of the semiconductor substrate 10.
  • the lower end of the anode region 19 may be at the same depth as the lower end of the base region 14, or may be located deeper than the lower end of the base region 14.
  • the first contact region 73 is a region of a second conductivity type having a higher doping concentration than the base region 14.
  • the first contact region 73 is, for example, a P++ type.
  • the doping concentration of the first contact region 73 in the transistor section 70 may be 1E19 cm ⁇ 3 or more and may be 1E21 cm ⁇ 3 or less.
  • the first contact region 73 may be provided in the transistor section 70, extending in the extension direction of the multiple trench sections.
  • the first contact region 73 is provided extending along the emitter regions 12 and base regions 14 that are alternately provided on the front surface 21 of the semiconductor substrate 10.
  • the second contact region 83 is a region of a second conductivity type having a higher doping concentration than the anode region 19.
  • the second contact region 83 is, for example, a P++ type.
  • the doping concentration of the second contact region 83 may be the same as or different from the doping concentration of the first contact region.
  • the doping concentration of the second contact region 83 may be higher than the doping concentration of the first contact region 73.
  • the doping concentration of the second contact region 83 in the diode section 80 may be 1E19 cm ⁇ 3 or more and 1E21 cm ⁇ 3 or less.
  • the second contact region 83 may be provided in the diode section 80, extending in the extension direction of the multiple trench sections.
  • the second contact region 83 is provided in correspondence with the extension direction of the first contact region 73.
  • FIG. 1B is an example of the a-a' cross section in FIG. 1A.
  • the a-a' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70.
  • the semiconductor device 100 of this example has the emitter region 12, base region 14, accumulation region 16, drift region 18, buffer region 20, semiconductor substrate 10 in which the first contact region 73 and second contact region 83 are provided, interlayer insulating film 38, trench contact section 60, emitter electrode 52, and collector electrode 24.
  • the emitter electrode 52 is formed above the semiconductor substrate 10 and interlayer insulating film 38.
  • the drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10.
  • the drift region 18 is, as an example, N-type.
  • the drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein.
  • the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.
  • a buffer region 20 of the first conductivity type may be provided below the drift region 18.
  • the buffer region 20 is N-type.
  • the doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18.
  • the buffer region 20 may be a field stop layer that prevents the depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.
  • the collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10.
  • the collector electrode 24 is formed of a conductive material such as a metal.
  • the base region 14 is a region of the second conductivity type provided above the drift region 18.
  • the doping concentration of the base region 14 may be the same as or different from the doping concentration of the anode region 19.
  • the doping concentration of the base region 14 may be 1E16 cm ⁇ 3 or more and 1E18 cm ⁇ 3 or less.
  • the base region 14 may be provided below the emitter region 12.
  • the base region 14 is provided in contact with the gate trench portion 40.
  • the base region 14 may be provided in contact with the dummy trench portion 30.
  • the accumulation region 16 is provided below the base region 14 in the depth direction of the semiconductor substrate 10, and is a region of a first conductivity type with a higher doping concentration than the drift region 18.
  • the accumulation region 16 is an N+ type, for example.
  • the accumulation region 16 is provided in the main region 75 of the transistor section 70, and is not provided in the diode section 80.
  • One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21.
  • Each trench portion is provided from the front surface 21 to the drift region 18.
  • each trench portion also penetrates these regions to reach the drift region 18.
  • the trench portion penetrating the doped region is not limited to being manufactured in the order of forming the doped region and then the trench portion.
  • the trench portion penetrating the doped region also includes a case where a doped region is formed between the trench portions after the trench portions are formed.
  • the gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21.
  • the gate insulating film 42 is formed to cover the inner wall of the gate trench.
  • the gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench.
  • the gate conductive portion 44 is formed inside the gate trench, further inside than the gate insulating film 42.
  • the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10.
  • the gate conductive portion 44 is formed of a conductive material such as polysilicon.
  • the gate trench portion 40 is covered by an interlayer insulating film 38 on the front surface 21.
  • the gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side across the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer on the surface layer of the interface of the base region 14 that contacts the gate trench.
  • the dummy trench portion 30 may have the same structure as the gate trench portion 40.
  • the dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side.
  • the dummy insulating film 32 is formed to cover the inner wall of the dummy trench.
  • the dummy conductive portion 34 is formed inside the dummy trench and is formed further inward than the dummy insulating film 32.
  • the dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10.
  • the dummy trench portion 30 is covered by an interlayer insulating film 38 on the front surface 21.
  • the interlayer insulating film 38 is provided on the front surface 21.
  • An emitter electrode 52 is provided above the interlayer insulating film 38.
  • the interlayer insulating film 38 is provided with one or more trench contact portions 60 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10.
  • the contact holes 55 and 56 may also be provided penetrating the interlayer insulating film 38, similar to the trench contact portions 60.
  • the trench contact portion 60 penetrates the interlayer insulating film 38 and the emitter region 12 to reach the base region 14 or the anode region 19.
  • the trench contact portion 60 electrically connects the emitter electrode 52 and the semiconductor substrate 10.
  • the depth of the lower end of the trench contact portion 60 is deeper than the depth of the lower end of the emitter region 12 in the depth direction of the semiconductor substrate 10. This improves the latch-up resistance of the semiconductor device 100.
  • the first contact region 73 is provided at the lower end of the trench contact portion 60.
  • the first contact region 73 may be provided so as to cover the bottom and part of the sidewall of the trench contact portion 60.
  • the first contact region 73 is provided in the transistor portion 70 and spaced apart from the emitter region 12.
  • the first contact region 73 is provided in the transistor portion 70 and spaced apart from the gate trench portion 40.
  • the first contact region 73 is formed by injecting a dopant through the trench contact portion 60.
  • the first contact region 73 may be formed first, and then the trench contact portion 60 may be provided.
  • the resistance of the bottom of the trench contact portion 60 in the transistor portion 70 is reduced, and latch-up breakdown can be suppressed.
  • the second contact region 83 is provided at the lower end of the trench contact portion 60.
  • the second contact region 83 may be provided so as to cover the bottom and part of the sidewall of the trench contact portion 60.
  • the second contact region 83 is formed by injecting a dopant through the trench contact portion 60.
  • the trench contact portion 60 may be provided after the second contact region 83 is formed first.
  • the doping concentration of the second contact region 83 and the doping concentration of the first contact region 73 may be the same or different. In this example, the doping concentration of the second contact region 83 is greater than the doping concentration of the first contact region 73.
  • the amount of the second conductive type dopant per unit volume in the mesa portion 81 of the diode portion 80 may be the same as or different from the amount of the second conductive type dopant per unit volume in the mesa portion 71 of the transistor portion 70.
  • the amount of the second conductive type dopant per unit volume in the mesa portion 71 of the transistor portion 70 may be the amount obtained by dividing the total amount of dopant contained in the base region 14 and the first contact region 73 by the volume of the mesa portion 71.
  • the amount of the second conductive type dopant per unit volume in the mesa portion 81 of the diode portion 80 may be the amount obtained by dividing the total amount of dopant contained in the anode region 19 and the second contact region 83 by the volume of the mesa portion 81.
  • the amount of the second conductive type dopant per unit volume in the mesa portion 81 of the diode portion 80 is equal to or greater than the amount of the second conductive type dopant per unit volume in the mesa portion 71 of the transistor portion 70. This suppresses hole injection from the transistor section 70 to the diode section 80, reducing the reverse recovery loss Err.
  • the amount of the second conductivity type dopant per unit volume in the mesa portion 81 of the diode portion 80 may be the same as or different from the amount of the second conductivity type dopant per unit volume in the mesa portion 71 of the main region 75.
  • the amount of the second conductivity type dopant per unit volume in the mesa portion 81 of the diode portion 80 is equal to or greater than the amount of the second conductivity type dopant per unit volume in the mesa portion 71 of the main region 75.
  • the collector region 22 is provided on the rear surface 23 of the semiconductor substrate 10 in the transistor portion 70.
  • the collector region 22 is a region of the second conductivity type that has a higher doping concentration than the base region 14.
  • the cathode region 82 is provided on the rear surface 23 of the semiconductor substrate 10 in the diode portion 80.
  • the cathode region 82 is a region of the first conductivity type having a doping concentration higher than that of the drift region 18.
  • the doping concentration of the cathode region may be 1E18 cm ⁇ 3 or more and may be 1E21 cm ⁇ 3 or less.
  • the doping concentration of the cathode region 82 may be changed according to the amount per unit volume of the second conductivity type dopant in the mesa portion 71 of the transistor portion 70 and the amount per unit volume of the second conductivity type dopant in the mesa portion 81 of the diode portion 80. This improves the trade-off between the forward voltage Vf and the reverse recovery loss Err in the diode portion 80. Details will be described later.
  • the semiconductor device 100 of this example does not have a lifetime control region inside the semiconductor substrate 10. This eliminates the need for additional ion implantation or the like to form the lifetime control region, thereby reducing costs.
  • FIG. 1C is an example of the bb' cross section in FIG. 1A.
  • the bb' cross section is a YZ plane along the trench contact portion 60 in the transistor portion 70.
  • the first contact region 73 is provided extending in the extension direction of the trench contact portion 60.
  • the first contact region 73 may cover the bottom and part of the sidewall of the trench contact portion 60.
  • the first contact region 73 may cover the sidewall of the trench contact portion 60 at the end in the trench extension direction (in this example, the Y-axis direction).
  • Well region 17 is a region of a second conductivity type provided closer to front surface 21 of semiconductor substrate 10 than drift region 18.
  • Well region 17 is an example of a well region provided on the edge side of semiconductor device 100.
  • Well region 17 is, as an example, a P+ type.
  • the well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided.
  • the diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30.
  • a portion of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 17.
  • the bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.
  • FIG. 1D is an example of the cc' cross section in FIG. 1A.
  • the cc' cross section is a YZ plane along the trench contact portion 60 in the diode portion 80.
  • the second contact region 83 is provided extending in the extension direction of the trench contact portion 60.
  • the second contact region 83 may cover a bottom portion and a portion of a sidewall of the trench contact portion 60.
  • the second contact region 83 may be provided discretely in the extension direction of the trench contact portion 60.
  • the second contact region 83 may cover a sidewall of the trench contact portion 60 at the end portion in the trench extension direction (the Y-axis direction in this example).
  • the first cathode portion 181 is a region of a first conductivity type having a higher doping concentration than the drift region 18.
  • the first cathode portion 181 is an N-type.
  • the width of the first cathode portion 181 in the trench extension direction (Y-axis direction) may be greater than the width of the second cathode portion 182 in the trench extension direction.
  • the second cathode portion 182 is a second conductivity type region provided adjacent to the first cathode portion 181 on the rear surface 23 of the semiconductor substrate 10. That is, the second cathode portion 182 may be in direct contact with the first cathode portion 181. In one example, the second cathode portion 182 is P-type.
  • the first cathode portion 181 may be formed by ion implanting an N-type dopant after a P-type dopant has been ion implanted in an ion implantation process for forming the second cathode portion 182.
  • the second cathode portion 182 may be formed by ion implanting a P-type dopant after an N-type dopant has been ion implanted in an ion implantation process for forming the first cathode portion 181.
  • the first cathode portion 181 and the second cathode portion 182 are arranged so as to form a boundary where they are in contact with each other.
  • the first cathode portion 181 and the second cathode portion 182 may be arranged alternately in any direction.
  • the first cathode portion 181 and the second cathode portion 182 are arranged alternately in the trench extension direction (e.g., the Y-axis direction), but may also be arranged alternately in the trench arrangement direction (e.g., the X-axis direction).
  • the first cathode portion 181 and the second cathode portion 182 may be arranged in a stripe pattern when viewed from above.
  • One of the first cathode portion 181 and the second cathode portion 182 may be formed in a dot pattern.
  • the second cathode portion 182 may be provided in the cathode region 82 in the diode portion 80 of this example.
  • the first cathode portion 181 and the second cathode portion 182 may be provided alternately in the cathode region 82 in the diode portion 80 of this example.
  • the first cathode portion 181 and the second cathode portion 182 may be provided so as to be in contact with each other in the cathode region 82 in the diode portion 80 of this example. This reduces the concentration of the first conductivity type dopant in the cathode region 82, and improves the forward voltage Vf of the diode portion 80.
  • FIG. 2 is a diagram showing a modified top surface of the semiconductor device 100. The differences from FIG. 1A will be explained using FIG. 2.
  • the emitter region 12 is provided on the front surface 21 of the semiconductor substrate 10, extending in the extension direction of the multiple trench portions.
  • the emitter region 12 may be provided extending from one base region 14 adjacent to the well region 17 in the Y-axis direction to the other base region 14. This reduces the amount of second conductivity type dopant per unit volume in the transistor portion 70, reduces the amount of holes injected from the transistor portion 70 to the diode portion 80, and reduces the forward voltage Vf of the diode portion 80.
  • the doping concentration of the anode region 19 is higher than the doping concentration of the base region 14.
  • the anode region 19 is P-type. This results in a greater amount of holes being injected from the front surface 21 to the back surface 23 of the diode section 80 than the amount of holes being injected from the transistor section 70 to the diode section 80, thereby reducing the forward voltage Vf of the diode section 80.
  • FIG. 3A is a diagram showing a modified example of the top surface of the semiconductor device 100. The differences from FIG. 1A will be explained using FIG. 3A.
  • the width of the contact hole 54a in the transistor section 70 in the trench arrangement direction and the width of the contact hole 54b in the diode section 80 in the trench arrangement direction may be the same or different.
  • the width of the trench contact section 60a in the transistor section 70 in the trench arrangement direction and the width of the trench contact section 60b in the diode section 80 in the trench arrangement direction may be the same or different.
  • the width of the trench contact section 60b in the diode section 80 in the trench arrangement direction is the same as the width of the trench contact section 60a in the transistor section 70.
  • the width of the trench contact section 60b in the diode section 80 in the trench arrangement direction is larger than the width of the trench contact section 60a in the transistor section 70.
  • the trench contact portion 60 may be provided in the mesa portion provided between the gate trench portion 40 and the dummy trench portion 30, closer to the dummy trench portion 30 than the gate trench portion 40.
  • the trench contact portion 60a in the transistor portion 70 is provided closer to the dummy trench portion 30 than the gate trench portion 40.
  • the emitter region 12 does not need to be provided between the trench contact section 60a and the dummy trench section 30.
  • the base region 14 is provided between the trench contact section 60a and the dummy trench section 30.
  • FIG. 3B is an example of the d-d' cross section in FIG. 3A.
  • the d-d' cross section is an XZ plane that passes through the emitter region 12 in the transistor section 70. The differences from FIG. 1B will be explained using FIG. 3B.
  • the width of the trench contact portion 60 in the diode portion 80 may be larger than the width of the trench contact portion 60a in the transistor portion 70.
  • the width of the trench contact portion 60 may be the opening width at the upper end of the interlayer insulating film 38, the width at the bottom of the trench contact portion 60, or the width at the same depth as the front surface 21 of the semiconductor substrate 10.
  • the width W60b of the trench contact portion 60b in the diode portion 80 is larger than the width W60a of the trench contact portion 60a in the transistor portion 70.
  • the trench contact portion 60a in the transistor portion 70 may be provided closer to the dummy trench portion 30 than to the gate trench portion 40.
  • the distance D1 between the center of the trench contact portion 60a and the gate trench portion 40 is greater than the distance D2 between the center of the trench contact portion 60a and the dummy trench portion 30. This allows the first contact region 73 to be disposed away from the gate trench portion 40, and reduces the variation in threshold voltage caused by the low concentration portion of the first contact region 73 formed by the diffusion of the first contact region 73 in the trench arrangement direction (X-axis direction) coming into contact with the sidewall of the gate trench portion 40.
  • the second contact region 83 may be provided so as to be in contact with the dummy trench section 30.
  • the second contact region 83 is provided in the mesa section 81 sandwiched between the two dummy trench sections 30 of the diode section 80, extending from the sidewall of one dummy trench section 30 to the sidewall of the other dummy trench section 30. This allows the amount of the second conductivity type dopant per unit volume in the diode section 80 to be greater than the amount of the second conductivity type dopant per unit volume in the transistor section 70.
  • FIG. 4 is a diagram showing a modified top surface of the semiconductor device 100.
  • the semiconductor device 100 has a transistor portion.
  • the semiconductor device 100 includes a drift region 18, a base region 14, an emitter region 12, a first contact region 73, and a trench contact portion 60.
  • the configuration of each of these regions may be the same as the configuration of the semiconductor device 100 described thus far, and therefore will not be described.
  • the first contact region 73 is not provided on the front surface 21.
  • the emitter regions 12 and the base regions 14 are alternately provided on the front surface 21 of the semiconductor device 100 in the trench extension direction.
  • FIG. 5A is a diagram showing the relationship between the doping concentration of the cathode region 82 and the forward voltage Vf of the diode section 80.
  • the horizontal axis represents the doping concentration of the cathode region 82, and the vertical axis represents the forward voltage Vf of the diode section 80.
  • the amount of the second conductivity type dopant per unit volume in the mesa section 81 of the diode section 80 is plotted. Each value is normalized.
  • the amount of the second conductivity type dopant per unit volume in the mesa portion 81 of the diode portion 80 is different.
  • the doping concentration Qp1 of the second conductivity type dopant in Example 1 shown by a square, is smaller than the doping concentration Qp2 in Example 2, shown by a circle.
  • the doping concentration Qp2 in Example 2 is smaller than the doping concentration Qp3 in Example 3, shown by a triangle.
  • the forward voltage Vf of the diode section 80 increases.
  • the forward voltage Vf of the diode section 80 can be increased by providing a second cathode section 182 in the cathode region 82.
  • the value of the forward voltage Vf of the diode section 80 can be adjusted by adjusting the amount per unit volume of the second conductivity type dopant in the mesa section 81 of the diode section 80 and the doping concentration of the cathode region 82.
  • FIG. 5B is a diagram showing the relationship between the forward voltage Vf and the reverse recovery loss Err of the diode section 80.
  • the horizontal axis represents the forward voltage Vf of the diode section 80, and the vertical axis represents the reverse recovery loss Err, and the plot is performed by changing the amount per unit volume of the second conductivity type dopant in the mesa section 81 of the diode section 80.
  • Each numerical value is normalized.
  • the relationship of the amount of the second conductivity type dopant per unit volume in the mesa portion 81 of the diode portion 80 is as described above.
  • the forward voltage Vf of the diode portion 80 decreases and the reverse recovery loss Err increases.
  • the relationship between the forward voltage Vf and the reverse recovery loss Err can be adjusted.
  • FIG. 6 is a flow chart showing an example of a method for manufacturing the semiconductor device 100.
  • the method for manufacturing the semiconductor device 100 of this example includes a step S100 for forming a plurality of trenches in the semiconductor substrate 10, a step S110 for forming a drift region 18 in the semiconductor substrate 10, a step S120 for forming the base region 14, the emitter region 12, and the anode region 19, a first ion implantation step S130 for forming the first contact region 73, and a second ion implantation step S140 for forming the second contact region 83.
  • the step S100 for forming a plurality of trenches in the semiconductor substrate 10 the step S110 for forming the drift region 18 in the semiconductor substrate 10
  • the step S120 for forming the base region 14, the emitter region 12, and the anode region 19 are contents that can be understood by anyone with ordinary knowledge, so explanations will be omitted.
  • the dose of ions implanted in the first ion implantation step S130 may be different from the dose of ions implanted in the second ion implantation step S140.
  • the first ion implantation step S130 and the second ion implantation step S140 may be performed at different times using different masks.
  • the dose of the second conductivity type dopant implanted in the second ion implantation step S140 is greater than the dose of the second conductivity type dopant implanted in the first ion implantation step S130. This allows the amount of the second conductivity type dopant per unit volume in the diode section 80 to be greater than the amount of the second conductivity type dopant per unit volume in the transistor section 70.
  • the first ion implantation step S130 and the second ion implantation step S140 may be the same ion implantation step.
  • the first ion implantation step S130 and the second ion implantation step S140 may be performed simultaneously using the same mask.
  • the first contact region 73 and the second contact region 83 may be formed simultaneously using the same mask, or may be formed at different times.
  • 10 semiconductor substrate, 12: emitter region, 14: base region, 16: accumulation region, 17: well region, 18: drift region, 19: anode region, 20: buffer region, 21: front surface, 22: collector region, 23: back surface, 24: collector electrode, 25: connection portion, 30: dummy trench portion, 31: extension portion, 32: dummy insulating film, 33: connection portion, 34: dummy conductive portion, 38: interlayer insulating film, 40: gate trench portion, 41: extension portion, 42: gate 1.

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JP2021064673A (ja) * 2019-10-11 2021-04-22 富士電機株式会社 半導体装置
WO2022004084A1 (ja) * 2020-07-03 2022-01-06 富士電機株式会社 半導体装置
JP2023019322A (ja) * 2021-07-29 2023-02-09 富士電機株式会社 半導体装置

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JP2021064673A (ja) * 2019-10-11 2021-04-22 富士電機株式会社 半導体装置
WO2022004084A1 (ja) * 2020-07-03 2022-01-06 富士電機株式会社 半導体装置
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