WO2024241188A1 - 半導体装置、及び半導体装置の作製方法 - Google Patents

半導体装置、及び半導体装置の作製方法 Download PDF

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Publication number
WO2024241188A1
WO2024241188A1 PCT/IB2024/054866 IB2024054866W WO2024241188A1 WO 2024241188 A1 WO2024241188 A1 WO 2024241188A1 IB 2024054866 W IB2024054866 W IB 2024054866W WO 2024241188 A1 WO2024241188 A1 WO 2024241188A1
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Prior art keywords
layer
conductive layer
insulating layer
semiconductor
conductive
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
國武寛司
木村肇
村川努
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to CN202480034667.5A priority Critical patent/CN121195614A/zh
Priority to KR1020257038692A priority patent/KR20260013188A/ko
Priority to JP2025521577A priority patent/JPWO2024241188A1/ja
Publication of WO2024241188A1 publication Critical patent/WO2024241188A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics

Definitions

  • One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.
  • a CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) that are processed from semiconductor wafers and made into chips, and on which electrodes that serve as connection terminals are formed.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.
  • transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices.
  • ICs integrated circuits
  • Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.
  • Patent Document 1 discloses a low-power consumption CPU that utilizes the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by utilizing the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple overlapping memory cells.
  • Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Alternatively, an object of one embodiment of the present invention is to provide a low-cost semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device having a transistor with favorable electrical characteristics. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device having a transistor with high on-state current. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Alternatively, an object of one embodiment of the present invention is to provide a novel semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a method for manufacturing the semiconductor device.
  • One aspect of the present invention includes a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer, the first transistor having a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth insulating layer, the second transistor having a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a fifth insulating layer, the first insulating layer being located on the first conductive layer, and the second conductive layer being located on the first insulating layer.
  • the first conductive layer has a first recess
  • the first insulating layer and the second conductive layer have a first opening at a position overlapping the first recess
  • the first semiconductor layer contacts an upper surface of the second conductive layer and the first recess, and contacts a side surface of the second conductive layer and a side surface of the first insulating layer within the first opening
  • the fourth insulating layer has a region located on the second conductive layer and a region located on the first semiconductor layer within the first opening
  • the third conductive layer has a first recess
  • the first conductive layer has a first recess
  • the first insulating layer has a first recess
  • the first semiconductor layer has a first recess
  • the second conductive layer has a first recess.
  • the opening has a region facing the first semiconductor layer with the fourth insulating layer sandwiched therebetween, the third conductive layer has a region overlapping the second conductive layer via the fourth insulating layer, the third conductive layer has a second recess, the second insulating layer is located on the third conductive layer, the fourth conductive layer is located on the second insulating layer, the second insulating layer and the fourth conductive layer have a second opening at a position overlapping the second recess, the second semiconductor layer is in contact with an upper surface of the fourth conductive layer and the second recess, and
  • the fifth insulating layer is in contact with the side of the fourth conductive layer and the side of the second insulating layer inside the second opening, the fifth insulating layer is located on the second semiconductor layer inside the second opening, the third insulating layer has a region that overlaps with the fourth conductive layer via the second semiconductor layer and has a third opening at a position that overlaps with the second opening, and the fifth conductive layer has a region that faces the second
  • the second opening may at least partially overlap the first opening.
  • the first conductive layer may have a sixth conductive layer and a seventh conductive layer on the sixth conductive layer
  • the third conductive layer may have an eighth conductive layer and a ninth conductive layer on the eighth conductive layer
  • the seventh conductive layer may have a first recess
  • the ninth conductive layer may have a second recess.
  • a sixth conductive layer may be provided, and the sixth conductive layer may be arranged to contact the upper surface of the fifth conductive layer.
  • the film thickness of the third insulating layer in the region overlapping with the fourth conductive layer and the second semiconductor layer may be thicker than the film thickness of the fourth insulating layer.
  • the fifth insulating layer may be at least partially located inside the third opening.
  • the first transistor has a sixth conductive layer
  • the second transistor has a seventh conductive layer
  • the first insulating layer has a first layer and a second layer on the first layer
  • the second insulating layer has a third layer and a fourth layer on the third layer
  • the sixth conductive layer is located on the first layer
  • the seventh conductive layer is located on the third layer
  • the second layer is an upper surface of the sixth conductive layer and and the side surface of the seventh conductive layer
  • the fourth layer covers the top surface and side surface of the seventh conductive layer
  • the first semiconductor layer has a region that faces the sixth conductive layer across the second layer and faces the third conductive layer across the fourth insulating layer in a cross-sectional view
  • the second semiconductor layer has a region that faces the seventh conductive layer across the fourth layer and faces the fifth conductive layer across the fifth insulating layer in a cross-sectional view.
  • the first semiconductor layer and the second semiconductor layer each have an oxide semiconductor
  • the oxide semiconductor has one or more selected from indium, element M, and zinc
  • element M may be one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the first insulating layer has a first region in contact with the first semiconductor layer
  • the second insulating layer has a second region in contact with the second semiconductor layer
  • the first region and the second region may each contain a halogen element
  • the halogen element may be one or more selected from chlorine, fluorine, bromine, and iodine.
  • the first semiconductor layer has a first region in contact with the bottom surface of the first recess and a second region in contact with the top surface of the second conductive layer
  • the second semiconductor layer has a third region in contact with the bottom surface of the second recess and a fourth region in contact with the top surface of the fourth conductive layer
  • each of the first to fourth regions may contain boron or phosphorus.
  • One aspect of the present invention includes forming a first conductive layer, forming a first insulating layer on the first conductive layer, forming a second conductive layer on the first insulating layer, forming a first opening in the second conductive layer and the first insulating layer at a position overlapping the first conductive layer, and forming a first recess in the first conductive layer so as to overlap the first opening, forming a first semiconductor layer in contact with the upper surface of the second conductive layer and the first recess, and inside the first opening in contact with a side of the second conductive layer and a side of the first insulating layer, and forming a first semiconductor layer.
  • a second insulating layer is formed so as to have a region located on the second conductive layer and a region located on the first semiconductor layer inside the first opening
  • a third conductive layer is formed so as to have a region facing the first semiconductor layer with the second insulating layer interposed therebetween inside the first opening and a region overlapping with the second conductive layer via the second insulating layer
  • a third insulating layer is formed on the third conductive layer
  • a fourth conductive layer is formed on the third insulating layer.
  • a second opening is formed in the third conductive layer at a position where the third conductive layer overlaps the fourth conductive layer, and a second recess is formed in the third conductive layer so as to overlap the second opening;
  • a second semiconductor layer is formed in contact with an upper surface of the fourth conductive layer and the second recess, and in contact with a side surface of the fourth conductive layer and a side surface of the third insulating layer within the second opening; and by processing the second semiconductor layer and the fourth conductive layer, a part of the upper surface of the third insulating layer is exposed, and at least a part of the third insulating layer is located within the second opening.
  • This is a method for manufacturing a semiconductor device which includes forming a sacrificial layer so as to cover the fourth conductive layer, the second semiconductor layer, and the sacrificial layer, performing planarization treatment on the fourth insulating layer and the sacrificial layer to planarize the upper surface of the sacrificial layer, removing the sacrificial layer, forming a fifth insulating layer so as to cover the second opening, forming a fifth conductive layer on the fifth insulating layer, and performing planarization treatment on the fifth conductive layer to remove the region of the fifth conductive layer and the fifth insulating layer that overlaps with the upper surface of the fourth insulating layer.
  • a second opening may be formed at a position where at least a portion of the second opening overlaps with the first opening.
  • a sixth conductive layer may be formed so as to be in contact with the upper surface of the fifth conductive layer.
  • the fourth insulating layer may be formed to have a thickness greater than that of the second insulating layer.
  • a semiconductor device with high operating speed can be provided.
  • a low-cost semiconductor device can be provided.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a semiconductor device having a transistor with favorable electrical characteristics can be provided.
  • a semiconductor device having a transistor with high on-state current can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with low power consumption can be provided.
  • a novel semiconductor device can be provided.
  • a method for manufacturing the above semiconductor device can be provided.
  • FIGs. 1A to 1C are circuit diagrams showing an example of a memory cell
  • FIGs. 1D and 1E are plan views showing an example of a semiconductor device
  • FIGs. 1F and 1G are cross-sectional views showing an example of a semiconductor device.
  • 2A and 2B are cross-sectional and plan views illustrating an example of a semiconductor device.
  • 3A to 3D are diagrams for explaining the concept of the heat treatment.
  • 4A and 4B are cross-sectional views showing an example of a semiconductor device.
  • 5A and 5B are plan views and cross-sectional views illustrating an example of a semiconductor device.
  • 6A and 6B are cross-sectional views showing an example of a semiconductor device.
  • 7A and 7B are cross-sectional views showing an example of a semiconductor device.
  • 8A and 8B are cross-sectional views showing an example of a semiconductor device.
  • 9A and 9B are cross-sectional views showing an example of a semiconductor device.
  • 10A and 10B are cross-sectional views showing an example of a semiconductor device.
  • 11A and 11B are plan views and cross-sectional views illustrating an example of a semiconductor device.
  • 12A to 12F are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 13A to 13D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 14A to 14D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 15A to 15E are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 16A is a plan view of an example of a storage device
  • FIG 16B is a cross-sectional view of the example of the storage device.
  • FIG. 17 is a cross-sectional view showing an example of a storage device.
  • FIG. 18 is a cross-sectional view showing an example of a storage device.
  • FIG. 19 is a block diagram illustrating a configuration example of a semiconductor device.
  • 20A and 20B are perspective views showing an example of a semiconductor device.
  • FIG. 21 is a block diagram illustrating the CPU.
  • 22A and 22B are perspective views showing an example of a semiconductor device.
  • 23A and 23B are perspective views showing an example of a semiconductor device.
  • 24A and 24B are diagrams showing various storage devices by hierarchical level.
  • FIGS. 25A and 25B are diagrams illustrating an example of an electronic component.
  • Fig. 26A to Fig. 26C are diagrams showing an example of a mainframe computer
  • Fig. 26D is a diagram showing an example of space equipment
  • Fig. 26E is a diagram showing an example of a storage system applicable to a data center.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking).
  • an ordinal number attached to a component in one place in this specification may not match an ordinal number attached to the same component in another place in this specification or in the claims.
  • a transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and switching operations that control conduction or non-conduction.
  • transistor includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).
  • a transistor using an oxide semiconductor or a metal oxide in a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide in a channel formation region may be referred to as an OS transistor.
  • a transistor having silicon in a channel formation region may be referred to as a Si transistor.
  • a transistor is an element having at least three terminals including a gate, a drain, and a source.
  • a transistor has a region (also called a channel formation region) in which a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and drain through the channel formation region.
  • a channel formation region refers to a region through which a current mainly flows.
  • source and drain may be interchanged when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms “source” and “drain” may be used interchangeably.
  • the impurity of a semiconductor refers to, for example, anything other than the main component constituting the semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be said to be an impurity.
  • the defect state density of the semiconductor may be increased or the crystallinity may be reduced.
  • the semiconductor is an oxide semiconductor
  • examples of the impurity that changes the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor.
  • Specific examples of the impurity include, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • water may also function as an impurity.
  • oxygen vacancies also referred to as V O
  • V O oxygen vacancies
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen.
  • An oxynitride refers to a material whose composition contains more nitrogen than oxygen.
  • SIMS secondary ion mass spectrometry
  • XPS X-ray photoelectron spectroscopy
  • film and “layer” can be interchanged depending on the circumstances.
  • conductive layer can be changed to the term “conductive film.”
  • insulating film can be changed to the term “insulating layer.”
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less.
  • approximately parallel refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • Perfect refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less.
  • approximately perpendicular refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • electrically connected includes cases where the connection is made via "something that has some kind of electrical action.”
  • something that has some kind of electrical action is not particularly limited as long as it allows the transmission and reception of electrical signals between the objects to be connected.
  • something that has some kind of electrical action includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.
  • the off-state current refers to leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state).
  • the off state refers to a state in which the voltage Vgs between the gate and source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor).
  • normally on refers to a state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate.
  • Normally off refers to a state in which no current flows through the transistor when no potential is applied to the gate or when a ground potential is applied to the gate.
  • a tapered shape refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.
  • A when it is stated that A is located on B, at least a part of A is located on B. Therefore, for example, it can be rephrased as A has an area located on B.
  • a contacts B or A overlaps B when it is stated that A contacts B or A overlaps B, at least a part of A contacts B or overlaps B. Therefore, it can be rephrased as A has an area contacting B or A has an area overlapping B, respectively.
  • a covers B at least a part of A covers B. Therefore, for example, it can be rephrased as A has an area covering B.
  • arrows indicating the X direction, Y direction, and Z direction may be used.
  • the "X direction” is the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction” and "Z direction.”
  • the X direction, Y direction, and Z direction are directions that intersect with each other.
  • the X direction, Y direction, and Z direction are directions that are perpendicular to each other.
  • a semiconductor device is a memory device provided with a memory cell having a first transistor and a second transistor on the first transistor.
  • the semiconductor device according to one embodiment of the present invention has a first insulating layer, a second insulating layer, and a third insulating layer in addition to the first and second transistors.
  • the first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth insulating layer.
  • the second transistor has a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a fifth insulating layer.
  • the first conductive layer functions as one of the source electrode and drain electrode of the first transistor.
  • the second conductive layer functions as the other of the source electrode and drain electrode of the first transistor.
  • the third conductive layer functions as the gate electrode of the first transistor and one of the source electrode and drain electrode of the second transistor.
  • the fourth conductive layer functions as the other of the source electrode and drain electrode of the second transistor.
  • the fifth conductive layer functions as the gate electrode of the second transistor.
  • the fourth insulating layer functions as the gate insulating layer of the first transistor.
  • the fifth insulating layer functions as the gate insulating layer of the second transistor.
  • a first insulating layer is provided between the first conductive layer and the second conductive layer.
  • a first opening is provided in the first insulating layer and the second conductive layer, reaching the first conductive layer.
  • the first semiconductor layer contacts the top surface of the first conductive layer, the side surface of the second conductive layer, and the side surface of the first insulating layer inside the first opening.
  • the first semiconductor layer also contacts the top surface of the second conductive layer.
  • the fourth insulating layer has a region located on the first semiconductor layer inside the first opening.
  • the third conductive layer has a region facing the first semiconductor layer with the fourth insulating layer sandwiched between them inside the first opening.
  • a second insulating layer is provided between the third conductive layer and the fourth conductive layer.
  • a second opening is provided in the second insulating layer and the fourth conductive layer, reaching the third conductive layer.
  • the second semiconductor layer contacts the upper surface of the third conductive layer, the side of the fourth conductive layer, and the side of the second insulating layer inside the second opening.
  • the second semiconductor layer also contacts the upper surface of the fourth conductive layer.
  • the fifth insulating layer has a region located on the second semiconductor layer inside the second opening.
  • the fifth conductive layer has a region facing the second semiconductor layer inside the second opening, sandwiching the fifth insulating layer.
  • a first recess is provided in the first conductive layer, and a second recess is provided in the second conductive layer.
  • the semiconductor device of one embodiment of the present invention can be a semiconductor device with high operating speed.
  • the fourth insulating layer functioning as a gate insulating layer of the first transistor is provided to cover the first semiconductor layer and the second conductive layer.
  • the third conductive layer functioning as a gate electrode of the first transistor is provided to have a region overlapping with the second conductive layer via the fourth insulating layer.
  • the semiconductor device of one embodiment of the present invention can be a low-cost semiconductor device. Furthermore, by not forming a capacitor in the memory cell, the area occupied by the memory cell can be reduced in some cases. In this case, the semiconductor device of one embodiment of the present invention can be a semiconductor device that can be miniaturized or highly integrated.
  • a third insulating layer is provided on the second semiconductor layer so as to have a region overlapping with a fourth conductive layer that functions as the other of the source electrode and drain electrode of the second transistor.
  • the third insulating layer is provided so as to have a region overlapping with the fourth conductive layer via the second semiconductor layer.
  • the third insulating layer has a third opening at a position overlapping with the second opening.
  • a fifth conductive layer is provided inside the third opening.
  • a sixth conductive layer is provided so as to be in contact with the top surface of the third insulating layer and the top surface of the fifth conductive layer that functions as the gate electrode of the second transistor.
  • the sixth conductive layer functions as a gate wiring.
  • a third insulating layer is provided between the fourth conductive layer and the sixth conductive layer.
  • the film thickness of the third insulating layer for example the film thickness of the third insulating layer in the region overlapping with the fourth conductive layer and the second semiconductor layer, is thicker than the film thickness of the fourth insulating layer that functions as the gate insulating layer of the first transistor. Therefore, the parasitic capacitance between the fourth conductive layer and the sixth conductive layer can be made smaller than the parasitic capacitance between the second conductive layer and the third conductive layer.
  • the second transistor can be a transistor with good electrical characteristics.
  • the second transistor can be a transistor that operates at high speed. Therefore, a semiconductor device of one embodiment of the present invention can be a semiconductor device that includes a transistor with good electrical characteristics.
  • a groove may be provided instead of the opening.
  • the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction.
  • the channel length direction has a component in the height direction (vertical direction), and therefore the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or a vertical channel transistor.
  • VFET Vertical Field Effect Transistor
  • the source electrode, the semiconductor layer, and the drain electrode can be stacked, so the area occupied can be significantly reduced compared to a so-called planar type transistor in which the semiconductor layer is arranged in a planar shape.
  • ⁇ Configuration Example 1 of Semiconductor Device> 1A is a circuit diagram illustrating a configuration example of a memory cell 10 included in a semiconductor device of one embodiment of the present invention.
  • the memory cell 10 includes a transistor 100 and a transistor 200.
  • One of the source and drain of the transistor 100 is electrically connected to wiring 13.
  • the other of the source and drain of the transistor 100 is electrically connected to wiring 15.
  • the gate of the transistor 100 is electrically connected to one of the source and drain of the transistor 200.
  • the other of the source and drain of the transistor 200 is electrically connected to wiring 23.
  • the gate of the transistor 200 is electrically connected to wiring 21.
  • a node to which the gate of the transistor 100 and one of the source and drain of the transistor 200 are connected is referred to as node ND1.
  • a capacitance Cp is formed between an electrode that functions as the other of the source and drain of transistor 100, the gate of transistor 100, and an electrode that functions as one of the source and drain of transistor 200.
  • the wiring 21 functions as a word line. A signal that controls the on/off state of the transistor 200 is supplied to the wiring 21.
  • the wiring 23 functions as a bit line.
  • a data signal to be supplied to the memory cell 10 is supplied to the wiring 23.
  • the transistor 200 When the transistor 200 is in an on state, data corresponding to the potential of the wiring 23 is written to the memory cell 10.
  • the transistor 200 When the transistor 200 is in an off state, the data written to the memory cell 10 is held. Specifically, the potential of the node ND1 is held.
  • the wiring 13 functions as a bit line.
  • the wiring 15 functions as a power supply line and is supplied with a power supply potential.
  • the potential of the node ND1 becomes a potential corresponding to the data.
  • a current having a magnitude corresponding to the potential of the node ND1 flows between the wiring 15 and the wiring 13.
  • the potential of the wiring 13 becomes a potential corresponding to the data stored in the memory cell 10. In this way, the data stored in the memory cell 10 can be read.
  • the reading can be a non-destructive read.
  • wiring 23 can be called a write bit line
  • wiring 13 can be called a read bit line
  • FIGS. 1B and 1C are circuit diagrams showing examples of the configuration of a memory cell 10, and show an example in which the position of capacitance Cp is different from that of the memory cell 10 shown in FIG. 1A.
  • FIG. 1B shows an example in which capacitance Cp is formed between an electrode that functions as one of the source and drain of transistor 100, and an electrode that functions as the gate of transistor 100 and one of the source and drain of transistor 200.
  • FIG. 1C shows an example in which capacitance Cp is formed between an electrode that functions as the gate of transistor 200, and an electrode that functions as the gate of transistor 100 and one of the source and drain of transistor 200.
  • FIG. 1D is a plan view showing an example of the configuration of transistor 100.
  • FIG. 1E is a plan view showing an example of the configuration of transistor 200. It can also be said that the plan views shown in FIG. 1D and FIG. 1E show example configurations in the XY plane. Note that in the plan views of FIG. 1D and FIG. 1E, some elements have been omitted to clarify the figures. The same applies to the subsequent plan views.
  • Figure 1F is a cross-sectional view taken along dashed lines A1-A2 in Figures 1D and 1E.
  • Figure 1G is a cross-sectional view taken along dashed lines A3-A4 in Figures 1D and 1E.
  • Figure 1F can also be said to show an example of the configuration of the XZ plane.
  • Figure 1G can also be said to show an example of the configuration of the YZ plane.
  • Figure 2A is a cross-sectional view between dashed lines A1-A2 shown in Figures 1D and 1E, and is an enlarged view of Figure 1F.
  • Figure 2B is a plan view showing an example of the cross-sectional configuration between dashed lines A5-A6 shown in Figure 2A.
  • the semiconductor device shown in Figures 1D to 1G, 2A, and 2B includes an insulating layer 110 on a substrate (not shown), a transistor 100 and an insulating layer 180 on the insulating layer 110, a transistor 200 and an insulating layer 280 on the transistor 100 and the insulating layer 180, an insulating layer 283 on the transistor 200 and the insulating layer 280, an insulating layer 285 on the insulating layer 283, and a conductive layer 265 on the transistor 200 and the insulating layer 285.
  • the insulating layer 110, the insulating layer 180, the insulating layer 280, the insulating layer 283, and the insulating layer 285 function as interlayer films.
  • the transistor 100 has a conductive layer 120, a conductive layer 140 on the insulating layer 180, a semiconductor layer 130, an insulating layer 150 on the semiconductor layer 130, and a conductive layer 220 on the insulating layer 150.
  • the conductive layer 120 has a conductive layer 120a and a conductive layer 120b on the conductive layer 120a.
  • the conductive layer 140 has a conductive layer 140a and a conductive layer 140b on the conductive layer 140a.
  • the conductive layer 220 has a conductive layer 220a and a conductive layer 220b on the conductive layer 220a.
  • the transistor 200 has a conductive layer 220, a conductive layer 240 on the insulating layer 280, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.
  • the conductive layer 240 has a conductive layer 240a and a conductive layer 240b on the conductive layer 240a. Note that the conductive layer 120, the conductive layer 140, the conductive layer 220, and the conductive layer 240 may each have a single-layer structure or a stacked structure of three or more layers.
  • the conductive layer 120 functions as one of the source electrode and drain electrode of the transistor 100.
  • the conductive layer 140 functions as the other of the source electrode and drain electrode of the transistor 100.
  • the conductive layer 220 functions as the gate electrode of the transistor 100 and one of the source electrode and drain electrode of the transistor 200.
  • the conductive layer 240 functions as the other of the source electrode and drain electrode of the transistor 200.
  • the conductive layer 260 functions as the gate electrode of the transistor 200.
  • the insulating layer 150 functions as a gate insulating layer of the transistor 100.
  • the insulating layer 250 functions as a gate insulating layer of the transistor 200.
  • the conductive layer 265 functions as a gate wiring.
  • At least a portion of the conductive layer 120 can function as the wiring 13 shown in FIG. 1A. At least a portion of the conductive layer 140 can function as the wiring 15 shown in FIG. 1A. At least a portion of the conductive layer 240 can function as the wiring 23 shown in FIG. 1A. At least a portion of the conductive layer 265 can function as the wiring 21 shown in FIG. 1A. Note that at least a portion of the conductive layer 120 may function as the wiring 15, and at least a portion of the conductive layer 140 may function as the wiring 13.
  • At least a part of the region of the semiconductor layer 130 in contact with the insulating layer 180 functions as a channel formation region of the transistor 100.
  • At least a part of the region of the semiconductor layer 230 in contact with the insulating layer 280 functions as a channel formation region of the transistor 200.
  • One of the region of the semiconductor layer 130 in contact with the conductive layer 120 and the region of the semiconductor layer 130 in contact with the conductive layer 140 functions as a source region, and the other functions as a drain region.
  • One of the region of the semiconductor layer 230 in contact with the conductive layer 220 and the region of the semiconductor layer 230 in contact with the conductive layer 240 functions as a source region, and the other functions as a drain region.
  • the channel formation region of the transistor 100 and the channel formation region of the transistor 200 are sandwiched between the source region and the drain region.
  • an opening 190 is provided in the conductive layer 140 and the insulating layer 180, reaching the conductive layer 120.
  • a recess 191 is provided in the conductive layer 120 at a position overlapping with the opening 190.
  • the recess 191 is provided in the conductive layer 120b.
  • the bottom of the recess 191 corresponds to the upper surface of the conductive layer 120, specifically the upper surface of the conductive layer 120b.
  • the sidewall of the recess 191 corresponds to the side surface of the conductive layer 120, specifically the side surface of the conductive layer 120b.
  • the opening 190 includes an opening in the insulating layer 180 and an opening in the conductive layer 140.
  • the opening in the area where the insulating layer 180 overlaps with the conductive layer 120 is a part of the opening 190
  • the opening in the area where the conductive layer 140 overlaps with the conductive layer 120 is another part of the opening 190.
  • the recess 191 may or may not be included in the opening 190.
  • An opening 290 is provided in the conductive layer 240 and the insulating layer 280, reaching the conductive layer 220.
  • a recess 291 is provided in the conductive layer 220 at a position overlapping with the opening 290.
  • the recess 291 is provided in the conductive layer 220b.
  • the bottom of the recess 291 corresponds to the upper surface of the conductive layer 220, specifically the upper surface of the conductive layer 220b.
  • the sidewall of the recess 291 corresponds to the side surface of the conductive layer 220, specifically the side surface of the conductive layer 220b.
  • the opening 290 is provided at a position where at least a portion of it overlaps with the opening 190.
  • the recess 191 is provided at a position where it overlaps with the opening 190.
  • the recess 191, the opening 190, the recess 291, and the opening 290 at least partially overlap each other. This makes it possible to reduce the area occupied by the memory cell 10 compared to, for example, a case where the opening 190 and the opening 290 do not overlap. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device that can be miniaturized or highly integrated. In addition, the memory capacity per unit area can be increased.
  • the opening 290 includes an opening in the insulating layer 280 and an opening in the conductive layer 240.
  • the opening in the area where the insulating layer 280 overlaps with the conductive layer 220 is a part of the opening 290
  • the opening in the area where the conductive layer 240 overlaps with the conductive layer 220 is another part of the opening 290.
  • the recess 291 may or may not be included in the opening 290.
  • opening 190 and opening 290 in a plan view may differ depending on each layer. Furthermore, when opening 190 as a whole has a circular shape in a plan view, the openings in each layer may or may not be concentric. Similarly, when opening 290 as a whole has a circular shape in a plan view, the openings in each layer may or may not be concentric.
  • the semiconductor layer 130, the insulating layer 150, and the conductive layer 220 are disposed so that at least some of them are located inside the opening 190.
  • the semiconductor layer 130 contacts the upper surface of the conductive layer 140.
  • the semiconductor layer 130 also contacts the bottom and sidewall of the recess 191.
  • the semiconductor layer 130 contacts the side of the conductive layer 140 and the side of the insulating layer 180 inside the opening 190.
  • the insulating layer 150 has a region located on the conductive layer 140 and a region located on the semiconductor layer 130 inside the opening 190.
  • the insulating layer 150 can be provided so as to cover the semiconductor layer 130 and the conductive layer 140.
  • the conductive layer 220 has a region facing the semiconductor layer 130 inside the opening 190 with the insulating layer 150 sandwiched therebetween.
  • the regions of the semiconductor layer 130 and the insulating layer 150 that are disposed inside the opening 190 are provided to reflect the shapes of the recess 191 and the opening 190.
  • the semiconductor layer 130 is provided to cover the bottom and sidewalls of the recess 191 and the sidewalls of the opening 190
  • the insulating layer 150 is provided to cover the semiconductor layer 130.
  • the conductive layer 220 is provided to fill at least a portion of the recess in the insulating layer 150.
  • At least some of the components of the transistor 200 are disposed inside the opening 290.
  • the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are disposed so that at least some of them are located inside the opening 290.
  • the semiconductor layer 230 contacts the upper surface of the conductive layer 240.
  • the semiconductor layer 230 also contacts the bottom and sidewalls of the recess 291.
  • the semiconductor layer 230 contacts the side surfaces of the conductive layer 240 and the insulating layer 280 inside the opening 290.
  • the insulating layer 250 is located on the semiconductor layer 230 inside the opening 290.
  • the conductive layer 260 has a region facing the semiconductor layer 230 inside the opening 290 with the insulating layer 250 in between.
  • the regions of the semiconductor layer 230 and the insulating layer 250 that are disposed inside the opening 290 are provided to reflect the shapes of the recess 291 and the opening 290.
  • the semiconductor layer 230 is provided to cover the bottom and sidewalls of the recess 291 and the sidewalls of the opening 290
  • the insulating layer 250 is provided to cover the semiconductor layer 230.
  • the conductive layer 260 is provided to fill at least a portion of the recess in the insulating layer 250.
  • the height of the lower surface of the insulating layer 150 and the conductive layer 220 inside the opening 190 can be made lower than the height of at least a part of the upper surface of the conductive layer 120 that contacts the insulating layer 180, compared to when the recess 191 is not present.
  • the height of the lower surface of the insulating layer 250 and the conductive layer 260 inside the opening 290 can be made lower than the height of at least a part of the upper surface of the conductive layer 220 that contacts the insulating layer 280, compared to when the recess 291 is not present.
  • each surface can be determined based on the surface on which the transistor is formed.
  • the top surface of the insulating layer 110 can be used as the reference.
  • the surface used as the reference is not limited to the surface on which the transistor is formed.
  • the top surface of a substrate on which the transistor or semiconductor device is provided can be used as the reference.
  • Distance Ta1 is the shortest distance from the upper surface of insulating layer 110 to the lower surface in the region overlapping with recess 191 of insulating layer 150.
  • Distance Tb1 is the shortest distance from the upper surface of insulating layer 110 to the lower surface in the region overlapping with recess 191 of conductive layer 220.
  • Distance Tc1 is the shortest distance from the upper surface of insulating layer 110 to the upper surface of conductive layer 120 that contacts insulating layer 180.
  • Distance Ta2 is the shortest distance from the upper surface of insulating layer 110 to the lower surface in the region overlapping with recess 291 of insulating layer 250.
  • Distance Tb2 is the shortest distance from the upper surface of insulating layer 110 to the lower surface in the region overlapping with recess 291 of conductive layer 260.
  • Distance Tc2 is the shortest distance from the top surface of insulating layer 110 to the top surface of conductive layer 220 that contacts insulating layer 280 and overlaps conductive layer 140.
  • the distance Tc1 is preferably longer than the distance Ta1. This increases the contact area between the side surface of the conductive layer 120 and the semiconductor layer 130, thereby reducing the contact resistance between the conductive layer 120 and the semiconductor layer 130. This makes it possible to suppress a decrease in the on-current of the transistor 100 caused by the contact resistance between the conductive layer 120 and the semiconductor layer 130.
  • the distance Tc2 is longer than the distance Ta2. This increases the contact area between the side surface of the conductive layer 220 and the semiconductor layer 230, and reduces the contact resistance between the conductive layer 220 and the semiconductor layer 230. Therefore, it is possible to suppress a decrease in the on-current of the transistor 200 caused by the contact resistance between the conductive layer 220 and the semiconductor layer 230.
  • distance Tc1 is more preferably equal to or greater than distance Tb1, and even more preferably greater than distance Tb1. This makes it easier for a gate electric field to be applied to the channel formation region of semiconductor layer 130, improving the electrical characteristics of transistor 100. Furthermore, a gate electric field is also more easily applied to the region of semiconductor layer 130 that is in contact with conductive layer 120, improving the on-current of transistor 100. Moreover, regardless of whether conductive layer 120 or conductive layer 140 is used for the drain electrode, the electrical characteristics of transistor 100 can be improved.
  • distance Tc2 is more preferably equal to or greater than distance Tb2, and even more preferably longer than distance Tb2. This makes it easier for a gate electric field to be applied to the channel formation region of semiconductor layer 230, improving the electrical characteristics of transistor 200. Furthermore, a gate electric field is also easier to be applied to the region of semiconductor layer 230 in contact with conductive layer 220, improving the on-current of transistor 200. Moreover, regardless of whether conductive layer 220 or conductive layer 240 is used for the drain electrode, the electrical characteristics of transistor 200 can be improved.
  • a conductive material containing oxygen for the conductive layer 120b it is preferable to use a conductive material containing oxygen for the conductive layer 120b.
  • a metal oxide used as the semiconductor layer 130, it is possible to suppress the formation of a region with high electrical resistance in the region of the conductive layer 120b that contacts the semiconductor layer 130 and the region in the vicinity thereof due to oxygen contained in the metal oxide. As a result, the contact resistance between the semiconductor layer 130 and the conductive layer 120b can be reduced.
  • a conductive material containing oxygen for the conductive layer 140a it is preferable to use. As a result, when a metal oxide is used as the semiconductor layer 130, the contact resistance between the semiconductor layer 130 and the conductive layer 140a can be reduced.
  • a conductive material containing oxygen for the conductive layer 220b it is preferable to use a conductive material containing oxygen for the conductive layer 220b.
  • a metal oxide is used as the semiconductor layer 230, the contact resistance between the semiconductor layer 230 and the conductive layer 220b can be reduced.
  • a conductive material containing oxygen for the conductive layer 240a it is preferable to use a conductive material containing oxygen for the conductive layer 240a. As a result, when a metal oxide is used as the semiconductor layer 230, the contact resistance between the semiconductor layer 230 and the conductive layer 240a can be reduced.
  • a conductive material containing oxygen is used for the layer of the stacked structure closest to the channel formation region, and the contact resistance with the semiconductor layer 130 or the semiconductor layer 230 is reduced, thereby shortening the current path between the source and drain. This makes it possible to increase the on-current of the transistor.
  • the conductive material containing oxygen it is preferable to use a metal oxide having conductivity (also called an oxide conductor).
  • the contact area with the conductive layer 140 is larger than when the semiconductor layer 130 contacts only the side surfaces of the conductive layer 140. This makes it possible to reduce the contact resistance between the semiconductor layer 130 and the conductive layer 140. Therefore, it is possible to suppress a decrease in the on-current of the transistor 100 caused by the contact resistance. Furthermore, when the semiconductor layer 230 contacts the upper surface and side surfaces of the conductive layer 240, the contact area with the conductive layer 240 is larger than when the semiconductor layer 230 contacts only the side surfaces of the conductive layer 240. This makes it possible to reduce the contact resistance between the semiconductor layer 230 and the conductive layer 240. Therefore, it is possible to suppress a decrease in the on-current of the transistor 200 caused by the contact resistance.
  • the insulating layer 150 is provided so as to cover the semiconductor layer 130 and the conductive layer 140.
  • the conductive layer 220 is provided so as to have an area overlapping with the conductive layer 140 via the insulating layer 150.
  • the memory cell 10 has a capacitance Cp as shown in FIG. 1A or FIG. 1B.
  • the capacitance Cp can be a capacitance in which the insulating layer 150 is a dielectric layer and the conductive layer 140 and the conductive layer 220 are a pair of electrodes.
  • the capacitance Cp shown in FIG. 1C has the insulating layer 250 as a dielectric layer and the conductive layer 220 and the conductive layer 260 as a pair of electrodes.
  • the semiconductor device of one embodiment of the present invention can be a low-cost semiconductor device. Furthermore, by not forming a capacitive element in the memory cell 10, the area occupied by the memory cell 10 can be reduced in some cases. In this case, the semiconductor device of one embodiment of the present invention can be a semiconductor device that can be miniaturized or highly integrated. In addition, the storage capacity per unit area can be increased.
  • the sum of the capacitance value of the capacitance Cp shown in FIG. 1A or FIG. 1B and the capacitance value of the capacitance Cp shown in FIG. 1C can be set to the capacitance value of the capacitance for holding data.
  • a capacitor may be formed in the memory cell 10. Specifically, a capacitor connected to the node ND1 of the memory cell 10 can be provided. This allows data to be held in the memory cell 10 for a long period of time.
  • the capacitance value of the capacitance Cp is too large, the operation of the semiconductor device of one embodiment of the present invention, specifically, the operation of the memory cell 10, may be slowed down.
  • the capacitance value of the capacitance Cp can be made larger than when the side surface of the conductive layer 140 is not covered with the conductive layer 220.
  • the insulating layer 285 has an opening 270 that reaches the semiconductor layer 230 at a position overlapping the opening 290. At least a portion of the components of the transistor 200 is disposed inside the opening 270. Specifically, the insulating layer 250 and the conductive layer 260 are disposed so that at least a portion of each is located inside the opening 270. At least a portion of the insulating layer 283 is located inside the opening 270. The insulating layer 283 covers the upper surface and side surfaces of the semiconductor layer 230 and the side surfaces of the conductive layer 240. The insulating layer 250 contacts the insulating layer 283 inside the opening 270. The opening 270 may be provided in the insulating layer 283.
  • the region of insulating layer 250 that is disposed inside opening 270 is provided to reflect the shape of opening 270.
  • insulating layer 283 is provided to cover the sidewall of opening 270 (the side surface of insulating layer 285), and insulating layer 250 is provided inside insulating layer 283.
  • conductive layer 260 is provided to fill at least a portion of the recess in insulating layer 250 that reflects the shape of opening 270.
  • the conductive layer 260 does not overlap the top surface of the conductive layer 240, so that the parasitic capacitance between the conductive layer 240 and the conductive layer 260 can be reduced.
  • the maximum width of the conductive layer 260 is smaller than the width D of the opening 290. In this way, when the maximum width of the conductive layer 260 is smaller than the width D of the opening 290, the parasitic capacitance between the conductive layer 260 and the conductive layer 240 can be reduced, which is preferable. Note that, for example, as shown in FIG. 2A, the magnitude relationship between the two widths in a semiconductor device of one embodiment of the present invention can be confirmed by a cross section parallel to the Z direction.
  • the width D of the opening 290 may vary in the depth direction.
  • the width D used here is the shortest distance between the two side surfaces of the conductive layer 240 on the opening 290 side in a cross-sectional view.
  • the minimum value of the width of the opening 290 in the conductive layer 240 is used as the width D of the opening 290.
  • the height of the upper surface of the conductive layer 260 and the height of the upper surface of the insulating layer 285 are the same or approximately the same.
  • the conductive layer 265 is provided on the insulating layer 285, the insulating layer 283, the insulating layer 250, and the conductive layer 260, and is in contact with the upper surface of the conductive layer 260.
  • the conductive layer 265 can also be in contact with the upper surface of the insulating layer 285, the upper surface of the insulating layer 283, and the upper surface of the insulating layer 250. It can also be said that the conductive layer 260 and the conductive layer 265 are electrically connected to each other.
  • the insulating layer 283 and the insulating layer 285 are located between the conductive layer 265 and the conductive layer 240.
  • the film thickness of the insulating layer 283 and the insulating layer 285, for example, the total film thickness of the insulating layer 283 and the insulating layer 285 in the region overlapping with the conductive layer 240 and the semiconductor layer 230 is thicker than the film thickness of the insulating layer 150. Therefore, the parasitic capacitance between conductive layer 240 and conductive layer 265 can be made smaller than the capacitance Cp between conductive layer 140 and conductive layer 220.
  • the transistor 200 has a configuration in which the parasitic capacitance between the other of the source electrode and the drain electrode and the gate electrode, and the parasitic capacitance between the other of the source electrode and the drain electrode and the gate wiring are reduced. Therefore, the transistor 200 can be operated at high speed, and the frequency characteristics of the memory cell 10 can be improved.
  • the transistor 200 can be a transistor with good electrical characteristics. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device including a transistor with good electrical characteristics.
  • FIG. 1F shows an example in which the ends of the conductive layer 140a, the conductive layer 140b, and the semiconductor layer 130 are aligned outside the opening 190.
  • FIG. 1F also shows an example in which the ends of the conductive layer 240a, the conductive layer 240b, and the semiconductor layer 230 are aligned outside the opening 290.
  • the conductive layer 140a, the conductive layer 140b, and the semiconductor layer 130 can be manufactured by processing using the same mask.
  • the conductive layer 240a, the conductive layer 240b, and the semiconductor layer 230 can be manufactured by processing using the same mask. Therefore, the number of masks required for manufacturing a semiconductor device can be reduced, which is preferable.
  • the conductive layer 140 has an opening 190 in a region overlapping with the conductive layer 120.
  • the conductive layer 140 is not provided inside the opening 190 of the insulating layer 180.
  • the conductive layer 140 does not contact the side of the insulating layer 180 inside the opening 190.
  • the opening 190 can be formed in the conductive layer 140 and the insulating layer 180 at once.
  • the film thickness distribution of the semiconductor layer 130 provided inside the opening 190 can be made uniform.
  • the conductive layer 240 has an opening 290 in the area where it overlaps with the conductive layer 220. It is also preferable that the conductive layer 240 is not provided inside the opening 290 of the insulating layer 280. In other words, it is preferable that the conductive layer 240 does not contact the side of the insulating layer 280 inside the opening 290.
  • 1F and 1G show an example in which the inclination of the side of the conductive layer 140 inside the opening 190 is equal to the inclination of the side of the insulating layer 180 inside the opening 190, but the inclination of these sides may be different.
  • the taper angle of the side of the conductive layer 140 inside the opening 190 is smaller than the taper angle of the side of the insulating layer 180 inside the opening 190.
  • the inclination of the side of each layer inside the opening 190 may be different.
  • the conductive layer 140 has a laminated structure, the inclination of the side of each layer inside the opening 190 may be different.
  • Figures 1F and 1G show an example in which the slope of the side of the conductive layer 240 inside the opening 290 is equal to the slope of the side of the insulating layer 280 inside the opening 290, but the slopes of these sides may be different.
  • the transistor 100 has a metal oxide (also called an oxide semiconductor) that functions as a semiconductor in the semiconductor layer 130 including the channel formation region.
  • the transistor 200 has a metal oxide (also called an oxide semiconductor) that functions as a semiconductor in the semiconductor layer 230 including the channel formation region. From the above, the transistor 100 and the transistor 200 can be said to be OS transistors.
  • oxygen vacancies ( VO ) and impurities are present in a channel formation region in an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate and the reliability may be reduced. Furthermore, hydrogen near the oxygen vacancies may form a defect in which hydrogen is inserted into the oxygen vacancy (hereinafter, this may be referred to as VOH ), and may generate electrons that serve as carriers. For this reason, when oxygen vacancies are present in the channel formation region in the oxide semiconductor, the OS transistor is likely to be normally on. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor is reduced and the channel formation region in the oxide semiconductor is made i-type (intrinsic) or substantially i-type.
  • the source and drain regions of an OS transistor are preferably regions having more oxygen vacancies, more VOH , or a higher concentration of impurities such as hydrogen, nitrogen, or metal elements than the channel formation region, thereby increasing the carrier concentration and lowering the resistance. That is, the source and drain regions of an OS transistor are preferably n-type regions having a higher carrier concentration and lower resistance than the channel formation region.
  • OS transistors have a low off-state current. Therefore, by using an OS transistor as the transistor 100 in particular, data can be retained in the memory cell 10 for a long period of time. As a result, a refresh operation is not necessary. Alternatively, the frequency of the refresh operation can be significantly reduced. As a result, the semiconductor device of one embodiment of the present invention can be a semiconductor device with low power consumption.
  • the transistor 200 can also be an OS transistor like the transistor 100.
  • the semiconductor layer 130 is provided inside the opening 190 of the insulating layer 180.
  • the transistor 100 has a configuration in which one of the source electrode and drain electrode (conductive layer 120 in this case) is located on the bottom and the other of the source electrode and drain electrode (conductive layer 140 in this case) is located on the top, so that current flows in the vertical direction.
  • a channel is formed along the side surface of the opening 190 of the insulating layer 180.
  • a channel is formed along the side surface of the opening 290 of the insulating layer 280.
  • the insulating layer 280 contacts the entire outer periphery of the semiconductor layer 230. Therefore, the channel formation region of the transistor 200 can be formed on the entire outer periphery of the semiconductor layer 230 inside the opening 290 (the entire region in contact with the insulating layer 280). Similarly, the insulating layer 180 contacts the entire outer periphery of the semiconductor layer 130. Therefore, the channel formation region of the transistor 100 can be formed on the entire outer periphery of the semiconductor layer 130 inside the opening 190 (the entire region in contact with the insulating layer 180). Note that FIG. 2B can also be considered a cross-sectional view in the XY plane including the channel formation region of the semiconductor layer 230.
  • the channel length of the transistor 100 and the transistor 200 is the distance between the source region and the drain region.
  • the channel length of the transistor 100 can correspond to the length of the side of the insulating layer 180 on the opening 190 side.
  • the channel length of the transistor 200 can correspond to the length of the side of the insulating layer 280 on the opening 290 side.
  • the channel length L1 of the transistor 100 and the channel length L2 of the transistor 200 are indicated by dashed double-headed arrows.
  • the channel length L1 corresponds to the length of the side of the insulating layer 180 on the opening 190 side.
  • the channel length L2 corresponds to the length of the side of the insulating layer 280 on the opening 290 side.
  • the channel length is set by the exposure limit of photolithography, but in one embodiment of the present invention, the channel length can be set by the film thickness of the insulating layer 180 or the insulating layer 280. Therefore, the channel length of the transistor 100 and the transistor 200 can be made into a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-current of the transistor 100 and the transistor 200, and improves the frequency characteristics.
  • the exposure limit of photolithography for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more.
  • a channel formation region, a source region, and a drain region can be formed inside the opening 190 and the opening 290.
  • the area occupied by the transistor 100 and the transistor 200 can be reduced compared to a horizontal transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. Therefore, the semiconductor device can be highly integrated.
  • the semiconductor device of one embodiment of the present invention is used for a memory device, the memory capacity per unit area can be increased.
  • the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. Therefore, the side of the conductive layer 260 arranged at the center faces the side of the semiconductor layer 230 through the insulating layer 250. That is, in a plan view, the entire periphery of the semiconductor layer 230 becomes a channel formation region. At this time, for example, the length of the periphery of the semiconductor layer 230 determines the channel width of the transistor 200. That is, it can be said that the channel width of the transistor 200 is determined by the width of the opening 290 (the diameter when the opening 290 is circular in a plan view). In FIGS.
  • the width D of the opening 290 is indicated by a double-headed arrow of a two-dot chain line.
  • the channel width W of the transistor 200 is indicated by a double-headed arrow of a one-dot chain line.
  • the width D of the opening 290 is set by the exposure limit of photolithography.
  • the width D of the opening 290 is set by the film thickness of each of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided inside the opening 290.
  • the width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less.
  • the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D x ⁇ ".
  • the above can also be applied to the width of the opening 190 by replacing the opening 290, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 with the opening 190, the semiconductor layer 130, the insulating layer 150, and the conductive layer 220, respectively.
  • the channel length L2 of the transistor 200 is at least smaller than the channel width W of the transistor 200.
  • the channel length L2 of the transistor 200 is preferably 0.1 to 0.99 times the channel width W of the transistor 200, and more preferably 0.5 to 0.8 times.
  • the channel length L1 of the transistor 100 is at least smaller than the channel width of the transistor 100.
  • the channel length L1 of the transistor 100 is preferably 0.1 to 0.99 times the channel width W of the transistor 100, and more preferably 0.5 to 0.8 times.
  • the opening 190 so as to have a circular shape in a planar view
  • the semiconductor layer 130, the insulating layer 150, and the conductive layer 220 are arranged concentrically.
  • the distance between the conductive layer 220 and the semiconductor layer 130 becomes approximately uniform, so that a gate electric field can be applied approximately uniformly to the semiconductor layer 130.
  • a gate electric field can be applied approximately uniformly to the semiconductor layer 230.
  • the openings 190, 290, and 270 are circular in plan view, but the present invention is not limited to this.
  • the openings 190, 290, and 270 can each be, for example, a circle, an approximately circular shape such as an ellipse, a polygon such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a shape with rounded corners of these polygons.
  • the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees). As shown in FIG.
  • the openings 190, 290, and 270 are preferably circular. By making them circular, the processing accuracy when forming the openings can be improved, and openings of a fine size can be formed.
  • a circle is not limited to a perfect circle.
  • Each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked structure.
  • FIGS. 1F and 1G show an example in which the conductive layer 120a, the conductive layer 220a, the semiconductor layer 130, the semiconductor layer 230, and the conductive layer 260 have a single-layer structure.
  • FIG. 2A shows an example in which the conductive layer 120a, the conductive layer 220a, the semiconductor layer 130, the semiconductor layer 230, and the conductive layer 260 have a stacked structure.
  • the semiconductor layer 130 and the semiconductor layer 230 have a channel formation region.
  • the channel formation region is i-type (intrinsic) or substantially i-type.
  • the semiconductor layer 130 and the semiconductor layer 230 further have a source region and a drain region.
  • the source region and the drain region are n-type regions (low resistance regions) having a higher carrier concentration than the channel formation region.
  • the crystallinity of the semiconductor material used for the semiconductor layer 130 and the semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystalline semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • the use of a single crystalline semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.
  • metal oxides can be used for the semiconductor layer 130 and the semiconductor layer 230.
  • the semiconductor layer 130 and the semiconductor layer 230 can be called oxide semiconductor layers.
  • the band gap of a metal oxide that functions as a semiconductor is preferably 2.0 eV or more, and more preferably 2.5 eV or more.
  • metal oxides examples include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably contains two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or semi-metal element that has a high bond energy with oxygen, for example, a metal element or semi-metal element that has a higher bond energy with oxygen than indium.
  • element M examples include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification may include metalloid elements.
  • the semiconductor layer 130 and the semiconductor layer 230 may be, for example, indium oxide (In oxide), indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), Indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn
  • the field effect mobility of the transistor can be increased.
  • a transistor with a large on-current can be realized.
  • the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium.
  • Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the carrier concentration may increase or the band gap may be narrowed, and the field effect mobility of the transistor may be increased.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • a metal oxide with a large band gap can be obtained.
  • the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained.
  • a shift in the threshold voltage of the transistor can be suppressed.
  • fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of the transistors vary depending on the composition of the metal oxide applied to the semiconductor layer 130 and the semiconductor layer 230. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, a semiconductor device that combines excellent electrical characteristics and high reliability can be obtained.
  • the metal oxide is In-M-Zn oxide
  • the atomic ratio of In in the In-M-Zn oxide is greater than or equal to the atomic ratio of M.
  • the nearby composition includes a range of ⁇
  • the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M.
  • the total proportion of the atomic numbers of the metal elements can be regarded as the proportion of the atomic number of element M.
  • the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained may be referred to as the indium content. The same applies to other metal elements.
  • the In-Zn oxide may also contain a trace amount of element M.
  • energy dispersive X-ray spectrometry EDX
  • XPS X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • EDX energy dispersive X-ray spectrometry
  • XPS X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content. In addition, it may be difficult to quantify element M, or element M may not be detected.
  • the sputtering method or the ALD method can be suitably used to form the metal oxide.
  • the composition of the metal oxide after the film formation may differ from the composition of the target.
  • the zinc content in the metal oxide after the film formation may decrease to about 50% compared to the target.
  • the chemical vapor deposition (CVD) method, the molecular beam epitaxy (MBE) method, the pulsed laser deposition (PLD) method, or the like may be used to form the metal oxide film.
  • the semiconductor layer 130 and the semiconductor layer 230 may have a stacked structure having two or more metal oxide layers.
  • the two or more metal oxide layers in the semiconductor layer 130 and the semiconductor layer 230 may have the same or approximately the same composition.
  • a stacked structure of metal oxide layers with the same composition for example, they can be formed using the same sputtering target, which reduces manufacturing costs.
  • the two or more metal oxide layers in semiconductor layer 130 and semiconductor layer 230 may have different compositions.
  • FIG. 2A shows an example in which the semiconductor layer 130 has a two-layer structure of an oxide layer 130a and an oxide layer 130b on the oxide layer 130a. Also, an example in which the semiconductor layer 230 has a two-layer structure of an oxide layer 230a and an oxide layer 230b on the oxide layer 230a is shown.
  • the transistor 100 can be a transistor with a large on-current.
  • the transistor 200 can be a transistor with a large on-current.
  • the threshold voltage of the transistor 100 may shift.
  • the drain current (hereinafter also referred to as cutoff current) flowing when the gate voltage is 0 V may become large.
  • the threshold voltage may become low.
  • the threshold voltage of the transistor 200 may shift.
  • the cutoff current of the transistor 200 may become large.
  • the transistor 200 is an n-channel transistor, the threshold voltage may become low.
  • the transistor 100 and the transistor 200 are n-channel transistors, the threshold voltage can be increased and the cutoff current can be reduced.
  • a small cutoff current is sometimes referred to as normally off.
  • the semiconductor layer 130 and the semiconductor layer 230 into a stacked structure and using a material having a higher conductivity than the oxide layer 130b and the oxide layer 230b for the oxide layer 130a and the oxide layer 230a, a normally-off transistor with a large on-current can be obtained. Therefore, a semiconductor device that achieves both low power consumption and high performance can be obtained.
  • the carrier concentration of the oxide layer 130a and the oxide layer 230a is preferably higher than that of the oxide layer 130b and the oxide layer 230b.
  • the conductivity is increased. Therefore, the contact resistance between the semiconductor layer 130 and the conductive layer 120, the contact resistance between the semiconductor layer 130 and the conductive layer 140, the contact resistance between the semiconductor layer 230 and the conductive layer 220, and the contact resistance between the semiconductor layer 230 and the conductive layer 240 can be reduced. Therefore, the transistor 100 and the transistor 200 can be a transistor with a large on-current. Furthermore, by decreasing the carrier concentration of the oxide layer 130b and the oxide layer 230b, the conductivity is decreased, and the transistor 100 and the transistor 200 can be a normally-off transistor.
  • the semiconductor layer 130 and the semiconductor layer 230 are not limited to the above-mentioned configuration, and the oxide layer 130a and the oxide layer 230a may be made of a material having a lower conductivity than the oxide layer 130b and the oxide layer 230b.
  • the carrier concentration of the oxide layer 130a and the oxide layer 230a may be lower than the carrier concentration of the oxide layer 130b and the oxide layer 230b.
  • the band gap of the first metal oxide used in the oxide layer 130a and the oxide layer 230a is different from the band gap of the second metal oxide used in the oxide layer 130b and the oxide layer 230b.
  • the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
  • the band gap of the first metal oxide used in the oxide layer 130a and the oxide layer 230a is preferably smaller than the band gap of the second metal oxide used in the oxide layer 130b and the oxide layer 230b. This can reduce the contact resistance between the semiconductor layer 130 and the conductive layer 120, the contact resistance between the semiconductor layer 130 and the conductive layer 140, the contact resistance between the semiconductor layer 230 and the conductive layer 220, and the contact resistance between the semiconductor layer 230 and the conductive layer 240. Therefore, the transistor 100 and the transistor 200 can be a transistor with a large on-current. In addition, when the transistor 100 and the transistor 200 are n-channel transistors, the threshold voltage can be increased, and the transistors can be normally-off transistors.
  • the large band gap of the second metal oxide can suppress the generation and induction of carriers in the oxide layer 130b and the oxide layer 230b, at the interface between the oxide layer 130b and the insulating layer 150, and at the interface between the oxide layer 230b and the insulating layer 250. This can improve the reliability of the transistor.
  • the semiconductor layer 130 and the semiconductor layer 230 are not limited to the above-mentioned configuration, and the band gap of the first metal oxide may be larger than the band gap of the second metal oxide.
  • the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide.
  • the first metal oxide may be configured to contain a trace amount of element M or to contain no element M.
  • the first metal oxide used in the oxide layer 130a and the oxide layer 230a is In-Zn oxide
  • the second metal oxide used in the oxide layer 130b and the oxide layer 230b is In-M-Zn oxide.
  • the first metal oxide can be In-Zn oxide
  • the second metal oxide can be In-Ga-Zn oxide.
  • This increases the on-current of the transistor 200 and provides a highly reliable transistor structure with little variation.
  • the conductive layer 120 or the conductive layer 140 when a metal oxide is used for the conductive layer 120 or the conductive layer 140 (in the case of a stacked structure, the layer closest to the channel formation region of the semiconductor layer 130), it is preferable to use In-Zn oxide or In-Sn-Zn oxide for the semiconductor layer 130 (or the oxide layer 130a) because the contact resistance can be reduced compared to when In-Ga-Zn oxide is used for the semiconductor layer 130 (or the oxide layer 130a).
  • indium tin oxide also referred to as ITO
  • ITSO indium tin oxide with silicon added
  • the conductive layer 220 or the conductive layer 240 in the case of a laminated structure, the layer closest to the channel formation region of the semiconductor layer 230
  • In-Zn oxide or In-Sn-Zn oxide for the semiconductor layer 230 (or the oxide layer 230a) because the contact resistance can be reduced compared to when In-Ga-Zn oxide is used for the semiconductor layer 230 (or the oxide layer 230a).
  • ITO or ITSO for the conductive layer 220b and the conductive layer 240a in FIG. 2A, use In-Zn oxide or In-Sn-Zn oxide for the oxide layer 230a, and use In-Ga-Zn oxide for the oxide layer 230b.
  • the semiconductor layer 130 and the semiconductor layer 230 are not limited to the above-mentioned configuration, and the content of element M in the first metal oxide may be higher than the content of element M in the second metal oxide.
  • the crystallinity of the semiconductor material used for the semiconductor layer 130 and the semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • a single crystal semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.
  • the semiconductor layer 130 and the semiconductor layer 230 each preferably have a metal oxide layer having crystallinity.
  • a metal oxide having crystallinity examples include a CAAC (c-axis aligned crystal) structure, a polycrystalline (Poly-crystal) structure, and a nanocrystalline (nc: nano-crystal) structure.
  • the CAAC structure is a crystal structure in which multiple microcrystals (typically multiple IGZO microcrystals) have a c-axis orientation, and the multiple microcrystals are connected without being oriented in the a-b plane.
  • multiple microcrystals typically multiple IGZO microcrystals
  • metal atoms are arranged in layers in the crystalline portion. Therefore, an OS film with a CAAC structure can be said to have a structure with layered crystal parts.
  • the polycrystalline structure has grain boundaries.
  • a minute gap also called a nanocrack or a microcrack
  • a minute space also called a nanospace or a microspace
  • the electrical resistance of the oxide semiconductor layer increases. This is because the electrical resistance of the minute gap or minute space is very high, for example, infinite.
  • an oxide semiconductor layer having a minute gap or minute space is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of the source electrode and the drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor.
  • the CAAC structure has fewer grain boundaries in the a-b plane than the polycrystalline structure, and therefore can realize a highly reliable semiconductor device.
  • the crystallinity of the semiconductor layer 130 and the semiconductor layer 230 can be analyzed, for example, by X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • the semiconductor layer 130 and the semiconductor layer 230 can each have a stacked structure of two or more metal oxide layers with different crystallinity.
  • the two or more metal oxide layers may have different compositions, or may have the same or approximately the same composition.
  • a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer can be used, and the second metal oxide layer can have a region with higher crystallinity than the first metal oxide layer.
  • the second metal oxide layer can have a region with lower crystallinity than the first metal oxide layer.
  • the second metal oxide layer when the second metal oxide layer has a region with lower crystallinity than the first metal oxide layer, the second metal oxide layer can be formed and then subjected to heat treatment (also called crystallization treatment) to increase the crystallinity of the second metal oxide layer.
  • heat treatment also called crystallization treatment
  • the oxide layer 130b on the oxide layer 130a having high crystallinity, it is also easy to improve the crystallinity of the oxide layer 130b.
  • the same can be said about the oxide layer 230a and the oxide layer 230b.
  • This makes it possible to improve the crystallinity of the entire semiconductor layer 130 and the entire semiconductor layer 230, which is preferable.
  • two layers of IGZO having different compositions may be stacked.
  • a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) may be used.
  • the semiconductor layer 130 and the semiconductor layer 230 may each have a stacked structure of three or more layers.
  • the semiconductor layer 130 can have a three-layer structure having, for example, an oxide layer, an oxide layer 130a on the oxide layer, and an oxide layer 130b on the oxide layer 130a.
  • an example will be described in which the semiconductor layer 130 has a three-layer structure, but a similar configuration can also be applied to the semiconductor layer 230.
  • the above-mentioned configurations can be applied to the oxide layer 130a and the oxide layer 130b.
  • the oxide layer located below the oxide layer 130a can have a similar configuration to that applicable to the oxide layer 130b. In the following, they will be described together as a pair of oxide layers sandwiching the oxide layer 130a.
  • the pair of oxide layers sandwiching the oxide layer 130a preferably have a band gap larger than that of the oxide layer 130a.
  • the oxide layer 130a is sandwiched between the pair of oxide layers with a larger band gap, and the oxide layer 130a mainly functions as a current path (channel).
  • sandwiching the oxide layer 130a between the pair of oxide layers it is possible to reduce trap levels at the interface of the oxide layer 130a and in its vicinity. This makes it possible to realize a buried channel type transistor in which the channel is kept away from the insulating layer interface, and to increase the field effect mobility.
  • the influence of the interface state that may be formed on the back channel side is reduced, and light deterioration of the transistor (e.g., negative bias light deterioration) can be suppressed, thereby improving the reliability of the transistor.
  • the thickness of the semiconductor layer 130 and the semiconductor layer 230 is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, and more preferably 20 nm or more and 50 nm or less.
  • the thickness of the semiconductor layer 130 and the semiconductor layer 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
  • the oxide semiconductor layer when forming the oxide semiconductor layer, it is preferable to use two types of film formation methods, a sputtering method and an ALD method. For example, if a first oxide semiconductor layer having a CAAC structure is formed by a sputtering method and then a second oxide semiconductor layer having a lower crystallinity than the CAAC structure is formed by an ALD method, it is expected that the atomic layer of the second oxide semiconductor layer will fill or repair the gaps in the atomic-level crystal parts of the CAAC structure of the first oxide semiconductor layer. In addition, it is preferable to perform heat treatment (for example, 100° C. or more and 500° C. or less, preferably 200° C. or more and 450° C. or less, more preferably 300° C.
  • heat treatment for example, 100° C. or more and 500° C. or less, preferably 200° C. or more and 450° C. or less, more preferably 300° C.
  • the second oxide semiconductor layer (in other words, each crystal molecule formed by the ALD method) will repair the gaps in the atomic-level crystal parts of the CAAC structure of the first oxide semiconductor layer by the heat treatment.
  • an oxide semiconductor layer formed using the above two types of film formation methods may be called a hybrid OS.
  • Figures 3A, 3B, 3C, and 3D are conceptual diagrams for explaining a cross section of an oxide semiconductor layer having a CAAC structure.
  • the c-axis is indicated by an arrow in each figure.
  • the oxide semiconductor layer 370a shown in FIG. 3A has a region 372a and a region 372b located between the regions 372a.
  • the region 372a corresponds to a region of a CAAC structure (i.e., a structure having layered crystal parts), and the region 372b corresponds to a region between the CAAC structures.
  • the CAAC structure has fewer crystal grain boundaries in the a-b plane than the polycrystalline structure. Thus, even in the oxide semiconductor layer 370a having a CAAC structure, there may be a minute gap or minute space (region 372b in FIG. 3A) between the crystal parts.
  • an oxide semiconductor layer having a CAAC structure is formed by sputtering as the first oxide semiconductor layer, and then an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, is formed by ALD as the second oxide semiconductor layer.
  • an oxide semiconductor layer having a region 372a is formed by sputtering as a first oxide semiconductor layer, and then an oxide semiconductor layer having a region 372c with lower crystallinity than the CAAC structure is formed by ALD as a second oxide semiconductor layer.
  • the oxide semiconductor layer 370b has a region 372a and a region 372c. Since the ALD method can deposit atoms one layer at a time, the second oxide semiconductor layer can be formed to fill the region 372b.
  • the oxide semiconductor layer 370c has a region 372a and a region 372c.
  • the 3C is a region having higher crystallinity or a higher density of crystal parts than the region 372a shown in FIG. 3B. By performing heat treatment, the crystallinity of either or both of the regions 372a and 372c can be increased.
  • the region 372c has, for example, a crystal part that has the same crystal structure as the crystal part of the region 372a.
  • the region 372c has, for example, a crystal part that is connected to the crystal part of the region 372a.
  • the oxide semiconductor layer 370d has a region 372a.
  • the region 372a has improved crystallinity compared to the region 372a shown in FIG. 3B and FIG. 3C, and the boundary between the region 372a and the region 372c disappears, or the boundary between the region 372a and the region 372c is no longer observed. Therefore, the entire oxide semiconductor layer 370d has a CAAC structure.
  • FIG. 3D when the entire oxide semiconductor layer 370d has a CAAC structure, a highly reliable semiconductor device can be realized.
  • the presence or absence of the boundary between the region 372a and the region 372c can be confirmed using, for example, a cross-sectional TEM or a cross-sectional STEM.
  • the small gap or the small space in the first oxide semiconductor layer can be filled by forming a second oxide semiconductor layer on the first oxide semiconductor layer or by forming a second oxide semiconductor layer and performing heat treatment.
  • a dense oxide semiconductor layer with increased crystallinity can be obtained.
  • the dense oxide semiconductor layer with increased crystallinity is used for the channel formation region of a transistor, it is expected that an increase in the electrical resistance of the oxide semiconductor layer can be suppressed or the initial characteristics (particularly the on-current) of the transistor can be improved, making the transistor suitable for high-speed driving.
  • the oxide semiconductor layer when an oxide semiconductor layer is formed by both the sputtering method and the ALD method, if the thickness of the oxide semiconductor layer formed by the ALD method is thin, the oxide semiconductor layer can be regarded as a single-layer structure, not a stacked structure of the oxide semiconductor layer formed by the sputtering method and the oxide semiconductor layer formed by the ALD method.
  • the oxide semiconductor layer formed by the ALD method when the thickness of the oxide semiconductor layer formed by the ALD method is more than 0 nm and 3 nm or less, preferably more than 0 nm and 2 nm or less, and more preferably more than 0 nm and 1 nm or less, the oxide semiconductor layer formed by the two film formation methods, the sputtering method and the ALD method, can be regarded as a single-layer structure. In such a case, for example, in a cross-sectional TEM image and a cross-sectional STEM image, the boundary between the oxide semiconductor layer formed by the sputtering method and the oxide semiconductor layer formed by the ALD method is not observed.
  • the thickness of the oxide semiconductor layer formed by the ALD method exceeds 3 nm, it may be considered to be a stacked structure, a multilayer structure, or a multiple structure of an oxide semiconductor layer formed by the sputtering method and an oxide semiconductor layer formed by the ALD method.
  • the oxide semiconductor layer is formed by both the sputtering method and the ALD method, it is preferable to use different compositions.
  • the oxide semiconductor layer formed using the above two types of film formation methods can be considered to have a structure in which the gaps in the crystal parts of the CAAC structure are filled with atomic layers formed by the ALD method. Note that this structure can be analyzed by analytical methods such as cross-sectional SEM, cross-sectional STEM, cross-sectional TEM, SIMS, and EDX.
  • the oxide semiconductor layer having a CAAC structure formed using the above-mentioned two types of film formation methods may have a higher dielectric constant, film density, and film hardness than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.
  • a transistor having excellent characteristics for example, a transistor with a large on-current, a transistor with a high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also called f characteristics), a highly reliable transistor, etc.
  • Hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to become water, and oxygen vacancies ( VO ) may be formed in the oxide semiconductor. Furthermore, a defect in which hydrogen is introduced into an oxygen vacancy (hereinafter referred to as VOH ) may function as a donor and generate an electron that is a carrier. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate an electron that is a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to be normally on (that is, the threshold voltage has a negative value). Furthermore, hydrogen in an oxide semiconductor is easily mobile due to stress such as heat or an electric field; therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.
  • VOH in the semiconductor layer 130 and the semiconductor layer 230 is highly purified intrinsic or substantially highly purified intrinsic.
  • impurities such as water and hydrogen from the oxide semiconductor
  • an oxide semiconductor with sufficiently reduced impurities such as VOH for a channel formation region of a transistor, stable electrical characteristics can be imparted.
  • oxygen addition treatment may be referred to as oxygen addition treatment.
  • the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , even more preferably less than 1 ⁇ 10 16 cm ⁇ 3 , still more preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and still more preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, and can be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • the carbon concentration in a channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and further preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and still more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in a channel formation region of an oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, and further preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy.
  • an electron serving as a carrier may be generated.
  • some of the hydrogen may bond to oxygen bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in a channel formation region of the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably less than 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , and further preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • the concentration of the alkali metal or the alkaline earth metal in a channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material in the channel formation region.
  • another semiconductor material include semiconductors made of single elements, or compound semiconductors.
  • semiconductors made of single elements include silicon and germanium.
  • compound semiconductors include gallium arsenide and silicon germanium.
  • Other examples of compound semiconductors include organic semiconductors and nitride semiconductors.
  • the aforementioned oxide semiconductor is also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.
  • Silicon that can be used as a semiconductor material for transistors includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • An example of polycrystalline silicon is low temperature polysilicon (LTPS).
  • the semiconductor layer of the transistor may have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), and zirconium selenide (representatively ZrSe 2 ).
  • MoS 2 molybdenum sulfide
  • MoSe 2 molybdenum selenide
  • MoTe 2 molybdenum tellurium
  • the insulating layers (insulating layer 110, insulating layer 150, insulating layer 180, insulating layer 250, insulating layer 280, insulating layer 283, insulating layer 285, etc.) of the semiconductor device, it is preferable to use an inorganic insulating film.
  • the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film.
  • oxide insulating film examples include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film.
  • nitride insulating film examples include a silicon nitride film and an aluminum nitride film.
  • Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film.
  • Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film.
  • An organic insulating film may be used for an insulating layer included in a semiconductor device.
  • Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.
  • materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin.
  • inorganic insulating materials with a low relative dielectric constant include silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen.
  • a material that can have ferroelectricity may be used for the insulating layer of the semiconductor device.
  • materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (where X is a real number greater than 0).
  • materials that can have ferroelectricity include materials obtained by adding an element J1 (here, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide.
  • the ratio of the number of atoms of hafnium to the number of atoms of the element J1 can be set appropriately, and for example, the ratio of the number of atoms of hafnium to the number of atoms of the element J1 may be set to 1:1 or close thereto.
  • materials that can have ferroelectricity include materials obtained by adding an element J2 (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide.
  • the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 may be set to 1: 1 or close to that.
  • piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiO x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may be used.
  • examples of materials that may have ferroelectricity include metal nitrides having element M1, element M2, and nitrogen.
  • element M1 is one or more selected from aluminum, gallium, and indium.
  • element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, and chromium.
  • the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately.
  • metal oxides having element M1 and nitrogen may have ferroelectricity even if they do not contain element M2.
  • examples of materials that may have ferroelectricity include materials in which element M3 is added to the above metal nitride.
  • element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, and the like.
  • the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.
  • examples of materials that may have ferroelectricity include perovskite-type oxynitrides such as SrTaO 2 N or BaTaO 2 N, and GaFeO 3 having a ⁇ -alumina structure.
  • metal oxides and metal nitrides are given as examples, but the present invention is not limited to these.
  • metal oxide nitrides in which nitrogen is added to the above-mentioned metal oxides, or metal nitride oxides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.
  • the insulating layer of the semiconductor device can have a laminated structure made of multiple materials selected from the materials listed above.
  • the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, so in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials that can have ferroelectricity.
  • Metal oxides containing hafnium and/or zirconium can exhibit ferroelectricity even when processed into thin films of a few nm.
  • metal oxides containing hafnium and/or zirconium can exhibit ferroelectricity even in very small areas. Therefore, by using metal oxides containing hafnium and/or zirconium, it is possible to miniaturize semiconductor devices.
  • a layer of a material that may have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film.
  • a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in this specification.
  • Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in the crystals contained in the ferroelectric layer by an external electric field. It is also presumed that the manifestation of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulating layer to manifest ferroelectricity, the insulating layer must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, since ferroelectricity is manifested.
  • the crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of cubic, tetragonal, orthorhombic, monoclinic, and hexagonal.
  • the insulating layer may have an amorphous structure. In this case, the insulating layer may be a composite structure having an amorphous structure and a crystalline structure.
  • a Group 3 element also called a IIIa element
  • the oxygen vacancy concentration in the oxide increases, making it easier to form crystals having an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals having an orthorhombic crystal structure and increases the amount of residual polarization.
  • the amount of Group 3 element added is too large, the crystallinity of the oxide may decrease and ferroelectricity may not be easily expressed.
  • the content of Group 3 element in an oxide having one or both of hafnium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and even more preferably 0.1 atomic% or more and 3 atomic% or less.
  • the content of Group 3 element refers to the ratio of the number of atoms of Group 3 element to the sum of the number of atoms of all metal elements contained in the layer.
  • the Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.
  • an insulating layer having a function of suppressing the permeation of impurities and oxygen for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer.
  • metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide
  • metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.
  • examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate).
  • Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxide nitride, and silicon nitride.
  • an insulating layer such as a gate insulating layer that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, may be referred to as excess oxygen).
  • an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, whereby oxygen vacancies in the oxide semiconductor layer can be reduced.
  • Examples of insulating layers that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.
  • the dielectric constant be low.
  • the parasitic capacitance that occurs between wiring can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, and therefore are suitable for the insulating layer 110.
  • the concentration of impurities such as water and hydrogen in the insulating layer 110 is reduced. This makes it possible to suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 130, for example.
  • a barrier insulating layer against hydrogen as the insulating layer 110.
  • the insulating layer 110 provided on the outside of the semiconductor layer 130 have barrier properties against hydrogen, it is possible to suppress, for example, the diffusion of hydrogen into the semiconductor layer 130.
  • Materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • a barrier insulating layer refers to an insulating layer having a barrier property.
  • the barrier property refers to a property that a corresponding substance is difficult to diffuse (also referred to as a property that a corresponding substance is difficult to permeate, a property that the permeability of a corresponding substance is low, or a function of suppressing the diffusion of a corresponding substance).
  • hydrogen when described as a corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁇ .
  • impurities when described as a corresponding substance refer to impurities in a channel formation region or a semiconductor layer unless otherwise specified, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2, etc.), a copper atom, etc.
  • oxygen when described as a corresponding substance refers to at least one of, for example, an oxygen atom, an oxygen molecule, etc.
  • a silicon nitride film as the insulating layer 110.
  • the insulating layer 180 and the insulating layer 280 preferably have the barrier insulating layer against hydrogen as described above.
  • the insulating layer 180 is provided so as to surround the semiconductor layer 130.
  • the insulating layer 280 is provided so as to surround the semiconductor layer 230.
  • the insulating layer 180 provided on the outside of the semiconductor layer 130 has a barrier property against hydrogen, so that the diffusion of hydrogen into the semiconductor layer 130 can be suppressed.
  • the insulating layer 280 provided on the outside of the semiconductor layer 230 has a barrier property against hydrogen, so that the diffusion of hydrogen into the semiconductor layer 230 can be suppressed.
  • the insulating layer 180 and the insulating layer 280 preferably have one or both of an aluminum oxide film and a silicon nitride film.
  • silicon nitride also has barrier properties against oxygen. Therefore, by using silicon nitride for the insulating layer 180, it is possible to suppress the extraction of oxygen from the semiconductor layer 130. This makes it possible to suppress the formation of an excessive amount of oxygen vacancies in the semiconductor layer 130. Similarly, by using silicon nitride for the insulating layer 280, it is possible to suppress the extraction of oxygen from the semiconductor layer 230. This makes it possible to suppress the formation of an excessive amount of oxygen vacancies in the semiconductor layer 230.
  • silicon nitride for the insulating layer 180 it is possible to prevent excess oxygen from being supplied to the semiconductor layer 130. Therefore, it is possible to prevent the channel formation region of the semiconductor layer 130 from becoming excessively oxygenated, and therefore it is possible to improve the reliability of the transistor 100.
  • silicon nitride for the insulating layer 280 it is possible to improve the reliability of the transistor 200.
  • the insulating layer 180 and the insulating layer 280 each have the above-mentioned oxide insulating film, oxynitride insulating film, or insulating layer having a region containing excess oxygen.
  • an insulating layer having a region containing excess oxygen can be formed by deposition using a sputtering method in an atmosphere containing oxygen.
  • the sputtering method does not require the use of molecules containing hydrogen in the deposition gas. Therefore, by using a sputtering method to deposit the insulating layer 180 and the insulating layer 280, the hydrogen concentration in the insulating layer 180 and the insulating layer 280 can be reduced. In this way, by depositing at least a part of the layers constituting the insulating layer 180 using a sputtering method, oxygen can be supplied from the insulating layer 180 to the channel formation region of the semiconductor layer 130, thereby reducing oxygen vacancies and VoH.
  • oxygen can be supplied from the insulating layer 280 to the channel formation region of the semiconductor layer 230, thereby reducing oxygen vacancies and VoH.
  • the concentration of impurities such as water and hydrogen in the insulating layer 180 and the insulating layer 280 is reduced. This makes it possible to suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 130 and the channel formation region of the semiconductor layer 230.
  • the thickness of the insulating layer 180 on the conductive layer 120 corresponds to the channel length of the transistor 100. Therefore, the thickness of the insulating layer 180 is set appropriately in accordance with the design value of the channel length of the transistor 100.
  • the thickness of the insulating layer 280 on the conductive layer 220 corresponds to the channel length of the transistor 200. Therefore, the thickness of the insulating layer 280 is set appropriately in accordance with the design value of the channel length of the transistor 200.
  • the insulating layer 180 and the insulating layer 280 it is preferable to use a single layer structure of, for example, a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film.
  • a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film it is preferable to use a three-layer structure in which, for example, a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in this order.
  • the insulating layer 150 and the insulating layer 250 preferably have a function of capturing hydrogen and fixing hydrogen. This can reduce the hydrogen concentration in the semiconductor layer 130 and the semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor). Thus, VOH in the channel formation region can be reduced, and the channel formation region can be made i-type or substantially i-type.
  • the material of the insulating layer having the function of capturing or fixing hydrogen includes metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, for example, oxides containing hafnium and zirconium.
  • these metal oxides preferably have an amorphous structure.
  • the amorphous structure may be realized by including silicon in these oxides.
  • the metal oxide may have one or both of a crystalline region and a crystal grain boundary in a part.
  • the ability to capture or adhere to the corresponding substance can also be said to have the property of making the corresponding substance less likely to diffuse. Therefore, the ability to capture or adhere to the corresponding substance can be rephrased as barrier properties.
  • the layer in contact with the semiconductor layer 130 and the layer in contact with the semiconductor layer 230 have the function of capturing and fixing hydrogen. This makes it possible to more effectively capture or fix hydrogen contained in the semiconductor layer 130 and the hydrogen contained in the semiconductor layer 230. Therefore, the hydrogen concentration in the semiconductor layer 130 and the semiconductor layer 230 can be reduced.
  • hafnium silicate or the like may be used as the layer of the insulating layer 150 in contact with the semiconductor layer 130 and the layer of the insulating layer 250 in contact with the semiconductor layer 230.
  • the layer has an amorphous structure.
  • the layer By making the layer an amorphous structure, the formation of grain boundaries can be suppressed. By suppressing the formation of grain boundaries, the flatness of the layer can be improved. This makes the film thickness distribution of the insulating layer 150 and the insulating layer 250 uniform, and makes it possible to reduce areas with extremely thin film thickness. This makes it possible to improve the breakdown voltage of the insulating layer 150 and the insulating layer 250. In addition, it is possible to make the film thickness distribution of the film provided on the insulating layer 150 and the insulating layer 250 uniform.
  • the insulating layer 150 and the insulating layer 250 can function as insulating films with low leakage current.
  • hafnium oxide is a high dielectric constant (high-k) material
  • hafnium silicate can also be a high dielectric constant (high-k) material depending on the silicon content. Therefore, when hafnium oxide or hafnium silicate is used for the gate insulation layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulation layer. It is also possible to reduce the equivalent oxide thickness (EOT) of the gate insulation layer.
  • EOT equivalent oxide thickness
  • an oxide containing one or both of aluminum and hafnium as the insulating layer 150 and the insulating layer 250, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.
  • the aforementioned barrier insulating layer against hydrogen is preferable to use as the insulating layer 150 and the insulating layer 250.
  • a barrier insulating layer against hydrogen As the insulating layer 150, it is possible to suppress the diffusion of impurities contained in the conductive layer 220 into the semiconductor layer 130.
  • a barrier insulating layer against hydrogen As the insulating layer 250, it is possible to suppress the diffusion of impurities contained in the conductive layer 220 into the semiconductor layer 230.
  • silicon nitride has high barrier properties against hydrogen and is therefore suitable as the insulating layer 150 and the insulating layer 250.
  • the insulating layer 150 and the insulating layer 250 may have an insulating layer having a thermally stable structure, such as silicon oxide or silicon oxynitride.
  • insulating layer 150 and insulating layer 250 may have an insulating layer with a heat-stable structure between a pair of insulating layers that have the function of capturing and fixing hydrogen.
  • the insulating layer 150 and the insulating layer 250 preferably have a barrier insulating layer against oxygen. This can suppress oxidation of the conductive layer 140, the conductive layer 220, the conductive layer 240, the conductive layer 260, and the like.
  • the insulating layer 150 and the insulating layer 250 have a stacked structure, it is preferable that the layer in contact with the conductive layer 140 or the conductive layer 240 is a barrier insulating layer against oxygen.
  • the layer in contact with the conductive layer 140, the layer in contact with the conductive layer 220, the layer in contact with the conductive layer 240, and the layer in contact with the conductive layer 260 are each preferably a barrier insulating layer against oxygen.
  • oxidation of the conductive layer 220 can be suppressed.
  • a barrier insulating layer against hydrogen and oxygen for the layer of the insulating layer 250 that contacts the conductive layer 260 oxidation of the conductive layer 260 can be suppressed.
  • Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).
  • the layer in the insulating layer 150 that contacts the conductive layer 140 is preferably less permeable to oxygen than at least the insulating layer 180.
  • the layer has a barrier property against oxygen, which can prevent the side surface of the conductive layer 140 from being oxidized and an oxide film from being formed on the side surface. This can prevent a decrease in the on-current or a decrease in the field effect mobility of the transistor 100.
  • the layer in the insulating layer 250 that contacts the conductive layer 240 is preferably less permeable to oxygen than at least the insulating layer 280.
  • this layer With a barrier property against oxygen, it is possible to prevent the side surface of the conductive layer 240 from being oxidized and an oxide film from being formed on the side surface. This makes it possible to prevent a decrease in the on-current or a decrease in the field effect mobility of the transistor 200.
  • each layer constituting the insulating layer 150 and the insulating layer 250 is preferably a thin film.
  • the insulating layer 150 and the insulating layer 250 each have a thickness of 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, so that the subthreshold swing value (also called S value), which is one of the transistor characteristics, can be reduced.
  • S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with a constant drain voltage in the subthreshold region.
  • each layer constituting the insulating layer 150 and the insulating layer 250 is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 5 nm or less, and even more preferably 1 nm or more and 3 nm or less.
  • the insulating layer 150 and the insulating layer 250 it is preferable to use a three-layer structure in which a first insulating layer having a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the semiconductor layer 130 side and the semiconductor layer 230 side, respectively.
  • a material with a low dielectric constant possessed by the first insulating layer it is preferable to use silicon oxide or silicon oxynitride.
  • the first insulating layer is a layer in contact with the semiconductor layer 130 or the semiconductor layer 230.
  • oxygen can be supplied to the semiconductor layer 130 and the semiconductor layer 230.
  • the third insulating layer it is possible to suppress the diffusion of oxygen contained in the first insulating layer into the conductive layer 220 and the conductive layer 260, and to suppress the oxidation of the conductive layer 220 and the conductive layer 260.
  • a decrease in the amount of oxygen supplied from the first insulating layer to the semiconductor layer 130 and the semiconductor layer 230 can be suppressed.
  • the insulating layer 150 and the insulating layer 250 it is preferable to use a four-layer structure in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer having a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the semiconductor layer 130 side and the semiconductor layer 230 side, respectively.
  • the first insulating layer to the third insulating layer can be applied with a configuration similar to that of the layers used in the above-mentioned three-layer structure.
  • the fourth insulating layer is a layer in contact with the semiconductor layer 130 or the semiconductor layer 230.
  • the fourth insulating layer has a barrier property against oxygen, so that oxygen can be suppressed from being released from the semiconductor layer 130 and the semiconductor layer 230.
  • aluminum oxide may be used as the fourth insulating layer.
  • Aluminum oxide has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the semiconductor layer 130 or the semiconductor layer 230.
  • the film thicknesses of the fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively.
  • the insulating layer 283 is preferably a barrier insulating layer against hydrogen. This makes it possible to suppress the diffusion of hydrogen from above the insulating layer 283 into, for example, the semiconductor layer 230. Silicon nitride films and silicon nitride oxide films each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulating layer 283.
  • impurities e.g., water and hydrogen
  • silicon nitride deposited by sputtering As the insulating layer 283. Sputtering does not require the use of hydrogen-containing molecules in the deposition gas, and therefore the hydrogen concentration in the insulating layer 283 can be reduced. Furthermore, by depositing the insulating layer 283 by sputtering, silicon nitride with high density can be formed.
  • an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 283.
  • the insulating layer 283 aluminum oxide, hafnium oxide, hafnium silicate, or the like can be used.
  • the insulating layer 283 may also have a laminated structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen.
  • the insulating layer 283 may be a laminated film of aluminum oxide and silicon nitride on the aluminum oxide.
  • the insulating layer 285 functions as an interlayer film, it is preferable to use a material with a low dielectric constant as described above. For example, it is preferable that the insulating layer 285 has a silicon oxide film.
  • conductive layer For the conductive layers (conductive layer 120, conductive layer 140, conductive layer 220, conductive layer 240, conductive layer 260, conductive layer 265, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements, etc.
  • a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium,
  • a nitride of the alloy or an oxide of the alloy may be used.
  • a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum
  • conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel
  • materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing the diffusion of oxygen, or materials that maintain conductivity even when oxygen is absorbed.
  • examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide to which silicon has been added, indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide.
  • a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.
  • Conductive materials based on tungsten, copper, or aluminum are preferred because they have high conductivity.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.
  • a metal oxide is used for the channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductive layer that functions as a gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.
  • the conductive layer 120, the conductive layer 140, the conductive layer 220, and the conductive layer 240 are conductive layers in contact with the semiconductor layer 130 or the semiconductor layer 230, respectively. Therefore, for these conductive layers, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also called an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion.
  • the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 120, the conductive layer 140, the conductive layer 220, and the conductive layer 240.
  • the conductive layer 120, the conductive layer 140, the conductive layer 220, or the conductive layer 240 By using a conductive material containing oxygen as the conductive layer 120, the conductive layer 140, the conductive layer 220, or the conductive layer 240, the conductive layer 120, the conductive layer 140, the conductive layer 220, or the conductive layer 240 can maintain the conductivity even if the conductive layer 120, the conductive layer 140, the conductive layer 220, or the conductive layer 240 absorbs oxygen.
  • the conductive layer 120 is preferable because it can maintain the conductivity.
  • Figure 2A shows an example in which the conductive layer 120 has a three-layer structure of a conductive layer 120a1, a conductive layer 120a2 on the conductive layer 120a1, and a conductive layer 120b on the conductive layer 120a2. Also, Figure 2A shows an example in which the conductive layer 220 has a three-layer structure of a conductive layer 220a1, a conductive layer 220a2 on the conductive layer 220a1, and a conductive layer 220b on the conductive layer 220a2.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen as the conductive layer 120a1 and the conductive layer 220a1, a material with high conductivity as the conductive layer 120a2 and the conductive layer 220a2, and a conductive material containing oxygen (more preferably an oxide conductor) as the conductive layer 120b and the conductive layer 220b.
  • titanium nitride as the conductive layer 120a1 and the conductive layer 220a1, tungsten as the conductive layer 120a2 and the conductive layer 220a2, and an oxide conductor (e.g., ITO, ITSO, or IZO (registered trademark)) as the conductive layer 120b and the conductive layer 220b.
  • an oxide conductor e.g., ITO, ITSO, or IZO (registered trademark)
  • the oxide conductor is in contact with the semiconductor layer 130.
  • the oxide conductor is in contact with the semiconductor layer 230.
  • an oxide conductor is used for the layer closest to the channel formation region of the semiconductor layer 130 and the semiconductor layer 230.
  • the oxide conductor has a lower contact resistance with the semiconductor layer 130 and the semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened in the transistor 100 and the transistor 200. Therefore, the on-current of the transistor 100 and the transistor 200 can be increased.
  • the conductive layer 120 can maintain conductivity even when in contact with the semiconductor layer 130.
  • the conductive layer 220 can maintain conductivity even when in contact with the semiconductor layer 230.
  • the conductive layer 120 can be prevented from being excessively oxidized by the insulating layer 110.
  • the conductivity of the conductive layer 120 and the conductive layer 220 can be increased.
  • FIG. 2A shows an example in which the conductive layer 140 has a two-layer structure of a conductive layer 140a and a conductive layer 140b on the conductive layer 140a.
  • FIG. 2A also shows an example in which the conductive layer 240 has a two-layer structure of a conductive layer 240a and a conductive layer 240b on the conductive layer 240a.
  • a conductive material containing oxygen for example, for the conductive layer 140a and the conductive layer 240a.
  • an oxide conductor for example, ITO, ITSO, or IZO (registered trademark)
  • ruthenium, tungsten, titanium nitride, or tantalum nitride for example, for the conductive layer 140b and the conductive layer 240b.
  • the conductive layer 260 is preferably made of a highly conductive material such as tungsten.
  • the conductive layer 260 is preferably made of a conductive material that is not easily oxidized, or a conductive material that has the function of suppressing the diffusion of oxygen.
  • examples of the conductive material include conductive materials that contain nitrogen (e.g., titanium nitride or tantalum nitride), and conductive materials that contain oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.
  • a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed for the conductive layer 260 may be used.
  • the conductive material containing the above-mentioned metal element and nitrogen for example, titanium nitride, tantalum nitride, etc.
  • one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may be used.
  • Indium gallium zinc oxide containing nitrogen may also be used.
  • FIG. 2A shows an example in which the conductive layer 260 has a two-layer structure of a conductive layer 260a and a conductive layer 260b on the conductive layer 260a.
  • the conductive layer 260 has a two-layer structure of a conductive layer 260a and a conductive layer 260b on the conductive layer 260a.
  • tantalum nitride as the conductive layer 260a and copper as the conductive layer 260b.
  • the conductive layer 260 may also have a laminated structure of three or more layers.
  • the conductive layer 260 may have a three-layer structure of tantalum nitride, titanium nitride on tantalum nitride, and tungsten on titanium nitride.
  • the conductive layer 265 preferably has high conductivity because it functions as a gate wiring. Tungsten is preferably used for the conductive layer 265.
  • the conductive layer 265 may have the same structure as the conductive layer 260. For example, a two-layer structure of titanium nitride and tungsten may be applied.
  • the substrate on which the transistor is formed for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used.
  • a insulating substrate for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (for example, an yttria stabilized zirconia substrate), and a resin substrate are available.
  • a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide are available.
  • a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
  • the conductive substrate there are a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate in which a conductor or a semiconductor is provided on an insulating substrate a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductive substrate, and the like.
  • a substrate having elements provided thereon may be used.
  • the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.
  • FIG. 1D can be referred to for the planar structure of the transistor 100
  • FIG. 1E can be referred to for the planar structure of the transistor 200.
  • Fig. 4A is a cross-sectional view taken along dashed lines A1-A2 in Fig. 1D and Fig. 1E.
  • Fig. 4B is a cross-sectional view taken along dashed lines A3-A4 in Fig. 1D and Fig. 1E.
  • Fig. 4A shows a transistor 100A as a modified example of the transistor 100.
  • Fig. 4B shows a transistor 200A as a modified example of the transistor 200.
  • the side of the conductive layer 140b in the transistor 100A in the opening 190 is located outside the side of the conductive layer 140a in the opening 190.
  • the side of the conductive layer 240b in the transistor 200A in the opening 290 is located outside the side of the conductive layer 240a in the opening 290.
  • the conductive layers 140 and 240 shown in FIG. 4A and FIG. 4B may be formed due to the process of forming the opening 190 and the opening 290.
  • the conductive layer 140 in the transistor 100A may be formed by removing a part of the conductive layer 140b after forming the opening 190 by etching.
  • the conductive layer 240 in the transistor 200A may be formed by removing a part of the conductive layer 240b after forming the opening 290 by etching.
  • the semiconductor layer 130 contacts the side surface of the conductive layer 140a as well as the top surface of the conductive layer 140a. Therefore, in the transistor 100A, the contact area between the semiconductor layer 130 and the conductive layer 140a can be made larger than that of the transistor 100 shown in Figures 1F and 1G. As described above, a conductive material containing oxygen can be used for the conductive layer 140a. Therefore, when a metal oxide is used as the semiconductor layer 130, the contact resistance per unit area between the semiconductor layer 130 and the conductive layer 140a can be made lower than the contact resistance per unit area between the semiconductor layer 130 and the conductive layer 140b.
  • the contact resistance between the semiconductor layer 130 and the conductive layer 140 can be made lower than that of the transistor 100 shown in Figures 1F and 1G.
  • the contact resistance between the semiconductor layer 230 and the conductive layer 240 can be made lower than that of the transistor 200 shown in Figures 1F and 1G.
  • the transistors 100 and 200 shown in FIG. 1F and FIG. 1G can be manufactured using a process that is simpler than that of the transistors 100A and 200A.
  • Fig. 5A is a plan view showing a configuration example of a transistor 100B which is a modification of the transistor 100.
  • Fig. 5B is a plan view showing a configuration example of a transistor 200B which is a modification of the transistor 200.
  • Fig. 5C is a cross-sectional view taken along dashed lines A1-A2 in Fig. 5A and Fig. 5B.
  • Fig. 5D is a cross-sectional view taken along dashed lines A3-A4 in Fig. 5A and Fig. 5B.
  • the side surfaces of the conductive layer 140a and the conductive layer 140b in the transistor 100B in the opening 190 are located outside the side surfaces of the insulating layer 180 in the opening 190.
  • the side surfaces of the conductive layer 240a and the conductive layer 240b in the transistor 200B in the opening 290 are located outside the side surfaces of the insulating layer 280 in the opening 290.
  • the opening 190 provided in the insulating layer 180 is referred to as opening 190a
  • the opening 190 provided in the conductive layer 140a and the conductive layer 140b is referred to as opening 190b.
  • the opening 290 provided in the insulating layer 280 is referred to as opening 290a, and the opening 290 provided in the conductive layer 240a and the conductive layer 240b is referred to as opening 290b.
  • the process of forming the opening 190 and the opening 290 may result in the formation of the conductive layer 140 and the conductive layer 240 shown in Figures 5A to 5D, respectively.
  • Fig. 6A is a cross-sectional view taken along dashed lines A1-A2 in Fig. 1D and Fig. 1E.
  • Fig. 6B is a cross-sectional view taken along dashed lines A3-A4 in Fig. 1D and Fig. 1E.
  • Fig. 6A shows a transistor 100C as a modified example of the transistor 100.
  • Fig. 6B shows a transistor 200C as a modified example of the transistor 200.
  • opening 190 reaches conductive layer 120a.
  • Semiconductor layer 130 contacts the upper surface of conductive layer 120a inside opening 190.
  • Opening 290 reaches conductive layer 220a.
  • Semiconductor layer 230 contacts the upper surface of conductive layer 220a inside opening 290. Note that although an example in which no recess is provided in conductive layer 120a and conductive layer 220a is shown in FIG. 6A and FIG. 6B, recesses may be provided in conductive layer 120a and conductive layer 220a.
  • the conductive layer 120b has an opening 190. Therefore, the difference between the distance Tc1 and the distance Tb1 is larger in the transistor 100C than in the transistor 100 shown in FIG. 2A, for example.
  • a gate electric field is more easily applied to the channel formation region of the semiconductor layer 230 than in the transistor 200 shown in FIG. 2A, for example.
  • the transistor 100 shown in FIG. 2A contacts the upper surface of the conductive layer 120b in the region overlapping with the opening 190. Therefore, for example, the transistor 100 shown in FIG. 2A has a larger area where the semiconductor layer 130 and the conductive layer 120b contact each other than the transistor 100C.
  • a conductive material containing oxygen can be used for the conductive layer 120b. Therefore, when a metal oxide is used as the semiconductor layer 130, the contact resistance per unit area between the semiconductor layer 130 and the conductive layer 120b can be lower than the contact resistance per unit area between the semiconductor layer 130 and the conductive layer 120a.
  • the transistor 100C can have a lower contact resistance between the semiconductor layer 130 and the conductive layer 120 than the transistor 100 shown in FIG. 2A.
  • the transistor 200C can have a lower contact resistance between the semiconductor layer 230 and the conductive layer 220 than the transistor 200 shown in FIG. 2A.
  • Fig. 7A is a cross-sectional view taken along dashed lines A1-A2 in Fig. 1D and Fig. 1E.
  • Fig. 7B is a cross-sectional view taken along dashed lines A3-A4 in Fig. 1D and Fig. 1E.
  • Fig. 7A shows a transistor 100D as a modification of the transistor 100.
  • Fig. 7B shows a transistor 200D as a modification of the transistor 200.
  • the insulating layer 180 has a three-layer structure of insulating layer 180a, insulating layer 180b on insulating layer 180a, and insulating layer 180c on insulating layer 180b.
  • the insulating layer 280 has a three-layer structure of insulating layer 280a, insulating layer 280b on insulating layer 280a, and insulating layer 280c on insulating layer 280b. Note that the insulating layer 180 and the insulating layer 280 may have a single layer structure, a two-layer structure, or a four or more layer structure.
  • the insulating layer 180a has a region in contact with the upper surface of the insulating layer 110, a region in contact with the side surface of the conductive layer 120, and a region in contact with the upper surface of the conductive layer 120.
  • the insulating layer 180c has a region in contact with the lower surface of the conductive layer 140a.
  • the insulating layer 280a has a region in contact with the insulating layer 150, a region in contact with the side of the conductive layer 220, and a region in contact with the upper surface of the conductive layer 220.
  • the insulating layer 280c has a region in contact with the lower surface of the conductive layer 240a.
  • the insulating layer 180b is a layer that is in contact with the channel formation region of the semiconductor layer 130.
  • oxygen can be supplied to the semiconductor layer 130.
  • the insulating layer 280b is a layer that is in contact with the channel formation region of the semiconductor layer 230.
  • oxygen can be supplied to the semiconductor layer 230.
  • the insulating layer 180b preferably has a region with a higher oxygen content than either or both of the insulating layer 180a and the insulating layer 180c.
  • the insulating layer 180b preferably has a region with a higher oxygen content than either of the insulating layer 180a and the insulating layer 180c.
  • insulating layer 280b has a region with a higher oxygen content than one or both of insulating layer 280a and insulating layer 280c.
  • insulating layer 280b has a region with a higher oxygen content than each of insulating layer 280a and insulating layer 280c.
  • the transistor 100D can be a transistor that has good electrical characteristics and high reliability.
  • the transistor 200D can be a transistor that has good electrical characteristics and high reliability.
  • the channel length of the transistor 100D and the transistor 200D is short, the influence of oxygen vacancies and VOH in the channel formation region on the electrical characteristics and reliability is particularly large. Therefore, it is preferable to optimize the amount of oxygen supplied to the semiconductor layer 130 and the semiconductor layer 230 after sufficiently reducing the hydrogen concentration in the semiconductor layer 130 and the hydrogen concentration in the semiconductor layer 230. This makes it possible to realize a transistor with a short channel length that has good electrical characteristics and high reliability.
  • the insulating layer 180b and the insulating layer 280b are preferably formed by a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • hydrogen is not required as a deposition gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 130 and the semiconductor layer 230 can be suppressed, and the electrical characteristics of the transistor 100D and the transistor 200D can be stabilized.
  • oxygen supplied to the semiconductor layer 130 when the amount of oxygen supplied to the semiconductor layer 130 is increased, for example, after forming the insulating layer 180b, heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere may be performed.
  • oxygen may be supplied by forming an oxide film in an oxygen atmosphere on the upper surface of the insulating layer 180b by a sputtering method. The oxide film may then be removed. By performing such treatment, oxygen can be supplied to the insulating layer 180b, and the amount of oxygen supplied to the semiconductor layer 130 can be increased.
  • oxygen by performing a similar treatment after forming the insulating layer 280b, oxygen can be supplied to the insulating layer 280b, and the amount of oxygen supplied to the semiconductor layer 230 can be increased.
  • the region of the semiconductor layer 130 in contact with the insulating layer 180a and the region in contact with the insulating layer 180c receive a smaller amount of oxygen than the region in contact with the insulating layer 180b. Therefore, the region of the semiconductor layer 130 in contact with the insulating layer 180a and the region in contact with the insulating layer 180c may have low resistance. In other words, by adjusting the film thickness of the insulating layer 180a and the insulating layer 180c, the range of the region that functions as one of the source region and the drain region of the transistor 100D can be controlled.
  • the region of the semiconductor layer 230 in contact with the insulating layer 280a and the region in contact with the insulating layer 280c receive a smaller amount of oxygen than the region in contact with the insulating layer 280b. Therefore, by adjusting the film thickness of the insulating layer 280a and the insulating layer 280c, the range of the region that functions as one of the source region and the drain region of the transistor 200D can be controlled. As described above, the film thicknesses of the insulating layer 180a, the insulating layer 180c, the insulating layer 280a, and the insulating layer 280c can be appropriately set according to the characteristics required for the transistor.
  • a material with a low dielectric constant for the insulating layer 180b and the insulating layer 280b. This can reduce the parasitic capacitance that occurs between the wirings.
  • silicon oxide or silicon oxynitride can be used for the insulating layer 180b and the insulating layer 280b.
  • a barrier insulating layer against oxygen for each of the insulating layer 180a, the insulating layer 180c, the insulating layer 280a, and the insulating layer 280c.
  • the conductive layer 220 can be oxidized and the electrical resistance of the conductive layer 220 can be prevented from increasing. Furthermore, by providing the insulating layer 280c between the insulating layer 280b and the conductive layer 240, the conductive layer 240 can be oxidized and the electrical resistance of the conductive layer 240 can be prevented from increasing.
  • an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 180a.
  • the insulating layer 180a magnesium oxide, aluminum oxide, hafnium oxide, or an oxide containing hafnium and silicon, etc. may be used.
  • a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulating layer 180a.
  • insulating layers having a function of capturing or fixing hydrogen may be used as the insulating layer 180c, the insulating layer 280a, and the insulating layer 280c.
  • insulating layer 180a, insulating layer 180c, insulating layer 280a, and insulating layer 280c can be made of silicon nitride, and insulating layer 180b and insulating layer 280b can be made of silicon oxide.
  • Fig. 8A is a cross-sectional view taken along dashed lines A1-A2 in Fig. 1D and Fig. 1E.
  • Fig. 8B is a cross-sectional view taken along dashed lines A3-A4 in Fig. 1D and Fig. 1E.
  • Fig. 8A shows a transistor 100E as a modification of the transistor 100.
  • Fig. 8B shows a transistor 200E as a modification of the transistor 200.
  • the semiconductor device shown in Figures 8A and 8B differs from the semiconductor device shown in Figures 1F and 1G in that it has an insulating layer 122.
  • an insulating layer 122 is provided on an insulating layer 110, and a conductive layer 120a and an insulating layer 180 are provided on the insulating layer 122.
  • the insulating layer 122 is preferably an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen in the semiconductor layer 130 to diffuse into the insulating layer 122 through the conductive layer 120a and the conductive layer 120b, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 130 can be reduced.
  • a silicon nitride film as the insulating layer 110 and an oxide film containing hafnium and silicon (hafnium silicate film) as the insulating layer 122.
  • Fig. 9A is a cross-sectional view taken along dashed lines A1-A2 in Fig. 1D and Fig. 1E.
  • Fig. 9B is a cross-sectional view taken along dashed lines A3-A4 in Fig. 1D and Fig. 1E.
  • Fig. 9A shows a transistor 100F as a modification of the transistor 100.
  • Fig. 9B shows a transistor 200F as a modification of the transistor 200.
  • Transistor 100F has a conductive layer 155.
  • Transistor 200F has a conductive layer 255.
  • insulating layer 180 has a two-layer stacked structure of insulating layer 180d and insulating layer 180e on insulating layer 180d.
  • insulating layer 280 has a two-layer stacked structure of insulating layer 280d and insulating layer 280e on insulating layer 280d.
  • conductive layer 155 is located on insulating layer 180d, and insulating layer 180e covers the upper and side surfaces of conductive layer 155.
  • semiconductor layer 130 has a region that faces conductive layer 155 across insulating layer 180e and faces conductive layer 220 across insulating layer 150.
  • the conductive layer 255 is located on the insulating layer 280d, and the insulating layer 280e covers the upper and side surfaces of the conductive layer 255.
  • the semiconductor layer 230 has a region that faces the conductive layer 255 across the insulating layer 280e and faces the conductive layer 260 across the insulating layer 250.
  • the conductive layer 155 functions as a backgate electrode of the transistor 100F.
  • the conductive layer 255 functions as a backgate electrode of the transistor 200F.
  • the transistor 100F and the transistor 200F each have a backgate electrode, which makes it easier to control the threshold voltage and suppresses fluctuations in the threshold voltage. Therefore, the transistor 100F and the transistor 200F can be transistors with high electrical characteristics and reliability.
  • the conductive layer 155 and the conductive layer 255 can be made of, for example, a material that can be used for the conductive layer 260.
  • Fig. 10A is a cross-sectional view taken along dashed lines A1-A2 in Fig. 1D and Fig. 1E.
  • Fig. 10B is a cross-sectional view taken along dashed lines A3-A4 in Fig. 1D and Fig. 1E.
  • Fig. 10A shows a transistor 100G as a modified example of the transistor 100.
  • Fig. 10B shows a transistor 200G as a modified example of the transistor 200.
  • the insulating layer 180 has a region 180i
  • the insulating layer 280 has a region 280i.
  • Region 180i and region 280i are regions that each contain a halogen element. At least a portion of region 180i is in contact with the semiconductor layer 130, and at least a portion of region 280i is in contact with the semiconductor layer 230.
  • the halogen element is preferably one or more elements selected from chlorine, fluorine, bromine, and iodine, and more preferably chlorine or fluorine. From the viewpoint of replacing oxygen, it is preferable to use fluorine, which has a higher electronegativity than oxygen.
  • the halogen element can be supplied from the region 180i into the semiconductor layer 130.
  • the region 280i has a halogen element
  • the halogen element can be supplied from the region 280i into the semiconductor layer 230.
  • the halogen element (X) becomes a defect (VoX) in which the halogen element enters the oxygen vacancy (Vo) in the semiconductor layer 130 and the semiconductor layer 230, and has the function of generating electrons that become carriers.
  • chlorine when chlorine (Cl) is used as the halogen element, chlorine exists stably in the state of VoCl in the semiconductor layer 130 (particularly at the interface between the insulating layer 180 and the semiconductor layer 130 and in the vicinity thereof) and in the semiconductor layer 230 (particularly at the interface between the insulating layer 280 and the semiconductor layer 230 and in the vicinity thereof). At this time, Cl can enter the existing Vo, and also be replaced with oxygen to become the state of VoCl.
  • oxygen substituted with Cl also referred to as excess oxygen
  • carrier generation by VoCl occurs preferentially with respect to carrier trapping by oxygen. Therefore, negative charges (also referred to as negative fixed charges) are formed at the interface between the insulating layer 180 and the semiconductor layer 130 and in the vicinity thereof.
  • the region 180i is in contact with the channel formation region in the semiconductor layer 130.
  • the presence of negative charges in the channel formation region can shift the threshold voltage of the transistor 100G to the positive side. Therefore, even if the transistor 100G has a fine structure or the channel length of the transistor 100G is extremely short, the transistor 100G can be normally off.
  • the insulating layer 280 has the region 280i
  • the transistor 200G can be normally off even if the transistor 200G has a fine structure or the channel length of the transistor 200G is extremely short.
  • an aluminum oxide layer for the insulating layer 180 and the insulating layer 280, and to use fluorine as the halogen element.
  • the insulating layer 180 and the insulating layer 280 may have a single-layer structure or a stacked structure.
  • the insulating layer 180 and the insulating layer 280 have a stacked structure, for example, it is preferable to have one or both of a silicon oxide layer and a silicon nitride layer in addition to the aluminum oxide layer.
  • oxygen bonded to aluminum is replaced with fluorine, and the desorbed oxygen is bonded to hydrogen to become an OH group (Al-O + F ⁇ Al-F + O + H ⁇ AlF + OH).
  • the presence of AlF on the back channel side not only forms negative charges in the channel formation region and positively shifts the threshold voltages of the transistors 100G and 200G, but also has a function of capturing or fixing hydrogen (also called gettering).
  • This allows the hydrogen concentration in the semiconductor layer 130 and the semiconductor layer 230 to be reduced.
  • the hydrogen concentration in the channel formation region of transistor 100G and the hydrogen concentration in the channel formation region of transistor 200G can be reduced. Therefore, the VoH in the channel formation region can be reduced, and the channel formation region can be made i-type or substantially i-type.
  • the conductive layer 120, the conductive layer 140, the conductive layer 220, and the conductive layer 240 may also have a halogen element.
  • the conductive layer 120 or the conductive layer 140 may supply a halogen element into the semiconductor layer 130.
  • the conductive layer 220 or the conductive layer 240 may supply a halogen element into the semiconductor layer 230.
  • the side surfaces of the conductive layer 120 and the conductive layer 140 facing the opening 190 are also provided with a hatching pattern similar to that of the region 180i.
  • the side surfaces of the conductive layer 220 and the conductive layer 240 facing the opening 290 are also provided with a hatching pattern similar to that of the region 280i.
  • the semiconductor layer 130 may be in contact with the insulating layer 180 and may have a region that contains a halogen element.
  • the semiconductor layer 230 may be in contact with the insulating layer 280 and may have a region that contains a halogen element.
  • the source and drain regions of the semiconductor layer 130 and the source and drain regions of the semiconductor layer 230 preferably contain an impurity element. It is preferable to use a first element as the impurity element. Alternatively, it is preferable to use both the first element and hydrogen as the impurity element.
  • region 130n1 the region of the semiconductor layer 130 that contacts the upper surface of the conductive layer 120 in the recess 191 is referred to as region 130n1.
  • region 130n2 The region of the semiconductor layer 130 that contacts the upper surface of the conductive layer 140 is referred to as region 130n2.
  • region 230n1 The region of the semiconductor layer 230 that contacts the upper surface of the conductive layer 220 in the recess 291 is referred to as region 230n1.
  • region 230n2 regions 130n1 and 130n2 are collectively referred to as region 130n
  • regions 230n1 and 230n2 are collectively referred to as region 230n. It is preferable that regions 130n and 230n contain an impurity element.
  • the conductive layer 120, the conductive layer 140, the conductive layer 220, and the conductive layer 240 may also contain impurity elements.
  • the regions of the conductive layer 120 and the conductive layer 140 that contact the semiconductor layer 130 are also given hatching patterns similar to those of the region 130n.
  • the regions of the conductive layer 220 and the conductive layer 240 that contact the semiconductor layer 230 are also given hatching patterns similar to those of the region 230n.
  • the first element it is preferable to use one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.).
  • the first element is not limited to the above elements, but may be one or more of the first transition elements (3d transition elements, 3d transition metals), second transition elements (4d transition elements, 4d transition metals), third transition elements (5d transition elements, 5d transition metals), alkaline earth metal elements, and elements contained in the rare earth elements.
  • the first element takes away oxygen from these regions, and oxygen vacancies are generated in these regions. Then, the oxygen vacancies combine with hydrogen in the film to generate carriers, and the resistance of the source region and the drain region can be reduced.
  • This can reduce the sheet resistance of the semiconductor layer 130, the sheet resistance of the semiconductor layer 230, the contact resistance between the semiconductor layer 130 and the conductive layer 120, the contact resistance between the semiconductor layer 130 and the conductive layer 140, the contact resistance between the semiconductor layer 230 and the conductive layer 220, and the contact resistance between the semiconductor layer 230 and the conductive layer 240. Therefore, the transistor 100G and the transistor 200G can be transistors with a large on-current. By increasing the on-current, the operating voltage of the transistor can be reduced. This can reduce the power consumption of the semiconductor device.
  • the first element When an element that easily bonds with oxygen is used as the first element, the first element exists in a state bonded with oxygen in the semiconductor layer. When an element that bonds with oxygen to stabilize the first element is used as the first element, the first element in the semiconductor layer exists stably in an oxidized state, and is therefore unlikely to be desorbed by heat, for example, during the manufacturing process of the semiconductor device, and a stable low-resistance region with low electrical resistance can be realized. For this reason, it is preferable to use an element whose oxide can exist as a solid at 25°C and 1 atmosphere as the first element.
  • preferred first elements include typical nonmetallic elements other than hydrogen, typical metallic elements, and transition elements (transition metals), and examples of particularly preferred first elements include boron, phosphorus, magnesium, aluminum, and silicon.
  • boron, phosphorus, magnesium, aluminum, or silicon it is preferable to use boron, phosphorus, magnesium, aluminum, or silicon as one of the first elements.
  • boron or phosphorus it is preferable to use boron or phosphorus as one of the first elements.
  • hydrogen In addition to causing the oxygen vacancies mentioned above, hydrogen also has the ability to bond with oxygen vacancies, making it a suitable impurity element.
  • both the first element and hydrogen as impurity elements, it is easy to reduce the electrical resistance of the source and drain regions in the semiconductor layer 130 and the semiconductor layer 230, and the low electrical resistance can be stably maintained.
  • the ions generated from the raw material gas can be added without mass separation, which is preferable because it can increase productivity.
  • B 2 H 6 gas boron and hydrogen can be supplied as impurity elements.
  • PH 3 gas phosphorus and hydrogen can be supplied as impurity elements.
  • the method of supplying the impurity element is not limited to this.
  • a specific element may be added by ionizing the raw material gas and mass separating the ions.
  • boron may be added to the region 130n and the region 230n after mass separation using B 2 H 6 gas.
  • the region 130n and the region 230n preferably include a region in which the concentration of an impurity element is 1 ⁇ 10 19 atoms/cm 3 or more and 1 ⁇ 10 23 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or more and 5 ⁇ 10 22 atoms/cm 3 or less, more preferably 1 ⁇ 10 20 atoms/cm 3 or more and 1 ⁇ 10 22 atoms/cm 3 or less.
  • the concentration of each of the impurity elements is preferably in the above range.
  • impurity elements may also be supplied to the channel formation region in the semiconductor layer 130 and the channel formation region in the semiconductor layer 230.
  • a part of the impurity elements contained in the region 130n and a part of the impurity elements contained in the region 230n may diffuse into the channel formation region.
  • the concentration of the impurity element in the channel formation region is preferably 1/10 or less, and more preferably 1/100 or less, of the concentration of the impurity element in the region 130n and the region 230n.
  • the concentration of impurity elements contained in the semiconductor layer 130 (including region 130n) and the semiconductor layer 230 (including region 230n) can be analyzed by, for example, an analysis method such as SIMS or XPS.
  • an analysis method such as SIMS or XPS.
  • the concentration distribution in the depth direction can be known by combining ion sputtering from the front side or back side with XPS analysis.
  • the source and drain regions of the semiconductor layer 130 and the source and drain regions of the semiconductor layer 230 are preferably more easily doped with impurity elements than the channel formation region. Therefore, the impurity element is preferably doped from a direction perpendicular or approximately perpendicular to the upper surface of the substrate. In this case, the amount of the impurity element doped is smaller in the surfaces of the semiconductor layer 130 and the semiconductor layer 230 that are inclined with respect to the upper surface of the substrate than in the surfaces that are parallel or approximately parallel to the upper surface of the substrate. In other words, the amount of the impurity element doped is larger in the source and drain regions of the semiconductor layer 130 and the source and drain regions of the semiconductor layer 230 than in the channel formation region. Therefore, the resistance of the source and drain regions can be preferentially reduced.
  • Fig. 11A is a plan view showing a configuration example of a transistor 100H which is a modification of the transistor 100.
  • Fig. 11B is a plan view showing a configuration example of a transistor 200H which is a modification of the transistor 200.
  • Fig. 11C is a cross-sectional view taken along dashed lines A1-A2 in Fig. 11A and Fig. 11B.
  • Fig. 11D is a cross-sectional view taken along dashed lines A3-A4 in Fig. 11A and Fig. 11B.
  • the semiconductor device has an insulating layer 250 that is located inside the opening 270, a region located on the insulating layer 283, and a region located on the insulating layer 285.
  • the conductive layer 260 has a region located inside the opening 270, a region located on the insulating layer 283, and a region located on the insulating layer 285.
  • the conductive layer 260 functions as a gate wiring.
  • the conductive layer 260 has an area that overlaps with the upper surface of the conductive layer 240, but between that area of the conductive layer 260 and the conductive layer 240, the insulating layer 250, the insulating layer 283, and the insulating layer 285 are located. This makes it possible to make the parasitic capacitance between the conductive layer 240 and the conductive layer 260 smaller than the capacitance Cp between the conductive layer 140 and the conductive layer 220.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, CVD, vacuum deposition, PLD, and ALD.
  • Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner.
  • RF sputtering is mainly used when depositing insulating films
  • DC sputtering is mainly used when depositing metal conductive films.
  • Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, or carbides using reactive sputtering.
  • CVD methods can also be classified into plasma CVD (PECVD), which uses plasma, thermal CVD (TCVD: Thermal CVD), which uses heat, and photo CVD (Photo CVD), which uses light. They can also be further classified into metal CVD (MCVD: Metal CVD) and metal organic CVD (MOCVD: Metal CVD) depending on the source gas used.
  • PECVD plasma CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal CVD
  • the plasma CVD method can obtain high-quality films at relatively low temperatures. Furthermore, since the thermal CVD method does not use plasma, it is a film formation method that can reduce plasma damage to the workpiece. For example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device. On the other hand, in the case of the thermal CVD method, which does not use plasma, such plasma damage does not occur, and therefore the yield of semiconductor devices can be increased. Furthermore, since no plasma damage occurs during film formation with the thermal CVD method, a film with fewer defects can be obtained.
  • the ALD method can be a thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy, or a PEALD method in which a plasma-excited reactant is used.
  • the CVD and ALD methods are different from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage.
  • the ALD method has excellent step coverage and excellent film thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example.
  • the ALD method since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.
  • a film of any composition can be formed by changing the flow rate ratio of the raw material gases.
  • a film with a continuously changing composition can be formed by changing the flow rate ratio of the raw material gases while forming the film.
  • a film of any composition can be formed by simultaneously introducing multiple different types of precursors. Or, when multiple different types of precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by wet film formation methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • the thin film When processing the thin film that constitutes the semiconductor device, for example, a photolithography method can be used.
  • the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like.
  • an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.
  • island-like refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these.
  • ultraviolet light, KrF laser light, ArF laser light, etc. can also be used.
  • Exposure can also be performed by immersion exposure technology.
  • Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure.
  • Electron beams can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.
  • the thin film can be etched by dry etching, wet etching, sandblasting, or other methods.
  • an insulating layer 110 is formed on a substrate (not shown), a conductive layer 120a is formed on the insulating layer 110, a conductive layer 120b is formed on the conductive layer 120a, an insulating layer 180 is formed on the conductive layer 120b, a conductive layer 140a is formed on the insulating layer 180, and a conductive layer 140b is formed on the conductive layer 140a.
  • planarization treatment it is preferable to perform a planarization treatment after the insulating layer 180 is formed to planarize the top surface of the insulating layer 180.
  • a planarization treatment also referred to as a CMP treatment
  • CMP chemical mechanical polishing
  • a planarization treatment also referred to as an etch-back treatment
  • the planarization treatment of the insulating layer 180 the formation surfaces of the conductive layer 140a and the conductive layer 240b can be made flat, and discontinuity of the conductive layer 140a and the conductive layer 140b can be suppressed. Note that the planarization treatment does not have to be performed, and in that case, the manufacturing cost can be reduced.
  • step discontinuity refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step).
  • an opening 190 is formed in the conductive layer 140b, the conductive layer 140a, and the insulating layer 180 at a position where the conductive layer 120b overlaps.
  • a recess 191 is formed in the conductive layer 120b so as to overlap the opening 190.
  • the opening 190 it is preferable to process a part of the conductive layer 120b, a part of the conductive layer 140a, a part of the conductive layer 140b, and a part of the insulating layer 180 using anisotropic etching. In particular, processing by a dry etching method is preferable because it is suitable for microfabrication. Also, the opening 190 may be formed under different processing conditions depending on the layer.
  • the inclination of the side surface of the conductive layer 120b in the recess 191 and the inclination of the side surface of the insulating layer 180, the conductive layer 140a, and the conductive layer 140b inside the opening 190 may differ from each other.
  • a region containing a halogen element may be provided on at least one of the upper surface and side surface of the conductive layer 120b in the recess 191, the side surface of the insulating layer 180, the conductive layer 140a, and the conductive layer 140b in the opening 190, and the upper surface of the conductive layer 140b.
  • regions include a region containing fluorine, a region containing chlorine, and a region containing fluorine and chlorine.
  • halogen elements derived from the etching gas used in the dry etching may remain in such regions.
  • the heat treatment is performed, for example, at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • an atmosphere of nitrogen gas or an inert gas or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the oxygen that has been desorbed.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less.
  • the semiconductor layer 130 is formed so as to cover the opening 190.
  • the semiconductor layer 130 is formed so as to contact the upper surface of the conductive layer 140b.
  • the semiconductor layer 130 is also formed so as to contact the bottom and sidewalls of the recess 191.
  • the semiconductor layer 130 is formed inside the opening 190 so as to contact the side surfaces of the insulating layer 180, the side surfaces of the conductive layer 140a, and the side surfaces of the conductive layer 140b.
  • the semiconductor layer 130 can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the semiconductor layer 130 is preferably formed as a film of as uniform thickness as possible along the top and side surfaces of the conductive layer 120b in the recess 191, the side surfaces of the insulating layer 180, the conductive layer 140a, and the conductive layer 140b in the opening 190, and the top surface of the conductive layer 140b.
  • a thin film can be formed with good controllability. Therefore, it is preferable to form the semiconductor layer 130 using the ALD method.
  • the semiconductor layer 130 has high crystallinity, the diffusion of impurities in the semiconductor layer 130 is suppressed, so that the electrical characteristics of the transistor are less likely to fluctuate and reliability can be improved.
  • the semiconductor layer 130 is formed by a sputtering method, it is easier to form a layer with high crystallinity than when an ALD method is used, which is preferable.
  • the semiconductor layer 130 is formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas.
  • the proportion of oxygen contained in the sputtering gas By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.
  • an In-M-Zn oxide target can be used.
  • an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and not more than 100%, preferably 70% to 100%.
  • a transistor using an oxygen-excessive oxide semiconductor in a channel formation region can have relatively high reliability.
  • one embodiment of the present invention is not limited thereto.
  • An oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%, when the semiconductor layer 130 is formed.
  • a transistor using an oxygen-deficient oxide semiconductor in a channel formation region can have relatively high field-effect mobility.
  • the crystallinity of the oxide semiconductor layer can be improved by forming the film while heating the substrate.
  • the semiconductor layer 130 preferably has both a layer formed by the ALD method and a layer formed by the sputtering method. This allows the semiconductor layer 130 to be formed with good coverage and to have high crystallinity.
  • the semiconductor layer 130 preferably has, for example, a layer formed by the sputtering method and a layer formed by the ALD method stacked in this order.
  • An oxide semiconductor layer formed by the sputtering method is likely to have crystallinity. Therefore, by providing a crystalline oxide semiconductor layer as the lower layer of the semiconductor layer 130, the crystallinity of the upper layer of the semiconductor layer 130 can be improved.
  • even if a pinhole or a step is formed in the oxide semiconductor layer formed by the sputtering method it can be blocked by the oxide semiconductor layer formed by the ALD method, which has good coverage.
  • the semiconductor layer 130 may be a two-layer structure in which a layer formed using a sputtering method and a layer formed using an ALD method are stacked in this order, a two-layer structure in which a layer formed using an ALD method and a layer formed using a sputtering method are stacked in this order, a three-layer structure in which a layer formed using an ALD method, a layer formed using a sputtering method and a layer formed using an ALD method are stacked in this order, or a three-layer structure in which a layer formed using a sputtering method, a layer formed using an ALD method and a layer formed using a sputtering method are stacked in this order.
  • the heat treatment is preferably performed in a temperature range in which the semiconductor layer 130 does not become polycrystallized.
  • the temperature of the heat treatment is preferably 100°C or higher and 650°C or lower, more preferably 250°C or higher and 600°C or lower, and even more preferably 350°C or higher and 550°C or lower.
  • the gas used in the above heat treatment is preferably highly purified.
  • a highly purified gas By performing the heat treatment using a highly purified gas, it is possible to prevent, for example, moisture from being absorbed into the semiconductor layer 130 as much as possible.
  • the heat treatment is performed at a temperature of 450° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas of 4:1.
  • This heat treatment including oxygen gas can reduce impurities such as carbon, water, and hydrogen in the semiconductor layer 130.
  • impurities such as carbon, water, and hydrogen in the semiconductor layer 130.
  • the crystallinity of the semiconductor layer 130 can be improved, and a denser and more compact structure can be obtained.
  • This increases the crystalline region in the semiconductor layer 130, and reduces the in-plane variation of the crystalline region in the semiconductor layer 130. Therefore, the in-plane variation of the electrical characteristics of the transistor can be reduced.
  • the insulating layer 180 contains oxygen
  • oxygen also called excess oxygen
  • excess oxygen that is desorbed by heating from an insulating layer in contact with the semiconductor layer 130 or an insulating layer located near the semiconductor layer 130 may be supplied to the semiconductor layer 130. Since the excess oxygen has a function of trapping electrons, negative charges are easily formed. Therefore, the threshold voltage of the transistor is shifted in the positive direction, making it possible to realize a normally-off transistor.
  • the semiconductor layer 130, the conductive layer 140a, and the conductive layer 140b are processed into an island shape, and a part of the upper surface of the insulating layer 180 is exposed.
  • the semiconductor layer 130, the conductive layer 140a, and the conductive layer 140b can be processed using the same mask. This is preferable because it reduces the number of masks required to manufacture a semiconductor device compared to, for example, processing the semiconductor layer 130, and the conductive layer 140a and the conductive layer 140b using different masks.
  • the insulating layer 150 is formed to have a region located on the conductive layer 140b and a region located on the semiconductor layer 130 inside the opening 190. Then, a conductive layer 220a is formed on the insulating layer 150, and a conductive layer 220b is formed on the conductive layer 220a. The insulating layer 150 is formed to cover the semiconductor layer 130, the conductive layer 140a, and the conductive layer 140b. Specifically, the insulating layer 150 can be formed in contact with the semiconductor layer 130, the insulating layer 180, the conductive layer 140a, and the conductive layer 140b.
  • the insulating layer 150 is formed along the semiconductor layer 130 that covers the sidewall of the opening 190 with a high aspect ratio. Therefore, it is preferable to use a film formation method with good coverage for forming the insulating layer 150.
  • the ALD method is preferably used for forming the insulating layer 150.
  • the conductive layer 220a is formed so as to fill at least a part of the recess of the insulating layer 150. Therefore, it is preferable to use a film formation method with good embedding properties for forming the conductive layer 220a.
  • the CVD method is preferably used for forming the conductive layer 220a.
  • the conductive layer 220a can have a laminated structure of a layer formed using, for example, the ALD method with good coverage properties and a layer formed using the CVD method with good embedding properties.
  • the conductive layer 220b can be formed using the same method as the method that can be used for forming the conductive layer 220a.
  • the conductive layer 220b can be formed using, for example, the CVD method.
  • a planarization treatment may be performed on the upper surface of the conductive layer 220a.
  • the conductive layer 220a can be processed, for example, by using an etching method.
  • a CMP treatment is preferable.
  • a planarization treatment may be performed on the upper surface of the conductive layer 220b.
  • the conductive layer 220a is formed to have an area facing the semiconductor layer 130 with the insulating layer 150 sandwiched between them inside the opening 190.
  • the conductive layer 220a and the conductive layer 220b are also formed to have an area overlapping with the conductive layer 140a and the conductive layer 140b through the insulating layer 150.
  • FIG. 12E shows an example in which part of the side surface of the conductive layer 140a and part of the side surface of the conductive layer 140b are covered by the conductive layer 220a through the insulating layer 150.
  • an insulating layer 280 is formed on the conductive layer 220b and on the insulating layer 150, a conductive layer 240a is formed on the insulating layer 280, and a conductive layer 240b is formed on the conductive layer 240a.
  • an opening 290 is formed in the conductive layer 240b, the conductive layer 240a, and the insulating layer 280 at a position where the conductive layer 240b overlaps with the conductive layer 220b.
  • a recess 291 is formed in the conductive layer 220b so as to overlap with the opening 290.
  • the description of the formation of the insulating layer 180, the conductive layer 140a, the conductive layer 140b, the opening 190, and the recess 191 described above can be referred to.
  • the opening 290 is formed at a position where it at least partially overlaps with the opening 190.
  • the recess 191 is formed at a position where it overlaps with the opening 190.
  • the recess 191, the opening 190, the recess 291, and the opening 290 at least partially overlap each other. This allows the area occupied by the memory cell 10 to be smaller than when, for example, the opening 190 and the opening 290 do not overlap. Therefore, a semiconductor device that can be miniaturized or highly integrated can be manufactured. Also, a semiconductor device with a large memory capacity per unit area can be manufactured.
  • a semiconductor layer 230 is formed so as to cover the opening 290.
  • the semiconductor layer 230 is formed so as to contact the upper surface of the conductive layer 240b.
  • the semiconductor layer 230 is also formed so as to contact the bottom and sidewalls of the recess 291.
  • the semiconductor layer 230 is formed inside the opening 290 so as to contact the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 240a, and the side surfaces of the conductive layer 240b.
  • the description of the formation of the semiconductor layer 130 described above can be referred to.
  • a sacrificial layer 262 is formed so as to cover the conductive layer 240a, the conductive layer 240b, and the semiconductor layer 230.
  • the sacrificial layer 262 is formed so that at least a portion of the sacrificial layer 262 is located inside the opening 290.
  • a SOC (Spin On Carbon) film and a SOG (Spin On Glass) film are suitable.
  • the sacrificial layer 262 is preferably a two-layer structure, for example, of a SOC film and a SOG film on the SOC film.
  • the sacrificial layer 262 is removed.
  • a gate insulating layer and a gate electrode (insulating layer 250 and conductive layer 260) will be provided in a later process. Therefore, it is preferable that the sacrificial layer 262 has a small area overlapping with the upper surface of the conductive layer 240b, or does not overlap with the upper surface of the conductive layer 240b. This makes it possible to manufacture a semiconductor device with a small parasitic capacitance between the conductive layer 240b and the conductive layer 260.
  • the width of the sacrificial layer 262 does not exceed the sum of the width D of the opening 290 and twice the film thickness of the insulating layer 250 to be formed later.
  • FIG. 13C shows an example in which the width of the sacrificial layer 262 is the width D of the opening 290.
  • an insulating layer 283 is formed to cover the insulating layer 280, the conductive layer 240a, the conductive layer 240b, the semiconductor layer 230, and the sacrificial layer 262, and an insulating layer 285 is formed on the insulating layer 283.
  • the insulating layer 285 By making the insulating layer 285 thicker, the distance between the conductive layer 240b and the gate wiring (conductive layer 260 or conductive layer 265) can be increased, and the parasitic capacitance between the conductive layer 240b and the gate wiring can be reduced. Specifically, by making the insulating layer 285 thicker than the insulating layer 150, the parasitic capacitance between the conductive layer 240b and the conductive layer 265 formed in a later process can be made smaller than the capacitance Cp between the conductive layer 140b and the conductive layer 220.
  • a silicon oxide film as the insulating layer 285 it is preferable to form a silicon oxide film as the insulating layer 285 using a sputtering method.
  • the sacrificial layer 262 is exposed to plasma containing oxygen when forming a silicon oxide film as the insulating layer 285 by sputtering. Therefore, a part or all of the sacrificial layer 262 may be etched. In this way, depending on the method of forming the insulating layer 285, the shape of the sacrificial layer 262 may be reduced or the sacrificial layer 262 may disappear. For this reason, it is preferable that the insulating layer formed on the sacrificial layer 262 has a laminated structure of the insulating layer 283 and the insulating layer 285, rather than a single layer of the insulating layer 285. This provides the effects of expanding the range of materials to be selected for the sacrificial layer 262 and the insulating layer 285, reducing the difficulty of manufacturing the semiconductor device, and the like.
  • an oxide film is used for the insulating layer 283, it is preferable to form it using a method other than the sputtering method, for example, the ALD method.
  • the ALD method it is preferable to form an aluminum oxide film, a hafnium oxide film, or a nitride film (such as a silicon nitride film) as the insulating layer 283 using the ALD method. This makes it possible to prevent the sacrificial layer 262 from being unintentionally processed when the insulating layer 283 is formed.
  • a planarization process is performed on the insulating layer 285 and the sacrificial layer 262. This exposes the upper surface of the sacrificial layer 262, and planarizes the upper surfaces of the sacrificial layer 262, the insulating layer 283, and the insulating layer 285.
  • CMP is a suitable method for the planarization process.
  • the planarization process at least a portion of the insulating layer 283 and the insulating layer 285 is removed.
  • a portion of the sacrificial layer 262 may be removed.
  • the sacrificial layer 262 is removed.
  • an opening 270 having an area overlapping with the opening 290 is formed in the insulating layer 285.
  • an opening 270 having an area overlapping with the opening 290 is formed in the insulating layer 283.
  • an insulating layer 250 is formed to cover the openings 270 and 290, and a conductive layer 260 is formed on the insulating layer 250.
  • the insulating layer 250 is provided in contact with the semiconductor layer 230, the insulating layer 283, and the insulating layer 285.
  • the insulating layer 250 and the conductive layer 260 are formed inside the opening 290 and the opening 270, respectively, which have a large aspect ratio. Therefore, it is preferable to use a film formation method with good coverage or embedding properties for forming the insulating layer 250 and the conductive layer 260, such as the ALD method or the CVD method. For example, it is preferable to use the ALD method for forming the insulating layer 250. Also, it is preferable to use the CVD method for forming the conductive layer 260. For example, when the conductive layer 260 has a stacked structure, it is preferable to use the CVD method for forming at least one layer.
  • a planarization process is performed on the conductive layer 260 to expose the upper surfaces of the insulating layer 283 and the insulating layer 285, and to planarize the upper surfaces of the conductive layer 260, the insulating layer 250, the insulating layer 283, and the insulating layer 285.
  • CMP is a suitable method for the planarization process.
  • the planarization process at least the regions of the conductive layer 260 and the insulating layer 250 that overlap with the upper surface of the insulating layer 285 are removed. This makes it possible to remove the region of the conductive layer 260 that overlaps with the upper surface of the conductive layer 240b. This makes it possible to suppress the occurrence of parasitic capacitance between the conductive layer 260 and the conductive layer 240b.
  • the height of the upper surface of the insulating layer 285 and the height of the upper surface of the conductive layer 260 are the same.
  • one of the height of the upper surface of the insulating layer 285 and the height of the upper surface of the conductive layer 260 may be higher than the other.
  • the vertical relationship between the heights of the upper surfaces of the two layers can be controlled by the difference in the polishing rates of the materials of the insulating layer 285 and the conductive layer 260.
  • a conductive layer 265 is formed on the insulating layer 285, the insulating layer 283, the insulating layer 250, and the conductive layer 260.
  • the conductive layer 265 is formed so as to be in contact with the upper surface of the conductive layer 260.
  • the conductive layer 265 can also be formed so as to be in contact with the upper surface of the insulating layer 285, the upper surface of the insulating layer 283, and the upper surface of the insulating layer 250.
  • Insulating layer 283 and insulating layer 285 are located between conductive layer 265 and conductive layer 240b. This allows the parasitic capacitance between conductive layer 240 and conductive layer 260 to be smaller than the capacitance Cp between conductive layer 140 and conductive layer 220.
  • a semiconductor device according to one embodiment of the present invention can be manufactured.
  • the insulating layer 180 and the insulating layer 280 may each be provided with a region having a halogen element.
  • the semiconductor layer 130 and the semiconductor layer 230 may each be provided with a region having a halogen element.
  • the semiconductor layer 130 and the semiconductor layer 230 may each be provided with a region having the first element.
  • At least one of the conductive layer 120a, the conductive layer 120b, the conductive layer 140a, the conductive layer 140b, the conductive layer 220a, the conductive layer 220b, the conductive layer 240a, and the conductive layer 240b may be provided with a region having the first element.
  • the following description can be applied even in the case where a halogen element or the first element described above is supplied to these layers by, for example, replacing the insulating layer 180, the semiconductor layer 130, the conductive layer 120a, the conductive layer 120b, the conductive layer 140a, and the conductive layer 140b with the insulating layer 280, the semiconductor layer 230, the conductive layer 220a, the conductive layer 220b, the conductive layer 240a, and the conductive layer 240b, respectively.
  • halogen element 188 is supplied to the side of opening 190 of insulating layer 180.
  • the region of insulating layer 180 to which halogen element 188 is supplied is shown as region 180i.
  • Region 180i includes at least the side of opening 190 of insulating layer 180.
  • halogen element 188 may also be supplied to one or more of conductive layer 140a, conductive layer 140b, conductive layer 120a, and conductive layer 120b.
  • FIG. 15A shows an example in which the sidewall of the opening 190 is perpendicular to the upper surface of the substrate.
  • the sidewall of the opening 190 is perpendicular or approximately perpendicular to the upper surface of the substrate, or has a tapered shape. Therefore, if the halogen element 188 is added perpendicular or approximately perpendicular to the upper surface of the substrate, it may be difficult to supply the halogen element 188 uniformly to a desired region.
  • the halogen element 188 is added from a direction tilted at an angle of more than 0 degrees and less than 90 degrees with respect to the upper surface of the substrate.
  • FIG. 15A shows an example in which the halogen element 188 is added in a state tilted at an angle ⁇ 188 with respect to the upper surface of the insulating layer 110.
  • the angle ⁇ 188 is preferably more than 0 degrees and less than 90 degrees, and is preferably 15 degrees or more and 80 degrees or less. This makes it easier to supply the halogen element to the side of the opening 190 of the insulating layer 180.
  • halogen element 188 The elements that can be used for halogen element 188 are as described above.
  • the halogen element 188 can be preferably supplied by plasma ion doping or ion implantation. These methods allow the concentration profile in the depth direction to be controlled with high precision by the ion acceleration voltage, dose, etc.
  • the angle ⁇ 188 can be set within the above range by tilting either or both of the substrate to be processed and the ion irradiation unit in the device.
  • Region 180i is a region in contact with the channel formation region of the semiconductor layer 130. Therefore, if other impurity elements are also supplied to region 180i when supplying the halogen element 188, the impurity elements may diffuse into the channel formation region of the semiconductor layer 130, affecting the characteristics and reliability of the transistor. Therefore, it is preferable to use an ion implantation method to supply the halogen element 188 to region 180i with high purity.
  • productivity can be improved by using the plasma ion doping method, in which the source gas is ionized and the ions are added without mass separation.
  • the ion implantation equipment or ion doping equipment used to supply halogen element 188 is also used in the manufacture of Si transistors such as LTPS transistors, so it is preferable because the equipment in the existing LTPS manufacturing line can be reused and no new capital investment is required. This makes it possible to reduce the capital investment costs associated with the manufacture of semiconductor devices.
  • the gas containing the halogen element described above can be used.
  • the gas either a gas of a simple halogen or a halide gas can be used .
  • fluorine typically, F2 gas, BF3 gas, C4F6 gas , C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, CH2F2 gas, or CH3F gas
  • chlorine typically , Cl2 gas, BCl3 gas, SiCl4 gas, or CCl4 gas can be used.
  • a mixed gas in which these source gases are diluted with hydrogen or a noble gas may be used.
  • the ion source is not limited to a gas, and a solid or liquid may be heated and vaporized.
  • the supply of the halogen element 188 can be controlled by setting conditions such as acceleration voltage and dose amount, taking into account the composition, density, and film thickness of the insulating layer 180.
  • the method of supplying the halogen element 188 is not limited, and for example, plasma processing or processing utilizing thermal diffusion by heating may be used.
  • the impurity element can be supplied by generating plasma in a gas atmosphere containing the halogen element to be supplied and performing plasma processing.
  • a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high density plasma CVD apparatus, or the like may be used as an apparatus for generating the above plasma.
  • the supplying step of the halogen element 188 may be performed while heating the substrate. This makes it possible to repair damage to the insulating layer 180 that occurs when the halogen element 188 is added. In other words, the addition of the halogen element 188 to the insulating layer 180 and the repair of the damage caused by the addition can be performed in parallel.
  • the substrate temperature during the halogen element 188 supply process is preferably 150°C or higher and lower than the distortion point of the substrate, more preferably 200°C or higher and 500°C or lower, even more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 400°C or lower, even more preferably 250°C or higher and 350°C or lower, or 300°C or higher and 400°C or lower, even more preferably 300°C or higher and 350°C or lower.
  • the semiconductor layer 130 by forming the semiconductor layer 130 while heating the substrate, it may be possible to supply the halogen element from the region 180i to the semiconductor layer 130. Also, during a heat treatment performed after forming the semiconductor layer 130, it may be possible to supply the halogen element from the region 180i to the semiconductor layer 130.
  • the halogen element 188 is added to the insulating layer 180, and then the halogen element 188 is supplied from the insulating layer 180 to the semiconductor layer 130.
  • This makes it possible to suppress damage to the channel formation region of the semiconductor layer 130 caused by the addition of the element, and to suppress deterioration of the crystallinity of the channel formation region caused by the addition of the element. Therefore, the reliability of the transistor can be improved.
  • the halogen element 188 may be supplied to the side surface of the semiconductor layer 130 located inside the opening 190.
  • the region of the semiconductor layer 130 to which the halogen element 188 is supplied is shown as region 130i.
  • Region 130i includes at least the side surface of the semiconductor layer 130 located inside the opening 190.
  • the halogen element 188 may also be supplied to one or more of the insulating layer 180, the conductive layer 140a, the conductive layer 140b, the conductive layer 120a, and the conductive layer 120b.
  • an impurity element 189 is supplied to the upper surface of the conductive layer 120b and the upper surface of the conductive layer 140b.
  • a region to which the impurity element 189 is supplied is shown as 220n.
  • a region to which the impurity element 189 is supplied is shown as 140n.
  • the semiconductor layer 130 is formed and, for example, a heat treatment is performed, so that the impurity element 189 can be supplied from the region 120n and the region 140n to the source region and the drain region of the semiconductor layer 130.
  • the impurity element 189 By supplying the impurity element 189 to the semiconductor layer 130 through the conductive layer 120 or the conductive layer 140, it is possible to suppress a decrease in the crystallinity of the semiconductor layer 130 compared to the case where the impurity element 189 is added directly to the semiconductor layer 130. Therefore, it is possible to suppress an increase in electrical resistance due to a decrease in crystallinity.
  • the impurity element 189 may be supplied to the semiconductor layer 130.
  • the region in the semiconductor layer 130 to which the impurity element 189 is supplied is shown as region 130n.
  • the impurity element 189 By adding the impurity element 189 to the semiconductor layer 130, the sheet resistance of the semiconductor layer 130, the contact resistance between the semiconductor layer 130 and the conductive layer 120, and the contact resistance between the semiconductor layer 130 and the conductive layer 140 can each be reduced.
  • the impurity element 189 is preferably added from a direction perpendicular or approximately perpendicular to the upper surface of the substrate.
  • a surface that is inclined with respect to the upper surface of the substrate, or a surface that is perpendicular or approximately perpendicular to the upper surface of the substrate is doped with a smaller amount of impurity element than a surface that is parallel or approximately parallel to the upper surface of the substrate.
  • a larger amount of impurity element is doped in the source and drain regions of the semiconductor layer 130 than in the channel formation region. Therefore, the resistance of the source and drain regions can be preferentially reduced.
  • Figure 15D shows an example in which regions 130n are formed at and near the interface between the semiconductor layer 130 and the upper surface of the conductive layer 120b, and at and near the interface between the semiconductor layer 130 and the upper surface of the conductive layer 140b.
  • impurity element 189 The elements that can be used for impurity element 189 are as described above.
  • the impurity element 189 can be preferably supplied by plasma ion doping or ion implantation. These methods allow the concentration profile in the depth direction to be controlled with high precision by the ion acceleration voltage, dose, etc.
  • the purity of the supplied impurity element can be increased.
  • the ion implantation method it is preferable to use the first element described above as the impurity element 189, and it is more preferable to use boron or phosphorus.
  • boron or phosphorus By using an element that bonds with oxygen to stabilize the impurity element 189, a stable region 130n with low electrical resistance can be realized.
  • productivity can be improved by using a plasma ion doping method in which the source gas is ionized and the ions are added without mass separation.
  • the plasma ion doping method it is preferable to use both the first element and hydrogen as the impurity element 189, and it is even more preferable to use both boron or phosphorus and hydrogen.
  • both an element that bonds with oxygen to stabilize it and hydrogen it is easy to reduce the electrical resistance of the region 130n and the low electrical resistance state can be stably maintained.
  • the ion implantation equipment or ion doping equipment used to supply the impurity element 189 is also used in the manufacture of Si transistors such as LTPS transistors, so it is preferable because the equipment in the existing LTPS manufacturing line can be reused and no new capital investment is required. This makes it possible to reduce the capital investment costs associated with the manufacture of semiconductor devices.
  • the impurity element 189 In the supplying process of the impurity element 189, it is preferable to control the processing conditions so that the concentration of the impurity element in the region of the semiconductor layer 130 that overlaps with the top surface of the conductive layer 120b or the top surface of the conductive layer 140b is higher than the concentration of the impurity element in other regions. This allows the impurity element 189 to be supplied at an optimal concentration to the source region and drain region of the semiconductor layer 130.
  • a gas containing the above - mentioned impurity element can be used as a source gas for the impurity element 189.
  • B2H6 gas or BF3 gas can be used.
  • phosphorus typically, PH3 gas can be used.
  • a mixed gas in which these source gases are diluted with hydrogen or a noble gas may also be used.
  • source gas examples include CH4 , N2 , NH3, AlH3 , AlCl3 , SiH4 , Si2H6 , F2 , HF, H2 , ( C5H5 ) 2Mg , and noble gases.
  • the ion source is not limited to gas, and a solid or liquid may be heated and vaporized.
  • the impurity element 189 it is preferable to use a gas containing boron and hydrogen to supply boron and hydrogen as the impurity element 189.
  • the impurity element 189 can be added without mass separation, and the resistance of the semiconductor layer 130 can be easily reduced, which is preferable because it is possible to improve both the productivity and characteristics of the semiconductor device.
  • the same source gas in the supplying process of the halogen element 188 and the supplying process of the impurity element 189, since this can reduce manufacturing costs.
  • the same source gas for example, by ionizing BF3 gas and subjecting the ions to mass separation, it is possible to supply fluorine as the halogen element 188 and to supply boron as the impurity element 189.
  • the supply of the impurity element 189 can be controlled by setting conditions such as acceleration voltage and dose amount, taking into account the composition, density, and film thickness of the semiconductor layer 130.
  • the method of supplying the impurity element 189 is not limited, and for example, plasma treatment or treatment using thermal diffusion by heating may be used.
  • the impurity element can be supplied by generating plasma in a gas atmosphere containing the impurity element to be supplied and performing plasma treatment.
  • a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high density plasma CVD apparatus, or the like can be used as an apparatus for generating the plasma.
  • the step of supplying the impurity element 189 is preferably performed while heating the substrate. This makes it possible to repair damage to the semiconductor layer 130 that occurs when the impurity element 189 is added. In other words, the addition of the impurity element 189 to the semiconductor layer 130 and the repair of damage caused by the addition can be performed in parallel.
  • the substrate temperature during the supply process of the impurity element 189 is preferably 150°C or higher and lower than the distortion point of the substrate, more preferably 200°C or higher and 500°C or lower, even more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 400°C or lower, even more preferably 250°C or higher and 350°C or lower, or 300°C or higher and 400°C or lower, even more preferably 300°C or higher and 350°C or lower.
  • a heat treatment may be performed. By performing the heat treatment, damage that the semiconductor layer 130 sustained during the process of supplying the impurity element 189 can be repaired.
  • the impurity element 189 By using an element that bonds with oxygen to stabilize the impurity element 189, it is possible to prevent the impurity element 189 from being detached due to heat applied during the manufacturing process of the semiconductor device, for example. Therefore, even if a heat treatment is performed after the impurity element 189 is added, or a film formation process is performed while the substrate is heated, the electrical resistance in the region 130n can be maintained at a low level.
  • impurity elements 189 may be added to the semiconductor layer 130 through the insulating layer 150. At this time, the impurity elements 189 may also be supplied to the insulating layer 150. It is preferable that the region 130n has a region with a higher concentration of the impurity elements 189 than the insulating layer 150, because this can reduce the electrical resistance of the region 130n.
  • the impurity element 189 By supplying the impurity element 189 to the semiconductor layer 130 through the insulating layer 150, it is possible to suppress a decrease in the crystallinity of the semiconductor layer 130 compared to the case where the impurity element 189 is added directly to the semiconductor layer 130. Therefore, it is possible to suppress an increase in electrical resistance due to a decrease in crystallinity.
  • the insulating layer 150 is formed after the impurity element 189 is added, the inside of the deposition chamber for the insulating layer 150 may be contaminated. For this reason, it is preferable to add the impurity element 189 after the insulating layer 150 is formed.
  • the thickness of the insulating layer 150 in the direction in which the impurity element 189 is added is thicker in the region provided along the side of the insulating layer 180 than in the region provided along the top surface of the conductive layer 120b or the top surface of the conductive layer 140b.
  • the amount of the impurity element 189 added is greater in the region of the semiconductor layer 130 provided along the top surface of the conductive layer 120b or the top surface of the conductive layer 140b than in the region provided along the side of the insulating layer 180. In this way, the impurity element 189 is prevented from entering the channel formation region of the semiconductor layer 130, and the resistance of the source region and the drain region can be preferentially reduced.
  • the semiconductor device of one embodiment of the present invention has a structure in which a gate electric field is easily applied to the semiconductor layer. Therefore, the electrical characteristics of the transistor can be improved.
  • the semiconductor device of one embodiment of the present invention has a structure in which data can be retained without providing a capacitor. Therefore, a low-cost semiconductor device can be provided.
  • a memory cell array can be formed by arranging memory cells 10 in a three-dimensional matrix.
  • Figure 16A is a plan view of a memory device.
  • Figure 16A shows an example in which 2 x 2 memory cells 10 (memory cells 10a to 10d) are arranged in the X and Y directions.
  • Figure 16B is a cross-sectional view taken along dashed line B1-B2 in Figure 16A.
  • two memory cells are connected to a common wiring (conductive layer 145 and conductive layer 245).
  • conductive layer 140 and conductive layer 265 are provided in memory cell 10a and memory cell 10b, respectively. Also, as shown in Figure 16A, one conductive layer 140 and one conductive layer 265 are provided in common to memory cell 10a and memory cell 10c. That is, conductive layer 140 contacts semiconductor layer 130 of memory cell 10a and semiconductor layer 130 of memory cell 10c. Also, another conductive layer 140 and conductive layer 265 are provided in common to memory cell 10b and memory cell 10d.
  • one conductive layer 240 is provided in common to memory cell 10a and memory cell 10b. That is, the conductive layer 240 contacts the semiconductor layer 230 of memory cell 10a and the semiconductor layer 230 of memory cell 10b. In addition, another conductive layer 240 is provided in common to memory cell 10c and memory cell 10d.
  • the memory device shown in FIG. 16A and FIG. 16B also has a conductive layer 145 and a conductive layer 245 that are electrically connected to the memory cell 10a and the memory cell 10b and function as plugs (also called connection electrodes).
  • the conductive layer 145 is disposed inside the openings formed in the insulating layer 110, the insulating layer 180, the insulating layer 150, and the insulating layer 280, and is in contact with the lower surface of the conductive layer 240a.
  • the conductive layer 245 is disposed inside the openings formed in the insulating layer 287, the insulating layer 285, the insulating layer 283, and the semiconductor layer 230, and is in contact with the upper surface of the conductive layer 240b.
  • the conductive layer 145 and the conductive layer 245 can be made of a conductive material that can be used for the conductive layer 140 and the conductive layer 240, or the like.
  • the conductive layer 245 can be in contact with the upper surface of the conductive layer 240a.
  • the conductive layer 245 can be in contact with the upper surface of the semiconductor layer 230. That is, the conductive layer 240b may have an opening at a position overlapping with the conductive layer 245.
  • the semiconductor layer 230 does not have to have an opening at a position overlapping with the conductive layer 245.
  • a connection point between the memory cell and the plug it is preferable that, among the layers constituting the conductive layer 240 and the semiconductor layer 230, a layer having a low contact resistance with the conductive layer 245 is in contact with the conductive layer 245.
  • the conductive layer 145 can be configured to be in contact with the bottom surface of the conductive layer 240b or the bottom surface of the semiconductor layer 230. That is, the conductive layer 240a may have an opening at a position overlapping with the conductive layer 245. Of the layers constituting the conductive layer 240 and the semiconductor layer 230, it is preferable that a layer having a low contact resistance with the conductive layer 145 be in contact with the conductive layer 145.
  • the layer having low wiring resistance be in contact with the conductive layer 145 and the conductive layer 245.
  • the insulating layer 287 functions as an interlayer film, it is preferable that the insulating layer 287 has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wiring can be reduced.
  • the concentration of impurities such as water and hydrogen in the insulating layer 287 is reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 230.
  • the conductive layer 145 and the conductive layer 245 function as plugs or wirings for electrically connecting the memory cell 10a and the memory cell 10b to circuit elements, wirings, electrodes, or terminals such as switches, transistors, capacitors, inductors, resistors, and diodes.
  • the conductive layer 145 can be electrically connected to a sense amplifier (not shown) provided under the memory device shown in FIG. 16B
  • the conductive layer 245 can be electrically connected to a similar memory device (not shown) provided on the memory device shown in FIG. 16B.
  • the conductive layer 145 and the conductive layer 245 function as part of the wiring 23 described in the previous embodiment. In this way, by providing a memory device or the like above or below the memory device shown in FIG. 16B, the memory capacity per unit area can be increased.
  • the memory cell 10a and the memory cell 10b are configured to be linearly symmetrical with respect to the perpendicular bisector C1-C2 of the dashed-dotted line B1-B2 shown in FIG. 16A.
  • the memory cell 10a and the memory cell 10b are also configured to be linearly symmetrical with respect to the perpendicular bisector C3-C4 of the dashed-dotted line B1-B2 shown in FIG. 16B.
  • the transistors 200a and 200b are also arranged symmetrically with the conductive layer 145 and the conductive layer 245 sandwiched therebetween.
  • the conductive layer 240 functions as the other of the source electrode and drain electrode of the transistor 200a and the other of the source electrode and drain electrode of the transistor 200b.
  • the transistors 200a and 200b share the conductive layer 145 and the conductive layer 245 that function as plugs. In this way, by configuring the connection between the two transistors and the plug as described above, a memory device that can be miniaturized or highly integrated can be provided.
  • transistors 100a and 100b are also arranged symmetrically across conductive layer 145 and conductive layer 245.
  • the conductive layer 120 may be provided in each of the memory cells 10a and 10b, or may be provided in common to the memory cells 10a and 10b. However, as shown in FIG. 16B, the conductive layer 120 is provided apart from the conductive layer 145 to prevent the conductive layer 120 and the conductive layer 145 from shorting out.
  • FIG. 17 shows an example in which the four memory cells shown in FIG. 16A are stacked in n layers (n is an integer of 3 or more) in the Z direction.
  • FIG. 17 is a cross-sectional view between dashed lines B1-B2 shown in FIG. 16A.
  • the memory device shown in FIG. 17 has n memory layers 60. Specifically, memory layer 60[2] is provided on memory layer 60[1], and (n-2) memory layers are further provided on memory layer 60[2], with memory layer 60[n] provided on the topmost layer.
  • the number of memory cells in one memory layer 60 is not particularly limited, and two or more memory cells can be included.
  • the memory cells in n memory layers 60 are electrically connected to a sense amplifier (not shown) provided below n memory layers 60 by conductive layers 145, 245, 247, 248, etc.
  • FIG. 17 shows an example in which the conductive layer 145 is in contact with the bottom surface of the conductive layer 240, and the conductive layer 245 is in contact with the top surface of the semiconductor layer 230.
  • various modes are possible for the connection points between the plugs such as the conductive layer 145 and the conductive layer 245 and each memory cell, and are not limited to the configuration shown in FIG. 17.
  • the cells can be integrated and arranged without increasing the area occupied by the memory cell array.
  • a 3D memory cell array can be constructed.
  • Figure 18 shows an example of the cross-sectional configuration of a memory device in which a layer having memory cells is stacked on a layer in which a driver circuit including a sense amplifier is provided.
  • memory cell 10 (transistor 100 and transistor 200) is provided above transistor 300.
  • Transistor 300 is one of the transistors contained in the sense amplifier.
  • the bit line can be shortened by configuring the sense amplifier so that it overlaps with the memory cell 10. This reduces the bit line capacitance and the storage capacitance of the memory cell.
  • the memory device shown in FIG. 18 can correspond to the semiconductor device 900 described in embodiment 3. Specifically, the transistor 300 corresponds to the transistor included in the sense amplifier 927 in the semiconductor device 900. Also, the memory cell 10 corresponds to the memory cell 950.
  • the transistor 300 is provided on a substrate 311 and has a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulating layer, a semiconductor region 313 that is a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b that function as a source region or a drain region.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • the semiconductor region 313 (part of the substrate 311) in which the channel is formed has a convex shape.
  • a conductive layer 316 is provided so as to cover the side and top surface of the semiconductor region 313 via an insulating layer 315.
  • the conductive layer 316 may be made of a material that adjusts the work function.
  • Such a transistor 300 is also called a FIN type transistor because it uses the convex portion of the semiconductor substrate.
  • an insulating layer that contacts the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided.
  • a semiconductor film having a convex shape may be formed by processing an SOI substrate.
  • transistor 300 shown in FIG. 18 is just an example, and the structure is not limited thereto, and an appropriate transistor can be used depending on the circuit configuration or driving method.
  • a wiring layer having an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers may be provided depending on the design.
  • the conductive layer functioning as a plug or wiring may be given the same reference symbol as a group of multiple structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.
  • an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order on the transistor 300 as an interlayer film.
  • a conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326.
  • the conductive layer 328 and the conductive layer 330 function as plugs or wiring.
  • the insulating layer that functions as an interlayer film may also function as a planarizing film that covers the uneven shape below it.
  • the upper surface of the insulating layer 322 may be planarized by a planarization process using, for example, a CMP method to improve flatness.
  • a wiring layer may be provided on the insulating layer 326 and the conductive layer 330.
  • insulating layer 350, insulating layer 352, and insulating layer 354 are stacked in this order.
  • conductive layer 356 is formed on insulating layer 350, insulating layer 352, and insulating layer 354. Conductive layer 356 functions as a plug or wiring.
  • the insulating layer 352 and insulating layer 354, which function as interlayer films, can be the insulating layers that can be used in the semiconductor device or memory device described above.
  • Conductive layers that function as plugs or wiring can be made of conductive materials that can be used for conductive layer 140 and conductive layer 240. It is preferable to use a high-melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. Alternatively, it is preferable to form the conductive layer from a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.
  • the conductive layer 240 of the transistor 200 is electrically connected to the low-resistance region 314b that functions as a source region or drain region of the transistor 300 through the conductive layer 643, the conductive layer 642, the conductive layer 644, the conductive layer 645, the conductive layer 646, the conductive layer 356, the conductive layer 330, and the conductive layer 328.
  • the conductive layer 643 is embedded in the insulating layer 280.
  • the conductive layer 644 is embedded in the insulating layer 180 and the insulating layer 150.
  • the conductive layer 646 is embedded in the insulating layer 110.
  • the conductive layer 642 is provided between the conductive layer 644 and the insulating layer 150 and between the conductive layer 643 and the insulating layer 280.
  • the conductive layer 645 is provided between the conductive layer 646 and the insulating layer 110 and between the conductive layer 644 and the insulating layer 180.
  • the conductive layer 642 can be manufactured using the same material and in the same process as the conductive layer 220.
  • the conductive layer 645 can be manufactured using the same material and in the same process as the conductive layer 120.
  • the insulating layer 110 electrically insulates the transistor 300 from the conductive layer 120.
  • the semiconductor device 900 can function as a memory device.
  • FIG. 19 shows a block diagram illustrating a configuration example of a semiconductor device 900.
  • the semiconductor device 900 shown in FIG. 19 has a driver circuit 910 and a memory array 920.
  • the memory array 920 has one or more memory cells 950.
  • FIG. 19 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.
  • the memory device described in embodiment 2 (e.g., memory cell 10) can be applied to memory cell 950.
  • the drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915.
  • the peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.
  • each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or signals may be added.
  • Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 912.
  • the control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.
  • the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900.
  • the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.
  • the voltage generation circuit 928 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.
  • the peripheral circuit 911 is a circuit for writing and reading data to the memory cells 950.
  • the peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.
  • the row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR.
  • the row decoder 941 is a circuit for specifying the row to be accessed
  • the column decoder 942 is a circuit for specifying the column to be accessed.
  • the row driver 923 has the function of selecting the row specified by the row decoder 941.
  • the column driver 924 has the function of writing data to the memory cell 950, the function of reading data from the memory cell 950, and the function of retaining the read data.
  • the input circuit 925 has a function of holding a signal WDA.
  • the data held by the input circuit 925 is output to the column driver 924.
  • the output data of the input circuit 925 is data (Din) to be written to the memory cell 950.
  • the data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926.
  • the output circuit 926 has a function of holding Dout.
  • the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900.
  • the data output from the output circuit 926 is the signal RDA.
  • the PSW 931 has a function of controlling the supply of V DD to the peripheral circuit 915.
  • the PSW 932 has a function of controlling the supply of V HM to the row driver 923.
  • the high power supply potential of the semiconductor device 900 is V DD
  • the low power supply potential is GND (ground potential).
  • V HM is a high power supply potential used to set the word line to a high level, and is higher than V DD .
  • the on/off state of the PSW 931 is controlled by a signal PON1, and the on/off state of the PSW 932 is controlled by a signal PON2.
  • the number of power supply domains to which V DD is supplied in the peripheral circuit 915 is one, but it may be more than one. In this case, a power switch may be provided for each power supply domain.
  • the driving circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Also, as shown in FIG. 20A, the driving circuit 910 and memory array 920 may be provided overlapping each other. By providing the driving circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Also, as shown in FIG. 20B, the memory array 920 may be provided in multiple layers on the driving circuit 910.
  • Figure 21 shows a block diagram of the arithmetic unit 960.
  • the arithmetic unit 960 shown in Figure 21 can be applied to, for example, a CPU.
  • the arithmetic unit 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a large number (several tens to several hundreds) of processor cores capable of parallel processing more than a CPU.
  • processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a large number (several tens to several hundreds) of processor cores capable of parallel processing more than a CPU.
  • the arithmetic device 960 shown in FIG. 21 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990.
  • the substrate 990 is a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface.
  • the cache 999 and the cache interface 989 may be provided on separate chips.
  • the cache 999 is connected to a main memory provided on a separate chip via a cache interface 989.
  • the cache interface 989 has a function of supplying a portion of the data held in the main memory to the cache 999.
  • the cache interface 989 also has a function of outputting a portion of the data held in the cache 999 to the ALU 991 or register 996, etc. via the bus interface 998.
  • a memory array 920 can be provided by stacking it on the arithmetic unit 960.
  • the memory array 920 can be used as a cache.
  • the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999.
  • a drive circuit 910 is included as part of the cache interface 989.
  • the arithmetic device 960 shown in FIG. 21 is merely an example of a simplified configuration, and the actual arithmetic device 960 has a wide variety of configurations depending on the application.
  • the more cores there are, the more preferable it is, but for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more.
  • the number of bits that the arithmetic device 960 can handle in the internal arithmetic circuit and data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.
  • Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993, decoded, and then input to the ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995.
  • the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates a signal for controlling the operation of the ALU 991. In addition, the interrupt controller 994 determines and processes interrupt requests from external input/output devices or peripheral circuits, etc., based on their priority or mask state, etc., while the arithmetic device 960 is executing a program. The register controller 997 generates an address for the register 996, and reads and writes to the register 996 depending on the state of the arithmetic device 960.
  • the timing controller 995 also generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997.
  • the timing controller 995 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.
  • the register controller 997 selects the holding operation in the register 996 according to instructions from the ALU 991. That is, it selects whether the memory cells in the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply potential is supplied to the memory cells in the register 996. If holding data in capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply potential to the memory cells in the register 996 can be stopped.
  • Figs. 22A and 22B show perspective views of a semiconductor device 970A.
  • the semiconductor device 970A has a layer 930 in which a memory array is provided on the arithmetic device 960.
  • the layer 930 has memory arrays 920L1, 920L2, and 920L3.
  • the arithmetic device 960 and each memory array have overlapping areas.
  • Fig. 22B shows the arithmetic device 960 and layer 930 separated.
  • connection distance between them can be shortened. This allows the communication speed between them to be increased. In addition, the short connection distance allows for reduced power consumption.
  • a method for stacking the layer 930 having a memory array and the arithmetic device 960 As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method of stacking the layer 930 having a memory array directly on the arithmetic device 960 (also called monolithic stacking) may be used, or a method of forming the arithmetic device 960 and the layer 930 on different substrates, bonding the two substrates, and electrically connecting them using a through via or conductive film bonding technology (Cu-Cu bonding, etc.) may be used.
  • the former method does not require consideration of misalignment during bonding, so not only can the chip size be reduced, but also the manufacturing costs can be reduced.
  • the arithmetic device 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache.
  • the memory array 920L1 can be used as an L1 cache (also called a level 1 cache)
  • the memory array 920L2 can be used as an L2 cache (also called a level 2 cache)
  • the memory array 920L3 can be used as an L3 cache (also called a level 3 cache).
  • the memory array 920L3 has the largest capacity and is accessed the least frequently.
  • the memory array 920L1 has the smallest capacity and is accessed the most frequently.
  • each memory array provided in the layer 930 can be used as a lower-level cache or a main memory.
  • the main memory has a larger capacity than the cache and is accessed less frequently.
  • a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided.
  • the driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1.
  • the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2
  • the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.
  • the drive circuit 910L1 may function as part of the cache interface 989, or the drive circuit 910L1 may be configured to be connected to the cache interface 989.
  • the drive circuit 910L2 and the drive circuit 910L3 may also function as part of the cache interface 989, or may be configured to be connected to it.
  • the control circuit 912 can cause some of the multiple memory cells 950 in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.
  • the semiconductor device 900 can cause some of the multiple memory cells 950 to function as a cache, and the other part to function as a main memory. In other words, the semiconductor device 900 can function both as a cache and as a main memory.
  • the semiconductor device 900 according to one aspect of the present invention can function as, for example, a universal memory.
  • a layer 930 having one memory array 920 may be provided on top of the computing device 960.
  • Figure 23A shows a perspective view of the semiconductor device 970B.
  • one memory array 920 can be divided into multiple areas, each of which can be used for different functions.
  • Figure 23A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.
  • the capacity of each of areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of area L1. With such a configuration, it is possible to improve the efficiency of calculation processing and increase the processing speed.
  • Figure 23B shows a perspective view of semiconductor device 970C.
  • the semiconductor device 970C has a layer 930L1 having a memory array 920L1 stacked on top of a layer 930L2 having a memory array 920L2, and a layer 930L3 having a memory array 920L3 stacked on top of that.
  • the memory array 920L1 which is physically closest to the computing device 960, can be used as a higher-level cache, and the memory array 920L3, which is the furthest, can be used as a lower-level cache or main memory. With this configuration, the capacity of each memory array can be increased, thereby further improving processing power.
  • Figure 24A shows various storage devices used in semiconductor devices by hierarchy. The higher the storage device, the faster the operating speed is required, and the lower the storage device, the larger the storage capacity and the higher the recording density are required.
  • a processor such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, and storage. Note that, although an example having up to an L3 cache is shown here, a lower cache may also be included.
  • Registers also have the function of storing, for example, setting information for the processor.
  • a cache has the function of duplicating and storing a portion of the data stored in the main memory. By duplicating frequently used data and storing it in the cache, the speed of accessing the data can be increased.
  • the storage capacity required for a cache is less than that of the main memory, but it is required to operate at a faster speed than the main memory.
  • data that is rewritten in the cache is duplicated and supplied to the main memory.
  • the main memory has the function of storing programs and data read from storage.
  • Storage has the function of holding data that requires long-term storage, as well as various programs used by processing units. Therefore, storage requires a larger memory capacity and higher recording density than operating speed. For example, high-capacity, non-volatile storage devices such as 3D NAND can be used.
  • a storage device (OS memory) using an oxide semiconductor according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. Therefore, as shown in FIG. 24A, the storage device according to one embodiment of the present invention can be suitably used in both the hierarchy where the cache is located and the hierarchy where the main memory is located. In addition, the storage device according to one embodiment of the present invention can also be applied to the hierarchy where the storage is located.
  • Figure 24B also shows an example in which SRAM is used as part of the cache and an OS memory according to one aspect of the present invention is used as the other part.
  • the lowest level cache can be called an LLC (Last Level cache).
  • LLC Low Level cache
  • the OS memory of one embodiment of the present invention has a fast operating speed and is capable of retaining data for a long period of time, making it suitable for use as an LLC. Note that the OS memory of one embodiment of the present invention can also be applied to an FLC (Final Level cache).
  • a configuration can be used in which SRAM is used for the higher-level cache (L1 cache, L2 cache, etc.), and the OS memory of one aspect of the present invention is used for the LLC. Also, as shown in FIG. 24B, not only the OS memory but also DRAM can be applied to the main memory.
  • the semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframe computers, space equipment, data centers (also referred to as Data Centers: DCs), and various electronic devices.
  • DCs Data Centers
  • Examples of electronic devices include television devices, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, and other electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the electronic device of this embodiment may have a sensor (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • FIG. 25A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 700 is mounted.
  • the electronic component 700 shown in FIG. 25A has a semiconductor device 710 in a mold 711. In FIG. 25A, some parts are omitted in order to show the inside of the electronic component 700.
  • the electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714.
  • the electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
  • the semiconductor device 710 also has a drive circuit layer 715 and a memory layer 716.
  • the memory layer 716 is configured by stacking a plurality of memory cell arrays.
  • the stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, each layer can be connected without using a through electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu bonding.
  • TSV Through Silicon Via
  • Cu-Cu bonding a through electrode technology
  • the drive circuit layer 715 and the memory layer 716 as a monolithic stack, for example, a so-called on-chip memory configuration in which the memory is formed directly on the processor can be configured. By configuring the on-chip memory, it is possible to increase the operation speed of the interface part between the processor and the memory.
  • the memory as an on-chip memory, it is possible to reduce the size of the connection wiring, for example, compared to technologies that use through electrodes such as TSVs, and therefore to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).
  • the memory cell arrays in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked.
  • OS transistors By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency.
  • the bandwidth is the amount of data transferred per unit time
  • the access latency is the time from access to the start of data exchange.
  • Si transistors when Si transistors are used for the memory layer 716, it is difficult to form a monolithic stacked configuration compared to OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.
  • the semiconductor device 710 may also be referred to as a die.
  • a die refers to a chip piece obtained during the manufacturing process of a semiconductor chip, for example, by forming a circuit pattern on a disk-shaped substrate (also called a wafer) and cutting it into cubes.
  • Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also called a silicon wafer
  • a silicon die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.
  • Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module).
  • Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.
  • Electronic component 730 shows an example in which semiconductor device 710 is used as a high bandwidth memory (HBM).
  • Semiconductor device 735 can be used in integrated circuits such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).
  • the package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.
  • the interposer 731 may be, for example, a silicon interposer or a resin interposer.
  • the interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732.
  • the interposer may be called a "rewiring substrate” or "intermediate substrate.”
  • a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode.
  • a TSV may be used as the through electrode.
  • HBM requires many wiring connections to achieve a wide memory bandwidth. For this reason, the interposer that implements the HBM requires fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that implements the HBM.
  • silicon interposers In addition, in SiP and MCM using silicon interposers, deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. In addition, since the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.
  • a composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacking memory cell array.
  • a heat sink may be provided overlapping the electronic component 730.
  • electrodes 733 may be provided on the bottom of the package substrate 732.
  • FIG. 25B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved.
  • the electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.
  • the electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA.
  • mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).
  • Fig. 26A shows a perspective view of a large scale computer 5600.
  • the large scale computer 5600 shown in Fig. 26A has a rack 5610 housing a plurality of rack-mounted computers 5620.
  • the large scale computer 5600 may also be called a supercomputer.
  • the computer 5620 can have the configuration shown in the perspective view of FIG. 26B, for example.
  • the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals.
  • a PC card 5621 is inserted into the slot 5631.
  • the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.
  • the PC card 5621 shown in FIG. 26C is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like.
  • the PC card 5621 has a board 5622.
  • the board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • FIG. 26C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for those semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be referred to.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • An example of the standard for the connection terminal 5629 is PCIe.
  • connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621 and inputting signals. They can also be, for example, interfaces for outputting signals calculated by the PC card 5621.
  • Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface).
  • Examples of the standards for each include HDMI (registered trademark).
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
  • the semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected to the terminals by, for example, reflow soldering to wiring provided on the board 5622.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • the electronic component 730 can be used for the semiconductor device 5627.
  • the semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • An example of the semiconductor device 5628 is a memory device.
  • the electronic component 700 can be used for the semiconductor device 5628.
  • the mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment.
  • the semiconductor device of one embodiment of the present invention includes an OS transistor.
  • the OS transistor has small changes in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and can be suitably used in an environment where radiation may be incident.
  • the OS transistor can be suitably used when used in outer space.
  • the OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe.
  • Examples of radiation include X-rays and neutron rays.
  • outer space refers to an altitude of 100 km or higher, for example, and the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.
  • Figure 26D shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Figure 26D also shows a planet 6804 in space.
  • the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit.
  • BMS battery management system
  • the use of OS transistors in the battery management system or battery control circuit described above is preferable because it consumes low power and has high reliability even in outer space.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, meson rays, etc.
  • the solar panel 6802 When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or where the amount of sunlight irradiating the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is advisable to provide the satellite 6800 with a secondary battery 6805. Note that the solar panel may be called a solar cell module.
  • the artificial satellite 6800 can generate a signal.
  • the signal is transmitted via the antenna 6803, and can be received, for example, by a receiver installed on the ground or by another artificial satellite.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device.
  • a semiconductor device including an OS transistor which is one embodiment of the present invention, is preferably used for the control device 6807.
  • the OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. In other words, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can also be configured to have a sensor.
  • the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground.
  • the artificial satellite 6800 can have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, and a space probe.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.
  • the semiconductor device can be suitably used in a storage system applied to a data center, for example.
  • the data center is required to perform long-term data management, such as ensuring data immutability.
  • long-term data management such as ensuring data immutability.
  • a semiconductor device By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores the data. This makes it possible to miniaturize the storage system, miniaturize the power source for storing data, and reduce the scale of cooling equipment. This makes it possible to save space in the data center.
  • the semiconductor device of one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.
  • Figure 26E shows a storage system applicable to a data center.
  • the storage system 7010 shown in Figure 26E has multiple servers 7001sb as hosts 7001 (illustrated as Host Computer). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage).
  • the host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).
  • SAN Storage Area Network
  • the host 7001 corresponds to a computer that accesses data stored in the storage 7003.
  • the hosts 7001 may be connected to each other via a network.
  • Storage 7003 uses flash memory to reduce data access speed, i.e. the time required to store and output data, but this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage.
  • cache memory is usually provided within the storage to reduce the time required to store and output data.
  • the above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.
  • OS transistors as transistors for storing data in the cache memory, which hold a potential corresponding to the data
  • the frequency of refreshing can be reduced and power consumption can be reduced.
  • miniaturization is possible.

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