WO2024240258A1 - 显示模组、显示装置及显示模组的控制方法 - Google Patents

显示模组、显示装置及显示模组的控制方法 Download PDF

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Publication number
WO2024240258A1
WO2024240258A1 PCT/CN2024/095280 CN2024095280W WO2024240258A1 WO 2024240258 A1 WO2024240258 A1 WO 2024240258A1 CN 2024095280 W CN2024095280 W CN 2024095280W WO 2024240258 A1 WO2024240258 A1 WO 2024240258A1
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WO
WIPO (PCT)
Prior art keywords
sub
pixels
row
data signal
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/095280
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English (en)
French (fr)
Inventor
包征
向炼
王明强
白久园
方远�
陈功
贺雪英
杨皓天
王畅
张家祥
杨鹏
张燚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US18/881,271 priority Critical patent/US20250391353A1/en
Publication of WO2024240258A1 publication Critical patent/WO2024240258A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present application relates to but is not limited to the field of display panel technology, and in particular to a display module, a display device, and a control method for the display module.
  • the data signal output unit in the DIC (Driver IC) does not work, and when it displays a line of white, the data signal output unit in the DIC works normally.
  • the data signal output unit switches from off to on. Due to the limitation of the voltage output capacity of the data signal output unit, it is easy to cause the data signal voltage output by the data signal output unit to be abnormal.
  • the data signal with abnormal voltage is written to the sub-pixel, it is easy to cause display abnormality and affect the display effect.
  • an embodiment of the present application provides a display module, including a driving module and a display panel, wherein the driving module includes a data signal output unit, and the display panel includes N rows of sub-pixels, and a scanning phase of each row of sub-pixels includes a data writing period and a reserved period immediately after the data writing period;
  • the data signal output unit is configured to be in an off state during a data writing period of the nth row of sub-pixels, and to be switched from an off state to an on state during a reserved period of the nth row of sub-pixels, so as to provide a stable first data signal to the n+1th row of sub-pixels during a data writing period of the n+1th row of sub-pixels, 0 ⁇ n ⁇ N.
  • the display module controls the data signal output unit to be in an off state during the data writing period of the n-th row of sub-pixels, and controls the data signal output unit to switch from the off state to the on state during the reserved period of the n-th row of sub-pixels, so as to advance the working time of the data signal output unit and reserve sufficient time for the data signal output unit to output a stable first data signal, thereby ensuring that the (n+1)-th row of sub-pixels writes a stable first data signal during the entire data writing period, thereby avoiding display abnormalities and improving display effects.
  • the reserved period includes a light emitting period immediately after the data writing period and an idle period immediately after the light emitting period;
  • the data signal output unit is also configured to be in an off state during the light-emitting period of the nth row of sub-pixels, and to switch from the off state to the on state during the idle period of the nth row of sub-pixels, so as to provide the stable first data signal to the n+1th row of sub-pixels during the data writing period of the n+1th row of sub-pixels.
  • the scanning phase further includes a preparation period immediately before the data writing period
  • the data signal output unit is further configured to switch from an off state to an on state during a reserved period of the nth row of sub-pixels, so as to output a stable first data signal during a preparation period of the n+1th row of sub-pixels, and The data writing period of the n+1th row of sub-pixels provides the stable first data signal to the n+1th row of sub-pixels.
  • the driving module further includes an enable signal unit
  • the enable signal unit is configured to provide a first potential enable signal to the data signal output unit during a data writing period of the sub-pixels in the nth row; and provide a second potential enable signal to the data signal output unit during a reserved period of the sub-pixels in the nth row;
  • the data signal output unit is also configured to be in an off state based on the control of the first potential enable signal during a data writing period of the nth row of sub-pixels; and to be converted from an off state to an on state based on the control of the second potential enable signal during a reserved period of the nth row of sub-pixels, so as to provide a stable first data signal to the n+1th row of sub-pixels during a data writing period of the n+1th row of sub-pixels.
  • the moment when the data signal output unit switches from the off state to the on state within the reserved period of the nth row of sub-pixels is between the last one-fifth period and the last one-tenth period of the reserved period.
  • the first data signal is a data signal corresponding to the maximum display brightness of the display panel.
  • the display module further includes a voltage module
  • the voltage module is configured to provide a second data signal to the sub-pixels in the n-th row during a data writing period of the sub-pixels in the n-th row.
  • the second data signal is a data signal corresponding to the minimum display brightness of the display panel.
  • the display module further includes a selection module
  • the selection module is configured to be in an off state during a reserved period of the nth row of sub-pixels and in an on state during a data writing period of the n+1th row of sub-pixels, so that the data signal output unit provides the stable first data signal to the n+1th row of sub-pixels.
  • the driving module further includes a selection signal output unit
  • the selection signal output unit is configured to provide a first potential selection signal to the selection module during a reserved period of the sub-pixels in the nth row; and provide a second potential selection signal to the selection module during a data writing period of the sub-pixels in the n+1th row;
  • the selection module is also configured to be in an off state based on the control of the first potential selection signal during a reserved period of the nth row of sub-pixels; and to be in an on state based on the control of the second potential selection signal during a data writing period of the n+1th row of sub-pixels, so that the data signal output unit provides the stable first data signal to the n+1th row of sub-pixels.
  • an embodiment of the present application provides a display device, which includes the above-mentioned display module.
  • the display device controls the data signal output unit to be in an off state during the data writing period of the n-th row of sub-pixels, and controls the data signal output unit to switch from the off state to the on state during the reserved period of the n-th row of sub-pixels, so as to advance the working time of the data signal output unit and reserve sufficient time for the data signal output unit to output a stable first data signal, thereby ensuring that the (n+1)-th row of sub-pixels writes a stable first data signal during the entire data writing period, thereby avoiding display abnormalities and improving display effects.
  • an embodiment of the present application provides a control method for a display module, wherein the display module includes a driving module and a display panel, the driving module includes a data signal output unit, the display panel includes N rows of sub-pixels, and a scanning phase of each row of sub-pixels includes a data writing period and a reserved period immediately after the data writing period;
  • the method comprises:
  • the data signal output unit is controlled to switch from an off state to an on state to provide a stable first data signal to the n+1th row of sub-pixels during the data writing period of the n+1th row of sub-pixels, 0 ⁇ n ⁇ N.
  • the control method of the display module controls the data signal output unit to be in an off state during the data writing period of the sub-pixels in the nth row, and controls the data signal output unit to switch from the off state to the on state during the reserved period of the sub-pixels in the nth row, so as to advance the working time of the data signal output unit and reserve sufficient time for the data signal output unit to output a stable first data signal, thereby ensuring that the sub-pixels in the n+1th row are written with a stable first data signal during the entire data writing period, avoiding display abnormalities and improving display effects.
  • the reserved period includes a light emitting period immediately after the data writing period and an idle period immediately after the light emitting period;
  • the step of controlling the data signal output unit to switch from an off state to an on state within the reserved period of the n-th row of sub-pixels comprises:
  • controlling the data signal output unit to be in an off state
  • the data signal output unit is controlled to switch from an off state to an on state.
  • the moment when the data signal output unit switches from the off state to the on state within the reserved period of the nth row of sub-pixels is between the last one-fifth period and the last one-tenth period of the reserved period.
  • the first data signal is a data signal corresponding to the maximum display brightness of the display panel.
  • FIG1 is a schematic diagram of a structure of a display module according to an embodiment of the present application.
  • FIG2 is a second schematic diagram of the structure of the display module provided in an embodiment of the present application.
  • FIG3 is a third schematic diagram of the structure of the display module provided in the embodiment of the present application.
  • FIG4 is a signal timing diagram of a display module in the related art
  • FIG5 is a signal timing diagram of a display module provided in an embodiment of the present application.
  • FIG. 6 is a flow chart of a method for controlling a display module provided in an embodiment of the present application.
  • the display module, the display device, and the control method of the display module provided in the embodiments of the present application are described below with reference to FIGS. 1 to 6 .
  • FIG. 1 is a schematic diagram of the structure of a display module provided in an embodiment of the present application.
  • the display module provided in the embodiment of the present application includes a driving module 1 and a display panel 2.
  • the display panel 2 may be an AMOLED (Active-Matrix Organic Light Emitting Diode) display panel.
  • the display panel 2 includes a plurality of sub-pixels 20, and the plurality of sub-pixels 20 may be distributed in N rows and M columns, where N>1 and M>0.
  • the plurality of sub-pixels 20 may include a plurality of color sub-pixels, such as a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G.
  • each sub-pixel 20 includes a pixel circuit, and the pixel circuit includes a light-emitting device.
  • each row of sub-pixels is scanned row by row.
  • the scanning phase of each row of sub-pixels includes a data writing period and a reserved period immediately after the data writing period.
  • the data writing period of a row of sub-pixels refers to the time period for writing data signals to the pixel circuits in the row of sub-pixels.
  • the reserved period of a row of sub-pixels refers to the time period reserved for the pixel circuits in the row of sub-pixels to drive the light-emitting devices to emit light based on the written data signals.
  • the driving module 1 may be a driving chip DIC.
  • the driving module 1 may be bound to the display panel 2 through COP (Chip On Panel) technology to reduce the border of the display module.
  • COP Chip On Panel
  • the driving module 1 includes a data signal output unit 11, which is configured to be in an off state during the data writing period of the nth row of sub-pixels, and is switched from the off state to the on state during the reserved period of the nth row of sub-pixels to provide a stable first data signal to the n+1th row of sub-pixels during the data writing period of the n+1th row of sub-pixels, 0 ⁇ n ⁇ N.
  • the data signal output unit 11 is in the off state, that is, the data signal output unit 11 does not work, that is, the data signal output unit 11 does not provide data signals to the nth row of sub-pixels to save power consumption.
  • the nth row of sub-pixels correspondingly displays black.
  • the data signal output unit 11 switches from the off state to the on state, that is, the data signal output unit 11 can start working at a certain moment in the reserved period of the nth row of sub-pixels (that is, the data signal output unit 11 does not work before this moment, and works after this moment), so as to output a stable first data signal before the data writing period of the n+1th row of sub-pixels, and ensure that a stable first data signal is provided to the n+1th row of sub-pixels during the entire data writing period of the n+1th row of sub-pixels.
  • the n+1th row of sub-pixels corresponds to displaying white
  • the first data signal is a data signal corresponding to the maximum display brightness (displaying a white picture) of the display panel 2.
  • a stable first data signal means that the voltage of the first data signal is stable.
  • the time when the data signal output unit 11 starts working is advanced, that is, the time when the data signal output unit 11 starts working is advanced from the scanning start moment of the n+1th row of sub-pixels to the reserved period of the nth row of sub-pixels, so as to reserve sufficient time for the data signal output by the data signal output unit 11 to recover from an abnormal state to a normal state, thereby ensuring that the n+1th row of sub-pixels writes a stable first data signal during the entire data writing period to avoid display abnormalities.
  • the reserved period of each row of sub-pixels includes a light-emitting period immediately after the data writing period and an idle period immediately after the light-emitting period.
  • the light-emitting period of a row of sub-pixels can be a time period in which the pixel circuit in the row of sub-pixels drives the light-emitting unit to emit light according to the written data signal.
  • the idle period of a row of sub-pixels can be a redundant time period between the row of sub-pixels and the next row of sub-pixels.
  • the data signal output unit 11 is also configured to be in an off state during the light-emitting period of the nth row of sub-pixels, and to switch from the off state to the on state during the idle period of the nth row of sub-pixels, so as to provide a stable first data signal to the n+1th row of sub-pixels during the data writing period of the n+1th row of sub-pixels.
  • the data signal output unit 11 is still in the off state, that is, the data signal output unit 11 is still not working, so as to avoid interfering with the operation of the pixel circuit.
  • the data signal output unit 11 is switched from the off state to the on state, that is, the data signal output unit 11 can start working at a certain moment during the idle period of the n-th row of sub-pixels, so as to output a stable first data signal before the data writing period of the n+1-th row of sub-pixels, and ensure that a stable first data signal is provided to the n+1-th row of sub-pixels during the entire data writing period of the n+1-th row of sub-pixels.
  • the scanning phase of each row of sub-pixels further includes a preparation period immediately before the data writing period.
  • the preparation period of a row of sub-pixels may be a preparation period of other signals required to write data signals into the row of sub-pixels.
  • the data signal output unit 11 is also configured to switch from an off state to an on state within a reserved period of the nth row of sub-pixels, so as to output a stable first data signal during a preparation period of the n+1th row of sub-pixels, and provide a stable first data signal to the n+1th row of sub-pixels during a data writing period of the n+1th row of sub-pixels.
  • the data signal output unit 11 is switched from the off state to the on state, so that a stable first data signal can be output during the preparation period of the n+1th row of sub-pixels, thereby effectively ensuring that the data signal output unit 11 provides a stable first data signal to the n+1th row of sub-pixels during the data writing period of the n+1th row of sub-pixels.
  • the driving module 1 may further include an enable signal unit 12 , and the enable signal unit 12 is connected to the data signal output unit 11 .
  • the enable signal unit 12 is configured to provide a first potential enable signal to the data signal output unit 11 during the data writing period of the sub-pixels in the nth row; and provide a second potential enable signal to the data signal output unit 11 during the reserved period of the sub-pixels in the nth row.
  • the data signal output unit 11 is also configured to be in an off state based on the control of the first potential enable signal during the data writing period of the sub-pixels in the nth row; and to be switched from an off state to an on state based on the control of the second potential enable signal during the reserved period of the sub-pixels in the nth row, so as to provide a stable first data signal to the sub-pixels in the n+1th row during the data writing period of the sub-pixels in the n+1th row.
  • the enable signal output by the enable signal unit 12 can control the on or off of the data signal output unit 11.
  • the potential of the first potential enable signal is opposite to that of the second potential enable signal. If the data signal output unit 11 is effective at a high level, that is, the data signal output unit 11 is turned on by a high level input, the first potential enable signal provided by the enable signal unit 12 to the data signal output unit 11 is a low potential, and the second potential enable signal is a high potential; if the data signal output unit 11 is effective at a low level, that is, the data signal output unit 11 is turned on by a low level input, the first potential enable signal provided by the enable signal unit 12 to the data signal output unit 11 is a high potential, and the second potential enable signal is a low potential.
  • the enable signal unit 12 inputs the first potential enable signal to the data signal output unit 11 to control the data signal output unit 11 to be in the off state.
  • the enable signal provided by the enable signal unit 12 to the data signal output unit 11 is converted from the first potential enable signal to the second potential enable signal, so that the data signal output unit 11 is switched from the off state to the on state during the reserved period of the n-th row of sub-pixels, ensuring that the data signal output unit 11 provides a stable first data signal to the n+1-th row of sub-pixels during the data writing period of the n+1-th row of sub-pixels.
  • the moment when the data signal output unit 11 switches from the off state to the on state during the reserved period of the nth row of sub-pixels is between the last one-fifth period and the last one-tenth period of the reserved period.
  • the data signal output unit 11 switches from the off state to the on state during this period, and can output a stable first data signal during the preparation period of the n+1th row of sub-pixels, effectively ensuring that the data signal output unit 11 provides a stable first data signal to the n+1th row of sub-pixels during the data writing period of the n+1th row of sub-pixels.
  • the display module further includes a voltage module 3 , and the voltage module 3 is configured to provide a second data signal to the sub-pixels in the n-th row during a data writing period of the sub-pixels in the n-th row.
  • the data signal output unit 11 does not work, and the voltage module 3 provides the second data signal to the nth row of sub-pixels.
  • the nth row of sub-pixels corresponds to displaying black, that is, the second data signal is a data signal corresponding to the minimum display brightness (displaying a black screen) of the display panel 2.
  • the display module further includes a selection module 4, which is connected between the data signal output unit 11 and the pixel circuit, and is also connected between the voltage module 3 and the pixel circuit.
  • the selection module 4 may be a data selector (multiplexer) Mux.
  • the selection module 4 is set to be in the off state during the reserved period of the nth row of sub-pixels and in the on state during the data writing period of the n+1th row of sub-pixels, so that the data signal output unit 11 provides a stable first data signal to the n+1th row of sub-pixels.
  • the selection module 4 is in an off state during the reserved period of each row of sub-pixels, and is in an on state during the data writing period of each row of sub-pixels. During the data writing period of the nth row of sub-pixels, the selection module 4 is in an on state, and the second data signal output by the voltage module 3 is provided to the nth row of sub-pixels, that is, the second data signal is written into the pixel circuit of the nth row of sub-pixels.
  • the selection module 4 is in an off state, and stops providing the second data signal output by the voltage module 3 to the nth row of sub-pixels, that is, the pixel circuit of the nth row of sub-pixels no longer writes the second data signal.
  • the data signal output unit 11 is switched from an off state to an on state, that is, the data signal output unit 11 starts to work, the voltage module 3 stops outputting the second data signal, and the data signal output unit 11 can output the first data signal with abnormal voltage, and the selection module 4 is in an off state, so that the first data signal with abnormal voltage will not be provided to the nth row of sub-pixels.
  • the selection module 4 is in the off state during the preparation period of each row of sub-pixels. During the preparation period of the n+1th row of sub-pixels, the selection module 4 is in the off state, and stops providing the data signal output by the data signal output unit 11 to the n+1th row of sub-pixels, so that the data signal output unit 11 can still output the first data signal with abnormal voltage during the preparation period of the n+1th row of sub-pixels, but before the data writing period of the n+1th row of sub-pixels, the data signal output unit 11 needs to output a stable first data signal.
  • the selection module 4 is in the on state, and provides the stable first data signal output by the data signal output unit 11 to the n+1th row of sub-pixels, that is, the stable first data signal is written into the pixel circuit of the n+1th row of sub-pixels.
  • the selection module 4 includes a plurality of selection units 41, and the M columns of sub-pixels can be divided into a plurality of groups of sub-pixels, and each group of sub-pixels includes a plurality of columns of sub-pixels, and the plurality of selection units 41 are connected one-to-one with the pixel circuits of the plurality of columns of sub-pixels in each group of sub-pixels.
  • the data signal output unit 11 has a plurality of output terminals, and each output terminal of the data signal output unit 11 is connected to the plurality of selection units 41 in the selection module 4, so that each output terminal of the data signal output unit 11 corresponds to a plurality of columns of sub-pixels in a group of sub-pixels.
  • the selection module 4 may adopt a Mux 1:6 scheme, that is, the selection module 4 includes six selection units 41, and each six columns of sub-pixels in the M columns of sub-pixels form a group, and each output terminal of the data signal output unit 11 corresponds to six columns of sub-pixels in a group of sub-pixels.
  • the selection module 4 may also adopt a Mux 1:9 scheme, a Mux 1:12 scheme, or other schemes, which are not specifically limited here.
  • the selection module 4 is set in this embodiment to reduce the wiring space. As shown in Figure 3, for flexible AMOLED wearable products, the setting of the selection module 4 can save the wiring area (Pad area) 40 space.
  • the driving module 1 further includes a selection signal output unit 13, which is connected to the selection module 4.
  • the selection signal output unit 13 is configured to output a selection signal to the selection module 4 during the reserved period of the sub-pixels in the nth row. 4 provides a first potential selection signal; in the data writing period of the sub-pixels in the n+1th row, provides a second potential selection signal to the selection module 4.
  • the selection module 4 is also configured to be in an off state based on the control of the first potential selection signal during the reserved period of the sub-pixels in the nth row; and in an on state based on the control of the second potential selection signal during the data writing period of the sub-pixels in the n+1th row, so that the data signal output unit provides a stable first data signal to the sub-pixels in the n+1th row.
  • the selection signal output by the selection signal output unit 13 can control the on or off of the selection module 4.
  • the potential of the first potential selection signal is opposite to that of the second potential selection signal. If the selection module 4 is effective at a high level, that is, the selection module 4 is input at a high level and is turned on, the first potential selection signal provided by the selection signal output unit 13 to the selection module 4 is a low potential, and the second potential selection signal is a high potential; if the selection module 4 is effective at a low level, that is, the selection module 4 is input at a low level and is turned on, the first potential selection signal provided by the selection signal output unit 13 to the selection module 4 is a high potential, and the second potential selection signal is a low potential.
  • the selection signal output unit 13 In the data writing period of the nth row of sub-pixels, the selection signal output unit 13 inputs the second potential selection signal to the selection module 4 to control the selection module 4 to be in the on state, so that the voltage module 3 provides the second data signal to the nth row of sub-pixels. In the reserved period of the nth row of sub-pixels, the selection signal output unit 13 inputs the first potential selection signal to the selection module 4 to control the selection module 4 to be in the off state, and stops providing the second data signal output by the voltage module 3 or the first data signal output by the data signal output unit 11 to the nth row of sub-pixels.
  • the selection signal output unit 13 In the preparation period of the n+1th row of sub-pixels, the selection signal output unit 13 inputs the first potential selection signal to the selection module 4 to control the selection module 4 to be in the off state, and stops providing the first data signal output by the data signal output unit 11 to the n+1th row of sub-pixels. In the data writing period of the n+1th row of sub-pixels, the selection signal output unit 13 inputs the second potential selection signal to the selection module 4 to control the selection module 4 to be in the on state, so that the data signal output unit 11 provides the stable first data signal to the n+1th row of sub-pixels.
  • each selection unit 41 includes a transistor T1, the control end of the transistor T1 is connected to the selection signal output unit 13, the input end of the transistor T1 is connected to the data signal output module 11 and the voltage module 3, and the output end of the transistor T1 is connected to the pixel circuit of the corresponding sub-pixel 20.
  • the selection signal output unit 13 may include a high and low potential output subunit (not shown in the figure) and a digital subunit (not shown in the figure).
  • the high and low potential output subunit is connected to the digital subunit, and the digital subunit is respectively connected to the control terminals of the transistors T1 in the plurality of selection units 41.
  • the high and low potential output subunit is used to provide a selection signal to the digital subunit.
  • the digital subunit is used to convert the selection signal into a waveform with a timing sequence to realize the conduction or shutdown of each selection unit 41 in the selection module 4 at different times.
  • A is a constant
  • VDD is the power supply voltage
  • Vdata is the data signal.
  • VDD is a constant voltage.
  • the voltage of the data signal Vdata is the largest under the black screen (the lowest display brightness), and the data signal Vdata is defined as VGMP at this time; the voltage of the data signal Vdata is the smallest under the white screen (the highest display brightness), and the data signal Vdata is defined as VGSP at this time.
  • the data signal Vdata changes between VGMP and VGSP.
  • the enable signal unit 12 provides the data signal output unit 11 with a first potential enable signal (i.e., a low potential enable signal SOPEN) to control the data signal output unit 11 to be in an off state, that is, to control the data signal output unit 11 not to output a data signal to save power consumption.
  • a first potential enable signal i.e., a low potential enable signal SOPEN
  • the voltage module 3 provides the second data signal VGMP to the sub-pixels in the nth row through the selection module 4 , so that the input signal ST at the input end of the selection module 4 (ie, the input end of the transistor T1 ) is the second data signal VGMP.
  • the data signal output unit 11 needs to work to provide a stable first data signal VGSP to the n+1th row of sub-pixels through the selection module 4.
  • the moment when the enable signal unit 12 provides the second potential enable signal (i.e., the high potential enable signal SOPEN) to the data signal output unit 11 is the same as the start moment of the row reference signal Hsync of the n+1th row of sub-pixels, that is, at the beginning moment of the scanning phase of the n+1th row of sub-pixels, the enable signal unit 12 provides the second potential enable signal (i.e., the high potential enable signal SOPEN) to the data signal output unit 11 to control the data signal output unit 11 to switch from the off state to the on state.
  • the second potential enable signal i.e., the high potential enable signal SOPEN
  • the data signal output unit 11 with normal voltage output capability can output a stable first data signal VGSP in the preparation period t1 of the n+1 row of sub-pixels, that is, the input signal ST at the input end of the selection module 4 can complete the voltage conversion (that is, conversion from the second data signal VGMP to the stable first data signal VGSP) in the preparation period t1 of the n+1 row of sub-pixels, as shown in the normal ST timing in FIG4.
  • the data signal output unit 11 with weak voltage output capability cannot output a stable first data signal VGSP in the preparation period t1 of the n+1 row of sub-pixels, that is, the input signal ST at the input end of the selection module 4 cannot complete the voltage conversion in the preparation period t1 of the n+1 row of sub-pixels, resulting in the input signal ST still being in an abnormal state (that is, the input signal ST is a first data signal with abnormal voltage) in the data writing stage t2 of the n+1 row of sub-pixels, as shown in the abnormal ST timing in FIG4.
  • the selection signal output unit 13 provides a plurality of second potential selection signals (i.e., the low potential selection signal MUX) to the selection module 4 to control the plurality of selection units 41 in the selection module 4 to be turned on in sequence, thereby providing the first data signal with abnormal voltage to the first sub-pixel (red sub-pixel R) in the sub-pixels in the n+1th row, resulting in the appearance of red lines on the display screen.
  • a plurality of second potential selection signals i.e., the low potential selection signal MUX
  • the moment when the enable signal unit 12 provides the second potential enable signal (i.e., the high potential enable signal SOPEN) to the data signal output unit 11 is advanced to the reserved period t3 of the n-th row of sub-pixels.
  • the data signal output unit 11 In the data writing period t2 of the n-th row of sub-pixels, the data signal output unit 11 is in the off state, and the selection signal output unit 13 provides a plurality of second potential selection signals (i.e., the low potential selection signal MUX) to the selection module 4 to control the plurality of selection units 41 in the selection module 4 to be turned on in sequence, and the second data signal VGMP of the voltage module 3 is written into the plurality of columns of sub-pixels in sequence.
  • the selection signal output unit 13 In the reserved period t3 of the n-th row of sub-pixels, the selection signal output unit 13 provides the first potential selection signal (i.e., the high potential selection signal MUX) to the selection module 4, controls the selection module 4 to be in the off state, and other signals start to work.
  • the enable signal unit 12 provides the second potential enable signal (i.e., the high potential enable signal SOPEN) to the data signal output unit 11 to control the data signal output unit 11 to switch from the off state to the on state.
  • the data signal output unit 11 with normal voltage output capability can output a stable first data signal VGSP in the reserved period t3 of the n-th row of sub-pixels, that is, the input signal ST at the input end of the selection module 4 can complete the voltage conversion (that is, convert from the second data signal VGMP to the stable first data signal VGSP) in the reserved period t3 of the n-th row of sub-pixels, as shown in the normal ST timing in FIG5.
  • the data signal output unit 11 with weak voltage output capability can also output a stable first data signal VGSP before the data writing period t2 of the n+1-th row of sub-pixels, that is, the input signal ST at the input end of the selection module 4 can complete the voltage conversion (that is, convert from the second data signal VGMP to the stable first data signal VGSP) before the data writing period t2 of the n+1-th row of sub-pixels, as shown in the abnormal ST timing in FIG5.
  • the selection signal output unit 13 provides a plurality of second potential selection signals (i.e., the low potential selection signal MUX) to the selection module 4 to control the plurality of selection units 41 in the selection module 4 to be turned on in sequence, and write the stable first data signal VGSP into the plurality of columns of sub-pixels in sequence, thereby avoiding writing the first data signal with abnormal voltage into the red sub-pixel R, and completely solving the problem of poor red line.
  • a plurality of second potential selection signals i.e., the low potential selection signal MUX
  • the display module provided by the embodiment of the present application controls the data signal output unit to be in an off state during the data writing period of the sub-pixels in the nth row, and controls the data signal output unit to switch from the off state to the on state during the reserved period of the sub-pixels in the nth row, so as to advance the working time of the data signal output unit, so as to reserve enough time for the data signal output unit to be turned on.
  • the output unit outputs a stable first data signal, thereby ensuring that the sub-pixels in the n+1th row write stable first data signals during the entire data writing period, avoiding display abnormalities and improving display effects.
  • an embodiment of the present application further provides a display device, comprising the above-mentioned display module.
  • the display device controls the data signal output unit to be in an off state during the data writing period of the n-th row of sub-pixels, and controls the data signal output unit to switch from the off state to the on state during the reserved period of the n-th row of sub-pixels, so as to advance the working time of the data signal output unit, so as to reserve sufficient time for the data signal output unit to output a stable first data signal, thereby ensuring that the (n+1)-th row of sub-pixels writes a stable first data signal during the entire data writing period, thereby avoiding display abnormalities and improving display effects.
  • the display device provided in the embodiment of the present application can be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • an embodiment of the present application also provides a control method for a display module, which can be applied to the above-mentioned display module.
  • Figure 6 is a flow chart of the control method for a display module provided by an embodiment of the present application.
  • the display module includes a driving module and a display panel, the driving module includes a data signal output unit, the display panel includes N rows of sub-pixels, and the scanning phase of each row of sub-pixels includes a data writing period and a reserved period immediately after the data writing period.
  • control method of the display module includes steps 610 to 620 as follows:
  • Step 610 during the data writing period of the sub-pixels in the nth row, control the data signal output unit to be in an off state.
  • Step 620 control the data signal output unit to switch from the off state to the on state during the reserved period of the nth row of sub-pixels, so as to provide a stable first data signal to the n+1th row of sub-pixels during the data writing period of the n+1th row of sub-pixels, 0 ⁇ n ⁇ N.
  • the reserved period includes a light emitting period immediately after the data writing period and an idle period immediately after the light emitting period.
  • controlling the data signal output unit to switch from an off state to an on state includes:
  • the data signal output unit is controlled to be in an off state
  • the data signal output unit is controlled to switch from the off state to the on state.
  • the moment when the data signal output unit switches from the off state to the on state within the reserved period of the nth row of sub-pixels is located between the last one-fifth period and the last one-tenth period of the reserved period.
  • the first data signal is a data signal corresponding to the maximum display brightness of the display panel.
  • the control method of the display module controls the data signal output unit to be in an off state during the data writing period of the sub-pixels in the nth row, and controls the data signal output unit to switch from the off state to the on state during the reserved period of the sub-pixels in the nth row, so as to advance the working time of the data signal output unit and reserve sufficient time for the data signal output unit to output a stable first data signal, thereby ensuring that the sub-pixels in the n+1th row are written with a stable first data signal during the entire data writing period, avoiding display abnormalities and improving display effects.
  • first, second, etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first”, “second”, etc. are generally of the same type, and the number of objects is not limited.
  • the first object can be one or more.

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Abstract

一种显示模组、显示装置及显示模组的控制方法。显示模组包括驱动模块（1）和显示面板（2），驱动模块（1）包括数据信号输出单元（11），显示面板（2）包括N行子像素，每行子像素的扫描阶段包括数据写入时段以及紧接在数据写入时段之后的预留时段；数据信号输出单元（11）设置为在第n行子像素的数据写入时段处于关断状态（610），在第n行子像素的预留时段内由关断状态切换为导通状态，以在第n+1行子像素的数据写入时段向第n+1行子像素提供稳定的第一数据信号，0＜n＜N（620）。

Description

显示模组、显示装置及显示模组的控制方法
本申请要求于2023年5月25日提交的、申请号为202310601149.4、发明名称为“显示模组、显示装置及显示模组的控制方法”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本申请涉及但不限于显示面板技术领域，尤其涉及一种显示模组、显示装置及显示模组的控制方法。
背景技术
为了节省功耗，显示模组在显示一行黑色时，DIC(Driver IC，驱动芯片)中的数据信号输出单元不工作，在显示一行白色时，DIC中的数据信号输出单元正常工作。在扫描完一行黑色所对应的子像素，并开始扫描一行白色所对应的子像素时，数据信号输出单元由关闭切换为开启，由于数据信号输出单元的电压输出能力的限制，容易导致数据信号输出单元输出的数据信号电压异常。而电压异常的数据信号写入至子像素，容易导致显示异常，影响显示效果。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本申请实施例提供了一种显示模组，包括驱动模块和显示面板，所述驱动模块包括数据信号输出单元，所述显示面板包括N行子像素，每行子像素的扫描阶段包括数据写入时段以及紧接在所述数据写入时段之后的预留时段；
所述数据信号输出单元设置为在第n行子像素的数据写入时段处于关断状态，在所述第n行子像素的预留时段内由关断状态切换为导通状态，以在第n+1行子像素的数据写入时段向所述第n+1行子像素提供稳定的第一数据信号，0＜n＜N。
本申请实施例提供的显示模组，通过控制数据信号输出单元在第n行子像素的数据写入时段处于关断状态，控制数据信号输出单元在第n行子像素的预留时段内由关断状态切换为导通状态，以将数据信号输出单元的工作时间提前，预留足够的时间供数据信号输出单元输出稳定的第一数据信号，从而保证第n+1行子像素在整个数据写入时段写入稳定的第一数据信号，避免显示异常，提高显示效果。
根据本申请的一个实施例，所述预留时段包括紧接在所述数据写入时段之后的发光时段以及紧接在所述发光时段之后的空闲时段；
所述数据信号输出单元还设置为在所述第n行子像素的发光时段处于关断状态，在所述第n行子像素的空闲时段内由关断状态切换为导通状态，以在所述第n+1行子像素的数据写入时段向所述第n+1行子像素提供所述稳定的第一数据信号。
根据本申请的一个实施例，所述扫描阶段还包括紧接在所述数据写入时段之前的准备时段；
所述数据信号输出单元还设置为在所述第n行子像素的预留时段内由关断状态切换为导通状态，以在所述第n+1行子像素的准备时段输出稳定的第一数据信号，并在所述 第n+1行子像素的数据写入时段向所述第n+1行子像素提供所述稳定的第一数据信号。
根据本申请的一个实施例，所述驱动模块还包括使能信号单元；
所述使能信号单元设置为在所述第n行子像素的数据写入时段，向所述数据信号输出单元提供第一电位使能信号；在所述第n行子像素的预留时段内，向所述数据信号输出单元提供第二电位使能信号；
所述数据信号输出单元还设置为在所述第n行子像素的数据写入时段，基于所述第一电位使能信号的控制处于关断状态；在所述第n行子像素的预留时段内，基于所述第二电位使能信号的控制由关断状态转换为导通状态，以在所述第n+1行子像素的数据写入时段向所述第n+1行子像素提供稳定的第一数据信号。
根据本申请的一个实施例，所述数据信号输出单元在所述第n行子像素的预留时段内由关断状态切换为导通状态的时刻，位于所述预留时段的后五分之一时段至后十分之一时段之间。
根据本申请的一个实施例，所述第一数据信号为所述显示面板的最大显示亮度所对应的数据信号。
根据本申请的一个实施例，所述显示模组还包括电压模块；
所述电压模块设置为在所述第n行子像素的数据写入时段，向所述第n行子像素提供第二数据信号。
根据本申请的一个实施例，所述第二数据信号为所述显示面板的最小显示亮度所对应的数据信号。
根据本申请的一个实施例，所述显示模组还包括选择模块；
所述选择模块设置为在所述第n行子像素的预留时段处于关断状态，在所述第n+1行子像素的数据写入时段处于导通状态，以使所述数据信号输出单元向所述第n+1行子像素提供所述稳定的第一数据信号。
根据本申请的一个实施例，所述驱动模块还包括选择信号输出单元；
所述选择信号输出单元设置为在所述第n行子像素的预留时段，向所述选择模块提供第一电位选择信号；在所述第n+1行子像素的数据写入时段，向所述选择模块提供第二电位选择信号；
所述选择模块还设置为在所述第n行子像素的预留时段，基于所述第一电位选择信号的控制处于关断状态；在所述第n+1行子像素的数据写入时段，基于所述第二电位选择信号的控制处于导通状态，以使所述数据信号输出单元向所述第n+1行子像素提供所述稳定的第一数据信号。
第二方面，本申请实施例提供了一种显示装置，该显示装置包括上述显示模组。
本申请实施例提供的显示装置，通过控制数据信号输出单元在第n行子像素的数据写入时段处于关断状态，控制数据信号输出单元在第n行子像素的预留时段内由关断状态切换为导通状态，以将数据信号输出单元的工作时间提前，预留足够的时间供数据信号输出单元输出稳定的第一数据信号，从而保证第n+1行子像素在整个数据写入时段写入稳定的第一数据信号，避免显示异常，提高显示效果。
第三方面，本申请实施例提供了一种显示模组的控制方法，所述显示模组包括驱动模块和显示面板，所述驱动模块包括数据信号输出单元，所述显示面板包括N行子像素，每行子像素的扫描阶段包括数据写入时段以及紧接在所述数据写入时段之后的预留时段； 所述方法包括：
在第n行子像素的数据写入时段，控制所述数据信号输出单元处于关断状态；
在所述第n行子像素的预留时段内，控制所述数据信号输出单元由关断状态切换为导通状态，以在第n+1行子像素的数据写入时段向所述第n+1行子像素提供稳定的第一数据信号，0＜n＜N。
本申请实施例提供的显示模组的控制方法，通过控制数据信号输出单元在第n行子像素的数据写入时段处于关断状态，控制数据信号输出单元在第n行子像素的预留时段内由关断状态切换为导通状态，以将数据信号输出单元的工作时间提前，预留足够的时间供数据信号输出单元输出稳定的第一数据信号，从而保证第n+1行子像素在整个数据写入时段写入稳定的第一数据信号，避免显示异常，提高显示效果。
根据本申请的一个实施例，所述预留时段包括紧接在所述数据写入时段之后的发光时段以及紧接在所述发光时段之后的空闲时段；
所述在所述第n行子像素的预留时段内，控制所述数据信号输出单元由关断状态切换为导通状态，包括：
在所述第n行子像素的发光时段，控制所述数据信号输出单元处于关断状态；
在所述第n行子像素的空闲时段内，控制所述数据信号输出单元由关断状态切换为导通状态。
根据本申请的一个实施例，所述数据信号输出单元在所述第n行子像素的预留时段内由关断状态切换为导通状态的时刻，位于所述预留时段的后五分之一时段至后十分之一时段之间。
根据本申请的一个实施例，所述第一数据信号为所述显示面板的最大显示亮度所对应的数据信号。
在阅读并理解了附图和详细描述后，可以明白其它方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1是本申请实施例提供的显示模组的结构示意图之一；
图2是本申请实施例提供的显示模组的结构示意图之二；
图3是本申请实施例提供的显示模组的结构示意图之三；
图4是相关技术中的显示模组的信号时序图；
图5是本申请实施例提供的显示模组的信号时序图；
图6是本申请实施例提供的显示模组的控制方法的流程示意图。
详述
下面详细描述本申请的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
下面参考图1-图6描述本申请实施例提供的显示模组、显示装置及显示模组的控制方法。
图1为本申请实施例提供的显示模组的一种结构示意图。
如图1所示，本申请实施例提供的显示模组包括驱动模块1和显示面板2。显示面板2可以为AMOLED(Active-Matrix Organic Light Emitting Diode，有源矩阵有机发光二极体)显示面板。显示面板2包括多个子像素20，多个子像素20可以呈N行M列分布，N＞1，M＞0。多个子像素20可以包括多种颜色子像素，如红色子像素R、蓝色子像素B和绿色子像素G。在一行子像素中，多种颜色子像素可以交替分布，如按照红色子像素R、绿色子像素G和蓝色子像素B的顺序交替分布。每个子像素20包括像素电路，像素电路包括发光器件。
显示面板2在显示画面时，对N行子像素逐行扫描。每行子像素的扫描阶段包括数据写入时段以及紧接在数据写入时段之后的预留时段。其中，一行子像素的数据写入时段是指向该行子像素中的像素电路写入数据信号的时间段。一行子像素的预留时段是指预留给该行子像素中的像素电路基于写入的数据信号驱动发光器件发光等工作的时间段。
驱动模块1可以为驱动芯片DIC，驱动模块1可以通过COP(Chip On Panel)技术绑定在显示面板2上，以减小显示模组的边框。
如图1所示，驱动模块1包括数据信号输出单元11，数据信号输出单元11设置为在第n行子像素的数据写入时段处于关断状态，在第n行子像素的预留时段内由关断状态切换为导通状态，以在第n+1行子像素的数据写入时段向第n+1行子像素提供稳定的第一数据信号，0＜n＜N。
在第n行子像素的数据写入时段，数据信号输出单元11处于关断状态，即数据信号输出单元11不工作，即数据信号输出单元11不向第n行子像素提供数据信号，以节省功耗。其中，第n行子像素对应显示黑色。
在第n行子像素的预留时段内，数据信号输出单元11由关断状态切换为导通状态，即数据信号输出单元11可以在第n行子像素的预留时段内的某一时刻开始工作(即数据信号输出单元11在该时刻之前不工作，在该时刻之后工作)，以在第n+1行子像素的数据写入时段之前输出稳定的第一数据信号，保证在第n+1行子像素的整个数据写入时段向第n+1行子像素提供稳定的第一数据信号。其中，第n+1行子像素对应显示白色，即第一数据信号为显示面板2的最大显示亮度(显示白色画面)所对应的数据信号。稳定的第一数据信号是指第一数据信号的电压稳定。
本实施例将数据信号输出单元11开始工作的时间提前，即将数据信号输出单元11开始工作的时间由第n+1行子像素的扫描开始时刻提前至第n行子像素的预留时段内，以预留足够的时间供数据信号输出单元11输出的数据信号由异常状态恢复为正常状态，从而保证第n+1行子像素在整个数据写入时段写入稳定的第一数据信号，避免显示异常。
在一些实施例中，每行子像素的预留时段包括紧接在数据写入时段之后的发光时段以及紧接在发光时段之后的空闲时段。一行子像素的发光时段可以为该行子像素中的像素电路根据写入的数据信号驱动发光单元进行发光的时间段。一行子像素的空闲时段可以为该行子像素与下一行子像素之间的冗余时间段。
数据信号输出单元11还设置为在第n行子像素的发光时段处于关断状态，在第n行子像素的空闲时段内由关断状态切换为导通状态，以在第n+1行子像素的数据写入时段向第n+1行子像素提供稳定的第一数据信号。
在第n行子像素的发光时段，数据信号输出单元11仍处于关断状态，即数据信号输出单元11仍不工作，以避免对像素电路的工作产生干扰。在第n行子像素的空闲时段内，数据信号输出单元11由关断状态切换为导通状态，即数据信号输出单元11可以在第n行子像素的空闲时段内的某一时刻开始工作，以在第n+1行子像素的数据写入时段之前输出稳定的第一数据信号，保证在第n+1行子像素的整个数据写入时段向第n+1行子像素提供稳定的第一数据信号。
在一些实施例中，每一行子像素的扫描阶段还包括紧接在数据写入时段之前的准备时段。一行子像素的准备时段可以为将数据信号写入该行子像素所需的其他信号的准备时间段。
数据信号输出单元11还设置为在第n行子像素的预留时段内由关断状态切换为导通状态，以在第n+1行子像素的准备时段输出稳定的第一数据信号，并在第n+1行子像素的数据写入时段向第n+1行子像素提供稳定的第一数据信号。
在第n行子像素的预留时段内，如在第n行子像素的空闲时段内，数据信号输出单元11由关断状态切换为导通状态，以在第n+1行子像素的准备时段即可输出稳定的第一数据信号，有效保证数据信号输出单元11在第n+1行子像素的数据写入时段向第n+1行子像素提供稳定的第一数据信号。
在一些实施例中，如图1所示，驱动模块1还可以包括使能信号单元12，使能信号单元12与数据信号输出单元11连接。
使能信号单元12设置为在第n行子像素的数据写入时段，向数据信号输出单元11提供第一电位使能信号；在第n行子像素的预留时段内，向数据信号输出单元11提供第二电位使能信号。数据信号输出单元11还设置为在第n行子像素的数据写入时段，基于第一电位使能信号的控制处于关断状态；在第n行子像素的预留时段内，基于第二电位使能信号的控制由关断状态转换为导通状态，以在第n+1行子像素的数据写入时段向第n+1行子像素提供稳定的第一数据信号。
使能信号单元12输出的使能信号可以控制数据信号输出单元11的导通或关断。第一电位使能信号与第二电位使能信号的电位相反。若数据信号输出单元11高电平有效，即数据信号输出单元11输入高电平导通，则使能信号单元12提供给数据信号输出单元11的第一电位使能信号为低电位，第二电位使能信号为高电位；若数据信号输出单元11低电平有效，即数据信号输出单元11输入低电平导通，则使能信号单元12提供给数据信号输出单元11的第一电位使能信号为高电位，第二电位使能信号为低电位。
在第n行子像素的数据写入时段，使能信号单元12将第一电位使能信号输入至数据信号输出单元11，以控制数据信号输出单元11处于关断状态。在第n行子像素的预留时段内的某一时刻，如第n行子像素的空闲时段内的某一时刻，使能信号单元12提供给数据信号输出单元11的使能信号由第一电位使能信号转换为第二电位使能信号，以使数据信号输出单元11在第n行子像素的预留时段内由关断状态切换为导通状态，保证数据信号输出单元11在第n+1行子像素的数据写入时段向第n+1行子像素提供稳定的第一数据信号。
在一些实施例中，数据信号输出单元11在第n行子像素的预留时段内由关断状态切换为导通状态的时刻，位于预留时段的后五分之一时段至后十分之一时段之间。数据信号输出单元11在该时间段内由关断状态切换为导通状态，可以在第n+1行子像素的准备时段输出稳定的第一数据信号，有效保证数据信号输出单元11在第n+1行子像素的数据写入时段向第n+1行子像素提供稳定的第一数据信号。
在一些实施例中，显示模组还包括电压模块3，电压模块3设置为在第n行子像素的数据写入时段，向第n行子像素提供第二数据信号。
为了节省功耗，在第n行子像素的数据写入时段，数据信号输出单元11不工作，由电压模块3向第n行子像素提供第二数据信号。其中，第n行子像素对应显示黑色，即第二数据信号为显示面板2的最小显示亮度(显示黑色画面)所对应的数据信号。
在一些实施例中，显示模组还包括选择模块4，选择模块4连接在数据信号输出单元11与像素电路之间，选择模块4还连接在电压模块3与像素电路之间。选择模块4可以为数据选择器(多路选择器)Mux。
选择模块4设置为在第n行子像素的预留时段处于关断状态，在第n+1行子像素的数据写入时段处于导通状态，以使数据信号输出单元11向第n+1行子像素提供稳定的第一数据信号。
选择模块4在每行子像素的预留时段均处于关断状态，在每行子像素的数据写入时段均处于导通状态。在第n行子像素的数据写入时段，选择模块4处于导通状态，将电压模块3输出的第二数据信号提供给第n行子像素，即第二数据信号写入第n行子像素的像素电路中。在第n行子像素的预留时段，选择模块4处于关断状态，停止将电压模块3输出的第二数据信号提供给第n行子像素，即第n行子像素的像素电路不再写入第二数据信号。另外，在第n行子像素的预留时段内，数据信号输出单元11由关断状态切换为导通状态，即数据信号输出单元11开始工作，电压模块3停止输出第二数据信号，数据信号输出单元11可以输出电压异常的第一数据信号，选择模块4处于关断状态，使得电压异常的第一数据信号不会提供给第n行子像素。
选择模块4在每行子像素的准备时段均处于关断状态。在第n+1行子像素的准备时段，选择模块4处于关断状态，停止将数据信号输出单元11输出的数据信号提供给第n+1行子像素，使得数据信号输出单元11在第n+1行子像素的准备时段仍可以输出电压异常的第一数据信号，但在第n+1行子像素的数据写入时段之前，数据信号输出单元11需要输出稳定的第一数据信号。在第n+1行子像素的数据写入时段，选择模块4处于导通状态，将数据信号输出单元11输出的稳定的第一数据信号提供给第n+1行子像素，即稳定的第一数据信号写入第n+1行子像素的像素电路中。
在一些实施例中，如图2所示，选择模块4包括多个选择单元41，M列子像素可以划分为多组子像素，且每组子像素包括多列子像素，多个选择单元41与每组子像素中的多列子像素的像素电路一一对应连接。数据信号输出单元11具有多个输出端，数据信号输出单元11的每个输出端均与选择模块4中的多个选择单元41连接，以使数据信号输出单元11的每个输出端对应一组子像素中的多列子像素。例如，选择模块4可以采用Mux 1:6方案，即选择模块4包括六个选择单元41，M列子像素中每六列子像素为一组，数据信号输出单元11的每个输出端对应一组子像素中的六列子像素。另外，选择模块4也可以采用Mux 1:9方案、Mux 1:12方案或其他方案，此处不作具体限定。
在每行子像素的数据写入时段，选择模块4中的多个选择单元41依次导通，以将数据信号依次写入一组子像素中的多列子像素的像素电路中。在每行子像素的准备时段和预留时段，选择模块4中的所有选择单元41均处于关断状态。本实施例设置选择模块4，可以减小布线空间。如图3所示，对于柔性AMOLED穿戴产品，选择模块4的设置可以节约布线区(Pad区)40空间。
在一些实施例中，驱动模块1还包括选择信号输出单元13，选择信号输出单元13与选择模块4连接。选择信号输出单元13设置为在第n行子像素的预留时段，向选择模块 4提供第一电位选择信号；在第n+1行子像素的数据写入时段，向选择模块4提供第二电位选择信号。选择模块4还设置为在第n行子像素的预留时段，基于第一电位选择信号的控制处于关断状态；在第n+1行子像素的数据写入时段，基于第二电位选择信号的控制处于导通状态，以使数据信号输出单元向第n+1行子像素提供稳定的第一数据信号。
选择信号输出单元13输出的选择信号可以控制选择模块4的导通或关断。第一电位选择信号与第二电位选择信号的电位相反。若选择模块4高电平有效，即选择模块4输入高电平导通，则选择信号输出单元13提供给选择模块4的第一电位选择信号为低电位，第二电位选择信号为高电位；若选择模块4低电平有效，即选择模块4输入低电平导通，则选择信号输出单元13提供给选择模块4的第一电位选择信号为高电位，第二电位选择信号为低电位。
在第n行子像素的数据写入时段，选择信号输出单元13将第二电位选择信号输入至选择模块4，以控制选择模块4处于导通状态，使电压模块3将第二数据信号提供给第n行子像素。在第n行子像素的预留时段，选择信号输出单元13将第一电位选择信号输入至选择模块4，以控制选择模块4处于关断状态，停止将电压模块3输出的第二数据信号或数据信号输出单元11输出的第一数据信号提供给第n行子像素。在第n+1行子像素的准备时段，选择信号输出单元13将第一电位选择信号输入至选择模块4，以控制选择模块4处于关断状态，停止将数据信号输出单元11输出的第一数据信号提供给第n+1行子像素。在第n+1行子像素的数据写入时段，选择信号输出单元13将第二电位选择信号输入至选择模块4，以控制选择模块4处于导通状态，使数据信号输出单元11将稳定的第一数据信号提供给第n+1行子像素。
在一些实施例中，如图2所示，每个选择单元41包括晶体管T1，晶体管T1的控制端与选择信号输出单元13连接，晶体管T1的输入端与数据信号输出模块11和电压模块3连接，晶体管T1的输出端与对应的子像素20的像素电路连接。
在一些实施例中，选择信号输出单元13可以包括高低电位输出子单元(图中未示出)和数位子单元(图中未示出)。高低电位输出子单元与数位子单元连接，数位子单元分别与多个选择单元41中的晶体管T1的控制端连接。
高低电位输出子单元用于向数位子单元提供选择信号。数位子单元用于将选择信号转化为具有时序的波形，以实现选择模块4中各个选择单元41在不同时刻的导通或关断。
下面结合图4和图5对本申请实施例提供的显示模组的工作原理进行详细说明。
本实施例中的显示模组属于电流驱动发光器件，会将外部电压转换成控制发光器件的电流Id＝A(VDD-Vdata)2。其中，A为常数，VDD为电源电压，Vdata为数据信号。VDD为恒定电压，通过改变数据信号Vdata的电压大小，可以控制流经发光器件的电流，进而控制发光器件的亮度。根据该电流公式可知，黑色画面(显示亮度最低)下数据信号Vdata的电压最大，定义此时数据信号Vdata为VGMP；白色画面(显示亮度最高)下数据信号Vdata的电压最小，定义此时数据信号Vdata为VGSP。随着像素发光强度的变化，数据信号Vdata在VGMP和VGSP之间变化。
显示面板2在显示画面时，对N行子像素逐行扫描。每行子像素的扫描由行参考信号Hsync来控制，即在每行子像素的扫描开始时刻，输入一个行参考信号Hsync，以表明该行子像素进入扫描阶段。在第n行子像素对应显示黑色时，使能信号单元12向数据信号输出单元11提供第一电位使能信号(即低电位的使能信号SOPEN)，以控制数据信号输出单元11处于关断状态，即控制数据信号输出单元11不输出数据信号，以节省功耗。 电压模块3通过选择模块4向第n行子像素提供第二数据信号VGMP，使选择模块4的输入端(即晶体管T1的输入端)的输入信号ST为第二数据信号VGMP。
在第n+1行子像素对应显示白色时，数据信号输出单元11需要工作，以通过选择模块4向第n+1行子像素提供稳定的第一数据信号VGSP。相关技术中，如图4所示，使能信号单元12向数据信号输出单元11提供第二电位使能信号(即高电位的使能信号SOPEN)的时刻与第n+1行子像素的行参考信号Hsync的开启时刻相同，也就是说，在第n+1行子像素的扫描阶段的开始时刻，使能信号单元12向数据信号输出单元11提供第二电位使能信号(即高电位的使能信号SOPEN)，以控制数据信号输出单元11由关断状态切换为导通状态。由于驱动模块1的生产工艺有波动性，导致不同数据信号输出单元11的电压输出能力不同。电压输出能力正常的数据信号输出单元11在第n+1行子像素的准备时段t1能够输出稳定的第一数据信号VGSP，即选择模块4的输入端的输入信号ST在第n+1行子像素的准备时段t1能够完成电压转换(即从第二数据信号VGMP转换为稳定的第一数据信号VGSP)，如图4中的正常ST时序。电压输出能力弱的数据信号输出单元11在第n+1行子像素的准备时段t1无法输出稳定的第一数据信号VGSP，即选择模块4的输入端的输入信号ST在第n+1行子像素的准备时段t1无法完成电压转换，导致输入信号ST在第n+1行子像素的数据写入阶段t2仍呈异常状态(即输入信号ST为电压异常的第一数据信号)，如图4中的异常ST时序。而在第n+1行子像素的数据写入阶段t2，选择信号输出单元13向选择模块4提供多个第二电位选择信号(即低电位的选择信号MUX)，以控制选择模块4中的多个选择单元41依次导通，从而将电压异常的第一数据信号提供给第n+1行子像素中的第一个子像素(红色子像素R)，导致显示画面出现红线。
基于此，如图5所示，本申请实施例将使能信号单元12向数据信号输出单元11提供第二电位使能信号(即高电位的使能信号SOPEN)的时刻提前至第n行子像素的预留时段t3内。在第n行子像素的数据写入时段t2，数据信号输出单元11处于关断状态，选择信号输出单元13向选择模块4提供多个第二电位选择信号(即低电位的选择信号MUX)，以控制选择模块4中的多个选择单元41依次导通，将电压模块3的第二数据信号VGMP依次写入多列子像素。在第n行子像素的预留时段t3，选择信号输出单元13向选择模块4提供第一电位选择信号(即高电位的选择信号MUX)，控制选择模块4处于关断状态，其他信号开始工作。使能信号单元12向数据信号输出单元11提供第二电位使能信号(即高电位的使能信号SOPEN)，以控制数据信号输出单元11由关断状态切换为导通状态。电压输出能力正常的数据信号输出单元11在第n行子像素的预留时段t3能够输出稳定的第一数据信号VGSP，即选择模块4的输入端的输入信号ST在第n行子像素的预留时段t3能够完成电压转换(即从第二数据信号VGMP转换为稳定的第一数据信号VGSP)，如图5中的正常ST时序。由于预留给数据信号输出单元11输出稳定的第一数据信号的时间变长，使得电压输出能力弱的数据信号输出单元11在第n+1行子像素的数据写入时段t2之前也能够输出稳定的第一数据信号VGSP，即选择模块4的输入端的输入信号ST在第n+1行子像素的数据写入时段t2之前能够完成电压转换(即从第二数据信号VGMP转换为稳定的第一数据信号VGSP)，如图5中的异常ST时序。在第n+1行子像素的数据写入时段t2，选择信号输出单元13向选择模块4提供多个第二电位选择信号(即低电位的选择信号MUX)，以控制选择模块4中的多个选择单元41依次导通，将稳定的第一数据信号VGSP依次写入多列子像素，从而避免将电压异常的第一数据信号写入红色子像素R，彻底解决红线不良的问题。
本申请实施例提供的显示模组，通过控制数据信号输出单元在第n行子像素的数据写入时段处于关断状态，控制数据信号输出单元在第n行子像素的预留时段内由关断状态切换为导通状态，以将数据信号输出单元的工作时间提前，以预留足够的时间供数据信号输 出单元输出稳定的第一数据信号，从而保证第n+1行子像素在整个数据写入时段写入稳定的第一数据信号，避免显示异常，提高显示效果。
相应地，本申请实施例还提供一种显示装置，包括上述显示模组。
本申请实施例提供的显示装置，通过控制数据信号输出单元在第n行子像素的数据写入时段处于关断状态，控制数据信号输出单元在第n行子像素的预留时段内由关断状态切换为导通状态，以将数据信号输出单元的工作时间提前，以预留足够的时间供数据信号输出单元输出稳定的第一数据信号，从而保证第n+1行子像素在整个数据写入时段写入稳定的第一数据信号，避免显示异常，提高显示效果。
本申请实施例提供的显示装置可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。
相应地，本申请实施例还提供一种显示模组的控制方法，能够应用于上述显示模组中。图6为本申请实施例提供的显示模组的控制方法的流程示意图。该显示模组包括驱动模块和显示面板，该驱动模块包括数据信号输出单元，该显示面板包括N行子像素，每行子像素的扫描阶段包括数据写入时段以及紧接在数据写入时段之后的预留时段。
如图6所示，本申请实施例提供的显示模组的控制方法包括步骤610至步骤620，如下：
步骤610、在第n行子像素的数据写入时段，控制数据信号输出单元处于关断状态。
步骤620、在第n行子像素的预留时段内，控制数据信号输出单元由关断状态切换为导通状态，以在第n+1行子像素的数据写入时段向第n+1行子像素提供稳定的第一数据信号，0＜n＜N。
在一些实施例中，预留时段包括紧接在数据写入时段之后的发光时段以及紧接在发光时段之后的空闲时段。步骤620中的在第n行子像素的预留时段内，控制数据信号输出单元由关断状态切换为导通状态，包括：
在第n行子像素的发光时段，控制数据信号输出单元处于关断状态；
在第n行子像素的空闲时段内，控制数据信号输出单元由关断状态切换为导通状态。
在一些实施例中，数据信号输出单元在第n行子像素的预留时段内由关断状态切换为导通状态的时刻，位于预留时段的后五分之一时段至后十分之一时段之间。
在一些实施例中，第一数据信号为显示面板的最大显示亮度所对应的数据信号。
本申请实施例提供的显示模组的控制方法，通过控制数据信号输出单元在第n行子像素的数据写入时段处于关断状态，控制数据信号输出单元在第n行子像素的预留时段内由关断状态切换为导通状态，以将数据信号输出单元的工作时间提前，预留足够的时间供数据信号输出单元输出稳定的第一数据信号，从而保证第n+1行子像素在整个数据写入时段写入稳定的第一数据信号，避免显示异常，提高显示效果。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”等所区分的对象通常为一类，并不限定对象的个数，例如第一对象可以是一个，也可以是多个。
在本申请的描述中，“多个”的含义是两个或两个以上。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示意性实施例”、“示 例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (15)

  1. 一种显示模组，包括驱动模块和显示面板，所述驱动模块包括数据信号输出单元，所述显示面板包括N行子像素，每行子像素的扫描阶段包括数据写入时段以及紧接在所述数据写入时段之后的预留时段；
    所述数据信号输出单元设置为在第n行子像素的数据写入时段处于关断状态，在所述第n行子像素的预留时段内由关断状态切换为导通状态，以在第n+1行子像素的数据写入时段向所述第n+1行子像素提供稳定的第一数据信号，0＜n＜N。
  2. 根据权利要求1所述的显示模组，其中，所述预留时段包括紧接在所述数据写入时段之后的发光时段以及紧接在所述发光时段之后的空闲时段；
    所述数据信号输出单元还设置为在所述第n行子像素的发光时段处于关断状态，在所述第n行子像素的空闲时段内由关断状态切换为导通状态，以在所述第n+1行子像素的数据写入时段向所述第n+1行子像素提供所述稳定的第一数据信号。
  3. 根据权利要求1所述的显示模组，其中，所述扫描阶段还包括紧接在所述数据写入时段之前的准备时段；
    所述数据信号输出单元还设置为在所述第n行子像素的预留时段内由关断状态切换为导通状态，以在所述第n+1行子像素的准备时段输出稳定的第一数据信号，并在所述第n+1行子像素的数据写入时段向所述第n+1行子像素提供所述稳定的第一数据信号。
  4. 根据权利要求1所述的显示模组，其中，所述驱动模块还包括使能信号单元；
    所述使能信号单元设置为在所述第n行子像素的数据写入时段，向所述数据信号输出单元提供第一电位使能信号；在所述第n行子像素的预留时段内，向所述数据信号输出单元提供第二电位使能信号；
    所述数据信号输出单元还设置为在所述第n行子像素的数据写入时段，基于所述第一电位使能信号的控制处于关断状态；在所述第n行子像素的预留时段内，基于所述第二电位使能信号的控制由关断状态转换为导通状态，以在所述第n+1行子像素的数据写入时段向所述第n+1行子像素提供稳定的第一数据信号。
  5. 根据权利要求1所述的显示模组，其中，所述数据信号输出单元在所述第n行子像素的预留时段内由关断状态切换为导通状态的时刻，位于所述预留时段的后五分之一时段至后十分之一时段之间。
  6. 根据权利要求1所述的显示模组，其中，所述第一数据信号为所述显示面板的最大显示亮度所对应的数据信号。
  7. 根据权利要求1所述的显示模组，其中，所述显示模组还包括电压模块；
    所述电压模块设置为在所述第n行子像素的数据写入时段，向所述第n行子像素提供第二数据信号。
  8. 根据权利要求7所述的显示模组，其中，所述第二数据信号为所述显示面板的最小显示亮度所对应的数据信号。
  9. 根据权利要求1所述的显示模组，其中，所述显示模组还包括选择模块；
    所述选择模块设置为在所述第n行子像素的预留时段处于关断状态，在所述第n+1行子像素的数据写入时段处于导通状态，以使所述数据信号输出单元向所述第n+1行子像素提供所述稳定的第一数据信号。
  10. 根据权利要求9所述的显示模组，其中，所述驱动模块还包括选择信号输出单元；
    所述选择信号输出单元设置为在所述第n行子像素的预留时段，向所述选择模块提供第一电位选择信号；在所述第n+1行子像素的数据写入时段，向所述选择模块提供第二电位选择信号；
    所述选择模块还设置为在所述第n行子像素的预留时段，基于所述第一电位选择信号的控制处于关断状态；在所述第n+1行子像素的数据写入时段，基于所述第二电位选择信号的控制处于导通状态，以使所述数据信号输出单元向所述第n+1行子像素提供所述稳定的第一数据信号。
  11. 一种显示装置，包括权利要求1至10中任一项所述的显示模组。
  12. 一种显示模组的控制方法，所述显示模组包括驱动模块和显示面板，所述驱动模块包括数据信号输出单元，所述显示面板包括N行子像素，每行子像素的扫描阶段包括数据写入时段以及紧接在所述数据写入时段之后的预留时段；所述方法包括：
    在第n行子像素的数据写入时段，控制所述数据信号输出单元处于关断状态；
    在所述第n行子像素的预留时段内，控制所述数据信号输出单元由关断状态切换为导通状态，以在第n+1行子像素的数据写入时段向所述第n+1行子像素提供稳定的第一数据信号，0＜n＜N。
  13. 根据权利要求12所述的显示模组的控制方法，其中，所述预留时段包括紧接在所述数据写入时段之后的发光时段以及紧接在所述发光时段之后的空闲时段；
    所述在所述第n行子像素的预留时段内，控制所述数据信号输出单元由关断状态切换为导通状态，包括：
    在所述第n行子像素的发光时段，控制所述数据信号输出单元处于关断状态；
    在所述第n行子像素的空闲时段内，控制所述数据信号输出单元由关断状态切换为导通状态。
  14. 根据权利要求12所述的显示模组的控制方法，其中，所述数据信号输出单元在所述第n行子像素的预留时段内由关断状态切换为导通状态的时刻，位于所述预留时段的后五分之一时段至后十分之一时段之间。
  15. 根据权利要求12所述的显示模组的控制方法，其中，所述第一数据信号为所述显示面板的最大显示亮度所对应的数据信号。
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