WO2024239304A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2024239304A1
WO2024239304A1 PCT/CN2023/096186 CN2023096186W WO2024239304A1 WO 2024239304 A1 WO2024239304 A1 WO 2024239304A1 CN 2023096186 W CN2023096186 W CN 2023096186W WO 2024239304 A1 WO2024239304 A1 WO 2024239304A1
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WIPO (PCT)
Prior art keywords
electrode
substrate
transistor
line
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/096186
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English (en)
French (fr)
Inventor
张跳梅
胡明
蒋志亮
邱海军
刘烺
马鸿博
杨明坤
刘臻
吴建鹏
高文辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Filing date
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US18/832,113 priority Critical patent/US20260182173A1/en
Priority to PCT/CN2023/096186 priority patent/WO2024239304A1/zh
Priority to CN202380009217.6A priority patent/CN119605353B/zh
Publication of WO2024239304A1 publication Critical patent/WO2024239304A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H10H29/32—Active-matrix LED displays characterised by the geometry or arrangement of elements within a subpixel, e.g. arrangement of the transistor within its RGB subpixel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H10H29/49—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H10H29/39—Connection of the pixel electrodes to the driving transistors

Definitions

  • the present invention relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a display substrate, the display substrate includes a driving circuit layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, the driving circuit layer includes at least a plurality of circuit units, at least one first power connection line and at least one second power connection line extending along a first direction, at least one first power line and at least one second power line extending along a second direction, at least one circuit unit includes a pixel driving circuit, the first power line is connected to the pixel driving circuit, the first power line is configured to continuously provide a high-level signal to the pixel driving circuit, the light-emitting structure layer includes at least a plurality of light-emitting units, at least one light-emitting unit includes a cathode, the second power line is connected to the cathode, the second power line is configured to continuously provide a low-level signal to the cathode; the first power line is connected to the first power connection line to form a mesh structure
  • the pixel driving circuit includes a first shielding electrode and at least one dual-gate structure transistor, wherein an orthographic projection of the first shielding electrode on the substrate at least partially overlaps with an orthographic projection of a node between two gate electrodes of the dual-gate structure transistor on the substrate; the first shielding electrode is connected to the first power connection line; or, the first shielding electrode is connected to the second power connection line.
  • the at least one dual-gate structure transistor includes a first initialization transistor and a compensation transistor, the first electrode of the first initialization transistor is connected to the first initial signal line, the first electrode of the compensation transistor is connected to the second electrode of the first initialization transistor, the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor on the substrate, and the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the compensation transistor on the substrate.
  • the first shielding electrode and the second power connection line are an integrated structure connected to each other.
  • the second power connection line is located on a side of the first power connection line close to the first initialization transistor and the compensation transistor.
  • the first shielding electrode includes at least a first sub-electrode and a second sub-electrode, the first end of the first sub-electrode is connected to the second power connection line, the second end of the first sub-electrode extends in a direction close to the first power connection line, and the orthographic projection of the second end of the first sub-electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor on the substrate; the first end of the second sub-electrode is connected to the second power connection line, the second end of the second sub-electrode extends in a direction close to the first power connection line, and the orthographic projection of the second end of the second sub-electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the compensation transistor on the substrate.
  • the first shielding electrode and the first power connection line are an integrated structure connected to each other.
  • the first power connection line is located between the second power connection line and the A side close to the first initialization transistor and the compensation transistor.
  • the first shielding electrode includes at least a third sub-electrode and a fourth sub-electrode, the first end of the third sub-electrode is connected to the first power connection line, the second end of the third sub-electrode extends in a direction close to the second power connection line, and the orthographic projection of the second end of the third sub-electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor on the substrate; the first end of the fourth sub-electrode is connected to the first power connection line, the second end of the fourth sub-electrode extends in a direction close to the second power connection line, and the orthographic projection of the second end of the fourth sub-electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the compensation transistor on the substrate.
  • the pixel driving circuit also includes a first storage capacitor and a second storage capacitor
  • the first storage capacitor includes at least a first plate and a third plate, the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate
  • the second storage capacitor includes at least a second plate and a fourth plate, the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate
  • the second plate is connected to the third plate
  • the fourth plate is connected to the first power connection line
  • the first shielding electrode is connected to the fourth plate.
  • the first shielding electrode and the fourth electrode plate are interconnected as an integral structure.
  • the first shielding electrode includes a first extension segment and a first shielding segment; the first extension segment is in the shape of a strip extending along the second direction, and the first shielding segment is in the shape of a strip extending along the first direction; the first end of the first extension segment is connected to the fourth electrode plate, and the second end of the first extension segment is connected to the first shielding segment; the first shielding segment includes a first shielding end and a second shielding end, and the orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor in the present circuit unit on the substrate, and the orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the compensation transistor in the adjacent circuit unit on the substrate.
  • the at least one dual-gate structure transistor further includes a data writing transistor and a first reference transistor, wherein a first electrode of the data writing transistor is connected to the data signal line.
  • the first electrode of the first reference transistor is connected to the first reference signal line, and the second electrode of the data writing transistor is connected to the second electrode of the first reference transistor;
  • the pixel driving circuit further includes a second shielding electrode, and the second shielding electrode is arranged between the first electrode of the data writing transistor and the second electrode of the data writing transistor.
  • the at least one dual-gate structure transistor further includes a data writing transistor and a first reference transistor, a first electrode of the data writing transistor is connected to a data signal line, a first electrode of the first reference transistor is connected to a first reference signal line, and a second electrode of the data writing transistor is connected to a second electrode of the first reference transistor;
  • the pixel driving circuit also includes a third shielding electrode and a fourth shielding electrode, wherein the orthographic projection of the third shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the data writing transistor on the substrate, and the orthographic projection of the fourth shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first reference transistor on the substrate.
  • an orthographic projection of the second power connection line on the substrate at least partially overlaps an orthographic projection of the first initial signal line on the substrate.
  • the driving circuit layer includes multiple conductive layers; the first power line and the first power connection line are arranged in different conductive layers, and the first power line is connected to the first power connection line through a via; the second power line and the second power connection line are arranged in different conductive layers, and the second power line is connected to the second power connection line through a via.
  • the first power connection line and the second power connection line are disposed on the same layer, and the first power line and the second power line are disposed on the same layer.
  • the multiple conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence along a direction away from the substrate; the first power connection line and the second power connection line are arranged in the third conductive layer, and the first power line and the second power line are arranged in the fourth conductive layer.
  • the driving circuit layer includes a plurality of conductive layers; the plurality of conductive layers at least include: The first conductive layer, the second conductive layer, and the third conductive layer are provided; the first shielding electrode is provided in the second conductive layer, or the first shielding electrode is provided in the third conductive layer.
  • the pixel driving circuit also includes a first storage capacitor and a second storage capacitor
  • the first storage capacitor includes at least a first electrode plate and a third electrode plate, and the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the third electrode plate on the substrate
  • the second storage capacitor includes at least a second electrode plate and a fourth electrode plate, and the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate on the substrate
  • the first electrode plate and the second electrode plate are arranged in the first conductive layer
  • the third electrode plate and the fourth electrode plate are arranged in the second conductive layer.
  • the present disclosure further provides a display device, comprising the aforementioned display substrate.
  • FIG1 is a schematic structural diagram of a display device
  • FIG4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • FIG6 is an enlarged view of the first storage capacitor and the second storage capacitor region in FIG5;
  • FIG7 is a schematic diagram of a display substrate after a semiconductor layer pattern is formed according to the present disclosure.
  • FIGS. 8A and 8B are schematic diagrams of a display substrate after a first conductive layer pattern is formed according to the present disclosure
  • FIGS. 9A and 9B are schematic diagrams of a display substrate after a second conductive layer pattern is formed according to the present disclosure.
  • FIG10 is a schematic diagram of a display substrate after a fourth insulating layer pattern is formed according to the present disclosure.
  • FIGS. 11A and 11B are schematic diagrams of a display substrate after a third conductive layer pattern is formed on the substrate according to the present disclosure
  • FIG12 is a schematic diagram of a display substrate after a fifth insulating layer pattern is formed according to the present disclosure.
  • FIG17 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG20 is a schematic diagram of another display substrate after a fifth insulating layer pattern is formed in the present disclosure.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the “source electrode” and the “drain electrode” may be interchanged, and the “source terminal” and the “drain terminal” may be interchanged.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line, the light emitting signal line and the data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected to the pixel driving circuit of the circuit unit.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc.
  • the scan driver may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc. to the light emitting driver.
  • the data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values and control signals received from the timing controller. For example, the data driver can sample grayscale values using a clock signal, and apply data voltages corresponding to grayscale values to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number.
  • the scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller.
  • the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm.
  • the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number.
  • the light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller.
  • the light driver can transmit the emission signal with a cut-off level pulse Sequentially provided to the light emitting signal lines E1 to Eo.
  • FIG2 is a schematic diagram of a planar structure of a display substrate.
  • the display substrate may include a display area and a frame area located around the display area.
  • the display area of the display substrate may include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light.
  • Each sub-pixel may include a circuit unit and a light-emitting unit, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to a scanning signal line, a data signal line, and a light-emitting signal line, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.
  • FIG3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels in the display substrate.
  • the display area of the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101.
  • the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited in the present disclosure.
  • the driving circuit layer 102 may include a plurality of circuit units, the circuit units may include at least a pixel driving circuit, the pixel driving circuit may include a plurality of transistors and a storage capacitor.
  • the light emitting structure layer 103 may include a plurality of light emitting units, the light emitting units may include at least a light emitting device, the light emitting device may include an anode, an organic light emitting layer and a cathode, the anode is connected to the pixel driving circuit, the organic light emitting layer is connected to the anode, the cathode is connected to the organic light emitting layer, and the organic light emitting layer emits light of corresponding colors under the drive of the anode and the cathode.
  • An exemplary embodiment of the present disclosure provides a display substrate, the display substrate includes a driving circuit layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, the driving circuit layer includes at least a plurality of circuit units, at least one first power connection line and at least one second power connection line extending along a first direction, at least one first power line and at least one second power line extending along a second direction, at least one circuit unit includes a pixel driving circuit, the first power line is connected to the pixel driving circuit, the first power line is configured to continuously provide a high-level signal to the pixel driving circuit, the light-emitting structure layer includes at least a plurality of light-emitting units, at least one light-emitting unit includes a cathode, the second power line is connected to the cathode, the second power line is configured to continuously provide a low-level signal to the cathode; the first power line is connected to the first power connection line to form a mesh
  • the pixel driving circuit includes a first shielding electrode and at least one dual-gate structure transistor, wherein an orthographic projection of the first shielding electrode on the substrate at least partially overlaps with an orthographic projection of a node between two gate electrodes of the dual-gate structure transistor on the substrate; the first shielding electrode is connected to the first power connection line; or, the first shielding electrode is connected to the second power connection line.
  • the at least one dual-gate structure transistor includes a first initialization transistor and a compensation transistor, the first electrode of the first initialization transistor is connected to the first initial signal line, the first electrode of the compensation transistor is connected to the second electrode of the first initialization transistor, the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor on the substrate, and the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the compensation transistor on the substrate.
  • the first shielding electrode and the first power connection line are an integral structure connected to each other.
  • the pixel driving circuit also includes a first storage capacitor and a second storage capacitor
  • the first storage capacitor includes at least a first plate and a third plate, the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate
  • the second storage capacitor includes at least a second plate and a fourth plate, the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate
  • the second plate is connected to the third plate
  • the fourth plate is connected to the first power connection line
  • the first shielding electrode is connected to the fourth plate.
  • the first shielding electrode and the fourth electrode plate are an integral structure connected to each other.
  • the display substrate of the present disclosure is described below by way of some exemplary embodiments.
  • FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C or 9T2C structure.
  • the pixel driving circuit of the exemplary embodiment of the present disclosure may be a 9T2C structure, which may include 9 transistors (a first transistor T1 to a ninth transistor T9) and 2 storage capacitors (a first storage capacitor C1 and a second storage capacitor C2), and the pixel driving circuit is respectively connected to 12 signal lines (a first scanning signal line S1, a second scanning signal line S2, a third scanning signal line S3, a fourth scanning signal line S4, a first light emitting signal line EM1, a second light emitting signal line EM2, a first initial signal line INIT1, a second initial signal line INIT2, a first reference signal line REF1, a second reference signal line REF2, a data signal line DATA and a first power line VDD).
  • 9 transistors a first transistor T1 to a ninth transistor T9
  • 2 storage capacitors a first storage capacitor C1 and a second storage capacitor C2
  • the pixel driving circuit is respectively connected to 12 signal lines (a first scanning signal line S1, a second scanning signal line S2, a
  • the pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5.
  • the first node N1 is connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the first storage capacitor C1, respectively.
  • the second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the eighth transistor T8, and the second electrode of the fifth transistor T5, respectively.
  • the third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively.
  • the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.
  • the fifth node N5 is connected to the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the second end of the first storage capacitor C1, and the second end of the second storage capacitor C2, respectively.
  • a first end (lower plate) of the first storage capacitor C1 is connected to the first node N1, and a second end (upper plate) of the first storage capacitor C1 is connected to the fifth node N5.
  • a first end (upper plate) of the second storage capacitor C2 is connected to the first power line VDD, and a second end (lower plate) of the second storage capacitor C2 is connected to the fifth node N5.
  • a gate electrode of the first transistor T1 is connected to the fourth scan signal line S4, a first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and a second electrode of the first transistor is connected to the first node N1.
  • the first transistor T1 transmits a first initial voltage to the gate electrode of the third transistor T3 and the first end of the first storage capacitor C1, so that the charge accumulated in the first storage capacitor C1 is released, and initialization is achieved.
  • the gate electrode of the second transistor T2 is connected to the second scan signal line S2.
  • the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the gate electrode of the third transistor T3 to the second electrode.
  • the gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first end of the first storage capacitor C1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the third transistor T3 can be called a driving transistor, and the third transistor T3 determines the size of the driving current according to the potential difference between its gate electrode and the first electrode.
  • a gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the fifth node N5.
  • the fourth transistor T4 When a turn-on signal is applied to the third scan signal line S3, the fourth transistor T4 enables the data voltage of the data signal line DATA to be input to the second end of the first storage capacitor C1 and the second end of the second storage capacitor C2.
  • a gate electrode of the fifth transistor T5 is connected to the first light emitting signal line EM1, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.
  • a gate electrode of the sixth transistor T6 is connected to the second light emitting signal line EM2, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.
  • the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device EL emit light.
  • a gate electrode of the seventh transistor T7 is connected to the first scan signal line S1
  • a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2
  • a second electrode of the seventh transistor T7 is connected to the fourth node N4.
  • a gate electrode of the eighth transistor T8 is connected to the first scan signal line S1, a first electrode of the eighth transistor T8 is connected to the second reference signal line REF2, and a second electrode of the eighth transistor T8 is connected to the second node N2.
  • the eighth transistor T8 transmits the second reference signal to the second node N2.
  • a gate electrode of the ninth transistor T9 is connected to the second scan signal line S2, a first electrode of the ninth transistor T9 is connected to the first reference signal line REF1, and a second electrode of the ninth transistor T9 is connected to the fifth node N5.
  • the ninth transistor T9 transmits the first reference signal to the fifth node N5.
  • the first transistor T1 may be referred to as a first initialization transistor
  • the second transistor T2 may be referred to as a compensation transistor
  • the third transistor T3 may be referred to as a driving transistor
  • the fourth transistor T4 may be referred to as a data writing transistor
  • the fifth transistor T5 may be referred to as a first light-emitting transistor
  • the sixth transistor T6 may be referred to as a second light-emitting transistor
  • the seventh transistor T7 may be referred to as a second initialization transistor
  • the eighth transistor T8 may be referred to as a second reference transistor
  • the ninth transistor T9 may be referred to as a first reference transistor.
  • the light emitting device EL may be an OLED, including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode).
  • the first electrode of the light emitting device EL is connected to the fourth node N4, the second electrode of the light emitting device EL is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low level signal, and the signal of the first power line VDD is a continuously provided high level signal.
  • the first transistor T1 to the ninth transistor T9 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the ninth transistor T9 may include a P-type transistor and an N-type transistor.
  • the first transistor T1 to the ninth transistor T9 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS for short), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide).
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • the low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate, that is, the LTPS+Oxide (LTPO for short) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, The display quality can be improved.
  • LTPS+Oxide (LTPO for short) display substrate which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, The display quality can be improved.
  • the operation process of the pixel driving circuit shown in FIG. 4 may include a first stage to a fifth stage.
  • the first phase may include multiple sub-phases that are repeatedly executed, and each sub-phase may include a first sub-phase and a second sub-phase that are executed in sequence.
  • the signals of the fourth scan signal line S4 and the first light emitting signal line EM1 are on signals, and the signals of other signal lines are off signals.
  • the signal of the fourth scan signal line S4 is an on signal, which can turn on the first transistor T1, and the first initial signal of the first initial signal line INIT1 can be provided to the first node N1 to initialize the first node N1.
  • the third transistor T3 is a P-type transistor, the third transistor T3 is turned on.
  • the on signal of the first light emitting signal line EM1 can turn on the fifth transistor T5, and the first power signal of the first power line VDD can be provided to the second node N2.
  • the signals of the second scan signal line S2 and the first light emitting signal line EM1 are on signals, and the signals of other signal lines are off signals.
  • the signal of the second scan signal line S2 is an on signal, which can turn on the second transistor T2, connect the first node N1 and the third node N3, and write the threshold voltage of the third transistor T3 to the first node N1.
  • the signal of the second scan signal line S2 is an on signal, which can turn on the ninth transistor T9, and the first reference signal of the first reference signal line REF1 is provided to the fifth node N5, and the fifth node N5 is initialized.
  • the on signal of the first light emitting signal line EM1 can turn on the fifth transistor T5, and the first power signal of the first power line VDD can be provided to the second node N2.
  • Phase 2 The signal of the third scan signal line S3 is an on signal, and the signals of other signal lines are off signals.
  • the signal of the third scan signal line S3 is an on signal, which can turn on the fourth transistor T4, and the data voltage provided by the data signal line DATA is written into the fifth node N5.
  • the signal of the first scanning signal line S1 is a conduction signal, and the signals of other signal lines are disconnection signals.
  • the signal of the first scanning signal line S1 is a conduction signal, so that the seventh transistor T7 is turned on, and the second initial signal of the second initial signal line INIT2 can be written into the fourth node N4 to initialize the fourth node N4, so as to prevent the residual signal of the previous frame from affecting the display of the current frame.
  • the signal of the first scanning signal line S1 is a conduction signal, so that the eighth transistor T8 is turned on, and the second reference signal line REF2 The second reference signal may be written into the second node N2.
  • Phase 4 The signal of the second light emitting signal line EM2 is an on signal, and the signals of other signal lines are off signals.
  • the signal of the second light emitting signal line EM2 is an on signal, so that the sixth transistor T6 is turned on, and the third node N3 and the fourth node N4 are connected, so that the potentials of the third node N3 and the fourth node N4 are the same.
  • the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are on signals, and the signals of other signal lines are off signals.
  • the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are on signals, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the first power signal of the first power line VDD can provide a driving signal to the light-emitting device EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, so as to drive the light-emitting device EL to emit light.
  • the driving transistor i.e., the third transistor T3
  • the driving transistor i.e., the third transistor T3
  • the driving transistor i.e., the third transistor T3
  • the driving transistor i.e., the third transistor T3
  • the second reference signal is written to the second node N2, and by changing the potential of the second node N2, it can help reduce the hysteresis of the driving transistor.
  • the fourth stage by connecting the third node N3 and the fourth node N4, the potential of the fourth node N4 can be increased, which is conducive to reducing the time required to reach the start-up voltage of the light-emitting device later.
  • the pixel driving circuit provided by the present disclosure can effectively improve the hysteresis of the driving transistor, which is beneficial to improving the display effect.
  • FIG5 is a schematic diagram of a planar structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driving circuit in three circuit units (a first circuit unit, a second circuit unit, and a third circuit unit) in the display substrate.
  • the display substrate may include a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the driving circuit layer may include at least a plurality of circuit units, the light-emitting structure layer may include at least a plurality of light-emitting units, at least one circuit unit includes a pixel driving circuit, at least one light-emitting unit includes a light-emitting device, the light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode, and the anode in the light-emitting unit is connected to the pixel driving circuit in the corresponding circuit unit.
  • the circuit unit referred to in the present disclosure Refers to the area divided according to the pixel driving circuit, and the light-emitting unit mentioned in the present disclosure refers to the area divided according to the light-emitting device.
  • the position of the orthogonal projection of the light-emitting unit on the substrate may correspond to the position of the orthogonal projection of the circuit unit on the substrate, or the position of the orthogonal projection of the light-emitting unit on the substrate may not correspond to the position of the orthogonal projection of the circuit unit on the substrate.
  • a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row
  • a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column
  • a plurality of unit rows and a plurality of unit columns constitute a circuit unit array arranged in an array
  • the first direction X intersects with the second direction Y.
  • the driving circuit layer may further include at least one first power line 51 extending along the second direction Y, at least one second power line 52 extending along the second direction Y, at least one first power connection line 68 extending along the first direction X, and at least one second power connection line 69 extending along the first direction X.
  • the first power line 51 is connected to the pixel driving circuit in the plurality of circuit units, and the first power line 51 is configured to continuously provide a high level signal to the pixel driving circuit
  • the second power line 52 is connected to the cathodes of the plurality of light emitting units, and the second power line 52 is configured to continuously provide a low level signal to the cathode.
  • the first power line 51 extending along the second direction Y is connected to the first power connection line 68 extending along the first direction X to form a mesh structure for transmitting the first power signal
  • the second power line 52 extending along the second direction Y is connected to the second power connection line 69 extending along the first direction X to form a mesh structure for transmitting the second power signal.
  • a extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.
  • the driving circuit layer may further include a reference signal connection line 54 and a first reference signal line 91.
  • the shape of the first reference signal line 91 may be a line shape extending along the first direction X
  • the shape of the reference signal connection line 54 may be a line shape extending along the second direction Y.
  • the reference signal connection line 54 is interconnected with the first reference signal line 91 to form a mesh structure for transmitting the first reference signal.
  • the driving circuit layer may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a Fourth conductive layer.
  • the first power line 51 and the first power connection line 68 can be arranged in different conductive layers, and the first power line 51 and the first power connection line 68 can be connected through a via.
  • the second power line 52 and the second power connection line 69 can be arranged in different conductive layers, and the second power line 52 and the second power connection line 69 can be connected through a via.
  • first power line 51 and the second power line 52 may be disposed in the same layer and formed simultaneously by the same patterning process
  • first power connection line 68 and the second power connection line 69 may be disposed in the same layer and formed simultaneously by the same patterning process.
  • first power connection line 68 and the second power connection line 69 may be disposed in the third conductive layer, and the first power line 51 and the second power line 52 may be disposed in the fourth conductive layer.
  • the reference signal connection line 54 and the first reference signal line 91 may be disposed in different conductive layers, and the reference signal connection line 54 and the first reference signal line 91 may be connected through a via.
  • the first reference signal line 91 may be disposed in the third conductive layer, and the reference signal connection line 54 may be disposed in the fourth conductive layer.
  • At least one circuit unit may include a plurality of transistors, and the semiconductor layer may include at least active layers of the plurality of transistors.
  • At least one pixel driving circuit may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emitting transistor, a sixth transistor T6 as a second light emitting transistor, a seventh transistor T7 as a second initialization transistor, an eighth transistor T8 as a second reference transistor, a ninth transistor T9 as a first reference transistor, a first storage capacitor and a second storage capacitor.
  • FIG6 is an enlarged view of the first storage capacitor and the second storage capacitor region in FIG5.
  • the first storage capacitor may include at least a first electrode plate 71 and a third electrode plate 73, and the orthographic projection of the third electrode plate 73 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 71 on the substrate.
  • the second storage capacitor may include at least a second electrode plate 72 and a fourth electrode plate 74, and the orthographic projection of the fourth electrode plate 74 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 72 on the substrate.
  • the first electrode plate 71 and the second electrode plate 72 can be arranged in the first conductive layer
  • the third electrode plate 73 and the fourth electrode plate 74 can be arranged in the second conductive layer
  • the first electrode plate 71 can serve as a gate electrode of the third transistor T3
  • the second electrode plate 72 is connected to the third electrode plate 73
  • the fourth electrode plate 74 is connected to the first power line 51.
  • the gate electrode of the first transistor T1 is connected to the fourth scan signal line 64, the first electrode of the first transistor T1 is connected to the first initial signal line 81, and the second electrode of the first transistor T1 is respectively connected to the first electrode of the second transistor T2 and the first electrode plate 71 of the first storage capacitor.
  • the gate electrode of the second transistor T2 is connected to the second scan signal line 62, and the second electrode of the second transistor T2 is respectively connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6.
  • the gate electrode of the third transistor T3 serves as the first electrode plate 71 of the first storage capacitor, and the first electrode of the third transistor T3 is respectively connected to the second electrode of the fifth transistor T5 and the second electrode of the eighth transistor T8.
  • the gate electrode of the fourth transistor T4 is connected to the third scan signal line 63, the first electrode of the fourth transistor T4 is connected to the data signal line 53, and the second electrode of the fourth transistor T4 is respectively connected to the second electrode of the ninth transistor T9, the third electrode plate 73 of the first storage capacitor, and the second electrode plate 72 of the second storage capacitor.
  • the gate electrode of the fifth transistor T5 is connected to the first light emitting signal line 31, and the first electrode of the fifth transistor T5 is connected to the first power line 51.
  • the gate electrode of the sixth transistor T6 is connected to the second light emitting signal line 32, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7.
  • the gate electrode of the seventh transistor T7 is connected to the first scanning signal line 61, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 82.
  • the gate electrode of the eighth transistor T8 is connected to the first scanning signal line 61, and the first electrode of the eighth transistor T8 is connected to the second reference signal line 92.
  • the gate electrode of the ninth transistor T9 is connected to the second scanning signal line 62, and the first electrode of the ninth transistor T9 is connected to the first reference signal line 91.
  • the shapes of the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first light-emitting signal line 31, the second light-emitting signal line 32, the first initial signal line 81, the second initial signal line 82, the first reference signal line 91 and the second reference signal line 92 can be line shapes whose main parts extend along the first direction X, and the shapes of the first power line 51 and the data signal line 53 can be line shapes whose main parts extend along the second direction Y.
  • At least one circuit unit may also include a first connection electrode 41, which is respectively connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2 and the first electrode plate 71 of the first storage capacitor, and the first connection electrode 41 can serve as the first node of the pixel driving circuit.
  • At least one circuit unit may further include a power shielding block 51-1, which is connected to the first power line 51, and the positive projection of the power shielding block 51-1 on the substrate at least partially overlaps with the positive projection of the first connecting electrode 41 on the substrate to shield the influence of other signals in the pixel driving circuit on the first node.
  • At least one circuit unit may further include a second shielding electrode 37, the second shielding electrode 37 is connected to the fourth electrode plate 74, and the second shielding electrode 37 is disposed between the first electrode and the second electrode of the fourth transistor T4.
  • the second shielding electrode 37 is configured to shield the influence of the data voltage jump on the fifth node, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.
  • At least one circuit unit may further include a third shielding electrode 38, the third shielding electrode 38 is connected to the second reference signal line 92, and the positive projection of the third shielding electrode 38 on the substrate overlaps at least partially with the positive projection of the node between the two gate electrodes of the fourth transistor T4 on the substrate.
  • the third shielding electrode 38 is configured to shield the influence of the data voltage jump on the fourth transistor T4, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.
  • At least one circuit unit may further include a fourth shielding electrode 39, the fourth shielding electrode 39 is connected to the second reference signal line 92, and the orthographic projection of the fourth shielding electrode 39 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the ninth transistor T9 on the substrate.
  • the fourth shielding electrode 39 is configured to shield the influence of the data voltage jump on the ninth transistor T9, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.
  • Thin film refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the preparation process of the display substrate of this embodiment may include the following operations.
  • the semiconductor layer pattern of each circuit unit in the display substrate may include at least a first active layer 11 of a first transistor T1, a second active layer 12 of a second transistor T2, a third active layer 13 of a third transistor T3, a fourth active layer 14 of a fourth transistor T4, a fifth active layer 15 of a fifth transistor T5, a sixth active layer 16 of a sixth transistor T6, a seventh active layer 17 of a seventh transistor T7, an eighth active layer 18 of an eighth transistor T8, and a ninth active layer 19 of a ninth transistor T9, and the first to third active layers 11 to 13 and the fifth to eighth active layers 15 to 18 may be an integral structure connected to each other, and the fourth active layer 14 and the ninth active layer 19 may be an integral structure connected to each other.
  • the fourth active layer 14 and the ninth active layer 19 of the nth unit row may be located on a side of the third active layer 13 close to the n-1th unit row, that is, the fourth active layer 14 and the ninth active layer 19 may be located on a side of the third active layer 13 of the present circuit unit in the opposite direction of the second direction Y.
  • the first active layer 11, the second active layer 12, and the fifth active layer 15 to the eighth active layer 18 of the nth unit row may be located on a side of the third active layer 13 close to the n+1th unit row, that is, the first active layer 11, the second active layer 12, the fifth active layer 15 to the eighth active layer 18 may be located on a side of the second direction Y of the third active layer 13 of the present circuit unit.
  • the first active layer 11 may be located on one side of the third active layer 13 of the present circuit unit in the second direction Y
  • the fifth active layer 15 may be located on one side of the first active layer 11 of the present circuit unit in the second direction Y
  • the eighth active layer 18 may be located on the fifth active layer 15 of the present circuit unit.
  • the second active layer 12 may be located on one side of the second direction Y of the third active layer 13 of the present circuit unit
  • the sixth active layer 16 may be located on one side of the second direction Y of the second active layer 12 of the present circuit unit
  • the seventh active layer 17 may be located on one side of the second direction Y of the sixth active layer 16 of the present circuit unit.
  • the first active layer 11, the fourth active layer 14, the fifth active layer 15 and the eighth active layer 18 can be located on one side of the first direction X of the circuit unit (such as the side opposite to the first direction X), and the second active layer 12, the sixth active layer 16, the seventh active layer 17 and the ninth active layer 19 can be located on the other side of the first direction X of the circuit unit (such as one side of the first direction X).
  • the first active layer 11 and the second active layer 12 may be shaped like an "L”
  • the third active layer 13 may be shaped like a "C”
  • the fourth active layer 14 and the ninth active layer 19 may be shaped like an "n”
  • the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 may be shaped like an "I”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be connected to each other, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer.
  • the first region 13-1 of the third active layer, the second region 15-2 of the fifth active layer, and the second region 18-2 of the eighth active layer may be connected to each other, and the first region 13-1 of the third active layer may serve as the second region 15-2 of the fifth active layer and the second region 18-2 of the eighth active layer at the same time, constituting a second node N2 of the pixel driving circuit.
  • the second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be connected to each other, and the second region 13-2 of the third active layer may serve as the second region 12-2 of the second active layer and the first region 16-1 of the sixth active layer at the same time, constituting a third node N3 of the pixel driving circuit.
  • the second area 14-2 of the fourth active layer and the second area 19-2 of the ninth active layer can be connected to each other, and the second area 14-2 of the fourth active layer can serve as the second area 19-2 of the ninth active layer.
  • the second area 16-2 of the sixth active layer and the second area 17-2 of the seventh active layer can be connected to each other, and the second area 16-2 of the sixth active layer can serve as the second area 17-2 of the seventh active layer, constituting a fourth node N4 of the pixel driving circuit.
  • the first area 11-1 of the first active layer, the first area 14-1 of the fourth active layer, the first area 15-1 of the fifth active layer, the first area 17-1 of the seventh active layer, the first area 18-1 of the eighth active layer, and the first area 19-1 of the ninth active layer can be separately arranged, and the first area 14-1 of the fourth active layer can be located in the channel area of the fourth active layer close to the third active layer 13
  • the first region 19 - 1 of the ninth active layer may be located on a side of the channel region of the ninth active layer close to the third active layer 13 .
  • semiconductor layers in circuit units adjacent in the first direction X are connected to each other, that is, the semiconductor layer of the first circuit unit of the nth unit row is connected to the semiconductor layer of the second circuit unit of the nth unit row, and the semiconductor layer of the second circuit unit of the nth unit row is connected to the semiconductor layer of the third circuit unit of the nth unit row.
  • the display substrate may further include a first active connection line 10 and a second active connection line 20.
  • the first active connection line 10 may be located at one side of the ninth active layer 19 in the second direction Y and connected to the first region 19-1 of the ninth active layer of each circuit unit.
  • the second active connection line 20 may be located at one side of the seventh active layer 17 in the second direction Y and connected to the first region 17-1 of the seventh active layer of each circuit unit.
  • the shape of the first active connection line 10 may be a zigzag shape with the main part extending along the first direction X, and the first active connection line 10 and the ninth active layer of the plurality of circuit units may be an integrated structure connected to each other. Since the first region of the ninth active layer is connected to the first reference signal line formed subsequently, the first active connection line 10 may be reused as the first reference signal line extending along the first direction X, which not only ensures that the first regions of the plurality of ninth active layers in a unit row have the same potential, but also reduces the voltage drop of the first reference signal, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the second active connection line 20 may be in the shape of a straight line with a main portion extending along the first direction X, and the second active connection line 20 and the seventh active layer of the plurality of circuit units may be an integral structure connected to each other. Since the first region of the seventh active layer is connected to the second initial signal line formed subsequently, the second active connection line 20 may be reused as the second initial signal line extending along the first direction X, which not only ensures that the first regions of the plurality of seventh active layers in a unit row have the same potential, but also reduces the voltage drop of the second initial signal, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • semiconductor layers in circuit units adjacent to each other in the second direction Y are spaced apart from each other, that is, the semiconductor layer of the first circuit unit of the n-1th unit row is not connected to the semiconductor layer of the first circuit unit of the nth unit row, and the semiconductor layer of the first circuit unit of the nth unit row is not connected to the semiconductor layer of the first circuit unit of the n+1th unit row.
  • the first gate electrode 21 may be in an "L" shape and may be located on one side of the first electrode plate 71 in the second direction Y.
  • the region where the first gate electrode 21 overlaps with the first active layer may serve as the gate electrode of the first transistor T1 of the dual-gate structure.
  • the second gate electrode 22 may be in a "T" shape and may be located on one side of the first electrode 71 in the second direction Y.
  • the area where the second gate electrode 22 overlaps the second active layer may serve as the gate electrode of the second transistor T2 of the dual-gate structure.
  • the fourth gate electrode 24 may be in an "L" shape and may be located on the side of the second electrode 72 in the opposite direction of the second direction Y.
  • the area where the fourth gate electrode 24 overlaps with the fourth active layer may serve as the gate electrode of the fourth transistor T4 of the dual-gate structure.
  • the fifth gate electrode 25 may be in the shape of a strip extending along the second direction Y and may be located on one side of the first gate electrode 21 in the second direction Y.
  • the region where the fifth gate electrode 25 overlaps with the fifth active layer may serve as the gate electrode of the fifth transistor T5.
  • the sixth gate electrode 26 may be in a strip shape extending along the first direction X and may be located on one side of the second gate electrode 22 in the second direction Y.
  • the region where the sixth gate electrode 26 overlaps the sixth active layer may serve as the gate electrode of the sixth transistor T6.
  • the ninth gate electrode 29 may be in the shape of a strip extending along the first direction X, and may be located on one side of the second electrode plate 72 in the opposite direction of the second direction Y.
  • the area where the ninth gate electrode 29 overlaps with the ninth active layer may serve as the gate electrode of the ninth transistor T9 of the dual-gate structure.
  • the shape of the first scan signal line 61 can be a line shape in which the main part extends along the first direction X, and can be located on one side of the fifth gate electrode 25 and the sixth gate electrode 26 in the second direction Y.
  • the area where the first scan signal line 61 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7, and the area where the first scan signal line 61 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.
  • the shape of the first electrode 71 of the first storage capacitor can be rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projection of the first electrode 71 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate.
  • the first electrode 71 can simultaneously serve as the lower electrode of the first storage capacitor and the gate electrode of the third transistor T3.
  • the shape of the second electrode plate 72 of the second storage capacitor may be rectangular, and the corners of the rectangle may be chamfered, and may be located on one side of the first electrode plate 71 in the opposite direction of the second direction Y, and on one side of the fourth gate electrode 24 and the ninth gate electrode 29 in the second direction Y, that is, in the second direction Y, the second electrode plate 72 is located between the first electrode plate 71 and the fourth gate electrode 24 (ninth gate electrode 29), and the orthographic projection of the second electrode plate 72 on the substrate does not overlap with the orthographic projection of the semiconductor layer on the substrate.
  • the second electrode plate 72 may serve as the lower electrode plate of the second storage capacitor.
  • the areas of the first electrode plate 71 and the second electrode plate 72 projected on the substrate may be the same or different.
  • the area where the first active connection line 10 is connected to the first area of the ninth active layer is bent toward the ninth active layer, so that a concave portion is formed on the side of the first active connection line 10 away from the ninth active layer.
  • a protrusion 72-1 is provided on the side of the second electrode plate 72 close to the first active connection line 10.
  • the shape of the protrusion 72-1 can be rectangular.
  • the first end of the protrusion 72-1 is connected to the second electrode plate 72, and the second end of the protrusion 72-1 extends into the concave portion of the first active connection line 10.
  • the second electrode plate 72 and the protrusion 72-1 may be an integral structure connected to each other.
  • the present disclosure can effectively increase the area of the second electrode plate 72 and the capacitance of the second storage capacitor by providing the concave portion of the first active connection line 10 and the protrusion 72-1 of the second electrode plate 72.
  • the first conductive layer can be used as a shield to perform a conductor process on the semiconductor layer, and the semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the ninth transistor T9, and the area not shielded by the first conductive layer is
  • the semiconductor layer is conductorized, that is, the first region and the second region of the first to ninth active layers are all conductorized.
  • Forming a second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 9A and 9B , where FIG. 9B is a schematic diagram of the second conductive layer in FIG. 9A .
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern of each circuit unit in the display substrate includes at least: a first light-emitting signal line 31, a second light-emitting signal line 32, a repair line 33, a first shielding electrode 36, a second shielding electrode 37, a third shielding electrode 38, a fourth shielding electrode 39, a third plate 73 of a first storage capacitor, a fourth plate 74 of a second storage capacitor, a first initial signal line 81, and a second reference signal line 92.
  • the shapes of the first light-emitting signal line 31, the second light-emitting signal line 32, the repair line 33, the first initial signal line 81 and the second reference signal line 92 can be line shapes in which the main part extends along the first direction X, the first light-emitting signal line 31, the second light-emitting signal line 32, the repair line 33 and the first initial signal line 81 can be located between the first gate electrode 21 and the first scanning signal line 61, and the second reference signal line 92 can be located on the side of the fourth gate electrode 24 in the opposite direction of the second direction Y.
  • the first light-emitting signal line 31 can be located on one side of the second direction Y of the first gate electrode 21 of the present circuit unit
  • the first initial signal line 81 can be located on one side of the second direction Y of the first light-emitting signal line 31 of the present circuit unit
  • the second light-emitting signal line 32 can be located on one side of the second direction Y of the first initial signal line 81 of the present circuit unit
  • the repair line 33 can be located on one side of the second direction Y of the second light-emitting signal line 32 of the present circuit unit, that is, the second light-emitting signal line 32 can be located between the first light-emitting signal line 31 and the repair line 33
  • the first initial signal line 81 can be located between the first light-emitting signal line 31 and the second light-emitting signal line 32
  • the second reference signal line 92 can be located on the side opposite to the second direction Y of the first light-emitting signal line 31.
  • a first light-emitting connection block 31-1 is disposed on one side of the first light-emitting signal line 31 close to the second light-emitting signal line 32.
  • the first light-emitting connection block 31-1 may be disposed in each circuit unit.
  • a first end of the first light-emitting connection block 31-1 is connected to the first light-emitting signal line 31.
  • the second end of the connection block 31-1 extends toward the second light emitting signal line 32, and the first light emitting connection block 31-1 is configured to be connected to the fifth gate electrode 25 through a seventh connection electrode formed subsequently.
  • the first light emitting signal line 31 and the plurality of first light emitting connection blocks 31-1 may be an integral structure connected to each other.
  • a second light-emitting connection block 32-1 is provided on one side of the second light-emitting signal line 32 close to the first light-emitting signal line 31, and the second light-emitting connection block 32-1 may be provided in each circuit unit, a first end of the second light-emitting connection block 32-1 is connected to the second light-emitting signal line 32, a second end of the second light-emitting connection block 32-1 extends toward the direction of the first light-emitting signal line 31, and the second light-emitting connection block 32-1 is configured to be connected to the sixth gate electrode 26 through an eighth connection electrode formed subsequently.
  • the second light-emitting signal line 32 and the plurality of second light-emitting connection blocks 32-1 may be an integrated structure connected to each other.
  • a first initial connection block 81-1 is provided on one side of the first initial signal line 81 close to the first light emitting signal line 31, and the first initial connection block 81-1 may be provided in each circuit unit, a first end of the first initial connection block 81-1 is connected to the first initial signal line 81, and a second end of the first initial connection block 81-1 extends toward the first light emitting signal line 31, and the first initial connection block 81-1 is configured to be connected to the first region of the first active layer through a ninth connection electrode formed subsequently, thereby realizing that the first initial signal line 81 is connected to the first electrode of the first transistor T1, and the first initial signal line 81 may write the first initial signal into the first electrode of the first transistor T1.
  • the first initial signal line 81 and a plurality of first initial connection blocks 81-1 may be an integrated structure connected to each other.
  • a second reference connection block 92-1 is provided on a side of the second reference signal line 92 of the n+1th unit row away from the fourth electrode plate 74 of the n+1th unit row.
  • the second reference connection block 92-1 may be provided in each circuit unit, a first end of the second reference connection block 92-1 is connected to the second reference signal line 92, and a second end of the second reference connection block 92-1 extends in a direction away from the fourth electrode plate 74, that is, in a direction toward the nth unit row.
  • the second reference connection block 92-1 of the second reference signal line 92 in the n+1th unit row is configured to be connected to the first region of the eighth active layer in the nth unit row through a sixth connection electrode formed subsequently, and provide a second reference signal to the first electrode of the eighth transistor T8 in the nth unit row.
  • the second reference signal line 92 and a plurality of second reference connection blocks 92-1 may be an integrated structure connected to each other.
  • the third electrode plate 73 of the first storage capacitor may be rectangular.
  • the rectangular shape can be chamfered at its corners and can be located between the first light-emitting signal line 31 and the second reference signal line 92 of the circuit unit.
  • the orthographic projection of the third electrode 73 on the substrate at least partially overlaps with the orthographic projection of the first electrode 71 on the substrate.
  • the third electrode 73 can serve as the upper electrode of the first storage capacitor.
  • the first electrode 71 and the third electrode 73 constitute the first storage capacitor C1 of the pixel driving circuit.
  • the contour shape of the fourth plate 74 of the second storage capacitor can be rectangular, the corners of the rectangle can be chamfered, and it can be located between the second reference signal line 92 and the third plate 73 of the circuit unit.
  • the orthographic projection of the fourth plate 74 on the substrate at least partially overlaps with the orthographic projection of the second plate 72 on the substrate.
  • the fourth plate 74 can serve as the upper plate of the second storage capacitor, and the second plate 72 and the fourth plate 74 constitute the second storage capacitor C2 of the pixel driving circuit.
  • the areas of the third electrode plate 73 and the fourth electrode plate 74 projected on the substrate may be the same or different.
  • the area of the fourth electrode plate 74 projected on the substrate may be larger than the area of the third electrode plate 73 projected on the substrate.
  • a second opening 76 is provided on the fourth electrode plate 74 of each circuit unit, and the second opening 76 may be located in the middle of the fourth electrode plate 74, and the second opening 76 may be rectangular, so that the fourth electrode plate 74 forms a ring structure.
  • the second opening 76 exposes the third insulating layer covering the second electrode plate 72, and the orthographic projection of the second electrode plate 72 on the substrate includes the orthographic projection of the second opening 76 on the substrate.
  • the second opening 76 is configured to accommodate the eleventh via hole formed subsequently, and the eleventh via hole is located in the second opening 76 and exposes the second electrode plate 72, so that the second connection electrode formed subsequently is connected to the second electrode plate 72.
  • the first shielding electrode 36 may be in a "T" shape and may be located on a side of the fourth electrode plate 74 close to the first light emitting signal line 31.
  • the first shielding electrode 36 may be provided in each circuit unit.
  • the "T"-shaped first shielding electrode 36 may include a first extension section 36-1 and the first shielding segment 36-2, the first end of the first extension segment 36-1 is connected to the fourth electrode plate 74, and the second end of the first extension segment 36-1 is connected to the first shielding segment 36-2 after extending toward the first light-emitting signal line 31.
  • the shape of the first shielding segment 36-2 can be a strip shape extending along the first direction X.
  • the positive projection of the first shielding end on the substrate overlaps with the positive projection of the semiconductor layer between the two gate electrodes of the first transistor T1 in the present circuit unit on the substrate at least partially.
  • the positive projection of the second shielding end on the substrate overlaps with the positive projection of the semiconductor layer between the two gate electrodes of the second transistor T2 in the adjacent circuit unit on the substrate at least partially.
  • the first shielding electrode 36 is configured to shield the influence of the data voltage jump on the first transistor T1 and the second transistor T2, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.
  • the second shielding electrode 37 may be in an "I" shape, may be located on a side of the fourth electrode plate 74 close to the second reference signal line 92, and may be provided in each circuit unit. A first end of the second shielding electrode 37 is connected to the fourth electrode plate 74, a second end of the second shielding electrode 37 extends toward the second reference signal line 92, and a second end of the second shielding electrode 37 may be located between a first electrode of the fourth transistor T4 and a second electrode of the fourth transistor T4.
  • the second shielding electrode 37 is configured to shield the influence of the data voltage jump on the fifth node N5, to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit, and to improve the display effect.
  • the fourth electrode plate 74 , the first shielding electrode 36 , and the second shielding electrode 37 may be an integral structure connected to each other.
  • the orthographic projection of the third shielding electrode 38 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the fourth transistor T4 in the present circuit unit on the substrate.
  • the orthographic projection of the fourth shielding electrode 39 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the ninth transistor T9 in the present circuit unit on the substrate.
  • the third shielding electrode 38 is configured to shield the influence of the data voltage jump on the fourth transistor T4
  • the fourth shielding electrode 39 is configured to shield the influence of the data voltage jump on the ninth transistor T9, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.
  • Forming a fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, and providing a plurality of vias in each circuit unit, as shown in FIG. 10 .
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed ninth connecting electrode to the first region of the first active layer through the via hole.
  • the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of the first active layer (also the first area of the second active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second area of the first active layer (also the first area of the second active layer), and the second via hole V2 is configured to connect a subsequently formed first connecting electrode to the second area of the first active layer (also the first area of the second active layer) through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first area of the fourth active layer, and the third via hole V3 is configured to connect a subsequently formed third connecting electrode to the first area of the fourth active layer through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second area of the fourth active layer (also the second area of the ninth active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second area of the fourth active layer (also the second area of the ninth active layer), and the fourth via hole V4 is configured to connect a subsequently formed second connecting electrode to the second area of the fourth active layer (also the second area of the ninth active layer) through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of the fifth active layer, and the fifth via hole V5 is configured to connect a subsequently formed fourth connecting electrode to the first area of the fifth active layer through the via hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second area of the sixth active layer (also the second area of the seventh active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the second area of the sixth active layer (also the second area of the seventh active layer), and the sixth via hole V6 is configured to connect a subsequently formed fifth connecting electrode to the second area of the sixth active layer (also the second area of the seventh active layer) through the via hole.
  • the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first area of the seventh active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first area of the seventh active layer, and the seventh via hole V7 is configured to connect a subsequently formed second initial signal line to the first area of the seventh active layer through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, and the fourth insulating layer, the first active layer, and the second active layer in the eighth via hole V8 are located within the range of the orthographic projection of the first region of the eighth active layer on the substrate.
  • the third insulating layer and the second insulating layer are etched away to expose the surface of the first region of the eighth active layer, and the eighth via hole V8 is configured to connect the subsequently formed sixth connection electrode to the first region of the eighth active layer through the via hole.
  • the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first opening 75 of the third electrode plate 73 on the substrate, the fourth insulating layer and the third insulating layer in the tenth via hole V10 are etched away to expose the surface of the first electrode plate 71, and the tenth via hole V10 is configured to connect a subsequently formed first connecting electrode to the first electrode plate 71 through the via hole.
  • the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second opening 76 of the fourth electrode plate 74 on the substrate, the fourth insulating layer and the third insulating layer in the eleventh via hole V11 are etched away to expose the surface of the second electrode plate 72, and the eleventh via hole V11 is configured to connect a subsequently formed second connecting electrode to the second electrode plate 72 through the via hole.
  • the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the third electrode plate 73 on the substrate, the fourth insulating layer in the twelfth via hole V12 is etched away to expose the surface of the third electrode plate 73, and the twelfth via hole V12 is configured to connect a subsequently formed second connecting electrode to the third electrode plate 73 through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the fourth electrode plate 74 on the substrate, the fourth insulating layer in the thirteenth via hole V13 is etched away to expose the surface of the fourth electrode plate 74, and the thirteenth via hole V13 is configured to connect a subsequently formed first power connection line to the fourth electrode plate 74 through the via hole.
  • the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the first gate electrode 21 on the substrate, the fourth insulating layer and the third insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the first gate electrode 21, and the fourteenth via hole V14 is configured to connect a subsequently formed fourth scanning signal line to the first gate electrode 21 through the via hole.
  • the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the fourth gate electrode 24 on the substrate, the fourth insulating layer and the third insulating layer in the sixteenth via hole V16 are etched away to expose the surface of the fourth gate electrode 24, and the sixteenth via hole V16 is configured to connect a subsequently formed third scanning signal line to the fourth gate electrode 24 through the via hole.
  • the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the fifth gate electrode 25 on the substrate, the fourth insulating layer and the third insulating layer in the seventeenth via hole V17 are etched away to expose the surface of the fifth gate electrode 25, and the seventeenth via hole V17 is configured to connect the subsequently formed seventh connecting electrode to the fifth gate electrode 25 through the via hole.
  • the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the sixth gate electrode 26 on the substrate, the fourth insulating layer and the third insulating layer in the eighteenth via hole V18 are etched away to expose the surface of the sixth gate electrode 26, and the eighteenth via hole V18 is configured to connect the subsequently formed eighth connecting electrode to the sixth gate electrode 26 through the via hole.
  • the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the ninth gate electrode 29 on the substrate, the fourth insulating layer and the third insulating layer in the nineteenth via hole V19 are etched away to expose the surface of the ninth gate electrode 29, and the nineteenth via hole V19 is configured to connect a subsequently formed second scanning signal line to the ninth gate electrode 29 through the via hole.
  • the orthographic projection of the twentieth via hole V20 on the substrate is located within the range of the orthographic projection of the first light-emitting connection block 31-1 of the first light-emitting signal line 31 on the substrate, the fourth insulating layer in the twentieth via hole V20 is etched away to expose the surface of the first light-emitting connection block 31-1, and the twentieth via hole V20 is configured to connect the subsequently formed seventh connection electrode to the first light-emitting connection block 31-1 through the via hole.
  • the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the second reference connection block 92-1 of the second reference signal line 92 on the substrate, the fourth insulating layer in the twenty-second via V22 is etched away to expose the surface of the second reference connection block 92-1, and the twenty-second via V22 is configured to connect the subsequently formed sixth connection electrode to the second reference connection block 92-1 through the via.
  • the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the first initial connection block 81-1 of the first initial signal line 81 on the substrate, the fourth insulating layer in the twenty-third via V23 is etched away to expose the surface of the first initial connection block 81-1, and the twenty-third via V23 is configured to connect the subsequently formed ninth connection electrode to the first initial connection block 81-1 through the via.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, as shown in FIGS. 11A and 11B , where FIG. 11B is a schematic diagram of the third conductive layer in FIG. 11A .
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer pattern of each circuit unit in the display substrate may include: a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a seventh connection electrode 47, an eighth connection electrode 48, a ninth connection electrode 49, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a fifth scan signal line 65, a first power connection line 68, a second power connection line 69, a second initial signal line 82 and a first reference signal line 91.
  • the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first power connection line 68, the second power connection line 69, the second initial signal line 82 and the first reference signal line 91 may be in the shape of a line whose main part extends along the first direction X.
  • the second scan signal line 62, the third scan signal line 63 and the first reference signal line 91 may be located on one side of the fourth electrode plate 74 in the opposite direction of the second direction Y, and the fourth scan signal line 64, the fifth scan signal line 65 and the second initial signal line 82 may be located on the second direction Y of the third electrode plate 73.
  • the first power connection line 68 may be located in the area where the third electrode plate 73 is located.
  • the second power connection line 69 may be located between the fifth scanning signal line 65 and the second initial signal line 82.
  • the second power connection line 69 may be located on one side of the first power connection line 68 in the second direction Y.
  • the orthographic projection of the second power connection line 69 on the substrate at least partially overlaps with the orthographic projection of the first initial signal line 81 on the substrate, and the second power connection line 69 is configured to be connected to the second power line formed subsequently, forming a low-voltage power grid structure of a mesh-like interconnected structure on the display substrate.
  • the first reference signal line 91 can be located on a side of the fourth electrode plate 74 in the opposite direction of the second direction Y
  • the second scan signal line 62 can be located on a side of the first reference signal line 91 in the opposite direction of the second direction Y
  • the third scan signal line 63 can be located on a side of the second scan signal line 62 in the opposite direction of the second direction Y.
  • the fourth scan signal line 64 can be located on one side of the second direction Y of the third electrode 73
  • the fifth scan signal line 65 can be located on one side of the second direction Y of the fourth scan signal line 64
  • the second power connection line 69 can be located on one side of the second direction Y of the fifth scan signal line 65
  • the second initial signal line 82 can be located on one side of the second direction Y of the second power connection line 69.
  • the second scan signal line 62 is connected to the ninth gate electrode 29 in each circuit unit through the nineteenth via hole V19, thereby realizing that the second scan signal line 62 is connected to the ninth gate electrode 29 of the ninth transistor T9, and the second scan signal line 62 can control the conduction and disconnection of the ninth transistor T9.
  • the second scan signal line 62 may be provided with a second scan connection block 62-1, and the second scan connection block 62-1 may be rectangular.
  • the middle portion of the second scan connection block 62-1 is connected to the second scan signal line 62, the first end of the second scan connection block 62-1 extends toward the first reference signal line 91, and the second end of the second scan connection block 62-1 extends toward the third scan signal line 63.
  • the second scan connection block 62-1 is configured to be connected to the ninth gate electrode 29 in each circuit unit through the nineteenth via hole V19, thereby realizing that the second scan signal line 62 is connected to the ninth gate electrode 29 of the ninth transistor T9, and the second scan signal line 62 can control the conduction and disconnection of the ninth transistor T9.
  • the fifth scan signal line 65 is connected to the second gate electrode 22 in each circuit unit through the fifteenth via hole V15, thereby realizing that the fifth scan signal line 65 is connected to the second gate electrode 22 of the second transistor T2, and the fifth scan signal line 65 can control the second transistor T2. On and off.
  • the fifth scan signal line 65 may be provided with a fifth scan connection block 65-1, and the fifth scan connection block 65-1 may be rectangular.
  • the middle portion of the fifth scan connection block 65-1 is connected to the fifth scan signal line 65, the first end of the fifth scan connection block 65-1 extends toward the second initial signal line 82, and the second end of the fifth scan connection block 65-1 extends toward the first reference signal line 91.
  • the fifth scan connection block 65-1 is configured to be connected to the second gate electrode 22 in each circuit unit through the fifteenth via hole V15, thereby realizing that the fifth scan signal line 65 is connected to the second gate electrode 22 of the second transistor T2, and the fifth scan signal line 65 can control the conduction and disconnection of the second transistor T2.
  • the second scan signal line 62 and the fifth scan signal line 65 can be extended to the frame area and connected to the same gate driving circuit to output the same scan signal, that is, the second scan signal line 62 and the fifth scan signal line 65 output the same second scan signal.
  • the third scan signal line 63 is connected to the fourth gate electrode 24 in each circuit unit through the sixteenth via hole V16, thereby realizing that the third scan signal line 63 is connected to the fourth gate electrode 24 of the fourth transistor T4, and the third scan signal line 63 can control the conduction and disconnection of the fourth transistor T4.
  • a third scan connection block 63-1 is disposed on one side of the third scan signal line 63 close to the first reference signal line 91, a first end of the third scan connection block 63-1 is connected to the third scan signal line 63, and a second end of the third scan connection block 63-1 extends toward the first reference signal line 91.
  • the third scan connection block 63-1 is configured to be connected to the fourth gate electrode 24 in each circuit unit through the sixteenth via hole V16, thereby realizing that the third scan signal line 63 is connected to the fourth gate electrode 24 of the fourth transistor T4, and the third scan signal line 63 can control the on and off of the fourth transistor T4.
  • the fourth scan signal line 64 is connected to the first gate electrode 21 in each circuit unit through the fourteenth via hole V14, thereby realizing that the fourth scan signal line 64 is connected to the first gate electrode 21 of the first transistor T1, and the fourth scan signal line 64 can control the conduction and disconnection of the first transistor T1.
  • the fourth scan signal line 64 may be provided with a fourth scan connection block 64-1, the fourth scan connection block 64-1 may be rectangular. The middle portion of the fourth scan connection block 64-1 is connected to the fourth scan signal line 64, the first end of the fourth scan connection block 64-1 extends toward the second initial signal line 82, and the second end of the fourth scan connection block 64-1 extends toward the first reference signal line 91.
  • the fourth scan connection block 64-1 is configured to be connected to the first gate electrode 21 in each circuit unit through the fourteenth via hole V14, thereby realizing that the fourth scan signal line 64 is connected to the first gate electrode 21 of the first transistor T1, and the fourth scan signal line 64 can control the conduction and disconnection of the first transistor T1.
  • the second initial signal line 82 is connected to the first region of the seventh active layer in each circuit unit through the seventh via V7, thereby realizing that the second initial signal line 82 is connected to the first electrode of the seventh transistor T7, and the second initial signal line 82 can write the second initial signal into the first electrode of the seventh transistor T7.
  • a second initial connection block 82-1 is disposed on one side of the second initial signal line 82 close to the fifth scan signal line 65, a first end of the second initial connection block 82-1 is connected to the second initial signal line 82, and a second end of the second initial connection block 82-1 extends toward the fifth scan signal line 65.
  • the second initial connection block 82-1 is configured to be connected to the first region of the seventh active layer in each circuit unit through the seventh via hole V7, thereby realizing that the second initial signal line 82 is connected to the first electrode of the seventh transistor T7, and the second initial signal line 82 can write the second initial signal into the first electrode of the seventh transistor T7.
  • the second active connection line 20 of the semiconductor layer is directly connected to the first area of the seventh active layer of multiple circuit units in a unit row, and the second initial signal line 82 of the third conductive layer is connected to the first area of the seventh active layer in multiple circuit units in a unit row through a via
  • the second active connection line 20 and the second initial signal line 82 constitute a signal line with a double-layer structure, which can not only ensure that the first areas of multiple seventh active layers in a unit row have the same potential, but also reduce the resistance of the signal line and the voltage drop of the second initial signal, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • a first reference connection block 91-1 is provided on one side of the first reference signal line 91 close to the first power connection line 68, a first end of the first reference connection block 91-1 is connected to the first reference signal line 91, and a second end of the first reference connection block 91-1 extends toward the direction of the first power connection line 68, and the first reference connection block 91-1 is configured to be connected to the first region of the ninth active layer through a ninth via V9 on the one hand, and to be connected to a reference signal connection line formed subsequently on the other hand.
  • the shape of the first active connection line 10 may be a zigzag shape with the main part extending along the first direction X, and the first active connection line 10 and the ninth active layer of the plurality of circuit units may be an integrated structure connected to each other. Since the first region of the ninth active layer is connected to the first reference signal line formed subsequently, the first active connection line 10 may be reused as the first reference signal line extending along the first direction X, which not only ensures that the first regions of the plurality of ninth active layers in a unit row have the same potential, but also reduces the voltage drop of the first reference signal, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the first power connection line 68 is connected to the fourth electrode plate 74 in each circuit unit through the thirteenth via hole V13, thereby realizing that the first power connection line 68 is connected to the fourth electrode plate 74. Since the first power connection line 68 is connected to the first power line formed subsequently, the first power connection line 68 can write the first power signal to the upper electrode plate of the second storage capacitor.
  • a first power connection block 68-1 is provided on one side of the first power connection line 68 away from the second power connection line 69, a first end of the first power connection block 68-1 is connected to the first power connection line 68, and a second end of the first power connection block 68-1 extends in a direction away from the second power connection line 69.
  • the first power connection block 68-1 is configured to be connected to the fourth electrode plate 74 through the thirteenth via V13 on one hand, and is configured to be connected to the first power line formed subsequently on the other hand.
  • the orthographic projection of the first power connection line 68 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 73 on the substrate, and the first power connection line 68 is configured to be connected to the subsequently formed first power line to form a high-voltage power grid structure with a mesh-like interconnected structure on the display substrate.
  • a second power connection block 69-1 is provided on a side of the second power connection line 69 away from the first power connection line 68, a first end of the second power connection block 69-1 is connected to the second power connection line 69, a second end of the second power connection block 69-1 extends in a direction away from the first power connection line 68, and the second power connection block 69-1 is configured to be connected to the subsequent
  • the second power connection block 69-1 may be provided between the first circuit unit and the second circuit unit.
  • the orthographic projection of the second power connection line 69 on the substrate at least partially overlaps with the orthographic projection of the first initial signal line 81 on the substrate, and the second power connection line 69 is configured to be connected to a subsequently formed second power line to form a low-voltage power grid structure with a mesh-like interconnected structure on the display substrate.
  • the first connection electrode 41 enables the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 71 of the first storage capacitor (i.e., the first end of the first storage capacitor) to have the same potential, and the first connection electrode 41 may serve as the first node N1 of the pixel driving circuit.
  • the second connection electrode 42 enables the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third electrode plate 73 of the first storage capacitor (i.e., the second end of the first storage capacitor), and the second electrode plate 72 of the second storage capacitor (i.e., the second end of the second storage capacitor) to have the same potential, and the second connection electrode 42 may serve as the fifth node N5 of the pixel driving circuit.
  • the third connection electrode 43 may be rectangular in shape and may be located between the first reference signal line 91 and the first power connection line 68.
  • the third connection electrode 43 is connected to the first region of the fourth active layer through the third via hole V3.
  • the third connection electrode 43 may serve as a first electrode of the fourth transistor T4 and is configured to be connected to a subsequently formed data signal line.
  • the fourth connection electrode 44 may be rectangular in shape and may be located at The fourth connection electrode 44 is connected to the first region of the fifth active layer through the fifth via hole V5 between the fifth scan signal line 65 and the second initial signal line 82.
  • the fourth connection electrode 44 may serve as a first electrode of the fifth transistor T5 and is configured to be connected to a first power line formed subsequently.
  • the sixth connection electrode 46 may be in the shape of a strip having a main portion extending along the first direction X, and may be located between the fifth scan signal line 65 and the second initial signal line 82. A first end of the sixth connection electrode 46 is connected to the first region of the eighth active layer through an eighth via hole V8, and a second end of the sixth connection electrode 46 is connected to the second reference connection block 92-1 through a twenty-second via hole V22. In an exemplary embodiment, the sixth connection electrode 46 may serve as a first electrode of the eighth transistor T8. Since the second reference connection block 92-1 is connected to the second reference signal line 92, the second reference signal line 92 is connected to the first electrode of the eighth transistor T8. The second reference signal line 92 in the nth unit row may write the second reference signal into the first electrode of the eighth transistor T8 in the n-1th unit row.
  • the eighth connection electrode 48 may be in the shape of a strip having a main portion extending along the first direction X, and may be located between the fifth scanning signal line 65 and the second initial signal line 82.
  • the first end of the eighth connection electrode 48 is connected to the sixth gate electrode 26 through the eighteenth via hole V18, and the second end of the eighth connection electrode 48 is connected to the second light-emitting connection block 32-1 through the twenty-first via hole V21.
  • the ninth connection electrode 49 may be in the shape of a strip having a main portion extending along the first direction X, and may be located between the fifth scan signal line 65 and the second initial signal line 82.
  • a first end of the ninth connection electrode 49 is connected to the first region of the first active layer through a first via hole V1
  • a second end of the ninth connection electrode 49 is connected to the first initial connection block 81-1 through a twenty-third via hole V23. Since the first initial connection block 81-1 is connected to the first initial signal line 81, the first initial signal line 81 is connected to the first electrode of the first transistor T1, and the first initial signal line 81 may write the first initial signal to the first electrode of the first transistor T1.
  • the plurality of via holes of each circuit unit in the display substrate includes at least a thirty-first via hole V31 , a thirty-second via hole V32 , a thirty-third via hole V33 , a thirty-fourth via hole V34 , and a thirty-fifth via hole V35 .
  • the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the third connecting electrode 43 on the substrate, the fifth insulating layer in the thirty-first via hole V31 is removed to expose the surface of the third connecting electrode 43, and the thirty-first via hole V31 is configured to connect a subsequently formed data signal line to the third connecting electrode 43 through the via hole.
  • the orthographic projection of the thirty-second via hole V32 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 44 on the substrate, the fifth insulating layer in the thirty-second via hole V32 is removed to expose the surface of the fourth connecting electrode 44, and the thirty-second via hole V32 is configured to connect a subsequently formed first power line to the fourth connecting electrode 44 through the via hole.
  • the orthographic projection of the thirty-third via hole V33 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 45 on the substrate, the fifth insulating layer in the thirty-third via hole V33 is removed to expose the surface of the fifth connecting electrode 45, and the thirty-third via hole V33 is configured to connect a subsequently formed anode connecting electrode to the fifth connecting electrode 45 through the via hole.
  • the orthographic projection of the thirty-fourth via hole V34 on the substrate is located at the first reference
  • the first reference connection block 91-1 of the reference signal line 91 is within the range of the positive projection on the substrate, the fifth insulating layer in the thirty-fourth via V34 is removed to expose the surface of the first reference connection block 91-1, and the thirty-fourth via V34 is configured to connect the subsequently formed reference signal connection line to the first reference connection block 91-1 through the via.
  • the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the first power connection block 68-1 of the first power connection line 68 on the substrate, the fifth insulating layer in the thirty-fifth via V35 is removed to expose the surface of the first power connection block 68-1, and the thirty-fifth via V35 is configured to connect the subsequently formed first power line to the first power connection block 68-1 through the via.
  • At least one circuit unit may further include a thirty-sixth via V36.
  • the orthographic projection of the thirty-sixth via V36 on the substrate is located within the range of the orthographic projection of the second power connection block 69-1 of the second power connection line 69 on the substrate, the fifth insulating layer in the thirty-sixth via V36 is removed, exposing the surface of the second power connection block 69-1, and the thirty-sixth via V36 is configured to connect the second power line formed subsequently to the second power connection block 69-1 through the via.
  • the thirty-sixth via V36 may be located between the first circuit unit and the second circuit unit.
  • the fourth conductive layer pattern of each circuit unit in the display substrate may include a first power supply line 51 , a data signal line 53 , a reference signal connection line 54 , and an anode connection electrode 55 .
  • the shape of the first power line 51, the data signal line 53 and the reference signal connection line 54 can be a strip shape with the main part extending along the second direction Y, the first power line 51 can be located on one side of the data signal line 53 in the first direction X, and the reference signal connection line 54 can be located on one side of the first power line 51 in the first direction X, that is, the first power line 51 can be located between the data signal line 53 and the reference signal connection line 54.
  • the shape of the first power line 51 can be a zigzag shape with the main part extending along the second direction Y.
  • the first power line 51 is connected to the fourth connection electrode 44 through the thirty-second via hole V32 on the one hand, and is connected to the first power connection block 68-1 through the thirty-fifth via hole V35 on the other hand. Since the fourth connection electrode 44 is connected to the first region of the fifth active layer through the via hole, the first power line 51 writes the first power signal into the first electrode of the fifth transistor T5.
  • the first power connection block 68-1 is connected to the first power connection line 68, the first power connection line 68 extending along the first direction X and the first power line 51 extending along the second direction Y are connected to each other, so that the first power line 51 and the first power connection line 68 form a mesh structure for transmitting the first power signal on the display substrate, which can not only effectively reduce the resistance of the first power line 51 and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the power shielding block 51-1 with a constant voltage can effectively shield the influence of other signals in the pixel driving circuit on the first node N1, thereby preventing other signals (such as data voltage jump) from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.
  • the first power line 51 and the power shielding block 51 - 1 may be an integral structure connected to each other.
  • the orthographic projection of the power shielding block 51 - 1 on the substrate may include the orthographic projection of the first connection electrode 41 on the substrate.
  • a third power connection block 51-2 is provided on one side of the first power line 51 close to the reference signal connection line 54.
  • the third power connection block 51-2 may be in the shape of a bar extending along the first direction X, a first end of the third power connection block 51-2 is connected to the first power line 51, and a second end of the third power connection block 51-2 is extended toward the direction of the reference signal connection line 54 and then connected to the first power connection block 68-1 through the thirty-fifth via hole V35.
  • the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the second connection electrode 42 on the substrate. Since the second connection electrode 42 serves as the fifth node N5 in the pixel driving circuit, the first power line 51 with a constant voltage can effectively shield the influence of other signals in the pixel driving circuit on the fifth node N5, thereby preventing other signals from affecting the potential of the fifth node N5 of the pixel driving circuit and improving the display effect.
  • the first power lines 51 may be designed with unequal widths.
  • the unequal width design of the first power lines 51 may not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the first power lines and the data signal lines.
  • the data signal line 53 may be in the shape of a straight line with a main portion extending along the second direction Y, and the data signal line 53 is connected to the third connection electrode 43 through the thirty-first via hole V31. Since the third connection electrode 43 is connected to the first region of the fourth active layer through the via hole, the data signal line 53 writes the data signal to the first electrode of the fourth transistor T4.
  • a data signal connection block 53-1 is provided on one side of the data signal line 53 close to the first power line 51, a first end of the data signal connection block 53-1 is connected to the data signal line 53, and a second end of the data signal connection block 53-1 extends toward the first power line 51.
  • the shape of the data signal connection block 53-1 may be rectangular.
  • the data signal connection block 53-1 is configured to be connected to the third connection electrode 43 through the thirty-first via hole V31.
  • the reference signal connection line 54 may be in the shape of a straight line with the main body extending along the second direction Y, and the reference signal connection line 54 is connected to the first reference connection block 91-1 through the thirty-fourth via hole V34.
  • the first reference connection block 91-1 is connected to the first reference signal line 91, the first reference signal line 91 with the main body extending along the first direction X and the reference signal connection line 54 with the main body extending along the second direction Y are connected to each other, so that the first reference signal line 91 and the reference signal connection line 54 form a mesh structure for transmitting the first reference signal on the display substrate, which can not only effectively reduce the resistance of the first reference signal line and reduce the voltage drop of the first reference signal, but also effectively improve the uniformity of the first reference signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the reference signal connection line 54 is provided on one side close to the data signal line 53.
  • a reference signal connection block 54-1 is provided, a first end of the reference signal connection block 54-1 is connected to the reference signal connection line 54, and a second end of the reference signal connection block 54-1 extends in the direction of the data signal line 53.
  • the reference signal connection block 54-1 may be rectangular in shape.
  • the reference signal connection block 54-1 is configured to be connected to the first reference connection block 91-1 through the thirty-fourth via hole V34.
  • the shape of the anode connection electrode 55 may be rectangular, and the anode connection electrode 55 is connected to the fifth connection electrode 45 through the thirty-third via hole V33. Since the fifth connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the via hole, the anode connection electrode 55 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In an exemplary embodiment, the anode connection electrode 55 is configured to be connected to the anode formed subsequently, so that the pixel driving circuit can drive the light-emitting device.
  • an orthographic projection of the anode connection electrode 55 on the substrate at least partially overlaps an orthographic projection of the repair line 33 on the substrate.
  • At least one circuit unit may further include a second power line 52.
  • the second power line 52 may be in the shape of a straight line extending along the second direction Y in the main body, and the second power line 52 is connected to the second power connection block 69-1 through the thirty-sixth via hole V36.
  • the second power connection block 69-1 is connected to the second power connection line 69, the second power connection line 69 extending along the first direction X in the main body and the second power line 52 extending along the second direction Y in the main body are connected to each other, so that the second power line 52 and the second power connection line 69 form a mesh structure for transmitting the second power signal on the display substrate, which can not only effectively reduce the resistance of the second power line 52 and reduce the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the second power supply line 52 may be located between the reference signal connection line 54 of the first circuit unit and the data signal line 53 of the second circuit unit.
  • the second power line 52 is provided with a fourth power connection block 52-1, the middle portion of the fourth power connection block 52-1 is connected to the second power line 52, the first end of the fourth power connection block 52-1 extends toward the reference signal connection line 54 of the first circuit unit, and the second end of the fourth power connection block 52-1 extends toward the data signal line 53 of the second circuit unit.
  • the shape of the fourth power connection block 52-1 can be rectangular.
  • the fourth power connection block 52-1 is configured to be connected to the second power connection block 69-1 through the thirty-sixth via V36.
  • the first power connection line 68 of the third conductive layer can be arranged in each unit row, and the first power line 51 of the fourth conductive layer can be arranged in each unit column.
  • Multiple first power lines 51 are respectively connected to multiple first power connection lines 68 to form a mesh structure for transmitting the first power signal.
  • the first reference signal line 91 of the third conductive layer can be arranged in each unit row, and the reference signal connection line 54 of the fourth conductive layer can be arranged in each unit column, and multiple first reference signal lines 91 are respectively connected to multiple reference signal connection lines 54 to form a mesh structure for transmitting the first reference signal.
  • the second power connection line 69 of the third conductive layer can be arranged in each unit row, and the second power line 52 of the fourth conductive layer can be arranged every two unit columns, and multiple second power lines 52 are respectively connected to multiple second power connection lines 69 to form a mesh structure for transmitting the second power signal.
  • the subsequent preparation process may include forming a first flat layer pattern, a plurality of anode vias are arranged on the first flat layer, the orthographic projection of the anode vias on the substrate is located within the range of the orthographic projection of the anode connecting electrode on the substrate, the first flat layer in the anode vias is removed to expose the surface of the anode connecting electrode, and the anode vias are configured to connect the subsequently formed anode to the anode connecting electrode through the vias.
  • the driving circuit layer of this embodiment is prepared on the substrate.
  • a light emitting structure layer and a packaging structure layer can be sequentially prepared on the driving circuit layer, which will not be described in detail here.
  • FIG14 is a schematic diagram of another planar structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driving circuit in three circuit units (a first circuit unit, a second circuit unit, and a third circuit unit) in the display substrate.
  • the main structure of the pixel driving circuit of the exemplary embodiment is substantially the same as that of the aforementioned embodiment, except that the second power connection line 69 of the present embodiment is located between the first power connection line 68 and the fourth scanning signal line 64, and the first shielding electrode 36 and the second power connection line 69 are an integrated structure connected to each other.
  • FIG15 is an enlarged view of the first storage capacitor and the second storage capacitor region in FIG14.
  • at least one circuit unit may further include a first shielding electrode 36, the first shielding electrode 36 is connected to the second power connection line 69, and the orthographic projection of the first shielding electrode 36 on the substrate is aligned with the first transistor
  • the orthographic projection of the node between the two gate electrodes of the second transistor T1 on the substrate at least partially overlaps, and the orthographic projection of the first shielding electrode 36 on the substrate overlaps at least partially with the orthographic projection of the node between the two gate electrodes of the second transistor T2 on the substrate.
  • the first shielding electrode 36 is configured to shield the influence of the data voltage jump on the first transistor T1 and the second transistor T2, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.
  • the first shielding electrode 36 may include a first sub-electrode 36-3 and a second sub-electrode 36-4.
  • the first end of the first sub-electrode 36-3 is connected to the second power connection line 69, and the second end of the first sub-electrode 36-3 extends in a direction away from the second power connection line 69, that is, extends in the opposite direction along the second direction Y.
  • the positive projection of the second end of the first sub-electrode 36-3 on the substrate at least partially overlaps with the positive projection of the node between the two gate electrodes of the first transistor T1 in the present circuit unit on the substrate.
  • the first end of the second sub-electrode 36-4 is connected to the second power connection line 69, and the second end of the second sub-electrode 36-4 extends in a direction away from the second power connection line 69, and the positive projection of the second end of the second sub-electrode 36-4 on the substrate at least partially overlaps with the positive projection of the node between the two gate electrodes of the second transistor T2 in the present circuit unit on the substrate.
  • the middle portion of the first sub-electrode 36-3 is connected to the second power connection line 69, the first end of the first sub-electrode 36-3 extends in the opposite direction of the second direction Y, and the second end of the first sub-electrode 36-3 extends in the second direction Y.
  • the orthographic projections of the first end and the second end of the first sub-electrode 36-3 on the substrate at least partially overlap with the orthographic projection of the node between the two gate electrodes of the first transistor T1 in the present circuit unit on the substrate.
  • the middle portion of the second sub-electrode 36-4 is connected to the second power connection line 69, the first end of the second sub-electrode 36-4 extends in the opposite direction of the second direction Y, and the second end of the second sub-electrode 36-4 extends in the second direction Y.
  • the orthographic projections of the first end and the second end of the second sub-electrode 36-4 on the substrate at least partially overlap with the orthographic projection of the node between the two gate electrodes of the second transistor T2 in the present circuit unit on the substrate.
  • the first shielding electrode 36 and the second power connection line 69 are an integral structure connected to each other.
  • At least one circuit unit may further include a second shielding electrode 37, a third shielding electrode 38 and a fourth shielding electrode 39, and the shapes, positions and connection structures of the second shielding electrode 37, the third shielding electrode 38 and the fourth shielding electrode 39 are substantially the same as those of the aforementioned embodiment.
  • a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer and a fourth insulating layer pattern are sequentially formed.
  • the semiconductor layer pattern may include at least a first active connection line 10, a second active connection line 20, and a first active layer 11 to a ninth active layer 19.
  • the first conductive layer pattern may include at least a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a fifth gate electrode 25, a sixth gate electrode 26, a ninth gate electrode 29, a first scanning signal line 61, a first plate 71 of a first storage capacitor and a second plate 72 of a second storage capacitor.
  • the second conductive layer pattern may include at least a first light emitting signal line 31, a second light emitting signal line 32, a repair line 33, a second shielding electrode 37, a third shielding electrode 38, a fourth shielding electrode 39, a third plate 73 of a first storage capacitor, a fourth plate 74 of a second storage capacitor, a first initial signal line 81 and a second reference signal line 92.
  • the plurality of vias on the fourth insulating layer may include at least a first via V1 to a twenty-third via V23.
  • the position, structure and connection relationship of the above patterns are substantially the same as those of the aforementioned embodiment, except that the second conductive layer of this embodiment is not provided with a first shielding electrode.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIGS. 16A and 16B , where FIG. 16B is a schematic diagram of the third conductive layer in FIG. 16A .
  • the third conductive layer pattern of each circuit unit in the display substrate may include: first to ninth connection electrodes 41 to 49, second scan signal lines 62, third scan signal lines 63, fourth scan signal lines 64, fifth scan signal lines 65, first power connection lines 68, second power connection lines 69, second initial signal lines 82, and first reference signal lines 91.
  • the structure of the third conductive layer of this exemplary embodiment is substantially the same as that of the previous embodiment, except that the second power connection line 69 of this embodiment is located between the first power connection line 68 and the fourth scan signal line 64, and the third conductive layer is provided with a first shielding electrode 36, and the first shielding electrode 36 and the second power connection line 69 are an integral structure connected to each other.
  • the second power connection line 69 may be located at one side of the third electrode plate 73 in the second direction Y and between the first power connection line 68 and the fourth scan signal line 64.
  • a second power connection block 69-1 is provided on one side of the source connection line 69 close to the first power connection line 68, a first end of the second power connection block 69-1 is connected to the second power connection line 69, a second end of the second power connection block 69-1 extends toward a direction close to the first power connection line 68, and the second power connection block 69-1 is configured to be connected to a second power line formed subsequently.
  • the second power connection block 69-1 may be provided between the first circuit unit and the second circuit unit.
  • the third conductive layer of at least one circuit unit may further include a first shielding electrode 36, the first shielding electrode 36 is connected to the second power connection line 69, the orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor T1 on the substrate, and the orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor T2 on the substrate.
  • the first shielding electrode 36 is configured to shield the influence of the data voltage jump on the first transistor T1 and the second transistor T2, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.
  • the first shielding electrode 36 may include a first sub-electrode 36-3 and a second sub-electrode 36-4, and the shapes of the first sub-electrode 36-3 and the second sub-electrode 36-4 may be rectangular.
  • the first end of the first sub-electrode 36-3 is connected to the second power connection line 69, and the second end of the first sub-electrode 36-3 extends in a direction away from the second power connection line 69, that is, extends in the opposite direction along the second direction Y.
  • the positive projection of the second end of the first sub-electrode 36-3 on the substrate overlaps at least partially with the positive projection of the semiconductor layer between the two gate electrodes of the first transistor T1 in the present circuit unit on the substrate.
  • the first end of the second sub-electrode 36-4 is connected to the second power connection line 69, and the second end of the second sub-electrode 36-4 extends in a direction away from the second power connection line 69, and the positive projection of the second end of the second sub-electrode 36-4 on the substrate overlaps at least partially with the positive projection of the semiconductor layer between the two gate electrodes of the second transistor T2 in the present circuit unit on the substrate.
  • the middle portion of the first sub-electrode 36-3 is connected to the second power connection line 69, the first end of the first sub-electrode 36-3 extends in the opposite direction of the second direction Y, and the second end of the first sub-electrode 36-3 extends along the second direction Y.
  • the orthographic projections of the first end and the second end of the first sub-electrode 36-3 on the substrate at least partially overlap with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor T1 in the present circuit unit on the substrate.
  • the middle portion of the second sub-electrode 36-4 is connected to the second power source.
  • the wiring 69 is connected, the first end of the second sub-electrode 36-4 extends in the opposite direction of the second direction Y, and the second end of the second sub-electrode 36-4 extends in the second direction Y.
  • the orthographic projections of the first end and the second end of the second sub-electrode 36-4 on the substrate at least partially overlap with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor T2 in the present circuit unit on the substrate.
  • the first shielding electrode 36 and the second power connection line 69 are an integral structure connected to each other.
  • the subsequent preparation process may include forming a first flat layer pattern, a plurality of anode vias are arranged on the first flat layer, the orthographic projection of the anode vias on the substrate is located within the range of the orthographic projection of the anode connecting electrode on the substrate, the first flat layer in the anode vias is removed to expose the surface of the anode connecting electrode, and the anode vias are configured to connect the subsequently formed anode to the anode connecting electrode through the vias.
  • the driving circuit layer of this embodiment is prepared on the substrate.
  • a light emitting structure layer and a packaging structure layer can be sequentially prepared on the driving circuit layer, which will not be described in detail here.
  • FIG17 is a schematic diagram of another planar structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driving circuit in three circuit units (a first circuit unit, a second circuit unit, and a third circuit unit) in the display substrate.
  • the main structure of the pixel driving circuit of the exemplary embodiment is substantially the same as that of the aforementioned embodiment, except that the first power connection line 68 of the present embodiment is located between the second power connection line 69 and the fourth scanning signal line 64, and the first shielding electrode 36 and the first power connection line 68 are an integrated structure connected to each other.
  • FIG. 18 is an enlarged view of the first storage capacitor and the second storage capacitor region in FIG. 17 .
  • at least one circuit unit may further include a first shielding electrode 36, the first shielding electrode 36 is connected to the first power connection line 68, the orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first transistor T1 on the substrate, and the orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the second transistor T2 on the substrate.
  • the first shielding electrode 36 is configured to shield the influence of the data voltage jump on the first transistor T1 and the second transistor T2, so as to avoid the influence of the data voltage jump on the first transistor T1 and the second transistor T2. Affects the normal operation of the pixel driving circuit and improves the display effect.
  • the first shielding electrode 36 includes a third sub-electrode 36-5 and a fourth sub-electrode 36-6.
  • a first end of the third sub-electrode 36-5 is connected to the first power connection line 68, and a second end of the third sub-electrode 36-5 extends in a direction away from the first power connection line 68, that is, extends in the opposite direction along the second direction Y.
  • the positive projection of the second end of the third sub-electrode 36-5 on the substrate overlaps at least partially with the positive projection of the node between the two gate electrodes of the first transistor T1 in the present circuit unit on the substrate.
  • a first end of the fourth sub-electrode 36-6 is connected to the first power connection line 68, and a second end of the fourth sub-electrode 36-6 extends in a direction away from the first power connection line 68, and a positive projection of the second end of the fourth sub-electrode 36-6 on the substrate overlaps at least partially with the positive projection of the node between the two gate electrodes of the second transistor T2 in the present circuit unit on the substrate.
  • the middle portion of the third sub-electrode 36-5 is connected to the first power connection line 68, the first end of the third sub-electrode 36-5 extends in the opposite direction of the second direction Y, and the second end of the third sub-electrode 36-5 extends in the second direction Y.
  • the orthographic projections of the first end and the second end of the third sub-electrode 36-5 on the substrate at least partially overlap with the orthographic projection of the node between the two gate electrodes of the first transistor T1 in the present circuit unit on the substrate.
  • the middle portion of the fourth sub-electrode 36-6 is connected to the first power connection line 68, the first end of the fourth sub-electrode 36-6 extends in the opposite direction of the second direction Y, and the second end of the fourth sub-electrode 36-6 extends in the second direction Y.
  • the orthographic projections of the first end and the second end of the fourth sub-electrode 36-6 on the substrate at least partially overlap with the orthographic projection of the node between the two gate electrodes of the second transistor T2 in the present circuit unit on the substrate.
  • the first shielding electrode 36 and the first power connection line 68 are an integral structure connected to each other.
  • At least one circuit unit may further include a second shielding electrode 37, a third shielding electrode 38 and a fourth shielding electrode 39, and the shapes, positions and connection structures of the second shielding electrode 37, the third shielding electrode 38 and the fourth shielding electrode 39 are substantially the same as those of the aforementioned embodiment.
  • the preparation process of the display substrate may include the following operations.
  • a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, and a fourth insulating layer pattern are sequentially formed.
  • the semiconductor layer pattern may include at least a first active connection line 10, a second active connection line 20, and a first active layer 11 to a ninth active layer 19.
  • the first conductive layer pattern may include at least a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a fifth gate electrode 25, a sixth gate electrode 26, a ninth gate electrode 29, a first scanning signal line 61, a first plate 71 of a first storage capacitor, and a second plate 72 of a second storage capacitor.
  • the second conductive layer pattern may include at least a first light emitting signal line 31, a second light emitting signal line 32, a repair line 33, a second shielding electrode 37, a third shielding electrode 38, a fourth shielding electrode 39, a third plate 73 of a first storage capacitor, a fourth plate 74 of a second storage capacitor, a first initial signal line 81, and a second reference signal line 92.
  • the plurality of vias on the fourth insulating layer may include at least a first via V1 to a twenty-third via V23.
  • the position, structure and connection relationship of the above pattern are basically the same as those of the previous embodiment, except that the second conductive layer of this embodiment does not have a first shielding electrode, and the thirteenth via V13 is configured to connect the subsequently formed connecting electrode to the fourth electrode plate 74 through the via.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIGS. 19A and 19B , where FIG. 19B is a schematic diagram of the third conductive layer in FIG. 19A .
  • the third conductive layer pattern of each circuit unit in the display substrate may include: a first connecting electrode 41 to a tenth connecting electrode 50, a second scanning signal line 62, a third scanning signal line 63, a fourth scanning signal line 64, a fifth scanning signal line 65, a first power connection line 68, a second power connection line 69, a second initial signal line 82 and a first reference signal line 91. Except for the tenth connecting electrode 50, the first power connection line 68 and the second power connection line 69, the shape, position and connection structure relationship of the above structures are basically the same as those in the previous embodiment, and will not be repeated here.
  • the first power connection line 68 is located between the second power connection line 69 and the fourth scan signal line 64 , and the first shielding electrode 36 and the first power connection line 68 are an integral structure connected to each other.
  • the first power connection line 68 may be located at one side of the third electrode plate 73 in the second direction Y.
  • the second power connection line 69 may be located between the first power connection line 68 and the first reference signal line 91 .
  • each circuit unit may further include a first shielding electrode 36, the first shielding electrode 36 is connected to the first power connection line 68, the orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor T1 on the substrate, and the orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor T2 on the substrate.
  • the first shielding electrode 36 is configured to shield the influence of the data voltage jump on the first transistor T1 and the second transistor T2, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.
  • the first shielding electrode 36 includes a third sub-electrode 36-5 and a fourth sub-electrode 36-6, and the shapes of the third sub-electrode 36-5 and the fourth sub-electrode 36-6 may be rectangular.
  • the first end of the third sub-electrode 36-5 is connected to the first power connection line 68, and the second end of the third sub-electrode 36-5 extends in a direction away from the first power connection line 68, that is, extends in the opposite direction along the second direction Y.
  • the positive projection of the second end of the third sub-electrode 36-5 on the substrate overlaps at least partially with the positive projection of the semiconductor layer between the two gate electrodes of the first transistor T1 in the present circuit unit on the substrate.
  • the first end of the fourth sub-electrode 36-6 is connected to the first power connection line 68, and the second end of the fourth sub-electrode 36-6 extends in a direction away from the first power connection line 68, and the positive projection of the second end of the fourth sub-electrode 36-6 on the substrate overlaps at least partially with the positive projection of the semiconductor layer between the two gate electrodes of the second transistor T2 in the present circuit unit on the substrate.
  • the middle portion of the third sub-electrode 36-5 is connected to the first power connection line 68, the first end of the third sub-electrode 36-5 extends in the opposite direction of the second direction Y, and the second end of the third sub-electrode 36-5 extends along the second direction Y.
  • the orthographic projections of the first end and the second end of the third sub-electrode 36-5 on the substrate at least partially overlap with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor T1 in the present circuit unit on the substrate.
  • the middle portion of the fourth sub-electrode 36-6 is connected to the first power connection line 68, the first end of the fourth sub-electrode 36-6 extends in the opposite direction of the second direction Y, and the second end of the fourth sub-electrode 36-6 extends in the second direction Y.
  • the orthographic projections of the first end and the second end of the fourth sub-electrode 36-6 on the substrate at least partially overlap with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor T2 in the present circuit unit on the substrate.
  • the first shielding electrode 36 and the first power connection line 68 are an integral structure connected to each other.
  • the tenth connection electrode 50 may be rectangular in shape and may be located between the first reference signal line 91 and the second power connection line 69.
  • the tenth connection electrode 50 is connected to the fourth electrode plate 74 through the thirteenth via hole V13.
  • the tenth connection electrode 50 is configured to be connected to a first power line formed subsequently.
  • Forming a fifth insulating layer pattern may include: depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer, and providing a plurality of vias in each circuit unit, as shown in FIG. 20 .
  • the multiple vias of each circuit unit in the display substrate include at least: the thirty-first via V31 to the thirty-fifth via V35, and the thirty-seventh via V37.
  • the positions, structures, and connection relationships of the thirty-first via V31 to the thirty-fourth via V34 are substantially the same as those in the aforementioned embodiments and will not be elaborated here.
  • the orthographic projection of the thirty-fifth via hole V35 on the substrate is located within the range of the orthographic projection of the tenth connecting electrode 50 on the substrate, the fifth insulating layer in the thirty-fifth via hole V35 is removed to expose the surface of the tenth connecting electrode 50, and the thirty-fifth via hole V35 is configured to connect a subsequently formed first power line to the tenth connecting electrode 50 through the via hole.
  • the orthographic projection of the thirty-seventh via hole V37 on the substrate may be located within the range of the orthographic projection of the third sub-electrode 36-5 on the substrate, the fifth insulating layer in the thirty-seventh via hole V37 is removed, exposing the surface of the third sub-electrode 36-5, and the thirty-seventh via hole V37 is configured to allow the first power line formed subsequently to be connected to the first power connection line 68 through the via hole.
  • the first power connection line 68 extending along the first direction X of the main part and the first power line 51 extending along the second direction Y of the main part are connected to each other, so that the first power line 51 and the first power connection line 68 form a mesh structure for transmitting the first power signal on the display substrate, which can not only effectively reduce the resistance of the first power line 51 and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • At least one circuit unit may further include a thirty-sixth via hole V36.
  • the orthographic projection of the thirty-sixth via hole V36 on the substrate is within the range of the orthographic projection of the second power connection block 69-1 of the second power connection line 69 on the substrate.
  • the insulating layer is removed to expose the surface of the second power connection block 69-1, and the thirty-sixth via V36 is configured to connect the second power line formed subsequently to the second power connection block 69-1 through the via.
  • the thirty-sixth via V36 may be located between the first circuit unit and the second circuit unit.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer, as shown in FIGS. 21A and 21B , where FIG. 21B is a schematic diagram of the fourth conductive layer in FIG. 21A .
  • the fourth conductive layer pattern of each circuit unit in the display substrate may include: a first power line 51, a data signal line 53, a reference signal connection line 54 and an anode connection electrode 55.
  • the positions, structures and connection relationships of the data signal line 53, the reference signal connection line 54 and the anode connection electrode 55 are substantially the same as those in the previous embodiment and will not be described in detail here.
  • a power shielding block 51-1 is provided on one side of the first power line 51 close to the reference signal connection line 54, a first end of the power shielding block 51-1 is connected to the first power line 51, and a second end of the power shielding block 51-1 extends in the direction of the reference signal connection line 54.
  • the shape of the power shielding block 51-1 may be rectangular, and the positive projection of the power shielding block 51-1 on the substrate at least partially overlaps with the positive projection of the first connection electrode 41 on the substrate.
  • the power shielding block 51-1 with a constant voltage can effectively shield the influence of other signals in the pixel driving circuit on the first node N1, thereby preventing other signals (such as data voltage jump) from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.
  • the first power line 51 and the power shielding block 51 - 1 may be an integral structure connected to each other.
  • the orthographic projection of the power shielding block 51 - 1 on the substrate may include the orthographic projection of the first connection electrode 41 on the substrate.
  • a third power connection block 51-2 is provided on one side of the first power line 51 close to the reference signal connection line 54.
  • the third power connection block 51-2 may be in the shape of a bar extending along the first direction X, a first end of the third power connection block 51-2 is connected to the first power line 51, and a second end of the third power connection block 51-2 extends toward the direction of the reference signal connection line 54, and then passes through the first power line 51.
  • the thirty-fifth via hole V35 is connected to the tenth connection electrode 50 .
  • the first power line 51 and the third power connection block 51 - 2 may be an integral structure connected to each other.
  • the fourth conductive layer pattern of each circuit unit in the display substrate may further include a fifth power connection block 51-3.
  • the first end of the fifth power connection block 51-3 is connected to the first power line 51, and the second end of the fifth power connection block 51-3 extends toward the data signal line 53 in the circuit unit.
  • the shape of the fifth power connection block 51-3 may be rectangular.
  • the fifth power connection block 51-3 is connected to the first power connection line 68 through the thirty-seventh via V37.
  • the first power connection line 68 extending along the first direction X of the main part and the first power line 51 extending along the second direction Y of the main part are connected to each other, so that the first power line 51 and the first power connection line 68 form a mesh structure for transmitting the first power signal on the display substrate, which can not only effectively reduce the resistance of the first power line 51 and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the subsequent preparation process may include forming a first flat layer pattern, a plurality of anode vias are arranged on the first flat layer, the orthographic projection of the anode vias on the substrate is located within the range of the orthographic projection of the anode connecting electrode on the substrate, the first flat layer in the anode vias is removed to expose the surface of the anode connecting electrode, and the anode vias are configured to connect the subsequently formed anode to the anode connecting electrode through the vias.
  • the driving circuit layer of this embodiment is prepared on the substrate.
  • a light emitting structure layer and a packaging structure layer can be sequentially prepared on the driving circuit layer, which will not be described in detail here.
  • the present embodiment of the disclosure sets a first power connection line, a second power connection line, a first power line and a second power line, and the first power line and the first power connection line are connected to each other, so that the first power line and the first power connection line form a mesh structure for transmitting the first power signal on the display substrate, and the second power line and the second power connection line are connected to each other, so that the second power line and the second power connection line form a mesh structure for transmitting the second power signal on the display substrate, which can not only effectively reduce the resistance of the first power line and the second power line, reduce the voltage drop of the first power signal and the second power signal, but also effectively improve the uniformity of the first power signal and the second power signal in the display substrate, thereby improving the display quality.
  • the disclosed embodiment can effectively shield the node between the two gate electrodes of the transistor with a dual-gate structure, ensure the normal operation of the pixel driving circuit, and improve the display effect.
  • the embodiment of the present disclosure sets a first reference signal line and a reference signal connecting line, and the first reference signal line and the reference signal connecting line are connected to each other, so that the first reference signal line and the reference signal connecting line form a mesh structure for transmitting the first reference signal on the display substrate.
  • This can not only effectively reduce the resistance of the first reference signal line and reduce the voltage drop of the first reference signal, but also effectively improve the uniformity of the first reference signal in the display substrate, effectively improve the display uniformity, and improve the display quality.
  • the disclosed embodiment forms a double-layer signal line by setting a first active connection line of the semiconductor layer and a first reference signal line of the third conductive layer, which can effectively reduce the voltage drop of the reference signal, help improve the uniformity of the panel, avoid poor display of the display substrate, and ensure the display effect of the display substrate.
  • the embodiment of the present disclosure can shield the influence of data voltage jump on the first transistor T1, the second transistor T2, the fourth transistor T4, the ninth transistor T9 and the key nodes by setting the first shielding electrode, the second shielding electrode, the third shielding electrode and the fourth shielding electrode, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.
  • the disclosed embodiment shields the first node N1 and the fifth node N5 of the pixel driving circuit by setting a first power line and a power shielding block, thereby effectively preventing other signals from affecting the potentials of the first node N1 and the fifth node N5 of the pixel driving circuit and improving the display effect.
  • the second power connection line is overlapped with the first initial signal line, so that the wiring layout is more reasonable.
  • the preparation process disclosed in the present invention is well compatible with the existing preparation process, and the process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.
  • the substrate may be a flexible substrate or a rigid substrate.
  • the rigid substrate may be, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the flexible substrate may include a first flexible material stacked
  • the material layer, the first inorganic material layer, the semiconductor layer, the second flexible material layer and the second inorganic material layer, the material of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET) or a surface-treated polymer soft film and the like
  • the material of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx) or silicon oxide (SiOx) and the like, which are used to improve the water and oxygen resistance of the substrate
  • the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer.
  • the first insulating layer is called a buffer layer
  • the second insulating layer and the third insulating layer are called gate insulating (GI) layers
  • the fourth insulating layer is called an interlayer insulating (ILD) layer
  • the fifth insulating layer is called a passivation (PVX) layer.
  • the first planar layer can be made of an organic material, such as a resin, etc.
  • the active layer can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene and other materials, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide material
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • sexithiophene or polythiophene and other materials that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.
  • a pixel driving circuit such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.
  • the present disclosure also provides a display device, comprising a display substrate of any of the above embodiments.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.

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Abstract

一种显示基板及显示装置。显示基板包括多个电路单元、第一电源连接线(68)、第二电源连接线(69)、第一电源线(51)和第二电源线(52)，电路单元包括像素驱动电路，第一电源线(51)与像素驱动电路连接，第一电源线(51)与第一电源连接线(68)连接，第二电源线(52)与第二电源连接线(69)连接；像素驱动电路包括第一屏蔽电极和至少一个双栅结构的晶体管，第一屏蔽电极在基底上的正投影与双栅结构的晶体管两个栅电极之间的节点在基底上的正投影至少部分交叠；第一屏蔽电极与第一电源连接线(68)或者第二电源连接线(69)连接。

Description

显示基板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，所述显示基板包括设置在基底上的驱动电路层以及设置在所述驱动电路层远离所述基底一侧的发光结构层，所述驱动电路层至少包括多个电路单元、沿着第一方向延伸的至少一条第一电源连接线和至少一条第二电源连接线、沿着第二方向延伸的至少一条第一电源线和至少一条第二电源线，至少一个电路单元包括像素驱动电路，所述第一电源线与所述像素驱动电路连接，所述第一电源线被配置为向所述像素驱动电路持续提供高电平信号，所述发光结构层至少包括多个发光单元，至少一个发光单元包括阴极，所述第二电源线与所述阴极连接，所述第二电源线被配置为向所述阴极持续提供低电平信号；所述第一电源线与所述第一电源连接线连接，形成传输第一电源信号的网状结构，所述第二电源线与所述第二电源连接线连接，形成传输第二电源信号的网状结构，所述第一方向与 所述第二方向交叉；
所述像素驱动电路包括第一屏蔽电极和至少一个双栅结构的晶体管，所述第一屏蔽电极在所述基底上的正投影与所述双栅结构的晶体管两个栅电极之间的节点在所述基底上的正投影至少部分交叠；所述第一屏蔽电极与所述第一电源连接线相连接；或者，所述第一屏蔽电极与所述第二电源连接线相连接。
在一些示例性实施例中，所述至少一个双栅结构的晶体管包括第一初始化晶体管和补偿晶体管，所述第一初始化晶体管的第一极与第一初始信号线连接，所述补偿晶体管的第一极与所述第一初始化晶体管的第二极连接，所述第一屏蔽电极在所述基底上的正投影与所述第一初始化晶体管两个栅电极之间的节点在所述基底上的正投影至少部分交叠，所述第一屏蔽电极在所述基底上的正投影与所述补偿晶体管两个栅电极之间的节点在所述基底上的正投影至少部分交叠。
在一些示例性实施例中，所述第一屏蔽电极与所述第二电源连接线为相互连接的一体结构。
在一些示例性实施例中，所述第二电源连接线位于所述第一电源连接线靠近所述第一初始化晶体管和补偿晶体管的一侧。
在一些示例性实施例中，所述第一屏蔽电极至少包括第一子电极和第二子电极，所述第一子电极的第一端与所述第二电源连接线连接，所述第一子电极的第二端向着靠近所述第一电源连接线的方向延伸，所述第一子电极的第二端在所述基底上的正投影与所述第一初始化晶体管两个栅电极之间的节点在基底上的正投影至少部分交叠；所述第二子电极的第一端与所述第二电源连接线连接，所述第二子电极的第二端向着靠近所述第一电源连接线的方向延伸，所述第二子电极的第二端在所述基底上的正投影与所述补偿晶体管两个栅电极之间的节点在所述基底上的正投影至少部分交叠。
在一些示例性实施例中，所述第一屏蔽电极与所述第一电源连接线为相互连接的一体结构。
在一些示例性实施例中，所述第一电源连接线位于所述第二电源连接线 靠近所述第一初始化晶体管和补偿晶体管的一侧。
在一些示例性实施例中，所述第一屏蔽电极至少包括第三子电极和第四子电极，所述第三子电极的第一端与所述第一电源连接线连接，所述第三子电极的第二端向着靠近所述第二电源连接线的方向延伸，所述第三子电极的第二端在所述基底上的正投影与所述第一初始化晶体管两个栅电极之间的节点在基底上的正投影至少部分交叠；所述第四子电极的第一端与所述第一电源连接线连接，所述第四子电极的第二端向着靠近所述第二电源连接线的方向延伸，所述第四子电极的第二端在所述基底上的正投影与所述补偿晶体管两个栅电极之间的节点在所述基底上的正投影至少部分交叠。
在一些示例性实施例中，所述像素驱动电路还包括第一存储电容和第二存储电容，所述第一存储电容至少包括第一极板和第三极板，所述第一极板在所述基底上的正投影与所述第三极板在所述基底上的正投影至少部分交叠；所述第二存储电容至少包括第二极板和第四极板，所述第二极板在所述基底上的正投影与所述第四极板在所述基底上的正投影至少部分交叠；所述第二极板与所述第三极板连接，所述第四极板与所述第一电源连接线连接，所述第一屏蔽电极与所述第四极板连接。
在一些示例性实施例中，所述第一屏蔽电极与所述第四极板为相互连接的一体结构。
在一些示例性实施例中，所述第一屏蔽电极包括第一延伸段和第一屏蔽段；所述第一延伸段的形状为沿着所述第二方向延伸的条形状，所述第一屏蔽段的形状为沿着所述第一方向延伸的条形状；所述第一延伸段的第一端与所述第四极板连接，所述第一延伸段的第二端与所述第一屏蔽段连接；所述第一屏蔽段包括第一屏蔽端和第二屏蔽端，所述第一屏蔽端在所述基底上的正投影与本电路单元中所述第一初始化晶体管两个栅电极之间的节点在基底上的正投影至少部分交叠，所述第二屏蔽端在所述基底上的正投影与相邻所述电路单元中的所述补偿晶体管两个栅电极之间的节点在所述基底上的正投影至少部分交叠。
在一些示例性实施例中，所述至少一个双栅结构的晶体管还包括数据写入晶体管和第一参考晶体管，所述数据写入晶体管的第一极与数据信号线连 接，所述第一参考晶体管的第一极与第一参考信号线连接，所述数据写入晶体管的第二极和所述第一参考晶体管的第二极连接；
所述像素驱动电路还包括第二屏蔽电极，所述第二屏蔽电极设置在所述数据写入晶体管的的第一极与所述数据写入晶体管的第二极之间。
在一些示例性实施例中，所述至少一个双栅结构的晶体管还包括数据写入晶体管和第一参考晶体管，所述数据写入晶体管的第一极与数据信号线连接，所述第一参考晶体管的第一极与第一参考信号线连接，所述数据写入晶体管的第二极和所述第一参考晶体管的第二极连接；
所述像素驱动电路还包括第三屏蔽电极和第四屏蔽电极，所述第三屏蔽电极在所述基底上的正投影与所述数据写入晶体管两个栅电极之间的节点在基底上的正投影至少部分交叠，所述第四屏蔽电极在所述基底上的正投影与所述第一参考晶体管两个栅电极之间的节点在基底上的正投影至少部分交叠。
在一些示例性实施例中，所述第二电源连接线在所述基底的正投影与所述第一初始信号线在所述基底的正投影至少部分交叠。
在一些示例性实施例中，在垂直于显示基板的平面上，所述驱动电路层包括多个导电层；所述第一电源线和所述第一电源连接线设置在不同的导电层中，所述第一电源线与所述第一电源连接线通过过孔连接；所述第二电源线和所述第二电源连接线设置在不同的导电层中，所述第二电源线与所述第二电源连接线通过过孔连接。
在一些示例性实施例中，所述第一电源连接线和所述第二电源连接线同层设置，所述第一电源线和所述第二电源线同层设置。
在一些示例性实施例中，所述多个导电层至少包括沿着远离所述基底方向依次设置的第一导电层、第二导电层、第三导电层和第四导电层；所述第一电源连接线和所述第二电源连接线设置在所述第三导电层中，所述第一电源线和所述第二电源线设置在所述第四导电层中。
在一些示例性实施例中，在垂直于显示基板的平面上，所述驱动电路层包括多个导电层；所述多个导电层至少包括沿着远离所述基底方向依次设置 的第一导电层、第二导电层、第三导电层；所述第一屏蔽电极设置在所述第二导电层中，或者所述第一屏蔽电极设置在所述第三导电层中。
在一些示例性实施例中，所述像素驱动电路还包括第一存储电容和第二存储电容，所述第一存储电容至少包括第一极板和第三极板，所述第一极板在所述基底上的正投影与所述第三极板在所述基底上的正投影至少部分交叠；所述第二存储电容至少包括第二极板和第四极板，所述第二极板在所述基底上的正投影与所述第四极板在所述基底上的正投影至少部分交叠；所述第一极板和所述第二极板设置在所述第一导电层中，所述第三极板和所述第四极板设置在所述第二导电层中。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板的剖面结构示意图；
图4为本公开示例性实施例一种像素驱动电路的等效电路图；
图5为本公开示例性实施例一种显示基板平面结构示意图；
图6为图5中第一存储电容和第二存储电容区域的放大图；
图7为本公开一种显示基板形成半导体层图案后的示意图；
图8A和图8B为本公开一种显示基板形成第一导电层图案后的示意图；
图9A和图9B为本公开一种显示基板形成第二导电层图案后的示意图；
图10为本公开一种显示基板形成第四绝缘层图案后的示意图；
图11A和图11B为本公开一种显示基板形成第三导电层图案后的示意图；
图12为本公开一种显示基板形成第五绝缘层图案后的示意图；
图13A和13B为本公开一种显示基板形成第四导电层图案后的示意图；
图14为本公开示例性实施例另一种显示基板平面结构示意图；
图15为图14中第一存储电容和第二存储电容区域的放大图；
图16A和图16B为本公开另一种显示基板形成第三导电层图案后的示意图；
图17为本公开示例性实施例又一种显示基板平面结构示意图；
图18为图17中第一存储电容和第二存储电容区域的放大图；
图19A和图19B为本公开又一种显示基板形成第三导电层图案后的示意图；
图20为本公开又一种显示基板形成第五绝缘层图案后的示意图；
图21A和21B为本公开又一种显示基板形成第四导电层图案后的示意图。
附图标记
10—第一有源连接线；  11—第一有源层；      12—第二有源层；
13—第三有源层；      14—第四有源层；      15—第五有源层；
16—第六有源层；      17—第七有源层；      18—第八有源层；
19—第九有源层；      20—第二有源连接线；  21—第一栅电极；
22—第二栅电极；      24—第四栅电极；      25—第五栅电极；
26—第六栅电极；      29—第九栅电极；      31—第一发光信号线；
32—第二发光信号线；  33—修复线；          36—第一屏蔽电极；
37—第二屏蔽电极；    38—第三屏蔽电极；    39—第四屏蔽电极；
41—第一连接电极；    42—第二连接电极；    43—第三连接电极；
44—第四连接电极；    45—第五连接电极；    46—第六连接电极；
47—第七连接电极；    48—第八连接电极；    49—第九连接电极；
50—第十连接电极；    51—第一电源线；      52—第二电源线；
53—数据信号线；      54—参考信号连接线；  55—阳极连接电极；
61—第一扫描信号线；  62—第二扫描信号线；  63—第三扫描信号线；
64—第四扫描信号线；  65—第五扫描信号线；  68—第一电源连接线；
69—第二电源连接线；  71—第一极板；        72—第二极板；
73—第三极板；        74—第四极板；        75—第一开口；
76—第二开口；        81—第一初始信号线；  82—第二初始信号线；
91—第一参考信号线；  92—第二参考信号线；  101—基底；
102—驱动电路层；     103—发光结构层；     104—封装结构层。
详述
下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系 根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和发光单元，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、发光信号线和数据信号线连接，发光单元可以包括发光器件，发光器件与电路单元的像素驱动电路连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号 顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。在示例性实施方式中，像素阵列可以设置在显示基板上。
图2为一种显示基板的平面结构示意图。在示例性实施方式中，显示基板可以包括显示区域和位于显示区域周边的边框区域。如图2所示，显示基板的显示区域可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3。每个子像素可以包括电路单元和发光单元，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。发光单元可以至少包括发光器件，发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括四个子像素，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
图3为一种显示基板的剖面结构示意图，示意了显示基板中三个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板的显示区域可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基 底。刚性基底可以为但不限于玻璃、石英中的一种或多种，柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，驱动电路层102可以包括多个电路单元，电路单元可以至少包括像素驱动电路，像素驱动电路可以包括多个晶体管和存储电容。发光结构层103可以包括多个发光单元，发光单元可以至少包括发光器件，发光器件可以包括阳极、有机发光层和阴极，阳极与像素驱动电路连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。
在示例性实施方式中，封装结构层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层可以包括发光层(EML)以及如下任意一层或多层：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。
本公开示例性实施例提供了一种显示基板，显示基板包括设置在基底上的驱动电路层以及设置在所述驱动电路层远离所述基底一侧的发光结构层，所述驱动电路层至少包括多个电路单元、沿着第一方向延伸的至少一条第一电源连接线和至少一条第二电源连接线、沿着第二方向延伸的至少一条第一电源线和至少一条第二电源线，至少一个电路单元包括像素驱动电路，所述第一电源线与所述像素驱动电路连接，所述第一电源线被配置为向所述像素驱动电路持续提供高电平信号，所述发光结构层至少包括多个发光单元，至少一个发光单元包括阴极，所述第二电源线与所述阴极连接，所述第二电源线被配置为向所述阴极持续提供低电平信号；所述第一电源线与所述第一电源连接线连接，形成传输第一电源信号的网状结构，所述第二电源线与所述第二电源连接线连接，形成传输第二电源信号的网状结构，所述第一方向与 所述第二方向交叉；
所述像素驱动电路包括第一屏蔽电极和至少一个双栅结构的晶体管，所述第一屏蔽电极在所述基底上的正投影与所述双栅结构的晶体管两个栅电极之间的节点在所述基底上的正投影至少部分交叠；所述第一屏蔽电极与所述第一电源连接线相连接；或者，所述第一屏蔽电极与所述第二电源连接线相连接。
在示例性实施方式中，所述至少一个双栅结构的晶体管包括第一初始化晶体管和补偿晶体管，所述第一初始化晶体管的第一极与第一初始信号线连接，所述补偿晶体管的第一极与所述第一初始化晶体管的第二极连接，所述第一屏蔽电极在所述基底上的正投影与所述第一初始化晶体管两个栅电极之间的节点在所述基底上的正投影至少部分交叠，所述第一屏蔽电极在所述基底上的正投影与所述补偿晶体管两个栅电极之间的节点在所述基底上的正投影至少部分交叠。
在示例性实施方式中，所述第一屏蔽电极与所述第一电源连接线为相互连接的一体结构。
在示例性实施方式中，所述第一屏蔽电极与所述第二电源连接线为相互连接的一体结构。
在示例性实施方式中，所述像素驱动电路还包括第一存储电容和第二存储电容，所述第一存储电容至少包括第一极板和第三极板，所述第一极板在所述基底上的正投影与所述第三极板在所述基底上的正投影至少部分交叠；所述第二存储电容至少包括第二极板和第四极板，所述第二极板在所述基底上的正投影与所述第四极板在所述基底上的正投影至少部分交叠；所述第二极板与所述第三极板连接，所述第四极板与所述第一电源连接线连接，所述第一屏蔽电极与所述第四极板连接。
在示例性实施方式中，所述第一屏蔽电极与所述第四极板为相互连接的一体结构。
下面通过一些示例性实施例对本公开显示基板进行举例说明。
图4为本公开示例性实施例一种像素驱动电路的等效电路图。在示例性 实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C、8T1C或9T2C结构。如图4所示，本公开示例性实施例的像素驱动电路可以为9T2C结构，可以包括9个晶体管(第一晶体管T1至第九晶体管T9)和2个存储电容(第一存储电容C1和第二存储电容C2)，像素驱动电路分别与12条信号线(第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、第四扫描信号线S4、第一发光信号线EM1、第二发光信号线EM2、第一初始信号线INIT1、第二初始信号线INIT2、第一参考信号线REF1、第二参考信号线REF2、数据信号线DATA和第一电源线VDD)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2、第三节点N3、第四节点N4和第五节点N5。其中，第一节点N1分别与第一晶体管的第二极、第二晶体管T2的第一极、第三晶体管T3的栅电极和第一存储电容C1的第一端连接。第二节点N2分别与第三晶体管T3的第一极、第八晶体管T8的第二极和第五晶体管T5的第二极连接。第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。第四节点N4分别与第六晶体管T6的第二极和第七晶体管T7的第二极连接。第五节点N5分别与第四晶体管T4的第二极、第九晶体管T9的第二极、第一存储电容C1的第二端和第二存储电容C2的第二端连接。
在示例性实施方式中，第一存储电容C1的第一端(下极板)与第一节点N1连接，第一存储电容C1的第二端(上极板)与第五节点N5连接。第二存储电容C2的第一端(上极板)与第一电源线VDD连接，第二存储电容C2的第二端(下极板)与第五节点N5连接。
在示例性实施方式中，第一晶体管T1的栅电极与第四扫描信号线S4连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第一节点N1连接。当导通信号施加到第四扫描信号线S4时，第一晶体管T1将第一初始电压传输到第三晶体管T3的栅电极和第一存储电容C1的第一端，使第一存储电容C1中累积的电荷释放，实现初始化。
在示例性实施方式中，第二晶体管T2的栅电极与第二扫描信号线S2连 接，第二晶体管T2的第一极与第一节点N1连接，第二晶体管T2的第二极与第三节点N3连接。当导通信号施加到第二扫描信号线S2时，第二晶体管T2使第三晶体管T3的栅电极与第二极连接。
在示例性实施方式中，第三晶体管T3的栅电极与第一节点N1连接，即第三晶体管T3的栅电极与第一存储电容C1的第一端连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其栅电极与第一极之间的电位差来确定驱动电流的大小。
在示例性实施方式中，第四晶体管T4的栅电极与第三扫描信号线S3连接，第四晶体管T4的第一极与数据信号线DATA连接，第四晶体管T4的第二极与第五节点N5连接。当导通信号施加到第三扫描信号线S3时，第四晶体管T4使数据信号线DATA的数据电压输入到第一存储电容C1的第二端和第二存储电容C2的第二端。
在示例性实施方式中，第五晶体管T5的栅电极与第一发光信号线EM1连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接。第六晶体管T6的栅电极与第二发光信号线EM2连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与第四节点N4连接。当导通信号施加到第一发光信号线EM1和第二发光信号线EM2时，第五晶体管T5和第六晶体管T6在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件EL发光。
在示例性实施方式中，第七晶体管T7的栅电极与第一扫描信号线S1连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7的第二极与第四节点N4连接。当导通信号施加到第一扫描信号线S1时，第七晶体管T7将第二初始电压传输到发光器件EL的第一极，使发光器件EL的第一极中累积的电荷释放，实现初始化。
在示例性实施方式中，第八晶体管T8的栅电极与第一扫描信号线S1连接，第八晶体管T8的第一极与第二参考信号线REF2连接，第八晶体管T8的第二极与第二节点N2连接。当导通信号施加到第一扫描信号线S1时，第八晶体管T8将第二参考信号传输到第二节点N2。
在示例性实施方式中，第九晶体管T9的栅电极与第二扫描信号线S2连接，第九晶体管T9的第一极与第一参考信号线REF1连接，第九晶体管T9的第二极与第五节点N5连接。当导通信号施加到第二扫描信号线S2时，第九晶体管T9将第一参考信号传输到第五节点N5。
在本公开的示例性实施方式中，第一晶体管T1可以称为第一初始化晶体管、第二晶体管T2可以称为补偿晶体管、第三晶体管T3可以称为驱动晶体管、第四晶体管T4可以称为数据写入晶体管、第五晶体管T5可以称为第一发光晶体管、第六晶体管T6可以称为第二发光晶体管、第七晶体管T7可以称为第二初始化晶体管、第八晶体管T8可以称为第二参考晶体管、第九晶体管T9可以称为第一参考晶体管。
在示例性实施方式中，发光器件EL可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。发光器件EL的第一极与第四节点N4连接，发光器件EL的第二极与第二电源线VSS连接，第二电源线VSS的信号为持续提供的低电平信号，第一电源线VDD的信号为持续提供的高电平信号。
在示例性实施方式中，第一晶体管T1到第九晶体管T9可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第九晶体管T9可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第九晶体管T9可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，即LTPS+Oxide(简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗， 可以提高显示品质。
在示例性实施方式中，图4所示像素驱动电路的工作过程可以包括第一阶段至第五阶段。
第一阶段。第一阶段可以包括重复执行的多个子阶段，每个子阶段可以包括依次执行的第一子阶段和第二子阶段。
在第一子阶段，第四扫描信号线S4和第一发光信号线EM1的信号为导通信号，其它信号线的信号为断开信号。第四扫描信号线S4的信号为导通信号可以使得第一晶体管T1导通，第一初始信号线INIT1的第一初始信号可以被提供至第一节点N1，对第一节点N1进行初始化。当第三晶体管T3为P型晶体管时，第三晶体管T3导通。第一发光信号线EM1的导通信号可以使得第五晶体管T5导通，第一电源线VDD的第一电源信号可以被提供至第二节点N2。
在第二子阶段，第二扫描信号线S2和第一发光信号线EM1的信号为导通信号，其它信号线的信号为断开信号。第二扫描信号线S2的信号为导通信号可以使得第二晶体管T2导通，将第一节点N1和第三节点N3连接，第三晶体管T3的阈值电压写入第一节点N1。第二扫描信号线S2的信号为导通信号可以使得第九晶体管T9导通，第一参考信号线REF1的第一参考信号被提供至第五节点N5，对第五节点N5进行初始化。第一发光信号线EM1的导通信号可以使得第五晶体管T5导通，第一电源线VDD的第一电源信号可以被提供至第二节点N2。
第二阶段。第三扫描信号线S3的信号为导通信号，其它信号线的信号为断开信号。第三扫描信号线S3的信号为导通信号，可以使得第四晶体管T4导通，数据信号线DATA提供的数据电压写入第五节点N5。
第三阶段。第一扫描信号线S1的信号为导通信号，其它信号线的信号为断开信号。第一扫描信号线S1的信号为导通信号使得第七晶体管T7导通，第二初始信号线INIT2的第二初始信号可以被写入第四节点N4，对第四节点N4进行初始化，避免上一帧残留信号影响本帧的显示。第一扫描信号线S1的信号为导通信号使得第八晶体管T8导通，第二参考信号线REF2 的第二参考信号可以被写入第二节点N2。
第四阶段。第二发光信号线EM2的信号为导通信号，其它信号线的信号为断开信号。第二发光信号线EM2的信号为导通信号使得第六晶体管T6导通，将第三节点N3和第四节点N4连接，使得第三节点N3和第四节点N4的电位相同。
第五阶段。第一发光信号线EM1和第二发光信号线EM2的信号为导通信号，其它信号线的信号为断开信号。第一发光信号线EM1和第二发光信号线EM2的信号为导通信号，使得第五晶体管T5和第六晶体管T6导通，第一电源线VDD的第一电源信号可以通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光器件EL提供驱动信号，驱动发光器件EL发光。
在示例性实施方式中，由于驱动晶体管(即第三晶体管T3)长期处于一种状态时，电子会被俘获在陷阱中，造成磁滞。因此第一阶段中，通过多次(例如三次)执行对第一节点N1的初始化和阈值电压写入过程，不仅可以减少驱动晶体管的磁滞，而且可以确保第一节点N1的电位稳定性。第三阶段将第二参考信号写入第二节点N2，通过改变第二节点N2的电位，可以有助于减少驱动晶体管的磁滞。第四阶段通过连接第三节点N3和第四节点N4，可以提高第四节点N4的电位，有利于减少后续达到发光器件的启亮电压所需的时长。
本公开所提供的像素驱动电路，可以有效改善驱动晶体管的磁滞情况，有利于提高显示效果。
图5为本公开示例性实施例一种显示基板平面结构示意图，示意了显示基板中3个电路单元(第一电路单元、第二电路单元和第三电路单元)中像素驱动电路的结构。在示例性实施方式中，显示基板可以包括设置在基底上的驱动电路层以及设置在驱动电路层远离基底一侧的发光结构层，驱动电路层可以至少包括多个电路单元，发光结构层至少包括多个发光单元，至少一个电路单元包括像素驱动电路，至少一个发光单元包括发光器件，发光器件可以至少包括阳极、有机发光层和阴极，发光单元中的阳极与对应电路单元中的像素驱动电路连接。在示例性实施方式中，本公开中所说的电路单元， 是指按照像素驱动电路划分的区域，本公开中所说的发光单元，是指按照发光器件划分的区域。在示例性实施例中，发光单元在基底上正投影的位置与电路单元在基底上正投影的位置可以是对应的，或者，发光单元在基底上正投影的位置与电路单元在基底上正投影的位置可以是不对应的。
在示例性实施例中，沿着第一方向X依次设置的多个电路单元可以称为单元行，沿着第二方向Y依次设置的多个电路单元可以称为单元列，多个单元行和多个单元列构成阵列排布的电路单元阵列，第一方向X与第二方向Y交叉。
如图5所示，在示例性实施方式中，驱动电路层还可以包括沿着第二方向Y延伸的至少一条第一电源线51、沿着第二方向Y延伸的至少一条第二电源线52、沿着第一方向X延伸的至少一条第一电源连接线68以及沿着第一方向X延伸的至少一条第二电源连接线69。在示例性实施方式中，第一电源线51与多个电路单元中的像素驱动电路连接，第一电源线51被配置为向像素驱动电路持续提供高电平信号，第二电源线52与多个发光单元的阴极连接，第二电源线52被配置为向阴极持续提供低电平信号。在示例性实施方式中，沿着第二方向Y延伸的第一电源线51与沿着第一方向X延伸的第一电源连接线68相互连接，形成传输第一电源信号的网状结构，沿着第二方向Y延伸的第二电源线52与沿着第一方向X延伸的第二电源连接线69相互连接，形成传输第二电源信号的网状结构。
本公开中，A沿B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿B方向伸展，且主要部分沿B方向伸展的长度大于次要部分沿其它方向伸展的长度。
在示例性实施方式中，驱动电路层还可以包括参考信号连接线54和第一参考信号线91，第一参考信号线91的形状可以为沿着第一方向X延伸的线形状，参考信号连接线54的形状可以为沿着第二方向Y延伸的线形状，参考信号连接线54与第一参考信号线91相互连接，形成传输第一参考信号的网状结构。
在示例性实施方式中，在垂直于显示基板的平面上，驱动电路层可以包括在基底上依次设置的半导体层、第一导电层、第二导电层、第三导电层和 第四导电层。第一电源线51和第一电源连接线68可以设置在不同的导电层中，第一电源线51与第一电源连接线68可以通过过孔连接。第二电源线52和第二电源连接线69可以设置在不同的导电层中，第二电源线52与第二电源连接线69可以通过过孔连接。
在示例性实施方式中，第一电源线51和第二电源线52可以同层设置，且通过同一次图案化工艺同步形成，第一电源连接线68和第二电源连接线69可以同层设置，且通过同一次图案化工艺同步形成。
在示例性实施方式中，第一电源连接线68和第二电源连接线69可以设置在第三导电层中，第一电源线51和第二电源线52可以设置在第四导电层中。
在示例性实施方式中，参考信号连接线54和第一参考信号线91可以设置在不同的导电层中，参考信号连接线54与第一参考信号线91可以通过过孔连接。
在示例性实施方式中，第一参考信号线91可以设置在第三导电层中，参考信号连接线54可以设置在第四导电层中。
在示例性实施方式中，至少一个电路单元可以包括多个晶体管，半导体层可以至少包括多个晶体管的有源层。
在示例性实施方式中，至少一个像素驱动电路可以包括作为第一初始化晶体管的第一晶体管T1、作为补偿晶体管的第二晶体管T2、作为驱动晶体管的第三晶体管T3、作为数据写入晶体管的第四晶体管T4、作为第一发光晶体管的第五晶体管T5、作为第二发光晶体管的第六晶体管T6、作为第二初始化晶体管的第七晶体管T7、作为第二参考晶体管的第八晶体管T8、作为第一参考晶体管的第九晶体管T9、第一存储电容和第二存储电容。
图6为图5中第一存储电容和第二存储电容区域的放大图。如图6所示，在示例性实施方式中，第一存储电容可以至少包括第一极板71和第三极板73，第三极板73在基底上的正投影与第一极板71在基底上的正投影至少部分交叠。第二存储电容可以至少包括第二极板72和第四极板74，第四极板74在基底上的正投影与第二极板72在基底上的正投影至少部分交叠。
在示例性实施方式中，第一极板71和第二极板72可以设置在第一导电层中，第三极板73和第四极板74可以设置在第二导电层中，第一极板71可以作为第三晶体管T3的栅电极，第二极板72与第三极板73连接，第四极板74与第一电源线51连接。
在示例性实施方式中，第一晶体管T1的栅电极与第四扫描信号线64连接，第一晶体管T1的第一极与第一初始信号线81连接，第一晶体管T1的第二极分别与第二晶体管T2的第一极和第一存储电容的第一极板71连接。第二晶体管T2的栅电极与第二扫描信号线62连接，第二晶体管T2的第二极分别与第三晶体管T3的第二极和第六晶体管T6的第一极连接。第三晶体管T3的栅电极作为第一存储电容的第一极板71，第三晶体管T3的第一极分别与第五晶体管T5的第二极和第八晶体管T8的第二极连接。第四晶体管T4的栅电极与第三扫描信号线63连接，第四晶体管T4的第一极与数据信号线53连接，第四晶体管T4的第二极分别与第九晶体管T9的第二极、第一存储电容的第三极板73和第二存储电容的第二极板72连接。第五晶体管T5的栅电极与第一发光信号线31连接，第五晶体管T5的第一极与第一电源线51连接。第六晶体管T6的栅电极与第二发光信号线32连接，第六晶体管T6的第二极与第七晶体管T7的第二极连接。第七晶体管T7的栅电极与第一扫描信号线61连接，第七晶体管T7的第一极与第二初始信号线82连接。第八晶体管T8的栅电极与第一扫描信号线61连接，第八晶体管T8的第一极与第二参考信号线92连接。第九晶体管T9的栅电极与第二扫描信号线62连接，第九晶体管T9的第一极与第一参考信号线91连接。
在示例性实施方式中，第二扫描信号线62和第五扫描信号线65传输相同的扫描信号。
在示例性实施方式中，第一扫描信号线61、第二扫描信号线62、第三扫描信号线63、第四扫描信号线64、第五扫描信号线65、第一发光信号线31、第二发光信号线32、第一初始信号线81、第二初始信号线82、第一参考信号线91和第二参考信号线92的形状可以为主体部分沿着第一方向X延伸的线形状，第一电源线51和数据信号线53的形状可以为主体部分沿着第二方向Y延伸的线形状。
在示例性实施方式中，至少一个电路单元还可以包括阳极连接电极55，阳极连接电极55一方面分别与第六晶体管T6的第二极和第七晶体管T7的第二极连接，另一方面与发光单元的阳极连接。
在示例性实施方式中，驱动电路层还可以包括修复线33，修复线33的形状可以为主体部分沿着第一方向X延伸的条形状，修复线33在基底上的正投影与阳极连接电极55在基底上的正投影至少部分交叠。
如图5和图6所示，在示例性实施方式中，至少一个电路单元还可以包括第一连接电极41，第一连接电极41分别与第一晶体管T1的第二极、第二晶体管T2的第一极和第一存储电容的第一极板71连接，第一连接电极41可以作为像素驱动电路的第一节点。
在示例性实施方式中，至少一个电路单元还可以包括电源屏蔽块51-1，电源屏蔽块51-1与第一电源线51连接，电源屏蔽块51-1在基底上的正投影与第一连接电极41在基底上的正投影至少部分交叠，以屏蔽像素驱动电路中其它信号对第一节点的影响。
在示例性实施方式中，至少一个电路单元还可以包括第二连接电极42，第二连接电极42分别与第四晶体管T4的第二极、第九晶体管T9的第二极、第一存储电容的第三极板73和第二存储电容的第二极板72连接，第二连接电极42可以作为像素驱动电路中的第五节点N5。
在示例性实施方式中，第一电源线51在基底上的正投影与第二连接电极42在基底上的正投影至少部分交叠，以屏蔽像素驱动电路中其它信号对第五节点的影响。
在示例性实施方式中，至少一个电路单元还可以包括第一屏蔽电极36，第一屏蔽电极36与第四极板74连接，第一屏蔽电极36在基底上的正投影与第一晶体管T1两个栅电极之间的节点在基底上的正投影至少部分交叠，第一屏蔽电极36在基底上的正投影与第二晶体管T2两个栅电极之间的节点在基底上的正投影至少部分交叠。在示例性实施方式中，第一屏蔽电极36被配置为屏蔽数据电压跳变对第一晶体管T1和第二晶体管T2的影响，避免数据电压跳变影响像素驱动电路的正常工作，提高显示效果。
在示例性实施方式中，至少一个电路单元还可以包括第二屏蔽电极37，第二屏蔽电极37与第四极板74连接，第二屏蔽电极37设置在第四晶体管T4的第一极和第二极之间。在示例性实施方式中，第二屏蔽电极37被配置为屏蔽数据电压跳变对第五节点的影响，避免数据电压跳变影响像素驱动电路的正常工作，提高显示效果。
在示例性实施方式中，第四极板74、第一屏蔽电极36和第二屏蔽电极37可以为相互连接的一体结构。
在示例性实施方式中，至少一个电路单元还可以包括第三屏蔽电极38，第三屏蔽电极38与第二参考信号线92连接，第三屏蔽电极38在基底上的正投影与第四晶体管T4两个栅电极之间的节点在基底上的正投影至少部分交叠。在示例性实施方式中，第三屏蔽电极38被配置为屏蔽数据电压跳变对第四晶体管T4的影响，避免数据电压跳变影响像素驱动电路的正常工作，提高显示效果。
在示例性实施方式中，至少一个电路单元还可以包括第四屏蔽电极39，第四屏蔽电极39与第二参考信号线92连接，第四屏蔽电极39在基底上的正投影与第九晶体管T9两个栅电极之间的节点在基底上的正投影至少部分交叠。在示例性实施方式中，第四屏蔽电极39被配置为屏蔽数据电压跳变对第九晶体管T9的影响，避免数据电压跳变影响像素驱动电路的正常工作，提高显示效果。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。 本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以第n单元行中3个电路单元为例，本实施例显示基板的制备过程可以包括如下操作。
(11)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层，如图7所示。
在示例性实施方式中，显示基板中每个电路单元的半导体层图案可以至少包括第一晶体管T1的第一有源层11、第二晶体管T2的第二有源层12、第三晶体管T3的第三有源层13、第四晶体管T4的第四有源层14、第五晶体管T5的第五有源层15、第六晶体管T6的第六有源层16、第七晶体管T7的第七有源层17、第八晶体管T8的第八有源层18和第九晶体管T9的第九有源层19，且第一有源层11至第三有源层13和第五有源层15至第八有源层18可以为相互连接的一体结构，第四有源层14和第九有源层19可以为相互连接的一体结构。
在示例性实施方式中，第n单元行的第四有源层14和第九有源层19可以位于第三有源层13靠近第n-1单元行的一侧，即第四有源层14和第九有源层19可以位于本电路单元的第三有源层13第二方向Y的反方向的一侧。第n单元行的第一有源层11、第二有源层12、第五有源层15至第八有源层18可以位于第三有源层13靠近第n+1单元行的一侧，即第一有源层11、第二有源层12、第五有源层15至第八有源层18可以位于本电路单元的第三有源层13第二方向Y的一侧。
在示例性实施方式中，第一有源层11可以位于本电路单元的第三有源层13第二方向Y的一侧，第五有源层15可以位于本电路单元的第一有源层11第二方向Y的一侧，第八有源层18可以位于本电路单元的第五有源层15第 二方向Y的一侧。第二有源层12可以位于本电路单元的第三有源层13第二方向Y的一侧，第六有源层16可以位于本电路单元的第二有源层12第二方向Y的一侧，第七有源层17可以位于本电路单元的第六有源层16第二方向Y的一侧。
在示例性实施方式中，第一有源层11、第四有源层14、第五有源层15和第八有源层18可以位于本电路单元第一方向X的一侧(如第一方向X的反方向一侧)，第二有源层12、第六有源层16第七有源层17和第九有源层19可以位于本电路单元第一方向X的另一侧(如第一方向X的一侧)。
在示例性实施方式中，第一有源层11和第二有源层12的形状可以呈“L”字形状，第三有源层13的形状可以呈“C”字形状，第四有源层14和第九有源层19的形状可以呈“n”字形状，第五有源层15、第六有源层16、第七有源层17和第八有源层18的形状可以呈“I”字形状。
在示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一有源层的第二区11-2和第二有源层的第一区12-1可以相互连接，第一有源层的第二区11-2可以作为第二有源层的第一区12-1。第三有源层的第一区13-1、第五有源层的第二区15-2和第八有源层的第二区18-2可以相互连接，第三有源层的第一区13-1可以同时作为第五有源层的第二区15-2和第八有源层的第二区18-2，构成像素驱动电路的第二节点N2。第二有源层的第二区12-2、第三有源层的第二区13-2和第六有源层的第一区16-1可以相互连接，第三有源层的第二区13-2可以同时作为第二有源层的第二区12-2和第六有源层的第一区16-1，构成像素驱动电路的第三节点N3。第四有源层的第二区14-2和第九有源层的第二区19-2可以相互连接，第四有源层的第二区14-2可以作为第九有源层的第二区19-2。第六有源层的第二区16-2和第七有源层的第二区17-2可以相互连接，第六有源层的第二区16-2可以作为第七有源层的第二区17-2，构成像素驱动电路的第四节点N4。第一有源层的第一区11-1、第四有源层的第一区14-1、第五有源层的第一区15-1、第七有源层的第一区17-1、第八有源层的第一区18-1和第九有源层的第一区19-1可以单独设置，第四有源层的第一区14-1可以位于第四有源层的沟道区靠近第三有源层13 的一侧，第九有源层的第一区19-1可以位于第九有源层的沟道区靠近第三有源层13的一侧。
在示例性实施方式中，至少一个单元行中，在第一方向X相邻的电路单元中的半导体层相互连接，即第n单元行的第一电路单元的半导体层与第n单元行的第二电路单元的半导体层相连接，第n单元行的第二电路单元的半导体层与第n单元行的第三电路单元的半导体层相连接。
在示例性实施方式中，显示基板还可以包括第一有源连接线10和第二有源连接线20。第一有源连接线10可以位于第九有源层19第二方向Y的一侧，且与每个电路单元的第九有源层的第一区19-1连接。第二有源连接线20可以位于第七有源层17第二方向Y的一侧，且与每个电路单元的第七有源层的第一区17-1连接。
在示例性实施方式中，第一有源连接线10的形状可以为主体部分沿着第一方向X延伸的折线状，第一有源连接线10与多个电路单元的第九有源层可以为相互连接的一体结构。由于第九有源层的第一区与后续形成的第一参考信号线连接，因而第一有源连接线10可以复用为沿着第一方向X延伸的第一参考信号线，不仅可以保证一单元行中的多个第九有源层的第一区具有相同的电位，而且可以减小第一参考信号的压降，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第二有源连接线20的形状可以为主体部分沿着第一方向X延伸的直线状，第二有源连接线20与多个电路单元的第七有源层可以为相互连接的一体结构。由于第七有源层的第一区与后续形成的第二初始信号线连接，因而第二有源连接线20可以复用为沿着第一方向X延伸的第二初始信号线，不仅可以保证一单元行中的多个第七有源层的第一区具有相同的电位，而且可以减小第二初始信号的压降，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，至少一个单元列中，在第二方向Y相邻的电路单元中的半导体层相互间隔，即第n-1单元行的第一电路单元的半导体层与第n单元行的第一电路单元的半导体层没有连接，第n单元行的第一电路单元的半导体层与第n+1单元行的第一电路单元的半导体层没有连接。
(12)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图8A和图8B所示，图8B为图8A中第一导电层的示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，显示基板中每个电路单元的第一导电层图案至少包括：第一栅电极21、第二栅电极22、第四栅电极24、第五栅电极25、第六栅电极26、第九栅电极29、第一扫描信号线61、第一存储电容的第一极板71和第二存储电容的第二极板72。
在示例性实施方式中，第一栅电极21的形状可以呈“L”字形状，可以位于第一极板71第二方向Y的一侧，第一栅电极21与第一有源层相重叠的区域可以作为双栅结构的第一晶体管T1的栅电极。
在示例性实施方式中，第二栅电极22的形状可以呈“T”字形状，可以位于第一极板71第二方向Y的一侧，第二栅电极22与第二有源层相重叠的区域可以作为双栅结构的第二晶体管T2的栅电极。
在示例性实施方式中，第四栅电极24的形状可以呈“L”字形状，可以位于第二极板72第二方向Y的反方向的一侧，第四栅电极24与第四有源层相重叠的区域可以作为双栅结构的第四晶体管T4的栅电极。
在示例性实施方式中，第五栅电极25的形状可以沿着第二方向Y延伸的条形状，可以位于第一栅电极21第二方向Y的一侧，第五栅电极25与第五有源层相重叠的区域可以作为第五晶体管T5的栅电极。
在示例性实施方式中，第六栅电极26的形状可以沿着第一方向X延伸的条形状，可以位于第二栅电极22第二方向Y的一侧，第六栅电极26与第六有源层相重叠的区域可以作为第六晶体管T6的栅电极。
在示例性实施方式中，第九栅电极29的形状可以沿着第一方向X延伸的条形状，可以位于第二极板72第二方向Y的反方向的一侧，第九栅电极29与第九有源层相重叠的区域可以作为双栅结构的第九晶体管T9的栅电极。
在示例性实施方式中，第一扫描信号线61的形状可以为主体部分沿着第一方向X延伸的线形状，可以位于第五栅电极25和第六栅电极26第二方向Y的一侧，第一扫描信号线61与第七有源层相重叠的区域可以作为第七晶体管T7的栅电极，第一扫描信号线61与第八有源层相重叠的区域可以作为第八晶体管T8的栅电极。
在示例性实施方式中，第一存储电容的第一极板71的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板71在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影至少部分重叠，第一极板71可以同时作为第一存储电容的下极板和第三晶体管T3的栅电极。
在示例性实施方式中，第二存储电容的第二极板72的形状可以为矩形状，矩形状的角部可以设置倒角，可以位于第一极板71第二方向Y的反方向的一侧，以及第四栅电极24和第九栅电极29第二方向Y的一侧，即在第二方向Y上，第二极板72位于第一极板71与第四栅电极24(第九栅电极29)之间，第二极板72在基底上的正投影与半导体层在基底上的正投影没有交叠。在示例性实施方式中，第二极板72可以作为第二存储电容的下极板。
在示例性实施方式中，第一极板71和第二极板72在基底上正投影的面积可以相同，或者不同。
在示例性实施方式中，第一有源连接线10与第九有源层的第一区连接的区域向第九有源层方向弯曲，使第一有源连接线10远离第九有源层的一侧形成凹部。第二极板72靠近第一有源连接线10的一侧设置有凸出部72-1，凸出部72-1的形状可以为矩形状，凸出部72-1的第一端与第二极板72连接，凸出部72-1的第二端伸入到第一有源连接线10的凹部中。
在示例性实施方式中，第二极板72和凸出部72-1可以为相互连接的一体结构。本公开通过设置第一有源连接线10的凹部和第二极板72的凸出部72-1，可以有效增加第二极板72的面积，有效增加第二存储电容的电容量。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第九晶体管T9的沟道区域，未被第一导电层遮挡区域的 半导体层被导体化，即第一有源层至第九有源层的第一区和第二区均被导体化。
(13)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，如图9A和图9B所示，图9B为图9A中第二导电层的示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，显示基板中每个电路单元的第二导电层图案至少包括：第一发光信号线31、第二发光信号线32、修复线33、第一屏蔽电极36、第二屏蔽电极37、第三屏蔽电极38、第四屏蔽电极39、第一存储电容的第三极板73、第二存储电容的第四极板74、第一初始信号线81和第二参考信号线92。
在示例性实施方式中，第一发光信号线31、第二发光信号线32、修复线33、第一初始信号线81和第二参考信号线92的形状可以为主体部分沿着第一方向X延伸的线形状，第一发光信号线31、第二发光信号线32、修复线33和第一初始信号线81可以位于第一栅电极21和第一扫描信号线61之间，第二参考信号线92可以位于第四栅电极24第二方向Y的反方向的一侧。
在示例性实施方式中，第一发光信号线31可以位于本电路单元的第一栅电极21第二方向Y的一侧，第一初始信号线81可以位于本电路单元的第一发光信号线31第二方向Y的一侧，第二发光信号线32可以位于本电路单元的第一初始信号线81第二方向Y的一侧，修复线33可以位于本电路单元的第二发光信号线32第二方向Y的一侧，即第二发光信号线32可以位于第一发光信号线31和修复线33之间，第一初始信号线81可以位于第一发光信号线31和第二发光信号线32之间，第二参考信号线92可以位于第一发光信号线31第二方向Y反方向一侧。
在示例性实施方式中，第一发光信号线31靠近第二发光信号线32的一侧设置有第一发光连接块31-1，第一发光连接块31-1可以设置在每个电路单元中，第一发光连接块31-1的第一端与第一发光信号线31连接，第一发光 连接块31-1的第二端向着第二发光信号线32的方向延伸，第一发光连接块31-1被配置为通过后续形成的第七连接电极与第五栅电极25连接。在示例性实施方式中，第一发光信号线31和多个第一发光连接块31-1可以为相互连接的一体结构。
在示例性实施方式中，第二发光信号线32靠近第一发光信号线31的一侧设置有第二发光连接块32-1，第二发光连接块32-1可以设置在每个电路单元中，第二发光连接块32-1的第一端与第二发光信号线32连接，第二发光连接块32-1的第二端向着第一发光信号线31的方向延伸，第二发光连接块32-1被配置为通过后续形成的第八连接电极与第六栅电极26连接。在示例性实施方式中，第二发光信号线32和多个第二发光连接块32-1可以为相互连接的一体结构。
在示例性实施方式中，第一初始信号线81靠近第一发光信号线31的一侧设置有第一初始连接块81-1，第一初始连接块81-1可以设置在每个电路单元中，第一初始连接块81-1的第一端与第一初始信号线81连接，第一初始连接块81-1的第二端向着第一发光信号线31的方向延伸，第一初始连接块81-1被配置为通过后续形成的第九连接电极与第一有源层的第一区连接，因而实现了第一初始信号线81连接第一晶体管T1的第一极，第一初始信号线81可以将第一初始信号写入第一晶体管T1的第一极。在示例性实施方式中，第一初始信号线81和多个第一初始连接块81-1可以为相互连接的一体结构。
在示例性实施方式中，第n+1单元行的第二参考信号线92远离第n+1单元行的第四极板74的一侧设置有第二参考连接块92-1。第二参考连接块92-1可以设置在每个电路单元中，第二参考连接块92-1的第一端与第二参考信号线92连接，第二参考连接块92-1的第二端向着远离第四极板74的方向延伸，即向着第n单元行的方向延伸。在示例性实施方式中，第n+1单元行中第二参考信号线92的第二参考连接块92-1被配置为通过后续形成的第六连接电极与第n单元行中的第八有源层的第一区连接，向第n单元行中的第八晶体管T8的第一极提供第二参考信号。在示例性实施方式中，第二参考信号线92和多个第二参考连接块92-1可以为相互连接的一体结构。
在示例性实施方式中，第一存储电容的第三极板73的轮廓形状可以为矩 形状，矩形状的角部可以设置倒角，可以位于本电路单元的第一发光信号线31和第二参考信号线92之间，第三极板73在基底上的正投影与第一极板71在基底上的正投影至少部分重叠，第三极板73可以作为第一存储电容的上极板，第一极板71和第三极板73构成像素驱动电路的第一存储电容C1。
在示例性实施方式中，第二存储电容的第四极板74的轮廓形状可以为矩形状，矩形状的角部可以设置倒角，可以位于本电路单元的第二参考信号线92和第三极板73之间，第四极板74在基底上的正投影与第二极板72在基底上的正投影至少部分重叠，第四极板74可以作为第二存储电容的上极板，第二极板72和第四极板74构成像素驱动电路的第二存储电容C2。
在示例性实施方式中，第三极板73和第四极板74在基底上正投影的面积可以相同，或者不同。例如，第四极板74在基底上正投影的面积可以大于第三极板73在基底上正投影的面积。
在示例性实施方式中，每个电路单元的第三极板73上设置有第一开口75，第一开口75可以位于第三极板73的中部，第一开口75可以为矩形，使第三极板73形成环形结构。第一开口75暴露出覆盖第一极板71的第三绝缘层，且第一极板71在基底上的正投影包含第一开口75在基底上的正投影。在示例性实施方式中，第一开口75被配置为容置后续形成的第十过孔，第十过孔位于第一开口75内并暴露出第一极板71，使后续形成的第一连接电极与第一极板71连接。
在示例性实施方式中，每个电路单元的第四极板74上设置有第二开口76，第二开口76可以位于第四极板74的中部，第二开口76可以为矩形，使第四极板74形成环形结构。第二开口76暴露出覆盖第二极板72的第三绝缘层，且第二极板72在基底上的正投影包含第二开口76在基底上的正投影。在示例性实施方式中，第二开口76被配置为容置后续形成的第十一过孔，第十一过孔位于第二开口76内并暴露出第二极板72，使后续形成的第二连接电极与第二极板72连接。
在示例性实施方式中，第一屏蔽电极36的形状可以呈“T”字形状，可以位于第四极板74靠近第一发光信号线31的一侧，第一屏蔽电极36可以设置在每个电路单元中。“T”字形状的第一屏蔽电极36可以包括第一延伸段36-1 和第一屏蔽段36-2，第一延伸段36-1的第一端与第四极板74连接，第一延伸段36-1的第二端向着第一发光信号线31延伸后与第一屏蔽段36-2连接。第一屏蔽段36-2的形状可以为沿着第一方向X延伸的条形状，对于第一屏蔽段36-2中位于第一延伸段36-1第一方向X一侧的第一屏蔽端和位于第一延伸段36-1第一方向X的反方向一侧的第二屏蔽端，第一屏蔽端在基底上的正投影与本电路单元中第一晶体管T1两个栅电极之间的半导体层在基底上的正投影至少部分重叠。第二屏蔽端在基底上的正投影与相邻电路单元中第二晶体管T2两个栅电极之间的半导体层在基底上的正投影至少部分重叠。在示例性实施方式中，第一屏蔽电极36被配置为屏蔽数据电压跳变对第一晶体管T1和第二晶体管T2的影响，避免数据电压跳变影响像素驱动电路的正常工作，提高显示效果。
在示例性实施方式中，第二屏蔽电极37的形状可以呈“I”字形状，可以位于第四极板74靠近第二参考信号线92的一侧，第二屏蔽电极37可以设置在每个电路单元中。第二屏蔽电极37的第一端与第四极板74连接，第二屏蔽电极37的第二端向着第二参考信号线92延伸，第二屏蔽电极37的第二端可位于第四晶体管T4的第一极和第四晶体管T4的第二极之间。在示例性实施方式中，第二屏蔽电极37被配置为屏蔽数据电压跳变对第五节点N5的影响，避免数据电压跳变影响像素驱动电路的正常工作，提高显示效果。
在示例性实施方式中，第四极板74、第一屏蔽电极36和第二屏蔽电极37可以为相互连接的一体结构。
在示例性实施方式中，第三屏蔽电极38和第四屏蔽电极39的形状可以呈矩形状，可以位于第二参考信号线92靠近第四极板74的一侧，第三屏蔽电极38和第四屏蔽电极39可以设置在每个电路单元中。第三屏蔽电极38的第一端与第二参考信号线92连接，第三屏蔽电极38的第二端向着第四极板74的方向延伸。第四屏蔽电极39的第一端与第二参考信号线92连接，第四屏蔽电极39的第二端向着第四极板74的方向延伸。第三屏蔽电极38在基底上的正投影与本电路单元中第四晶体管T4两个栅电极之间的半导体层在基底上的正投影至少部分交叠。第四屏蔽电极39在基底上的正投影与本电路单元中第九晶体管T9两个栅电极之间的半导体层在基底上的正投影至少部 分交叠。在示例性实施方式中，第三屏蔽电极38被配置为屏蔽数据电压跳变对第四晶体管T4的影响，第四屏蔽电极39被配置为屏蔽数据电压跳变对第九晶体管T9的影响，避免数据电压跳变影响像素驱动电路的正常工作，提高显示效果。
在示例性实施方式中，修复线33作为预先设置的修复线，被配置为通过焊接方式修复失效的阳极。修复线33被配置为在显示基板出现亮点不良时，通过修复线33向出现亮点不良的子像素的阳极输入信号，将其修复成暗点。
(14)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，每个电路单元中设置有多个过孔，如图10所示。
在示例性实施方式中，显示基板中每个电路单元的多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10、第十一过孔V11、第十二过孔V12、第十三过孔V13、第十四过孔V14、第十五过孔V15、第十六过孔V16、第十七过孔V17、第十八过孔V18、第十九过孔V19、第二十过孔V20、第二十一过孔V21、第二十二过孔V22和第二十三过孔V23。
在示例性实施方式中，第一过孔V1在基底上的正投影位于第一有源层的第一区在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第一过孔V1被配置为使后续形成的第九连接电极通过该过孔与第一有源层的第一区连接。
在示例性实施方式中，第二过孔V2在基底上的正投影位于第一有源层的第二区(也是第二有源层的第一区)在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区(也是第二有源层的第一区)的表面，第二过孔V2被配置为使后续形成的第一连接电极通过该过孔与第一有源层的第二区(也是第二有源层的第一区)连接。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第四有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第三过孔V3被配置为使后续形成的第三连接电极通过该过孔与第四有源层的第一区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第四有源层的第二区(也是第九有源层的第二区)在基底上的正投影的范围之内，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第二区(也是第九有源层的第二区)的表面，第四过孔V4被配置为使后续形成的第二连接电极通过该过孔与第四有源层的第二区(也是第九有源层的第二区)连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第五有源层的第一区在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第五过孔V5被配置为使后续形成的第四连接电极通过该过孔与第五有源层的第一区连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于第六有源层的第二区(也是第七有源层的第二区)在基底上的正投影的范围之内，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区(也是第七有源层的第二区)的表面，第六过孔V6被配置为使后续形成的第五连接电极通过该过孔与第六有源层的第二区(也是第七有源层的第二区)连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于第七有源层的第一区在基底上的正投影的范围之内，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区的表面，第七过孔V7被配置为使后续形成的第二初始信号线通过该过孔与第七有源层的第一区连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于第八有源层的第一区在基底上的正投影的范围之内，第八过孔V8内的第四绝缘层、第 三绝缘层和第二绝缘层被刻蚀掉，暴露出第八有源层的第一区的表面，第八过孔V8被配置为使后续形成的第六连接电极通过该过孔与第八有源层的第一区连接。
在示例性实施方式中，第九过孔V9在基底上的正投影位于第九有源层的第一区在基底上的正投影的范围之内，第九过孔V9内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第九有源层的第一区的表面，第九过孔V9被配置为使后续形成的第一参考信号线通过该过孔与第九有源层的第一区连接。
在示例性实施方式中，第十过孔V10在基底上的正投影位于第三极板73的第一开口75在基底上的正投影的范围之内，第十过孔V10内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板71的表面，第十过孔V10被配置为使后续形成的第一连接电极通过该过孔与第一极板71连接。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于第四极板74的第二开口76在基底上的正投影的范围之内，第十一过孔V11内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第二极板72的表面，第十一过孔V11被配置为使后续形成的第二连接电极通过该过孔与第二极板72连接。
在示例性实施方式中，第十二过孔V12在基底上的正投影位于第三极板73在基底上的正投影的范围之内，第十二过孔V12内的第四绝缘层被刻蚀掉，暴露出第三极板73的表面，第十二过孔V12被配置为使后续形成的第二连接电极通过该过孔与第三极板73连接。
在示例性实施方式中，第十三过孔V13在基底上的正投影位于第四极板74在基底上的正投影的范围之内，第十三过孔V13内的第四绝缘层被刻蚀掉，暴露出第四极板74的表面，第十三过孔V13被配置为使后续形成的第一电源连接线通过该过孔与第四极板74连接。
在示例性实施方式中，第十四过孔V14在基底上的正投影位于第一栅电极21在基底上的正投影的范围之内，第十四过孔V14内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一栅电极21的表面，第十四过孔V14被配置为使后续形成的第四扫描信号线通过该过孔与第一栅电极21连接。
在示例性实施方式中，第十五过孔V15在基底上的正投影位于第二栅电极22在基底上的正投影的范围之内，第十五过孔V15内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第二栅电极22的表面，第十五过孔V15被配置为使后续形成的第五扫描信号线通过该过孔与第二栅电极22连接。
在示例性实施方式中，第十六过孔V16在基底上的正投影位于第四栅电极24在基底上的正投影的范围之内，第十六过孔V16内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第四栅电极24的表面，第十六过孔V16被配置为使后续形成的第三扫描信号线通过该过孔与第四栅电极24连接。
在示例性实施方式中，第十七过孔V17在基底上的正投影位于第五栅电极25在基底上的正投影的范围之内，第十七过孔V17内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第五栅电极25的表面，第十七过孔V17被配置为使后续形成的第七连接电极通过该过孔与第五栅电极25连接。
在示例性实施方式中，第十八过孔V18在基底上的正投影位于第六栅电极26在基底上的正投影的范围之内，第十八过孔V18内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第六栅电极26的表面，第十八过孔V18被配置为使后续形成的第八连接电极通过该过孔与第六栅电极26连接。
在示例性实施方式中，第十九过孔V19在基底上的正投影位于第九栅电极29在基底上的正投影的范围之内，第十九过孔V19内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第九栅电极29的表面，第十九过孔V19被配置为使后续形成的第二扫描信号线通过该过孔与第九栅电极29连接。
在示例性实施方式中，第二十过孔V20在基底上的正投影位于第一发光信号线31的第一发光连接块31-1在基底上的正投影的范围之内，第二十过孔V20内的第四绝缘层被刻蚀掉，暴露出第一发光连接块31-1的表面，第二十过孔V20被配置为使后续形成的第七连接电极通过该过孔与第一发光连接块31-1连接。
在示例性实施方式中，第二十一过孔V21在基底上的正投影位于第二发光信号线32的第二发光连接块32-1在基底上的正投影的范围之内，第二十一过孔V21内的第四绝缘层被刻蚀掉，暴露出第二发光连接块32-1的表面， 第二十一过孔V21被配置为使后续形成的第八连接电极通过该过孔与第二发光连接块32-1连接。
在示例性实施方式中，第二十二过孔V22在基底上的正投影位于第二参考信号线92的第二参考连接块92-1在基底上的正投影的范围之内，第二十二过孔V22内的第四绝缘层被刻蚀掉，暴露出第二参考连接块92-1的表面，第二十二过孔V22被配置为使后续形成的第六连接电极通过该过孔与第二参考连接块92-1连接。
在示例性实施方式中，第二十三过孔V23在基底上的正投影位于第一初始信号线81的第一初始连接块81-1在基底上的正投影的范围之内，第二十三过孔V23内的第四绝缘层被刻蚀掉，暴露出第一初始连接块81-1的表面，第二十三过孔V23被配置为使后续形成的第九连接电极通过该过孔与第一初始连接块81-1连接。
(15)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，如图11A和图11B所示，图11B为图11A中第三导电层的示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，显示基板中每个电路单元的第三导电层图案均可以包括：第一连接电极41、第二连接电极42、第三连接电极43、第四连接电极44、第五连接电极45、第六连接电极46、第七连接电极47、第八连接电极48、第九连接电极49、第二扫描信号线62、第三扫描信号线63、第四扫描信号线64、第五扫描信号线65、第一电源连接线68、第二电源连接线69、第二初始信号线82和第一参考信号线91。
在示例性实施方式中，第二扫描信号线62、第三扫描信号线63、第四扫描信号线64、第五扫描信号线65、第一电源连接线68、第二电源连接线69、第二初始信号线82和第一参考信号线91的形状可以为主体部分沿着第一方向X延伸的线形状。第二扫描信号线62、第三扫描信号线63和第一参考信号线91可以位于第四极板74第二方向Y反方向的一侧，第四扫描信号线64、第五扫描信号线65和第二初始信号线82可以位于第三极板73第二方向Y 的一侧。第一电源连接线68可以位于第三极板73所在区域。第二电源连接线69可以位于第五扫描信号线65和第二初始信号线82之间。第二电源连接线69可以位于第一电源连接线68第二方向Y的一侧。
在示例性实施方式中，第二电源连接线69在基底的正投影与第一初始信号线81在基底的正投影至少部分交叠，第二电源连接线69被配置为与后续形成的第二电源线连接，在显示基板上形成网状连通结构的低压电源网格结构。在示例性实施方式中，第一参考信号线91可以位于第四极板74第二方向Y反方向的一侧，第二扫描信号线62可以位于第一参考信号线91第二方向Y反方向的一侧，第三扫描信号线63可以位于第二扫描信号线62第二方向Y反方向的一侧。
在示例性实施方式中，第四扫描信号线64可以位于第三极板73第二方向Y的一侧，第五扫描信号线65可以位于第四扫描信号线64第二方向Y的一侧，第二电源连接线69可以位于第五扫描信号线65第二方向Y的一侧，第二初始信号线82可以位于第二电源连接线69第二方向Y的一侧。
在示例性实施方式中，第二扫描信号线62通过第十九过孔V19与每个电路单元中的第九栅电极29连接，因而实现了第二扫描信号线62连接第九晶体管T9的第九栅电极29，第二扫描信号线62可以控制第九晶体管T9的导通和断开。
在示例性实施方式中，第二扫描信号线62可以设置有第二扫描连接块62-1，第二扫描连接块62-1可以为矩形状。第二扫描连接块62-1的中部与第二扫描信号线62连接，第二扫描连接块62-1的第一端向着第一参考信号线91延伸，第二扫描连接块62-1的第二端向着第三扫描信号线63延伸。在示例性实施方式中，第二扫描连接块62-1被配置为通过第十九过孔V19与每个电路单元中的第九栅电极29连接，因而实现了第二扫描信号线62连接第九晶体管T9的第九栅电极29，第二扫描信号线62可以控制第九晶体管T9的导通和断开。
在示例性实施方式中，第五扫描信号线65通过第十五过孔V15与每个电路单元中的第二栅电极22连接，因而实现了第五扫描信号线65连接第二晶体管T2的第二栅电极22，第五扫描信号线65可以控制第二晶体管T2的 导通和断开。
在示例性实施方式中，第五扫描信号线65可以设置有第五扫描连接块65-1，第五扫描连接块65-1可以为矩形状。第五扫描连接块65-1的中部与第五扫描信号线65连接，第五扫描连接块65-1的第一端向着第二初始信号线82延伸，第五扫描连接块65-1的第二端向着第一参考信号线91延伸。在示例性实施方式中，第五扫描连接块65-1被配置为通过第十五过孔V15与每个电路单元中的第二栅电极22连接，因而实现了第五扫描信号线65连接第二晶体管T2的第二栅电极22，第五扫描信号线65可以控制第二晶体管T2的导通和断开。
在示例性实施方式中，第二扫描信号线62和第五扫描信号线65可以延伸到边框区域后，与同一个栅极驱动电路连接，实现相同扫描信号的输出，即第二扫描信号线62和第五扫描信号线65输出相同的第二扫描信号。
在示例性实施方式中，第三扫描信号线63通过第十六过孔V16与每个电路单元中的第四栅电极24连接，因而实现了第三扫描信号线63连接第四晶体管T4的第四栅电极24，第三扫描信号线63可以控制第四晶体管T4的导通和断开。
在示例性实施方式中，第三扫描信号线63靠近第一参考信号线91的一侧设置有第三扫描连接块63-1，第三扫描连接块63-1的第一端与第三扫描信号线63连接，第三扫描连接块63-1的第二端向着第一参考信号线91的方向延伸。在示例性实施方式中，第三扫描连接块63-1被配置为通过第十六过孔V16与每个电路单元中的第四栅电极24连接，因而实现了第三扫描信号线63连接第四晶体管T4的第四栅电极24，第三扫描信号线63可以控制第四晶体管T4的导通和断开。
在示例性实施方式中，第四扫描信号线64通过第十四过孔V14与每个电路单元中的第一栅电极21连接，因而实现了第四扫描信号线64连接第一晶体管T1的第一栅电极21，第四扫描信号线64可以控制第一晶体管T1的导通和断开。
在示例性实施方式中，第四扫描信号线64可以设置有第四扫描连接块 64-1，第四扫描连接块64-1可以为矩形状。第四扫描连接块64-1的中部与第四扫描信号线64连接，第四扫描连接块64-1的第一端向着第二初始信号线82延伸，第四扫描连接块64-1的第二端向着第一参考信号线91延伸。在示例性实施方式中，第四扫描连接块64-1被配置为通过第十四过孔V14与每个电路单元中的第一栅电极21连接，因而实现了第四扫描信号线64连接第一晶体管T1的第一栅电极21，第四扫描信号线64可以控制第一晶体管T1的导通和断开。
在示例性实施方式中，第二初始信号线82通过第七过孔V7与每个电路单元中的第七有源层的第一区连接，因而实现了第二初始信号线82连接第七晶体管T7的第一极，第二初始信号线82可以将第二初始信号写入第七晶体管T7的第一极。
在示例性实施方式中，第二初始信号线82靠近第五扫描信号线65的一侧设置有第二初始连接块82-1，第二初始连接块82-1的第一端与第二初始信号线82连接，第二初始连接块82-1的第二端向着第五扫描信号线65的方向延伸。在示例性实施方式中，第二初始连接块82-1被配置为通过第七过孔V7与每个电路单元中的第七有源层的第一区连接，因而实现了第二初始信号线82连接第七晶体管T7的第一极，第二初始信号线82可以将第二初始信号写入第七晶体管T7的第一极。在示例性实施方式中，由于半导体层的第二有源连接线20与一个单元行中多个电路单元的第七有源层的第一区直接连接，第三导电层的第二初始信号线82与一个单元行中多个电路单元中的第七有源层的第一区通过过孔连接，因而第二有源连接线20和第二初始信号线82构成双层结构的信号线，不仅可以保证一单元行中的多个第七有源层的第一区具有相同的电位，而且可以减小信号线的电阻，可以减小第二初始信号的压降，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第一参考信号线91通过第九过孔V9与每个电路单元中的第九有源层的第一区连接，因而实现了第一参考信号线91连接第九晶体管T9的第一极，第一参考信号线91可以将第一参考信号写入第九晶体管T9的第一极。
在示例性实施方式中，第一参考信号线91靠近第一电源连接线68的一侧设置有第一参考连接块91-1，第一参考连接块91-1的第一端与第一参考信号线91连接，第一参考连接块91-1的第二端向着第一电源连接线68的方向延伸，第一参考连接块91-1一方面被配置为通过第九过孔V9与第九有源层的第一区连接，另一方面被配置为与后续形成的参考信号连接线连接。
在示例性实施方式中，第一有源连接线10的形状可以为主体部分沿着第一方向X延伸的折线状，第一有源连接线10与多个电路单元的第九有源层可以为相互连接的一体结构。由于第九有源层的第一区与后续形成的第一参考信号线连接，因而第一有源连接线10可以复用为沿着第一方向X延伸的第一参考信号线，不仅可以保证一单元行中的多个第九有源层的第一区具有相同的电位，而且可以减小第一参考信号的压降，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第一电源连接线68通过第十三过孔V13与每个电路单元中的第四极板74连接，因而实现了第一电源连接线68连接第四极板74。由于第一电源连接线68与后续形成的第一电源线连接，因而第一电源连接线68可以将第一电源信号写入第二存储电容的上极板。
在示例性实施方式中，第一电源连接线68远离第二电源连接线69的一侧设置有第一电源连接块68-1，第一电源连接块68-1的第一端与第一电源连接线68连接，第一电源连接块68-1的第二端向着远离第二电源连接线69的方向延伸。在示例性实施方式中，第一电源连接块68-1一方面被被配置为通过第十三过孔V13与第四极板74连接，另一方面被配置为与后续形成的第一电源线连接。
在示例性实施方式中，第一电源连接线68在基底上的正投影与第三极板73在基底上的正投影至少部分交叠，第一电源连接线68被配置为与后续形成的第一电源线连接，在显示基板上形成网状连通结构的高压电源网格结构。
在示例性实施方式中，至少一个电路单元中，第二电源连接线69远离第一电源连接线68的一侧设置有第二电源连接块69-1，第二电源连接块69-1的第一端与第二电源连接线69连接，第二电源连接块69-1的第二端向着远离第一电源连接线68的方向延伸，第二电源连接块69-1被配置为与后续形 成的第二电源线连接。在示例性实施方式中，第二电源连接块69-1可以设置在第一电路单元与第二电路单元之间。
在示例性实施方式中，第二电源连接线69在基底的正投影与第一初始信号线81在基底的正投影至少部分交叠，第二电源连接线69被配置为与后续形成的第二电源线连接，在显示基板上形成网状连通结构的低压电源网格结构。
在示例性实施方式中，第一连接电极41的形状可以为主体部分沿着第二方向Y延伸的条形状，可以位于第四扫描信号线64与第一电源连接线68之间，第一连接电极41的第一端通过第二过孔V2与第一有源层的第二区(也是第二有源层的第一区)连接，第一连接电极41的第二端通过第十过孔V10与第一极板71连接。在示例性实施方式中，第一连接电极41使第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的栅电极和第一存储电容的第一极板71(即第一存储电容的第一端)具有相同的电位，第一连接电极41可以作为像素驱动电路的第一节点N1。
在示例性实施方式中，第二连接电极42的形状可以为主体部分沿着第二方向Y延伸的折线状，可以位于第一参考信号线91和第一电源连接线68之间，第二连接电极42的第一端通过第四过孔V4与第四有源层的第二区(也是第九有源层的第二区)连接，第二连接电极42的第二端通过第十二过孔V12与第三极板73连接，第一端与第二端之间的第三端通过第十一过孔V11与第二极板72连接。在示例性实施方式中，第二连接电极42使第四晶体管T4的第二极、第九晶体管T9的第二极、第一存储电容的第三极板73(即第一存储电容的第二端)和第二存储电容的第二极板72(即第二存储电容的第二端)具有相同的电位，第二连接电极42可以作为像素驱动电路的第五节点N5。
在示例性实施方式中，第三连接电极43的形状可以为矩形状，可以位于第一参考信号线91和第一电源连接线68之间，第三连接电极43通过第三过孔V3与第四有源层的第一区连接。在示例性实施方式中，第三连接电极43可以作为第四晶体管T4的第一极，被配置为与后续形成的数据信号线连接。
在示例性实施方式中，第四连接电极44的形状可以为矩形状，可以位于 第五扫描信号线65与第二初始信号线82之间，第四连接电极44通过第五过孔V5与第五有源层的第一区连接。在示例性实施方式中，第四连接电极44可以作为第五晶体管T5的第一极，被配置为与后续形成的第一电源线连接。
在示例性实施方式中，第五连接电极45的形状可以为“L”字形状，可以位于第五扫描信号线65与第二初始信号线82之间，第五连接电极45通过第六过孔V6与第六有源层的第二区(也是第七有源层的第二区)连接。在示例性实施方式中，第五连接电极45可以作为第六晶体管T6的第二极和第七晶体管T7的第二极，被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，第六连接电极46的形状可以为主体部分沿着第一方向X延伸的条形状，可以位于第五扫描信号线65与第二初始信号线82之间，第六连接电极46的第一端通过第八过孔V8与第八有源层的第一区连接，第六连接电极46的第二端通过第二十二过孔V22与第二参考连接块92-1连接。在示例性实施方式中，第六连接电极46可以作为第八晶体管T8的第一极，由于第二参考连接块92-1与第二参考信号线92连接，因而实现了第二参考信号线92连接第八晶体管T8的第一极，第n单元行中的第二参考信号线92可以将第二参考信号写入第n-1单元行中的第八晶体管T8的第一极。
在示例性实施方式中，第七连接电极47的形状可以为主体部分沿着第一方向X延伸的条形状，可以位于第五扫描信号线65与第二初始信号线82之间，第七连接电极47的第一端通过第十七过孔V17与第五栅电极25连接，第七连接电极47的第二端通过第二十过孔V20与第一发光连接块31-1连接。由于第一发光连接块31-1与第一发光信号线31连接，因而实现了第一发光信号线31连接第五晶体管T5的第五栅电极25，第一发光信号线31可以控制第五晶体管T5的导通和断开。
在示例性实施方式中，第八连接电极48的形状可以为主体部分沿着第一方向X延伸的条形状，可以位于第五扫描信号线65与第二初始信号线82之间，第八连接电极48的第一端通过第十八过孔V18与第六栅电极26连接，第八连接电极48的第二端通过第二十一过孔V21与第二发光连接块32-1连接。由于第二发光连接块32-1与第二发光信号线32连接，因而实现了第二发光信号线32连接第六晶体管T6的第六栅电极26，第二发光信号线32可 以控制第六晶体管T6的导通和断开。
在示例性实施方式中，第九连接电极49的形状可以为主体部分沿着第一方向X延伸的条形状，可以位于第五扫描信号线65与第二初始信号线82之间，第九连接电极49的第一端通过第一过孔V1与第一有源层的第一区连接，第九连接电极49的第二端通过第二十三过孔V23与第一初始连接块81-1连接。由于第一初始连接块81-1与第一初始信号线81连接，因而实现了第一初始信号线81连接第一晶体管T1的第一极，第一初始信号线81可以将第一初始信号写入第一晶体管T1的第一极。
(16)形成第五绝缘层图案。在示例性实施方式中，形成第五绝缘层图案可以包括：在形成前述图案的基底上，沉积第五绝缘薄膜，采用图案化工艺对第五绝缘薄膜进行图案化，形成覆盖第三导电层的第五绝缘层，每个电路单元中设置有多个过孔，如图12所示。
在示例性实施方式中，显示基板中每个电路单元的多个过孔至少包括：第三十一过孔V31、第三十二过孔V32、第三十三过孔V33、第三十四过孔V34和第三十五过孔V35。
在示例性实施方式中，第三十一过孔V31在基底上的正投影位于第三连接电极43在基底上的正投影的范围之内，第三十一过孔V31内的第五绝缘层被去掉，暴露出第三连接电极43的表面，第三十一过孔V31被配置为使后续形成的数据信号线通过该过孔与第三连接电极43连接。
在示例性实施方式中，第三十二过孔V32在基底上的正投影位于第四连接电极44在基底上的正投影的范围之内，第三十二过孔V32内的第五绝缘层被去掉，暴露出第四连接电极44的表面，第三十二过孔V32被配置为使后续形成的第一电源线通过该过孔与第四连接电极44连接。
在示例性实施方式中，第三十三过孔V33在基底上的正投影位于第五连接电极45在基底上的正投影的范围之内，第三十三过孔V33内的第五绝缘层被去掉，暴露出第五连接电极45的表面，第三十三过孔V33被配置为使后续形成的阳极连接电极通过该过孔与第五连接电极45连接。
在示例性实施方式中，第三十四过孔V34在基底上的正投影位于第一参 考信号线91的第一参考连接块91-1在基底上的正投影的范围之内，第三十四过孔V34内的第五绝缘层被去掉，暴露出第一参考连接块91-1的表面，第三十四过孔V34被配置为使后续形成的参考信号连接线通过该过孔与第一参考连接块91-1连接。
在示例性实施方式中，第三十五过孔V35在基底上的正投影位于第一电源连接线68的第一电源连接块68-1在基底上的正投影的范围之内，第三十五过孔V35内的第五绝缘层被去掉，暴露出第一电源连接块68-1的表面，第三十五过孔V35被配置为使后续形成的第一电源线通过该过孔与第一电源连接块68-1连接。
在示例性实施方式中，至少一个电路单元中，还可以包括第三十六过孔V36。第三十六过孔V36在基底上的正投影位于第二电源连接线69的第二电源连接块69-1在基底上的正投影的范围之内，第三十六过孔V36内的第五绝缘层被去掉，暴露出第二电源连接块69-1的表面，第三十六过孔V36被配置为使后续形成的第二电源线通过该过孔与第二电源连接块69-1连接。在示例性实施方式中，第三十六过孔V36可以位于第一电路单元与第二电路单元之间。
(17)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第五绝缘层上的第四导电层，如图13A和13B所示，图13B为图13A中第四导电层的示意图。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，显示基板中每个电路单元的第四导电层图案均可以包括：第一电源线51、数据信号线53、参考信号连接线54和阳极连接电极55。
在示例性实施方式中，第一电源线51、数据信号线53和参考信号连接线54的形状可以为主体部分沿着第二方向Y延伸的条形状，第一电源线51可以位于数据信号线53第一方向X的一侧，参考信号连接线54可以位于第一电源线51第一方向X的一侧，即第一电源线51可以位于数据信号线53和参考信号连接线54之间。
在示例性实施方式中，第一电源线51的形状可以为主体部分沿着第二方向Y延伸的折线状，第一电源线51一方面通过第三十二过孔V32与第四连接电极44连接，另一方面通过第三十五过孔V35与第一电源连接块68-1连接。由于第四连接电极44通过过孔与第五有源层的第一区连接，因而实现了第一电源线51将第一电源信号写入第五晶体管T5的第一极。由于第一电源连接块68-1与第一电源连接线68连接，因而实现了主体部分沿着第一方向X延伸的第一电源连接线68与主体部分沿着第二方向Y延伸的第一电源线51的相互连接，使得第一电源线51和第一电源连接线68在显示基板上形成网状的传输第一电源信号的网状结构，不仅可以有效降低第一电源线51的电阻，减小第一电源信号的压降，而且可以有效提升显示基板中第一电源信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，第一电源线51靠近参考信号连接线54的一侧设置有电源屏蔽块51-1，电源屏蔽块51-1的第一端与第一电源线51连接，电源屏蔽块51-1的第二端向着参考信号连接线54的方向延伸。电源屏蔽块51-1的形状可以为矩形状，电源屏蔽块51-1在基底上的正投影与第一连接电极41在基底上的正投影至少部分交叠。由于第一连接电极41作为像素驱动电路中的第一节点N1，因而恒定电压的电源屏蔽块51-1可以有效屏蔽像素驱动电路中其它信号对第一节点N1的影响，避免了其它信号(如数据电压跳变)影响像素驱动电路的第一节点N1的电位，提高了显示效果。
在示例性实施方式中，第一电源线51和电源屏蔽块51-1可以为相互连接的一体结构。
在示例性实施方式中，电源屏蔽块51-1在基底上的正投影可以包含第一连接电极41在基底上的正投影。
在示例性实施方式中，第一电源线51靠近参考信号连接线54的一侧设置有第三电源连接块51-2。第三电源连接块51-2的形状可以为沿着第一方向X延伸的条形状，第三电源连接块51-2的第一端与第一电源线51连接，第三电源连接块51-2的第二端向着参考信号连接线54的方向延伸后，通过第三十五过孔V35与第一电源连接块68-1连接。
在示例性实施方式中，第一电源线51和第三电源连接块51-2可以为相 互连接的一体结构。
在示例性实施方式中，第一电源线51在基底上的正投影与第二连接电极42在基底上的正投影至少部分交叠。由于第二连接电极42作为像素驱动电路中的第五节点N5，因而恒定电压的第一电源线51可以有效屏蔽像素驱动电路中其它信号对第五节点N5的影响，避免了其它信号影响像素驱动电路的第五节点N5的电位，提高了显示效果。
在示例性实施方式中，第一电源线51可以为非等宽度设计，采用非等宽度设计的第一电源线51不仅可以便于像素结构的布局，而且可以降低第一电源线与数据信号线之间的寄生电容。
在示例性实施方式中，数据信号线53的形状可以为主体部分沿着第二方向Y延伸的直线状，数据信号线53通过第三十一过孔V31与第三连接电极43连接。由于第三连接电极43通过过孔与第四有源层的第一区连接，因而实现了数据信号线53将数据信号写入第四晶体管T4的第一极。
在示例性实施方式中，数据信号线53靠近第一电源线51的一侧设置有数据信号连接块53-1，数据信号连接块53-1的第一端与数据信号线53连接，数据信号连接块53-1的第二端向着第一电源线51的方向延伸。数据信号连接块53-1的形状可以为矩形状。数据信号连接块53-1被配置为通过第三十一过孔V31与第三连接电极43连接。
在示例性实施方式中，参考信号连接线54的形状可以为主体部分沿着第二方向Y延伸的直线状，参考信号连接线54通过第三十四过孔V34与第一参考连接块91-1连接。由于第一参考连接块91-1与第一参考信号线91连接，因而实现了主体部分沿着第一方向X延伸的第一参考信号线91与主体部分沿着第二方向Y延伸的参考信号连接线54的相互连接，使得第一参考信号线91和参考信号连接线54在显示基板上形成网状的传输第一参考信号的网状结构，不仅可以有效降低第一参考信号线的电阻，减小第一参考信号的压降，而且可以有效提升显示基板中第一参考信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，参考信号连接线54靠近数据信号线53的一侧设 置有参考信号连接块54-1，参考信号连接块54-1的第一端与参考信号连接线54连接，参考信号连接块54-1的第二端向着数据信号线53的方向延伸。参考信号连接块54-1的形状可以为矩形状。参考信号连接块54-1被配置为通过第三十四过孔V34与第一参考连接块91-1连接。
在示例性实施方式中，阳极连接电极55的形状可以为矩形状，阳极连接电极55通过第三十三过孔V33与第五连接电极45连接。由于第五连接电极45通过过孔与第六有源层的第二区(也是第七有源层的第二区)连接，因而实现了阳极连接电极55与第六晶体管T6的第二极和第七晶体管T7的第二极连接。在示例性实施方式中，阳极连接电极55被配置为与后续形成的阳极连接，因而可以实现像素驱动电路驱动发光器件。
在示例性实施方式中，阳极连接电极55在基底上的正投影与修复线33在基底上的正投影至少部分交叠。
在示例性实施方式中，至少一个电路单元中还可以包括第二电源线52。第二电源线52的形状可以为主体部分沿着第二方向Y延伸的直线状，第二电源线52通过第三十六过孔V36与第二电源连接块69-1连接。由于第二电源连接块69-1与第二电源连接线69连接，因而实现了主体部分沿着第一方向X延伸的第二电源连接线69与主体部分沿着第二方向Y延伸的第二电源线52的相互连接，使得第二电源线52和第二电源连接线69在显示基板上形成网状的传输第二电源信号的网状结构，不仅可以有效降低第二电源线52的电阻，减小第二电源信号的压降，而且可以有效提升显示基板中第二电源信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，第二电源线52可以位于第一电路单元的参考信号连接线54与第二电路单元的数据信号线53之间。
在示例性实施方式中，第二电源线52设置有第四电源连接块52-1，第四电源连接块52-1的中部与第二电源线52连接，第四电源连接块52-1的第一端向着第一电路单元的参考信号连接线54方向延伸，第四电源连接块52-1的第二端向着第二电路单元的数据信号线53方向延伸。第四电源连接块52-1的形状可以为矩形状。在示例性实施方式中，第四电源连接块52-1被配置为通过第三十六过孔V36与第二电源连接块69-1连接。
在示例性实施方式中，第三导电层的第一电源连接线68可以设置在每个单元行中，第四导电层的第一电源线51可以设置在每个单元列中，多条第一电源线51分别连接多条第一电源连接线68，形成传输第一电源信号的网状结构。
在示例性实施方式中，第三导电层的第一参考信号线91可以设置在每个单元行中，第四导电层的参考信号连接线54可以设置在每个单元列中，多条第一参考信号线91分别连接多条参考信号连接线54，形成传输第一参考信号的网状结构。
在示例性实施方式中，第三导电层的第二电源连接线69可以设置在每个单元行中，第四导电层的第二电源线52可以每隔2个单元列设置一条，多条第二电源线52分别连接多条第二电源连接线69，形成传输第二电源信号的网状结构。
后续制备过程可以包括形成第一平坦层图案，第一平坦层上设置有多个阳极过孔，阳极过孔在基底上的正投影位于阳极连接电极在基底上的正投影的范围之内，阳极过孔内的第一平坦层被去掉，暴露出阳极连接电极的表面，阳极过孔被配置为使后续形成的阳极通过该过孔与阳极连接电极连接。
至此，在基底上制备完成本实施例的驱动电路层。在示例性实施方式中，制备完成驱动电路层后，可以在驱动电路层上依次制备发光结构层和封装结构层，这里不再赘述。
图14为本公开示例性实施例另一种显示基板平面结构示意图，示意了显示基板中3个电路单元(第一电路单元、第二电路单元和第三电路单元)中像素驱动电路的结构。如图14所示，本示例性实施例像素驱动电路的主体结构与前述实施例基本上相同，所不同的是，本实施例第二电源连接线69位于第一电源连接线68和第四扫描信号线64之间，第一屏蔽电极36与第二电源连接线69为相互连接的一体结构。
图15为图14中第一存储电容和第二存储电容区域的放大图。如图15所示，至少一个电路单元还可以包括第一屏蔽电极36，第一屏蔽电极36与第二电源连接线69连接，第一屏蔽电极36在基底上的正投影与第一晶体管 T1两个栅电极之间的节点在基底上的正投影至少部分交叠，第一屏蔽电极36在基底上的正投影与第二晶体管T2两个栅电极之间的节点在基底上的正投影至少部分交叠。在示例性实施方式中，第一屏蔽电极36被配置为屏蔽数据电压跳变对第一晶体管T1和第二晶体管T2的影响，避免数据电压跳变影响像素驱动电路的正常工作，提高显示效果。
在示例性实施方式中，第一屏蔽电极36可以包括第一子电极36-3和第二子电极36-4。第一子电极36-3的第一端与第二电源连接线69连接，第一子电极36-3的第二端向着远离第二电源连接线69的方向延伸，即沿着第二方向Y反方向延伸。第一子电极36-3的第二端在基底上的正投影与本电路单元中第一晶体管T1两个栅电极之间的节点在基底上的正投影至少部分交叠。第二子电极36-4的第一端与第二电源连接线69连接，第二子电极36-4的第二端向着远离第二电源连接线69的方向延伸，第二子电极36-4的第二端在基底上的正投影与本电路单元中的第二晶体管T2的两个栅电极之间的节点在基底上的正投影至少部分交叠。
在一些可能的示例性实施方式中，第一子电极36-3的中部与第二电源连接线69连接，第一子电极36-3的第一端沿第二方向Y反方向延伸，第一子电极36-3的第二端沿第二方向Y延伸。第一子电极36-3的第一端和第二端在基底上的正投影与本电路单元中第一晶体管T1两个栅电极之间的节点在基底上的正投影至少部分交叠。
在一些可能的示例性实施方式中，第二子电极36-4的中部与第二电源连接线69连接，第二子电极36-4的第一端沿第二方向Y反方向延伸，第二子电极36-4的第二端沿第二方向Y延伸。第二子电极36-4的第一端和第二端在基底上的正投影与本电路单元中的第二晶体管T2的两个栅电极之间的节点在基底上的正投影至少部分交叠。
在示例性实施方式中，第一屏蔽电极36与第二电源连接线69为相互连接的一体结构。
在示例性实施方式中，至少一个电路单元还可以包括第二屏蔽电极37、第三屏蔽电极38和第四屏蔽电极39，第二屏蔽电极37、第三屏蔽电极38和第四屏蔽电极39的形状、位置和连接结构与前述实施例基本上相同。
下面通过显示基板的制备过程进行示例性说明。在示例性实施方式中，以第n单元行中3个电路单元为例，本实施例显示基板的制备过程可以包括如下操作。
(21)依次形成第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层和第四绝缘层图案。半导体层图案可以至少包括第一有源连接线10、第二有源连接线20、第一有源层11至第九有源层19。第一导电层图案可以至少包括第一栅电极21、第二栅电极22、第四栅电极24、第五栅电极25、第六栅电极26、第九栅电极29、第一扫描信号线61、第一存储电容的第一极板71和第二存储电容的第二极板72，第二导电层图案可以至少包括第一发光信号线31、第二发光信号线32、修复线33、第二屏蔽电极37、第三屏蔽电极38、第四屏蔽电极39、第一存储电容的第三极板73、第二存储电容的第四极板74、第一初始信号线81和第二参考信号线92，第四绝缘层上的多个过孔可以至少包括第一过孔V1至第二十三过孔V23。上述图案的位置、结构和连接关系与前述实施例基本上相同，所不同的是，本实施例的第二导电层没有设置第一屏蔽电极。
(22)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，如图16A和图16B所示，图16B为图16A中第三导电层的示意图。
在示例性实施方式中，显示基板中每个电路单元的第三导电层图案可以包括：第一连接电极41至第九连接电极49、第二扫描信号线62、第三扫描信号线63、第四扫描信号线64、第五扫描信号线65、第一电源连接线68、第二电源连接线69、第二初始信号线82和第一参考信号线91。本示例性实施例第三导电层的结构与前述实施例基本上相同，所不同的是，本实施例第二电源连接线69位于第一电源连接线68和第四扫描信号线64之间，第三导电层设置有第一屏蔽电极36，第一屏蔽电极36与第二电源连接线69为相互连接的一体结构。
在示例性实施方式中，第二电源连接线69可以位于第三极板73第二方向Y的一侧，且位于第一电源连接线68和第四扫描信号线64之间。第二电 源连接线69靠近第一电源连接线68的一侧设置有第二电源连接块69-1，第二电源连接块69-1的第一端与第二电源连接线69连接，第二电源连接块69-1的第二端向着靠近第一电源连接线68的方向延伸，第二电源连接块69-1被配置为与后续形成的第二电源线连接。在示例性实施方式中，第二电源连接块69-1可以设置在第一电路单元与第二电路单元之间。
在示例性实施方式中，至少一个电路单元的第三导电层还可以包括第一屏蔽电极36，第一屏蔽电极36与第二电源连接线69连接，第一屏蔽电极36在基底上的正投影与第一晶体管T1两个栅电极之间的半导体层在基底上的正投影至少部分交叠，第一屏蔽电极36在基底上的正投影与第二晶体管T2两个栅电极之间的半导体层在基底上的正投影至少部分交叠。在示例性实施方式中，第一屏蔽电极36被配置为屏蔽数据电压跳变对第一晶体管T1和第二晶体管T2的影响，避免数据电压跳变影响像素驱动电路的正常工作，提高显示效果。
在示例性实施方式中，第一屏蔽电极36可以包括第一子电极36-3和第二子电极36-4，第一子电极36-3和第二子电极36-4的形状可以呈矩形状。第一子电极36-3的第一端与第二电源连接线69连接，第一子电极36-3的第二端向着远离第二电源连接线69的方向延伸，即沿着第二方向Y反方向延伸。第一子电极36-3的第二端在基底上的正投影与本电路单元中第一晶体管T1两个栅电极之间的半导体层在基底上的正投影至少部分交叠。第二子电极36-4的第一端与第二电源连接线69连接，第二子电极36-4的第二端向着远离第二电源连接线69的方向延伸，第二子电极36-4的第二端在基底上的正投影与本电路单元中的第二晶体管T2的两个栅电极之间的半导体层在基底上的正投影至少部分交叠。
在一些可能的示例性实施方式中，第一子电极36-3的中部与第二电源连接线69连接，第一子电极36-3的第一端沿着第二方向Y反方向延伸，第一子电极36-3的第二端沿着第二方向Y延伸。第一子电极36-3的第一端和第二端在基底上的正投影与本电路单元中第一晶体管T1两个栅电极之间的半导体层在基底上的正投影至少部分交叠。
在一些可能示例性实施方式中，第二子电极36-4的中部与第二电源连 接线69连接，第二子电极36-4的第一端沿第二方向Y反方向延伸，第二子电极36-4的第二端沿第二方向Y延伸。第二子电极36-4的第一端和第二端在基底上的正投影与本电路单元中的第二晶体管T2的两个栅电极之间的半导体层在基底上的正投影至少部分交叠。
在示例性实施方式中，第一屏蔽电极36与第二电源连接线69为相互连接的一体结构。
(23)形成第五绝缘层和第四导电层图案，如图14所示。上述图案的位置、结构和连接关系与前述实施例基本上相同，这里不再赘述。
后续制备过程可以包括形成第一平坦层图案，第一平坦层上设置有多个阳极过孔，阳极过孔在基底上的正投影位于阳极连接电极在基底上的正投影的范围之内，阳极过孔内的第一平坦层被去掉，暴露出阳极连接电极的表面，阳极过孔被配置为使后续形成的阳极通过该过孔与阳极连接电极连接。
至此，在基底上制备完成本实施例的驱动电路层。在示例性实施方式中，制备完成驱动电路层后，可以在驱动电路层上依次制备发光结构层和封装结构层，这里不再赘述。
图17为本公开示例性实施例又一种显示基板平面结构示意图，示意了显示基板中3个电路单元(第一电路单元、第二电路单元和第三电路单元)中像素驱动电路的结构。如图17所示，本示例性实施例像素驱动电路的主体结构与前述实施例基本上相同，所不同的是，本实施例第一电源连接线68位于第二电源连接线69和第四扫描信号线64之间，第一屏蔽电极36与第一电源连接线68为相互连接的一体结构。
图18为图17中第一存储电容和第二存储电容区域的放大图。如图18所示，至少一个电路单元还可以包括第一屏蔽电极36，第一屏蔽电极36与第一电源连接线68连接，第一屏蔽电极36在基底上的正投影与第一晶体管T1两个栅电极之间的节点在基底上的正投影至少部分交叠，第一屏蔽电极36在基底上的正投影与第二晶体管T2两个栅电极之间的节点在基底上的正投影至少部分交叠。在示例性实施方式中，第一屏蔽电极36被配置为屏蔽数据电压跳变对第一晶体管T1和第二晶体管T2的影响，避免数据电压跳变影 响像素驱动电路的正常工作，提高显示效果。
在示例性实施方式中，第一屏蔽电极36包括第三子电极36-5和第四子电极36-6。第三子电极36-5的第一端与第一电源连接线68连接，第三子电极36-5的第二端向着远离第一电源连接线68的方向延伸，即沿着第二方向Y反方向延伸。第三子电极36-5的第二端在基底上的正投影与本电路单元中第一晶体管T1两个栅电极之间的节点在基底上的正投影至少部分交叠。第四子电极36-6的第一端与第一电源连接线68连接，第四子电极36-6的第二端向着远离第一电源连接线68的方向延伸，第四子电极36-6的第二端在基底上的正投影与本电路单元中的第二晶体管T2的两个栅电极之间的节点在基底上的正投影至少部分交叠。
在一些可能的示例性实施方式中，第三子电极36-5的中部与第一电源连接线68连接，第三子电极36-5的第一端沿第二方向Y反方向延伸，第三子电极36-5的第二端沿第二方向Y延伸。第三子电极36-5的第一端和第二端在基底上的正投影与本电路单元中第一晶体管T1两个栅电极之间的节点在基底上的正投影至少部分交叠。
在一些可能的示例性实施方式中，第四子电极36-6的中部与第一电源连接线68连接，第四子电极36-6的第一端沿第二方向Y反方向延伸，第四子电极36-6的第二端沿第二方向Y延伸。第四子电极36-6的第一端和第二端在基底上的正投影与本电路单元中的第二晶体管T2的两个栅电极之间的节点在基底上的正投影至少部分交叠。
在示例性实施方式中，第一屏蔽电极36与第一电源连接线68为相互连接的一体结构。
在示例性实施方式中，至少一个电路单元还可以包括第二屏蔽电极37、第三屏蔽电极38和第四屏蔽电极39，第二屏蔽电极37、第三屏蔽电极38和第四屏蔽电极39的形状、位置和连接结构与前述实施例基本上相同。
下面通过显示基板的制备过程进行示例性说明。在示例性实施方式中，以第n单元行中3个电路单元为例，本实施例显示基板的制备过程可以包括如下操作。
(31)依次形成第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层图案。半导体层图案可以至少包括第一有源连接线10、第二有源连接线20、第一有源层11至第九有源层19。第一导电层图案可以至少包括第一栅电极21、第二栅电极22、第四栅电极24、第五栅电极25、第六栅电极26、第九栅电极29、第一扫描信号线61、第一存储电容的第一极板71和第二存储电容的第二极板72，第二导电层图案可以至少包括第一发光信号线31、第二发光信号线32、修复线33、第二屏蔽电极37、第三屏蔽电极38、第四屏蔽电极39、第一存储电容的第三极板73、第二存储电容的第四极板74、第一初始信号线81和第二参考信号线92，第四绝缘层上的多个过孔可以至少包括第一过孔V1至第二十三过孔V23。上述图案的位置、结构和连接关系与前述实施例基本上相同，所不同的是，本实施例的第二导电层没有设置第一屏蔽电极，第十三过孔V13被配置为使后续形成的连接电极通过该过孔与第四极板74连接。
(32)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，如图19A和图19B所示，图19B为图19A中第三导电层的示意图。
在示例性实施方式中，显示基板中每个电路单元的第三导电层图案可以包括：第一连接电极41至第十连接电极50、第二扫描信号线62、第三扫描信号线63、第四扫描信号线64、第五扫描信号线65、第一电源连接线68、第二电源连接线69、第二初始信号线82和第一参考信号线91，除了第十连接电极50、第一电源连接线68和第二电源连接线69，上述结构的形状、位置和连接结构关系与前述实施例基本上相同，这里不再赘述。
在示例性实施方式中，第一电源连接线68位于第二电源连接线69和第四扫描信号线64之间，第一屏蔽电极36与第一电源连接线68为相互连接的一体结构。
在示例性实施方式中，第一电源连接线68可以位于第三极板73第二方向Y的一侧。第二电源连接线69可以位于第一电源连接线68与第一参考信号线91之间。
在示例性实施方式中，每个电路单元还可以包括第一屏蔽电极36，第一屏蔽电极36与第一电源连接线68连接，第一屏蔽电极36在基底上的正投影与第一晶体管T1两个栅电极之间的半导体层在基底上的正投影至少部分交叠，第一屏蔽电极36在基底上的正投影与第二晶体管T2两个栅电极之间的半导体层在基底上的正投影至少部分交叠。在示例性实施方式中，第一屏蔽电极36被配置为屏蔽数据电压跳变对第一晶体管T1和第二晶体管T2的影响，避免数据电压跳变影响像素驱动电路的正常工作，提高显示效果。
在示例性实施方式中，第一屏蔽电极36包括第三子电极36-5和第四子电极36-6，第三子电极36-5和第四子电极36-6的形状可以呈矩形状。第三子电极36-5的第一端与第一电源连接线68连接，第三子电极36-5的第二端向着远离第一电源连接线68的方向延伸，即沿着第二方向Y反方向延伸。第三子电极36-5的第二端在基底上的正投影与本电路单元中第一晶体管T1两个栅电极之间的半导体层在基底上的正投影至少部分交叠。第四子电极36-6的第一端与第一电源连接线68连接，第四子电极36-6的第二端向着远离第一电源连接线68的方向延伸，第四子电极36-6的第二端在基底上的正投影与本电路单元中的第二晶体管T2的两个栅电极之间的半导体层在基底上的正投影至少部分交叠。
在一些可能的示例性实施方式中，第三子电极36-5的中部与第一电源连接线68连接，第三子电极36-5的第一端沿着第二方向Y反方向延伸，第三子电极36-5的第二端沿着第二方向Y延伸。第三子电极36-5的第一端和第二端在基底上的正投影与本电路单元中第一晶体管T1两个栅电极之间的半导体层在基底上的正投影至少部分交叠。
在一些可能的示例性实施方式中，第四子电极36-6的中部与第一电源连接线68连接，第四子电极36-6的第一端沿第二方向Y反方向延伸，第四子电极36-6的第二端沿第二方向Y延伸。第四子电极36-6的第一端和第二端在基底上的正投影与本电路单元中的第二晶体管T2的两个栅电极之间的半导体层在基底上的正投影至少部分交叠。
在示例性实施方式中，第一屏蔽电极36与第一电源连接线68为相互连接的一体结构。
在示例性实施方式中，第十连接电极50的形状可以为矩形状，可以位于第一参考信号线91与第二电源连接线69之间，第十连接电极50通过第十三过孔V13与第四极板74连接。在示例性实施方式中，第十连接电极50被配置为与后续形成的第一电源线连接。
(33)形成第五绝缘层图案。在示例性实施方式中，形成第五绝缘层图案可以包括：在形成前述图案的基底上，沉积第五绝缘薄膜，采用图案化工艺对第五绝缘薄膜进行图案化，形成覆盖第三导电层的第五绝缘层，每个电路单元中设置有多个过孔，如图20所示。
在示例性实施方式中，显示基板中每个电路单元的多个过孔至少包括：第三十一过孔V31至第三十五过孔V35、第三十七过孔V37，第三十一过孔V31至第三十四过孔V34的位置、结构和连接关系与前述实施例基本上相同，这里不再赘述。
在示例性实施方式中，第三十五过孔V35在基底上的正投影位于第十连接电极50在基底上的正投影的范围之内，第三十五过孔V35内的第五绝缘层被去掉，暴露出第十连接电极50的表面，第三十五过孔V35被配置为使后续形成的第一电源线通过该过孔与第十连接电极50连接。
在示例性实施方式中，第三十七过孔V37在基底上的正投影可以位于第三子电极36-5在基底上的正投影的范围之内，第三十七过孔V37内的第五绝缘层被去掉，暴露出第三子电极36-5的表面，第三十七过孔V37被配置为使后续形成的第一电源线通过该过孔与第一电源连接线68连接。由于第三子电极36-5与第一电源连接线68连接，因而实现了主体部分沿着第一方向X延伸的第一电源连接线68与主体部分沿着第二方向Y延伸的第一电源线51的相互连接，使得第一电源线51和第一电源连接线68在显示基板上形成网状的传输第一电源信号的网状结构，不仅可以有效降低第一电源线51的电阻，减小第一电源信号的压降，而且可以有效提升显示基板中第一电源信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，至少一个电路单元中，还可以包括第三十六过孔V36。第三十六过孔V36在基底上的正投影位于第二电源连接线69的第二电源连接块69-1在基底上的正投影的范围之内，第三十六过孔V36内的第五 绝缘层被去掉，暴露出第二电源连接块69-1的表面，第三十六过孔V36被配置为使后续形成的第二电源线通过该过孔与第二电源连接块69-1连接。在示例性实施方式中，第三十六过孔V36可以位于第一电路单元与第二电路单元之间。
(34)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第五绝缘层上的第四导电层，如图21A和21B所示，图21B为图21A中第四导电层的示意图。
在示例性实施方式中，显示基板中每个电路单元的第四导电层图案均可以包括：第一电源线51、数据信号线53、参考信号连接线54和阳极连接电极55。数据信号线53、参考信号连接线54和阳极连接电极55的位置、结构和连接关系与前述实施例基本上相同，这里不再赘述。
在示例性实施方式中，第一电源线51靠近参考信号连接线54的一侧设置有电源屏蔽块51-1，电源屏蔽块51-1的第一端与第一电源线51连接，电源屏蔽块51-1的第二端向着参考信号连接线54的方向延伸。电源屏蔽块51-1的形状可以为矩形状，电源屏蔽块51-1在基底上的正投影与第一连接电极41在基底上的正投影至少部分交叠。由于第一连接电极41作为像素驱动电路中的第一节点N1，因而恒定电压的电源屏蔽块51-1可以有效屏蔽像素驱动电路中其它信号对第一节点N1的影响，避免了其它信号(如数据电压跳变)影响像素驱动电路的第一节点N1的电位，提高了显示效果。
在示例性实施方式中，第一电源线51和电源屏蔽块51-1可以为相互连接的一体结构。
在示例性实施方式中，电源屏蔽块51-1在基底上的正投影可以包含第一连接电极41在基底上的正投影。
在示例性实施方式中，第一电源线51靠近参考信号连接线54的一侧设置有第三电源连接块51-2。第三电源连接块51-2的形状可以为沿着第一方向X延伸的条形状，第三电源连接块51-2的第一端与第一电源线51连接，第三电源连接块51-2的第二端向着参考信号连接线54的方向延伸后，通过第 三十五过孔V35与第十连接电极50连接。
在示例性实施方式中，第一电源线51和第三电源连接块51-2可以为相互连接的一体结构。
在示例性实施方式中，显示基板中每个电路单元的第四导电层图案还可以包括第五电源连接块51-3。第五电源连接块51-3的第一端与第一电源线51连接，第五电源连接块51-3的第二端向着本电路单元内数据信号线53方向延伸，第五电源连接块51-3的形状可以为矩形状。第五电源连接块51-3通过第三十七过孔V37与第一电源连接线68连接。由于第五电源连接块51-3与第一电源线51连接，因而实现了主体部分沿着第一方向X延伸的第一电源连接线68与主体部分沿着第二方向Y延伸的第一电源线51的相互连接，使得第一电源线51和第一电源连接线68在显示基板上形成网状的传输第一电源信号的网状结构，不仅可以有效降低第一电源线51的电阻，减小第一电源信号的压降，而且可以有效提升显示基板中第一电源信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
后续制备过程可以包括形成第一平坦层图案，第一平坦层上设置有多个阳极过孔，阳极过孔在基底上的正投影位于阳极连接电极在基底上的正投影的范围之内，阳极过孔内的第一平坦层被去掉，暴露出阳极连接电极的表面，阳极过孔被配置为使后续形成的阳极通过该过孔与阳极连接电极连接。
至此，在基底上制备完成本实施例的驱动电路层。在示例性实施方式中，制备完成驱动电路层后，可以在驱动电路层上依次制备发光结构层和封装结构层，这里不再赘述。
从以上描述的本实施例显示基板的结构以及制备过程可以看出，本公开实施例通过设置第一电源连接线、第二电源连接线、第一电源线和第二电源线，第一电源线与第一电源连接线相互连接，使得第一电源线和第一电源连接线在显示基板上形成网状的传输第一电源信号的网状结构，第二电源线与第二电源连接线相互连接，使得第二电源线和第二电源连接线在显示基板上形成网状的传输第二电源信号的网状结构，不仅可以有效降低第一电源线和第二电源线的电阻，减小第一电源信号和第二电源信号的压降，而且可以有效提升显示基板中第一电源信号和第二电源信号的均一性，提高了显示品质 和显示质量。本公开实施例通过设置屏蔽电极与具有恒定电位的第一电源连接线或者第二电源连接线连接，可以对双栅结构的晶体管两个栅电极之间的节点进行有效屏蔽，保证像素驱动电路的正常工作，提高显示效果。
本公开实施例通过设置第一参考信号线和参考信号连接线，且第一参考信号线与参考信号连接线相互连接，使得第一参考信号线和参考信号连接线在显示基板上形成网状的传输第一参考信号的网状结构，不仅可以有效降低第一参考信号线的电阻，减小第一参考信号的压降，而且可以有效提升显示基板中第一参考信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
本公开实施例通过设置半导体层的第一有源连接线和第三导电层的第一参考信号线构成双层结构的信号线，可以有效减小参考信号的压降，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
本公开实施例通过设置第一屏蔽电极、第二屏蔽电极、第三屏蔽电极和第四屏蔽电极，可以屏蔽数据电压跳变对第一晶体管T1、第二晶体管T2、第四晶体管T4、第九晶体管T9和关键节点的影响，避免数据电压跳变影响像素驱动电路的正常工作，提高显示效果。
本公开实施例通过设置第一电源线和电源屏蔽块屏蔽像素驱动电路的第一节点N1和第五节点N5，有效避免了其它信号影响像素驱动电路的第一节点N1和第五节点N5的电位，提高了显示效果。
本公开实施例通过将第二电源连接线与第一初始信号线重叠设置，使得走线布局更加合理。
本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性基底可以为但不限于玻璃、石英中的一种或多种，柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材 料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层，第五绝缘层称为钝化(PVX)层。第一平坦层可以采用有机材料，如树脂等。有源层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
本公开还提供一种显示装置，显示装置包括前述任一实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在 不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种显示基板，包括设置在基底上的驱动电路层以及设置在所述驱动电路层远离所述基底一侧的发光结构层，所述驱动电路层至少包括多个电路单元、沿着第一方向延伸的至少一条第一电源连接线和至少一条第二电源连接线、沿着第二方向延伸的至少一条第一电源线和至少一条第二电源线，至少一个电路单元包括像素驱动电路，所述第一电源线与所述像素驱动电路连接，所述第一电源线被配置为向所述像素驱动电路持续提供高电平信号，所述发光结构层至少包括多个发光单元，至少一个发光单元包括阴极，所述第二电源线与所述阴极连接，所述第二电源线被配置为向所述阴极持续提供低电平信号；所述第一电源线与所述第一电源连接线连接，形成传输第一电源信号的网状结构，所述第二电源线与所述第二电源连接线连接，形成传输第二电源信号的网状结构，所述第一方向与所述第二方向交叉；
    所述像素驱动电路包括第一屏蔽电极和至少一个双栅结构的晶体管，所述第一屏蔽电极在所述基底上的正投影与所述双栅结构的晶体管两个栅电极之间的节点在所述基底上的正投影至少部分交叠；所述第一屏蔽电极与所述第一电源连接线相连接；或者，所述第一屏蔽电极与所述第二电源连接线相连接。
  2. 如权利要求1所述的显示基板，其中，所述至少一个双栅结构的晶体管包括第一初始化晶体管和补偿晶体管，所述第一初始化晶体管的第一极与第一初始信号线连接，所述补偿晶体管的第一极与所述第一初始化晶体管的第二极连接，所述第一屏蔽电极在所述基底上的正投影与所述第一初始化晶体管两个栅电极之间的节点在所述基底上的正投影至少部分交叠，所述第一屏蔽电极在所述基底上的正投影与所述补偿晶体管两个栅电极之间的节点在所述基底上的正投影至少部分交叠。
  3. 如权利要求2所述的显示基板，其中，所述第一屏蔽电极与所述第二电源连接线为相互连接的一体结构。
  4. 如权利要求3所述的显示基板，其中，所述第二电源连接线位于所述第一电源连接线靠近所述第一初始化晶体管和补偿晶体管的一侧。
  5. 如权利要求4所述的显示基板，其中，所述第一屏蔽电极至少包括第一子电极和第二子电极，所述第一子电极的第一端与所述第二电源连接线连接，所述第一子电极的第二端向着靠近所述第一电源连接线的方向延伸，所述第一子电极的第二端在所述基底上的正投影与所述第一初始化晶体管两个栅电极之间的节点在基底上的正投影至少部分交叠；所述第二子电极的第一端与所述第二电源连接线连接，所述第二子电极的第二端向着靠近所述第一电源连接线的方向延伸，所述第二子电极的第二端在所述基底上的正投影与所述补偿晶体管两个栅电极之间的节点在所述基底上的正投影至少部分交叠。
  6. 如权利要求2所述的显示基板，其中，所述第一屏蔽电极与所述第一电源连接线为相互连接的一体结构。
  7. 如权利要求6所述的显示基板，其中，所述第一电源连接线位于所述第二电源连接线靠近所述第一初始化晶体管和补偿晶体管的一侧。
  8. 如权利要求7所述的显示基板，其中，所述第一屏蔽电极至少包括第三子电极和第四子电极，所述第三子电极的第一端与所述第一电源连接线连接，所述第三子电极的第二端向着靠近所述第二电源连接线的方向延伸，所述第三子电极的第二端在所述基底上的正投影与所述第一初始化晶体管两个栅电极之间的节点在基底上的正投影至少部分交叠；所述第四子电极的第一端与所述第一电源连接线连接，所述第四子电极的第二端向着靠近所述第二电源连接线的方向延伸，所述第四子电极的第二端在所述基底上的正投影与所述补偿晶体管两个栅电极之间的节点在所述基底上的正投影至少部分交叠。
  9. 如权利要求2所述的显示基板，其中，所述像素驱动电路还包括第一存储电容和第二存储电容，所述第一存储电容至少包括第一极板和第三极板，所述第一极板在所述基底上的正投影与所述第三极板在所述基底上的正投影至少部分交叠；所述第二存储电容至少包括第二极板和第四极板，所述第二极板在所述基底上的正投影与所述第四极板在所述基底上的正投影至少部分交叠；所述第二极板与所述第三极板连接，所述第四极板与所述第一电源连接线连接，所述第一屏蔽电极与所述第四极板连接。
  10. 如权利要求9所述的显示基板，其中，所述第一屏蔽电极与所述第四极板为相互连接的一体结构。
  11. 如权利要求9所述的显示基板，其中，所述第一屏蔽电极包括第一延伸段和第一屏蔽段；所述第一延伸段的形状为沿着所述第二方向延伸的条形状，所述第一屏蔽段的形状为沿着所述第一方向延伸的条形状；所述第一延伸段的第一端与所述第四极板连接，所述第一延伸段的第二端与所述第一屏蔽段连接；所述第一屏蔽段包括第一屏蔽端和第二屏蔽端，所述第一屏蔽端在所述基底上的正投影与本电路单元中所述第一初始化晶体管两个栅电极之间的节点在基底上的正投影至少部分交叠，所述第二屏蔽端在所述基底上的正投影与相邻所述电路单元中的所述补偿晶体管两个栅电极之间的节点在所述基底上的正投影至少部分交叠。
  12. 如权利要求1所述的显示基板，其中，所述至少一个双栅结构的晶体管还包括数据写入晶体管和第一参考晶体管，所述数据写入晶体管的第一极与数据信号线连接，所述第一参考晶体管的第一极与第一参考信号线连接，所述数据写入晶体管的第二极和所述第一参考晶体管的第二极连接；
    所述像素驱动电路还包括第二屏蔽电极，所述第二屏蔽电极设置在所述数据写入晶体管的第一极与所述数据写入晶体管的第二极之间。
  13. 如权利要求1所述的显示基板，其中，所述至少一个双栅结构的晶体管还包括数据写入晶体管和第一参考晶体管，所述数据写入晶体管的第一极与数据信号线连接，所述第一参考晶体管的第一极与第一参考信号线连接，所述数据写入晶体管的第二极和所述第一参考晶体管的第二极连接；
    所述像素驱动电路还包括第三屏蔽电极和第四屏蔽电极，所述第三屏蔽电极在所述基底上的正投影与所述数据写入晶体管两个栅电极之间的节点在基底上的正投影至少部分交叠，所述第四屏蔽电极在所述基底上的正投影与所述第一参考晶体管两个栅电极之间的节点在基底上的正投影至少部分交叠。
  14. 如权利要求2所述的显示基板，其中，所述第二电源连接线在所述基底的正投影与所述第一初始信号线在所述基底的正投影至少部分交叠。
  15. 如权利要求1至14任一所述的显示基板，其中，在垂直于显示基板的平面上，所述驱动电路层包括多个导电层；所述第一电源线和所述第一电源连接线设置在不同的导电层中，所述第一电源线与所述第一电源连接线通过过孔连接；所述第二电源线和所述第二电源连接线设置在不同的导电层中，所述第二电源线与所述第二电源连接线通过过孔连接。
  16. 如权利要求15所述的显示基板，其中，所述第一电源连接线和所述第二电源连接线同层设置，所述第一电源线和所述第二电源线同层设置。
  17. 如权利要求15所述的显示基板，其中，所述多个导电层至少包括沿着远离所述基底方向依次设置的第一导电层、第二导电层、第三导电层和第四导电层；所述第一电源连接线和所述第二电源连接线设置在所述第三导电层中，所述第一电源线和所述第二电源线设置在所述第四导电层中。
  18. 如权利要求1至14任一所述的显示基板，其中，在垂直于显示基板的平面上，所述驱动电路层包括多个导电层；所述多个导电层至少包括沿着远离所述基底方向依次设置的第一导电层、第二导电层、第三导电层；所述第一屏蔽电极设置在所述第二导电层中，或者，所述第一屏蔽电极设置在所述第三导电层中。
  19. 如权利要求18所述的显示基板，其中，所述像素驱动电路还包括第一存储电容和第二存储电容，所述第一存储电容至少包括第一极板和第三极板，所述第一极板在所述基底上的正投影与所述第三极板在所述基底上的正投影至少部分交叠；所述第二存储电容至少包括第二极板和第四极板，所述第二极板在所述基底上的正投影与所述第四极板在所述基底上的正投影至少部分交叠；所述第一极板和所述第二极板设置在所述第一导电层中，所述第三极板和所述第四极板设置在所述第二导电层中。
  20. 一种显示装置，其中，包括如权利要求1至19任一所述的显示基板。
PCT/CN2023/096186 2023-05-25 2023-05-25 显示基板及显示装置 Ceased WO2024239304A1 (zh)

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