Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
  • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
  • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Definitions

• This disclosure relates to a semiconductor integrated circuit device, and in particular to a layout configuration of an IO cell equipped with an input/output circuit for exchanging signals with the outside of the semiconductor integrated circuit device.
• the IO cells that make up semiconductor integrated circuit devices and exchange signals with the outside world are generally equipped with output buffers and ESD (Electrostatic Discharging) protection circuits. Furthermore, with the miniaturization of semiconductor integrated circuit devices in recent years, the demand for higher speeds is becoming ever greater.
• ESD Electrostatic Discharging
• Patent Document 1 discloses a technique for providing wiring on the back surface of a substrate directly below a transistor and connecting the source/drain of the transistor to the wiring, in order to increase the integration density of semiconductor integrated circuit devices.
• Patent Document 1 in a configuration in which wiring is provided directly under a transistor, there is no disclosure of a specific layout structure for a circuit that passes a large current, such as an output circuit in an input/output circuit. In addition, there is no disclosure of a specific layout structure for an ESD protection circuit.
• This disclosure provides a specific layout structure for a circuit that passes a large current and an ESD protection circuit in a semiconductor integrated circuit device having a configuration in which wiring is provided directly under a transistor.
• a semiconductor integrated circuit device includes a first output transistor section including a first transistor of a first conductivity type connected between a first power supply that supplies a first power supply voltage and an output terminal, a first power supply wiring that supplies the first power supply voltage, and an output wiring that is connected to the output terminal, the first output transistor section constituting the channel, source, and drain of the first transistor, and including a first active region of the first conductivity type having a nanosheet as a channel, the first power supply wiring is arranged in a wiring layer on the back side of the first transistor so as to overlap the first active region in a planar view, and is connected via a via to the underside of a portion of the first active region that serves as the source of the first transistor, and the output wiring is arranged in the same wiring layer as the first power supply wiring so as to overlap the first active region in a planar view, and is connected via a via to the underside of a portion of the first active region that serves as the drain of the first transistor.
• the first output transistor section which includes a first transistor connected between a first power supply and an output terminal, includes a first active region that constitutes the channel, source, and drain of the first transistor.
• the first active region has a nanosheet as a channel.
• the first power supply wiring and the output wiring are arranged in a wiring layer on the back side of the first transistor so as to overlap the first active region in a planar view.
• the first power supply wiring is connected through a via to the underside of the portion of the first active region that serves as the source of the first transistor, and the output wiring is connected through a via to the underside of the portion of the first active region that serves as the drain of the first transistor.
• a semiconductor integrated circuit device includes an ESD (Electrostatic Discharge) protection diode connected between a first power supply that supplies a first power supply voltage and an output terminal, a first power supply wiring that supplies the first power supply voltage, and an output wiring connected to the output terminal, the ESD protection diode forming one of the anode and cathode terminals, a first active region of a first conductivity type having a first nanosheet, and a second active region of a second conductivity type having a second nanosheet that forms the other of the anode and cathode terminals, the first power supply wiring is arranged in a wiring layer on the back side of the first and second active regions so as to overlap the first active region in a planar view, and is connected to the lower surface of the portion of the first active region that sandwiches the first nanosheet through a via, and the output wiring is arranged in the same wiring layer as the first power supply wiring so as to overlap the second active region in a planar view, and is connected
• ESD Electrostatic Discharge
• the ESD protection diode connected between the first power supply and the output terminal includes a first active region of a first conductivity type constituting one of the anode and cathode terminals, and a second active region of a second conductivity type constituting the other of the anode and cathode terminals.
• the first and second active regions have nanosheets.
• the first power supply wiring and the output wiring are arranged in a wiring layer on the rear side of the first and second active regions.
• the first power supply wiring is connected through a via to the underside of the portion of the first active region that sandwiches the nanosheet
• the output wiring is connected through a via to the underside of the portion of the second active region that sandwiches the nanosheet.
• a semiconductor integrated circuit device includes a first output transistor section including a first transistor of a first conductivity type connected between a first power supply that supplies a first power supply voltage and a first node, a protective resistor connected between an output terminal and the first node, and a first power supply wiring that supplies the first power supply voltage, the first output transistor section constituting the channel, source, and drain of the first transistor, and including a first active region of the first conductivity type having a nanosheet as a channel, the first power supply wiring is arranged in a wiring layer on the back side of the first transistor so as to overlap the first active region in a planar view, and is connected to the underside of a portion of the first active region that serves as the source of the first transistor through a via, and the protective resistor is formed in an upper layer of the first active region, one end of which is connected to a portion of the first active region that serves as the drain of the first transistor, and the other end of which is connected to an output wiring that is connected to the
• the first output transistor section which includes a first transistor connected between a first power supply and a first node, includes a first active region that constitutes the channel, source, and drain of the first transistor.
• the first active region has a nanosheet as a channel.
• the first power supply wiring is disposed in a wiring layer on the back side of the first transistor, and is connected to the underside of the portion of the first active region that serves as the source of the first transistor through a via.
• the resistive element connected between the output terminal and the first node is formed in an upper layer of the first active region, with one end connected to the portion of the first active region that serves as the drain of the first transistor, and the other end connected to the output wiring that is connected to the output terminal. This allows a large current to flow to the output terminal without expanding the layout area.
• a circuit that passes a large current and an ESD protection circuit can be realized in a small area.
• FIG. 1 is a plan view showing a schematic overall configuration of a semiconductor integrated circuit device according to an embodiment; 1 is a circuit diagram of an output circuit according to a first embodiment; 1.
• Outline Example of IO Cell Layout in First Embodiment FIG. 4 is a plan view showing the layout of the output transistor N1 in FIG.
• FIG. 4 is a plan view showing the layout of the output transistor N1 in FIG. 6A and 6B are cross-sectional views of the layouts of FIGS. 4 and 5.
• 1A and 1B are diagrams illustrating another example of the configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.
• FIG. 4 is a plan view showing the layout of the output transistor P1 in FIG.
• FIG. 4 is a plan view showing the layout of the output transistor P1 in FIG.
• FIG. 4 is a plan view showing the layout of the diode 1a in FIG. 3;
• FIG. 4 is a plan view showing the layout of the diode 1a in FIG. 3; 10 and 11.
• (a) and (b) are cross-sectional views of the layout of FIG.
• FIG. 4 is a plan view showing the layout of the diode 1b in FIG.
• FIG. 4 is a plan view showing the layout of the diode 1b in FIG. 13 is a circuit diagram of an output circuit according to a second embodiment of the present invention; 13.
• FIG. 17 is a plan view showing the layout of the output transistor N1 in FIG.
• FIG. 17 is a plan view showing the layout of the output transistor N1 in FIG.
• FIG. 17 is a plan view showing the layout of the output transistor N1 in FIG.
• FIG. 17 is a plan view showing the layout of the output transistor N1 in FIG.
• FIG. 17 is a plan view showing the layout of the output transistor P1 in FIG.
• FIG. 17 is a plan view showing the layout of the output transistor P1 in FIG.
• FIG. 17 is a plan view showing the layout of the diode 1a in FIG. 16;
• FIG. 17 is a plan view showing the layout of the diode 1b in FIG.
• FIG. 13 is a circuit diagram of an output circuit according to a modified example of the second embodiment. 13 is a schematic example of an IO cell layout according to a modification of the second embodiment.
• VDDIO and “VSS” refer to the power supply voltage or the power supply itself.
• the transistors are formed on a P-type substrate and an N-type well.
• the transistors may be formed on a P-type well or on an N-type substrate.
• FIG. 1 is a plan view showing a schematic overall configuration of a semiconductor integrated circuit device according to an embodiment.
• the semiconductor integrated circuit device 1 shown in FIG. 1 includes a core region 2 in which an internal core circuit is formed, and an IO region 3 provided between the core region 2 and a chip edge in which an interface circuit (IO circuit) is formed.
• an IO cell row 10A is provided so as to surround the peripheral portion of the semiconductor integrated circuit device 1 in a ring shape.
• a plurality of IO cells 10 constituting an interface circuit are arranged in the IO cell row 10A.
• a plurality of external connection pads are arranged in the semiconductor integrated circuit device 1.
• the external connection pads are provided on the back side of the semiconductor chip.
• the IO cell row 10A may be provided in a part of the peripheral portion of the semiconductor integrated circuit device 1.
• the IO cells 10 include signal IO cells and power IO cells.
• the signal IO cells include circuits necessary for transmitting signals between the outside of the semiconductor integrated circuit device 1 or between the core region 2, such as a level shifter circuit, an output buffer circuit, and an ESD protection circuit.
• the power IO cells supply each power source supplied to the external connection pads to the inside of the semiconductor integrated circuit device 1, and include an ESD protection circuit, etc.
• FIG. 2 is a circuit diagram of the output circuit 11 included in the IO cell 10. Note that the actual output circuit includes circuit elements other than those shown in FIG. 2, but these are omitted from FIG. 2.
• the output circuit 11 shown in FIG. 2 includes an external output terminal PAD, output transistors P1 and N1, and ESD (Electrostatic Discharge) protection diodes 1a and 1b.
• the output transistor P1 is a P-conductivity type transistor
• the output transistor N1 is an N-conductivity type transistor.
• the output transistors P1 and N1 output an output signal to the external output terminal PAD according to the signal received at their gates.
• the source of the output transistor P1 is connected to VDDIO, and the drain is connected to the external output terminal PAD.
• the source of the output transistor N1 is connected to VSS, and the drain is connected to the external output terminal PAD.
• ESD protection diode 1a is provided between VSS and the external output terminal PAD, with the anode connected to VSS and the cathode connected to the external output terminal PAD.
• ESD protection diode 1b is provided between VDDIO and the external output terminal PAD, with the anode connected to the external output terminal PAD and the cathode connected to VDDIO.
• FIG. 3 is an example of an outline of the layout of an IO cell.
• the layout in FIG. 3 corresponds to IO cell 10a, which is one of the IO cells 10 lined up on the bottom side of the semiconductor integrated circuit device 1 in FIG. 1.
• the X direction (corresponding to the first direction) is the direction along the outer side of the semiconductor integrated circuit device 1, and is the direction in which the multiple IO cells 10 are lined up.
• the Y direction (corresponding to the second direction) is the direction perpendicular to the X direction.
• An IO cell generally has a high power supply voltage region that includes an ESD protection circuit and an output buffer for outputting signals to the outside of the semiconductor integrated circuit device, and a low power supply voltage region that includes circuits for inputting and outputting signals to the inside of the semiconductor integrated circuit device.
• the IO cell 10a in FIG. 3 is divided into a low power supply voltage region 6 and a high power supply voltage region 7 in the Y direction.
• the low power supply voltage region 6 is on the core region 2 side
• the high power supply voltage region 7 is on the chip edge side.
• the low power supply voltage region 6 is located close to the output transistors N1 and P1, and includes, for example, a circuit that generates a signal that is input to the gates of the output transistors N1 and P1.
• the IO cell 10a shown in FIG. 3 is configured with the output circuit 11 of FIG. 2.
• the ESD protection diode 1a, the ESD protection diode 1b, the output transistor P1, and the output transistor N1 are arranged in this order from the chip edge.
• the arrangement of the ESD protection diodes 1a, 1b and the output transistors P1, N1 is not limited to that shown in FIG. 3.
• the positions of the output transistor P1 and the output transistor N1 may be interchanged, and the positions of the ESD protection diode 1a and the ESD protection diode 1b may be interchanged.
• FIG. 4 shows the structure of the BM0 (Backside Metal 0) layer, the BM1 (Backside Metal 1) layer, and the BM2 (Backside Metal 2) layer, which are wiring layers provided on the back surface of the semiconductor chip on which the transistor is formed.
• the BM1 layer is located below the BM0 layer, i.e., farther from the transistor, and the BM2 layer is located below the BM1 layer, i.e., farther from the transistor.
• FIG. 5 shows the structure of the BM0 wiring layer and its upper layer.
• FIG. 6 is a cross-sectional view of the layout of FIG. 4 and FIG. 5, where (a) shows the cross-sectional structure along the line X1-X1' and (b) shows the cross-sectional structure along the line Y1-Y1'.
• the direction perpendicular to the substrate surface is the Z direction.
• an output transistor section 30N is formed in the center of the figure, and a guard ring section 40A is formed in a ring shape around it.
• power supply wiring 21 and output wiring 22 extending in the Y direction are arranged in the BM2 layer.
• the power supply wiring 21 supplies a power supply voltage VSS.
• the output wiring 22 is connected to an external output terminal PAD.
• the power supply wiring 21 and the output wiring 22 are arranged with the minimum spacing allowed by the constraints of the manufacturing process.
• power supply wiring 23 and output wiring 24 are arranged, extending in the X-direction.
• the power supply wiring 23 is connected to the power supply wiring 21 in the BM2 layer through a via.
• the output wiring 24 is connected to the output wiring 22 in the BM2 layer through a via.
• the power supply wiring 23 and the output wiring 24 are arranged with the minimum spacing allowed by the constraints of the manufacturing process.
• a power supply wiring 25 and an output wiring 26 are arranged, extending in the Y direction.
• the power supply wiring 25 is connected to the power supply wiring 23 in the BM1 layer through a via.
• the power supply wiring 25 is formed in the guard ring section 40A, and is also formed so as to pass through the output transistor section 30N.
• the output wiring 26 is connected to the output wiring 24 in the BM1 layer through a via.
• the output wiring 26 is formed in the output transistor section 30N.
• an N-type active region 31 extending in the X-direction is formed.
• the active region constitutes the channel, source, and drain of a transistor.
• the active region that constitutes a nanosheet FET has a nanosheet as a channel.
• the portions of the active region that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet. Note that, as will be described later, there are cases in which the active region does not constitute a transistor.
• each active area 31 includes six nanosheets 32.
• Each nanosheet 32 is made up of three overlapping sheets in a plan view and extends in the X direction.
• the part that becomes the source of the transistor overlaps with the power supply wiring 25 in the BM0 layer in a planar view, and is connected to the power supply wiring 25 through a via.
• the part that becomes the drain of the transistor overlaps with the output wiring 26 in the BM0 layer in a planar view, and is connected to the output wiring 26 through a via.
• a gate wiring 33 is formed extending in the Y direction across the five active regions 31.
• the gate wiring 33 surrounds the outer periphery of the nanosheet 32 in the Y and Z directions via a gate insulating film (not shown).
• the gate wiring 33 corresponds to the gate of transistor N1.
• a signal wiring 34 extending in the X direction is arranged.
• the signal wiring 34 is connected to the gate wiring 33 in the output transistor section 30N through a via.
• the signal wiring 34 supplies a signal INN to the gate of transistor N1.
• a P-type active region 41 is formed in the guard ring portion 40A.
• the active region 41 includes nanosheets 42.
• Each nanosheet 42 is made up of three overlapping sheets in a plan view and extends in the X direction. However, the active region 41 does not function as a transistor.
• the portions sandwiching the nanosheet 42 overlap with the power supply wiring 25 in the BM0 layer in a plan view, and are connected to the power supply wiring 25 through vias.
• the active region 41 supplies the power supply voltage VSS supplied from the power supply wiring 25 to the P-type substrate or P-type well.
• the guard ring portion 40A suppresses noise propagation and latch-up between the output transistor portion 30N and the surrounding transistors, etc.
• a gate wiring 43 extending in the Y direction is formed in the active region 41.
• the gate wiring 43 surrounds the outer periphery of the nanosheet 42 in the Y direction and Z direction via a gate insulating film (not shown).
• the gate wiring 43 does not function as a gate of a transistor.
• Local wiring (LI) 44 is arranged extending in the Y direction.
• the local wiring 44 is formed on the upper surface of the active region 41.
• power supply wiring 45 is arranged extending in the X direction.
• the power supply wiring 45 is connected to the local wiring 44, and is also connected to the gate wiring 43. As a result, the power supply voltage VSS is supplied to the gate wiring 43 in the guard ring portion 40A.
• the above configuration provides the following effects.
• the only wiring placed on the back of the transistor is the power supply wiring that supplies VSS and the output wiring that is connected to the external output terminal PAD.
• the power supply wiring and output wiring are laid out to the maximum extent possible. This allows a large current to flow while also suppressing wiring resistance.
• the power supply wiring and output wiring in the BM0 layer are connected to the active region 31 that constitutes the output transistor N1 only through vias. This allows the resistance value to be reduced and allows a large current to flow.
• the output transistor section 30N which includes the transistor N1 connected between the power supply VSS and the external output terminal PAD, includes an active region 31 that constitutes the channel, source, and drain of the transistor N1.
• the active region 31 has a nanosheet 32 as a channel.
• the power supply wiring 25 and the output wiring 26 are arranged in the wiring layer on the back side of the transistor N1 so as to overlap the active region 31 in a planar view.
• the power supply wiring 25 is connected through a via to the underside of the portion of the active region 31 that serves as the source of the transistor N1
• the output wiring 26 is connected through a via to the underside of the portion of the active region 31 that serves as the drain of the transistor N1. This makes it possible to pass a large current through the output terminal without expanding the layout area.
• the power supply wiring 21, 23, 25 and the output wiring 22, 24, 26 are formed in a wiring layer provided on the back surface of the semiconductor chip, this is not limited to the above.
• the power supply wiring and the output wiring may be formed on the back surface of the transistor (active region).
• the back surface of the transistor refers to the side opposite to the side on which the local wiring, metal wiring, etc. connected to the transistor are stacked.
• the power supply wiring 21, 23, 25 and the output wiring 22, 24, 26 may also be formed in multiple wiring layers.
• a wiring layer may be provided even lower than the BM2 layer to form the back wiring.
• the power supply wiring and output wiring formed on the back surface side of the transistor may be formed using a semiconductor chip separate from the semiconductor chip on which the transistor is formed.
• FIG. 7(a) is another configuration example of a semiconductor integrated circuit device according to an embodiment.
• the semiconductor integrated circuit device 100 shown in FIG. 7(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B).
• the above-mentioned IO cells and the like are arranged on chip A.
• Chip B has power wiring and output wiring formed in a wiring layer provided on its surface.
• Chip B is attached to the back side of chip A using bumps or the like.
• FIG. 7(b) shows a cross section of line X1-X1' in the layout of FIGS. 4 and 5 in this configuration example.
• a power supply wiring for supplying VSS and an output wiring connected to an external output terminal PAD are formed in a wiring layer provided on the surface of chip B.
• Power supply wiring 25 in the BM0 layer is connected through a via to a portion that becomes the source of a transistor in active region 31 of chip A.
• Output wiring 26 in the BM0 layer is connected through a via to a portion that becomes the drain of a transistor in active region 31 of chip A.
• This configuration example also provides the same effect as the IO cell described above. Note that in this configuration example, the power supply wiring and output wiring below the BM2 layer may also be formed on chip B.
• This configuration example can also be applied to the layouts described below.
• Figures 8 and 9 are plan views showing details of the layout of the output transistor P1 in Figure 3.
• Figure 8 shows the structure of the BM0-BM2 layer
• Figure 9 shows the structure of the BM0 wiring layer and the layers above it.
• the layouts of Figures 8 and 9 have a P-type conductivity for the active region 36 in the output transistor section 30P, and an N-type conductivity for the active region 46 in the guard ring section 40B.
• the power supply voltage supplied to the portion of the active region 36 that becomes the source of transistor P1 is VDDIO, and the signal supplied to the gate of transistor P1 is INP.
• the layouts of Figures 8 and 9 can be easily understood from the explanation of the layouts of Figures 4 and 5, so a detailed explanation will be omitted here.
• the output wiring 27 in the BM2 layer is continuous with the output wiring 22 in the BM2 layer of the output transistor N1.
• the output transistor section 30P which includes a transistor P1 connected between a power supply VDDIO and an external output terminal PAD, includes an active region 36 that constitutes the channel, source, and drain of the transistor P1.
• the active region 36 has a nanosheet as a channel.
• the power supply wiring 28 and the output wiring 29 are arranged in the wiring layer on the rear side of the transistor P1 so as to overlap the active region 36 in a planar view.
• the power supply wiring 28 is connected through a via to the underside of the portion of the active region 36 that serves as the source of the transistor P1
• the output wiring 29 is connected through a via to the underside of the portion of the active region 36 that serves as the drain of the transistor P1. This makes it possible to pass a large current through the output terminal without expanding the layout area.
• Figures 10 and 11 are plan views showing details of the layout of the ESD protection diode 1a in Figure 3.
• Figure 10 shows the structure of the BM0-BM2 layers.
• Figure 11 shows the structure of the BM0 wiring layer and its upper layers.
• Figure 12 is a cross-sectional view of the layout of Figures 10 and 11, where (a) shows the cross-sectional structure along line X1-X1' and (b) shows the cross-sectional structure along line Y1-Y1'.
• a cathode portion 60 is formed at the top, center, and bottom of the figure, and an anode portion 70 is formed surrounding the cathode portion 60.
• power supply wiring 51 and output wiring 52 extending in the Y direction are arranged in the BM2 layer.
• Power supply wiring 51 supplies a power supply voltage VSS.
• Output wiring 52 is connected to an external output terminal PAD.
• Power supply wiring 51 and output wiring 52 are arranged with the minimum spacing allowed by the constraints of the manufacturing process.
• power supply wiring 53 and output wiring 54 are arranged, extending in the X-direction.
• Power supply wiring 53 is connected to power supply wiring 51 in the BM2 layer through a via.
• Output wiring 54 is connected to output wiring 52 in the BM2 layer through a via.
• Power supply wiring 53 and output wiring 54 are arranged with the minimum spacing allowed by the constraints of the manufacturing process.
• a power supply wiring 55 and an output wiring 56 are arranged, extending in the Y direction.
• the power supply wiring 55 is connected to the power supply wiring 53 in the BM1 layer through a via.
• the power supply wiring 55 is formed in the anode section 70.
• the output wiring 56 is connected to the output wiring 54 in the BM1 layer through a via.
• the output wiring 56 is formed in the cathode section 60.
• an N-type active region 61 extending in the X direction is formed.
• Each active region 61 includes six nanosheets 62.
• Each nanosheet 62 is made up of three overlapping sheets in a plan view and extends in the X direction. However, the active region 61 does not function as a transistor.
• the portion sandwiching the nanosheet 62 overlaps with the output wiring 56 in the BM0 layer in a plan view, and is connected to the output wiring 56 through a via.
• a gate wiring 63 extending in the Y direction is formed in the active region 61.
• the gate wiring 63 surrounds the outer periphery of the nanosheet 62 in the Y direction and Z direction via a gate insulating film (not shown). However, the gate wiring 63 does not function as a gate of a transistor.
• the gate wiring 63 is connected to the active region 61 via a local wiring 64 and an M0 wiring 65.
• each active region 71 includes a nanosheet 72.
• Each nanosheet 72 is made up of three overlapping sheets in a plan view and extends in the X direction. However, the active region 71 does not function as a transistor.
• the portion sandwiching the nanosheet 72 overlaps with the power supply wiring 55 in the BM0 layer in a plan view, and is connected to the power supply wiring 55 through a via.
• a gate wiring 73 extending in the Y direction is formed in the active region 71.
• the gate wiring 73 surrounds the outer periphery of the nanosheet 72 in the Y and Z directions via a gate insulating film (not shown). However, the gate wiring 73 is not the gate of a transistor.
• the gate wiring 73 is connected to the active region 71 via a local wiring 74 and an M0 wiring 75. In other words, the potential of the gate wiring 73 is fixed to VSS.
• the above-mentioned configuration provides the following effects.
• the only wiring arranged on the back surface of the active regions 61, 71 that make up the ESD protection diode 1a is the power supply wiring that supplies VSS and the output wiring that is connected to the external output terminal PAD.
• the power supply wiring and output wiring are laid out to the maximum extent possible. This makes it possible to reduce the wiring resistance and improve the characteristics and capabilities of the ESD protection diode 1a.
• the power supply wiring and output wiring in the BM0 layer are connected to the active regions 61 and 71 that constitute the ESD protection diode 1a only through vias. This allows the resistance value to be reduced, improving the characteristics and capabilities of the ESD protection diode 1a.
• the ESD protection diode 1a connected between the power supply VSS and the external output terminal PAD includes a P-type active region 71 constituting the anode section 70 and an N-type active region 61 constituting the cathode section 60.
• the active region 61 has a nanosheet 62
• the active region 71 has a nanosheet 72.
• the power supply wiring 55 and the output wiring 56 are arranged in a wiring layer on the rear side of the active regions 61 and 71.
• the power supply wiring 55 is connected through a via to the underside of the portion of the active region 71 that sandwiches the nanosheet 72
• the output wiring 56 is connected through a via to the underside of the portion of the active region 61 that sandwiches the nanosheet 62.
• the power supply wiring 51, 53, and 55 and the output wiring 52, 54, and 56 may be formed in multiple wiring layers.
• a wiring layer may be provided even lower than the BM2 layer to form the back wiring.
• Figures 13 and 14 are plan views showing details of the layout of the ESD protection diode 1b in Figure 3.
• Figure 13 shows the structure of the BM0-BM2 layer
• Figure 14 shows the structure of the BM0 wiring layer and the layers above it.
• the positions of the anode and cathode parts are swapped compared to the layouts of Figures 10 and 11. That is, the anode parts 70A are formed at the top, center, and bottom of the figures, and the cathode parts 60A are formed so as to surround the anode parts 70A.
• the conductivity type of the active region 77 in the anode part 70A is P type
• the conductivity type of the active region 67 in the cathode part 60A is N type.
• the power supply voltage supplied to the part of the active region 67 of the cathode part 60A that sandwiches the nanosheet is VDDIO.
• the output wiring 57 in the BM2 layer is continuous with the output wiring 52 in the BM2 layer of the ESD protection diode 1a.
• the output wirings 52 and 57 are also continuous with the output wirings 22 and 27 in the BM2 layer of the output transistors N1 and P1.
• the ESD protection diode 1b connected between the power supply VDDIO and the external output terminal PAD has an N-type active region 67 constituting the cathode section 60A, and a P-type active region 77 constituting the anode section 70A.
• the power supply wiring 58 and the output wiring 59 are arranged in a wiring layer on the rear side of the active regions 67, 77.
• the power supply wiring 58 is connected through a via to the underside of the portion of the active region 67 that sandwiches the nanosheet
• the output wiring 59 is connected through a via to the underside of the portion of the active region 77 that sandwiches the nanosheet. This makes it possible to improve the characteristics and capabilities of the ESD protection diode 1b without expanding the layout area.
• Second Embodiment Fig. 15 is a circuit configuration diagram of an output circuit included in an IO cell 10 in the second embodiment. Note that an actual output circuit includes circuit elements other than those shown in Fig. 15, but these are omitted in Fig. 15.
• the output circuit shown in FIG. 15 includes the external output terminal PAD, output transistors P1 and N1, and ESD protection diodes 1a and 1b of the output circuit 11 shown in FIG. 2, as well as protection resistors Rsn and Rsp.
• the output transistor P1 has a source connected to VDDIO and a drain connected to the external output terminal PAD via a protective resistor Rsp.
• the output transistor N1 has a source connected to VSS and a drain connected to the external output terminal PAD via a protective resistor Rsn.
• the protective resistors Rsp and Rsn are composed of multiple resistive elements formed in a wiring layer formed in the BEOL (Back End of Line: wiring process).
• the node between the output transistor N1 and the protective resistor Rsn is referred to as node A, and the node between the output transistor P1 and the protective resistor Rsp is referred to as node B.
• FIG. 16 is an example of an outline of the layout of an IO cell in this embodiment.
• resistance elements RU are arranged in an array in the XY direction above the region in which ESD protection diode 1a and ESD protection diode 1b are arranged.
• the resistance elements RU are formed in a layer above the M0 wiring layer.
• the resistance elements RU arranged above ESD protection diode 1b are connected to each other to form a protection resistor Rsp.
• the resistance elements RU arranged above ESD protection diode 1a are connected to each other to form a protection resistor Rsn.
• the protective resistor Rsp is connected between the external output terminal PAD and node B, and a wire corresponding to node B extends from the region where the protective resistor Rsp is configured toward the region where the output transistor P1 is arranged.
• the protective resistor Rsn is connected between the external output terminal PAD and node A, and a wire corresponding to node A extends from the region where the protective resistor Rsn is configured toward the region where the output transistor N1 is arranged.
• the positions of the protective resistors Rsp and Rsn on the plane are not limited to those shown in FIG. 16.
• Figures 17 and 18 are plan views showing details of the layout of the output transistor N1 in Figure 16.
• Figure 17 shows the structure of the BM0-BM2 layer
• Figure 18 shows the structure of the BM0 wiring layer and the layers above it. Note that the description of the same configuration as the layouts shown in Figures 4 and 5 may be omitted or simplified.
• power supply wiring 121 extending in the Y direction is arranged in the BM2 layer.
• the power supply wiring 121 supplies the power supply voltage VSS.
• the power supply wiring 121 is arranged at the minimum interval allowed by the constraints of the manufacturing process.
• power supply wiring 122 extending in the X-direction is arranged.
• the power supply wiring 122 is connected to the power supply wiring 121 in the BM2 layer through vias, and supplies the power supply voltage VSS.
• the power supply wiring 122 is arranged with the minimum spacing allowed by the constraints of the manufacturing process.
• a power supply wiring 123 extending in the Y direction is arranged.
• the power supply wiring 123 is connected to the power supply wiring 122 in the BM1 layer through a via, and supplies the power supply voltage VSS.
• all the wiring arranged on the BM0-BM2 layers is power wiring that supplies VSS.
• an N-type active region 131 extending in the X direction is formed.
• the part that becomes the source of the transistor N1 overlaps with the power supply wiring 123 in the BM0 layer in a plan view, and is connected to the power supply wiring 123 through a via.
• the part that becomes the drain of the transistor N1 is connected to a wiring 135 formed in the M0 wiring layer through a via.
• the wiring 135 corresponds to node A.
• the wiring 135 is connected to the protective resistor Rsn through a wiring and a via (not shown).
• one end of the protective resistor Rsn is connected to the part that becomes the drain of the transistor N1 in the active region 131.
• the other end of the protective resistor Rsn is connected to an output wiring (not shown) that is connected to the external output terminal PAD.
• FIGS. 19 and 20 are plan views showing the details of the layout of output transistor P1 in FIG. 16.
• FIG. 19 shows the structure of the BM0-BM2 layers
• FIG. 20 shows the structure of the BM0 wiring layer and the layers above it. Note that descriptions of configurations similar to the layouts shown in FIGS. 8 and 9 may be omitted or simplified.
• power supply wiring 126 extending in the Y direction is arranged in the BM2 layer.
• the power supply wiring 126 supplies the power supply voltage VDDIO.
• the power supply wiring 126 is arranged with the minimum spacing allowed by the constraints of the manufacturing process.
• power supply wiring 127 extending in the X-direction is arranged.
• the power supply wiring 127 is connected to the power supply wiring 126 in the BM2 layer through vias, and supplies the power supply voltage VDDIO.
• the power supply wiring 127 is arranged with the minimum spacing allowed by the constraints of the manufacturing process.
• a power supply wiring 128 extending in the Y direction is arranged.
• the power supply wiring 128 is connected to the power supply wiring 127 in the BM1 layer through a via, and supplies the power supply voltage VDDIO.
• all the wiring arranged on the BM0-BM2 layers is power wiring that supplies VDDIO.
• a P-type active region 136 extending in the X-direction is formed.
• the part of the active region 136 that becomes the source of the transistor P1 overlaps with the power supply wiring 128 in the BM0 layer in a plan view and is connected through a via.
• the part of the active region 136 that becomes the drain of the transistor P1 is connected through a via to a wiring 139 formed in the M0 wiring layer.
• the wiring 139 corresponds to node B.
• the wiring 139 is connected to the protective resistor Rsp through a wiring and a via (not shown). That is, one end of the protective resistor Rsp is connected to the part of the active region 136 that becomes the drain of the transistor P1.
• the other end of the protective resistor Rsp is connected to an output wiring (not shown) that is connected to the external output terminal PAD.
• the above-mentioned configuration provides the following effects.
• the only wiring arranged on the back surface of the transistor is the power supply wiring that supplies VSS and VDDIO. Furthermore, in the BM1 layer and BM2 layer, the power supply wiring is laid out to the maximum extent. As a result, it is possible to pass a larger current than in the configuration shown in the first embodiment, and the wiring resistance can be further suppressed.
• the output transistor section 130N which includes the transistor N1 connected between the power supply VSS and the node A, includes the active region 131 that constitutes the channel, source, and drain of the transistor N1.
• the active region 131 has a nanosheet as a channel.
• the power supply wiring 123 is disposed in a wiring layer on the back side of the transistor N1, and is connected through a via to the underside of the part of the active region 131 that serves as the source of the transistor N1.
• the protective resistor element Rsn which is connected between the external output terminal PAD and the node A, is formed in the upper layer of the active region 131, and has one end connected to the part of the active region 131 that serves as the drain of the transistor N1, and the other end connected to the output wiring that is connected to the external output terminal PAD.
• the output transistor section 130P which includes a transistor P1 connected between the power supply VDDIO and node B, includes an active region 136 that constitutes the channel, source, and drain of the transistor P1.
• the active region 136 has a nanosheet as a channel.
• the power supply wiring 128 is disposed in a wiring layer on the rear side of the transistor P1, and is connected through a via to the underside of the part of the active region 136 that serves as the source of the transistor P1.
• the protective resistor element Rsp which is connected between the external output terminal PAD and node B, is formed in the upper layer of the active region 136, and has one end connected to the part of the active region 136 that serves as the drain of the transistor P1, and the other end connected to the output wiring connected to the external output terminal PAD.
• This configuration allows a large current to flow through the output terminal without increasing the layout area.
• Fig. 21 is a plan view showing the details of the layout of the ESD protection diode 1a in Fig. 16, showing the BM0 wiring layer and the structure of the layers thereover.
• Fig. 22 is a plan view showing the details of the layout of the ESD protection diode 1b in Fig. 16, showing the BM0 wiring layer and the structure of the layers thereover.
• the layout structure of the ESD protection diodes 1a, 1b in this embodiment is the same as the layout structure of the ESD protection diodes 1a, 1b in the first embodiment shown in Figures 10 to 14.
• Figure 21 shows the same configuration as Figure 11, with the letters "PAD” added to the M0 wiring 65 in the cathode section 60.
• the M0 wiring 65 is connected to the protective resistor Rsn via wiring and vias (not shown).
• Figure 22 shows the same configuration as Figure 14, with the letters "PAD” added to the M0 wiring 78 in the anode section 70A.
• the M0 wiring 78 is connected to the protective resistor Rsp via wiring and vias (not shown).
• the same effect as the ESD protection diodes 1a and 1b in the first embodiment can be obtained. Furthermore, since there is no need to provide an area for connecting the protection resistors Rsn and Rsp to the external output terminal PAD, an increase in area is suppressed.
• Fig. 23 is a circuit diagram of an output circuit according to a modified example of the second embodiment.
• the circuit configuration of Fig. 23 is almost the same as the circuit configuration of Fig. 15 in the second embodiment, but the insertion position of the protective resistor is different. That is, in the output circuit of Fig. 23, a protective resistor Rs is provided instead of the protective resistors Rsn and Rsp in Fig. 15.
• the drains of the output transistors P1 and N1 are connected to each other, and the protective resistor Rs is provided between the external output terminal PAD and the drains of the output transistors P1 and N1.
• the node between the drains of the output transistors P1 and N1 and the protective resistor Rs is referred to as a node C.
• FIG. 24 shows an example of an outline of the layout of an IO cell in this modified example.
• the resistance elements RU arranged on the ESD protection diodes 1a and 1b are connected to each other to form a protection resistor Rs.
• the M0 wiring 135 corresponding to node A in the output transistor N1 and the M0 wiring 139 corresponding to node B in the output transistor P1 in the second embodiment both correspond to node C.
• the layout structure of the output transistors N1 and P1 and the ESD protection diodes 1a and 1b is the same as in the second embodiment. Thus, the same effects as in the second embodiment can be obtained.
• the output circuit has both a P-conductivity type transistor and an N-conductivity type output transistor as a single stage transistor, but this is not limited to this and may have a configuration in which multiple stages of transistors, such as two or three stages, are connected in series. Also, the output circuit in the above-mentioned embodiment may be an input/output circuit including an input circuit.
• the present disclosure makes it possible to realize a circuit that passes a large current and an ESD protection circuit in a semiconductor integrated circuit device having a configuration in which wiring is provided directly under a transistor, which is useful for improving the performance of, for example, a SoC (System on Chip).
• SoC System on Chip

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