WO2024201264A1 - 半導体装置、及び半導体装置の作製方法 - Google Patents

半導体装置、及び半導体装置の作製方法 Download PDF

Info

Publication number
WO2024201264A1
WO2024201264A1 PCT/IB2024/052821 IB2024052821W WO2024201264A1 WO 2024201264 A1 WO2024201264 A1 WO 2024201264A1 IB 2024052821 W IB2024052821 W IB 2024052821W WO 2024201264 A1 WO2024201264 A1 WO 2024201264A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
insulating layer
conductive layer
oxide
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2024/052821
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
倉田求
方堂涼太
遠藤俊弥
菊池秋広
太田将志
齋藤暁
國武寛司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2025509043A priority Critical patent/JPWO2024201264A1/ja
Priority to CN202480018717.0A priority patent/CN120958963A/zh
Priority to KR1020257032266A priority patent/KR20250165603A/ko
Publication of WO2024201264A1 publication Critical patent/WO2024201264A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • One aspect of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, or manufacturing methods thereof.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.
  • a CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) that are chipped by processing a semiconductor wafer and have electrodes that serve as connection terminals.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.
  • transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices.
  • ICs integrated circuits
  • Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.
  • Patent Document 1 discloses a low-power consumption CPU that utilizes the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by utilizing the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple overlapping memory cells.
  • Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.
  • One embodiment of the present invention has an object to provide a semiconductor device or storage device having a transistor with good electrical characteristics. Another embodiment of the present invention has an object to provide a semiconductor device or storage device having a transistor with high on-state current. Another embodiment of the present invention has an object to provide a semiconductor device or storage device having a fine transistor. Another embodiment of the present invention has an object to provide a semiconductor device or storage device with high integration. Another embodiment of the present invention has an object to provide a display device with high definition or a high aperture ratio. Another embodiment of the present invention has an object to provide a highly reliable transistor, semiconductor device, display device, or storage device. Another embodiment of the present invention has an object to provide a semiconductor device, display device, or storage device with low power consumption.
  • One aspect of the present invention is a semiconductor device having a transistor, a first insulating layer, and a second insulating layer.
  • the transistor has a first conductive layer, a second conductive layer, a third conductive layer, a third insulating layer, and an oxide semiconductor layer.
  • the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer are stacked in this order.
  • the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have an opening that reaches the first conductive layer.
  • the third insulating layer has a region in the opening that is in contact with a part of the top surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, and a side surface of the second insulating layer.
  • the oxide semiconductor layer has a region that is in contact with a top surface of the first conductive layer, a top surface and a side surface of the third insulating layer, and a top surface of the third conductive layer.
  • the third insulating layer has a portion that protrudes toward the oxide semiconductor layer in the region in contact with the top surface of the first conductive layer.
  • the fourth insulating layer is preferably provided on the oxide semiconductor layer so as to fill the opening.
  • the upper surface of the fourth insulating layer is flat.
  • the oxide semiconductor layer preferably contains one or both of indium and zinc.
  • the first insulating layer preferably contains silicon and nitrogen.
  • the second insulating layer preferably contains silicon and nitrogen.
  • the first insulating layer preferably has a fifth insulating layer, a sixth insulating layer on the fifth insulating layer, and a seventh insulating layer on the sixth insulating layer.
  • the second insulating layer preferably has an eighth insulating layer, a ninth insulating layer on the eighth insulating layer, and a tenth insulating layer on the ninth insulating layer.
  • the fifth insulating layer, the seventh insulating layer, the eighth insulating layer, and the tenth insulating layer preferably each have silicon and nitrogen.
  • the sixth insulating layer and the ninth insulating layer preferably each have silicon and oxygen.
  • the sixth insulating layer preferably has a region that is thicker than each of the fifth insulating layer and the seventh insulating layer.
  • the ninth insulating layer preferably has a region that is thicker than each of the eighth insulating layer and the tenth insulating layer.
  • the oxide semiconductor layer contacts the side of the third conductive layer at the opening.
  • One aspect of the present invention is a method for manufacturing a semiconductor device, which includes forming a first conductive layer, forming a first insulating layer on the first conductive layer, forming a second conductive layer on the first insulating layer, forming a second insulating layer on the second conductive layer, forming a third conductive layer on the second insulating layer, forming a mask layer on the third conductive layer, forming an opening that reaches the first conductive layer in the first insulating layer, the second conductive layer, the second insulating layer, the third conductive layer, and the mask layer, forming a third insulating layer that contacts the sidewall and bottom of the opening, forming a dummy layer on the third insulating layer, processing the third insulating layer and the dummy layer to expose the top surface of the first conductive layer in the area overlapping the opening and to expose the top and side surfaces of the mask layer, removing the mask layer, removing the dummy layer, and forming a semiconductor layer on the first
  • a semiconductor device or storage device having a transistor with good electrical characteristics can be provided.
  • a semiconductor device or storage device having a transistor with a large on-state current can be provided.
  • a semiconductor device or storage device having a fine transistor can be provided.
  • a semiconductor device or storage device with high integration can be provided.
  • a display device with high definition or a high aperture ratio can be provided.
  • a highly reliable transistor, semiconductor device, display device, or storage device can be provided.
  • a semiconductor device, display device, or storage device with low power consumption can be provided.
  • a semiconductor device, display device, or storage device with high operation speed can be provided.
  • a method for manufacturing the above-mentioned transistor, semiconductor device, display device, or storage device can be provided.
  • a novel transistor, semiconductor device, display device, or storage device can be provided.
  • a method for manufacturing the novel transistor, semiconductor device, display device, or storage device can be provided.
  • Fig. 1A is a plan view showing an example of a semiconductor device
  • Figs. 1B to 1E are cross-sectional views showing an example of the semiconductor device.
  • 2A and 2B are perspective views showing an example of a semiconductor device.
  • 3A and 3B are cross-sectional views showing an example of a semiconductor device.
  • 4A and 4B are cross-sectional views showing an example of a semiconductor device.
  • Fig. 5A is a plan view showing an example of a semiconductor device
  • Figs. 5B to 5D are cross-sectional views showing an example of the semiconductor device.
  • 6A and 6B are cross-sectional views showing an example of a semiconductor device.
  • 7A and 7B are cross-sectional views showing an example of a semiconductor device.
  • Fig. 1A is a plan view showing an example of a semiconductor device
  • Figs. 1B to 1E are cross-sectional views showing an example of the semiconductor device.
  • 2A and 2B are perspective views showing an example of
  • FIG. 8A is a plan view showing an example of a semiconductor device
  • Figs. 8B to 8D are cross-sectional views showing an example of the semiconductor device.
  • FIG. 9 is a cross-sectional view showing an example of a semiconductor device.
  • Fig. 10A is a plan view showing an example of a semiconductor device
  • Figs. 10B to 10D are cross-sectional views showing an example of the semiconductor device.
  • 11A to 11C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 12A to 12C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 13A to 13C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 14A to 14C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • Fig. 15A is a plan view showing an example of a storage device
  • Figs. 15B and 15C are cross-sectional views showing an example of the storage device.
  • 16A is a plan view of an example of a storage device
  • FIG 16B is a cross-sectional view of the example of the storage device.
  • FIG. 17 is a cross-sectional view showing an example of a storage device.
  • FIG. 18 is a cross-sectional view showing an example of a storage device.
  • FIG. 19 is a block diagram illustrating a configuration example of a semiconductor device.
  • 20A to 20H are diagrams for explaining examples of the circuit configuration of a memory cell.
  • 21A and 21B are perspective views illustrating a configuration example of a semiconductor device.
  • FIG. 22 is a block diagram illustrating the CPU.
  • 23A and 23B are perspective views of a semiconductor device.
  • 24A and 24B are perspective views of a semiconductor device.
  • 25A and 25B are diagrams showing various storage devices by hierarchical level.
  • 26A and 26B are perspective views showing an example of a display device.
  • FIG. 27 is a cross-sectional view showing an example of a display device.
  • FIG. 28 is a cross-sectional view showing an example of a display device.
  • 29A to 29C are diagrams showing configuration examples of a display device.
  • 30A and 30B are diagrams illustrating an example of an electronic component.
  • FIGS. 31C are diagrams showing an example of a mainframe computer
  • Fig. 31D is a diagram showing an example of space equipment
  • Fig. 31E is a diagram showing an example of a storage system applicable to a data center.
  • 32A to 32F are diagrams showing an example of an electronic device.
  • 33A to 33G are diagrams showing an example of an electronic device.
  • 34A to 34F are diagrams showing an example of an electronic device.
  • 35A and 35B are cross-sectional views of a semiconductor device assumed in the device simulation.
  • FIG. 36 is a diagram showing the Id-Vg characteristics obtained by device simulation.
  • FIG. 37A is a diagram showing the correlation between the shift voltage calculated from the Id-Vg characteristics and the subthreshold swing value
  • FIG 37B is a diagram showing the correlation between the field effect mobility calculated from the Id-Vg characteristics and the DIBL.
  • FIG. 38 is a diagram showing the electron density distribution obtained by the device simulation.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking).
  • an ordinal number attached to a component in one place in this specification may not match an ordinal number attached to the same component in another place in this specification or in the claims.
  • a transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conduction.
  • transistor includes IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).
  • a transistor that uses an oxide semiconductor or a metal oxide in a semiconductor layer and a transistor that has an oxide semiconductor or a metal oxide in a channel formation region may be referred to as an OS transistor.
  • a transistor that has silicon in a channel formation region may be referred to as a Si transistor.
  • a transistor is an element having at least three terminals including a gate, a drain, and a source.
  • a transistor has a region (also called a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and drain through the channel formation region.
  • a channel formation region refers to a region through which a current mainly flows.
  • source and drain may be interchangeable when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms “source” and “drain” can be used interchangeably.
  • the impurity of a semiconductor refers to, for example, anything other than the main component constituting the semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be said to be an impurity.
  • the defect level density of the semiconductor may increase or the crystallinity may decrease.
  • the semiconductor is an oxide semiconductor
  • examples of the impurity that changes the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor.
  • Specific examples of the impurity include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • water may also function as an impurity.
  • oxygen vacancies also referred to as V O
  • V O oxygen vacancies
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen.
  • An oxynitride refers to a material whose composition contains more nitrogen than oxygen.
  • SIMS secondary ion mass spectrometry
  • XPS X-ray photoelectron spectrometry
  • SIMS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more).
  • SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%).
  • film and “layer” can be interchanged depending on the circumstances.
  • conductive layer can be changed to the term “conductive film.”
  • insulating film can be changed to the term “insulating layer.”
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. This therefore includes cases in which the angle is -5 degrees or more and 5 degrees or less.
  • approximately parallel refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • Perpendicular refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. This therefore includes cases in which the angle is 85 degrees or more and 95 degrees or less.
  • approximately perpendicular refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • electrically connected includes cases where the connection is made via "something that has some kind of electrical action.”
  • something that has some kind of electrical action is not particularly limited as long as it allows the transmission and reception of electrical signals between the connected objects.
  • something that has some kind of electrical action includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.
  • off-state current refers to the leakage current between the source and drain when a transistor is in the off state (also called a non-conducting state or cut-off state).
  • the off state refers to a state in which the voltage Vgs between the gate and source is lower than the threshold voltage Vth in an n-channel transistor (higher than Vth in a p-channel transistor). Note that this may be referred to as the voltage between the gate and source Vg.
  • the voltage between the gate and source may also be referred to simply as the gate voltage.
  • the normally-on characteristic refers to a state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate.
  • the normally-off characteristic refers to a state in which no current flows through the transistor when no potential is applied to the gate or when a ground potential is applied to the gate.
  • the top surface shape of a certain component refers to the contour shape of the component when viewed from a planar view.
  • a planar view refers to a view from the normal direction of the surface on which the component is formed, or the surface of the support (e.g., substrate) on which the component is formed.
  • top surface shapes roughly match means that at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where parts of the mask pattern are the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer, in which case it may also be said that "top surface shapes roughly match.” Furthermore, when the top surface shapes match or roughly match, it can also be said that the edges are aligned or roughly matched, or that the side edges are aligned or roughly matched.
  • a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.
  • A covers B
  • at least a part of A covers B. Therefore, for example, it can be rephrased as saying that A has an area that covers B.
  • a device fabricated using a metal mask or an FMM may be referred to as a device with an MM (metal mask) structure.
  • a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.
  • SBS Side By Side
  • the SBS structure allows the materials and configuration to be optimized for each light-emitting element, which increases the freedom of material and configuration selection and makes it easier to improve brightness and reliability.
  • holes or electrons may be referred to as "carriers".
  • the hole injection layer or electron injection layer may be referred to as the "carrier injection layer”
  • the hole transport layer or electron transport layer may be referred to as the “carrier transport layer”
  • the hole block layer or electron block layer may be referred to as the "carrier block layer”.
  • the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable.
  • one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.
  • the light-emitting element has an EL layer between a pair of electrodes.
  • the EL layer has at least a light-emitting layer.
  • layers also called functional layers
  • the EL layer has include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer).
  • the light-receiving element also called a light-receiving device
  • one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.
  • the sacrificial layer is a layer that is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that make up the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.
  • step discontinuity refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step, etc.).
  • arrows indicating the X-direction, Y-direction, and Z-direction may be used.
  • the "X-direction” refers to the direction along the X-axis, and may not distinguish between the forward direction and the reverse direction unless otherwise specified. The same applies to the "Y-direction” and "Z-direction”.
  • the X-direction, Y-direction, and Z-direction are directions that intersect with each other.
  • the X-direction, Y-direction, and Z-direction are directions that are perpendicular to each other.
  • one of the X-direction, Y-direction, and Z-direction may be called the "first direction” or “first direction”.
  • the other may be called the “second direction” or “second direction”.
  • the remaining one may be called the "third direction” or "third direction”.
  • One embodiment of the present invention is a semiconductor device having a transistor, a first insulating layer, and a second insulating layer.
  • the transistor has a first conductive layer, a second conductive layer, a third conductive layer, a third insulating layer, and an oxide semiconductor layer.
  • the first conductive layer functions as one of a source electrode and a drain electrode of the transistor.
  • the second conductive layer functions as a gate electrode.
  • the third conductive layer functions as the other of the source electrode and drain electrode.
  • the third insulating layer functions as a gate insulating layer.
  • the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer are stacked in this order.
  • the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have an opening that reaches the first conductive layer.
  • the third insulating layer has a region in the opening that contacts a part of the upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, and a side surface of the second insulating layer.
  • the oxide semiconductor layer has a region that contacts the upper surface of the first conductive layer, the upper surface and side surface of the third insulating layer, and the upper surface of the third conductive layer.
  • the third insulating layer has a portion that protrudes toward the oxide semiconductor layer in the region that contacts the upper surface of the first conductive layer.
  • a gate electrode is provided around the oxide semiconductor layer and the gate insulating layer.
  • a region of the oxide semiconductor layer that overlaps with the gate electrode via the gate insulating layer functions as a channel formation region.
  • the channel length of the transistor can be controlled by the film thickness of the gate electrode, and therefore the transistor can have a short channel length. Therefore, the transistor can have a large on-current, and the semiconductor device can operate at a high speed.
  • the source electrode and drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction.
  • the channel length direction has a component in the height direction (vertical direction), and therefore the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, vertical channel transistor, etc.
  • VFET Vertical Field Effect Transistor
  • the transistor can have a source electrode, a semiconductor layer, and a drain electrode that are stacked, so the area occupied can be significantly reduced compared to a so-called planar type transistor in which the semiconductor layer is arranged in a planar shape.
  • FIG. 1A is a plan view (also referred to as a top view) of a semiconductor device including a transistor 200A.
  • FIG. 1B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 1A.
  • FIG. 1C is a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 1A.
  • FIG. 1D is a cross-sectional view taken along dashed dotted line A5-A6 in FIGS. 1B and 1C. Note that in the plan view of FIG.
  • FIG. 2A is a perspective view of the semiconductor device. In the perspective view of FIG. 2A, some components are also omitted.
  • FIG. 2B shows a cross section taken along dashed dotted line B1-B2 in FIG. 2A.
  • the semiconductor device shown in Figures 1A to 2B has an insulating layer 210 on a substrate (not shown), a transistor 200A on the insulating layer 210, an insulating layer 280 on the insulating layer 210, an insulating layer 281 on the insulating layer 280, an insulating layer 283 on the transistor 200A, and an insulating layer 285 on the insulating layer 283.
  • the insulating layer 210, the insulating layer 280, the insulating layer 281, the insulating layer 283, and the insulating layer 285 function as interlayer films. Note that in Figures 2A and 2B, the insulating layer 283 and the insulating layer 285 are omitted, and the insulating layer 281 and the insulating layer 280 are shown transparently with their outlines indicated by dashed lines.
  • Transistor 200A has a conductive layer 220, a conductive layer 260 on insulating layer 280, a conductive layer 240 on insulating layer 281, an insulating layer 250, and an oxide semiconductor layer 230.
  • the conductive layer 220, insulating layer 280, conductive layer 260, insulating layer 281, and conductive layer 240 are stacked in this order.
  • An opening 290 reaching the conductive layer 220 is provided in the insulating layer 280, conductive layer 260, insulating layer 281, and conductive layer 240.
  • the bottom of the opening 290 is the top surface of the conductive layer 220
  • the side walls of the opening 290 are the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 260, the side surfaces of the insulating layer 281, and the side surfaces of the conductive layer 240.
  • the opening 290 includes an opening in the insulating layer 280, an opening in the conductive layer 260, an opening in the insulating layer 281, and an opening in the conductive layer 240.
  • the opening in the area where the insulating layer 280 overlaps with the conductive layer 220 is a part of the opening 290
  • the opening in the area where the conductive layer 260 overlaps with the conductive layer 220 is another part of the opening 290
  • the opening in the area where the insulating layer 281 overlaps with the conductive layer 220 is another part of the opening 290
  • the opening in the area where the conductive layer 240 overlaps with the conductive layer 220 is another part of the opening 290.
  • An insulating layer 250 is provided within the opening 290.
  • the insulating layer 250 is provided to reflect the shape of the opening 290. Specifically, the insulating layer 250 is provided so as to cover the sidewalls and part of the bottom of the opening 290.
  • the insulating layer 250 has an opening 270 that reaches the conductive layer 220. Here, the bottom of the opening 270 is the top surface of the conductive layer 220.
  • the insulating layer 250 contacts the top surface of part of the conductive layer 220, the side of the insulating layer 280, the side of the conductive layer 260, the side of the insulating layer 281, and the side of the conductive layer 240.
  • FIG. 1E shows an enlarged view of the bottom of the opening 290 shown in FIG. 1B and its vicinity.
  • the insulating layer 250 has a protruding portion 250p in a region in contact with the conductive layer 220.
  • the protruding portion 250p is a portion that protrudes toward the oxide semiconductor layer 230 side in a region in contact with the conductive layer 220. More specifically, the protruding portion 250p is a portion that protrudes further than the side surface of the insulating layer 250 on the oxide semiconductor layer 230 side in a region of the insulating layer 250 that is not in contact with the conductive layer 220.
  • the bottom surface of the protruding portion 250p is in contact with the top surface of the conductive layer 220. Furthermore, in the protruding portion 250p, the top surface and side surface of the insulating layer 250 are in contact with the oxide semiconductor layer 230.
  • the insulating layer 250 is provided in contact with the sidewalls and a part of the bottom of the opening 290.
  • the insulating layer 250 can be formed, for example, using a dummy layer. Specifically, a first insulating layer that becomes the insulating layer 250 is formed, a dummy layer is formed on the first insulating layer, and the first insulating layer and the dummy layer are processed to expose the conductive layer 220 in the area overlapping with the opening 290 and form the insulating layer 250 having the protruding portion 250p. For example, anisotropic etching can be suitably used to process the first insulating layer and the dummy layer. The dummy layer is then removed. The method for manufacturing the semiconductor device will be described in detail later.
  • the oxide semiconductor layer 230 is provided so as to cover the conductive layer 220, the insulating layer 250, and the conductive layer 240.
  • the oxide semiconductor layer 230 has a region in contact with the upper surface of the conductive layer 240, the upper surface and side surfaces of the insulating layer 250, and the upper surface of the conductive layer 220.
  • the oxide semiconductor layer 230 contacts the upper surface of the conductive layer 220 at the opening 270.
  • the oxide semiconductor layer 230 functions as a semiconductor layer
  • the insulating layer 250 functions as a gate insulating layer
  • the conductive layer 260 functions as a gate electrode
  • the conductive layer 220 functions as one of the source electrode and the drain electrode
  • the conductive layer 240 functions as the other of the source electrode and the drain electrode.
  • the region of the oxide semiconductor layer 230 in contact with the conductive layer 220 functions as one of the source region and the drain region
  • the region in contact with the conductive layer 240 functions as the other of the source region and the drain region.
  • the portion of the oxide semiconductor layer 230 that overlaps with the conductive layer 260 via the insulating layer 250 and its vicinity function as a channel formation region of the transistor 200A.
  • the channel formation region is sandwiched between the source region and the drain region. Note that, for ease of explanation, the portion of the oxide semiconductor layer 230 that overlaps with the conductive layer 260 may be described as the channel formation region.
  • the transistor 200A has a metal oxide (also called an oxide semiconductor) that functions as a semiconductor in the oxide semiconductor layer 230, which includes a channel formation region.
  • the transistor 200A can be said to be an OS transistor.
  • oxygen vacancies ( VO ) and impurities are present in a channel formation region in an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate and the reliability may be reduced. Furthermore, hydrogen near the oxygen vacancies may form a defect in which hydrogen is inserted into the oxygen vacancy (hereinafter sometimes referred to as VOH ), and may generate electrons that serve as carriers. For this reason, when oxygen vacancies are present in the channel formation region in the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor is reduced and the channel formation region in the oxide semiconductor is made i-type (intrinsic) or substantially i-type.
  • the source and drain regions of an OS transistor are preferably low-resistance regions having a higher carrier concentration due to a larger amount of oxygen vacancies ( VO ) or VOH or a higher concentration of impurities (e.g., hydrogen, nitrogen, and metal elements) than the channel formation region.
  • the source and drain regions of an OS transistor are preferably low-resistance regions having a higher carrier concentration than the channel formation region.
  • the oxide semiconductor layer 230 and the conductive layer 220 come into contact with each other, a metal compound or oxygen vacancy is formed, and the electrical resistance of the region of the oxide semiconductor layer 230 that comes into contact with the conductive layer 220 is reduced. This makes it possible to reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220.
  • the electrical resistance of the region of the oxide semiconductor layer 230 that comes into contact with the conductive layer 240 is reduced. This makes it possible to reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240.
  • the region between the channel formation region and the source region, and the region between the channel formation region and the drain region function as offset regions.
  • the offset region is a region that is in contact with the insulating layer 250 of the oxide semiconductor layer 230 and does not overlap with the conductive layer 260.
  • the offset region is a region that has higher electrical resistance than the source region and the drain region.
  • the oxide semiconductor layer 230 is provided in the opening 290.
  • the transistor 200A has a configuration in which one of the source electrode and drain electrode (here, the conductive layer 220) is located on the lower side and the other of the source electrode and drain electrode (here, the conductive layer 240) is located on the upper side, so that the current flows in the vertical direction.
  • a channel is formed along the side surface of the insulating layer 250 provided on the side wall of the opening 290.
  • FIGS. 3A and 3B are enlarged views of Figures 1B and 1D.
  • the channel length L of the transistor 200A is the length of the region of the oxide semiconductor layer 230 that overlaps with the conductive layer 260 via the insulating layer 250 in a cross-sectional view in the XZ plane (or YZ plane).
  • the channel length of the transistor 200A is determined by the thickness of the conductive layer 260.
  • the channel length L of the transistor 200A is indicated by a dashed double-headed arrow.
  • the channel length L can also be said to be the length of the region where the conductive layer 260 and the insulating layer 250 contact each other in a cross-sectional view in the XZ plane (or YZ plane).
  • the term "when viewed from a cross section” is used, but more specifically, this can be rephrased as "when viewed from a cross section in the same direction.”
  • this can be rephrased as "when viewed from a cross section in the same direction.”
  • the relationship when viewed from a cross section in the same direction is explained. In this case, the relationship between the multiple components can be explained using a single cross-sectional view.
  • the channel length is affected by the performance of the exposure equipment used in fabrication, but in the present invention, the channel length can be controlled by the film thickness of the conductive layer 260. Therefore, the channel length of the transistor 200A can be made smaller than the minimum value of the dimension that the exposure equipment can expose (hereinafter also referred to as the minimum dimension).
  • the channel length of the transistor 200A can be, for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and can be 0.1 nm or more, 1 nm or more, or 5 nm or more. This increases the on-current of the transistor 200A, and improves the frequency characteristics.
  • the heights in the Z direction at which the channel formation region, the source region, and the drain region are provided are different from one another. Therefore, the area occupied by the transistor 200A can be made smaller than that of a planar transistor. Therefore, the degree of integration of the semiconductor device can be increased. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.
  • the oxide semiconductor layer 230 and the insulating layer 250 are provided concentrically, and the conductive layer 260 is provided on the outer periphery of the oxide semiconductor layer 230 and the insulating layer 250.
  • the side surface of the oxide semiconductor layer 230 faces the side surface of the conductive layer 260 via the insulating layer 250. That is, in plan view, the entire circumference of the oxide semiconductor layer 230 becomes a channel formation region. At this time, the channel width W of the transistor 200A is determined by the circumference of the oxide semiconductor layer 230.
  • the channel width W of the transistor 200A can be the circumference of a circle formed by the side surface of the insulating layer 250 side of the region of the oxide semiconductor layer 230 that overlaps with the conductive layer 260 in plan view.
  • the width Da of the circle (corresponding to the diameter of the circle) is "D-T250 x 2", which is obtained by subtracting twice the thickness T250 of the insulating layer 250 from the width D of the opening 290 (corresponding to the diameter of the opening 290).
  • the channel width W can be calculated as "Da x ⁇ ". Therefore, the channel width W can be controlled by the width D of the opening 290 and the thickness T250 of the insulating layer 250.
  • the channel width W can be increased, and the on-current can be increased.
  • the width Da is indicated by a dotted double arrow
  • the channel width W is indicated by a solid double arrow.
  • the width D is indicated by a two-dot chain double arrow
  • the thickness T250 of the insulating layer 250 and the thickness T230 of the oxide semiconductor layer 230 are each indicated by a solid single arrow.
  • the thickness T250 of the insulating layer 250 can be, for example, the shortest distance between the side of the insulating layer 250 that contacts the conductive layer 260 and the side that contacts the oxide semiconductor layer 230 in the region where the conductive layer 260 and the oxide semiconductor layer 230 overlap with the insulating layer 250 interposed therebetween.
  • the thickness T230 of the oxide semiconductor layer 230 can be, for example, the shortest distance between the side of the oxide semiconductor layer 230 that contacts the insulating layer 250 and the side that contacts the insulating layer 283 in the region where the conductive layer 260 and the oxide semiconductor layer 230 overlap with the insulating layer 250 interposed therebetween.
  • the width D of the opening 290 is affected by the performance of the exposure device used in the fabrication. In other words, the width D is equal to or greater than the minimum dimension of the exposure device.
  • the width D of the opening 290 can be, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and can be 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less.
  • the width D can be determined appropriately taking into account the thickness T250, the thickness T230, and the desired channel width W.
  • the width D and the width Da may each vary in the depth direction of the opening 290.
  • the width D is used here as the shortest distance between the two side surfaces of the conductive layer 260 on the opening 290 side in a cross-sectional view.
  • the minimum value of the width of the opening 290 in the conductive layer 260 is used as the width D of the opening 290.
  • the width Da is used as the shortest distance between the two side surfaces on the insulating layer 250 side in the region of the oxide semiconductor layer 230 that overlaps with the conductive layer 60 side in a cross-sectional view.
  • the channel length L of the transistor 200A is preferably at least smaller than the channel width W of the transistor 200A.
  • the channel length L of the transistor 200A is preferably 0.1 to 0.99 times the channel width W of the transistor 200A, and more preferably 0.5 to 0.8 times the channel width W of the transistor 200A. With this configuration, a transistor with good electrical characteristics and high reliability can be realized.
  • An opening 290 that is circular in plan view is formed in the conductive layer 260. Furthermore, by providing the oxide semiconductor layer 230 and the insulating layer 250 within the opening 290, the oxide semiconductor layer 230 and the insulating layer 250 are provided concentrically. As a result, the distance between the conductive layer 260 and the oxide semiconductor layer 230 becomes approximately uniform, so that a gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.
  • the opening 290 in plan view can also be substantially circular, such as an ellipse, polygonal, such as a rectangle, or polygonal, such as a rectangle, with rounded corners.
  • FIG. 3A shows a configuration in which the upper surface of the conductive layer 220 is flat, but one embodiment of the present invention is not limited to this.
  • a recess that overlaps with the opening 270 may be formed on the upper surface of the conductive layer 220.
  • the oxide semiconductor layer 230 comes into contact with the upper surface and side surfaces of the conductive layer 220, thereby increasing the contact area therebetween, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 can be reduced.
  • the height of the upper surface of the insulating layer 250 at the highest position is the same as the height of the upper surface of the conductive layer 240, but one embodiment of the present invention is not limited to this.
  • the height of the upper surface of the insulating layer 250 at the highest position can be different from the height of the upper surface of the conductive layer 240. It is preferable that the height of the upper surface of the insulating layer 250 at the highest position is lower than the height of the upper surface of the conductive layer 240.
  • the oxide semiconductor layer 230 contacts the upper surface and side surface of the conductive layer 240, so that the contact area between them is increased, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.
  • FIG. 3A shows a configuration in which the top surface of the insulating layer 250 is flat
  • one embodiment of the present invention is not limited to this.
  • the top surface of the insulating layer 250 at the highest position may have a curved surface.
  • the height of the top surface of the insulating layer 250 decreases from the conductive layer 240 side toward the oxide semiconductor layer 230 side in a cross-sectional view. This reduces unevenness on the formation surface of the oxide semiconductor layer 230, and improves the coverage of the oxide semiconductor layer 230.
  • FIG. 1C shows a structure in which the end of the oxide semiconductor layer 230 is located inside the end of the conductive layer 240 outside the opening 290.
  • one embodiment of the present invention is not limited to this.
  • a structure in which the end of the oxide semiconductor layer 230 and the end of the conductive layer 240 coincide or approximately coincide in the X direction can be used.
  • a structure in which the end of the oxide semiconductor layer 230 is located outside the end of the conductive layer 240 can be used.
  • the oxide semiconductor layer 230 contacts the upper surface and side surface of the conductive layer 240, thereby increasing the contact area therebetween, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.
  • Figures 5A to 5C show a structure in which the end of the oxide semiconductor layer 230 and the end of the conductive layer 240 coincide.
  • Figure 5A is a plan view of a semiconductor device having a transistor 200A.
  • Figure 5B is a cross-sectional view between dashed dotted lines A1-A2 shown in Figure 5A.
  • Figure 5C is a cross-sectional view between dashed dotted lines A3-A4 shown in Figure 5A.
  • the oxide semiconductor layer 230 is provided over the entire upper surface of the conductive layer 240.
  • the conductive layer 240 and another conductive layer here, the conductive layer 244
  • openings are provided in the insulating layer 285, the insulating layer 283, and the oxide semiconductor layer 230, and the conductive layer 244 is formed in the opening, so that the conductive layer 240 and the conductive layer 244 are in contact with each other.
  • the structure in which the conductive layer 240 and the other conductive layer are connected to each other is not limited to this.
  • the sidewall of the opening 290 is preferably perpendicular to the upper surface of the insulating layer 210.
  • the film provided in the opening 290 is formed using the atomic layer deposition (ALD) method.
  • the ALD method can deposit atoms one layer at a time, and therefore has the effects of enabling extremely thin film formation, film formation on a structure with a high aspect ratio, film formation with few defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Therefore, the film can be formed on the side surface of the opening 290 with good coverage.
  • the oxide semiconductor layer 230 and the insulating layer 250 are each formed using the ALD method.
  • the opening 290 is provided so that the sidewall of the opening 290 is perpendicular to the upper surface of the insulating layer 210, but one embodiment of the present invention is not limited thereto.
  • the sidewall of the opening 290 can be tapered.
  • the coverage of the oxide semiconductor layer 230 and the insulating layer 250 provided in the opening 290 can be improved, and defects such as voids can be reduced.
  • the angle between the side surface of the insulating layer 280 in the opening 290 and the upper surface of the insulating layer 210 is preferably 45 degrees or more and less than 90 degrees.
  • the semiconductor device can be miniaturized or highly integrated, as described above.
  • the angle is 45 degrees or more, or 50 degrees or more, and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less, the coverage of the film formed inside the opening 290 is improved, which is preferable.
  • the sidewall of the opening 290 may have an inverse tapered shape.
  • the angle between the side surface of the insulating layer 280 at the opening 290 and the top surface of the insulating layer 210 may be greater than 90 degrees.
  • conductive layer 240 and conductive layer 260 come into contact, there is a risk of them shorting out. Therefore, it is preferable that conductive layer 240 does not come into contact with the side of conductive layer 260 at opening 290. Furthermore, it is even more preferable that conductive layer 240 does not come into contact with the side of insulating layer 281 at opening 290. This makes it possible to suppress shorting between conductive layer 240 and conductive layer 260. Furthermore, by forming the opening in conductive layer 240, the opening in insulating layer 281, and the opening in conductive layer 260 in the same process, it is possible to achieve a configuration in which conductive layer 240 and conductive layer 260 do not come into contact.
  • the opening in insulating layer 280 is also formed in the same process.
  • the film thickness of the insulating layer 250 and the oxide semiconductor layer 230 provided in the opening 290 can be made more uniform.
  • the insulating layer 250 and the oxide semiconductor layer 230 can be prevented from being divided by steps caused by the conductive layer 240, the insulating layer 281, the conductive layer 260, and the insulating layer 280.
  • FIGS. 1B and 1C show a configuration in which the side of the conductive layer 240, the side of the insulating layer 281, the side of the conductive layer 260, and the side of the insulating layer 280 in the opening 290 are flush with each other, but one aspect of the present invention is not limited to this.
  • the side of the conductive layer 240 and the side of the insulating layer 281 in the opening 290 may be discontinuous.
  • the inclination of the side of the conductive layer 240, the side of the insulating layer 281, the side of the conductive layer 260, and the side of the insulating layer 280 in the opening 290 may be different from each other.
  • the angle between the side of the conductive layer 240 and the upper surface of the insulating layer 210 is smaller than the angle between the side of the insulating layer 281 and the upper surface of the insulating layer 210.
  • the transistor 200A has a structure in which a conductive layer 260 functioning as a gate electrode is located on the outer periphery of the oxide semiconductor layer 230 via an insulating layer 250, and the gate electrode surrounds the channel formation region. Therefore, the transistor 200A can be said to have a GAA (Gate All Around) structure.
  • the transistor 200A can also be said to be a VFET with a GAA structure.
  • FIG. 1D can also be said to be a cross-sectional view in the XY plane including the channel formation region of the oxide semiconductor layer 230.
  • the conductive layer 240 and the conductive layer 260 extend in different directions. This reduces the area of the overlapping region of the conductive layer 240 and the conductive layer 260, thereby reducing the parasitic capacitance between the conductive layer 240 and the conductive layer 260.
  • the conductive layer 220 and the conductive layer 260 extend in different directions. This reduces the area of the overlapping region of the conductive layer 220 and the conductive layer 260, thereby reducing the parasitic capacitance between the conductive layer 220 and the conductive layer 260.
  • FIG. 2A and other figures show a configuration in which the conductive layer 240 and the conductive layer 260 extend in mutually orthogonal directions in a plan view, and the conductive layer 220 and the conductive layer 260 extend in mutually orthogonal directions. This reduces the parasitic capacitance, which is preferable.
  • the directions in which the conductive layer 220, the conductive layer 240, and the conductive layer 260 extend are not particularly limited.
  • FIGS. 7A and 7B show an example in which the conductive layer 220, the oxide semiconductor layer 230, and the conductive layer 240 each have a stacked structure.
  • An insulating layer 283 is provided on the transistor 200A.
  • the insulating layer 283 has a region in contact with the top and side surfaces of the oxide semiconductor layer 230, the top and side surfaces of the conductive layer 240, and the top surface of the insulating layer 281.
  • the insulating layer 283 has a region in contact with the top and side surfaces of the oxide semiconductor layer 230 in the opening 290.
  • An insulating layer 285 is provided on the insulating layer 283.
  • the insulating layer 285 is in contact with the top and side surfaces of the insulating layer 283 in the opening 290.
  • the insulating layer 285 is provided in contact with the insulating layer 283 so as to fill the opening 290. It can also be said that the insulating layer 283 and the insulating layer 285 are provided on the oxide semiconductor layer 230 so as to fill the opening 290.
  • the upper surface of the insulating layer 285 is preferably flat. This improves the coverage of the layers provided on the insulating layer 285.
  • a structure in which the insulating layer 283 and the insulating layer 285 are provided between the opposing oxide semiconductor layers 230 in the opening 290 has been described, but one embodiment of the present invention is not limited to this.
  • a structure in which the recesses of the oxide semiconductor layers 230 in the opening 290 are filled with the insulating layer 283 can be used.
  • a structure in which the opposing oxide semiconductor layers 230 are in contact with each other in the opening 290 can be used. In this case, the step of the formation surface of the insulating layer 283 provided on the oxide semiconductor layer 230 is reduced, and the coverage of the insulating layer 283 can be improved.
  • the oxide semiconductor layer 230 has a channel formation region.
  • the channel formation region is i-type (intrinsic) or substantially i-type.
  • the oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are low-resistance regions having a higher carrier concentration than the channel formation region.
  • the crystallinity of the semiconductor material used for the oxide semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • the use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.
  • the band gap of a metal oxide that functions as a semiconductor is preferably 2.0 eV or more, and more preferably 2.5 eV or more.
  • metal oxides examples include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably contains two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or semi-metal element that has a high bond energy with oxygen, for example, a metal element or semi-metal element that has a higher bond energy with oxygen than indium.
  • element M examples include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification may include metalloid elements.
  • the oxide semiconductor layer 230 may be, for example, indium oxide (In oxide), indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), or aluminum zinc oxide (Al-Zn oxide, also referred to as AZO).
  • In oxide indium oxide
  • In-Zn oxide indium zinc oxide
  • In-Zn oxide also referred to as IZO (registered trademark)
  • indium tin oxide In-Sn oxide
  • In-Ti oxide indium titanium oxide
  • In-Ga oxide indium gallium oxide
  • In-Ga-Al oxide indium gall
  • indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO, or IAGZO), etc.
  • indium tin oxide containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.
  • the field effect mobility of the transistor can be increased.
  • a transistor with a large on-current can be realized.
  • the metal oxide may contain one or more metal elements having a high period number in the periodic table.
  • the field effect mobility of the transistor may be increased.
  • metal elements having a high period number include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may contain one or more nonmetallic elements.
  • the carrier concentration increases or the band gap decreases, which may increase the field effect mobility of the transistor.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline and the diffusion of impurities in the metal oxide can be suppressed. This suppresses fluctuations in the electrical characteristics of the transistor and increases its reliability.
  • a metal oxide with a large band gap By increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, a metal oxide with a large band gap can be obtained. In addition, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. In addition, a shift in the threshold voltage of the transistor can be suppressed. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide applied to the oxide semiconductor layer 230. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, it is possible to obtain a semiconductor device that has both excellent electrical characteristics and high reliability.
  • the metal oxide is In-M-Zn oxide
  • the atomic ratio of In in the In-M-Zn oxide is greater than or equal to the atomic ratio of element M.
  • the nearby composition includes a range of
  • the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of the element M.
  • element M contains multiple metal elements
  • the total proportion of the atomic numbers of the metal elements can be regarded as the proportion of the atomic number of element M.
  • the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained may be referred to as the indium content. The same applies to other metal elements.
  • the In-Zn oxide may also contain a trace amount of element M.
  • the composition of the metal oxide used in the oxide semiconductor layer 230 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES).
  • EDX energy dispersive X-ray spectrometry
  • XPS X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • a combination of these techniques may be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, may be difficult to quantify, or may be below the detection limit.
  • the sputtering method or the ALD method can be suitably used to form the metal oxide.
  • the composition of the metal oxide after film formation may differ from the composition of the target.
  • the zinc content in the metal oxide after film formation may decrease to about 50% compared to the target.
  • the chemical vapor deposition (CVD) method, the molecular beam epitaxy (MBE) method, the pulsed laser deposition (PLD) method, etc. can also be used to form the metal oxide film.
  • the thickness T230 of the oxide semiconductor layer 230 is preferably 1 nm or more and 30 nm or less, more preferably 3 nm or more and 30 nm or less, more preferably 3 nm or more and 20 nm or less, more preferably 3 nm or more and 15 nm or less, more preferably 3 nm or more and 12 nm or less, more preferably 5 nm or more and 12 nm or less, and more preferably 5 nm or more and 10 nm or less.
  • the oxide semiconductor layer 230 can have a stacked structure having two or more metal oxide layers.
  • the compositions of the two or more metal oxide layers in the oxide semiconductor layer 230 may be the same or approximately the same.
  • they can be formed using the same sputtering target, thereby reducing manufacturing costs.
  • compositions of the two or more metal oxide layers in the oxide semiconductor layer 230 may be different from each other.
  • FIG. 7A shows an example in which the oxide semiconductor layer 230 has a two-layer structure of an oxide layer 230a and an oxide layer 230b on the oxide layer 230a.
  • a material having a higher conductivity than the oxide layer 230b for the oxide layer 230a it is preferable to use a material having a higher conductivity than the oxide layer 230b for the oxide layer 230a.
  • a material having a higher conductivity for the oxide layer 230a in contact with the source electrode and the drain electrode here, the conductive layer 220 and the conductive layer 240
  • the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced, and a transistor with a large on-current can be obtained.
  • the carrier concentration of the oxide layer 230a is preferably higher than that of the oxide layer 230b. Increasing the carrier concentration of the oxide layer 230a increases the electrical conductivity, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 and between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced, resulting in a transistor with a large on-current.
  • the oxide semiconductor layer 230 is not limited to the above-mentioned configuration, and the oxide layer 230a may be made of a material having a lower conductivity than the oxide layer 230b.
  • the carrier concentration of the oxide layer 230a may be lower than the carrier concentration of the oxide layer 230b.
  • the band gap of the first metal oxide used in oxide layer 230a is preferably different from the band gap of the second metal oxide used in oxide layer 230b.
  • the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
  • the band gap of the first metal oxide used in the oxide layer 230a is preferably smaller than the band gap of the second metal oxide used in the oxide layer 230b. This can reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 and between the oxide semiconductor layer 230 and the conductive layer 240, and can provide a transistor with a large on-current.
  • the transistor 200A is an n-channel transistor, the threshold voltage can be increased, and the transistor can be a normally-off transistor.
  • the large band gap of the second metal oxide can suppress the generation and induction of carriers in the oxide layer 230b and at the interface between the oxide layer 230b and the insulating layer 250. This can improve the reliability of the transistor.
  • the oxide semiconductor layer 230 is not limited to the above-mentioned configuration, and the band gap of the first metal oxide may be larger than the band gap of the second metal oxide.
  • the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide.
  • the first metal oxide may be configured to contain a trace amount of element M or may not contain element M.
  • the first metal oxide used in the oxide layer 230a is In-Zn oxide
  • the second metal oxide used in the oxide layer 230b is In-M-Zn oxide.
  • the first metal oxide can be In-Zn oxide
  • the second metal oxide can be In-Ga-Zn oxide.
  • the oxide layer 230b provided on the insulating layer 283 side is preferably one through which substances are less likely to diffuse. This can suppress the diffusion of impurities from the insulating layer 283 side into the oxide semiconductor layer 230. Examples of such impurities include metals, hydrogen, and water contained in the insulating layers 283 and 285.
  • the content of element M in the second metal oxide is preferably higher than the content of element M in the first metal oxide. This can result in the oxide layer 230b being one through which substances are less likely to diffuse.
  • the oxide layer 230b is preferably highly crystalline. This can enhance the effect of suppressing the diffusion of impurities.
  • This increases the on-state current of transistor 200A and creates a highly reliable transistor structure with minimal variation.
  • oxide semiconductor layer 230 is not limited to the above-mentioned configuration, and the content of element M in the first metal oxide may be higher than the content of element M in the second metal oxide.
  • the oxide semiconductor layer 230 preferably contains a metal oxide having crystallinity.
  • a metal oxide having crystallinity examples include a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a nano-crystalline (nc: nano-crystal) structure.
  • the substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation.
  • the crystallinity of the oxide semiconductor layer 230 can be analyzed, for example, by X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • the oxide semiconductor layer 230 may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, it may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, and the second metal oxide layer may have a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. In this case, the first metal oxide layer and the second metal oxide layer may have different compositions, or may have the same or approximately the same composition.
  • the crystallinity of the oxide layer 230b is preferably higher than that of the oxide layer 230a.
  • the oxide layer 230a with low crystallinity on the conductive layer 220 and the side in contact with the conductive layer 220 the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced, and a transistor with a large on-current can be obtained.
  • FIG. 7A shows an example in which the oxide semiconductor layer 230 has a two-layer structure, but one embodiment of the present invention is not limited to this.
  • the oxide semiconductor layer 230 can have a stacked structure of three or more layers.
  • FIG. 7B shows an example in which the oxide semiconductor layer 230 has a three-layer structure of an oxide layer 230a, an oxide layer 230c on the oxide layer 230a, and an oxide layer 230b on the oxide layer 230c.
  • Hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to become water, and oxygen vacancies ( VO ) may be formed in the oxide semiconductor. Furthermore, a defect in which hydrogen enters an oxygen vacancy (hereinafter referred to as VOH ) may function as a donor and generate an electron that is a carrier. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate an electron that is a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics (that is, the threshold voltage has a negative value). Furthermore, hydrogen in an oxide semiconductor is easily mobile due to stress such as heat or an electric field; therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.
  • VOH in the oxide semiconductor layer 230 it is preferable to reduce VOH in the oxide semiconductor layer 230 as much as possible to make the oxide semiconductor layer 230 highly pure intrinsic or substantially highly pure intrinsic.
  • it is important to remove impurities such as water and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to repair oxygen vacancies.
  • impurities such as water and hydrogen from the oxide semiconductor
  • an oxide semiconductor with sufficiently reduced impurities such as VOH for a channel formation region of a transistor stable electrical characteristics can be imparted.
  • oxygen addition treatment oxygen addition treatment.
  • the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , even more preferably less than 1 ⁇ 10 16 cm ⁇ 3 , still more preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and still more preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, and can be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • the carbon concentration in a channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and further preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and still more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in a channel formation region of an oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, and further preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, and thus oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond to oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable that hydrogen in a channel formation region of the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably less than 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , and further preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • the concentration of the alkali metal or the alkaline earth metal in a channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the semiconductor device of this embodiment may also be applied to transistors using other semiconductor materials in the channel formation region.
  • semiconductors made of single elements include semiconductors made of single elements, or compound semiconductors.
  • semiconductors made of single elements include silicon and germanium.
  • compound semiconductors include gallium arsenide and silicon germanium.
  • Other examples of compound semiconductors include organic semiconductors and nitride semiconductors.
  • the aforementioned oxide semiconductor is also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.
  • Silicon that can be used as a semiconductor material for transistors includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • An example of polycrystalline silicon is low temperature polysilicon (LTPS).
  • the semiconductor layer of the transistor may have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), zirconium selenide (representatively ZrSe 2 ), and the like.
  • an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 250, insulating layer 280, insulating layer 281, insulating layer 283, insulating layer 285, etc.) included in the semiconductor device.
  • the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film.
  • oxide insulating film examples include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film.
  • nitride insulating film examples include a silicon nitride film and an aluminum nitride film.
  • Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film.
  • Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film.
  • An organic insulating film may be used for an insulating layer of the semiconductor device.
  • Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.
  • Materials with a low relative dielectric constant include, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin.
  • inorganic insulating materials with a low relative dielectric constant include, for example, silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Another example is silicon oxide with vacancies. These silicon oxides can also be configured to contain nitrogen.
  • a material that can have ferroelectricity may be used for the insulating layer of the semiconductor device.
  • materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (where X is a real number greater than 0).
  • materials that can have ferroelectricity include materials in which an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide.
  • the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set appropriately, and for example, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set to 1:1 or close to 1:1.
  • materials that can have ferroelectricity include materials in which an element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide.
  • element M1 is one or more selected from aluminum, gallium, indium, etc.
  • element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Note that the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Furthermore, a metal oxide having element M1 and nitrogen may have ferroelectricity even if it does not contain element M2.
  • element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.
  • the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.
  • Examples of materials that can have ferroelectric properties include perovskite-type oxynitrides such as SrTaO 2 N and BaTaO 2 N, and GaFeO 3 with a ⁇ -alumina structure.
  • metal oxides and metal nitrides are given as examples, but the present invention is not limited to these.
  • metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, etc. may also be used.
  • the insulating layer 130 can have a laminated structure made of multiple materials selected from the materials listed above.
  • the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials that can have ferroelectricity.
  • Metal oxides containing hafnium and/or zirconium can have ferroelectricity even in thin films of a few nm. Metal oxides containing hafnium and/or zirconium can also have ferroelectricity even in very small areas. Therefore, by using metal oxides containing hafnium and/or zirconium, it is possible to miniaturize semiconductor devices.
  • a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film.
  • a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in this specification.
  • Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in the crystals contained in the ferroelectric layer by an external electric field. It is also presumed that the manifestation of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulating layer to manifest ferroelectricity, the insulating layer 130 must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, since this manifests ferroelectricity.
  • the crystal structure of the crystals contained in the insulating layer may be one or more selected from the cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems.
  • the insulating layer may have an amorphous structure. In this case, the insulating layer may be a composite structure having an amorphous structure and a crystalline structure.
  • the electrical characteristics of a transistor using a metal oxide can be stabilized by surrounding it with an insulating layer that has a function of suppressing the permeation of impurities and oxygen.
  • an insulating layer that has a function of suppressing the permeation of impurities and oxygen for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer.
  • metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide
  • metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.
  • examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen include oxides containing aluminum and hafnium (hafnium aluminate).
  • Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.
  • An insulating layer such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near an oxide semiconductor layer is preferably an insulating layer that has a region that contains oxygen that is released by heating (hereinafter, may be referred to as excess oxygen).
  • an insulating layer that has a region that contains excess oxygen can be in contact with an oxide semiconductor layer or located near the oxide semiconductor layer to reduce oxygen vacancies in the oxide semiconductor layer.
  • Examples of insulating layers that are likely to form a region that contains excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide that has vacancies.
  • the dielectric constant be low.
  • the parasitic capacitance that occurs between wiring can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, so are suitable for the insulating layer 210.
  • the concentration of impurities such as water and hydrogen in the insulating layer 210 is reduced. This makes it possible to suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230.
  • the insulating layer 210 provided on the outside of the oxide semiconductor layer 230 has barrier properties against hydrogen, which can suppress the diffusion of hydrogen into the oxide semiconductor layer 230.
  • Materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon oxide nitride.
  • a barrier insulating layer refers to an insulating layer having a barrier property.
  • the barrier property refers to a property that the target substance is difficult to diffuse (also referred to as a property that the target substance is difficult to permeate, a property that the target substance has low permeability, or a function of suppressing the diffusion of the target substance).
  • hydrogen refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁇ .
  • impurities when impurities are described as the target substance, they refer to impurities in the channel formation region or the semiconductor layer unless otherwise specified, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2, etc.), a copper atom, etc.
  • oxygen when oxygen is described as the target substance, it refers to at least one of, for example, an oxygen atom, an oxygen molecule, etc.
  • a silicon nitride film as the insulating layer 210.
  • the insulating layer 280 and the insulating layer 281 each have a barrier insulating layer against hydrogen as described above.
  • the insulating layer 280 and the insulating layer 281 are provided so as to surround the oxide semiconductor layer 230 via the insulating layer 250.
  • the insulating layer 280 and the insulating layer 281 provided on the outside of the oxide semiconductor layer 230 have a barrier property against hydrogen, so that the diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed.
  • the insulating layer 280 and the insulating layer 281 each have a silicon nitride film.
  • Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layer 280 and the insulating layer 281, it is possible to suppress the extraction of oxygen from the oxide semiconductor layer 230 and the increase in oxygen vacancies in the oxide semiconductor layer 230. For example, it is preferable to use a single-layer structure of a silicon nitride film as the insulating layer 280. Similarly, it is preferable to use a single-layer structure of a silicon nitride film as the insulating layer 281.
  • a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in this order as the insulating layer 280.
  • a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in this order as the insulating layer 281.
  • the concentrations of impurities such as water and hydrogen in the insulating layer 280 and the insulating layer 281 are reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.
  • the length of the offset region of the transistor 200A can be adjusted by the thickness of the insulating layer 280 on the conductive layer 220 and the thickness of the insulating layer 281 on the conductive layer 260.
  • the thicknesses of the insulating layer 280 and the insulating layer 281 are set appropriately according to the desired electrical characteristics of the transistor 200A.
  • the insulating layer 250 preferably has a function of capturing hydrogen and fixing hydrogen.
  • the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in a channel formation region of a transistor) can be reduced.
  • VOH in the channel formation region can be reduced and the channel formation region can be made i-type or substantially i-type.
  • Materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, for example, oxides containing hafnium and zirconium.
  • these metal oxides preferably have an amorphous structure.
  • the amorphous structure may be realized by including silicon in these oxides.
  • the metal oxide may have one or both of a crystalline region and a crystal grain boundary in a part of the metal oxide.
  • the ability to capture or adhere to a target substance can also be said to have the property of making the target substance less likely to diffuse. Therefore, the ability to capture or adhere to a target substance can be rephrased as having barrier properties.
  • FIGS. 7A and 7B show an example in which insulating layer 250 has a two-layer structure of insulating layer 250a and insulating layer 250b on insulating layer 250a.
  • the layer in contact with the oxide semiconductor layer 230 has the function of capturing hydrogen and fixing hydrogen.
  • the insulating layer 250b has the function of capturing hydrogen and fixing hydrogen.
  • the insulating layer 250b has a function of capturing or fixing hydrogen, so that the hydrogen contained in the oxide semiconductor layer 230 can be captured or fixed more effectively. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.
  • hafnium silicate or the like can be used as the insulating layer 250b.
  • the insulating layer 250b has an amorphous structure.
  • the insulating layer 250b By making the insulating layer 250b have an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer 250b. This makes the thickness of the insulating layer 250b more uniform, and it is possible to suppress the occurrence of extremely thin portions, thereby improving the breakdown voltage of the insulating layer 250b. In addition, it is possible to make the thickness of the layer (e.g., the oxide semiconductor layer 230) provided on the insulating layer 250b more uniform.
  • the layer e.g., the oxide semiconductor layer 230
  • the insulating layer 250b By suppressing the formation of grain boundaries in the insulating layer 250b, it is possible to reduce the leakage current caused by defect levels in the grain boundaries. This allows the insulating layer 250b to function as an insulating film with low leakage current.
  • Hafnium oxide is a high dielectric constant (high-k) material, so hafnium silicate can also be a high dielectric constant (high-k) material depending on the silicon content. Therefore, by using a high dielectric constant material for the gate insulation layer, it is possible to lower the gate potential applied when the transistor is operating while maintaining the physical thickness of the gate insulation layer. It is also possible to reduce the equivalent oxide thickness (EOT) of the gate insulation layer.
  • high-k high dielectric constant
  • EOT equivalent oxide thickness
  • a barrier insulating layer against hydrogen for the insulating layer 250a, it is possible to prevent hydrogen contained in the insulating layer 280, the insulating layer 281, and the conductive layer 260 from diffusing into the oxide semiconductor layer 230.
  • Silicon nitride has high barrier properties against hydrogen, making it particularly suitable for the insulating layer 250a.
  • a high dielectric constant (high-k) material for the insulating layer 250.
  • An example of a high-k material is an oxide containing one or both of aluminum and hafnium.
  • an oxide containing one or both of aluminum and hafnium as the insulating layer 250b, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.
  • the insulating layer 250 may have an insulating layer having a thermally stable structure, such as silicon oxide or silicon oxynitride.
  • the insulating layer 250 may have an insulating layer with a heat-stable structure between a pair of insulating layers that have the function of capturing and fixing hydrogen.
  • the insulating layer 250 preferably has a barrier insulating layer against oxygen. This can prevent oxygen contained in the oxide semiconductor layer 230 from diffusing through the insulating layer 250 to the insulating layer 280, the conductive layer 260, and the insulating layer 281. This can prevent oxygen vacancies from being formed in the oxide semiconductor layer 230. In addition, it can prevent the conductive layer 260 from being oxidized by the oxygen contained in the oxide semiconductor layer 230.
  • the insulating layer 250 has a stacked structure, it is more preferable that the layer in contact with the oxide semiconductor layer 230 and the layer in contact with the conductive layer 260 are each a barrier insulating layer against oxygen.
  • Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).
  • the thickness T250 of the insulating layer 250 is preferably 0.1 nm or more and 30 nm or less, preferably 0.1 nm or more and 20 nm or less, preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less.
  • the insulating layer 250 it is preferable to use a three-layer structure in which a first insulating layer having a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the oxide semiconductor layer 230 side. It is preferable to use silicon oxide or silicon oxynitride as the material with a low dielectric constant of the first insulating layer.
  • the first insulating layer is a layer in contact with the oxide semiconductor layer 230. By using an oxide or oxynitride for the first insulating layer, oxygen can be supplied to the oxide semiconductor layer 230.
  • the third insulating layer it is possible to prevent the oxygen contained in the first insulating layer from diffusing to the conductive layer 260 and the conductive layer 260 from being oxidized. In addition, it is possible to prevent a decrease in the amount of oxygen supplied from the first insulating layer to the oxide semiconductor layer 230.
  • the insulating layer 250 it is preferable to use a four-layer structure in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer having a material with a low relative dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the oxide semiconductor layer 230 side.
  • the first insulating layer to the third insulating layer can have a similar structure to the layers used in the above-mentioned three-layer structure.
  • the fourth insulating layer is a layer in contact with the oxide semiconductor layer 230.
  • the fourth insulating layer has a barrier property against oxygen, so that oxygen can be prevented from being released from the oxide semiconductor layer 230.
  • aluminum oxide may be used as the fourth insulating layer.
  • Aluminum oxide has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230.
  • each layer constituting the insulating layer 250 is thin.
  • the thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion.
  • the film thicknesses of the fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively.
  • the insulating layer 283 is preferably a barrier insulating layer against hydrogen. This can suppress the diffusion of hydrogen from above the insulating layer 283 to the oxide semiconductor layer 230. Silicon nitride films and silicon nitride oxide films each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used for the insulating layer 283.
  • a barrier insulating layer against oxygen for the insulating layer 283 the oxygen contained in the oxide semiconductor layer 230 is suppressed from diffusing to the insulating layer 283 side, and an increase in oxygen vacancies in the oxide semiconductor layer 230 can be suppressed.
  • silicon nitride deposited by sputtering As the insulating layer 283.
  • Sputtering does not require the use of a gas containing hydrogen in the deposition gas, and therefore the hydrogen concentration in the insulating layer 283 can be reduced.
  • silicon nitride with high density can be formed.
  • an insulating layer having a function of capturing or fixing hydrogen can be used. With such a configuration, it is possible to suppress the diffusion of hydrogen from above the insulating layer 283 to the oxide semiconductor layer 230, and further to capture or fix the hydrogen contained in the oxide semiconductor layer 230. Therefore, it is possible to reduce the hydrogen concentration in the oxide semiconductor layer 230.
  • hafnium silicate or the like can be used.
  • the insulating layer 283 can have a laminated structure of an insulating layer that has the function of capturing or fixing hydrogen, and a barrier insulating layer against hydrogen.
  • the insulating layer 283 can be a laminated film of aluminum oxide and silicon nitride on the aluminum oxide.
  • the insulating layer 285 functions as an interlayer film, it is preferable to use a material with a low dielectric constant as described above. For example, it is preferable that the insulating layer 285 has a silicon oxide film.
  • a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements, etc.
  • a nitride of the alloy or an oxide of the alloy may be used.
  • a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • Conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are not easily oxidized, have a function of suppressing the diffusion of oxygen, or are materials that maintain low electrical resistance even when oxygen is absorbed.
  • Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide.
  • ITO indium oxide containing titanium oxide
  • ITSO indium tin oxide with added silicon
  • IZO indium zinc oxide
  • a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.
  • Conductive materials based on tungsten, copper, or aluminum are preferred due to their high conductivity.
  • a plurality of conductive layers made of the above materials may be stacked.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen.
  • a laminate structure may also be formed by combining the above-mentioned material containing a metal element with a conductive material containing nitrogen.
  • a laminate structure may also be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen and a conductive material containing nitrogen.
  • a metal oxide is used for the channel formation region of a transistor
  • the conductive layer 220 and the conductive layer 240 are each a conductive layer in contact with the oxide semiconductor layer 230, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, an oxide conductive material, or a conductive material that has a function of suppressing oxygen diffusion.
  • a conductive material that contains nitrogen and a conductive material that contains oxygen This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.
  • the electrical resistance can be kept low even if the conductive layer 220 or the conductive layer 240 absorbs oxygen. Also, even when an insulating layer containing oxygen such as hafnium oxide is used as the insulating layer 210, the conductive layer 220 is preferable because it can keep the electrical resistance low.
  • ITO, ITSO, IZO (registered trademark), etc. are preferably used as the conductive layer 220 and the conductive layer 240, respectively.
  • the conductive layer 220 has a three-layer structure of a conductive layer 220a, a conductive layer 220b on the conductive layer 220a, and a conductive layer 220c on the conductive layer 220b.
  • a conductive material containing oxygen is used as the conductive layer 220c that contacts the oxide semiconductor layer 230.
  • a conductive material containing oxygen is more preferable to use as the conductive layer 220c that contacts the oxide semiconductor layer 230.
  • titanium nitride as the conductive layer 220a, tungsten as the conductive layer 220b, and ITO or ITSO as the conductive layer 220c.
  • titanium nitride contacts the insulating layer 210
  • ITO or ITSO contacts the oxide semiconductor layer 230.
  • the conductive layer 220 can be prevented from being oxidized by the insulating layer 210, and the electrical resistance can be prevented from increasing.
  • tungsten which has high electrical conductivity, as the conductive layer 220b, the electrical resistance of the conductive layer 220 can be reduced.
  • FIG. 3A shows a configuration in which the upper surface of the conductive layer 220 is flat, but this is not a limited aspect of the present invention.
  • a recess that overlaps with the opening 290 may be formed on the upper surface of the conductive layer 220.
  • the conductive layer 240 has a two-layer structure of a conductive layer 240a and a conductive layer 240b on the conductive layer 240a.
  • a material having a higher conductivity than the conductive layer 240b as the conductive layer 240a, and to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen as the conductive layer 240b.
  • a conductive material containing oxygen as the conductive layer 240b in contact with the oxide semiconductor layer 230.
  • the conductive layer 260 preferably has high conductivity because it functions as a gate wiring. It is preferable to use a highly conductive material such as tungsten for the conductive layer 260. It is also preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen for the conductive layer 260. As described above, examples of the conductive material include conductive materials that contain nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials that contain oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.
  • nitrogen e.g., titanium nitride or tantalum nitride
  • conductive materials that contain oxygen e.g., ruthenium oxide
  • the conductive layer 260 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed.
  • the conductive material containing the metal element and nitrogen described above for example, titanium nitride, tantalum nitride, etc.
  • one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • the substrate on which the transistor is formed for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used.
  • a insulating substrate for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), a resin substrate, etc. are available.
  • a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide, etc. are available.
  • Fig. 8A is a plan view of a semiconductor device including a transistor 200B.
  • Fig. 8B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 8A.
  • Fig. 8C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 8A.
  • Fig. 8D is a cross-sectional view taken along dashed dotted line A5-A6 in Figs. 8B and 8C.
  • Fig. 9 shows an enlarged view of Fig. 8B.
  • an insulating layer 222 is provided on an insulating layer 210, and a conductive layer 220 and an insulating layer 280 are provided on the insulating layer 222.
  • the insulating layer 222 is preferably an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen in the oxide semiconductor layer 230 to diffuse into the insulating layer 222 via the conductive layer 220, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.
  • Insulating layer 281a has a region in contact with the upper surface of insulating layer 280 (here, insulating layer 280c), a region in contact with the side of conductive layer 260, and a region in contact with the upper surface of conductive layer 260. Insulating layer 281c has a region in contact with the lower surface of conductive layer 240.
  • the conductive layer 260 is oxidized by the oxygen contained in the insulating layer 280b, and the electrical resistance of the conductive layer 260 is prevented from increasing.
  • the conductive layer 260 is oxidized by the oxygen contained in the insulating layer 281b, and the electrical resistance of the conductive layer 240 is prevented from increasing.
  • silicon nitride can be used for insulating layers 280a, 280c, 281a, and 281c
  • silicon oxide can be used for insulating layers 280b and 281b.
  • Different materials can be used for part or all of insulating layers 280a, 280c, 281a, and 281c.
  • Different materials can also be used for insulating layers 280b and 281b.
  • different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.
  • Fig. 10A is a plan view of a semiconductor device including a transistor 200C.
  • Fig. 10B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 10A.
  • Fig. 10C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 10A.
  • Fig. 10D is a cross-sectional view taken along dashed dotted line A5-A6 in Figs. 10B and 10C.
  • the semiconductor device shown in Figures 10A to 10D differs from the semiconductor device shown in Figures 1A to 1D mainly in that it has an insulating layer 223.
  • the insulating layer 223 is provided so as to cover the oxide semiconductor layer 230.
  • the insulating layer 223 has regions in contact with the upper and side surfaces of the oxide semiconductor layer 230, the upper and side surfaces of the conductive layer 240, and the upper surface of the insulating layer 281.
  • An insulating layer 283 is provided on the insulating layer 223.
  • the oxide semiconductor layer 230 has regions in contact with the insulating layer 223 and the insulating layer 250 and sandwiched between them.
  • an insulating layer having a function of capturing or fixing hydrogen as the insulating layer 223. This allows the oxide semiconductor layer 230 to be in contact with the insulating layers (here, the insulating layer 250 and the insulating layer 223) having a function of capturing or fixing hydrogen and to be sandwiched between these insulating layers.
  • the insulating layer 283 is preferably an insulating layer having a function of capturing or fixing hydrogen.
  • the insulating layer 223 is preferably an insulating layer having a function of capturing or fixing hydrogen. This allows the oxide semiconductor layer 230 to be sandwiched between insulating layers having a function of capturing or fixing hydrogen (here, insulating layer 250 and insulating layer 223), and a barrier insulating layer for hydrogen (here, insulating layer 283) to be provided on the outside. With this configuration, the diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed, and the hydrogen concentration in the oxide semiconductor layer 230 can be further reduced.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, CVD, vacuum deposition, PLD, and ALD.
  • Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner.
  • RF sputtering is mainly used when depositing insulating films
  • DC sputtering is mainly used when depositing metal conductive films.
  • Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using the reactive sputtering method.
  • CVD methods can be classified into plasma CVD (PECVD) which uses plasma, thermal CVD (TCVD: Thermal CVD) which uses heat, and photo CVD (Photo CVD) which uses light. They can also be further divided into metal CVD (MCVD: Metal CVD) and metal organic CVD (MOCVD: Metal CVD) depending on the source gas used.
  • PECVD plasma CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal CVD
  • the plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can reduce plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, with the thermal CVD method, which does not use plasma, such plasma damage does not occur, and the yield of semiconductor devices can be increased. Furthermore, with the thermal CVD method, no plasma damage occurs during film formation, so films with fewer defects can be obtained.
  • the ALD method can be a thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy, or a PEALD method in which a plasma-excited reactant is used.
  • the CVD and ALD methods are different from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios.
  • the ALD method since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.
  • the CVD method allows the deposition of a film of any composition by varying the flow rate ratio of the raw material gases.
  • the CVD method allows the deposition of a film whose composition changes continuously by changing the flow rate ratio of the raw material gases while the film is being deposited.
  • the time required for deposition can be shortened compared to deposition using multiple deposition chambers, since no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.
  • a film of any composition can be formed by simultaneously introducing multiple different types of precursors.
  • a film of any composition can be formed by controlling the number of cycles of each precursor.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed by wet film formation methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • the thin film When processing the thin film that constitutes the semiconductor device, a photolithography method or the like can be used.
  • the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method, or the like.
  • island-shaped thin films may be directly formed using a film formation method that uses a shielding mask such as a metal mask.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these.
  • ultraviolet light, KrF laser light, ArF laser light, etc. can also be used.
  • Exposure can also be performed by immersion exposure technology.
  • Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure.
  • Electron beams can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.
  • Methods such as dry etching, wet etching, and sandblasting can be used to etch thin films.
  • the oxide semiconductor layer 230 and the insulating layer 250 are shown as single layers.
  • a conductive layer 220 is formed on an insulating layer 210, and an insulating layer 280 is formed on the conductive layer 220.
  • planarization treatment for example, a chemical mechanical polishing (CMP) method can be used.
  • CMP chemical mechanical polishing
  • a conductive layer 260 is formed on the insulating layer 280, and an insulating layer 281 is formed on the conductive layer 260.
  • the planarization treatment on the insulating layer 281 to planarize the upper surface of the insulating layer 281.
  • the planarization treatment does not have to be performed, and in that case, the manufacturing cost can be reduced.
  • the conductive film is a conductive film 240A that will become the conductive layer 240a and a conductive film 240B that will become the conductive layer 240b.
  • the film 276A is formed on the conductive film 240B.
  • the film 276A can be formed by sputtering, CVD, MBE, PLD, or ALD.
  • the film 276A functions as a mask layer for forming an opening 290 in the insulating layer 280, the insulating layer 281, the conductive layer 260, the conductive film 240A, and the conductive film 240B in a later process.
  • the mask layer can also be called a hard mask.
  • the film 276A can be continuously formed without exposure to the air. This can increase productivity.
  • the conductive film 240A, the conductive film 240B, and the film 276A can be continuously formed using the same sputtering device.
  • a resist mask 279 is formed on the film 276A.
  • the film 276A is processed using the resist mask 279 as a mask to form a layer 276 having an opening 290A.
  • the opening 290A is provided in an area that overlaps with the opening 290.
  • the resist mask 279 is removed.
  • the conductive film 240A, the conductive film 240B, the conductive layer 260, the insulating layer 280, and the insulating layer 281 are processed using the layer 276 as a mask to form the conductive film 240A, the conductive film 240B, the conductive layer 260, the insulating layer 280, and the insulating layer 281 having an opening 290.
  • the layer 276 functions as a hard mask. Note that here, a configuration in which the upper surface of the conductive layer 220 is flat is shown. As shown in FIG. 7A, a recess overlapping the opening 290 can also be formed in the upper surface of the conductive layer 220.
  • the aspect ratio of the opening 290 is large, it is preferable to use anisotropic etching to process the conductive film 240A, the conductive film 240B, the conductive layer 260, the insulating layer 280, and the insulating layer 281.
  • anisotropic etching to process the conductive film 240A, the conductive film 240B, the conductive layer 260, the insulating layer 280, and the insulating layer 281.
  • processing by a dry etching method is preferable because it is suitable for fine processing.
  • the processing conditions may be different for each of the conductive film 240B, the conductive layer 260, the insulating layer 280, and the insulating layer 281.
  • the inclinations of the side surfaces of the conductive film 240A, the conductive film 240B, the conductive layer 260, the insulating layer 280, and the insulating layer 281 in the opening 290 may differ from one another.
  • a heat treatment may be performed.
  • the heat treatment is performed, for example, at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower.
  • the heat treatment can be performed in an atmosphere of nitrogen gas, inert gas, or dry air (CDA: Clean Dry Air). Alternatively, the heat treatment can be performed in an atmosphere containing a plurality of these. Alternatively, the heat treatment can be performed under reduced pressure. By performing the heat treatment, impurities such as water contained in the insulating layer 280 and the insulating layer 281 can be reduced. It is preferable that the gas and dry air used in the heat treatment have high purity. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulating layer 280 and the insulating layer 281 as much as possible.
  • an insulating film 250A is formed to cover the opening 290A and the opening 290, and a film 254A is formed to cover the insulating film 250A.
  • the insulating film 250A will later become the insulating layer 250.
  • the insulating film 250A is provided in contact with the upper surface of the conductive layer 220, the side of the insulating layer 280, the side of the conductive layer 260, the side of the insulating layer 281, and the upper surface and side of the conductive layer 240.
  • the film 254A functions as a dummy layer for processing the insulating film 250A into the insulating layer 250 in a later process, and the dummy layer is removed after the insulating layer 250 is formed.
  • a material with a high selection ratio for the film 254A In removing the dummy layer, it is preferable to use a material with a high selection ratio for the film 254A. Specifically, in removing the dummy layer, it is preferable to use a material with an etching rate faster than the etching rate of the insulating layer 250 for the film 254A. This can prevent the insulating layer 250 from becoming thin when the dummy layer is removed.
  • a metal material and an inorganic insulating material can be used as the film 254A.
  • silicon oxide is used for the insulating layer 250
  • aluminum oxide can be suitably used for the film 254A.
  • a metal oxide that can be used for the oxide semiconductor layer 230 can be used for the film 254A.
  • IGZO indium gallium zinc oxide
  • the insulating film 250A and the film 254A are provided in the opening 290 with a large aspect ratio. Therefore, it is preferable to use a film formation method with good coverage for forming the insulating film 250A and the film 254A, and it is more preferable to use a CVD method or an ALD method.
  • insulating film 250A and film 254A are processed to form insulating layer 250 and layer 254.
  • the upper and side surfaces of layer 276 are exposed, and part of the upper surface of conductive layer 220 (conductive layer 220c in this case) is exposed in opening 290.
  • insulating layer 250 is formed in contact with the sidewall and part of the bottom of opening 290, and layer 254 is formed in contact with insulating layer 250.
  • protrusion 250p is formed in the region where the upper surface of insulating layer 250 and layer 254 are in contact.
  • Anisotropic etching can be suitably used to form insulating layer 250 and layer 254.
  • layer 276 is removed.
  • a dry etching method can be suitably used to remove layer 276.
  • the layer 254 is removed.
  • a wet etching method can be suitably used for removing the layer 254.
  • damage to the insulating layer 250 that functions as a gate insulating layer can be suppressed.
  • a developer for example, a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixed solution containing two or more of these, etc., can be preferably used.
  • TMAH tetramethylammonium hydroxide
  • a mixed acid-based chemical solution containing water, phosphoric acid, dilute hydrofluoric acid, and nitric acid may be used.
  • the chemical solution used in the wet etching process may be alkaline or may be acidic.
  • layer 254 is removed after layer 276
  • one embodiment of the present invention is not limited to this.
  • the order of the step of removing layer 276 and the step of removing layer 254 does not matter.
  • Layer 276 can also be removed after layer 254 is removed.
  • layers 276 and 254 can be removed in the same step.
  • the oxide semiconductor layer 230 is formed.
  • the oxide semiconductor layer 230 is provided in contact with the upper surface of the conductive layer 220, the upper surface and side surfaces of the insulating layer 250, and the upper surface of the conductive layer 240.
  • the insulating layer 250 By forming the insulating layer 250 with the layer 276 provided on the conductive layer 240, the insulating layer 250 is not formed on the upper surface of the conductive layer 240. In addition, by removing the layer 276 and forming the oxide semiconductor layer 230 with the conductive layer 240 exposed, it is possible to achieve a configuration in which the oxide semiconductor layer 230 is in contact with the conductive layer 240. This makes it possible to form a region in the oxide semiconductor layer 230 that is in contact with the conductive layer 240, that is, the other of the source region and the drain region.
  • the oxide semiconductor layer 230 can be formed, for example, by sputtering, CVD, MBE, PLD, or ALD.
  • the oxide semiconductor layer 230 is preferably formed in the opening 290 along the side of the insulating layer 250 with a thickness as uniform as possible.
  • a thin film can be formed with good controllability. Therefore, it is preferable to form the oxide semiconductor layer 230 using the ALD method.
  • the oxide semiconductor layer 230 has high crystallinity, the diffusion of impurities in the oxide semiconductor layer 230 is suppressed, so that the electrical characteristics of the transistor are less likely to fluctuate and reliability can be improved.
  • the oxide semiconductor layer 230 is formed by a sputtering method, it is easier to form a layer with high crystallinity than when the ALD method is used, which is preferable.
  • the oxide semiconductor layer 230 is formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas.
  • the sputtering gas By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.
  • an In-M-Zn oxide target or the like can be used.
  • an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and not more than 100%, preferably 70% to 100%, inclusive.
  • a transistor using an oxygen-excessive oxide semiconductor in a channel formation region can have relatively high reliability.
  • one embodiment of the present invention is not limited thereto.
  • An oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%, inclusive.
  • a transistor using an oxygen-deficient oxide semiconductor in a channel formation region can have relatively high field-effect mobility.
  • the crystallinity of the oxide semiconductor layer can be improved by forming the film while heating the substrate.
  • the oxide semiconductor layer 230 is processed into an island shape.
  • the heat treatment is preferably performed within a temperature range in which the oxide semiconductor layer 230 does not become polycrystallized.
  • the temperature of the heat treatment is preferably 100°C or higher, 250°C or higher, or 350°C or higher, and is preferably 650°C or lower, 600°C or lower, or 550°C or lower.
  • the gas used in the above heat treatment is preferably highly purified.
  • a highly purified gas By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being introduced into the oxide semiconductor layer 230 as much as possible.
  • the heat treatment is performed at a temperature of 450° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas of 4:1.
  • a heat treatment including oxygen gas impurities such as carbon, water, and hydrogen in the oxide semiconductor layer 230 can be reduced.
  • impurities in the film By reducing the impurities in the film in this way, the crystallinity of the oxide semiconductor layer 230 can be improved, and a denser and more compact structure can be obtained.
  • This increases the crystalline region in the oxide semiconductor layer 230, and reduces the in-plane variation of the crystalline region in the oxide semiconductor layer 230. Therefore, the in-plane variation of the electrical characteristics of the transistor can be reduced.
  • the insulating layer 250 contains oxygen
  • conductive film 240A and conductive film 240B are processed into an island shape to form conductive layer 240 (conductive layer 240a and conductive layer 240b).
  • the oxide semiconductor layer 230 is processed into an island shape and then the conductive layer 240 is processed into an island shape has been described here, one embodiment of the present invention is not limited thereto.
  • the order of the step of processing the conductive layer 240 into an island shape and the step of processing the oxide semiconductor layer 230 into an island shape is not particularly limited.
  • the oxide semiconductor layer 230 can be processed into an island shape.
  • the conductive layer 240 and the oxide semiconductor layer 230 can be processed in the same step by using the same mask. This can simplify the manufacturing process of the semiconductor device. For example, exposure using a multi-tone mask (typically a half-tone mask or a gray-tone mask) may be used for these processes.
  • a multi-tone mask typically a half-tone mask or a gray-tone mask
  • an insulating layer 283 is formed on the oxide semiconductor layer 230 and the conductive layer 240, and an insulating layer 285 is formed on the insulating layer 283.
  • the planarization treatment on the insulating layer 285 to planarize the top surface of the insulating layer 285.
  • the planarization treatment does not have to be performed, and in that case, the manufacturing cost can be reduced.
  • a semiconductor device can be manufactured.
  • the memory device of one embodiment of the present invention includes a memory cell.
  • the memory cell includes a transistor and a capacitor.
  • Fig. 15A is a plan view of a memory device including a transistor 200A and a capacitor 100.
  • Fig. 15B is a cross-sectional view taken along dashed line A1-A2 in Fig. 15A.
  • Fig. 15C is a cross-sectional view taken along dashed line A3-A4 in Fig. 15A.
  • 15A to 15C includes an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a memory cell 150 on the conductive layer 110, an insulating layer 180 on the conductive layer 110, an insulating layer 280, an insulating layer 281, an insulating layer 283 on the memory cell 150, and an insulating layer 285 on the insulating layer 283.
  • the insulating layer 140, the insulating layer 180, the insulating layer 280, the insulating layer 281, the insulating layer 283, and the insulating layer 285 function as interlayer films.
  • the conductive layer 110 and the conductive layer 260 function as wiring.
  • the memory cell 150 has a capacitance element 100 on a conductive layer 110 and a transistor 200A on the capacitance element 100.
  • the capacitance element 100 has a conductive layer 115 on the conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 120 on the insulating layer 130.
  • the conductive layer 120 functions as one of a pair of electrodes (sometimes called the upper electrode)
  • the conductive layer 115 functions as the other of the pair of electrodes (sometimes called the lower electrode)
  • the insulating layer 130 functions as a dielectric.
  • the capacitance element 100 constitutes a MIM (Metal-Insulator-Metal) capacitance.
  • the insulating layer 180 has an opening 190 that reaches the conductive layer 110. At least a portion of the conductive layer 115 is disposed in the opening 190.
  • the conductive layer 115 has a region that contacts the upper surface of the conductive layer 110 in the opening 190, a region that contacts the side surface of the insulating layer 180 in the opening 190, and a region that contacts at least a portion of the upper surface of the insulating layer 180.
  • the insulating layer 130 is disposed so that at least a portion of it is located in the opening 190.
  • the conductive layer 120 is disposed so that at least a portion of it is located in the opening 190. As shown in FIG.
  • the conductive layer 120 is preferably disposed so as to fill the opening 190.
  • the films disposed in the openings 190 are preferably formed using the ALD method. This improves the coverage of the films.
  • the conductive layer 115, the insulating layer 130, and the conductive layer 120 are each formed using the ALD method.
  • the upper electrode and the lower electrode face each other with a dielectric between them, not only on the bottom surface but also on the side surfaces, so that the capacitance per unit area can be increased. Therefore, the deeper the opening 190, the greater the capacitance of the capacitance element 100 can be. Increasing the capacitance per unit area of the capacitance element 100 in this way can stabilize the read operation of the memory device. It can also promote miniaturization or high integration of memory devices.
  • 15B and 15C show an example in which the sidewall of the opening 190 is perpendicular to the upper surface of the conductive layer 110.
  • the opening 190 has a cylindrical shape.
  • a conductive layer 115 and an insulating layer 130 are laminated along the sidewall of the opening 190 and the upper surface of the conductive layer 110.
  • a conductive layer 120 is provided on the insulating layer 130 so as to fill the opening 190.
  • a capacitance element 100 having such a configuration can be called a trench type capacitance or a trench capacitance.
  • An insulating layer 280 is disposed on the capacitance element 100. That is, the insulating layer 280 is disposed on the conductive layer 115, the insulating layer 130, and the conductive layer 120. In other words, the conductive layer 120 is disposed below the insulating layer 280.
  • the transistor 200A has a conductive layer 120 (corresponding to the conductive layer 220 in FIG. 1B, etc.), a conductive layer 260 on the insulating layer 280, a conductive layer 240 on the insulating layer 281, an oxide semiconductor layer 230, and an insulating layer 250.
  • the description of FIG. 1A to FIG. 7B can be referred to for the transistor 200A, and therefore detailed description thereof will be omitted.
  • the transistor included in the memory cell 150 is not limited to the transistor 200A, and each of the transistors exemplified in the first embodiment can be applied.
  • the transistor 200A is provided so as to overlap with the capacitor 100.
  • the opening 290 in which part of the structure of the transistor 200A is provided has an area overlapping with the opening 190 in which part of the structure of the capacitor 100 is provided.
  • the conductive layer 120 functions as one of the source electrode and drain electrode of the transistor 200A and as the upper electrode of the capacitor 100, so that the transistor 200A and the capacitor 100 share part of their structures.
  • the transistor 200A and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of the memory cell 150, so that the memory cells 150 can be arranged at a high density, and the memory capacity of the memory device can be increased. In other words, the memory device can be highly integrated.
  • the transistor 200A By providing the transistor 200A above the capacitor 100, the transistor 200A does not undergo the manufacturing process of the capacitor 100 and is therefore not affected by the heat applied during the manufacturing process. Therefore, in the transistor 200A, it is possible to suppress the deterioration of electrical characteristics such as fluctuations in threshold voltage and increases in parasitic resistance, as well as the increase in variation in electrical characteristics due to the deterioration of electrical characteristics.
  • FIG. 20A A circuit diagram of the memory device shown in this embodiment is shown in FIG. 20A.
  • the configuration shown in FIG. 15A to FIG. 15C functions as a memory cell.
  • the memory cell 951 has a transistor M1 and a capacitance element CA.
  • the transistor M1 corresponds to the transistor 200A
  • the capacitance element CA corresponds to the capacitance element 100.
  • One of the source and drain of transistor M1 is connected to one of a pair of electrodes of capacitance element CA.
  • the other of the source and drain of transistor M1 is connected to wiring BIL.
  • the gate of transistor M1 is connected to wiring WOL.
  • the other of the pair of electrodes of capacitance element CA is connected to wiring CAL.
  • the wiring BIL corresponds to the conductive layer 240
  • the wiring WOL corresponds to the conductive layer 260
  • the wiring CAL corresponds to the conductive layer 110.
  • the conductive layer 240 is provided extending in the X direction
  • the conductive layer 260 is provided extending in the Y direction.
  • the wiring BIL and the wiring WOL are provided crossing each other.
  • the wiring CAL (conductive layer 110) may be provided in a planar shape.
  • the wiring CAL (conductive layer 110) may be provided parallel to the wiring WOL (conductive layer 260) or parallel to the wiring BIL (conductive layer 240).
  • the capacitor 100 includes a conductive layer 115, an insulating layer 130, and a conductive layer 120.
  • a conductive layer 110 is provided under the conductive layer 115.
  • the conductive layer 115 has a region in contact with the conductive layer 110.
  • the conductive layer 110 is provided on the insulating layer 140.
  • the conductive layer 110 functions as a wiring CAL and can be provided in a planar shape, for example.
  • the conductive layer 110 can be formed as a single layer or a stacked layer using the conductive material described in the [Conductive Layer] section of embodiment 1.
  • a conductive material with high conductivity such as tungsten, can be used as the conductive layer 110.
  • the conductivity of the conductive layer 110 can be improved and the conductive layer 110 can function sufficiently as a wiring CAL.
  • the conductive layer 115 is preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen, either in a single layer or in a laminated form.
  • a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen either in a single layer or in a laminated form.
  • titanium nitride or indium tin oxide with added silicon may be used.
  • tungsten Alternatively, for example, a structure in which titanium nitride is laminated on tungsten may be used.
  • a structure in which tungsten is laminated on a first titanium nitride, and a second titanium nitride is laminated on the tungsten may be used.
  • the insulating layer 130 when an oxide is used for the insulating layer 130, the insulating layer 130 can suppress the conductive layer 110 from being oxidized. Also, when an oxide is used for the insulating layer 180, the insulating layer 180 can suppress the conductive layer 110 from being oxidized.
  • the insulating layer 130 is provided on the conductive layer 115.
  • the insulating layer 130 is provided so as to contact the upper surface and side surfaces of the conductive layer 115.
  • the insulating layer 130 has a structure that covers the side end portions of the conductive layer 110. This can prevent the conductive layer 115 and the conductive layer 120 from shorting out.
  • the side end of the insulating layer 130 and the side end of the conductive layer 115 may be structured to coincide or approximately coincide.
  • the insulating layer 130 and the conductive layer 115 can be formed using the same mask, simplifying the manufacturing process of the memory device.
  • the insulating layer 130 can be made thick enough to suppress leakage current, while still ensuring sufficient capacitance for the capacitance element 100.
  • the insulating layer 130 is preferably made of a laminate of insulating layers made of a high-k material, and preferably has a laminate structure of a material with a high dielectric constant (high-k) and a material with a higher dielectric strength than the high-k material.
  • the insulating layer 130 can be made of an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide.
  • the insulating film can be made of an insulating film laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide.
  • the insulating film can be made of an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide.
  • the dielectric strength is improved, and electrostatic breakdown of the capacitance element 100 can be suppressed.
  • a material that can have ferroelectric properties may be used as the insulating layer 130.
  • materials that can have ferroelectric properties please refer to the description of embodiment 1.
  • Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even when the thickness is a few nm, and are therefore preferred as the insulating layer 130.
  • the thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm to 9 nm). For example, the thickness is preferably 8 nm to 12 nm.
  • Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and are therefore preferable as the insulating layer 130.
  • the ferroelectric layer can have ferroelectricity even when the area (occupied area) in a plan view is 100 ⁇ m 2 or less, 10 ⁇ m 2 or less, 1 ⁇ m 2 or less, or 0.1 ⁇ m 2 or less.
  • the ferroelectric layer may have ferroelectricity even when the area is 10,000 nm 2 or less, or 1,000 nm 2 or less.
  • a ferroelectric is an insulator that has the property that polarization occurs inside when an electric field is applied from the outside, and that the polarization remains even when the electric field is made zero. For this reason, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric.
  • a nonvolatile memory element that uses a ferroelectric capacitor is sometimes called a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, etc.
  • a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance element 100, the memory device shown in this embodiment functions as a ferroelectric memory.
  • the conductive layer 120 is provided in contact with a portion of the upper surface of the insulating layer 130.
  • the side end of the conductive layer 120 is preferably located inside the side end of the conductive layer 115 in both the X direction and the Y direction.
  • the side end of the conductive layer 120 may be located outside the side end of the conductive layer 115.
  • the conductive layer 120 can be formed as a single layer or a stacked layer using the conductive material described in the [Conductive Layer] section of the first embodiment.
  • a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen For example, titanium nitride or tantalum nitride can be used.
  • a structure in which tantalum nitride is stacked on titanium nitride may be used. In this case, titanium nitride is in contact with the insulating layer 130, and tantalum nitride is in contact with the oxide semiconductor layer 230.
  • the conductive layer 120 has a region in contact with the oxide semiconductor layer 230, it is preferable to use a conductive material containing oxygen.
  • a conductive material containing oxygen as the conductive layer 120, the electrical resistance of the conductive layer 120 can be kept low even if the conductive layer 120 absorbs oxygen.
  • an insulating layer containing oxygen such as zirconium oxide
  • the conductive layer 120 is preferable because it can keep the electrical resistance low.
  • ITO, ITSO, IZO (registered trademark), etc. can be used as the conductive layer 120 in a single layer or a stacked layer.
  • the insulating layer 180 functions as an interlayer film, it is preferable that the insulating layer 180 has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. As the insulating layer 180, a single layer or a multilayer insulating layer containing a material with a low dielectric constant can be used. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the insulating layer 180 is shown as a single layer in Figures 15B and 15C, this is not a limitation of one embodiment of the present invention.
  • the insulating layer 180 can have a two-layer laminate structure.
  • the memory cell 150 including the transistor 200A and the capacitor 100 described in this embodiment can be used as a memory cell of a storage device.
  • the transistor 200A is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor.
  • the transistor 200A has a small off-state current; therefore, when used in a storage device, stored content can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the storage device can be sufficiently reduced. Furthermore, the high frequency characteristics of the transistor 200A allow high-speed reading and writing of the storage device.
  • a memory cell array By arranging the memory cells 150 in a three-dimensional matrix, a memory cell array can be formed.
  • FIG. 16A is a plan view of a memory device.
  • FIG. 16A shows an example in which 2 ⁇ 2 memory cells (memory cells 150a to 150d) are arranged in the X and Y directions.
  • FIG. 16B is a cross-sectional view taken along dashed line A3-A4 in FIG. 16A.
  • two memory cells (memory cell 150a and memory cell 150b in FIG. 16B) are connected to a common wiring (conductive layer 246).
  • each of the memory cells 150a and 150b shown in FIG. 16A and FIG. 16B has the same configuration as the memory cell 150.
  • the memory cell 150a has a capacitor 100a and a transistor 200a
  • the memory cell 150b has a capacitor 100b and a transistor 200b.
  • the memory cells 150c and 150d shown in FIG. 16A also have the same configuration as the memory cell 150. Therefore, in the memory device shown in FIG. 16A and FIG. 16B, the same reference numerals are attached to structures having the same functions as the structures constituting the memory device shown in FIG. 15.
  • the description of the memory cell 150 in ⁇ Configuration Example 1 of Memory Device> can be referred to.
  • a conductive layer 260 functioning as a wiring WOL is provided in each of the memory cells 150a and 150b. Also, as shown in FIG. 16A, one conductive layer 260 is provided in common to the memory cells 150a and 150c, and another conductive layer 260 is provided in common to the memory cells 150b and 150d. Also, one conductive layer 240 functioning as a part of the wiring BIL is provided in common to the memory cells 150a and 150b. That is, the conductive layer 240 is in contact with the oxide semiconductor layer 230 of the memory cell 150a and the oxide semiconductor layer 230 of the memory cell 150b. Also, the other conductive layer 240 is provided in common to the memory cells 150c and 150d.
  • 16A and 16B has conductive layers 245 and 246 that are electrically connected to memory cells 150a and 150b and function as plugs (which can also be called connection electrodes).
  • the conductive layer 245 is disposed in openings formed in insulating layers 140, 180, 130, 280, and 281, and is in contact with the bottom surface of the conductive layer 240.
  • the conductive layer 246 is disposed in openings formed in insulating layers 285 and 283, and is in contact with the top surface of the conductive layer 240. Note that the conductive layers 245 and 246 can be made of a conductive material that can be used for the conductive layer 240.
  • the insulating layer 285 functions as an interlayer film, it is preferable that the insulating layer 285 has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wiring lines can be reduced.
  • the concentration of impurities such as water and hydrogen in the insulating layer 285 is reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.
  • the conductive layers 245 and 246 function as plugs or wirings for electrically connecting circuit elements, wirings, electrodes, or terminals such as switches, transistors, capacitors, inductors, resistors, and diodes to the memory cells 150a and 150b.
  • the conductive layer 245 can be electrically connected to a sense amplifier (not shown) provided under the memory device shown in FIG. 16B
  • the conductive layer 246 can be electrically connected to a similar memory device (not shown) provided above the memory device shown in FIG. 16B.
  • the conductive layers 245 and 246 function as part of the wiring BIL. In this way, by providing a memory device or the like above or below the memory device shown in FIG. 16B, the memory capacity per unit area can be increased.
  • Memory cell 150a and memory cell 150b are configured to be linearly symmetrical with respect to the perpendicular bisector of dashed line A3-A4. Therefore, transistor 200a and transistor 200b are also arranged symmetrically with conductive layer 245 and conductive layer 246 in between.
  • conductive layer 240 functions as the other of the source electrode and drain electrode of transistor 200a and as the other of the source electrode and drain electrode of transistor 200b.
  • Transistor 200a and transistor 200b share conductive layer 245 and conductive layer 246 that function as plugs. In this way, by configuring the connection between two transistors and a plug as described above, a memory device that can be miniaturized or highly integrated can be provided.
  • the conductive layer 110 functioning as the wiring CAL may be provided in each of the memory cells 150a and 150b, or may be provided in common to the memory cells 150a and 150b. However, as shown in FIG. 16B, the conductive layer 110 is provided apart from the conductive layer 245 to prevent the conductive layer 110 and the conductive layer 245 from being short-circuited.
  • FIG. 17 shows an example in which the four memory cells shown in FIG. 16A are stacked in n layers (n is an integer of 3 or more) in the Z direction.
  • FIG. 17 is a cross-sectional view taken along dashed line A3-A4 shown in FIG. 16A.
  • the memory device shown in FIG. 17 has n memory layers 160. Specifically, memory layer 160[2] is provided on memory layer 160[1], and (n-2) memory layers are further provided on memory layer 160[2], with memory layer 160[n] provided on the topmost layer. There is no particular limit to the number of memory cells in one memory layer 160, and two or more memory cells may be included.
  • the memory cells in n memory layers 160 are electrically connected to a sense amplifier (not shown) provided below n memory layers 160 by conductive layers 245, 246, 247, 248, etc.
  • the cells can be integrated and arranged without increasing the area occupied by the memory cell array.
  • a 3D memory cell array can be constructed.
  • Figure 18 shows an example of the cross-sectional configuration of a memory device in which a layer having memory cells is stacked on top of a layer in which a drive circuit including a sense amplifier is provided.
  • a memory cell 150 (transistor 200A and capacitive element 100) is provided above transistor 300.
  • Transistor 300 is one of the transistors contained in the sense amplifier.
  • the bit line can be shortened by configuring the sense amplifier so that it overlaps with the memory cell 150. This reduces the bit line capacitance and the storage capacitance of the memory cell.
  • the memory device shown in FIG. 18 can correspond to the semiconductor device 900 described in embodiment 3. Specifically, the transistor 300 corresponds to the transistor included in the sense amplifier 927 in the semiconductor device 900. Also, the memory cell 150 corresponds to the memory cell 950.
  • the transistor 300 is provided on a substrate 311 and has a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulating layer, a semiconductor region 313 that is a part of the substrate 311, and low-resistance regions 314a and 314b that function as source and drain regions.
  • the transistor 300 can be a p-channel type or an n-channel type.
  • the semiconductor region 313 (part of the substrate 311) in which the channel is formed has a convex shape.
  • a conductive layer 316 is provided so as to cover the side and top surface of the semiconductor region 313 via an insulating layer 315.
  • the conductive layer 316 may be made of a material that adjusts the work function.
  • Such a transistor 300 is also called a FIN type transistor because it uses the convex portion of the semiconductor substrate.
  • an insulating layer that contacts the top of the convex portion and functions as a mask for forming the convex portion may be provided.
  • a semiconductor film having a convex shape may be formed by processing an SOI substrate.
  • transistor 300 shown in FIG. 18 is just an example, and the structure is not limited to this, and an appropriate transistor can be used depending on the circuit configuration or driving method.
  • a wiring layer having an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers may be provided depending on the design.
  • the conductive layer functioning as a plug or wiring may be given the same reference symbol as a group of multiple structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.
  • an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film.
  • a conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326.
  • the conductive layer 328 and the conductive layer 330 function as plugs or wiring.
  • the insulating layer that functions as an interlayer film may also function as a planarizing film that covers the uneven shape below it.
  • the top surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve flatness.
  • a wiring layer may be provided on the insulating layer 326 and the conductive layer 330.
  • insulating layer 350, insulating layer 352, and insulating layer 354 are laminated in this order.
  • conductive layer 356 is formed on insulating layer 350, insulating layer 352, and insulating layer 354. Conductive layer 356 functions as a plug or wiring.
  • the insulating layer 352 and insulating layer 354, which function as interlayer films, can be the insulating layer that can be used in the semiconductor device or memory device described above.
  • a conductive layer that functions as a plug or wiring can be made of a conductive material that can be applied to the conductive layer 240. It is preferable to use a high melting point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is preferable to use tungsten. Alternatively, it is preferable to form the conductive layer from a low resistance conductive material, such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.
  • the conductive layer 240 of the transistor 200A is electrically connected to the low-resistance region 314b that functions as the source region or drain region of the transistor 300 via the conductive layer 643, the conductive layer 642, the conductive layer 644, the conductive layer 645, the conductive layer 646, the conductive layer 356, the conductive layer 330, and the conductive layer 328.
  • the conductive layer 643 is embedded in the insulating layer 280 and the insulating layer 281.
  • the conductive layer 642 is provided on the insulating layer 130 and embedded in the insulating layer 641.
  • the conductive layer 642 can be manufactured using the same material and in the same process as the conductive layer 120.
  • the conductive layer 644 is embedded in the insulating layer 180 and the insulating layer 130.
  • the conductive layer 645 is embedded in the insulating layer 647.
  • the conductive layer 645 can be manufactured using the same material and in the same process as the conductive layer 110.
  • the conductive layer 646 is embedded in the insulating layer 648.
  • the transistor 300 and the conductive layer 110 are electrically insulated by the insulating layer 648.
  • the memory device of this embodiment has transistors with reduced parasitic capacitance, and therefore the operating speed can be increased.
  • the memory device of this embodiment has a capacitive element and a transistor stacked on top of each other, and therefore the area occupied by the memory cell in a plan view can be reduced, and a memory device with a high degree of integration can be realized.
  • the semiconductor device 900 can function as a memory device.
  • FIG. 19 shows a block diagram illustrating an example of the configuration of a semiconductor device 900.
  • the semiconductor device 900 shown in FIG. 19 has a driver circuit 910 and a memory array 920.
  • the memory array 920 has one or more memory cells 950.
  • FIG. 19 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.
  • the memory device described in embodiment 2 (such as memory cell 150) can be applied to memory cell 950.
  • the drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915.
  • the peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.
  • each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or other signals may be added.
  • Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • Signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 912.
  • the control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.
  • the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900.
  • the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.
  • the voltage generation circuit 928 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.
  • the peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950.
  • the peripheral circuit 911 has a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.
  • the row decoder 941 and column decoder 942 have the function of decoding the signal ADDR.
  • the row decoder 941 is a circuit for specifying the row to be accessed
  • the column decoder 942 is a circuit for specifying the column to be accessed.
  • the row driver 923 has the function of selecting the row specified by the row decoder 941.
  • the column driver 924 has the function of writing data to the memory cell 950, the function of reading data from the memory cell 950, the function of retaining the read data, etc.
  • the input circuit 925 has a function of holding a signal WDA.
  • the data held by the input circuit 925 is output to the column driver 924.
  • the output data of the input circuit 925 is data (Din) to be written to the memory cell 950.
  • the data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926.
  • the output circuit 926 has a function of holding Dout.
  • the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900.
  • the data output from the output circuit 926 is the signal RDA.
  • the PSW 931 has a function of controlling the supply of V DD to the peripheral circuit 915.
  • the PSW 932 has a function of controlling the supply of V HM to the row driver 923.
  • the high power supply voltage of the semiconductor device 900 is V DD
  • the low power supply voltage is GND (ground potential).
  • V HM is a high power supply voltage used to set the word line to a high level, and is higher than V DD .
  • the on/off of the PSW 931 is controlled by a signal PON1, and the on/off of the PSW 932 is controlled by a signal PON2.
  • the number of power supply domains to which V DD is supplied in the peripheral circuit 915 is one, but it may be more than one. In this case, a power switch may be provided for each power supply domain.
  • [DOSRAM] 20A shows an example of a circuit configuration of a memory cell of a DRAM.
  • a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM).
  • the memory cell 951 includes a transistor M1 and a capacitor CA.
  • the transistor M1 may have a front gate (sometimes simply called a gate) and a back gate.
  • the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected.
  • the first terminal of transistor M1 is connected to the first terminal of capacitance element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL.
  • the second terminal of capacitance element CA is connected to wiring CAL.
  • the memory cell that can be used for memory cell 950 is not limited to memory cell 951, and the circuit configuration can be changed.
  • memory cell 952 shown in FIG. 20B may be used.
  • Memory cell 952 is an example of a memory cell that does not have a capacitance element CA and a wiring CAL.
  • the first terminal of transistor M1 is in an electrically floating state.
  • the potential written through transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, as shown by the dashed line. This configuration can greatly simplify the configuration of the memory cell.
  • an OS transistor has a characteristic that its off-state current is extremely small.
  • the leakage current of transistor M1 can be made extremely low. In other words, since written data can be held by transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary.
  • the leakage current is extremely low, multi-value data or analog data can be held in memory cell 951 and memory cell 952.
  • [NOSRAM] 20C shows an example of a circuit configuration of a gain cell type memory cell having two transistors and one capacitor.
  • the memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB.
  • a storage device having a gain cell type memory cell using an OS transistor as the transistor M2 is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).
  • the first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL.
  • the second terminal of capacitance element CB is connected to wiring CAL.
  • the first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB.
  • a low-level potential sometimes called a reference potential
  • Data is written by applying a high-level potential to the wiring WOL, turning on transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitance element CB.
  • transistor M2 when transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and this potential is written to the first terminal of the capacitance element CB and the gate of transistor M3.
  • a low-level potential is applied to the wiring WOL, turning off transistor M2, thereby maintaining the potential of the first terminal of the capacitance element CB and the potential of the gate of transistor M3.
  • Data is read by applying a predetermined potential to the wiring SL.
  • the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate of transistor M3 and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held in the first terminal of capacitance element CB (or the gate of transistor M3) can be read. In other words, the information written in this memory cell can be read from the potential held in the first terminal of capacitance element CB (or the gate of transistor M3).
  • the wiring WBL and the wiring RBL may be combined into a single wiring BIL.
  • FIG. 20D An example of the circuit configuration of such a memory cell is shown in FIG. 20D.
  • Memory cell 954 is configured such that the wiring WBL and the wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. In other words, memory cell 954 is configured to operate the write bit line and the read bit line as a single wiring BIL.
  • Memory cell 955 shown in FIG. 20E is an example in which the capacitance element CB and wiring CAL in memory cell 953 are omitted.
  • memory cell 956 shown in FIG. 20F is an example in which the capacitance element CB and wiring CAL in memory cell 954 are omitted.
  • OS transistor for at least transistor M2.
  • OS transistors for transistors M2 and M3.
  • the OS transistor Since the OS transistor has the characteristic of having an extremely small off-state current, written data can be held for a long time by the transistor M2, and therefore the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. In addition, since the leakage current is extremely low, multi-value data or analog data can be held in the memory cell 953, memory cell 954, memory cell 955, and memory cell 956.
  • Memory cell 953, memory cell 954, memory cell 955, and memory cell 956, in which an OS transistor is used as transistor M2, are one form of NOSRAM.
  • Si transistors may be used as transistor M3.
  • Si transistors can increase the field effect mobility and can also be used as p-channel transistors, allowing for greater freedom in circuit design.
  • the memory cell can be configured as a unipolar circuit.
  • FIG. 20G shows a 3-transistor, 1-capacitor gain cell type memory cell 957.
  • Memory cell 957 has transistors M4 to M6 and a capacitative element CC.
  • the first terminal of transistor M4 is connected to the first terminal of the capacitance element CC, the second terminal of transistor M4 is connected to the wiring BIL, and the gate of transistor M4 is connected to the wiring WOL.
  • the second terminal of the capacitance element CC is connected to the first terminal of transistor M5 and the wiring GNDL.
  • the second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of the capacitance element CC.
  • the second terminal of transistor M6 is connected to the wiring BIL, and the gate of transistor M6 is connected to the wiring RWL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a write word line
  • the wiring RWL functions as a read word line.
  • the wiring GNDL is a wiring that provides a low-level potential.
  • Data is written by applying a high-level potential to the wiring WOL, turning on transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitance element CC.
  • transistor M4 when transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and this potential is written to the first terminal of the capacitance element CC and the gate of transistor M5.
  • a low-level potential is applied to the wiring WOL, turning off transistor M4, thereby maintaining the potential of the first terminal of the capacitance element CC and the potential of the gate of transistor M5.
  • Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL and applying a high-level potential to the wiring RWL. Since the wiring RWL is at a high-level potential, the transistor M6 is turned on and the wiring BIL and the second terminal of the transistor M5 are in a conductive state. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5, and the potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5).
  • the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5) can be read.
  • the information written in this memory cell can be read from the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5).
  • Si transistors may be used as transistors M5 and M6. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystal state of the silicon used in the semiconductor layer.
  • the memory cell can be configured as a unipolar circuit.
  • OS-SRAM 20H shows an example of a static random access memory (SRAM) using an OS transistor.
  • SRAM static random access memory
  • OS-SRAM oxide semiconductor SRAM
  • a memory cell 958 shown in FIG. 20H is a memory cell of an SRAM capable of backing up data.
  • Memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.
  • the first terminal of transistor M7 is connected to the wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10.
  • the gate of transistor M7 is connected to the wiring WOL.
  • the first terminal of transistor M8 is connected to the wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9.
  • the gate of transistor M8 is connected to the wiring WOL.
  • the second terminal of transistor MS1 is connected to the wiring VDL.
  • the second terminal of transistor MS2 is connected to the wiring VDL.
  • the second terminal of transistor MS3 is connected to the wiring GNDL.
  • the second terminal of transistor MS4 is connected to the wiring GNDL.
  • the second terminal of transistor M9 is connected to the first terminal of capacitance element CD1, and the gate of transistor M9 is connected to wiring BRL.
  • the second terminal of transistor M10 is connected to the first terminal of capacitance element CD2, and the gate of transistor M10 is connected to wiring BRL.
  • the second terminal of the capacitance element CD1 is connected to the wiring GNDL, and the second terminal of the capacitance element CD2 is connected to the wiring GNDL.
  • the wiring BIL and the wiring BILB function as bit lines
  • the wiring WOL functions as a word line
  • the wiring BRL is a wiring that controls the on/off state of the transistors M9 and M10.
  • the wiring VDL is a wiring that provides a high-level potential
  • the wiring GNDL is a wiring that provides a low-level potential.
  • Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal side of the transistor M10.
  • the memory cell 958 forms an inverter loop with the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Since the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Also, since the transistors M9 and M10 are on, the potential of the second terminal of the transistor M7 and the potential of the second terminal of the transistor M8 are held in the first terminal of the capacitance element CD2 and the first terminal of the capacitance element CD1, respectively.
  • a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL, and the transistors M7 to M10 are turned off, thereby holding the potential of the first terminal of the capacitance element CD1 and the first terminal of the capacitance element CD2.
  • the wirings BIL and BILB are precharged to a predetermined potential beforehand, and then a high-level potential is applied to the wiring WOL and a high-level potential is applied to the wiring BRL.
  • the potential of the first terminal of the capacitance element CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB.
  • the potential of the first terminal of the capacitance element CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL.
  • the potentials of the wirings BIL and BILB change from the precharged potentials to the potential of the first terminal of the capacitance element CD2 and the potential of the first terminal of the capacitance element CD1, respectively, so that the potential held in the memory cell can be read from the potential of the wiring BIL or wiring BILB.
  • OS transistors as transistors M7 to M10. This allows written data to be held for a long time by transistors M7 to M10, reducing the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be made unnecessary.
  • Si transistors may be used as transistors MS1 to MS4.
  • the driving circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Also, as shown in FIG. 21A, the driving circuit 910 and memory array 920 may be provided overlapping each other. By providing the driving circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Also, as shown in FIG. 21B, the memory array 920 may be provided in multiple layers on the driving circuit 910.
  • FIG. 22 shows a block diagram of the arithmetic unit 960.
  • the arithmetic unit 960 shown in FIG. 22 can be applied to, for example, a CPU (Central Processing Unit).
  • the arithmetic unit 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.
  • processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.
  • the arithmetic device 960 shown in FIG. 22 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990.
  • the substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface.
  • the cache 999 and the cache interface 989 may also be provided on separate chips.
  • the cache 999 is connected to a main memory provided on a separate chip via a cache interface 989.
  • the cache interface 989 has a function of supplying a portion of the data held in the main memory to the cache 999.
  • the cache interface 989 also has a function of outputting a portion of the data held in the cache 999 to the ALU 991 or register 996, etc. via the bus interface 998.
  • a memory array 920 can be provided by stacking it on the arithmetic unit 960.
  • the memory array 920 can be used as a cache.
  • the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999.
  • the cache interface 989 it is also preferable that the cache interface 989 has a drive circuit 910 as part of it.
  • the arithmetic device 960 shown in FIG. 22 is merely one example of a simplified configuration, and the actual arithmetic device 960 has a wide variety of configurations depending on the application.
  • the more cores there are, the more preferable it is, but for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more.
  • the number of bits that the arithmetic device 960 can handle in its internal arithmetic circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.
  • Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993, decoded, and then input to the ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995.
  • the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, while the arithmetic unit 960 is executing a program, the interrupt controller 994 determines and processes interrupt requests from external input/output devices, peripheral circuits, etc. based on their priority and mask state. The register controller 997 generates the address of the register 996, and reads and writes to the register 996 depending on the state of the arithmetic unit 960.
  • the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997.
  • the timing controller 995 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.
  • the register controller 997 selects the holding operation in the register 996 according to instructions from the ALU 991. That is, it selects whether the memory cells in the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, power supply voltage is supplied to the memory cells in the register 996. If holding data in capacitive elements is selected, data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.
  • Figs. 23A and 23B show perspective views of a semiconductor device 970A.
  • the semiconductor device 970A has a layer 930 in which a memory array is provided on the arithmetic device 960.
  • the layer 930 has memory arrays 920L1, 920L2, and 920L3.
  • the arithmetic device 960 and each memory array have overlapping areas.
  • Fig. 23B shows the arithmetic device 960 and layer 930 separated.
  • connection distance between them can be shortened. This allows the communication speed between them to be increased. In addition, the short connection distance allows for reduced power consumption.
  • a method for stacking the layer 930 having the memory array and the arithmetic device 960 As a method for stacking the layer 930 having the memory array and the arithmetic device 960, a method of stacking the layer 930 having the memory array directly on the arithmetic device 960 (also called monolithic stacking) may be used, or a method of forming the arithmetic device 960 and the layer 930 on different substrates, bonding the two substrates, and electrically connecting them using through-vias or conductive film bonding technology (such as Cu-Cu bonding) may be used.
  • the former method does not require consideration of misalignment during bonding, so not only can the chip size be reduced, but the manufacturing costs can also be reduced.
  • the arithmetic device 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache.
  • the memory array 920L1 can be used as an L1 cache (also called a level 1 cache)
  • the memory array 920L2 can be used as an L2 cache (also called a level 2 cache)
  • the memory array 920L3 can be used as an L3 cache (also called a level 3 cache).
  • the memory array 920L3 has the largest capacity and is accessed least frequently.
  • the memory array 920L1 has the smallest capacity and is accessed most frequently.
  • each memory array provided in the layer 930 can be used as a lower-level cache or a main memory.
  • the main memory has a larger capacity than the cache and is accessed less frequently.
  • the driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1.
  • the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2
  • the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.
  • the drive circuit 910L1 may function as part of the cache interface 989, or the drive circuit 910L1 may be configured to be connected to the cache interface 989.
  • the drive circuit 910L2 and the drive circuit 910L3 may also function as part of the cache interface 989, or may be configured to be connected to it.
  • the control circuit 912 can cause some of the multiple memory cells 950 in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.
  • the semiconductor device 900 can cause some of the multiple memory cells 950 to function as a cache, and the other part to function as a main memory. In other words, the semiconductor device 900 can function as both a cache and a main memory.
  • the semiconductor device 900 according to one aspect of the present invention can function as, for example, a universal memory.
  • a layer 930 having one memory array 920 may be provided over the computing device 960.
  • FIG. 24A shows a perspective view of the semiconductor device 970B.
  • one memory array 920 can be divided into multiple areas, each of which can be used for a different function.
  • Figure 24A shows an example in which area L1 is used as an L1 cache, area L2 as an L2 cache, and area L3 as an L3 cache.
  • the capacity of each of areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of area L1. With this configuration, it is possible to improve the efficiency of calculation processing and increase the processing speed.
  • Figure 24B shows a perspective view of semiconductor device 970C.
  • Semiconductor device 970C has a layer 930L1 having memory array 920L1 stacked on top of a layer 930L2 having memory array 920L2, and a layer 930L3 having memory array 920L3 stacked on top of that.
  • the memory array 920L1 which is physically closest to the arithmetic device 960, can be used as a higher-level cache, and the memory array 920L3, which is the furthest, can be used as a lower-level cache or main memory. With this configuration, the capacity of each memory array can be increased, thereby further improving processing power.
  • Figure 25A shows various storage devices used in semiconductor devices by hierarchy. The higher the storage device, the faster the operating speed is required, and the lower the storage device, the larger the storage capacity and the higher the recording density are required.
  • a processor such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, storage, etc. Note that although an example having up to an L3 cache is shown here, it is also possible to have even lower-level caches.
  • Registers also have the function of storing setting information for the processor.
  • a cache has the function of duplicating and storing a portion of the data stored in the main memory. By duplicating frequently used data and storing it in the cache, the speed of accessing the data can be increased.
  • the storage capacity required for a cache is less than that of the main memory, but it is required to operate at a faster speed than the main memory.
  • data that is rewritten in the cache is duplicated and supplied to the main memory.
  • the main memory has the function of holding programs, data, etc. read from storage.
  • Storage has the function of holding data that requires long-term storage and various programs used by processing units. Therefore, storage requires a larger memory capacity and higher recording density than operating speed. For example, high-capacity, non-volatile storage devices such as 3D NAND can be used.
  • a storage device (OS memory) using an oxide semiconductor according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. Therefore, as shown in FIG. 25A, the storage device according to one embodiment of the present invention can be suitably used in both the hierarchy where the cache is located and the hierarchy where the main memory is located. The storage device according to one embodiment of the present invention can also be applied to the hierarchy where the storage is located.
  • FIG. 25B shows an example in which SRAM is used for part of the cache and an OS memory according to one aspect of the present invention is used for the other part.
  • the lowest level cache can be called an LLC (Last Level cache).
  • LLC Low Level cache
  • an LLC is not required to operate faster than higher level caches, it is desirable for it to have a large storage capacity.
  • the OS memory of one embodiment of the present invention is suitable for use as an LLC because it operates quickly and can retain data for long periods of time. Note that the OS memory of one embodiment of the present invention can also be applied to an FLC (Final Level cache).
  • a configuration can be used in which SRAM is used for the higher-level cache (L1 cache, L2 cache, etc.), and the OS memory of one aspect of the present invention is used for the LLC. Also, as shown in FIG. 25B, not only the OS memory but also DRAM can be used for the main memory.
  • the semiconductor device of one embodiment of the present invention can be used for a display device or a module having the display device.
  • the module having the display device include a module in which a connector such as a flexible printed circuit (hereinafter, referred to as FPC) or a TCP (Tape Carrier Package) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a COG (Chip On Glass) method or a COF (Chip On Film) method, etc.
  • FPC flexible printed circuit
  • TCP Tape Carrier Package
  • the display device of this embodiment may have a function as a touch panel.
  • various detection elements also called sensor elements
  • various detection elements that can detect the proximity or contact of a detectable object such as a finger can be applied to the display device.
  • Sensor types include, for example, capacitive type, resistive film type, surface acoustic wave type, infrared type, optical type, and pressure sensitive type.
  • Examples of the capacitance type include the surface capacitance type and the projected capacitance type.
  • Examples of the projected capacitance type include the self-capacitance type and the mutual capacitance type.
  • the mutual capacitance type is preferable because it allows simultaneous multi-point detection.
  • touch panels examples include out-cell, on-cell, and in-cell types.
  • an in-cell touch panel is one in which electrodes constituting a sensing element are provided on one or both of the substrate supporting the display element and the opposing substrate.
  • Display module 26A shows a perspective view of the display module 170.
  • the display module 170 includes a display device 600A and an FPC 298. Note that the display device included in the display module 170 is not limited to the display device 600A and may be a display device 600B described later.
  • the display module 170 has a substrate 291 and a substrate 299.
  • the display module 170 has a display section 297.
  • the display section 297 is an area that displays an image in the display module 170, and is an area in which light from each pixel provided in a pixel section 294 described later can be viewed.
  • FIG. 26B shows a perspective view that shows a schematic configuration on the substrate 291 side.
  • a circuit section 292, a pixel circuit section 293 on the circuit section 292, and a pixel section 294 on the pixel circuit section 293 are stacked on the substrate 291.
  • a terminal section 295 for connecting to an FPC 298 is provided in a portion of the substrate 291 that does not overlap with the pixel section 294.
  • the terminal section 295 and the circuit section 292 are electrically connected by a wiring section 296 that is composed of a plurality of wirings.
  • the semiconductor device of one embodiment of the present invention can be applied to one or both of the circuit portion 292 and the pixel circuit portion 293.
  • the pixel section 294 has a number of pixels 294a arranged periodically. An enlarged view of one pixel 294a is shown on the right side of FIG. 26B.
  • FIG. 26B shows an example in which one pixel 294a has a sub-pixel 130R that emits red light, a sub-pixel 130G that emits green light, and a sub-pixel 130B that emits blue light.
  • the subpixel has a display element.
  • Various elements can be used as the display element, such as a liquid crystal element and a light-emitting element.
  • a shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) element a display element using a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type can also be used.
  • a QLED (Quantum-dot LED) using a light source and color conversion technology using quantum dot material may be used.
  • Light-emitting elements include, for example, self-emitting light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. As LEDs, for example, mini LEDs and micro LEDs can be used.
  • LEDs Light Emitting Diodes
  • OLEDs Organic LEDs
  • semiconductor lasers As LEDs, for example, mini LEDs and micro LEDs can be used.
  • pixel arrangement in the display device of this embodiment, and various methods can be applied.
  • pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a Pentile arrangement.
  • Figure 26B shows an example in which a stripe arrangement is applied to the pixel arrangement.
  • the pixel circuit section 293 has a plurality of pixel circuits 293a arranged periodically.
  • Each pixel circuit 293a is a circuit that controls the driving of multiple elements in one pixel 294a.
  • One pixel circuit 293a can be configured to have three circuits that control the light emission of one light-emitting element.
  • the pixel circuit 293a can be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitance for each light-emitting element. At this time, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display device.
  • the circuit section 292 has a circuit that drives each pixel circuit 293a of the pixel circuit section 293.
  • the circuit section 292 has one or both of a gate line driver circuit and a source line driver circuit.
  • the circuit section 292 may have at least one of an arithmetic circuit, a memory circuit, a power supply circuit, etc.
  • the FPC 298 functions as wiring for supplying a video signal, a power supply potential, etc. from the outside to the circuit section 292.
  • An IC may also be mounted on the FPC 298.
  • the display module 170 can be configured such that one or both of the pixel circuit section 293 and the circuit section 292 are stacked below the pixel section 294, so that the aperture ratio (effective display area ratio) of the display section 297 can be made extremely high.
  • the pixels 294a can be arranged at an extremely high density, so that the resolution of the display section 297 can be made extremely high.
  • a display module 170 Since such a display module 170 has extremely high resolution, it can be suitably used in VR devices such as HMDs or glasses-type AR devices. For example, even in a configuration in which the display section of the display module 170 is viewed through a lens, the display module 170 has an extremely high resolution display section 297, so that even if the display section is enlarged with a lens, the pixels are not visible, and a highly immersive display can be performed. Furthermore, the display module 170 is not limited to this, and can be suitably used in electronic devices with relatively small display sections. For example, it can be suitably used in the display section of a wearable electronic device such as a wristwatch.
  • Display Device Configuration Example 1 shows a cross-sectional view of a display device 600A.
  • the display device 600A is an example of a display device to which an MML (metal maskless) structure is applied.
  • the display device 600A has a light-emitting element manufactured without using a fine metal mask.
  • the island-shaped light-emitting layer in the light-emitting element of a display device to which the MML structure is applied is formed by depositing a light-emitting layer on one surface and then processing it using photolithography. This makes it possible to realize a high-definition display device or a display device with a high aperture ratio, which has been difficult to achieve until now. Furthermore, since the light-emitting layer can be made separately for each color, a display device with extremely vivid images, high contrast, and high display quality can be realized.
  • a display device is composed of three types of light-emitting elements, one that emits blue light, one that emits green light, and one that emits red light
  • the deposition of the light-emitting layer and processing by photolithography can be repeated three times to form three types of island-shaped light-emitting layers.
  • Devices with an MML structure can be manufactured without using a metal mask, and therefore can exceed the upper limit of fineness resulting from the alignment accuracy of the metal mask. Furthermore, when devices are manufactured without using a metal mask, the equipment required for manufacturing the metal mask and the process of cleaning the metal mask are unnecessary. Furthermore, since the same or similar equipment as that used to manufacture transistors can be used for photolithography processing, there is no need to introduce special equipment to manufacture devices with an MML structure. In this way, the MML structure makes it possible to keep manufacturing costs low, making it suitable for mass production of devices.
  • a display device to which the MML structure is applied for example, there is no need to artificially increase the resolution by applying a special pixel arrangement such as a pentile arrangement, so it is possible to realize a display device with high resolution (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more) with a so-called stripe arrangement in which R, G, and B sub-pixels are each arranged in one direction.
  • a special pixel arrangement such as a pentile arrangement
  • the sacrificial layer By providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting element can be improved.
  • the sacrificial layer may remain in the completed display device, or may be removed during the manufacturing process.
  • the sacrificial layer 618a shown in Figures 27 and 28 is part of the sacrificial layer that was provided on the light-emitting layer.
  • the display device 600A shown in FIG. 27 is a schematic cross-sectional view of a display device (semiconductor device) according to one embodiment of the present invention.
  • the display device 600A has a configuration in which a pixel circuit, a driver circuit, and the like are provided on a substrate 410.
  • a wiring layer 670 is also illustrated in the display device 600A shown in FIG. 27, in addition to the element layer 620, the element layer 630, and the element layer 660.
  • the wiring layer 670 is a layer in which wiring is provided.
  • the element layer 630 is preferably provided with a pixel circuit of the display device.
  • the element layer 620 is preferably provided with a driver circuit of the display device (one or both of a gate driver and a source driver).
  • the element layer 620 may also be provided with one or more types of circuits such as an arithmetic circuit and a memory circuit.
  • the element layer 620 has, as an example, a substrate 410 on which a transistor 400d is formed.
  • a wiring layer 670 is provided above the transistor 400d, and the wiring layer 670 has wiring that electrically connects the transistor 400d to a conductive layer or a transistor (conductive layer 514 in FIG. 27) provided in the element layer 630.
  • An element layer 630 and an element layer 660 are provided above the wiring layer 670, and the element layer 630 has, as an example, a transistor MTCK.
  • the element layer 660 has a light-emitting element 650 (light-emitting element 650R, light-emitting element 650G, and light-emitting element 650B in FIG. 27) and the like.
  • Transistor 400d is an example of a transistor included in element layer 620.
  • Transistor MTCK is an example of a transistor included in element layer 630.
  • the light-emitting elements (light-emitting element 650R, light-emitting element 650G, and light-emitting element 650B) are an example of a light-emitting element included in element layer 660.
  • the substrate 410 may be a semiconductor substrate (for example, a single crystal substrate made of silicon or germanium).
  • a silicon-on-insulator (SOI) substrate for example, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film may be used for the substrate 410 other than a semiconductor substrate.
  • the substrate 410 is described as a semiconductor substrate having silicon as a material. Therefore, the transistors included in the element layer 620 may be Si transistors.
  • the transistor 400d has an element isolation layer 412, a conductive layer 416, an insulating layer 415, an insulating layer 417, a semiconductor region 413 made of a part of the substrate 410, and a low-resistance region 414a and a low-resistance region 414b that function as a source region or a drain region. Therefore, the transistor 400d is a Si transistor. Note that although FIG. 27 shows a configuration in which one of the source and drain of the transistor 400d is electrically connected to the conductive layer 514 provided in the element layer 630 through the conductive layer 428, the conductive layer 430, and the conductive layer 456, the electrical connection configuration of the display device of one embodiment of the present invention is not limited thereto.
  • the transistor 400d can be made into a Fin type by, for example, configuring the upper surface and the side surface in the channel width direction of the semiconductor region 413 to be covered with the conductive layer 416 via the insulating layer 415 that functions as a gate insulating layer.
  • the effective channel width can be increased, and the on characteristics of the transistor 400d can be improved.
  • the contribution of the electric field of the gate electrode can be increased, and therefore the off characteristics of the transistor 400d can be improved.
  • the transistor 400d may be a planar type instead of a Fin type.
  • the transistor 400d can be a p-channel type or an n-channel type. Alternatively, multiple transistors 400d can be provided, and both p-channel and n-channel types can be used.
  • the region in which the channel of the semiconductor region 413 is formed, the region nearby, and the low resistance region 414a and low resistance region 414b that become the source region or drain region preferably contain a silicon-based semiconductor, specifically, single crystal silicon.
  • each of the above-mentioned regions may be formed using, for example, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride.
  • a configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used.
  • the transistor 400d may be, for example, a HEMT (High Electron Mobility Transistor) using gallium arsenide and aluminum gallium arsenide.
  • HEMT High Electron Mobility Transistor
  • the conductive layer 416 which functions as a gate electrode, can be made of a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron or aluminum.
  • the conductive layer 416 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material.
  • the threshold voltage of the transistor can be adjusted by selecting the material of the conductive layer. Specifically, it is preferable to use one or both of titanium nitride and tantalum nitride as the conductive layer. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use one or both of tungsten and aluminum as a laminated layer for the conductive layer, and in particular, it is preferable to use tungsten in terms of heat resistance.
  • the element isolation layer 412 is provided to isolate multiple transistors formed on the substrate 410 from each other.
  • the element isolation layer can be formed, for example, by using a LOCOS (Local Oxidation of Silicon) method, a STI (Shallow Trench Isolation) method, or a mesa isolation method.
  • LOCOS Local Oxidation of Silicon
  • STI Shallow Trench Isolation
  • an insulating layer 420 and an insulating layer 422 are stacked in this order from the substrate 410 side.
  • the insulating layer 420 and the insulating layer 422 for example, one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride can be used.
  • the insulating layer 422 may function as a planarizing film that planarizes steps caused by the insulating layer 420 and the transistor 400d covered by the insulating layer 422.
  • the top surface of the insulating layer 422 may be planarized by a planarization process using a CMP method or the like to improve the planarity.
  • a conductive layer 428 is embedded in the insulating layer 420 and the insulating layer 422, and connects to the transistor MTCK and the like that are provided above the insulating layer 422.
  • the conductive layer 428 functions as a plug or wiring.
  • a wiring layer 670 is provided on the transistor 400d.
  • the wiring layer 670 includes, for example, an insulating layer 424, an insulating layer 426, a conductive layer 430, an insulating layer 450, an insulating layer 452, an insulating layer 454, and a conductive layer 456.
  • Insulating layer 424 and insulating layer 426 are stacked in this order on insulating layer 422 and conductive layer 428.
  • an opening is formed in insulating layer 424 and insulating layer 426 in the area overlapping conductive layer 428.
  • conductive layer 430 is embedded in the opening.
  • Insulating layer 450, insulating layer 452, and insulating layer 454 are stacked in this order on insulating layer 426 and conductive layer 430. In addition, openings are formed in insulating layer 450, insulating layer 452, and insulating layer 454 in the area overlapping conductive layer 430. Conductive layer 456 is embedded in the opening.
  • the conductive layer 430 and the conductive layer 456 function as a plug or wiring that connects to the transistor 400d.
  • insulating layers having barrier properties against one or more selected from hydrogen, oxygen, and water for the insulating layers 424 and 450, similar to the insulating layer 592 described later. It is also preferable to use insulating layers having a relatively low dielectric constant for the insulating layers 426, 452, and 454, similar to the insulating layer 594 described later, in order to reduce parasitic capacitance occurring between wirings.
  • the insulating layers 426, 452, and 454 function as interlayer insulating films and planarizing films.
  • the conductive layer 456 preferably includes a conductive layer having barrier properties against one or more selected from hydrogen, oxygen, and water.
  • tantalum nitride may be used as the insulating layer having a barrier property against hydrogen.
  • tantalum nitride may be used as the insulating layer having a barrier property against hydrogen.
  • the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulating layer 450 having a barrier property against hydrogen.
  • An insulating layer 513 is provided above the insulating layer 454 and the conductive layer 456.
  • An insulating layer IS1 is provided on the insulating layer 513.
  • a conductive layer that functions as a plug or wiring is embedded in the insulating layer IS1 and the insulating layer 513. This allows the transistor 400d to be electrically connected to the conductive layer 514 provided in the element layer 630. Alternatively, one of the source and drain of the transistor MTCK and one of the source and drain of the transistor 400d may be electrically connected.
  • the transistor MTCK is provided on the insulating layer IS1. Furthermore, the insulating layer IS3, the insulating layer 574, and the insulating layer 581 are stacked in this order on the transistor MTCK. Furthermore, the insulating layer IS3, the insulating layer 574, and the insulating layer 581 are embedded with a conductive layer MPG that functions as a plug or wiring.
  • the insulating layer 574 preferably has a function of suppressing the diffusion of impurities such as water and hydrogen (e.g., hydrogen atoms and/or hydrogen molecules).
  • impurities such as water and hydrogen (e.g., hydrogen atoms and/or hydrogen molecules).
  • the insulating layer 574 preferably functions as a barrier insulating film that suppresses the impurities from being mixed into the transistor MTCK.
  • the insulating layer 574 also preferably has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and/or oxygen molecules).
  • the insulating layer 574 preferably has lower oxygen permeability than the insulating layers IS21, IS22, and IS3.
  • the insulating layer 574 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen. Therefore, the insulating layer 574 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O , NO, and NO2 ), and copper atoms (the impurities are unlikely to permeate through the insulating material). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and/or oxygen molecules) (the oxygen is unlikely to permeate through the insulating material).
  • oxygen e.g., oxygen atoms and/or oxygen molecules
  • the materials that can be used for the insulating layer having the function of suppressing the permeation of impurities and oxygen, as exemplified in embodiment 1, can be used.
  • the insulating layer 574 it is preferable to use aluminum oxide or silicon nitride for the insulating layer 574. This can prevent impurities such as water and hydrogen from diffusing from above the insulating layer 574 to the transistor MTCK. Alternatively, it can prevent oxygen contained in the insulating layer IS3, etc. from diffusing above the insulating layer 574.
  • the insulating layer 581 is a film that functions as an interlayer film, and preferably has a lower dielectric constant than the insulating layer 574.
  • the relative dielectric constant of the insulating layer 581 is preferably less than 4, and more preferably less than 3.
  • the relative dielectric constant of the insulating layer 581 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulating layer 574.
  • the insulating layer 581 preferably has a reduced concentration of impurities such as water and hydrogen in the film.
  • the insulating layer 581 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride.
  • the insulating layer 581 can be made of, for example, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies.
  • silicon oxide and silicon oxynitride are preferred because they are thermally stable.
  • materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form a region containing oxygen that is released by heating.
  • the insulating layer 581 can be made of resin.
  • the material that can be used for the insulating layer 581 may be an appropriate combination of the above-mentioned materials.
  • Insulating layer 592 and insulating layer 594 are laminated in this order on insulating layer 574 and insulating layer 581.
  • an insulating film having a barrier property that prevents impurities such as water and hydrogen from diffusing from the substrate 410 and the transistor MTCK to a region above the insulating layer 592 (for example, a region where the light-emitting element 650R, the light-emitting element 650G, and the light-emitting element 650B are provided) is preferably used. Therefore, for the insulating layer 592, an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (the impurities are unlikely to permeate through the insulating material) is preferably used.
  • an insulating material having a function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N 2 O, NO, and NO 2 ), and copper atoms (the oxygen is unlikely to permeate through the insulating material) is preferably used.
  • the insulating layer 592 has a function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules).
  • An example of a film that has barrier properties against hydrogen is silicon nitride formed by the CVD method.
  • the amount of desorption of hydrogen can be analyzed by, for example, thermal desorption spectrometry (TDS).
  • TDS thermal desorption spectrometry
  • the amount of desorption of hydrogen from the insulating layer 424 can be determined by TDS to be 10 ⁇ 10 15 atoms/cm 2 or less, preferably 5 ⁇ 10 15 atoms/cm 2 or less, per area of the insulating layer 424, when the film surface temperature is in the range of 50° C. to 500° C. , and calculated as hydrogen atoms.
  • insulating layer 594 is preferably an interlayer film with a low dielectric constant. For this reason, materials that can be used for insulating layer 581 can be used for insulating layer 594.
  • the insulating layer 594 has a lower dielectric constant than the insulating layer 592.
  • the relative dielectric constant of the insulating layer 594 is preferably less than 4, and more preferably less than 3.
  • the relative dielectric constant of the insulating layer 594 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulating layer 592.
  • a conductive layer MPG that functions as a plug or wiring is embedded in the insulating layer GI1 and the insulating layer IS3, and a conductive layer 596 that functions as a plug or wiring is embedded in the insulating layer 592 and the insulating layer 594.
  • the conductive layer MPG and the conductive layer 596 are electrically connected to a light-emitting element and the like that is provided above the insulating layer 594.
  • a conductive layer that functions as a plug or wiring may be given the same reference symbol as a group of multiple structures.
  • the wiring and the plug that connects to the wiring may be one body. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.
  • each plug and wiring for example, conductive layer MPG, conductive layer 428, conductive layer 430, conductive layer 456, conductive layer 514, and conductive layer 596
  • one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials can be used in a single layer or a stacked layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferably used. Alternatively, it is preferable to form the wiring from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.
  • Insulating layer 598 and insulating layer 599 are formed in order on insulating layer 594 and conductive layer 596.
  • insulating layer 598 As an example, it is preferable to use an insulating layer having barrier properties against one or more selected from hydrogen, oxygen, and water as insulating layer 598, similar to insulating layer 592. Also, it is preferable to use an insulating layer having a relatively low relative dielectric constant as insulating layer 599, similar to insulating layer 594, in order to reduce parasitic capacitance occurring between wirings. Also, insulating layer 599 functions as an interlayer insulating film and a planarizing film.
  • a light-emitting element 650 and a connection portion 640 are formed on the insulating layer 599.
  • connection portion 640 may be called a cathode contact portion, and is electrically connected to the cathode electrodes of the light-emitting elements 650R, 650G, and 650B.
  • a conductive layer formed in the same process and from the same material as the conductive layers 611a to 611c is electrically connected to the common electrode 615, which will be described later.
  • FIG. 27 shows an example in which the conductive layer is electrically connected to the common electrode 615 via the common layer 614, which will be described later, but the conductive layer and the common electrode 615 may be in direct contact.
  • connection portion 640 may be provided so as to surround the four sides of the display portion in a plan view, or may be provided within the display portion (e.g., between adjacent light-emitting elements 650) (not shown).
  • Light-emitting element 650R has conductive layer 611a as a pixel electrode.
  • light-emitting element 650G has conductive layer 611b as a pixel electrode
  • light-emitting element 650B has conductive layer 611c as a pixel electrode.
  • the conductive layers 611a, 611b, and 611c are each connected to the conductive layer 596 embedded in the insulating layer 594 via a conductive layer (plug) embedded in the insulating layer 599.
  • Light-emitting element 650R has layer 613a, a common layer 614 on layer 613a, and a common electrode 615 on common layer 614.
  • Light-emitting element 650G has layer 613b, a common layer 614 on layer 613b, and a common electrode 615 on common layer 614.
  • Light-emitting element 650B has layer 613c, a common layer 614 on layer 613c, and a common electrode 615 on common layer 614.
  • metals, alloys, electrically conductive compounds, and mixtures thereof can be appropriately used.
  • specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing appropriate combinations of these.
  • Indium tin oxide In-Sn oxide, also called ITO
  • In-Si-Sn oxide also called ITSO
  • indium zinc oxide In-Zn oxide
  • In-W-Zn oxide can also be used.
  • the material include alloys containing aluminum (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and alloys containing silver, such as an alloy of silver and magnesium, and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC).
  • the material include elements belonging to Group 1 or Group 2 of the periodic table (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, and alloys containing appropriate combinations of these, graphene, etc.
  • elements belonging to Group 1 or Group 2 of the periodic table e.g., lithium, cesium, calcium, strontium
  • rare earth metals such as europium and ytterbium
  • the display device 600A uses an SBS structure.
  • the SBS structure allows the material and configuration to be optimized for each light-emitting element, which increases the freedom of material and configuration selection and makes it easier to improve brightness and reliability.
  • the display device 600A is a top emission type.
  • transistors and the like can be arranged so as to overlap the light emitting region of the light emitting element, so the aperture ratio of the pixel can be increased compared to a bottom emission type.
  • layer 613a is formed so as to cover the upper surface and side surfaces of conductive layer 611a.
  • layer 613b is formed so as to cover the upper surface and side surfaces of conductive layer 611b.
  • layer 613c is formed so as to cover the upper surface and side surfaces of conductive layer 611c. Therefore, the entire region in which conductive layer 611a, conductive layer 611b, and conductive layer 611c are provided can be used as the light-emitting region of light-emitting element 650R, light-emitting element 650G, and light-emitting element 650B, and the aperture ratio of the pixel can be increased.
  • layer 613a and common layer 614 can be collectively referred to as the EL layer.
  • layer 613b and common layer 614 can be collectively referred to as the EL layer.
  • layer 613c and common layer 614 can be collectively referred to as the EL layer.
  • the EL layer has at least a light-emitting layer.
  • the light-emitting layer has one or more types of light-emitting materials.
  • a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used.
  • a material that emits near-infrared light can also be used as the light-emitting material.
  • Light-emitting materials that light-emitting elements have include, for example, materials that emit fluorescence (fluorescent materials), materials that emit phosphorescence (phosphorescent materials), materials that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).
  • fluorescent materials materials that emit fluorescence
  • phosphorescent materials materials that emit phosphorescence
  • TADF thermally activated delayed fluorescence
  • inorganic compounds quantum dot materials, etc.
  • the light-emitting layer may have one or more organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material).
  • the one or more organic compounds one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) may be used.
  • a bipolar substance a substance with high electron transport properties and hole transport properties
  • a TADF material may be used as the one or more organic compounds.
  • the EL layer may have one or more of a layer containing a substance with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a substance with high electron blocking properties (electron blocking layer), a layer containing a substance with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a substance with high hole blocking properties (hole blocking layer).
  • the EL layer may contain one or both of a bipolar substance and a TADF material.
  • Eigen elements can be made of either low molecular weight compounds or high molecular weight compounds, and may contain inorganic compounds.
  • the layers constituting the luminescent element can be formed by deposition methods (including vacuum deposition methods), transfer methods, printing methods, inkjet methods, coating methods, etc.
  • the light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units).
  • the light-emitting unit has at least one light-emitting layer.
  • the tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer has the function of injecting electrons into one of the two light-emitting units and injecting holes into the other.
  • the tandem structure makes it possible to obtain a light-emitting element capable of emitting light with high brightness. Furthermore, the tandem structure can reduce the current required to obtain the same brightness compared to a single structure, thereby improving reliability.
  • the tandem structure can also be called a stack structure.
  • Layers 613a, 613b, and 613c are processed into island shapes by photolithography. Therefore, at the ends of layers 613a, 613b, and 613c, the angle between the top surface and the side surface is close to 90 degrees.
  • an organic film formed using FMM Fine Metal Mask
  • the top surface is formed in a slope over a range of 1 ⁇ m to 10 ⁇ m to the end, resulting in a shape in which it is difficult to distinguish between the top surface and the side surface.
  • top and side surfaces of layers 613a, 613b, and 613c are clearly distinguished. As a result, in adjacent layers 613a and 613b, one side surface of layer 613a and one side surface of layer 613b are arranged opposite each other. This is the same for any combination of layers 613a, 613b, and 613c.
  • Layer 613a, layer 613b, and layer 613c each have at least a light-emitting layer.
  • layer 613a has a light-emitting layer that emits red light
  • layer 613b has a light-emitting layer that emits green light
  • layer 613c has a light-emitting layer that emits blue light.
  • each light-emitting layer can be colored in a color other than the above, such as cyan, magenta, yellow, or white.
  • the layers 613a, 613b, and 613c preferably have a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Since the surfaces of the layers 613a, 613b, and 613c may be exposed during the manufacturing process of the display device, providing the carrier transport layer on the light-emitting layer can prevent the light-emitting layer from being exposed to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting element.
  • a carrier transport layer electron transport layer or hole transport layer
  • the common layer 614 has, for example, an electron injection layer or a hole injection layer.
  • the common layer 614 may have a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer.
  • the common layer 614 is shared by the light-emitting element 650R, the light-emitting element 650G, and the light-emitting element 650B. Note that the common layer 614 does not have to be provided, and the entire EL layer of the light-emitting element may be provided in an island shape, such as the layer 613a, the layer 613b, and the layer 613c.
  • the common electrode 615 is shared by the light-emitting elements 650R, 650G, and 650B. As shown in FIG. 27, the common electrode 615 shared by the multiple light-emitting elements is electrically connected to a conductive layer included in the connection portion 640.
  • the insulating layer 625 preferably has a function as a barrier insulating layer against water and/or oxygen.
  • the insulating layer 625 preferably has a function of suppressing the diffusion of water and/or oxygen.
  • the insulating layer 625 preferably has a function of capturing or fixing (also referred to as gettering) water and/or oxygen.
  • the insulating layer 625 has a function as a barrier insulating layer or a gettering function, so that it is possible to suppress the intrusion of impurities (typically, water and/or oxygen) that may diffuse from the outside into each light-emitting element. With this structure, a highly reliable light-emitting element and a highly reliable display device can be provided.
  • the insulating layer 625 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 625 and causing deterioration of the EL layer. In addition, by lowering the impurity concentration in the insulating layer 625, the barrier properties against water and/or oxygen can be improved. For example, it is desirable that the insulating layer 625 has a sufficiently low hydrogen concentration or a sufficiently low carbon concentration, or preferably both.
  • an insulating layer containing an organic material can be suitably used.
  • the organic material it is preferable to use a photosensitive organic resin, for example, a photosensitive resin composition containing an acrylic resin.
  • acrylic resin does not only refer to polymethacrylic acid ester or methacrylic resin, but may refer to acrylic polymers in a broad sense.
  • the organic materials that can be used for the insulating layer 627 are not limited to those mentioned above.
  • the insulating layer 627 may be made of acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins.
  • the insulating layer 627 may be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral (PVB), polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin.
  • the insulating layer 627 may be made of a photoresist, for example, as a photosensitive resin. Examples of photosensitive resins include positive-type materials and negative-type materials.
  • the insulating layer 627 may be made of a material that absorbs visible light. By absorbing the light emitted from the light-emitting element with the insulating layer 627, it is possible to suppress leakage of light from the light-emitting element to an adjacent light-emitting element through the insulating layer 627 (stray light). This can improve the display quality of the display device. In addition, since the display quality can be improved without using a polarizing plate in the display device, it is possible to reduce the weight and thickness of the display device.
  • Materials that absorb visible light include materials containing pigments such as black, materials containing dyes, resin materials with light absorbing properties (e.g., polyimide), and resin materials that can be used in color filters (color filter materials).
  • resin materials with light absorbing properties e.g., polyimide
  • color filter materials resin materials that can be used in color filters
  • by mixing three or more colors of color filter materials it is possible to create a resin layer that is black or close to black.
  • the insulating layer 627 can be formed using a wet film formation method such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • a wet film formation method such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • the insulating layer 627 is formed at a temperature lower than the heat resistance temperature of the EL layer.
  • the substrate temperature when forming the insulating layer 627 is typically 200°C or lower, preferably 180°C or lower, more preferably 160°C or lower, more preferably 150°C or lower, and more preferably 140°C or lower.
  • the insulating layer 627 preferably has a tapered shape on the side.
  • the side end of the insulating layer 627 into a forward tapered shape (less than 90°, preferably 60° or less, and more preferably 45° or less)
  • the common layer 614 and common electrode 615 provided on the side end of the insulating layer 627 can be formed with good coverage without causing discontinuities or localized thinning. This can improve the in-plane uniformity of the common layer 614 and common electrode 615, thereby improving the display quality of the display device.
  • the upper surface of the insulating layer 627 preferably has a convex curved shape.
  • the convex curved shape of the upper surface of the insulating layer 627 preferably has a shape that bulges gently toward the center.
  • Insulating layer 627 is formed in the region between the two EL layers (e.g., the region between layers 613a and 613b). At this time, a portion of insulating layer 627 is disposed in a position sandwiched between a side edge of one EL layer (e.g., layer 613a) and a side edge of the other EL layer (e.g., layer 613b).
  • one end of the insulating layer 627 overlaps with the conductive layer 611a that functions as a pixel electrode, and the other end of the insulating layer 627 overlaps with the conductive layer 611b that functions as a pixel electrode.
  • the end of the insulating layer 627 can be formed on a flat or approximately flat region of the layer 613a (layer 613b). Therefore, it is relatively easy to process the tapered shape of the insulating layer 627 as described above.
  • the insulating layer 627, etc. it is possible to prevent the formation of discontinuities and locally thin areas in the common layer 614 and common electrode 615 from the flat or roughly flat area of layer 613a to the flat or roughly flat area of layer 613b. This makes it possible to prevent connection failures caused by discontinuities and increases in electrical resistance caused by locally thin areas in the common layer 614 and common electrode 615 between each light-emitting element.
  • the display device of this embodiment can narrow the distance between light-emitting elements.
  • the distance between light-emitting elements, between EL layers, or between pixel electrodes can be less than 10 ⁇ m, 8 ⁇ m or less, 5 ⁇ m or less, 3 ⁇ m or less, 2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less.
  • the display device of this embodiment has an area where the distance between two adjacent island-shaped EL layers is 1 ⁇ m or less, preferably an area where the distance is 0.5 ⁇ m (500 nm) or less, and more preferably an area where the distance is 100 nm or less. In this way, by narrowing the distance between each light-emitting element, a display device with high definition and large aperture ratio can be provided.
  • a protective layer 631 is provided on the light-emitting element 650.
  • the protective layer 631 is a film that functions as a passivation film that protects the light-emitting element 650. By providing the protective layer 631 that covers the light-emitting element, impurities such as water and oxygen can be prevented from entering the light-emitting element, and the reliability of the light-emitting element 650 can be improved.
  • the protective layer 631 is preferably a single-layer structure or a laminated structure that includes at least an inorganic insulating film.
  • the inorganic insulating film examples include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film.
  • a semiconductor material such as indium gallium oxide or indium gallium zinc oxide (IGZO) may be used as the protective layer 631.
  • the protective layer 631 can be formed by using an ALD method, a CVD method, a sputtering method, or the like. Note that, although a configuration including an inorganic insulating film has been exemplified as the protective layer 631, this is not limiting.
  • the protective layer 631 may be a laminated structure of an inorganic insulating film and an organic insulating film.
  • the protective layer 631 and the substrate 610 are bonded via an adhesive layer 607.
  • a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting element.
  • the space between the substrate 410 and the substrate 610 is filled with an adhesive layer 607, and a solid sealing structure is applied.
  • the space may be filled with an inert gas (such as nitrogen or argon) and a hollow sealing structure may be applied.
  • the adhesive layer 607 may be provided so as not to overlap with the light-emitting element.
  • the space may also be filled with a resin different from the adhesive layer 607 provided in a frame shape.
  • various types of curing adhesives can be used, such as ultraviolet-curing photocuring adhesives, reaction-curing adhesives, heat-curing adhesives, and anaerobic adhesives.
  • these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins.
  • epoxy resins with low moisture permeability are preferred.
  • Two-part mixed resins may also be used.
  • An adhesive sheet may also be used.
  • the display device 600A is a top emission type. Light emitted by the light emitting elements is emitted towards the substrate 610. For this reason, it is preferable to use a material that is highly transparent to visible light for the substrate 610. For example, a substrate that is highly transparent to visible light among the substrates that can be used for the substrate 410 can be selected for the substrate 610.
  • the pixel electrode contains a material that reflects visible light
  • the opposing electrode (common electrode 615) contains a material that transmits visible light.
  • the display device of one embodiment of the present invention may be a bottom emission type in which light emitted from a light-emitting element is emitted toward the substrate 410, rather than a top emission type.
  • a substrate that has high transparency to visible light is selected as the substrate 410.
  • FIG. 28 shows a cross-sectional view of the display device 600B.
  • the display device 600B can be a flexible display device (also called a flexible display) by using flexible substrates for the substrate 541 and the substrate 610.
  • the substrate 541 is attached to the insulating layer 545 by an adhesive layer 543.
  • the substrate 610 is attached to the protective layer 631 by an adhesive layer 607.
  • the element layer 660 of the display device 600B differs from the element layer 660 of the display device 600A mainly in that the same configuration is applied to the layers 613a, 613b, and 613c, and further in that the colored layers 628R, 628G, and 628B are provided.
  • Layer 613a, layer 613b, and layer 613c are formed in the same process and with the same material. Furthermore, layer 613a, layer 613b, and layer 613c are separated from each other.
  • leakage current sometimes called horizontal leakage current, horizontal leakage current, or lateral leakage current
  • the light-emitting elements 650R, 650G, and 650B shown in FIG. 28 emit white light.
  • the white light emitted by the light-emitting elements 650R, 650G, and 650B passes through the colored layers 628R, 628G, and 628B, thereby obtaining light of the desired color.
  • a light-emitting element configured to emit white light may emit light of a specific wavelength, such as red, green, or blue, with the light being enhanced.
  • the light emitted by the light-emitting element 650R is extracted as red light to the outside of the display device 600B via the colored layer 628R.
  • the light emitted by the light-emitting element 650G is extracted as green light to the outside of the display device 600B via the colored layer 628G.
  • the light emitted by the light-emitting element 650B is extracted as blue light to the outside of the display device 600B via the colored layer 628B.
  • the light emitting elements 650R, 650G, and 650B shown in FIG. 28 emit blue light.
  • the layers 613a, 613b, and 613c each have one or more light emitting layers that emit blue light.
  • the blue light emitted by the light emitting element 650B can be extracted.
  • a color conversion layer is provided between the light emitting element 650R and the coloring layer 628R and between the light emitting element 650G and the coloring layer 628G, so that the blue light emitted by the light emitting element 650R or the light emitting element 650G can be converted into light with a longer wavelength, and red or green light can be extracted.
  • the coloring layer absorbs light other than the desired color, and the color purity of the light that the subpixel emits can be increased.
  • the colored layers are colored layers that selectively transmit light in a specific wavelength range and absorb light in other wavelength ranges.
  • a red (R) color filter that transmits light in the red wavelength range
  • a green (G) color filter that transmits light in the green wavelength range
  • a blue (B) color filter that transmits light in the blue wavelength range
  • R red
  • G green
  • B blue
  • metal materials, resin materials, pigments, and dyes can be used.
  • the colored layers are formed at the desired positions by a printing method, an inkjet method, an etching method using photolithography, or the like.
  • the element layer 630 of the display device 600B has a similar configuration to the element layer 630 of the display device 600A, so a detailed description will be omitted.
  • Display device 600B differs from display device 600A in that it does not have element layer 620 but has element layer 635.
  • Element layer 635 has the same configuration as element layer 630.
  • At least a part of the transistors in the element layer 635 is electrically connected to the conductive layer or the transistors in the element layer 630 via plugs, wiring, etc. Note that a wiring layer 670 may be provided between the element layer 630 and the element layer 635.
  • the element layer 635 is provided with one or both of a pixel circuit and a driver circuit of a display device.
  • element layer 630 and element layer 635 an example in which two element layers having OS transistors are stacked (element layer 630 and element layer 635) is shown, but the number of stacked element layers is not limited to this, and may be three or more layers.
  • the bottom layer is used for the driver circuit (either or both of the gate driver and source driver) of the display device
  • the top layer is used for the pixel circuit of the display device
  • the layers located between are used for the pixel circuit or driver circuit, respectively.
  • Si transistors are typically formed on single crystal Si wafers, making it difficult to make them flexible.
  • a display device is constructed using only OS transistors without using Si transistors, a flexible configuration can be made using a relatively simple manufacturing process.
  • FIG. 29A shows a schematic top view of a portion of a display unit having multiple light-emitting elements.
  • the display unit has multiple light-emitting elements 61R that emit red light, multiple light-emitting elements 61G that emit green light, and multiple light-emitting elements 61B that emit blue light.
  • the symbols R, G, and B are given within the light-emitting region of each light-emitting element to easily distinguish between the light-emitting elements.
  • FIG. 29A illustrates a configuration having three light-emitting colors, red (R), green (G), and blue (B), but this is not limiting. For example, a configuration having four or more colors may be used.
  • FIG. 29B is a cross-sectional view taken along dashed line A1-A2 in FIG. 29A.
  • Light-emitting element 61R, light-emitting element 61G, and light-emitting element 61B shown in FIG. 29B are each provided on insulating layer 363, and have conductive layer 171 functioning as a pixel electrode and conductive layer 173 functioning as a common electrode.
  • conductive layer 171 functioning as a pixel electrode
  • conductive layer 173 functioning as a common electrode.
  • One or both of an inorganic insulating film and an organic insulating film can be used as insulating layer 363.
  • the light-emitting element 61R has an EL layer 172R between the conductive layer 171 functioning as a pixel electrode and the conductive layer 173 functioning as a common electrode.
  • the EL layer 172R has a light-emitting compound that emits light having a peak at least in the red wavelength range.
  • the EL layer 172G of the light-emitting element 61G has a light-emitting compound that emits light having a peak at least in the green wavelength range.
  • the EL layer 172B of the light-emitting element 61B has a light-emitting compound that emits light having a peak at least in the blue wavelength range.
  • the conductive layer 171 functioning as a pixel electrode is provided for each light-emitting element.
  • the conductive layer 173 functioning as a common electrode is provided as a continuous layer common to each light-emitting element.
  • a conductive film that is transparent to visible light is used for either the conductive layer 171 functioning as a pixel electrode or the conductive layer 173 functioning as a common electrode, and a conductive film that is reflective is used for the other.
  • the light-emitting element 61R is a top-emission type
  • the light 175R emitted from the light-emitting element 61R is emitted toward the conductive layer 173.
  • the light-emitting element 61R is a top-emission type
  • the light 175G emitted from the light-emitting element 61G is emitted toward the conductive layer 173.
  • the light-emitting element 61B is a top-emission type
  • the light 175B emitted from the light-emitting element 61B is emitted toward the conductive layer 173.
  • An insulating layer 272 is provided to cover the end of the conductive layer 171 that functions as a pixel electrode.
  • the end of the insulating layer 272 is preferably tapered.
  • an inorganic insulating film and an organic insulating film can be used.
  • the insulating layer 272 is provided to prevent adjacent light-emitting elements from unintentionally shorting electrically and causing erroneous light emission. In addition, when a metal mask is used to form the EL layer, the insulating layer 272 also functions to prevent the metal mask from coming into contact with the conductive layer 171.
  • EL layer 172R, EL layer 172G, and EL layer 172B each have a region in contact with the upper surface of conductive layer 171, which functions as a pixel electrode, and a region in contact with the surface of insulating layer 272.
  • the ends of EL layer 172R, EL layer 172G, and EL layer 172B are located on insulating layer 272.
  • a gap is provided between two EL layers between light-emitting elements that emit different light colors.
  • EL layer 172R, EL layer 172G, and EL layer 172B are provided so as not to be in contact with each other. This makes it possible to preferably prevent current from flowing through two adjacent EL layers and causing unintended light emission (also known as crosstalk). This makes it possible to increase contrast and realize a display device with high display quality.
  • EL layer 172R, EL layer 172G, and EL layer 172B can be separately produced by a vacuum deposition method using a shadow mask such as a metal mask. Alternatively, they may be separately produced by a photolithography method. By using the photolithography method, it is possible to produce a high-definition display device that is difficult to achieve when using a metal mask.
  • a protective layer 271 is provided on the conductive layer 173, which functions as a common electrode, to cover the light-emitting elements 61R, 61G, and 61B.
  • the protective layer 271 has a function of preventing impurities such as water from diffusing from above to each light-emitting element.
  • the material of the protective layer 631 described above can be referenced for the material of the protective layer 271.
  • Figure 29C shows a light-emitting element 61W that emits white light.
  • the light-emitting element 61W has an EL layer 172W that emits white light between a conductive layer 171 that functions as a pixel electrode and a conductive layer 173 that functions as a common electrode.
  • the EL layer 172W may be configured by stacking two or more light-emitting layers selected so that the combination of their respective light-emitting colors produces white light.
  • a tandem-type EL layer may also be used, in which a charge-generating layer is sandwiched between the light-emitting layers.
  • Figure 29C shows three light-emitting elements 61W lined up.
  • a colored layer 264R is provided on the top of the left light-emitting element 61W.
  • the colored layer 264R functions as a bandpass filter that transmits red light.
  • a colored layer 264G that transmits green light is provided on the top of the center light-emitting element 61W
  • a colored layer 264B that transmits blue light is provided on the top of the right light-emitting element 61W. This allows the display device to display color images.
  • the EL layer 172W is separated between two adjacent light-emitting elements 61W. This makes it possible to prevent unintended light emission in two adjacent light-emitting elements 61W due to current flowing through the EL layer 172W.
  • a stacked EL layer in which a charge generating layer is provided between two light-emitting layers is used as the EL layer 172W.
  • the higher the resolution i.e., the smaller the distance between adjacent pixels, the more pronounced the effect of crosstalk becomes, resulting in a decrease in contrast. Therefore, by using such a configuration, a display device that combines high resolution and high contrast can be realized.
  • the separation of the EL layer 172W is preferably performed by photolithography. This allows the spacing between the light-emitting elements to be narrowed, resulting in a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.
  • the semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, large-scale computers, space equipment, data centers (also referred to as Data Centers: DCs), and various electronic devices.
  • DCs Data Centers
  • the semiconductor device of one embodiment of the present invention it is possible to achieve low power consumption and high performance in electronic components, large-scale computers, space equipment, data centers, and various electronic devices.
  • a display device including a semiconductor device according to one embodiment of the present invention can be used as a display portion of various electronic devices.
  • a display device including a semiconductor device according to one embodiment of the present invention can easily achieve high definition and high resolution.
  • Electronic devices include, for example, electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of one embodiment of the present invention can be used favorably in electronic devices having a relatively small display area because it is possible to increase the resolution.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.
  • the display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • a resolution of 4K, 8K, or higher is preferable.
  • the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, 5000 ppi or more, or 7000 ppi or more.
  • the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.
  • the electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • FIG. 30A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 700 is mounted.
  • the electronic component 700 shown in FIG. 30A has a semiconductor device 710 in a mold 711. In FIG. 30A, some parts are omitted in order to show the inside of the electronic component 700.
  • the electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714.
  • the electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
  • the semiconductor device 710 has a drive circuit layer 715 and a memory layer 716.
  • the memory layer 716 is configured by stacking a plurality of memory cell arrays.
  • the stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) and bonding technology such as Cu-Cu direct bonding.
  • TSV Through Silicon Via
  • bonding technology such as Cu-Cu direct bonding.
  • connection wiring By configuring the memory on-chip, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).
  • the multiple memory cell arrays in the memory layer 716 are formed using OS transistors and the multiple memory cell arrays are monolithically stacked.
  • OS transistors By configuring the multiple memory cell arrays as a monolithic stack, it is possible to improve one or both of the memory bandwidth and the memory access latency.
  • the bandwidth is the amount of data transferred per unit time
  • the access latency is the time from access to the start of data exchange.
  • Si transistors when Si transistors are used for the memory layer 716, it is difficult to configure the memory layer 716 as a monolithic stack compared to OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in the monolithic stack configuration.
  • the semiconductor device 710 may be referred to as a die.
  • a die refers to a chip piece obtained during the manufacturing process of a semiconductor chip by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into cubes.
  • Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also called a silicon wafer
  • a silicon die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.
  • Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module).
  • Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.
  • Electronic component 730 shows an example in which semiconductor device 710 is used as a high bandwidth memory (HBM).
  • Semiconductor device 735 can be used in integrated circuits such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).
  • the package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.
  • the interposer 731 may be, for example, a silicon interposer or a resin interposer.
  • the interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732.
  • the interposer is sometimes called a "rewiring substrate” or "intermediate substrate.”
  • a through electrode is provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrode.
  • a TSV can also be used as the through electrode.
  • the interposer that implements the HBM requires fine, high-density wiring. For this reason, it is preferable to use a silicon interposer for the interposer that implements the HBM.
  • the reliability is less likely to decrease due to the difference in the expansion coefficient between the integrated circuit and the interposer.
  • the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is less likely to occur.
  • a composite structure may be used that combines a memory cell array stacked using TSVs and a monolithic stacking memory cell array.
  • a heat sink may be provided overlapping the electronic component 730.
  • electrodes 733 may be provided on the bottom of the package substrate 732.
  • FIG. 30B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved.
  • the electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.
  • the electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA.
  • mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).
  • Fig. 31A shows a perspective view of a large scale computer 5600.
  • the large scale computer 5600 shown in Fig. 31A has a rack 5610 housing a plurality of rack-mounted computers 5620.
  • the large scale computer 5600 may also be called a supercomputer.
  • Computer 5620 can have the configuration shown in the perspective view in FIG. 31B, for example.
  • computer 5620 has motherboard 5630, which has multiple slots 5631 and multiple connection terminals.
  • PC card 5621 is inserted into slot 5631.
  • PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to motherboard 5630.
  • the PC card 5621 shown in FIG. 31C is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like.
  • the PC card 5621 has a board 5622.
  • the board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • FIG. 31C illustrates semiconductor devices other than the semiconductor devices 5626, 5627, and 5628, but for those semiconductor devices, the following description of the semiconductor devices 5626, 5627, and 5628 can be referred to.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • An example of the standard for the connection terminal 5629 is PCIe.
  • Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
  • the semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • the electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • An example of the semiconductor device 5628 is a memory device.
  • the electronic component 700 can be used as the semiconductor device 5628.
  • the mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment.
  • a semiconductor device includes an OS transistor.
  • the OS transistor has small changes in electrical characteristics due to radiation exposure. In other words, it has high resistance to radiation and can be suitably used in an environment where radiation may be incident.
  • the OS transistor can be suitably used in outer space.
  • the OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays.
  • outer space refers to an altitude of 100 km or higher, for example, and the outer space described in this specification can include one or more of the thermosphere, mesosphere, and stratosphere.
  • FIG. 31D shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that FIG. 31D also shows a planet 6804 in space.
  • the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit.
  • BMS battery management system
  • the use of OS transistors in the battery management system or battery control circuit described above is preferable because it consumes low power and has high reliability even in space.
  • Outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • the power required for the operation of the satellite 6800 is generated.
  • the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated.
  • the solar panel may be called a solar cell module.
  • Satellite 6800 can generate a signal.
  • the signal is transmitted via antenna 6803, and can be received, for example, by a receiver installed on the ground or by another satellite.
  • the position of the receiver that received the signal can be measured.
  • satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device.
  • a semiconductor device including an OS transistor which is one embodiment of the present invention, is preferably used for the control device 6807.
  • an OS transistor Compared to a Si transistor, an OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure. In other words, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can be configured to have a sensor. For example, by configuring it to have a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected off an object located on the ground. Or, by configuring it to have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is given as an example of space equipment, but the present invention is not limited to this.
  • a semiconductor device according to one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.
  • the semiconductor device can be suitably used in a storage system applied to a data center or the like.
  • the data center is required to perform long-term management of data, such as ensuring the immutability of the data.
  • it is necessary to increase the size of the building, for example, by installing storage and servers for storing a huge amount of data, securing a stable power source for holding the data, or securing cooling equipment required for holding the data.
  • a semiconductor device By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores the data. This makes it possible to miniaturize the storage system, miniaturize the power source for storing data, and reduce the scale of cooling equipment. This makes it possible to save space in the data center.
  • the semiconductor device of one embodiment of the present invention has low power consumption, and therefore can reduce heat generation from the circuit. This can reduce adverse effects of the heat on the circuit itself, peripheral circuits, and modules. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. This can improve the reliability of the data center.
  • FIG. 31E shows a storage system applicable to a data center.
  • the storage system 7010 shown in FIG. 31E has multiple servers 7001sb as hosts 7001 (illustrated as Host computer). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage).
  • the host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).
  • SAN Storage Area Network
  • the host 7001 corresponds to a computer that accesses data stored in the storage 7003.
  • the hosts 7001 may be connected to each other via a network.
  • Storage 7003 uses flash memory to reduce data access speed, i.e. the time required to store and output data, but this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage.
  • cache memory is usually provided within the storage to reduce the time required to store and output data.
  • the above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.
  • OS transistors as transistors for storing data in the cache memory, which hold a potential according to the data, the frequency of refreshing can be reduced and power consumption can be reduced.
  • the memory cell array miniaturization is possible.
  • FIG. 32A to 32F An example of a wearable device that can be worn on the head will be described with reference to Figures 32A to 32F.
  • These wearable devices have at least one of a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content.
  • the electronic device 700A shown in FIG. 32A has a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.
  • the display device according to one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can display images with extremely high resolution.
  • the semiconductor device according to one embodiment of the present invention can be applied to the control unit (not shown). This can reduce the power consumption of the electronic device.
  • Electronic device 700A can project an image displayed on display panel 751 onto display area 756 of optical member 753. Because optical member 753 is translucent, the user can see the image displayed in the display area superimposed on the transmitted image visible through optical member 753. Therefore, electronic device 700A is an electronic device capable of AR display.
  • the electronic device 700A may be provided with a camera capable of capturing an image in front of it as an imaging unit.
  • the electronic device 700A may be provided with an acceleration sensor such as a gyro sensor, so that the electronic device 700A can detect the orientation of the user's head and display an image corresponding to that orientation in the display area 756.
  • the communication unit has a wireless communication device, and can supply video signals and the like via the wireless communication device.
  • a connector can be provided to which a cable through which a video signal and power supply potential can be connected.
  • the electronic device 700A is equipped with a battery and can be charged wirelessly, wired, or both.
  • the housing 721 may be provided with a touch sensor module.
  • the touch sensor module has a function of detecting that the outer surface of the housing 721 is touched.
  • the touch sensor module can detect a tap operation or a slide operation by the user and execute various processes. For example, a tap operation can execute processes such as pausing or resuming a video, and a slide operation can execute processes such as fast-forwarding or rewinding. Furthermore, by providing a touch sensor module on each of the two housings 721, the range of operations can be expanded.
  • Electronic device 800A shown in FIG. 32B and electronic device 800B shown in FIG. 32C each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832. Note that display unit 820 and communication unit 822 are omitted in FIG. 32C.
  • a display device can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high resolution can be provided. This allows the user to feel a high sense of immersion.
  • a semiconductor device can be applied to the control portion 824. This allows the power consumption of the electronic device to be reduced.
  • the display unit 820 is provided inside the housing 821 at a position that can be seen through the lens 832. In addition, by displaying different images on the pair of display units 820, it is also possible to perform a three-dimensional display using parallax.
  • the electronic device 800A and the electronic device 800B can each be considered electronic devices for VR.
  • a user wearing the electronic device 800A or the electronic device 800B can view the image displayed on the display unit 820 through the lens 832.
  • Electric device 800A and electronic device 800B each preferably have a mechanism that can adjust the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that they have a mechanism that can adjust the focus by changing the distance between lens 832 and display unit 820.
  • the attachment unit 823 allows the user to attach the electronic device 800A or electronic device 800B to the head. Note that in FIG. 32B and other figures, the attachment unit 823 is shaped like the temples of glasses, but is not limited to this. The attachment unit 823 only needs to be wearable by the user, and may be shaped like a helmet or band, for example.
  • the imaging unit 825 has a function of acquiring external information.
  • the data acquired by the imaging unit 825 can be output to the display unit 820.
  • An image sensor can be used for the imaging unit 825.
  • multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.
  • a distance measuring sensor capable of measuring the distance to an object
  • the imaging unit 825 is one aspect of the detection unit.
  • the detection unit for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection and Ranging) can be used.
  • LIDAR Light Detection and Ranging
  • the electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone.
  • a vibration mechanism that functions as a bone conduction earphone.
  • a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This makes it possible to enjoy video and audio by simply wearing the electronic device 800A without the need for separate audio equipment such as headphones, earphones, or speakers.
  • Each of the electronic devices 800A and 800B may have an input terminal.
  • the input terminal can be connected to a cable that supplies a video signal from a video output device or the like, and power for charging a battery provided within the electronic device.
  • the electronic device of one embodiment of the present invention may have a function of wireless communication with the earphone 750.
  • the earphone 750 has a communication unit (not shown) and has a wireless communication function.
  • the earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function.
  • the electronic device 700A shown in FIG. 32A has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device may have an earphone unit.
  • the electronic device 800B shown in FIG. 32C has an earphone unit 827.
  • the earphone unit 827 and the control unit 824 may be configured to be connected to each other by wire.
  • a part of the wiring connecting the earphone unit 827 and the control unit 824 may be disposed inside the housing 821 or the mounting unit 823.
  • the earphone unit 827 and the mounting unit 823 may also have a magnet. This allows the earphone unit 827 to be fixed to the mounting unit 823 by magnetic force, which is preferable as it makes storage easier.
  • the electronic device may have an audio output terminal to which earphones or headphones can be connected.
  • the electronic device may also have one or both of an audio input terminal and an audio input mechanism.
  • a sound collection device such as a microphone can be used as the audio input mechanism.
  • the electronic device may be endowed with the functionality of a so-called headset.
  • FIGS. 32D and 32E show perspective views of goggle-type electronic device 850A for VR.
  • FIG. 32D and FIG. 32E show an example in which a pair of curved display devices 840 (display device 840_R and display device 840_L) are included in housing 845.
  • Electronic device 850A also includes a motion detection unit 841, a gaze detection unit 842, a calculation unit 843, a communication unit 844, a lens 848, an operation button 851, a mounting device 854, a sensor 855, a dial 856, etc.
  • the user can see one display device per eye. This makes it possible to display high-resolution images even when performing 3D display using parallax.
  • the display device 840 is curved in an arc shape roughly centered on the user's eye. This makes it possible for the user to see more natural images because the distance from the user's eye to the display surface of the display device 840 is constant.
  • the user's eyes can be configured to be positioned in the normal direction to the display surface of the display device 840, so that the effect can be essentially ignored, especially in the horizontal direction, making it possible to display more realistic images.
  • lens 848 is positioned between display device 840 and the user's eyes.
  • FIG. 32E shows an example having dial 856 that changes the position of the lens to adjust the diopter. Note that if electronic device 850A has an autofocus function, it does not need to have dial 856 for adjusting the diopter.
  • FIG. 32F shows a goggle-type electronic device 850B that has one display device 840. This configuration makes it possible to reduce the number of parts.
  • the display device 840 can display two images, one for the right eye and one for the left eye, side by side in two left and right areas. This makes it possible to display a stereoscopic image using binocular parallax. Note that the display device 840 may display two different images side by side using parallax, or may display two identical images side by side without using parallax.
  • a single image visible to both eyes may be displayed across the entire area of the display device 840. This allows a panoramic image to be displayed across both ends of the field of view, enhancing realism.
  • the display device according to one embodiment of the present invention can be applied to the display device 840.
  • the display device according to one embodiment of the present invention has extremely high definition, so that even if the image is enlarged using the lens 848, the pixels are not visible to the user, and a more realistic image can be displayed.
  • the electronic device 6500 shown in FIG. 33A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509.
  • the electronic device 6520 shown in FIG. 33B is a portable information terminal that can be used as a tablet terminal.
  • the electronic device 6520 includes a housing 6501, a display unit 6502, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a control device 6509, and a connection terminal 6519.
  • the display portion 6502 has a touch panel function.
  • the control device 6509 has, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be used for one or both of the display portion 6502 and the control device 6509.
  • FIG. 33C is a schematic cross-sectional view including the end of the housing 6501 of the electronic device 6500 or electronic device 6520 on the microphone 6506 side.
  • a translucent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.
  • the display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).
  • a part of the display panel 6511 is folded back in the area outside the display unit 6502, and the FPC 6515 is connected to the folded back part.
  • An IC 6516 is mounted on the FPC 6515.
  • the FPC 6515 is connected to a terminal provided on a printed circuit board 6517.
  • the flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized.
  • the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small.
  • a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.
  • Figure 33D shows an example of a television device.
  • a display unit 7000 is built into a housing 7101.
  • the housing 7101 is supported by a stand 7103.
  • a display device can be applied to the display portion 7000.
  • the television device 7100 shown in FIG. 33D can be operated using operation switches provided on the housing 7101 and a separate remote control 7111.
  • the display unit 7000 may be provided with a touch sensor, and the television device 7100 may be operated by touching the display unit 7000 with a finger or the like.
  • the remote control 7111 may have a display unit that displays information output from the remote control 7111.
  • the channel and volume can be operated using operation keys or a touch panel provided on the remote control 7111, and the image displayed on the display unit 7000 can be operated.
  • the television device 7100 is configured to include a receiver and a modem.
  • the receiver can receive general television broadcasts.
  • by connecting to a wired or wireless communication network via the modem it is also possible to carry out one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.
  • FIG. 33E shows an example of a notebook computer.
  • the notebook computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and a control device 7215.
  • a display portion 7000 is incorporated in the housing 7211.
  • the control device 7215 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be used for one or both of the display portion 7000 and the control device 7215.
  • the digital signage 7300 shown in FIG. 33F has a housing 7301, a display unit 7000, and a speaker 7303. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.
  • Figure 33G shows digital signage 7400 attached to a cylindrical pole 7401.
  • Digital signage 7400 has a display unit 7000 that is provided along the curved surface of pole 7401.
  • a display device according to one embodiment of the present invention can be applied to the display portion 7000.
  • the larger the display unit 7000 the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of an advertisement, for example.
  • a touch panel By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • the semiconductor device and display device of one embodiment of the present invention can be applied to the area around the driver's seat of an automobile, which is a moving object.
  • FIG. 34A is a diagram showing the area around the windshield inside the interior of a vehicle.
  • FIG. 34A shows display panel 9001a, display panel 9001b, and display panel 9001c attached to the dashboard, and display panel 9001d attached to a pillar.
  • the display panels 9001a to 9001c can provide various information by displaying navigation information, speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc.
  • the display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, improving the design.
  • the display panels 9001a to 9001c can also be used as lighting devices.
  • the display panel 9001d can display images from an imaging means installed on the vehicle body to complement the field of view (blind spots) blocked by pillars. In other words, by displaying images from an imaging means installed on the outside of the vehicle, blind spots can be complemented and safety can be increased. Furthermore, by displaying images that complement the invisible parts, safety checks can be performed more naturally and without any sense of discomfort.
  • the display panel 9001d can also be used as a lighting device.
  • FIG. 34B is a perspective view showing a wristwatch-type mobile information terminal 9200.
  • the mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark).
  • the display surface of the display unit 9001 is curved, and display can be performed along the curved display surface.
  • the mobile information terminal 9200 can also make hands-free calls by communicating with, for example, a headset capable of wireless communication.
  • the mobile information terminal 9200 can also transmit data to and from other information terminals and charge itself via a connection terminal 9006. Charging may be performed by wireless power supply.
  • the mobile information terminal 9200 shown in FIG. 34B has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light), a microphone 9008, etc.
  • FIG 34C is a perspective view of a foldable mobile information terminal 9201.
  • the mobile information terminal 9201 has a housing 9000a, a housing 9000b, a display portion 9001, and an operation button 9056.
  • the housings 9000a and 9000b are connected by a hinge 9055, which allows the device to be folded in half.
  • the display unit 9001 of the mobile information terminal 9201 is supported by two housings (housing 9000a and housing 9000b) connected by a hinge 9055.
  • Figures 34D to 34F are perspective views showing a foldable mobile information terminal 9202. Also, Figure 34D is a perspective view of the mobile information terminal 9202 in an unfolded state, Figure 34F is a folded state, and Figure 34E is a perspective view of a state in the process of changing from one of Figures 34D and 34F to the other. In this way, the mobile information terminal 9202 can be folded into three.
  • the display unit 9001 of the mobile information terminal 9202 is supported by three housings 9000 connected by hinges 9055.
  • the display device of one embodiment of the present invention can be applied to the display portion 9001.
  • the display portion 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.
  • the portable information terminal 9201 and the portable information terminal 9202 each have excellent portability when folded, and excellent display visibility when unfolded due to their seamless, large display areas.
  • the semiconductor device of one embodiment of the present invention can be reduced by applying the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO 2 ). In addition, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming because of its low power consumption.
  • CO 2 greenhouse gases
  • FIG 35A shows a cross-sectional view of a semiconductor device assumed in the calculations of this example.
  • Transistor A of the semiconductor device shown in Figure 35A is similar to transistor 200A described in embodiment 1, except that the number of stacked layers of some layers is different.
  • device simulation was also performed on the configuration of the semiconductor device shown in Figure 35B.
  • Transistor B of the semiconductor device shown in Figure 35B differs from transistor A mainly in that a conductive layer 260 functioning as a gate electrode is provided in an opening 290.
  • a conductive layer 240 is provided on an insulating layer 280, and an opening 290 reaching the conductive layer 220 is provided in the insulating layer 280 and the conductive layer 240.
  • the materials of each layer assumed in the device simulation are explained below.
  • the conductive layer 220 is assumed to be an ITSO film
  • the insulating layer 280 is assumed to be a silicon nitride film
  • the insulating layer 281 is assumed to be a silicon nitride film
  • the insulating layer 250 is assumed to be a four-layer structure in which a silicon nitride film (insulating layer 250a), a hafnium oxide film (insulating layer 250b), a silicon oxide film (insulating layer 250c) and an aluminum oxide film (insulating layer 250d) are stacked in this order
  • the conductive layer 240 is assumed to be an ITSO film.
  • the conductive layer 260 was set to a work function value without assuming a specific material.
  • Table 1 shows a list of parameters used in the device simulation of this embodiment.
  • the transistor channel length was assumed to be 60 nm, and the channel width was assumed to be 30 ⁇ nm (approximately 94 nm).
  • the insulating layer 280 was assumed to have a three-layer structure in which a 10 nm-thick silicon nitride film (insulating layer 280a), a 60 nm-thick silicon oxide film (insulating layer 280b), and a 10 nm-thick silicon nitride film (insulating layer 280c) were stacked in this order.
  • the horizontal axis shows the gate voltage (Vg)
  • the left vertical axis shows the drain current (Id)
  • the right vertical axis shows the field effect mobility ( ⁇ FE) at a drain voltage (Vd) of 1.2 V.
  • FIG. 37A shows the correlation between the shift voltage (Vsh) calculated from each Id-Vg characteristic and the subthreshold swing value (S value, S.S.).
  • FIG. 37B shows the correlation between the field effect mobility ( ⁇ FE) calculated from each Id-Vg characteristic and DIBL (Drain-Induced Barrier Lowering).
  • the shift voltage (Vsh) is the gate voltage (Vg) when the drain current (Id) obtained by interpolation becomes 1 pA (1 ⁇ 10 ⁇ 12 A) or less.
  • the S value refers to the change in the gate voltage (Vg) in the subthreshold region that changes the drain current (Id) by one order of magnitude at a constant drain voltage (Vd).
  • the DIBL is the amount of change in the shift voltage (Vsh) when the drain voltage (Vd) is changed by 1 V, and is one of the indicators of the short channel effect.
  • transistor A As shown in Figures 36, 37A, and 37B, compared to transistor B, transistor A, which is one embodiment of the present invention, was found to have a smaller S value and a shift voltage closer to 0 V. It was also found to have a higher field effect mobility and suppressed the short channel effect.
  • the electron density distribution of the oxide semiconductor layer 230 was calculated.
  • the electron concentration distribution of the oxide semiconductor layer 230 is shown in FIG. 38.
  • the electron density distribution of transistor A is shown on the left, and that of transistor B is shown on the right.
  • the upper side shows the electron density distribution when the gate voltage (Vgs) is the shift voltage (Vsh), and the lower side shows the electron density distribution when the gate voltage (Vgs) is +4.0 V.
  • the upper side shows the electron density distribution in the subthreshold region of the transistor, and the lower side shows the electron density distribution in the on region.
  • the electron density in the subthreshold region is low on the conductive layer 260 side of the oxide semiconductor layer 230, and high on the opposite side of the conductive layer 260 (here, the center side of the opening 290). That is, it was found that in the transistor A, a current starts to flow in the region on the center side of the opening 290 away from the conductive layer 260.
  • the perimeter of the side of the oxide semiconductor layer 230 on the opposite side of the conductive layer 260 (here, the center side of the opening 290) is shorter than the perimeter of the side of the oxide semiconductor layer 230 on the conductive layer 260 side.
  • the electric field strength when a voltage is applied to the gate increases as it approaches the center side of the opening 290 from the conductive layer 260 side. Therefore, it is considered that the S value decreases because the electric field strength of the gate in the region where the current starts to flow increases in the subthreshold region.
  • transistor A the electron density in the on region was high on the conductive layer 260 side of the oxide semiconductor layer 230 and low on the opposite side of the conductive layer 260 (here, the center side of the opening 290). In other words, it was confirmed that in transistor A, the current path in the on region is on the conductive layer 260 side.
  • ADDR signal, BIL: wiring, BILB: wiring, BRL: wiring, BW: signal, CA: capacitive element, CAL: wiring, CB: capacitive element, CC: capacitive element, CE: signal, CLK: signal, GNDL: wiring, GW: signal, IS21: insulating layer, IS22: insulating layer, M10: transistor, MPG: conductive layer, MTCK: transistor, RBL: wiring, RDA: signal, RWL: wiring, SL: wiring, VDL: wiring, WAKE: signal, WBL: wiring, WDA: signal, WOL: wiring, 61B: light-emitting element, 61G: light-emitting element , 61R: light-emitting element, 61W: light-emitting element, 100a: capacitive element, 100b: capacitive element, 100: capacitive element, 110: conductive layer, 115: conductive layer, 120: conductive layer, 130B: subpixel, 130G: subpixel, 130R:

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
PCT/IB2024/052821 2023-03-31 2024-03-25 半導体装置、及び半導体装置の作製方法 Ceased WO2024201264A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2025509043A JPWO2024201264A1 (https=) 2023-03-31 2024-03-25
CN202480018717.0A CN120958963A (zh) 2023-03-31 2024-03-25 半导体装置及半导体装置的制造方法
KR1020257032266A KR20250165603A (ko) 2023-03-31 2024-03-25 반도체 장치 및 반도체 장치의 제작 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2023-058108 2023-03-31
JP2023058108 2023-03-31

Publications (1)

Publication Number Publication Date
WO2024201264A1 true WO2024201264A1 (ja) 2024-10-03

Family

ID=92903902

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2024/052821 Ceased WO2024201264A1 (ja) 2023-03-31 2024-03-25 半導体装置、及び半導体装置の作製方法

Country Status (4)

Country Link
JP (1) JPWO2024201264A1 (https=)
KR (1) KR20250165603A (https=)
CN (1) CN120958963A (https=)
WO (1) WO2024201264A1 (https=)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014179596A (ja) * 2013-02-12 2014-09-25 Semiconductor Energy Lab Co Ltd 半導体装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2020150233A (ja) * 2019-03-15 2020-09-17 キオクシア株式会社 半導体記憶装置
JP2022049605A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 半導体装置及び半導体記憶装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101870119B1 (ko) 2009-12-25 2018-06-25 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
CN107947763B (zh) 2010-08-06 2021-12-28 株式会社半导体能源研究所 半导体集成电路
US9312257B2 (en) 2012-02-29 2016-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN114424339A (zh) 2019-09-20 2022-04-29 株式会社半导体能源研究所 半导体装置及半导体装置的制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014179596A (ja) * 2013-02-12 2014-09-25 Semiconductor Energy Lab Co Ltd 半導体装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2020150233A (ja) * 2019-03-15 2020-09-17 キオクシア株式会社 半導体記憶装置
JP2022049605A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 半導体装置及び半導体記憶装置

Also Published As

Publication number Publication date
CN120958963A (zh) 2025-11-14
JPWO2024201264A1 (https=) 2024-10-03
KR20250165603A (ko) 2025-11-26

Similar Documents

Publication Publication Date Title
US20240379869A1 (en) Semiconductor Device
US20240395940A1 (en) Semiconductor device, memory device, and method for manufacturing semiconductor device
WO2024201259A1 (ja) 半導体装置、及び、半導体装置の作製方法
WO2024241187A1 (ja) 半導体装置
JP2025010084A (ja) 酸化物半導体層、酸化物半導体層の作製方法、半導体装置、及び半導体装置の作製方法
WO2024201264A1 (ja) 半導体装置、及び半導体装置の作製方法
WO2024201267A1 (ja) 半導体装置、及び、半導体装置の作製方法
WO2024194729A1 (ja) 半導体装置、及び、半導体装置の作製方法
WO2024201207A1 (ja) 半導体装置、及び、半導体装置の作製方法
WO2024231787A1 (ja) 半導体装置、及び、半導体装置の作製方法
WO2024236396A1 (ja) 半導体装置、記憶装置、半導体装置の作製方法
WO2024241136A1 (ja) 半導体装置
WO2024224246A1 (ja) 半導体装置、及び、半導体装置の作製方法
JP2025010064A (ja) 半導体装置
WO2025114840A1 (ja) 半導体装置、及び半導体装置の作製方法
WO2025141446A1 (ja) 半導体装置、及び半導体装置の作製方法
WO2025177132A1 (ja) 半導体装置、及び半導体装置の作製方法
WO2025062253A1 (ja) 半導体装置
WO2025224595A1 (ja) 半導体装置及び半導体装置の作製方法
CN118943200A (zh) 半导体装置
WO2025017438A1 (ja) 半導体装置、及び半導体装置の作製方法
WO2025017441A1 (ja) 製造装置、及び、半導体装置の作製方法
WO2025022270A1 (ja) 半導体装置
WO2025022294A1 (ja) 酸化物半導体層、酸化物半導体層の作製方法、半導体装置、及び半導体装置の作製方法
WO2024252248A1 (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 24778396

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2025509043

Country of ref document: JP

ENP Entry into the national phase

Ref document number: 1020257032266

Country of ref document: KR

Free format text: ST27 STATUS EVENT CODE: A-0-1-A10-A15-NAP-PA0105 (AS PROVIDED BY THE NATIONAL OFFICE)

WWE Wipo information: entry into national phase

Ref document number: KR1020257032266

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 24778396

Country of ref document: EP

Kind code of ref document: A1