WO2024201207A1 - 半導体装置、及び、半導体装置の作製方法 - Google Patents

半導体装置、及び、半導体装置の作製方法 Download PDF

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Publication number
WO2024201207A1
WO2024201207A1 PCT/IB2024/052585 IB2024052585W WO2024201207A1 WO 2024201207 A1 WO2024201207 A1 WO 2024201207A1 IB 2024052585 W IB2024052585 W IB 2024052585W WO 2024201207 A1 WO2024201207 A1 WO 2024201207A1
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Prior art keywords
layer
conductive layer
insulating layer
oxide
opening
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
宮入秀和
村川努
山田淳
國武寛司
太田将志
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to KR1020257031640A priority Critical patent/KR20250162799A/ko
Priority to CN202480019053.XA priority patent/CN120958970A/zh
Priority to JP2025509037A priority patent/JPWO2024201207A1/ja
Publication of WO2024201207A1 publication Critical patent/WO2024201207A1/ja
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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
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    • H10B—ELECTRONIC MEMORY DEVICES
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
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    • H10B—ELECTRONIC MEMORY DEVICES
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections

Definitions

  • One aspect of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.
  • a CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) that are chipped by processing a semiconductor wafer and have electrodes that serve as connection terminals.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.
  • transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices.
  • ICs integrated circuits
  • Silicon-based semiconductor materials are widely known as semiconductor materials that can be used for transistors, but oxide semiconductors are also attracting attention as other materials.
  • Patent Document 1 discloses a low-power consumption CPU that utilizes the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by utilizing the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in a superimposed manner.
  • Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.
  • An object of one embodiment of the present invention is to provide a transistor with small parasitic capacitance. Alternatively, an object of one embodiment of the present invention is to provide a transistor with good electrical characteristics. Alternatively, an object of one embodiment of the present invention is to provide a transistor with high on-state current. Alternatively, an object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated. Alternatively, an object of one embodiment of the present invention is to provide a display device with high definition or a high aperture ratio. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, display device, or storage device.
  • an object of one embodiment of the present invention is to provide a semiconductor device, display device, or storage device with low power consumption.
  • an object of one embodiment of the present invention is to provide a storage device with high operation speed.
  • an object of one embodiment of the present invention is to provide a method for manufacturing the transistor, semiconductor device, display device, or storage device.
  • One aspect of the present invention has a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, an oxide semiconductor layer, a first insulating layer, a second insulating layer, and a third insulating layer, the first insulating layer being located on the first conductive layer, the second conductive layer being located on the first insulating layer, the first insulating layer and the second conductive layer having a first opening reaching the first conductive layer, the oxide semiconductor layer contacting at least the top surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer within the first opening, the second insulating layer being located on the oxide semiconductor layer within the first opening, and the third insulating layer.
  • the conductive layer overlaps with the oxide semiconductor layer through the second insulating layer in the first opening, and in a cross-sectional view, the maximum width of the third conductive layer is equal to or less than the minimum width of the first opening in the second conductive layer.
  • the third insulating layer is located on the second conductive layer through the second insulating layer, and has a second opening that reaches the third conductive layer at a position overlapping with the first opening. In a cross-sectional view, the maximum width of the second opening is equal to or less than the minimum width of the first opening in the second conductive layer.
  • the fourth conductive layer contacts the upper surface of the third conductive layer in the second opening.
  • one aspect of the present invention has a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, an oxide semiconductor layer, a first insulating layer, a second insulating layer, and a third insulating layer
  • the first insulating layer is located on the first conductive layer
  • the second conductive layer is located on the first insulating layer
  • the first insulating layer and the second conductive layer have a first opening reaching the first conductive layer
  • the oxide semiconductor layer contacts at least an upper surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer within the first opening
  • the second insulating layer contacts the oxide semiconductor within the first opening.
  • the semiconductor device of each of the above configurations preferably has a fifth conductive layer, which is located on the third insulating layer and in contact with the upper surface of the fourth conductive layer.
  • the fourth conductive layer has both a portion located within the second opening and a portion in contact with the upper surface of the third insulating layer.
  • the maximum width of the third conductive layer is smaller than the maximum width of the second opening.
  • the maximum width of the second opening is smaller than the maximum width of the third conductive layer.
  • one embodiment of the present invention includes forming a first conductive layer, forming a first insulating film on the first conductive layer, forming a second conductive layer on the first insulating film having a first opening in a region overlapping with the first conductive layer, processing the first insulating film to form a first insulating layer having a second opening reaching the first conductive layer, forming an oxide semiconductor layer in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and side surface of the second conductive layer, forming a second insulating layer on the oxide semiconductor layer, forming a first conductive film on the second insulating layer, and processing the first conductive film using anisotropic etching to form a second insulating layer of the first conductive film.
  • a method for manufacturing a semiconductor device in which a portion overlapping the upper surface of the conductive layer is removed, a third conductive layer is formed in which both ends of the upper surface are located within the first opening or the second opening in a cross-sectional view, a portion of the upper surface of the first insulating layer is exposed by processing the second insulating layer, the oxide semiconductor layer, and the second conductive layer, a second insulating film is formed on the first insulating layer, the second insulating layer, and the third conductive layer, and the second insulating film is processed to form a third insulating layer having a third opening that reaches the third conductive layer, and the maximum width of the third opening in a cross-sectional view is equal to or less than the minimum width of the first opening in the second conductive layer.
  • one embodiment of the present invention includes forming a first conductive layer, forming a first insulating film on the first conductive layer, forming a second conductive layer on the first insulating film having a first opening in a region overlapping with the first conductive layer, processing the first insulating film to form a first insulating layer having a second opening reaching the first conductive layer, forming an oxide semiconductor layer in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer, forming a second insulating layer on the oxide semiconductor layer, forming a first conductive film on the second insulating layer, and processing the first conductive film using a chemical mechanical polishing method to form a second conductive layer of the first conductive film.
  • a method for manufacturing a semiconductor device comprising: removing a portion overlapping with the top surface of the first conductive layer; forming a third conductive layer whose maximum width in a cross-sectional view is equal to or less than the minimum width of the first opening in the second conductive layer; processing the second insulating layer, the oxide semiconductor layer, and the second conductive layer to expose a portion of the top surface of the first insulating layer; forming a second insulating film on the first insulating layer, the second insulating layer, and the third conductive layer; and processing the second insulating film to form a third insulating layer having a third opening that reaches the third conductive layer; and a maximum width of the third opening in a cross-sectional view is equal to or less than the minimum width of the first opening in the second conductive layer.
  • a transistor with small parasitic capacitance can be provided.
  • a transistor with good electrical characteristics can be provided.
  • a transistor with high on-state current can be provided.
  • a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated can be provided.
  • a display device with high definition or a high aperture ratio can be provided.
  • a highly reliable transistor, a semiconductor device, a display device, or a memory device can be provided.
  • a semiconductor device, a display device, or a memory device with low power consumption can be provided.
  • a memory device with high operation speed can be provided.
  • a method for manufacturing the above-mentioned transistor, semiconductor device, display device, or memory device can be provided.
  • Fig. 1A is a plan view showing an example of a semiconductor device
  • Figs. 1B to 1D are cross-sectional views showing an example of the semiconductor device.
  • 2A and 2B are cross-sectional views showing an example of a semiconductor device.
  • Fig. 3A is a plan view showing an example of a semiconductor device
  • Figs. 3B to 3D are cross-sectional views showing an example of the semiconductor device.
  • Fig. 4A is a plan view showing an example of a semiconductor device
  • Figs. 4B to 4D are cross-sectional views showing an example of the semiconductor device.
  • 5A to 5F are cross-sectional views showing an example of a semiconductor device.
  • 6A to 6F are cross-sectional views showing an example of a semiconductor device.
  • FIG. 7A to 7F are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 8A1, 8A2, 8B, 8C, 8D1, and 8D2 are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 9A to 9F are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • Fig. 10A is a plan view of an example of a storage device
  • Figs. 10B and 10C are cross-sectional views of the example of the storage device.
  • 11A is a plan view of an example of a storage device
  • FIG. 11B is a cross-sectional view of the example of the storage device.
  • FIG. 12 is a cross-sectional view showing an example of a storage device.
  • FIG. 13 is a cross-sectional view showing an example of a storage device.
  • FIG. 14 is a block diagram illustrating a configuration example of a semiconductor device.
  • 15A to 15H are diagrams for explaining examples of the circuit configuration of a memory cell.
  • 16A and 16B are perspective views illustrating a configuration example of a semiconductor device.
  • FIG. 17 is a block diagram illustrating the CPU.
  • 18A and 18B are perspective views of a semiconductor device.
  • 19A and 19B are perspective views of a semiconductor device.
  • 20A and 20B are diagrams showing various storage devices by hierarchical level.
  • 21A and 21B are perspective views showing an example of a display device.
  • FIG. 22 is a cross-sectional view showing an example of a display device.
  • FIG. 22 is a cross-sectional view showing an example of a display device.
  • FIG. 23 is a cross-sectional view showing an example of a display device.
  • 24A to 24C are diagrams showing configuration examples of a display device.
  • 25A and 25B are diagrams illustrating an example of an electronic component.
  • Fig. 26A to Fig. 26C are diagrams showing an example of a mainframe computer
  • Fig. 26D is a diagram showing an example of space equipment
  • Fig. 26E is a diagram showing an example of a storage system applicable to a data center.
  • 27A to 27F are diagrams showing an example of an electronic device.
  • 28A to 28G are diagrams showing an example of an electronic device.
  • 29A to 29F are diagrams showing an example of an electronic device.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking).
  • an ordinal number attached to a component in one part of this specification may not match an ordinal number attached to the same component in another part of this specification or in the claims.
  • a transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and switching to control conduction or non-conduction.
  • transistor includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).
  • a transistor using an oxide semiconductor or a metal oxide in a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide in a channel formation region may be referred to as an OS transistor.
  • a transistor having silicon in a channel formation region may be referred to as a Si transistor.
  • a transistor is an element having at least three terminals including a gate, a drain, and a source.
  • a transistor has a region (also called a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and drain through the channel formation region.
  • a channel formation region refers to a region through which a current mainly flows.
  • source and drain may be interchanged when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms “source” and “drain” can be used interchangeably.
  • the impurity of a semiconductor refers to, for example, anything other than the main component constituting the semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be said to be an impurity.
  • the defect level density of the semiconductor may increase or the crystallinity may decrease.
  • the semiconductor is an oxide semiconductor
  • examples of the impurity that changes the characteristics of the semiconductor include, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and a transition metal other than the main component of the oxide semiconductor.
  • Specific examples of the impurity include, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • water may also function as an impurity.
  • oxygen vacancies also referred to as V O
  • V O oxygen vacancies
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen.
  • An oxynitride refers to a material whose composition contains more nitrogen than oxygen.
  • SIMS secondary ion mass spectrometry
  • XPS X-ray photoelectron spectroscopy
  • SIMS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more).
  • SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less).
  • film and “layer” can be interchanged depending on the circumstances.
  • conductive layer can be changed to the term “conductive film.”
  • insulating film can be changed to the term “insulating layer.”
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less.
  • approximately parallel refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • Perfect refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less.
  • approximately perpendicular refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • electrically connected includes cases where the connection is made via "something that has some kind of electrical action.”
  • something that has some kind of electrical action is not particularly limited as long as it allows the transmission and reception of electrical signals between the connected objects.
  • something that has some kind of electrical action includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.
  • the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state).
  • the off-state refers to a state in which the voltage Vgs between the gate and source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor).
  • normally on refers to a state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate.
  • Normally off refers to a state in which no current flows through the transistor when no potential is applied to the gate or when a ground potential is applied to the gate.
  • the top surface shape of a certain component refers to the contour shape of the component in a planar view.
  • a planar view refers to a view from the normal direction of the surface on which the component is formed or the surface of the support (e.g., substrate) on which the component is formed.
  • top surface shapes roughly match means that at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer, in which case it may also be said that "top surface shapes roughly match.” Furthermore, when the top surface shapes match or roughly match, it can also be said that the edges are aligned or roughly matched, or that the side edges are aligned or roughly matched.
  • a tapered shape refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.
  • A covers B
  • at least a part of A covers B. Therefore, for example, it can be rephrased as saying that A has an area that covers B.
  • a device fabricated using a metal mask or an FMM may be referred to as a device with an MM (metal mask) structure.
  • a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.
  • SBS Side By Side
  • the SBS structure allows the materials and configuration to be optimized for each light-emitting element, which increases the freedom of material and configuration selection and makes it easier to improve brightness and reliability.
  • holes or electrons may be referred to as "carriers".
  • the hole injection layer or electron injection layer may be referred to as the "carrier injection layer”
  • the hole transport layer or electron transport layer may be referred to as the “carrier transport layer”
  • the hole block layer or electron block layer may be referred to as the "carrier block layer”.
  • the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable.
  • one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.
  • the light-emitting element has an EL layer between a pair of electrodes.
  • the EL layer has at least a light-emitting layer.
  • the layers (also called functional layers) that the EL layer has include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer).
  • the light-receiving element also called a light-receiving device
  • one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.
  • the sacrificial layer (which may also be referred to as a mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that make up the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.
  • step discontinuity refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step, etc.).
  • arrows indicating the X direction, Y direction, and Z direction may be used.
  • the "X direction” is the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated.
  • the X direction, Y direction, and Z direction are directions that intersect with each other.
  • the X direction, Y direction, and Z direction are directions that are perpendicular to each other.
  • a semiconductor device has a first conductive layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a first insulating layer, and a second insulating layer.
  • the first insulating layer is located on the first conductive layer, and the second conductive layer is located on the first insulating layer.
  • the first insulating layer and the second conductive layer have a first opening that reaches the first conductive layer.
  • the oxide semiconductor layer contacts at least the top surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer in the first opening.
  • the second insulating layer is located on the oxide semiconductor layer in the first opening.
  • the third conductive layer overlaps the oxide semiconductor layer through the second insulating layer in the first opening.
  • the first conductive layer functions as one of the source and drain electrodes of the transistor.
  • the second conductive layer functions as the other of the source and drain electrodes of the transistor.
  • the third conductive layer functions as the gate electrode of the transistor, and the second insulating layer functions as the gate insulating layer.
  • parasitic capacitance occurs in the area where the second conductive layer and the third conductive layer overlap, which may slow down the operation of the transistor and degrade the frequency characteristics of the circuit.
  • the maximum width of the third conductive layer is equal to or smaller than the minimum width of the opening in the second conductive layer in a cross-sectional view.
  • both ends of the upper surface of the third conductive layer may be located within the first opening in a cross-sectional view.
  • the semiconductor device further includes a third insulating layer and a fourth conductive layer.
  • the third insulating layer is located on the second conductive layer via the second insulating layer, and has a second opening that reaches the third conductive layer at a position overlapping with the first opening.
  • the maximum width of the second opening is equal to or smaller than the minimum width of the first opening in the second conductive layer.
  • the fourth conductive layer contacts the upper surface of the third conductive layer within the second opening.
  • the fourth conductive layer has a portion located in the second opening and a portion in contact with the upper surface of the third insulating layer. At this time, the fourth conductive layer is electrically connected to the third conductive layer and functions as a gate wiring.
  • a third insulating layer is provided between the second conductive layer and the fourth conductive layer. Therefore, the physical distance between the second conductive layer and the fourth conductive layer can be increased, and the parasitic capacitance between the second conductive layer and the fourth conductive layer can be reduced. In other words, compared to when the third conductive layer serves as both the gate electrode and the gate wiring, the parasitic capacitance can be reduced by using the fourth conductive layer on the third insulating layer as the gate wiring.
  • the maximum value of the width of the second opening is equal to or less than the minimum value of the width of the first opening in the second conductive layer, the physical distance between the portion of the fourth conductive layer located in the second opening and the third conductive layer can also be increased, and the occurrence of parasitic capacitance can be suppressed.
  • the height of the upper surface of the fourth conductive layer and the height of the upper surface of the third insulating layer may be the same or approximately the same.
  • the semiconductor device of one embodiment of the present invention may have a fifth conductive layer on the third insulating layer in contact with the upper surface of the fourth conductive layer.
  • the fifth conductive layer is electrically connected to the third conductive layer via the fourth conductive layer and functions as a gate wiring.
  • a third insulating layer is provided between the second conductive layer and the fifth conductive layer. Therefore, the physical distance between the second conductive layer and the fifth conductive layer can be increased, and the parasitic capacitance between the second conductive layer and the fifth conductive layer can be reduced.
  • the physical distance between the part of the fourth conductive layer located in the second opening and the third conductive layer can also be increased, and the occurrence of parasitic capacitance can be suppressed.
  • the semiconductor device of one embodiment of the present invention has a configuration in which parasitic capacitance is reduced, and therefore the frequency characteristics of the circuit can be improved.
  • the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction.
  • the channel length direction has a component in the height direction (vertical direction), and therefore the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, vertical channel transistor, etc.
  • VFET Vertical Field Effect Transistor
  • the transistor can have a source electrode, a semiconductor layer, and a drain electrode that are stacked, so the area occupied can be significantly reduced compared to a so-called planar type transistor in which the semiconductor layer is arranged in a planar shape.
  • FIG. 1A is a plan view of a semiconductor device including a transistor 200A.
  • FIG. 1B is a cross-sectional view taken along dashed lines A1-A2 in FIG. 1A.
  • FIG. 1C is a cross-sectional view taken along dashed lines A3-A4 in FIG. 1A.
  • FIG. 1D is a cross-sectional view taken along dashed lines A5-A6 in FIGS. 1B and 1C.
  • FIG. 1D can also be considered a cross-sectional view of an XY plane including an insulating layer 280. Note that some elements are omitted in the plan view of FIG. 1A for clarity. Some elements may also be omitted in the subsequent plan views.
  • the semiconductor device shown in Figures 1A to 1D, 2A, and 2B includes an insulating layer 210 on a substrate (not shown), a transistor 200A on the insulating layer 210, an insulating layer 280 on the insulating layer 210, an insulating layer 283 on the transistor 200A, an insulating layer 285 on the insulating layer 283, a conductive layer 263 located in an opening 270 provided in the insulating layer 283 and the insulating layer 285, and a conductive layer 265 on the insulating layer 285.
  • the insulating layer 210, the insulating layer 280, the insulating layer 283, and the insulating layer 285 function as interlayer films.
  • Transistor 200A has a conductive layer 220, a conductive layer 240 on insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 on oxide semiconductor layer 230, and a conductive layer 260 on insulating layer 250.
  • an opening 290 is provided in the insulating layer 280 and the conductive layer 240, reaching the conductive layer 220.
  • the bottom of the opening 290 is the upper surface of the conductive layer 220
  • the sidewalls of the opening 290 are the side surfaces of the insulating layer 280 and the conductive layer 240.
  • the opening 290 includes an opening in the insulating layer 280 and an opening in the conductive layer 240.
  • the opening in the area where the insulating layer 280 overlaps with the conductive layer 220 is a part of the opening 290
  • the opening in the area where the conductive layer 240 overlaps with the conductive layer 220 is another part of the opening 290.
  • oxide semiconductor layer 230, insulating layer 250, and conductive layer 260 are disposed such that at least a portion of each is located within opening 290.
  • oxide semiconductor layer 230 contacts the top surface of conductive layer 220, the side surface of insulating layer 280, and the side surface of conductive layer 240.
  • the portions of the oxide semiconductor layer 230 and the insulating layer 250 that are disposed within the opening 290 are provided to reflect the shape of the opening 290.
  • the oxide semiconductor layer 230 is provided to cover the bottom and sidewalls of the opening 290
  • the insulating layer 250 is provided to cover the oxide semiconductor layer 230.
  • the conductive layer 260 is provided to fill at least a portion of the recess in the insulating layer 250 that reflects the shape of the opening 290.
  • the conductive layer 260 is not located on the conductive layer 240, so that the parasitic capacitance between the conductive layer 240 and the conductive layer 260 can be reduced.
  • the maximum width of the conductive layer 260 is the width Da within the opening 290.
  • the width Da is smaller than the width D of the opening 290.
  • the parasitic capacitance between the conductive layer 260 and the conductive layer 240 can be reduced, which is preferable.
  • the magnitude relationship between the two widths in a semiconductor device according to one embodiment of the present invention can be confirmed by a cross section parallel to the Z direction.
  • the width D of the opening 290 may vary in the depth direction.
  • the width D is defined as the shortest distance between the two side surfaces of the conductive layer 240 on the opening 290 side in a cross-sectional view.
  • the minimum width of the opening 290 in the conductive layer 240 is defined as the width D of the opening 290.
  • the region of the oxide semiconductor layer 230 in contact with the conductive layer 240 may function as a low resistance region.
  • the conductive layer 260 is not located on the region of the oxide semiconductor layer 230 in contact with the conductive layer 240, so that the parasitic capacitance between the low resistance region of the oxide semiconductor layer 230 and the conductive layer 260 can also be reduced.
  • the insulating layer 283 and the insulating layer 285 have an opening 270 that reaches the conductive layer 260.
  • the bottom of the opening 270 is the upper surface of the conductive layer 260
  • the sidewalls of the opening 270 are the side surfaces of the insulating layer 283 and the insulating layer 285.
  • the opening 270 includes an opening in the insulating layer 283 and an opening in the insulating layer 285.
  • the opening in the area where the insulating layer 283 overlaps with the conductive layer 260 is a part of the opening 270
  • the opening in the area where the insulating layer 285 overlaps with the conductive layer 260 is another part of the opening 270.
  • the conductive layer 263 is located within the opening 270.
  • the conductive layer 263 contacts the upper surface of the conductive layer 260 within the opening 270. It can also be said that the conductive layer 263 is embedded within the opening 270. It is preferable that the height of the upper surface of the conductive layer 263 and the height of the upper surface of the insulating layer 285 are the same or approximately the same.
  • the width Db of the opening 270 is smaller than the width D of the opening 290. In this way, when the width Db is smaller than the width D, the upper surfaces of the conductive layer 263 and the conductive layer 240 do not overlap, and the parasitic capacitance between the conductive layer 263 and the conductive layer 240 can be reduced, which is preferable.
  • the width Db of the opening 270 may vary in the depth direction.
  • the maximum width of the opening 270 provided in the insulating layer 283 and the insulating layer 285 in a cross-sectional view is used as the width Db.
  • the conductive layer 260 is electrically connected to the conductive layer 265 provided on the insulating layer 285 via the conductive layer 263.
  • the conductive layer 265 is in contact with the upper surface of the conductive layer 263.
  • Insulating layer 283 and insulating layer 285 are located between conductive layer 265 and conductive layer 240. This allows the physical distance between conductive layer 265 and conductive layer 240 to be increased, and the parasitic capacitance between conductive layer 265 and conductive layer 240 to be reduced.
  • the oxide semiconductor layer 230 functions as a semiconductor layer
  • the conductive layer 260 functions as a gate electrode
  • the insulating layer 250 functions as a gate insulating layer
  • the conductive layer 220 functions as one of the source electrode and the drain electrode
  • the conductive layer 240 functions as the other of the source electrode and the drain electrode.
  • the conductive layer 265 functions as a gate wiring.
  • the transistor 200A has a configuration in which the parasitic capacitance between the other of the source electrode and the drain electrode and the gate electrode, and the parasitic capacitance between the other of the source electrode and the drain electrode and the gate wiring are reduced. Therefore, the frequency characteristics of the circuit can be improved.
  • the oxide semiconductor layer 230 is provided inside the opening 290 of the insulating layer 280.
  • the transistor 200A has a configuration in which one of the source electrode and the drain electrode (conductive layer 220 here) is located on the lower side and the other of the source electrode and the drain electrode (conductive layer 240 here) is located on the upper side, so that a current flows in the vertical direction. In other words, a channel is formed along the side surface of the opening 290 of the insulating layer 280.
  • the oxide semiconductor layer 230 contacts the upper surface of the conductive layer 220 and the side surface of the conductive layer 240.
  • the oxide semiconductor layer 230 also contacts a part of the upper surface of the conductive layer 240. In this way, the oxide semiconductor layer 230 contacts not only the side surface but also the upper surface of the conductive layer 240, so that the area of contact between the oxide semiconductor layer 230 and the conductive layer 240 can be increased. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.
  • the end of the conductive layer 240, the end of the oxide semiconductor layer 230, and the end of the insulating layer 250 are aligned outside the opening 290.
  • the conductive layer 240, the oxide semiconductor layer 230, and the insulating layer 250 can be manufactured by processing using the same mask. Therefore, the number of masks required for manufacturing the semiconductor device can be reduced, which is preferable.
  • the present invention is not limited to this.
  • any of the end of the oxide semiconductor layer 230, the end of the insulating layer 250, and the end of the conductive layer 240 may be located inside or outside the others.
  • the sidewall of the opening 290 is preferably perpendicular or approximately perpendicular to the upper surface of the insulating layer 210.
  • the film provided inside the opening 290 is formed using the atomic layer deposition (ALD) method.
  • the ALD method can deposit atoms one layer at a time, and therefore has the effects of enabling extremely thin film formation, film formation on a structure with a high aspect ratio, film formation with few defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Therefore, the film can be formed on the side surface of the opening 290 with good coverage.
  • the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each formed using the ALD method.
  • the opening 290 is provided so that the sidewall of the opening 290 is perpendicular to the upper surface of the insulating layer 210, but the present invention is not limited to this.
  • the sidewall of the opening 290 may be tapered (see FIG. 6D described later). By tapering the sidewall of the opening 290, the coverage of the oxide semiconductor layer 230, the insulating layer 250, etc. can be improved, and defects such as voids can be reduced.
  • the taper angle ⁇ of the side surface of the insulating layer 280 in the opening 290 is preferably 45 degrees or more and less than 90 degrees.
  • the semiconductor device can be miniaturized or highly integrated.
  • the taper angle ⁇ is 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less, the coverage of the film formed in the opening 290 is improved, which is preferable.
  • the sidewall of the opening 290 may have an inverse tapered shape.
  • the taper angle ⁇ of the side surface of the insulating layer 280 in the opening 290 may be greater than 90 degrees.
  • the insulating layer 250 is provided in contact with the upper surface of the oxide semiconductor layer 230.
  • the insulating layer 250 has a region in contact with the upper surface of the conductive layer 240 and a region in contact with the insulating layer 280.
  • the conductive layer 240 has an opening in a region overlapping with the conductive layer 220.
  • the conductive layer 240 is not provided inside the opening of the insulating layer 280.
  • the conductive layer 240 does not have a region in contact with the side of the insulating layer 280 in the opening 290.
  • the opening of the conductive layer 240 and the opening of the insulating layer 280 can be formed at the same time.
  • the film thickness distribution of the oxide semiconductor layer 230 provided inside the opening 290 can be made uniform. Furthermore, it is possible to prevent the oxide semiconductor layer 230 from being divided by a step between the conductive layer 240 and the insulating layer 280.
  • FIGS. 1B and 1C show a configuration in which the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280 in the opening 290 are flush (aligned or roughly aligned), but the present invention is not limited to this.
  • the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280 in the opening 290 may be discontinuous.
  • the inclination of the side surface of the conductive layer 240 in the opening 290 and the inclination of the side surface of the insulating layer 280 in the opening 290 may be different from each other.
  • the taper angle of the side surface of the conductive layer 240 in the opening 290 is smaller than the taper angle of the side surface of the insulating layer 280 in the opening 290.
  • the present invention is not limited to this.
  • a recess that overlaps with the opening 290 may be formed on the upper surface of the conductive layer 220.
  • Transistor 200A has a metal oxide (also called an oxide semiconductor) that functions as a semiconductor in the oxide semiconductor layer 230 including the channel formation region.
  • transistor 200A can be said to be an OS transistor.
  • oxygen vacancies ( VO ) and impurities are present in a channel formation region in an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate and the reliability may be reduced. Furthermore, hydrogen near the oxygen vacancies may form a defect in which hydrogen is inserted into the oxygen vacancies (hereinafter sometimes referred to as VOH ), and may generate electrons that serve as carriers. For this reason, when oxygen vacancies are present in the channel formation region in the oxide semiconductor, the OS transistor is likely to be normally on. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor is reduced and the channel formation region in the oxide semiconductor is made i-type (intrinsic) or substantially i-type.
  • the source and drain regions of an OS transistor are preferably regions having more oxygen vacancies, more VOH , or a higher concentration of impurities such as hydrogen, nitrogen, or metal elements than the channel formation region, thereby increasing the carrier concentration and lowering the resistance. That is, the source and drain regions of an OS transistor are preferably n-type regions having a higher carrier concentration and lower resistance than the channel formation region.
  • the region of the oxide semiconductor layer 230 in contact with the insulating layer 280 and its vicinity function as the channel formation region of the transistor 200A.
  • One of the region of the oxide semiconductor layer 230 in contact with the conductive layer 220 and the region of the oxide semiconductor layer 230 in contact with the conductive layer 240 functions as a source region, and the other functions as a drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.
  • the oxide semiconductor layer 230 and the conductive layer 220 come into contact with each other, a metal compound or oxygen vacancy is formed, and the region of the oxide semiconductor layer 230 that comes into contact with the conductive layer 220 becomes less resistant. This reduces the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220.
  • the oxide semiconductor layer 230 and the conductive layer 240 come into contact with each other, the region of the oxide semiconductor layer 230 that comes into contact with the conductive layer 240 becomes less resistant. This reduces the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240.
  • the insulating layer 280 contacts the entire outer periphery of the oxide semiconductor layer 230. Therefore, the channel formation region of the transistor 200A can be formed on the entire outer periphery of the oxide semiconductor layer 230 in the opening 290 (the entire region in contact with the insulating layer 280). Note that FIG. 1D can also be considered a cross-sectional view in the XY plane including the channel formation region of the oxide semiconductor layer 230.
  • the channel length of the transistor 200A is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200A is determined by the thickness of the insulating layer 280 on the conductive layer 220.
  • the channel length L of the transistor 200A is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L is the distance between the end of the region where the oxide semiconductor layer 230 and the conductive layer 220 contact each other and the end of the region where the oxide semiconductor layer 230 and the conductive layer 240 contact each other. In other words, the channel length L corresponds to the length of the side of the insulating layer 280 on the opening 290 side in a cross-sectional view.
  • the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult.
  • the channel length can be set by the film thickness of the insulating layer 280. Therefore, the channel length of the transistor 200A can be made into a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-current of the transistor 200A, improving the frequency characteristics.
  • a channel formation region, a source region, and a drain region can be formed in the opening 290.
  • the area occupied by the transistor 200A can be reduced compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.
  • the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. Therefore, the side surface of the conductive layer 260 arranged at the center faces the side surface of the oxide semiconductor layer 230 through the insulating layer 250. That is, in a plan view, the entire circumference of the oxide semiconductor layer 230 becomes a channel formation region.
  • the channel width of the transistor 200A is determined by the length of the outer periphery of the oxide semiconductor layer 230. That is, it can be said that the channel width of the transistor 200A is determined by the width of the opening 290 (the diameter when the opening 290 is circular in a plan view).
  • the width D of the opening 290 is indicated by a double-headed arrow of a two-dot chain line.
  • the channel width W of the transistor 200A is indicated by a double-headed arrow of a one-dot chain line.
  • the width D of the opening 290 is limited by the exposure limit of photolithography.
  • the width D of the opening 290 is set by the film thickness of each of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the opening 290.
  • the width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D x ⁇ ".
  • the channel length L of the transistor 200A is at least smaller than the channel width W of the transistor 200A.
  • the channel length L of the transistor 200A is preferably 0.1 to 0.99 times the channel width W of the transistor 200A, and more preferably 0.5 to 0.8 times. With such a configuration, a transistor having good electrical characteristics and high reliability can be realized.
  • the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. This makes the distance between the conductive layer 260 and the oxide semiconductor layer 230 approximately uniform, so that a gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.
  • the opening 290 is circular in plan view, but the present invention is not limited to this.
  • the opening 290 may be substantially circular, such as an ellipse, polygonal, such as a rectangle, or polygonal, such as a rectangle, with rounded corners.
  • each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked structure.
  • FIGS. 1B and 1C show an example in which the conductive layer 220, the oxide semiconductor layer 230, the conductive layer 240, the insulating layer 250, and the conductive layer 260 each have a single-layer structure.
  • FIGS. 2A and 2B show an example in which the conductive layer 220, the oxide semiconductor layer 230, the conductive layer 240, the insulating layer 250, and the conductive layer 260 each have a stacked structure.
  • the oxide semiconductor layer 230 has a channel formation region.
  • the channel formation region is i-type (intrinsic) or substantially i-type.
  • the oxide semiconductor layer 230 further has a source region and a drain region.
  • the source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region.
  • the crystallinity of the semiconductor material used for the oxide semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • the use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.
  • the band gap of a metal oxide that functions as a semiconductor is preferably 2.0 eV or more, and more preferably 2.5 eV or more.
  • metal oxides examples include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably contains two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or semi-metal element having a high bond energy with oxygen, for example, a metal element or semi-metal element having a bond energy with oxygen higher than that of indium.
  • element M examples include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification may include metalloid elements.
  • the oxide semiconductor layer 230 may be, for example, indium oxide (In oxide), indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), Indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZ
  • the field effect mobility of the transistor can be increased.
  • a transistor with a large on-current can be realized.
  • the metal oxide may contain one or more metal elements having a high period number in the periodic table instead of or in addition to indium.
  • metal elements having a high period number include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the carrier concentration may increase or the band gap may be narrowed, which may increase the field effect mobility of the transistor.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • a metal oxide with a large band gap can be obtained.
  • the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained.
  • a shift in the threshold voltage of the transistor can be suppressed.
  • fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide applied to the oxide semiconductor layer 230. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.
  • the metal oxide is In-M-Zn oxide
  • the atomic ratio of In in the In-M-Zn oxide is greater than or equal to the atomic ratio of M.
  • the nearby composition includes a range of ⁇
  • the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M.
  • the total proportion of the atomic numbers of the metal elements can be regarded as the proportion of the atomic number of element M.
  • the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained may be referred to as the indium content. The same applies to other metal elements.
  • the In-Zn oxide may also contain a trace amount of element M.
  • EDX energy dispersive X-ray spectrometry
  • XPS X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • the metal oxide can be formed by sputtering or ALD.
  • the composition of the metal oxide after film formation may differ from the composition of the target.
  • the zinc content in the metal oxide after film formation may decrease to about 50% compared to the target.
  • the metal oxide may be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or the like.
  • the oxide semiconductor layer 230 may have a stacked structure having two or more metal oxide layers.
  • the two or more metal oxide layers in the oxide semiconductor layer 230 may have the same or approximately the same composition.
  • the two or more metal oxide layers in the oxide semiconductor layer 230 may have different compositions.
  • Figure 2A shows an example in which the oxide semiconductor layer 230 has a two-layer structure of an oxide layer 230a and an oxide layer 230b on the oxide layer 230a.
  • a material having a higher conductivity than the oxide layer 230b for the oxide layer 230a it is preferable to use a material having a higher conductivity than the oxide layer 230b for the oxide layer 230a.
  • a material having a higher conductivity for the oxide layer 230a in contact with the source electrode and the drain electrode (the conductive layer 220 and the conductive layer 240)
  • the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced, and a transistor having a large on-current can be obtained.
  • the threshold voltage of the transistor 200A may shift, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may become large.
  • the threshold voltage may become low. Therefore, it is preferable to use a material with lower conductivity than the oxide layer 230a for the oxide layer 230b.
  • the threshold voltage can be increased, and the transistor can have a small cutoff current. Note that a small cutoff current may be referred to as a normally-off transistor.
  • the oxide semiconductor layer 230 As described above, by forming the oxide semiconductor layer 230 into a stacked structure and using a material having a higher conductivity than the oxide layer 230b for the oxide layer 230a, a transistor that is normally off and has a large on-state current can be obtained. Therefore, a semiconductor device that achieves both low power consumption and high performance can be obtained.
  • the carrier concentration of the oxide layer 230a is preferably higher than that of the oxide layer 230b.
  • the conductivity is increased, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced, and a transistor with a large on-current can be obtained.
  • the conductivity is decreased, and a normally-off transistor can be obtained.
  • the oxide semiconductor layer 230 is not limited to the above-mentioned configuration, and the oxide layer 230a may be made of a material having a lower conductivity than the oxide layer 230b.
  • the carrier concentration of the oxide layer 230a may be lower than the carrier concentration of the oxide layer 230b.
  • the band gap of the first metal oxide used in the oxide layer 230a is different from the band gap of the second metal oxide used in the oxide layer 230b.
  • the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
  • the band gap of the first metal oxide used in the oxide layer 230a is preferably smaller than the band gap of the second metal oxide used in the oxide layer 230b. This can reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 and between the oxide semiconductor layer 230 and the conductive layer 240, and can provide a transistor with a large on-current.
  • the transistor 200A is an n-channel transistor, the threshold voltage can be increased, and the transistor can be a normally-off transistor.
  • the large band gap of the second metal oxide can suppress the generation and induction of carriers in the oxide layer 230b and at the interface between the oxide layer 230b and the insulating layer 250. This can improve the reliability of the transistor.
  • the oxide semiconductor layer 230 is not limited to the above-mentioned configuration, and the band gap of the first metal oxide may be larger than the band gap of the second metal oxide.
  • the content of element M in the first metal oxide is lower than the content of element M in the second metal oxide.
  • the first metal oxide may be configured to contain a trace amount of element M or to contain no element M.
  • the first metal oxide used in the oxide layer 230a is In-Zn oxide
  • the second metal oxide used in the oxide layer 230b is In-M-Zn oxide.
  • the first metal oxide can be In-Zn oxide
  • the second metal oxide can be In-Ga-Zn oxide.
  • This increases the on-state current of transistor 200A and creates a highly reliable transistor structure with minimal variation.
  • oxide semiconductor layer 230 is not limited to the above-mentioned configuration, and the content of element M in the first metal oxide may be higher than the content of element M in the second metal oxide.
  • the oxide semiconductor layer 230 preferably has a crystalline metal oxide layer.
  • the crystalline metal oxide structure include a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a nano-crystalline (nc: nano-crystal) structure.
  • the crystallinity of the oxide semiconductor layer 230 can be analyzed, for example, by X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • the oxide semiconductor layer 230 may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, it may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, and the second metal oxide layer may have a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. In this case, the first metal oxide layer and the second metal oxide layer may have different compositions, or may have the same or approximately the same composition.
  • the oxide layer 230b by forming the oxide layer 230b on the oxide layer 230a having high crystallinity, it is also easy to improve the crystallinity of the oxide layer 230b. This makes it possible to improve the crystallinity of the entire oxide semiconductor layer 230, which is preferable.
  • gallium, aluminum, or tin as the element M.
  • two layers of IGZO having different compositions may be stacked.
  • a laminated structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) may be used.
  • FIG. 2B shows an example in which the oxide semiconductor layer 230 has a three-layer structure including an oxide layer 230c, an oxide layer 230a on the oxide layer 230c, and an oxide layer 230b on the oxide layer 230a.
  • the above-mentioned configuration can be applied to the oxide layer 230a and the oxide layer 230b.
  • the oxide layer 230c can have a similar configuration to that applicable to the oxide layer 230b.
  • the oxide layer 230b and the oxide layer 230c preferably have a larger band gap than the oxide layer 230a.
  • the oxide layer 230a is sandwiched between the oxide layer 230b and the oxide layer 230c, which have a larger band gap, and the oxide layer 230a mainly functions as a current path (channel).
  • sandwiching the oxide layer 230a between the oxide layer 230b and the oxide layer 230c it is possible to reduce the trap level at the interface of the oxide layer 230a and its vicinity.
  • a buried channel type transistor in which the channel is away from the insulating layer interface can be realized, and the field effect mobility can be increased.
  • the influence of the interface state that may be formed on the back channel side is reduced, and the light deterioration of the transistor (e.g., negative bias light deterioration) can be suppressed, and the reliability of the transistor can be improved.
  • the thickness of the oxide semiconductor layer 230 is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, and more preferably 20 nm or more and 50 nm or less.
  • the thickness of the oxide semiconductor layer 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
  • Hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to become water, and oxygen vacancies ( VO ) may be formed in the oxide semiconductor. Furthermore, a defect in which hydrogen enters an oxygen vacancy (hereinafter referred to as VOH ) may function as a donor and generate an electron that is a carrier. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate an electron that is a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to be normally on (that is, the threshold voltage has a negative value). Furthermore, hydrogen in an oxide semiconductor is easily mobile due to stress such as heat or an electric field, and therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.
  • VOH in the oxide semiconductor layer 230 it is preferable to reduce VOH in the oxide semiconductor layer 230 as much as possible to make the oxide semiconductor layer 230 highly pure intrinsic or substantially highly pure intrinsic.
  • it is important to remove impurities such as water and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to repair oxygen vacancies.
  • impurities such as water and hydrogen from the oxide semiconductor
  • an oxide semiconductor with sufficiently reduced impurities such as VOH for a channel formation region of a transistor stable electrical characteristics can be imparted.
  • oxygen addition treatment oxygen addition treatment.
  • the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , even more preferably less than 1 ⁇ 10 16 cm ⁇ 3 , still more preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and still more preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, and can be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • the carbon concentration in a channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and further preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and still more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in a channel formation region of an oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, and further preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy.
  • an electron serving as a carrier may be generated.
  • some of the hydrogen may bond to oxygen bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in a channel formation region of the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably less than 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , and further preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • the concentration of the alkali metal or the alkaline earth metal in a channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material in the channel formation region.
  • the other semiconductor material include semiconductors made of single elements, or compound semiconductors.
  • semiconductors made of single elements include silicon and germanium.
  • compound semiconductors include gallium arsenide and silicon germanium.
  • Other examples of compound semiconductors include organic semiconductors and nitride semiconductors.
  • the aforementioned oxide semiconductor is also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.
  • Silicon that can be used as a semiconductor material for transistors includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • An example of polycrystalline silicon is low temperature polysilicon (LTPS).
  • the semiconductor layer of the transistor may have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), zirconium selenide (representatively ZrSe 2 ), and the like.
  • an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 250, insulating layer 280, insulating layer 283, insulating layer 285, etc.) included in the semiconductor device.
  • the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film.
  • oxide insulating film examples include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film.
  • nitride insulating film examples include a silicon nitride film and an aluminum nitride film.
  • Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film.
  • Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film.
  • An organic insulating film may be used for the insulating layer of the semiconductor device.
  • Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.
  • materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin.
  • inorganic insulating materials with a low relative dielectric constant include silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen.
  • a material that can have ferroelectricity may be used for the insulating layer of the semiconductor device.
  • materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (X is a real number greater than 0).
  • materials that can have ferroelectricity include materials in which an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide.
  • the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set appropriately, and for example, it is preferable that the ratio of the number of atoms of hafnium to the number of atoms of element J1 is 1:1 or close to 1:1.
  • materials that can have ferroelectricity include materials in which an element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide.
  • the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, and for example, it is preferable that the ratio of the number of zirconium atoms to the number of atoms of element J2 is 1: 1 or close to 1.
  • piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiO x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may be used.
  • examples of materials that may have ferroelectricity include metal nitrides having element M1, element M2, and nitrogen.
  • element M1 is one or more selected from aluminum, gallium, indium, etc.
  • element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. It should be noted that the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Also, metal oxides having element M1 and nitrogen may have ferroelectricity even if they do not contain element M2.
  • examples of materials that may have ferroelectricity include materials in which element M3 is added to the above metal nitride.
  • element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.
  • the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.
  • examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO 2 N and BaTaO 2 N, and GaFeO 3 with a ⁇ -alumina structure.
  • metal oxides and metal nitrides are exemplified, but the present invention is not limited to these.
  • metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.
  • the insulating layer 130 can have a laminated structure made of multiple materials selected from the materials listed above.
  • the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials that can have ferroelectricity.
  • Metal oxides containing hafnium and/or zirconium can have ferroelectricity even in thin films of a few nm. Metal oxides containing hafnium and/or zirconium can also have ferroelectricity even in very small areas. Therefore, by using metal oxides containing hafnium and/or zirconium, it is possible to miniaturize semiconductor devices.
  • a layer of a material that may have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film.
  • a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in this specification.
  • ferroelectricity is expressed by the displacement of oxygen or nitrogen in the crystals contained in the ferroelectric layer due to an external electric field. It is also presumed that the expression of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulating layer to express ferroelectricity, the insulating layer 130 must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, since ferroelectricity is expressed.
  • the crystal structure of the crystals contained in the insulating layer may be one or more selected from the cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems.
  • the insulating layer may have an amorphous structure. In this case, the insulating layer may be a composite structure having an amorphous structure and a crystalline structure.
  • a Group 3 element also called a IIIa element
  • the oxygen vacancy concentration in the oxide increases, making it easier to form crystals having an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals having an orthorhombic crystal structure and increases the remanent polarization.
  • the amount of the Group 3 element added is too large, the crystallinity of the oxide may decrease and it may be difficult to express ferroelectricity.
  • the content of the Group 3 element in the oxide having one or both of hafnium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and even more preferably 0.1 atomic% or more and 3 atomic% or less.
  • the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer.
  • the Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.
  • an insulating layer having a function of suppressing the permeation of impurities and oxygen for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer.
  • metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide
  • metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.
  • examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate).
  • Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxide nitride, and silicon nitride.
  • an insulating layer such as a gate insulating layer that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, may be referred to as excess oxygen).
  • an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, whereby oxygen vacancies in the oxide semiconductor layer can be reduced.
  • Examples of insulating layers that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.
  • the dielectric constant be low.
  • the parasitic capacitance that occurs between wiring can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, so are suitable for the insulating layer 210.
  • the concentration of impurities such as water and hydrogen in the insulating layer 210 is reduced. This can suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230.
  • a barrier insulating layer against hydrogen as the insulating layer 210.
  • the insulating layer 210 provided on the outside of the oxide semiconductor layer 230 has a barrier property against hydrogen, so that the diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed.
  • Materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon oxynitride.
  • a barrier insulating layer refers to an insulating layer having a barrier property.
  • the barrier property refers to a property that a corresponding substance is difficult to diffuse (also referred to as a property that a corresponding substance is difficult to permeate, a property that the permeability of a corresponding substance is low, or a function of suppressing the diffusion of a corresponding substance).
  • hydrogen when described as a corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁇ .
  • impurities when described as a corresponding substance refer to impurities in a channel formation region or a semiconductor layer unless otherwise specified, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2 , etc.), a copper atom, etc.
  • oxygen when described as a corresponding substance refers to at least one of, for example, an oxygen atom, an oxygen molecule, etc.
  • a silicon nitride film as the insulating layer 210.
  • the insulating layer 280 preferably has the aforementioned barrier insulating layer against hydrogen.
  • the insulating layer 280 is provided so as to surround the oxide semiconductor layer 230.
  • the insulating layer 280 provided on the outside of the oxide semiconductor layer 230 has barrier properties against hydrogen, so that the diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed.
  • the insulating layer 280 preferably has a silicon nitride film.
  • Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layer 280, oxygen is extracted from the oxide semiconductor layer 230, and the formation of an excessive amount of oxygen vacancies in the oxide semiconductor layer 230 can be suppressed.
  • the insulating layer 280 by using silicon nitride for the insulating layer 280, it is possible to prevent excess oxygen from being supplied to the oxide semiconductor layer 230. Therefore, it is possible to prevent the channel formation region of the oxide semiconductor layer 230 from becoming excessively oxygenated, thereby improving the reliability of the transistor 200A.
  • the insulating layer 280 has an oxide insulating film, an oxynitride insulating film, or an insulating layer having a region containing excess oxygen, as described above.
  • an insulating layer having a region containing excess oxygen can be formed by deposition using a sputtering method in an atmosphere containing oxygen.
  • a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas the hydrogen concentration in the insulating layer 280 can be reduced.
  • the concentration of impurities such as water and hydrogen in the insulating layer 280 is reduced. This can suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230.
  • the thickness of the insulating layer 280 on the conductive layer 220 corresponds to the channel length of the transistor 200A, so the thickness of the insulating layer 280 is appropriately set according to the design value of the channel length of the transistor 200A.
  • insulating layer 280 it is preferable to use a single-layer structure of a silicon nitride film as the insulating layer 280.
  • insulating layer 280 it is preferable to use a three-layer structure in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in this order as the insulating layer 280.
  • the insulating layer 250 preferably has a function of capturing hydrogen and fixing hydrogen.
  • the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in a channel formation region of a transistor) can be reduced.
  • VOH in the channel formation region can be reduced and the channel formation region can be made i-type or substantially i-type.
  • the material of the insulating layer having the function of capturing or fixing hydrogen includes metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, for example, oxides containing hafnium and zirconium.
  • these metal oxides preferably have an amorphous structure.
  • the amorphous structure may be realized by including silicon in these oxides.
  • the metal oxide may have one or both of a crystalline region and a crystal grain boundary in a part.
  • the ability to capture or adhere to the corresponding substance can also be said to have the property of making the corresponding substance less likely to diffuse. Therefore, the ability to capture or adhere to the corresponding substance can be rephrased as barrier properties.
  • Figures 2A and 2B show an example in which insulating layer 250 has a two-layer structure of insulating layer 250a and insulating layer 250b on insulating layer 250a.
  • the layer in contact with the oxide semiconductor layer 230 has the function of capturing hydrogen and fixing hydrogen. That is, in FIG. 2A and FIG. 2B, it is preferable that the insulating layer 250a has the function of capturing hydrogen and fixing hydrogen. In addition, it is preferable to use the above-mentioned barrier insulating layer against hydrogen as the insulating layer 250b.
  • the insulating layer 250a has a function of capturing or fixing hydrogen, so that the hydrogen contained in the oxide semiconductor layer 230 can be captured or fixed more effectively. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.
  • hafnium silicate or the like can be used as the insulating layer 250a.
  • the insulating layer 250a preferably has an amorphous structure.
  • the insulating layer 250a By making the insulating layer 250a an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer 250a. This makes the film thickness distribution of the insulating layer 250a uniform, and it is possible to reduce the number of areas where the film thickness is extremely thin, thereby improving the breakdown voltage of the insulating layer 250a. In addition, it is possible to uniform the film thickness distribution of the film provided on the insulating layer 250a.
  • the insulating layer 250a can function as an insulating film with low leakage current.
  • hafnium oxide is a high dielectric constant (high-k) material, so hafnium silicate can also be a high dielectric constant (high-k) material depending on the silicon content. Therefore, when the insulating layer 250a is used as a gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulating layer. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer.
  • EOT equivalent oxide thickness
  • Silicon nitride has high barrier properties against hydrogen and is therefore suitable for the insulating layer 250b.
  • a high dielectric constant (high-k) material for the insulating layer 250.
  • An example of a high-k material is an oxide containing one or both of aluminum and hafnium.
  • an oxide containing one or both of aluminum and hafnium as the insulating layer 250a, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.
  • the insulating layer 250 may have an insulating layer having a thermally stable structure, such as silicon oxide or silicon oxynitride.
  • the insulating layer 250 may have an insulating layer with a heat-stable structure between a pair of insulating layers that have the function of capturing and fixing hydrogen.
  • the insulating layer 250 has a barrier insulating layer against oxygen. This can suppress oxidation of the conductive layer 240, the conductive layer 260, etc.
  • the layer in contact with the conductive layer 240 and the layer in contact with the conductive layer 260 are each a barrier insulating layer against oxygen.
  • oxidation of the conductive layer 260 can be suppressed.
  • Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).
  • the layer in insulating layer 250 that contacts conductive layer 240 is preferably less permeable to oxygen than insulating layer 280.
  • the layer has a barrier property against oxygen, which can prevent the side surface of conductive layer 240 from being oxidized and an oxide film from being formed on the side surface. This can prevent a decrease in the on-current or a decrease in the field effect mobility of transistor 200A.
  • the thickness of the insulating layer 250 is preferably 0.1 nm or more and 30 nm or less, preferably 0.1 nm or more and 20 nm or less, preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5.0 nm or less, more preferably 0.5 nm or more and 5.0 nm or less, more preferably 1.0 nm or more and less than 5.0 nm, and even more preferably 1.0 nm or more and 3.0 nm or less.
  • the insulating layer 250 it is preferable to use a three-layer structure in which a first insulating layer having a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the oxide semiconductor layer 230 side.
  • a material having a low dielectric constant of the first insulating layer it is preferable to use silicon oxide or silicon oxynitride.
  • the first insulating layer is a layer in contact with the oxide semiconductor layer 230. By using an oxide for the first insulating layer, oxygen can be supplied to the oxide semiconductor layer 230.
  • the third insulating layer it is possible to suppress the diffusion of oxygen contained in the first insulating layer to the conductive layer 260 and suppress the oxidation of the conductive layer 260. In addition, it is possible to suppress a decrease in the amount of oxygen supplied from the first insulating layer to the oxide semiconductor layer 230.
  • a four-layer structure is preferably used in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer having a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the oxide semiconductor layer 230 side.
  • the first insulating layer to the third insulating layer can have a similar structure to the layers used in the above-mentioned three-layer structure.
  • the fourth insulating layer is a layer in contact with the oxide semiconductor layer 230.
  • the fourth insulating layer has a barrier property against oxygen, so that oxygen can be prevented from being released from the oxide semiconductor layer 230.
  • aluminum oxide may be used as the fourth insulating layer.
  • Aluminum oxide has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230.
  • each layer constituting the insulating layer 250 is thin.
  • the thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less.
  • each layer constituting the insulating layer 250 may have a region with the above-mentioned thickness in at least a portion.
  • the film thicknesses of the fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively.
  • the insulating layer 283 is preferably a barrier insulating layer against hydrogen. This can suppress the diffusion of hydrogen from above the insulating layer 283 to the oxide semiconductor layer 230.
  • a silicon nitride film and a silicon nitride oxide film each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used for the insulating layer 283.
  • silicon nitride deposited by sputtering As the insulating layer 283. Sputtering does not require the use of hydrogen-containing molecules in the deposition gas, and therefore the hydrogen concentration in the insulating layer 283 can be reduced. Furthermore, by depositing the insulating layer 283 by sputtering, silicon nitride with high density can be formed.
  • an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 283.
  • Hafnium silicate or the like can be used as the insulating layer 283.
  • the insulating layer 283 may also have a laminated structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen.
  • the insulating layer 283 may be a laminated film of aluminum oxide and silicon nitride on the aluminum oxide.
  • the insulating layer 285 functions as an interlayer film, it is preferable to use a material with a low dielectric constant as described above. For example, it is preferable that the insulating layer 285 has a silicon oxide film.
  • conductive layer 220, conductive layer 240, conductive layer 260, conductive layer 263, conductive layer 265, etc. it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements, etc.
  • a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium
  • a nitride of the alloy or an oxide of the alloy may be used.
  • a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum
  • conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel
  • materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing oxygen diffusion, or materials that maintain conductivity even when oxygen is absorbed.
  • examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide.
  • ITO indium oxide containing titanium oxide
  • ITSO indium tin oxide with added silicon
  • IZO indium zinc oxide
  • a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.
  • Conductive materials based on tungsten, copper, or aluminum are preferred because they have high conductivity.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing nitrogen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen and a conductive material containing nitrogen.
  • a metal oxide is used for the channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductive layer that functions as a gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.
  • the conductive layer 220 and the conductive layer 240 are each a conductive layer in contact with the oxide semiconductor layer 230, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, an oxide conductive material, or a conductive material that has a function of suppressing oxygen diffusion.
  • a conductive material that is not easily oxidized a conductive material that maintains low electrical resistance even when oxidized, an oxide conductive material, or a conductive material that has a function of suppressing oxygen diffusion.
  • Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.
  • the conductive layer 220 or the conductive layer 240 can maintain its conductivity even if it absorbs oxygen.
  • the conductive layer 220 is preferable because it can maintain its conductivity.
  • ITO, ITSO, IZO (registered trademark), etc. are preferably used as each of the conductive layer 220 and the conductive layer 240.
  • the conductive layer 220 has a three-layer structure including a conductive layer 220a, a conductive layer 220b on the conductive layer 220a, and a conductive layer 220c on the conductive layer 220b.
  • a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen as the conductive layer 220a, a material with high conductivity as the conductive layer 220b, and a conductive material containing oxygen as the conductive layer 220c.
  • the conductive layer 220a it is preferable to use titanium nitride as the conductive layer 220a, tungsten as the conductive layer 220b, and ITO or ITSO as the conductive layer 220c.
  • titanium nitride is in contact with the insulating layer 210
  • ITO or ITSO is in contact with the oxide semiconductor layer 230.
  • the conductive layer 220 can maintain conductivity even when it is in contact with the oxide semiconductor layer 230.
  • the insulating layer 210 can prevent the conductive layer 220 from being excessively oxidized.
  • the conductivity of the conductive layer 220 can be increased.
  • the conductive layer 240 has a two-layer structure of a conductive layer 240a and a conductive layer 240b on the conductive layer 240a.
  • a material having a higher conductivity than the conductive layer 240b as the conductive layer 240a
  • a conductive material containing oxygen as the conductive layer 240b.
  • ruthenium, tungsten, titanium nitride, or tantalum nitride as the conductive layer 240a
  • ITO or ITSO is in contact with the oxide semiconductor layer 230.
  • the conductive layer 240 can maintain conductivity even when in contact with the oxide semiconductor layer 230.
  • the conductive layer 240 can be increased in conductivity by using a material having a higher conductivity than the conductive layer 240b as the conductive layer 240a.
  • the conductive layer 260 is preferably made of a highly conductive material such as tungsten.
  • the conductive layer 260 is preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen.
  • examples of the conductive material include conductive materials that contain nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials that contain oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.
  • a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed for the conductive layer 260 may be used.
  • the conductive material containing the above-mentioned metal element and nitrogen for example, titanium nitride, tantalum nitride, etc.
  • one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may be used.
  • Indium gallium zinc oxide containing nitrogen may also be used.
  • the conductive layer 260 has a two-layer structure of a conductive layer 260a and a conductive layer 260b on the conductive layer 260a.
  • tantalum nitride as the conductive layer 260a and copper as the conductive layer 260b. With such a configuration, the conductivity of the conductive layer 260 can be increased.
  • the conductive layer 260 may also have a laminated structure of three or more layers.
  • the conductive layer 260 may have a three-layer structure of tantalum nitride, titanium nitride on tantalum nitride, and tungsten on titanium nitride.
  • the conductive layer 263 can be formed using any of the various conductive materials described above.
  • the conductive layer 263 can have the same structure as the conductive layer 260.
  • the conductive layer 263 has a two-layer structure of a conductive layer 263a and a conductive layer 263b on the conductive layer 263a.
  • the conductive layer 265 preferably has high conductivity because it functions as a gate wiring. Tungsten is preferably used for the conductive layer 265.
  • the conductive layer 265 may have the same structure as the conductive layer 260. For example, a two-layer structure of titanium nitride and tungsten may be applied.
  • the substrate on which the transistor is formed for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used.
  • a insulating substrate for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), a resin substrate, etc. are available.
  • a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide, etc. are available.
  • a semiconductor substrate having an insulating region inside the aforementioned semiconductor substrate for example, an SOI (Silicon On Insulator) substrate, etc. are available.
  • the conductive substrate there is a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. are available.
  • a substrate having a metal nitride, a substrate having a metal oxide, etc. are available.
  • a substrate in which a conductor or a semiconductor is provided on an insulating substrate
  • a substrate in which a conductor or an insulator is provided on a semiconductor substrate a substrate in which a semiconductor or an insulator is provided on a conductive substrate, etc.
  • a substrate provided with elements may be used.
  • the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.
  • Figure 3A is a plan view of a semiconductor device including a transistor 200B.
  • Figure 3B is a cross-sectional view taken along dashed dotted line A1-A2 in Figure 3A.
  • Figure 3C is a cross-sectional view taken along dashed dotted line A3-A4 in Figure 3A.
  • Figure 3D is a cross-sectional view taken along dashed dotted line A5-A6 in Figures 3B and 3C.
  • the semiconductor device shown in Figures 3A to 3D differs from the semiconductor device shown in Figures 1A to 1D in the shapes of conductive layer 260 and conductive layer 263.
  • differences from the above content will be mainly described, and overlapping parts will be referred to and may not be described.
  • the height of the upper surface of the conductive layer 260 and the height of the upper surface of the insulating layer 250 are the same or approximately the same. Also, in FIGS. 1B and 1C, a part of the conductive layer 263 is located within the opening 290, but in FIGS. 3B and 3C, the conductive layer 263 is not located within the opening 290, and the lower surface of the conductive layer 263 is located above the upper surface of the conductive layer 240.
  • conductive layer 260 is not located on conductive layer 240, so that the parasitic capacitance between conductive layer 240 and conductive layer 260 can be reduced.
  • the maximum width of conductive layer 260 is the width Dc of the upper surface of conductive layer 260. This width Dc is set to be equal to or smaller than the width D of opening 290. In this way, if the maximum width of conductive layer 260 is equal to or smaller than the width D of opening 290, the parasitic capacitance between conductive layer 260 and conductive layer 240 can be reduced, which is preferable.
  • the width Db of the opening 270 is smaller than the width D of the opening 290. In this way, when the width Db is smaller than the width D, the parasitic capacitance between the conductive layer 263 and the conductive layer 240 can be reduced, which is preferable.
  • the conductive layer 260 is electrically connected to the conductive layer 265 provided on the insulating layer 285 via the conductive layer 263.
  • the conductive layer 265 is in contact with the upper surface of the conductive layer 263.
  • Insulating layer 283 and insulating layer 285 are located between conductive layer 265 and conductive layer 240. This allows the physical distance between conductive layer 265 and conductive layer 240 to be increased, and the parasitic capacitance between conductive layer 265 and conductive layer 240 to be reduced.
  • Fig. 4A is a plan view of a semiconductor device including a transistor 200C.
  • Fig. 4B is a cross-sectional view taken along dash-dotted line A1-A2 in Fig. 4A.
  • Fig. 4C is a cross-sectional view taken along dash-dotted line A3-A4 in Fig. 4A.
  • Fig. 4D is a cross-sectional view taken along dash-dotted line A5-A6 in Figs. 4B and 4C.
  • Fig. 4D can also be regarded as a cross-sectional view in the XY plane including the insulating layer 280b and the channel formation region of the oxide semiconductor layer 230.
  • the semiconductor device shown in Figures 4A to 4D differs from the semiconductor device shown in Figures 1A to 1D in that it has an insulating layer 222 and that the insulating layer 280 has a three-layer structure.
  • an insulating layer 222 is provided on an insulating layer 210, and a conductive layer 220 and an insulating layer 280 are provided on the insulating layer 222.
  • the insulating layer 222 is preferably an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen in the oxide semiconductor layer 230 to diffuse to the insulating layer 222 through the conductive layer 220, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.
  • a silicon nitride film as the insulating layer 210 and an oxide film containing hafnium and silicon (hafnium silicate film) as the insulating layer 222.
  • the insulating layer 280 has an insulating layer 280a, an insulating layer 280b on the insulating layer 280a, and an insulating layer 280c on the insulating layer 280b.
  • the insulating layer 280a has a region in contact with the upper surface of the insulating layer 222, a region in contact with the side surface of the conductive layer 220, and a region in contact with the upper surface of the conductive layer 220.
  • the insulating layer 280c has a region in contact with the lower surface of the conductive layer 240.
  • the insulating layer 280b is a layer that is in contact with the channel formation region of the oxide semiconductor layer 230.
  • oxygen can be supplied to the oxide semiconductor layer 230.
  • the insulating layer 280b preferably has a region with a higher oxygen content than at least one of the insulating layer 280a and the insulating layer 280c.
  • the insulating layer 280b preferably has a region with a higher oxygen content than each of the insulating layer 280a and the insulating layer 280c.
  • a film that releases oxygen by heating for the insulating layer 280b.
  • oxygen can be supplied to the oxide semiconductor layer 230.
  • oxygen is supplied from the insulating layer 280b to the oxide semiconductor layer 230, particularly to a channel formation region of the oxide semiconductor layer 230, oxygen vacancies and VOH in the oxide semiconductor layer 230 can be reduced, and a transistor with good electrical characteristics and high reliability can be obtained.
  • the amount of released oxygen molecules from the insulating layer 280b is preferably greater than or equal to 1.0 ⁇ 10 14 molecules/cm 2 and less than 1.0 ⁇ 10 15 molecules/cm 2. Note that the amount of released oxygen molecules can be measured by thermal desorption spectrometry.
  • the channel length of the transistor 200B when the channel length of the transistor 200B is short, the influence of oxygen vacancies in the channel formation region and VOH on the electrical characteristics and reliability becomes particularly large. Therefore, by sufficiently reducing the hydrogen concentration in the oxide semiconductor layer 230 and then optimizing the amount of oxygen supplied to the oxide semiconductor layer 230, a transistor with a short channel length having favorable electrical characteristics and high reliability can be realized.
  • the insulating layer 280b is preferably formed by a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • hydrogen gas is not required as a deposition gas, and therefore a film with an extremely low hydrogen content can be obtained. This can suppress the supply of hydrogen to the oxide semiconductor layer 230, and stabilize the electrical characteristics of the transistor 200B.
  • oxygen supplied to the oxide semiconductor layer 230 is increased, for example, after the insulating layer 280b is formed, heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere may be performed.
  • oxygen may be supplied by forming an oxide film in an oxygen atmosphere on the upper surface of the insulating layer 280b by a sputtering method. The oxide film may then be removed. By performing such treatment, oxygen can be supplied to the insulating layer 280b, and the amount of oxygen supplied to the oxide semiconductor layer 230 can be increased.
  • the amount of oxygen supplied to the region of the oxide semiconductor layer 230 in contact with the insulating layer 280a and the region in contact with the insulating layer 280c is smaller than that in contact with the insulating layer 280b. Therefore, the region of the oxide semiconductor layer 230 in contact with the insulating layer 280a and the region in contact with the insulating layer 280c may have low resistance.
  • the thickness of the insulating layer 280a the range of the region that functions as one of the source region and the drain region can be controlled.
  • the thickness of the insulating layer 280c the range of the region that functions as the other of the source region and the drain region can be controlled. In this way, the thicknesses of the insulating layers 280a and 280c can be appropriately set according to the characteristics required for the transistor.
  • the insulating layer 280b it is preferable to use a material with a low dielectric constant for the insulating layer 280b. This can reduce the parasitic capacitance that occurs between the wiring.
  • silicon oxide or silicon oxynitride can be used as the insulating layer 280b.
  • a barrier insulating layer against oxygen for each of the insulating layer 280a and the insulating layer 280c.
  • the insulating layer 280a between the insulating layer 280b and the conductive layer 220, it is possible to prevent the conductive layer 220 from being oxidized and the resistance of the conductive layer 220 from increasing.
  • the insulating layer 280c between the insulating layer 280b and the conductive layer 240, it is possible to prevent the conductive layer 240 from being oxidized and the resistance of the conductive layer 240 from increasing.
  • an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 280a.
  • the insulating layer 280a magnesium oxide, aluminum oxide, hafnium oxide, or an oxide containing hafnium and silicon, etc. may be used.
  • a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulating layer 280a.
  • an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 280c.
  • insulating layer 280a and insulating layer 280c can be made of silicon nitride, and insulating layer 280b can be made of silicon oxide.
  • Figures 5A, 5B, and 5E are cross-sectional views of a semiconductor device having a transistor 200D.
  • Figures 5C, 5D, and 5F are cross-sectional views of a semiconductor device having a transistor 200E.
  • a plan view of a semiconductor device having a transistor 200D or a transistor 200E is similar to a plan view of a semiconductor device having a transistor 200C. That is, Figures 5A and 5C correspond to cross-sectional views taken along dashed lines A1-A2 in Figure 4A, and Figures 5B and 5D correspond to cross-sectional views taken along dashed lines A3-A4 in Figure 4A.
  • Figure 5E is a cross-sectional view taken along dashed lines A5-A6 in Figures 5A and 5B.
  • Figure 5F is a cross-sectional view taken along dashed lines A5-A6 in Figures 5C and 5D.
  • 5E and 5F can also be considered as cross-sectional views in the XY plane including the channel formation regions of the insulating layer 280 and the oxide semiconductor layer 230, respectively.
  • the semiconductor device shown in Figures 5A, 5B, and 5E differs from the semiconductor device shown in Figures 1A to 1D in that it has an insulating layer 223.
  • the semiconductor device shown in Figures 5A, 5B, and 5E has a configuration in which an insulating layer 223, an oxide semiconductor layer 230, an insulating layer 250, and a conductive layer 260 are provided in this order inside an opening in an insulating layer 280.
  • the insulating layer 223 is provided between the insulating layer 280 and the oxide semiconductor layer 230.
  • the insulating layer 223 is provided so as to cover the sidewall of the opening 290
  • the oxide semiconductor layer 230 is provided so as to cover the side surface of the insulating layer 223 and the bottom of the opening 290
  • the insulating layer 250 is provided so as to cover the oxide semiconductor layer 230
  • the conductive layer 260 is provided so as to fill the recess of the insulating layer 250 that reflects the shape of the opening 290.
  • the insulating layer 223 is preferably an insulating layer having a function of capturing or fixing hydrogen. This allows a structure in which the oxide semiconductor layer 230 is sandwiched between insulating layers (here, the insulating layer 250 and the insulating layer 223) having a function of capturing or fixing hydrogen, and a barrier insulating layer against hydrogen (here, the insulating layer 280) is provided on the outside. With this structure, diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed, and the hydrogen concentration in the oxide semiconductor layer 230 can be further reduced.
  • the semiconductor device shown in Figures 5C, 5D, and 5F differs from the semiconductor device shown in Figures 1A to 1D in that it has insulating layers 221 and 223.
  • the semiconductor device shown in Figures 5C, 5D, and 5F has a configuration in which an insulating layer 221, an insulating layer 223, an oxide semiconductor layer 230, an insulating layer 250, and a conductive layer 260 are provided in this order inside an opening in an insulating layer 280.
  • the insulating layer 221 and the insulating layer 223 are provided between the insulating layer 280 and the oxide semiconductor layer 230.
  • the insulating layer 221 is provided so as to cover the side wall of the opening 290
  • the insulating layer 223 is provided so as to cover the side surface of the insulating layer 221
  • the oxide semiconductor layer 230 is provided so as to cover the side surface of the insulating layer 223 and the bottom of the opening 290
  • the insulating layer 250 is provided so as to cover the oxide semiconductor layer 230
  • the conductive layer 260 is provided so as to fill the recess of the insulating layer 250 that reflects the shape of the opening 290.
  • the insulating layer 221 is preferably a barrier insulating layer against hydrogen.
  • the insulating layer 223 is preferably an insulating layer having a function of capturing or fixing hydrogen. This allows the oxide semiconductor layer 230 to be sandwiched between insulating layers (here, the insulating layer 250 and the insulating layer 223) having a function of capturing or fixing hydrogen, and a barrier insulating layer against hydrogen (here, the insulating layer 221) is provided on the outside of the insulating layers. With this structure, the diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed, and the hydrogen concentration in the oxide semiconductor layer 230 can be further reduced.
  • the insulating layer 280 since the insulating layer 221 has a barrier property against hydrogen, the insulating layer 280 does not need to have a barrier property against hydrogen, and there is a wide range of material choices.
  • a material with a low relative dielectric constant may be used as the insulating layer 280.
  • the parasitic capacitance that occurs between wirings can be reduced.
  • the insulating layer 280 is shown as a single layer in Figures 5C, 5D, and 5F, the insulating layer 280 may have a laminated structure.
  • the transistor shown in FIG. 6A differs from the transistor 200B shown in FIG. 3B in that it does not have a conductive layer 263.
  • the transistor shown in FIG. 6B also differs from the transistor 200A shown in FIG. 1B in that it does not have a conductive layer 263.
  • the conductive layer 260 and the conductive layer 265 may be directly connected without providing the conductive layer 263.
  • the conductive layer 265 has both a portion located within the opening 270 provided in the insulating layer 283 and the insulating layer 285, and a portion in contact with the upper surface of the insulating layer 285.
  • the conductive layer 265 contacts the upper surface of the conductive layer 260 within the opening 270. Even with this configuration, the physical distance between the conductive layer 265 and the conductive layer 240 can be increased, and the parasitic capacitance between the conductive layer 265 and the conductive layer 240 can be reduced.
  • the width Db of the opening 270 may be equal to or approximately equal to the width D of the opening 290. Note that, as shown in FIG. 1B and other figures, configurations in which the width Db is smaller than the width D are more preferable than those in FIG. 6C because they can reduce the parasitic capacitance between the low resistance region of the oxide semiconductor layer 230 and the conductive layer 263.
  • the sidewalls of the opening 290 provided in the insulating layer 280 and the conductive layer 240 may be tapered.
  • the maximum width of the conductive layer 260 is the width Dc of the upper surface of the conductive layer 260.
  • the width Dc is smaller than the width D, which is the minimum width of the opening 290 provided in the conductive layer 240.
  • the width Db of the opening 270 provided in the insulating layer 283 and the insulating layer 285 can be equal to or smaller than the width D. In this way, even if the sidewalls of the opening 290 are tapered, a semiconductor device having a configuration with reduced parasitic capacitance can be manufactured.
  • FIG. 1B and other figures show an example in which the width Db of the opening 270 provided in the insulating layer 283 and the insulating layer 285 is larger than the maximum width (width Da) of the conductive layer 260, but this is not limited to the example.
  • the width Db may be smaller than the width Da. That is, in a cross-sectional view, the maximum width of the conductive layer 260 may be larger or smaller than the maximum width of the conductive layer 263, or may be the same or approximately the same.
  • the transistor may also have a back gate. Having a back gate makes it easier to control the threshold voltage and suppresses fluctuations in the threshold voltage, thereby improving the electrical characteristics and reliability of the transistor.
  • the semiconductor device shown in FIG. 6F has an insulating layer 210 on a substrate (not shown), a transistor on the insulating layer 210, an insulating layer 280a on the insulating layer 210, an insulating layer 280b on the insulating layer 280a, an insulating layer 283 on the transistor, an insulating layer 285 on the insulating layer 283, a conductive layer 263 located in an opening 270 provided in the insulating layer 283 and the insulating layer 285, and a conductive layer 265 on the insulating layer 285.
  • the insulating layer 210, the insulating layer 280a, the insulating layer 280b, the insulating layer 283, and the insulating layer 285 function as interlayer films.
  • the transistor shown in FIG. 6F has a conductive layer 220, a conductive layer 255 on the insulating layer 280a, a conductive layer 240 on the insulating layer 280b, an insulating layer 223 in contact with the side surfaces of the insulating layer 280a, the side surfaces of the conductive layer 255, and the side surfaces of the insulating layer 280b, an oxide semiconductor layer 230 in contact with the top surface of the conductive layer 220, the side surfaces of the insulating layer 223, and the top surface of the conductive layer 240, an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.
  • the oxide semiconductor layer 230 functions as a semiconductor layer
  • the conductive layer 260 functions as a first gate electrode
  • the insulating layer 250 functions as a first gate insulating layer
  • the conductive layer 255 functions as a second gate electrode
  • the insulating layer 223 functions as a second gate insulating layer
  • the conductive layer 220 functions as one of the source electrode and the drain electrode
  • the conductive layer 240 functions as the other of the source electrode and the drain electrode.
  • the conductive layer 265 functions as a gate wiring.
  • an opening 290 is provided in insulating layer 280a, conductive layer 255, insulating layer 280b, and conductive layer 240, reaching conductive layer 220.
  • the bottom of opening 290 is the upper surface of conductive layer 220
  • the sidewalls of opening 290 are the side surface of insulating layer 280a, the side surface of conductive layer 255, the side surface of insulating layer 280b, and the side surface of conductive layer 240.
  • At least some of the components of the transistor are disposed within the opening 290.
  • the insulating layer 223, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are disposed such that at least some of them are located within the opening 290.
  • the insulating layer 223 contacts the upper surface of the conductive layer 220, the side of the insulating layer 280a, the side of the conductive layer 255, the side of the insulating layer 280b, and the side of the conductive layer 240 within the opening 290.
  • the oxide semiconductor layer 230 contacts the upper surface of the conductive layer 220 within the opening 290.
  • the conductive layer 255 can be made of a material that can be used for the conductive layer 260.
  • the insulating layer 223 can be made of a material that can be used for the insulating layer 250.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, CVD, vacuum deposition, PLD, and ALD.
  • Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner.
  • RF sputtering is mainly used when depositing insulating films
  • DC sputtering is mainly used when depositing metal conductive films.
  • Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.
  • CVD methods can also be classified into plasma CVD (PECVD) methods, which use plasma, thermal CVD (TCVD: Thermal CVD) methods, which use heat, and photo CVD (Photo CVD) methods, which use light. They can also be further divided into metal CVD (MCVD: Metal CVD) methods and metal organic CVD (MOCVD: Metal CVD) methods, depending on the source gas used.
  • PECVD plasma CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal CVD
  • the plasma CVD method can produce high-quality films at relatively low temperatures.
  • the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma.
  • wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device.
  • thermal CVD which does not use plasma, such plasma damage does not occur, so the yield of semiconductor devices can be increased.
  • no plasma damage occurs during film formation, so films with fewer defects can be obtained.
  • the ALD method can be a thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy, or a PEALD method in which a plasma-excited reactant is used.
  • the CVD and ALD methods are different from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios.
  • the ALD method since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.
  • the CVD method can form a film of any composition by adjusting the flow rate ratio of the source gases.
  • the CVD method can form a film whose composition changes continuously by changing the flow rate ratio of the source gases while forming the film.
  • the time required for film formation can be shortened compared to forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.
  • a film of any composition can be formed by simultaneously introducing multiple different types of precursors.
  • a film of any composition can be formed by controlling the number of cycles of each precursor.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by wet film formation methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • the thin film when processing the thin film that constitutes the semiconductor device, a photolithography method or the like can be used.
  • the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like.
  • an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these.
  • ultraviolet light, KrF laser light, ArF laser light, etc. can also be used.
  • Exposure can also be performed by immersion exposure technology.
  • Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure.
  • Electron beams can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.
  • Dry etching, wet etching, sandblasting, etc. can be used to etch thin films.
  • a conductive layer 220 is formed on an insulating layer 210, an insulating layer 280 is formed on the conductive layer 220, and a conductive layer 240 is formed on the insulating layer 280.
  • planarization treatment also referred to as a CMP treatment
  • CMP chemical mechanical polishing
  • an opening 290 is formed in the conductive layer 240 and the insulating layer 280 at a position where the conductive layer 220 overlaps.
  • the opening 290 has a large aspect ratio, it is preferable to process a part of the conductive layer 240 and a part of the insulating layer 280 using anisotropic etching. In particular, processing by dry etching is preferable because it is suitable for fine processing. Different processing conditions may be used depending on the layer. Note that, depending on the processing conditions of the conductive layer 240 and the insulating layer 280, the inclination of the side surface of the conductive layer 240 and the inclination of the side surface of the insulating layer 280 within the opening 290 may differ from each other.
  • the heat treatment is performed, for example, at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • an atmosphere of nitrogen gas or an inert gas or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less.
  • an oxide semiconductor layer 230 is formed to cover the opening 290.
  • the oxide semiconductor layer 230 is provided in contact with the upper surface of the conductive layer 220, the side surface of the insulating layer 280, and the upper surface and side surface of the conductive layer 240.
  • the oxide semiconductor layer 230 can be formed, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the oxide semiconductor layer 230 is preferably formed as a film of as uniform thickness as possible within the opening 290 along the top surface of the conductive layer 220, the side surface of the insulating layer 280, and the side surface of the conductive layer 240.
  • a thin film can be formed with good controllability. Therefore, it is preferable to form the oxide semiconductor layer 230 using the ALD method.
  • the oxide semiconductor layer 230 has high crystallinity, the diffusion of impurities in the oxide semiconductor layer 230 is suppressed, so that the electrical characteristics of the transistor are less likely to fluctuate and the reliability can be improved.
  • the oxide semiconductor layer 230 is formed by a sputtering method, it is easier to form a layer with high crystallinity than when an ALD method is used, which is preferable.
  • the oxide semiconductor layer 230 is formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a noble gas is used as a sputtering gas.
  • the amount of excess oxygen in the oxide film to be formed can be increased.
  • an In-M-Zn oxide target or the like can be used.
  • an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and not more than 100%, preferably 70% to 100%.
  • a transistor using an oxygen-excessive oxide semiconductor in a channel formation region can have relatively high reliability.
  • one embodiment of the present invention is not limited thereto.
  • An oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%, when the oxide semiconductor layer 230 is formed.
  • a transistor using an oxygen-deficient oxide semiconductor in a channel formation region can have relatively high field-effect mobility.
  • the crystallinity of the oxide semiconductor layer can be improved by performing film formation while heating the substrate.
  • the heat treatment is preferably performed in a temperature range in which the oxide semiconductor layer 230 does not become polycrystallized.
  • the temperature of the heat treatment is preferably 100° C. or higher and 650° C. or lower, more preferably 250° C. or higher and 600° C. or lower, and even more preferably 350° C. or higher and 550° C. or lower.
  • the gas used in the heat treatment is preferably highly purified. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor layer 230 as much as possible.
  • the heat treatment is performed at a temperature of 450° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas of 4:1.
  • heat treatment including oxygen gas, impurities such as carbon, water, and hydrogen in the oxide semiconductor layer 230 can be reduced.
  • impurities in the film By reducing the impurities in the film in this way, the crystallinity of the oxide semiconductor layer 230 can be improved, and a denser and more compact structure can be obtained.
  • This increases the crystalline region in the oxide semiconductor layer 230, and reduces the in-plane variation of the crystalline region in the oxide semiconductor layer 230. Therefore, the in-plane variation of the electrical characteristics of the transistor can be reduced.
  • the insulating layer 280 contains oxygen
  • an insulating layer 250 is formed on the oxide semiconductor layer 230, and a conductive layer 260 is formed on the insulating layer 250.
  • the insulating layer 250 is formed in contact with the oxide semiconductor layer 230 provided in the opening 290 with a large aspect ratio. Therefore, it is preferable to form the insulating layer 250 using a film formation method with good coverage, and it is more preferable to use a CVD method or an ALD method.
  • the conductive layer 260 is formed in contact with the insulating layer 250 provided in the opening 290 with a large aspect ratio. Therefore, it is preferable to form the conductive layer 260 using a film formation method with good coverage, and it is more preferable to use a CVD method or an ALD method.
  • anisotropic etching is used to remove the portion of conductive layer 260 that overlaps with the upper surface of conductive layer 240. As shown in FIG. 7D, conductive layer 260 is processed so that both ends of its upper surface are located within opening 290. Note that before anisotropic etching is performed, a CMP process may be performed to flatten the upper surface of conductive layer 260. This is preferable as it increases the flatness of the upper surface of conductive layer 260.
  • anisotropic etching By using anisotropic etching to remove the portion of conductive layer 260 that overlaps with the upper surface of conductive layer 240, it becomes easier to selectively etch conductive layer 260, and removal of insulating layer 250 can be suppressed.
  • the conductive layer 260 does not overlap the upper surface of the conductive layer 240. This makes it possible to suppress the occurrence of parasitic capacitance between the conductive layer 260 and the conductive layer 240.
  • the insulating layer 250, the oxide semiconductor layer 230, and the conductive layer 240 are processed into an island shape, and a part of the upper surface of the insulating layer 280 is exposed.
  • the insulating layer 250, the oxide semiconductor layer 230, and the conductive layer 240 can be processed using the same mask. This is preferable because it reduces the number of masks required to manufacture a semiconductor device.
  • an insulating layer 283 is formed on the insulating layer 280, the insulating layer 250, and the conductive layer 260, and an insulating layer 285 is formed on the insulating layer 283. Then, the upper surface of the insulating layer 285 is planarized by performing a CMP process (FIG. 7F).
  • a resist mask 289 is formed on the insulating layer 285. Then, using the resist mask 289, an opening 270 is formed in the insulating layer 283 and the insulating layer 285, reaching the conductive layer 260. At this time, as shown in FIG. 8A1, a part of the insulating layer 283 (sidewall 283a) may remain on the conductive layer 260. For example, when the insulating layer 283 is formed using a film formation method with high coverage (such as an ALD method), the sidewall 283a may remain. Also, as shown in FIG. 8A2, the insulating layer 283 may not remain on the conductive layer 260.
  • the width of the opening in resist mask 289 is preferably smaller than the width of opening 290. This allows the overlap between conductive layer 260 and conductive layer 240 to be reduced, and the occurrence of parasitic capacitance between conductive layer 260 and conductive layer 240 to be suppressed.
  • a conductive layer 263 is formed on the insulating layer 285 and in the opening 270 (FIG. 8B), and a CMP process is performed to remove the portion of the conductive layer 263 that overlaps with the upper surface of the insulating layer 285 (FIG. 8C).
  • the conductive layer 263 can be formed in the insulating layer 283 and the opening provided in the insulating layer 285.
  • the height of the upper surface of the insulating layer 285 and the height of the upper surface of the conductive layer 263 are the same.
  • one of the height of the upper surface of the insulating layer 285 and the height of the upper surface of the conductive layer 263 may be higher than the other.
  • the vertical relationship between the heights of the upper surfaces of the two layers can be controlled by the difference in the polishing rates of the materials of the insulating layer 285 and the conductive layer 263.
  • the width Db of the opening 270 provided in the insulating layer 283 and the insulating layer 285 is smaller than the width D of the opening 290, and the conductive layer 263 is not located on the conductive layer 240. Therefore, the parasitic capacitance between the conductive layer 263 and the conductive layer 240 can be reduced.
  • the region of the oxide semiconductor layer 230 in contact with the conductive layer 240 may function as a low-resistance region.
  • the conductive layer 263 is not located on the region of the oxide semiconductor layer 230 in contact with the conductive layer 240, so that the parasitic capacitance between the low-resistance region of the oxide semiconductor layer 230 and the conductive layer 263 can also be reduced.
  • FIG. 8D1 shows an example in which a sidewall 283a is located on the conductive layer 260
  • FIG. 8D2 shows an example in which a sidewall 283a does not remain on the conductive layer 260.
  • An insulating layer 283 and an insulating layer 285 are located between the conductive layer 265 and the conductive layer 240. This allows the physical distance between the conductive layer 265 and the conductive layer 240 to be increased, and the parasitic capacitance between the conductive layer 265 and the conductive layer 240 to be reduced.
  • a semiconductor device according to one embodiment of the present invention can be manufactured.
  • Example of manufacturing method of configuration example 2 A manufacturing method example of the above-described semiconductor device according to the second structural example (see FIGS. 3A to 3D) will be described with reference to FIGS. 9A to 9F. Note that detailed description of the same parts as those in the manufacturing method example of the first structural example will be omitted in some cases.
  • a conductive layer 220 is formed on an insulating layer 210, and an insulating layer 280 is formed on the conductive layer 220.
  • the upper surface of the insulating layer 280 is planarized by CMP processing.
  • CMP processing By planarizing the upper surface of the insulating layer 280 by CMP processing here, it is possible to prevent the conductive layer 260 from remaining in unnecessary locations when CMP processing is performed on the conductive layer 260 in a later process.
  • a conductive layer 240 is formed in contact with the upper surface of the planarized insulating layer 280 ( Figure 9A).
  • an opening 290 is formed in the conductive layer 240 and the insulating layer 280 at a position where the conductive layer 220 overlaps.
  • a heat treatment may be performed after the formation of the opening 290.
  • an oxide semiconductor layer 230 is formed so as to cover the opening 290, an insulating layer 250 is formed on the oxide semiconductor layer 230, and a conductive layer 260 is formed on the insulating layer 250.
  • a CMP process is performed to remove the portion of the conductive layer 260 that overlaps with the upper surface of the conductive layer 240.
  • the conductive layer 260 is processed so that the maximum width (here, this corresponds to the width Dc of the upper surface of the conductive layer 260) is equal to or smaller than the width D of the opening 290.
  • a CMP process may be performed to flatten the upper surface of the conductive layer 260. This is preferable because the flatness of the upper surface of the conductive layer 260 is high even after performing anisotropic etching.
  • the conductive layer 260 does not overlap the upper surface of the conductive layer 240. This makes it possible to suppress the occurrence of parasitic capacitance between the conductive layer 260 and the conductive layer 240.
  • the insulating layer 250, the oxide semiconductor layer 230, and the conductive layer 240 are processed into an island shape, and a part of the upper surface of the insulating layer 280 is exposed.
  • the insulating layer 250, the oxide semiconductor layer 230, and the conductive layer 240 can be processed using the same mask. This is preferable because it reduces the number of masks required to manufacture a semiconductor device.
  • an insulating layer 283 is formed on the insulating layer 280, the insulating layer 250, and the conductive layer 260, and an insulating layer 285 is formed on the insulating layer 283.
  • the upper surface of the insulating layer 285 is planarized by performing a CMP process, and then an opening 270 is formed in the insulating layer 283 and the insulating layer 285, reaching the conductive layer 260.
  • a conductive layer 263 is formed on the insulating layer 285 and in the opening 270, and a CMP process is performed to remove the portion of the conductive layer 263 that overlaps with the upper surface of the insulating layer 285. As a result, the conductive layer 263 can be formed in the opening 270, as shown in FIG. 9F.
  • the width Db of the opening 270 is smaller than the width D of the opening 290, and the conductive layer 263 is not located on the conductive layer 240. Therefore, the parasitic capacitance between the conductive layer 263 and the conductive layer 240 can be reduced, which is preferable.
  • conductive layer 265 is formed on conductive layer 263 and insulating layer 285. Insulating layer 283 and insulating layer 285 are located between conductive layer 265 and conductive layer 240. This allows the physical distance between conductive layer 265 and conductive layer 240 to be increased, and the parasitic capacitance between conductive layer 265 and conductive layer 240 to be reduced.
  • a semiconductor device according to one embodiment of the present invention can be manufactured.
  • the semiconductor device of this embodiment has a configuration in which the parasitic capacitance between the source electrode or drain electrode and the gate electrode, and the parasitic capacitance between the source electrode or drain electrode and the gate wiring are reduced. Therefore, the frequency characteristics of the circuit can be improved.
  • the memory device of one embodiment of the present invention includes a memory cell.
  • the memory cell includes a transistor and a capacitor.
  • Fig. 10A is a plan view of a memory device including a transistor 200A and a capacitor 100.
  • Fig. 10B is a cross-sectional view taken along dashed line A1-A2 in Fig. 10A.
  • Fig. 10C is a cross-sectional view taken along dashed line A3-A4 in Fig. 10A.
  • 10A to 10C includes an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a memory cell 150 on the conductive layer 110, an insulating layer 180 on the conductive layer 110, an insulating layer 280, an insulating layer 283 on the memory cell 150, an insulating layer 285 on the insulating layer 283, a conductive layer 263 embedded in the insulating layer 283 and the insulating layer 285, and a conductive layer 265 on the insulating layer 285.
  • the insulating layer 140, the insulating layer 180, the insulating layer 280, the insulating layer 283, and the insulating layer 285 function as interlayer films.
  • the conductive layer 110 and the conductive layer 265 function as wiring.
  • the conductive layer 263 has a function of electrically connecting the conductive layer 265 to the conductive layer 260 of the memory cell 150.
  • the memory cell 150 has a capacitor element 100 on a conductive layer 110 and a transistor 200A on the capacitor element 100.
  • the capacitance element 100 has a conductive layer 115 on the conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 120 on the insulating layer 130.
  • the conductive layer 120 functions as one of a pair of electrodes (sometimes called an upper electrode)
  • the conductive layer 115 functions as the other of the pair of electrodes (sometimes called a lower electrode)
  • the insulating layer 130 functions as a dielectric.
  • the capacitance element 100 constitutes a MIM (Metal-Insulator-Metal) capacitance.
  • the insulating layer 180 has an opening 190 that reaches the conductive layer 110. At least a portion of the conductive layer 115 is disposed in the opening 190.
  • the conductive layer 115 has a region in contact with the upper surface of the conductive layer 110 in the opening 190, a region in contact with the side surface of the insulating layer 180 in the opening 190, and a region in contact with at least a portion of the upper surface of the insulating layer 180.
  • the insulating layer 130 is disposed so that at least a portion of it is located in the opening 190.
  • the conductive layer 120 is disposed so that at least a portion of it is located in the opening 190. As shown in FIG.
  • the conductive layer 120 is preferably disposed so as to fill the opening 190.
  • the films disposed inside the opening 190 are preferably formed using the ALD method. This improves the coverage of the film.
  • the conductive layer 115, the insulating layer 130, and the conductive layer 120 are each formed using the ALD method.
  • the capacitive element 100 is configured such that the upper electrode and the lower electrode face each other with a dielectric between them, not only on the bottom surface but also on the side surfaces, allowing the capacitance per unit area to be increased. Therefore, the deeper the opening 190, the greater the capacitance of the capacitive element 100 can be. Increasing the capacitance per unit area of the capacitive element 100 in this way can stabilize the read operation of the memory device. It can also promote miniaturization or high integration of memory devices.
  • FIGS. 10B and 10C show an example in which the sidewall of the opening 190 is perpendicular to the upper surface of the conductive layer 110.
  • the opening 190 has a cylindrical shape.
  • a conductive layer 115 and an insulating layer 130 are laminated along the sidewall of the opening 190 and the upper surface of the conductive layer 110.
  • a conductive layer 120 is provided on the insulating layer 130 so as to fill the opening 190.
  • a capacitance element 100 having such a configuration may be called a trench type capacitance or a trench capacitance.
  • An insulating layer 280 is disposed on the capacitance element 100. That is, the insulating layer 280 is disposed on the conductive layer 115, the insulating layer 130, and the conductive layer 120. In other words, the conductive layer 120 is disposed below the insulating layer 280.
  • Transistor 200A has a conductive layer 120 (corresponding to conductive layer 220 in FIG. 1B, etc.), a conductive layer 240 on an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.
  • the oxide semiconductor layer 230 functions as a semiconductor layer
  • the conductive layer 260 functions as a gate electrode
  • the insulating layer 250 functions as a gate insulating layer
  • the conductive layer 120 functions as one of a source electrode and a drain electrode
  • the conductive layer 240 functions as the other of the source electrode and the drain electrode.
  • transistor 200A the description in embodiment 1 (FIGS. 1 and 2) can be referred to, and detailed description will be omitted.
  • the transistor in memory cell 150 is not limited to transistor 200A, and each of the transistors exemplified in embodiment 1 can be applied.
  • the transistor 200A is provided so as to overlap with the capacitor 100.
  • the opening 290 in which part of the structure of the transistor 200A is provided has an area overlapping with the opening 190 in which part of the structure of the capacitor 100 is provided.
  • the conductive layer 120 functions as one of the source electrode and drain electrode of the transistor 200A and as the upper electrode of the capacitor 100, so that the transistor 200A and the capacitor 100 share part of their structures.
  • the transistor 200A and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of the memory cell 150, so that the memory cells 150 can be arranged at a high density, and the memory capacity of the memory device can be increased. In other words, the memory device can be highly integrated.
  • the transistor 200A is not subjected to the thermal history during the manufacture of the capacitor 100. Therefore, in the transistor 200A, it is possible to suppress the deterioration of electrical characteristics such as fluctuations in threshold voltage and increases in parasitic resistance, as well as the increase in variation in electrical characteristics due to the deterioration of electrical characteristics.
  • FIG. 15A A circuit diagram of the memory device shown in this embodiment is shown in FIG. 15A.
  • the configuration shown in FIG. 10A to FIG. 10C functions as a memory cell.
  • the memory cell 951 has a transistor M1 and a capacitor CA.
  • the transistor M1 corresponds to the transistor 200A
  • the capacitor CA corresponds to the capacitor 100.
  • One of the source and drain of transistor M1 is connected to one of a pair of electrodes of capacitance element CA.
  • the other of the source and drain of transistor M1 is connected to wiring BIL.
  • the gate of transistor M1 is connected to wiring WOL.
  • the other of the pair of electrodes of capacitance element CA is connected to wiring CAL.
  • the wiring BIL corresponds to the conductive layer 240
  • the wiring WOL corresponds to the conductive layer 265
  • the wiring CAL corresponds to the conductive layer 110.
  • the conductive layer 265 is provided extending in the X direction
  • the conductive layer 240 is provided extending in the Y direction.
  • the wiring BIL and the wiring WOL are provided crossing each other.
  • the wiring CAL (conductive layer 110) is provided in a planar shape, but the present invention is not limited to this.
  • the wiring CAL may be provided parallel to the wiring WOL (conductive layer 265) or parallel to the wiring BIL (conductive layer 240).
  • the capacitor 100 includes a conductive layer 115, an insulating layer 130, and a conductive layer 120.
  • a conductive layer 110 is provided under the conductive layer 115.
  • the conductive layer 115 has a region in contact with the conductive layer 110.
  • the conductive layer 110 is provided on the insulating layer 140.
  • the conductive layer 110 functions as a wiring CAL and can be provided in a planar shape, for example.
  • the conductive layer 110 can be formed as a single layer or a stacked layer using the conductive material described in the [Conductive Layer] section of Embodiment 1.
  • a conductive material with high conductivity such as tungsten, can be used as the conductive layer 110.
  • the conductivity of the conductive layer 110 can be improved and the conductive layer 110 can function sufficiently as a wiring CAL.
  • the conductive layer 115 is preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen, in a single layer or a laminated layer.
  • a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen in a single layer or a laminated layer.
  • titanium nitride or indium tin oxide with added silicon may be used.
  • tungsten Alternatively, for example, a structure in which titanium nitride is laminated on tungsten may be used.
  • a structure in which tungsten is laminated on a first titanium nitride, and a second titanium nitride is laminated on the tungsten may be used.
  • the insulating layer 130 when an oxide is used for the insulating layer 130, the insulating layer 130 can suppress the conductive layer 110 from being oxidized. Furthermore, when an oxide is used for the insulating layer 180, the insulating layer 180 can suppress the conductive layer 110 from being oxidized.
  • the insulating layer 130 is provided on the conductive layer 115.
  • the insulating layer 130 is provided so as to contact the upper surface and side surfaces of the conductive layer 115.
  • the insulating layer 130 has a structure that covers the side end portion of the conductive layer 110. This can prevent the conductive layer 115 and the conductive layer 120 from shorting out.
  • the side end of the insulating layer 130 and the side end of the conductive layer 115 may be aligned.
  • the insulating layer 130 and the conductive layer 115 can be formed using the same mask, and the manufacturing process of the memory device can be simplified.
  • the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitance element 100 can be sufficiently ensured.
  • the insulating layer 130 is preferably made of a high-k material and is preferably a laminated structure of a high dielectric constant (high-k) material and a material having a higher dielectric strength than the high-k material.
  • the insulating layer 130 may be an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide.
  • the insulating film may be laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide.
  • the insulating film may be laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide.
  • a material that can have ferroelectricity may be used as the insulating layer 130.
  • materials that can have ferroelectricity please refer to the description of embodiment 1.
  • Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when the thickness is a few nm, and are therefore preferred as the insulating layer 130.
  • the thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm to 9 nm). For example, the thickness is preferably 8 nm to 12 nm.
  • a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130.
  • the ferroelectricity can be maintained even if the area (occupied area) of the ferroelectric layer in a plan view is 100 ⁇ m 2 or less, 10 ⁇ m 2 or less, 1 ⁇ m 2 or less, or 0.1 ⁇ m 2 or less.
  • the ferroelectricity even if the area is 10,000 nm 2 or less, or 1,000 nm 2 or less, the ferroelectricity may be maintained.
  • the occupied area of the capacitance element 100 can be reduced.
  • a ferroelectric is an insulator that has the property that polarization occurs inside when an electric field is applied from the outside, and that the polarization remains even when the electric field is made zero. For this reason, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric.
  • a nonvolatile memory element using a ferroelectric capacitor is sometimes called a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, etc.
  • a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance element 100, the memory device shown in this embodiment functions as a ferroelectric memory.
  • the conductive layer 120 is provided in contact with a portion of the upper surface of the insulating layer 130.
  • the side end of the conductive layer 120 is preferably located inside the side end of the conductive layer 115 in both the X direction and the Y direction.
  • the side end of the conductive layer 120 may be located outside the side end of the conductive layer 115.
  • the conductive layer 120 can be formed as a single layer or a stacked layer using the conductive material described in the section [Conductive Layer] of Embodiment 1. It is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen as the conductive layer 120.
  • a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen as the conductive layer 120.
  • titanium nitride or tantalum nitride can be used.
  • a structure in which tantalum nitride is stacked on titanium nitride may be used. In this case, titanium nitride is in contact with the insulating layer 130, and tantalum nitride is in contact with the oxide semiconductor layer 230.
  • the conductive layer 120 has a region in contact with the oxide semiconductor layer 230, it is preferable to use a conductive material containing oxygen.
  • a conductive material containing oxygen as the conductive layer 120, the conductive layer 120 can maintain its conductivity even if it absorbs oxygen.
  • an insulating layer containing oxygen such as zirconium oxide is used as the insulating layer 130, the conductive layer 120 is preferable because it can maintain its conductivity.
  • the conductive layer 120 for example, ITO, ITSO, IZO (registered trademark), or the like can be used in a single layer or a stacked layer.
  • the insulating layer 180 functions as an interlayer film, it is preferable that the insulating layer 180 has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.
  • an insulating layer containing a material with a low dielectric constant can be used in a single layer or a multilayer structure. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the insulating layer 180 is shown as a single layer in Figs. 10B and 10C, the present invention is not limited to this.
  • the insulating layer 180 may be a laminated structure of two layers, or a laminated structure of three or more layers.
  • the memory cell 150 including the transistor 200A and the capacitor 100 described in this embodiment can be used as a memory cell of a storage device.
  • the transistor 200A is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor.
  • the transistor 200A has a small off-state current; therefore, when used in a storage device, stored content can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the storage device can be sufficiently reduced. Furthermore, the high frequency characteristics of the transistor 200A allow high-speed reading and writing of the storage device.
  • a memory cell array can be formed by arranging memory cells 150 in a three-dimensional matrix.
  • Figure 11A is a plan view of a memory device.
  • Figure 11A shows an example in which 2 x 2 memory cells (memory cells 150a to 150d) are arranged in the X and Y directions.
  • Figure 11B is a cross-sectional view taken along dashed line A3-A4 in Figure 11A.
  • two memory cells (memory cell 150a and memory cell 150b in Figure 11B) are connected to a common wiring (conductive layer 246).
  • each of the memory cells 150a and 150b shown in FIG. 11A and FIG. 11B has the same configuration as the memory cell 150.
  • the memory cell 150a has a capacitor 100a and a transistor 200a
  • the memory cell 150b has a capacitor 100b and a transistor 200b.
  • the memory cells 150c and 150d shown in FIG. 11A also have the same configuration as the memory cell 150. Therefore, in the memory device shown in FIG. 11A and FIG. 11B, the same reference numerals are attached to structures having the same functions as the structures constituting the memory device shown in FIG. 10.
  • the description of the memory cell 150 in ⁇ Configuration Example 1 of Memory Device> can be referred to.
  • a conductive layer 265 functioning as a wiring WOL is provided in each of the memory cells 150a and 150b.
  • one conductive layer 265 is provided in common to the memory cells 150a and 150c, and another conductive layer 265 is provided in common to the memory cells 150b and 150d.
  • a conductive layer 240 functioning as a part of the wiring BIL is provided in common to the memory cells 150a and 150b. That is, the conductive layer 240 is in contact with the oxide semiconductor layer 230 of the memory cell 150a and the oxide semiconductor layer 230 of the memory cell 150b.
  • the other conductive layer 240 is provided in common to the memory cells 150c and 150d.
  • 11B shows an example in which the conductive layer 240 has a two-layer structure of a conductive layer 240a and a conductive layer 240b on the conductive layer 240a.
  • the conductive layer 240 has a two-layer structure of a conductive layer 240a and a conductive layer 240b on the conductive layer 240a.
  • the 11A and 11B includes a conductive layer 245 and a conductive layer 246 that are electrically connected to the memory cell 150a and the memory cell 150b and function as plugs (which can also be called connection electrodes).
  • the conductive layer 245 is disposed in an opening formed in the insulating layer 140, the insulating layer 180, the insulating layer 130, and the insulating layer 280, and is in contact with the bottom surface of the conductive layer 240a.
  • the conductive layer 246 is disposed in an opening formed in the insulating layer 287, the insulating layer 285, the insulating layer 283, the insulating layer 250, the oxide semiconductor layer 230, and the conductive layer 240b, and is in contact with the top surface of the conductive layer 240a.
  • the conductive layer 245 and the conductive layer 246 can be formed using a conductive material that can be used for the conductive layer 240, or the like.
  • the conductive layer 246 can be in contact with the upper surface of the conductive layer 240b.
  • the conductive layer 246 can be in contact with the upper surface of the oxide semiconductor layer 230.
  • the conductive layer 240b and the oxide semiconductor layer 230 do not need to have an opening at a position overlapping with the conductive layer 246.
  • a layer having low contact resistance with the conductive layer 246 among the layers constituting the conductive layer 240 and the oxide semiconductor layer 230 is in contact with the conductive layer 246.
  • the conductive layer 245 can be in contact with the bottom surface of the conductive layer 240b or the bottom surface of the oxide semiconductor layer 230. That is, the conductive layer 240a may have an opening at a position overlapping with the conductive layer 246.
  • a layer having low contact resistance with the conductive layer 245 be in contact with the conductive layer 245.
  • the layer having low wiring resistance be in contact with the conductive layer 245 and the conductive layer 246.
  • the insulating layer 287 functions as an interlayer film, it is preferable that the insulating layer 287 has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wiring can be reduced.
  • the concentration of impurities such as water and hydrogen in the insulating layer 287 is reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.
  • the conductive layer 245 and the conductive layer 246 function as plugs or wirings for electrically connecting circuit elements, wirings, electrodes, or terminals such as switches, transistors, capacitors, inductors, resistors, and diodes to the memory cells 150a and 150b.
  • the conductive layer 245 can be electrically connected to a sense amplifier (not shown) provided under the memory device shown in FIG. 11B
  • the conductive layer 246 can be electrically connected to a similar memory device (not shown) provided on the memory device shown in FIG. 11B.
  • the conductive layer 245 and the conductive layer 246 function as part of the wiring BIL. In this way, by providing a memory device or the like above or below the memory device shown in FIG. 11B, the memory capacity per unit area can be increased.
  • the memory cell 150a and the memory cell 150b are configured to be linearly symmetrical with respect to the perpendicular bisector of the dashed dotted line A3-A4 as the axis of symmetry. Therefore, the transistor 200a and the transistor 200b are also arranged symmetrically with the conductive layer 245 and the conductive layer 246 sandwiched therebetween.
  • the conductive layer 240 functions as the other of the source electrode and drain electrode of the transistor 200a and as the other of the source electrode and drain electrode of the transistor 200b.
  • the transistor 200a and the transistor 200b share the conductive layer 245 and the conductive layer 246 that function as plugs. In this way, by configuring the connection between the two transistors and the plug as described above, a memory device that can be miniaturized or highly integrated can be provided.
  • the conductive layer 110 functioning as the wiring CAL may be provided in each of the memory cells 150a and 150b, or may be provided in common to the memory cells 150a and 150b. However, as shown in FIG. 11B, the conductive layer 110 is provided apart from the conductive layer 245 so that the conductive layer 110 and the conductive layer 245 are not short-circuited.
  • FIG. 12 shows an example in which the four memory cells shown in FIG. 11A are stacked in n layers (n is an integer of 3 or more) in the Z direction.
  • FIG. 12 is a cross-sectional view between dashed lines A3-A4 shown in FIG. 11A.
  • the memory device shown in FIG. 12 has n memory layers 160. Specifically, memory layer 160[2] is provided on memory layer 160[1], and (n-2) memory layers are further provided on memory layer 160[2], with memory layer 160[n] provided on the topmost layer.
  • the number of memory cells in one memory layer 160 is not particularly limited, and two or more memory cells can be included.
  • the memory cells in n memory layers 160 are electrically connected to a sense amplifier (not shown) provided below n memory layers 160 by conductive layers 245, 246, 247, 248, etc.
  • FIG. 12 shows an example in which the conductive layer 245 is in contact with the bottom surface of the conductive layer 240, and the conductive layer 246 is in contact with the top surface of the oxide semiconductor layer 230.
  • various modes are possible for the connection points between the plugs such as the conductive layer 245 and the conductive layer 246 and each memory cell, and are not limited to the configuration in FIG. 12.
  • the cells can be integrated and arranged without increasing the area occupied by the memory cell array.
  • a 3D memory cell array can be constructed.
  • Figure 13 shows an example of the cross-sectional configuration of a memory device in which a layer having memory cells is stacked on a layer in which a driver circuit including a sense amplifier is provided.
  • a memory cell 150 (transistor 200A and capacitance element 100) is provided above transistor 300.
  • Transistor 300 is one of the transistors contained in the sense amplifier.
  • the bit line can be shortened by configuring the sense amplifier so that it overlaps with the memory cell 150. This reduces the bit line capacitance, enabling the memory device to operate at high speed.
  • the memory device shown in FIG. 13 can correspond to the semiconductor device 900 described in embodiment 3. Specifically, the transistor 300 corresponds to the transistor included in the sense amplifier 927 in the semiconductor device 900. Also, the memory cell 150 corresponds to the memory cell 950.
  • the transistor 300 is provided on a substrate 311 and has a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulating layer, a semiconductor region 313 that is a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b that function as a source region or a drain region.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • the semiconductor region 313 (part of the substrate 311) in which the channel is formed has a convex shape.
  • a conductive layer 316 is provided so as to cover the side and top surface of the semiconductor region 313 via an insulating layer 315.
  • the conductive layer 316 may be made of a material that adjusts the work function.
  • Such a transistor 300 is also called a FIN type transistor because it uses the convex portion of the semiconductor substrate.
  • an insulating layer that is in contact with the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided.
  • a semiconductor film having a convex shape may be formed by processing an SOI substrate.
  • transistor 300 shown in FIG. 13 is just an example, and the structure is not limited thereto, and an appropriate transistor can be used depending on the circuit configuration or driving method.
  • a wiring layer having an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers may be provided depending on the design.
  • the conductive layer functioning as a plug or wiring may be given the same reference symbol as a group of multiple structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.
  • an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order on the transistor 300 as an interlayer film.
  • a conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326.
  • the conductive layer 328 and the conductive layer 330 function as plugs or wiring.
  • the insulating layer that functions as an interlayer film may also function as a planarizing film that covers the uneven shape below it.
  • the upper surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve flatness.
  • a wiring layer may be provided on the insulating layer 326 and the conductive layer 330.
  • insulating layer 350, insulating layer 352, and insulating layer 354 are stacked in this order.
  • conductive layer 356 is formed on insulating layer 350, insulating layer 352, and insulating layer 354. Conductive layer 356 functions as a plug or wiring.
  • the insulating layer 352 and insulating layer 354, which function as interlayer films, can be the insulating layers that can be used in the semiconductor device or memory device described above.
  • Conductive layers that function as plugs or wiring can be made of a conductive material that can be used for the conductive layer 240. It is preferable to use a high-melting point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is preferable to use tungsten. Alternatively, it is preferable to form the conductive layer from a low-resistance conductive material, such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.
  • the conductive layer 240 of the transistor 200A is electrically connected to the low-resistance region 314b that functions as the source region or drain region of the transistor 300 via the conductive layer 643, the conductive layer 642, the conductive layer 644, the conductive layer 645, the conductive layer 646, the conductive layer 356, the conductive layer 330, and the conductive layer 328.
  • the conductive layer 643 is embedded in the insulating layer 280.
  • the conductive layer 642 is provided on the insulating layer 130 and embedded in the insulating layer 641.
  • the conductive layer 642 can be manufactured using the same material and in the same process as the conductive layer 120.
  • the conductive layer 644 is embedded in the insulating layer 180 and the insulating layer 130.
  • the conductive layer 645 is embedded in the insulating layer 647.
  • the conductive layer 645 can be manufactured using the same material and in the same process as the conductive layer 110.
  • the conductive layer 646 is embedded in the insulating layer 648.
  • the transistor 300 and the conductive layer 110 are electrically insulated by the insulating layer 648.
  • the memory device of this embodiment has transistors with reduced parasitic capacitance, and therefore the operating speed can be increased.
  • the memory device of this embodiment has a capacitive element and a transistor stacked on top of each other, and therefore the area occupied by the memory cell in a plan view can be reduced, and a highly integrated memory device can be realized.
  • the semiconductor device 900 can function as a memory device.
  • FIG. 14 shows a block diagram illustrating a configuration example of a semiconductor device 900.
  • the semiconductor device 900 shown in FIG. 14 has a driver circuit 910 and a memory array 920.
  • the memory array 920 has one or more memory cells 950.
  • FIG. 14 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.
  • the memory device described in embodiment 2 (such as memory cell 150) can be applied to memory cell 950.
  • the drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915.
  • the peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.
  • each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or other signals may be added.
  • Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 912.
  • the control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.
  • the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900.
  • the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.
  • the voltage generation circuit 928 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.
  • the peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950.
  • the peripheral circuit 911 has a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.
  • the row decoder 941 and column decoder 942 have the function of decoding the signal ADDR.
  • the row decoder 941 is a circuit for specifying the row to be accessed
  • the column decoder 942 is a circuit for specifying the column to be accessed.
  • the row driver 923 has the function of selecting the row specified by the row decoder 941.
  • the column driver 924 has the function of writing data to the memory cell 950, the function of reading data from the memory cell 950, the function of retaining the read data, etc.
  • the input circuit 925 has a function of holding a signal WDA.
  • the data held by the input circuit 925 is output to the column driver 924.
  • the output data of the input circuit 925 is data (Din) to be written to the memory cell 950.
  • the data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926.
  • the output circuit 926 has a function of holding Dout.
  • the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900.
  • the data output from the output circuit 926 is the signal RDA.
  • the PSW 931 has a function of controlling the supply of V DD to the peripheral circuit 915.
  • the PSW 932 has a function of controlling the supply of V HM to the row driver 923.
  • the high power supply potential of the semiconductor device 900 is V DD
  • the low power supply potential is GND (ground potential).
  • V HM is a high power supply potential used to set the word line to a high level, and is higher than V DD .
  • the signal PON1 controls the on/off of the PSW 931
  • the signal PON2 controls the on/off of the PSW 932.
  • the number of power supply domains to which V DD is supplied in the peripheral circuit 915 is one, but it may be more than one. In this case, a power switch may be provided for each power supply domain.
  • [DOSRAM] 15A shows an example of a circuit configuration of a memory cell of a DRAM.
  • a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM).
  • a memory cell 951 includes a transistor M1 and a capacitor CA.
  • the transistor M1 may have a front gate (sometimes simply called a gate) and a back gate.
  • the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected.
  • the first terminal of transistor M1 is connected to the first terminal of capacitance element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL.
  • the second terminal of capacitance element CA is connected to wiring CAL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.
  • Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitance element CA into a conductive state (a state in which current can flow).
  • memory cell that can be used for memory cell 950 is not limited to memory cell 951, and the circuit configuration can be changed.
  • memory cell 952 shown in FIG. 15B may be used.
  • Memory cell 952 is an example in which the memory cell does not have a capacitance element CA and a wiring CAL.
  • the first terminal of transistor M1 is in an electrically floating state.
  • the potential written through transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, as shown by the dashed line.
  • an OS transistor has a characteristic that its off-state current is extremely small.
  • the leakage current of transistor M1 can be made extremely low. That is, since written data can be held by transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary.
  • the leakage current is extremely low, multi-value data or analog data can be held in memory cell 951 and memory cell 952.
  • [NOSRAM] 15C shows an example of a circuit configuration of a gain cell type memory cell having two transistors and one capacitor.
  • the memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB.
  • a storage device having a gain cell type memory cell using an OS transistor as the transistor M2 is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).
  • the first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL.
  • the second terminal of capacitance element CB is connected to wiring CAL.
  • the first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB.
  • a low-level potential sometimes called a reference potential
  • Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and bringing the wiring WBL and the first terminal of the capacitance element CB into a conductive state.
  • a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitance element CB and the gate of the transistor M3.
  • a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitance element CB and the potential of the gate of the transistor M3.
  • Data is read by applying a predetermined potential to the wiring SL.
  • the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate of transistor M3 and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held in the first terminal of capacitance element CB (or the gate of transistor M3) can be read. In other words, the information written in this memory cell can be read from the potential held in the first terminal of capacitance element CB (or the gate of transistor M3).
  • the wiring WBL and the wiring RBL may be combined into a single wiring BIL.
  • An example of the circuit configuration of such a memory cell is shown in FIG. 15D.
  • the memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL.
  • the memory cell 954 is configured to operate the write bit line and the read bit line as a single wiring BIL.
  • Memory cell 955 shown in FIG. 15E is an example in which the capacitance element CB and the wiring CAL in memory cell 953 are omitted.
  • memory cell 956 shown in FIG. 15F is an example in which the capacitance element CB and the wiring CAL in memory cell 954 are omitted.
  • OS transistor for at least transistor M2.
  • OS transistors for transistors M2 and M3.
  • the OS transistor Since the OS transistor has a characteristic that the off-state current is extremely small, the written data can be held for a long time by the transistor M2, and therefore the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. In addition, since the leakage current is extremely low, multi-value data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.
  • Memory cell 953, memory cell 954, memory cell 955, and memory cell 956, in which an OS transistor is used as transistor M2, are one embodiment of NOSRAM.
  • Si transistors may be used as transistor M3.
  • Si transistors can increase the field effect mobility and can also be used as p-channel transistors, allowing for greater freedom in circuit design.
  • the memory cell can be configured as a unipolar circuit.
  • FIG. 15G shows a three-transistor, one-capacitor gain cell type memory cell 957.
  • the memory cell 957 has transistors M4 to M6 and a capacitative element CC.
  • the first terminal of transistor M4 is connected to the first terminal of the capacitance element CC, the second terminal of transistor M4 is connected to the wiring BIL, and the gate of transistor M4 is connected to the wiring WOL.
  • the second terminal of the capacitance element CC is connected to the first terminal of transistor M5 and the wiring GNDL.
  • the second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of the capacitance element CC.
  • the second terminal of transistor M6 is connected to the wiring BIL, and the gate of transistor M6 is connected to the wiring RWL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a write word line
  • the wiring RWL functions as a read word line.
  • the wiring GNDL is a wiring that provides a low-level potential.
  • Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and bringing the wiring BIL and the first terminal of the capacitance element CC into electrical continuity. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitance element CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby retaining the potential of the first terminal of the capacitance element CC and the potential of the gate of the transistor M5.
  • Data is read by precharging the wiring BIL with a predetermined potential, then electrically floating the wiring BIL and applying a high-level potential to the wiring RWL. Since the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are in a conductive state. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5, and the potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5).
  • the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5) can be read.
  • the information written in this memory cell can be read from the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5).
  • Si transistors may be used as transistors M5 and M6. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystal state of the silicon used in the semiconductor layer.
  • the memory cell can be configured as a unipolar circuit.
  • [OS-SRAM] 15H shows an example of a static random access memory (SRAM) using an OS transistor.
  • SRAM static random access memory
  • OS-SRAM oxide semiconductor SRAM
  • a memory cell 958 shown in FIG. 15H is a memory cell of an SRAM capable of backing up data.
  • Memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.
  • the first terminal of transistor M7 is connected to the wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10.
  • the gate of transistor M7 is connected to the wiring WOL.
  • the first terminal of transistor M8 is connected to the wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9.
  • the gate of transistor M8 is connected to the wiring WOL.
  • the second terminal of transistor MS1 is connected to the wiring VDL.
  • the second terminal of transistor MS2 is connected to the wiring VDL.
  • the second terminal of transistor MS3 is connected to the wiring GNDL.
  • the second terminal of transistor MS4 is connected to the wiring GNDL.
  • the second terminal of transistor M9 is connected to the first terminal of capacitance element CD1, and the gate of transistor M9 is connected to wiring BRL.
  • the second terminal of transistor M10 is connected to the first terminal of capacitance element CD2, and the gate of transistor M10 is connected to wiring BRL.
  • the second terminal of the capacitance element CD1 is connected to the wiring GNDL, and the second terminal of the capacitance element CD2 is connected to the wiring GNDL.
  • the wiring BIL and the wiring BILB function as bit lines
  • the wiring WOL functions as a word line
  • the wiring BRL is a wiring that controls the on/off state of the transistors M9 and M10.
  • the wiring VDL is a wiring that provides a high-level potential
  • the wiring GNDL is a wiring that provides a low-level potential.
  • Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal side of the transistor M10.
  • the memory cell 958 forms an inverter loop with the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Since the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Also, since the transistors M9 and M10 are on, the potential of the second terminal of the transistor M7 and the potential of the second terminal of the transistor M8 are held in the first terminal of the capacitance element CD2 and the first terminal of the capacitance element CD1, respectively.
  • a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potential of the first terminal of the capacitance element CD1 and the first terminal of the capacitance element CD2.
  • the wirings BIL and BILB are precharged to a predetermined potential beforehand, and then a high-level potential is applied to the wiring WOL and a high-level potential is applied to the wiring BRL.
  • the potential of the first terminal of the capacitance element CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB.
  • the potential of the first terminal of the capacitance element CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL.
  • the potentials of the wirings BIL and BILB change from the precharged potentials to the potential of the first terminal of the capacitance element CD2 and the potential of the first terminal of the capacitance element CD1, respectively, so that the potential held in the memory cell can be read from the potential of the wiring BIL or wiring BILB.
  • OS transistors as the transistors M7 to M10. This allows the written data to be held for a long time by the transistors M7 to M10, so that the frequency of refreshing the memory cells can be reduced. Alternatively, the refresh operation of the memory cells can be eliminated.
  • Si transistors may be used as transistors MS1 to MS4.
  • the driving circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Also, as shown in FIG. 16A, the driving circuit 910 and memory array 920 may be provided overlapping each other. By providing the driving circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Also, as shown in FIG. 16B, the memory array 920 may be provided in multiple layers on the driving circuit 910.
  • Figure 17 shows a block diagram of the arithmetic unit 960.
  • the arithmetic unit 960 shown in Figure 17 can be applied to, for example, a CPU (Central Processing Unit).
  • the arithmetic unit 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a large number (several tens to several hundreds) of processor cores capable of parallel processing more than a CPU.
  • processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a large number (several tens to several hundreds) of processor cores capable of parallel processing more than a CPU.
  • the arithmetic device 960 shown in FIG. 17 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990.
  • the substrate 990 is a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface.
  • the cache 999 and the cache interface 989 may be provided on separate chips.
  • the cache 999 is connected to a main memory provided on a separate chip via a cache interface 989.
  • the cache interface 989 has a function of supplying a portion of the data held in the main memory to the cache 999.
  • the cache interface 989 also has a function of outputting a portion of the data held in the cache 999 to the ALU 991 or register 996, etc. via the bus interface 998.
  • a memory array 920 can be provided by stacking it on the arithmetic unit 960.
  • the memory array 920 can be used as a cache.
  • the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999.
  • a drive circuit 910 is included as part of the cache interface 989.
  • the arithmetic device 960 shown in FIG. 17 is merely an example of a simplified configuration, and the actual arithmetic device 960 has a wide variety of configurations depending on the application.
  • the more cores there are, the more preferable it is, but for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more.
  • the number of bits that the arithmetic device 960 can handle in its internal arithmetic circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.
  • Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993, decoded, and then input to the ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995.
  • the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates a signal for controlling the operation of the ALU 991. In addition, the interrupt controller 994 determines and processes interrupt requests from external input/output devices, peripheral circuits, etc. based on their priority and mask state while the arithmetic device 960 is executing a program. The register controller 997 generates an address for the register 996, and reads and writes to the register 996 depending on the state of the arithmetic device 960.
  • the timing controller 995 also generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997.
  • the timing controller 995 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.
  • the register controller 997 selects the holding operation in the register 996 according to instructions from the ALU 991. That is, it selects whether the memory cells in the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 996. If holding data in capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.
  • Figs. 18A and 18B show perspective views of a semiconductor device 970A.
  • the semiconductor device 970A has a layer 930 in which a memory array is provided on the arithmetic device 960.
  • the layer 930 has memory arrays 920L1, 920L2, and 920L3.
  • the arithmetic device 960 and each memory array have overlapping areas.
  • Fig. 18B shows the arithmetic device 960 and layer 930 separated.
  • connection distance between them can be shortened. This allows the communication speed between them to be increased. In addition, the short connection distance allows for reduced power consumption.
  • a method for stacking the layer 930 having a memory array and the arithmetic device 960 As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method of stacking the layer 930 having a memory array directly on the arithmetic device 960 (also called monolithic stacking) may be used, or a method of forming the arithmetic device 960 and the layer 930 on different substrates, bonding the two substrates, and electrically connecting them using a through via or conductive film bonding technology (such as Cu-Cu bonding) may be used.
  • the former method does not require consideration of misalignment during bonding, so it is possible to reduce not only the chip size but also the manufacturing cost.
  • the arithmetic device 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache.
  • the memory array 920L1 can be used as an L1 cache (also called a level 1 cache)
  • the memory array 920L2 can be used as an L2 cache (also called a level 2 cache)
  • the memory array 920L3 can be used as an L3 cache (also called a level 3 cache).
  • the memory array 920L3 has the largest capacity and is accessed the least frequently.
  • the memory array 920L1 has the smallest capacity and is accessed the most frequently.
  • each memory array provided in the layer 930 can be used as a lower-level cache or a main memory.
  • the main memory has a larger capacity than the cache and is accessed less frequently.
  • a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided.
  • the driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1.
  • the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2
  • the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.
  • the drive circuit 910L1 may function as part of the cache interface 989, or the drive circuit 910L1 may be configured to be connected to the cache interface 989.
  • the drive circuit 910L2 and the drive circuit 910L3 may also function as part of the cache interface 989, or may be configured to be connected to it.
  • the control circuit 912 can cause some of the multiple memory cells 950 in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.
  • the semiconductor device 900 can cause some of the multiple memory cells 950 to function as a cache, and the other part to function as a main memory. In other words, the semiconductor device 900 can function both as a cache and as a main memory.
  • the semiconductor device 900 according to one aspect of the present invention can function as, for example, a universal memory.
  • a layer 930 having one memory array 920 may be provided on top of the computing device 960.
  • Figure 19A shows a perspective view of the semiconductor device 970B.
  • one memory array 920 can be divided into multiple areas, each of which can be used for different functions.
  • Figure 19A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.
  • the capacity of each of areas L1 to L3 can be changed according to the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of area L1. With such a configuration, it is possible to improve the efficiency of calculation processing and increase the processing speed.
  • Figure 19B shows a perspective view of semiconductor device 970C.
  • the semiconductor device 970C has a layer 930L1 having a memory array 920L1 stacked on top of a layer 930L2 having a memory array 920L2, and a layer 930L3 having a memory array 920L3 stacked on top of that.
  • the memory array 920L1 which is physically closest to the computing device 960, can be used as a higher-level cache, and the memory array 920L3, which is the furthest, can be used as a lower-level cache or main memory. With this configuration, the capacity of each memory array can be increased, thereby further improving processing power.
  • Figure 20A shows various storage devices used in semiconductor devices by hierarchy. The higher the storage device, the faster the operating speed is required, and the lower the storage device, the larger the storage capacity and the higher the recording density are required.
  • a processor such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, storage, etc. Note that, although an example having up to an L3 cache is shown here, it is also possible to have even lower-level caches.
  • Registers also have the function of storing setting information for the processor.
  • a cache has the function of duplicating and storing a portion of the data stored in the main memory. By duplicating frequently used data and storing it in the cache, the speed of accessing the data can be increased.
  • the storage capacity required for a cache is less than that of the main memory, but it is required to operate at a faster speed than the main memory.
  • data that is rewritten in the cache is duplicated and supplied to the main memory.
  • the main memory has the function of holding programs, data, etc. read from storage.
  • Storage has the function of holding data that requires long-term storage and various programs used by processing units. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed.
  • a high-capacity, non-volatile storage device such as 3D NAND can be used.
  • a storage device (OS memory) using an oxide semiconductor according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. Therefore, as shown in FIG. 20A, the storage device according to one embodiment of the present invention can be suitably used in both the hierarchy where the cache is located and the hierarchy where the main memory is located. In addition, the storage device according to one embodiment of the present invention can also be applied to the hierarchy where the storage is located.
  • Figure 20B also shows an example in which SRAM is used for part of the cache and an OS memory according to one aspect of the present invention is used for the other part.
  • the lowest level cache can be called an LLC (Last Level cache).
  • LLC Low Level cache
  • the OS memory of one embodiment of the present invention has a fast operating speed and is capable of retaining data for a long period of time, making it suitable for use as an LLC. Note that the OS memory of one embodiment of the present invention can also be applied to an FLC (Final Level cache).
  • a configuration can be used in which SRAM is used for the higher-level cache (L1 cache, L2 cache, etc.) and the OS memory of one aspect of the present invention is used for the LLC. Also, as shown in FIG. 20B, not only the OS memory but also DRAM can be used for the main memory.
  • the semiconductor device of one embodiment of the present invention can be used for a display device or a module having the display device.
  • the module having the display device include a module in which a connector such as a flexible printed circuit (hereinafter, referred to as FPC) or a TCP (Tape Carrier Package) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a COG (Chip On Glass) method, a COF (Chip On Film) method, or the like.
  • FPC flexible printed circuit
  • TCP Tape Carrier Package
  • the display device of this embodiment may also have a function as a touch panel.
  • various detection elements also called sensor elements
  • various detection elements that can detect the proximity or contact of a detectable object such as a finger can be applied to the display device.
  • Sensor types include, for example, capacitance type, resistive film type, surface acoustic wave type, infrared type, optical type, and pressure sensitive type.
  • Examples of the capacitance type include a surface capacitance type and a projected capacitance type.
  • Examples of the projected capacitance type include a self-capacitance type and a mutual capacitance type.
  • the mutual capacitance type is preferable because it allows simultaneous multi-point detection.
  • touch panels examples include out-cell, on-cell, and in-cell types.
  • an in-cell touch panel is one in which electrodes constituting a detection element are provided on one or both of the substrate supporting the display element and the opposing substrate.
  • Display module 21A shows a perspective view of the display module 170.
  • the display module 170 includes a display device 600A and an FPC 298. Note that the display device included in the display module 170 is not limited to the display device 600A and may be a display device 600B described later.
  • the display module 170 has a substrate 291 and a substrate 299.
  • the display module 170 has a display section 297.
  • the display section 297 is an area that displays an image in the display module 170, and is an area in which light from each pixel provided in a pixel section 294 described later can be viewed.
  • Figure 21B shows a perspective view that shows a schematic configuration on the substrate 291 side.
  • a circuit portion 292 On the substrate 291, a circuit portion 292, a pixel circuit portion 293 on the circuit portion 292, and a pixel portion 294 on the pixel circuit portion 293 are stacked.
  • a terminal portion 295 for connecting to an FPC 298 is provided in a portion of the substrate 291 that does not overlap with the pixel portion 294.
  • the terminal portion 295 and the circuit portion 292 are electrically connected by a wiring portion 296 that is composed of multiple wirings.
  • the semiconductor device of one embodiment of the present invention can be used as one or both of the circuit portion 292 and the pixel circuit portion 293.
  • the pixel section 294 has a number of pixels 294a arranged periodically. An enlarged view of one pixel 294a is shown on the right side of FIG. 21B.
  • FIG. 21B shows an example in which one pixel 294a has a subpixel 130R that emits red light, a subpixel 130G that emits green light, and a subpixel 130B that emits blue light.
  • the subpixel has a display element.
  • Various elements can be used as the display element, including, for example, a liquid crystal element and a light-emitting element.
  • a shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) element a display element using a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type can also be used.
  • a QLED Quantum-dot LED
  • a light source and color conversion technology using quantum dot materials may be used.
  • light-emitting elements include self-emitting light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. Examples of LEDs that can be used include mini LEDs and micro LEDs.
  • the pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied.
  • Examples of pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a Pentile arrangement.
  • Figure 21B shows an example in which a stripe arrangement is applied to the pixel arrangement.
  • the pixel circuit section 293 has a number of pixel circuits 293a arranged periodically.
  • One pixel circuit 293a is a circuit that controls the driving of multiple elements in one pixel 294a.
  • One pixel circuit 293a can be configured to have three circuits that control the light emission of one light-emitting element.
  • the pixel circuit 293a can be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitance for each light-emitting element. At this time, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display device.
  • the circuit portion 292 has a circuit that drives each pixel circuit 293a of the pixel circuit portion 293.
  • a gate line driver circuit and a source line driver circuit.
  • it may have at least one of an arithmetic circuit, a memory circuit, a power supply circuit, etc.
  • the FPC 298 functions as wiring for supplying a video signal, a power supply potential, etc. from the outside to the circuit section 292.
  • An IC may also be mounted on the FPC 298.
  • the display module 170 can be configured such that one or both of the pixel circuit section 293 and the circuit section 292 are stacked below the pixel section 294, so that the aperture ratio (effective display area ratio) of the display section 297 can be made extremely high.
  • the pixels 294a can be arranged at an extremely high density, so that the resolution of the display section 297 can be made extremely high.
  • Such a display module 170 has extremely high resolution and can therefore be suitably used in VR devices such as HMDs or glasses-type AR devices. For example, even in a configuration in which the display section of the display module 170 is viewed through a lens, the display module 170 has an extremely high resolution display section 297, so that even if the display section is enlarged with a lens, the pixels are not visible, allowing for a highly immersive display.
  • the display module 170 is not limited to this and can be suitably used in electronic devices with relatively small display sections. For example, it can be suitably used in the display section of a wearable electronic device such as a wristwatch.
  • Display Device Configuration Example 1 22 shows a cross-sectional view of a display device 600A.
  • the display device 600A is an example of a display device to which an MML (metal maskless) structure is applied.
  • the display device 600A has light-emitting elements fabricated without using a fine metal mask.
  • the island-shaped light-emitting layer in the light-emitting element of a display device to which the MML structure is applied is formed by depositing a light-emitting layer on one surface and then processing it using a photolithography method. This makes it possible to realize a high-definition display device or a display device with a high aperture ratio, which has been difficult to achieve until now. Furthermore, since the light-emitting layer can be made separately for each color, a display device with extremely vivid images, high contrast, and high display quality can be realized.
  • a display device is composed of three types of light-emitting elements, one that emits blue light, one that emits green light, and one that emits red light
  • three types of island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and processing by photolithography three times.
  • Devices with an MML structure can be manufactured without using a metal mask, and therefore can exceed the upper limit of definition resulting from the alignment accuracy of the metal mask. Furthermore, when devices are manufactured without using a metal mask, the equipment required for manufacturing the metal mask and the process of cleaning the metal mask can be eliminated. Furthermore, since the same or similar equipment as that used to manufacture transistors can be used for photolithography processing, there is no need to introduce special equipment to manufacture devices with an MML structure. In this way, the MML structure makes it possible to keep manufacturing costs low, and is therefore suitable for mass production of devices.
  • a display device to which the MML structure is applied there is no need to artificially increase the resolution by applying a special pixel arrangement such as a Pentile arrangement, so it is possible to realize a display device with high resolution (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more) with a so-called stripe arrangement in which R, G, and B sub-pixels are each arranged in one direction.
  • a special pixel arrangement such as a Pentile arrangement
  • the sacrificial layer may remain in the completed display device, or may be removed during the manufacturing process.
  • the sacrificial layer 618a shown in Figures 22 and 23 is a part of the sacrificial layer that was provided on the light-emitting layer.
  • the display device 600A shown in FIG. 22 is a schematic cross-sectional view of a display device (semiconductor device) according to one embodiment of the present invention.
  • the display device 600A has a configuration in which a pixel circuit, a driver circuit, and the like are provided over a substrate 410.
  • a wiring layer 670 is also illustrated in the display device 600A shown in FIG. 22, in addition to the element layer 620, the element layer 630, and the element layer 660.
  • the wiring layer 670 is a layer in which wiring is provided.
  • the element layer 630 is preferably provided with a pixel circuit of the display device.
  • the element layer 620 is preferably provided with a driver circuit of the display device (one or both of a gate driver and a source driver).
  • the element layer 620 may also be provided with one or more types of circuits such as an arithmetic circuit and a memory circuit.
  • the element layer 620 has, as an example, a substrate 410 on which a transistor 400d is formed.
  • a wiring layer 670 is provided above the transistor 400d, and the wiring layer 670 has wiring that electrically connects the transistor 400d to a conductive layer or a transistor (conductive layer 514 in FIG. 22) provided in the element layer 630.
  • An element layer 630 and an element layer 660 are provided above the wiring layer 670, and the element layer 630 has, as an example, a transistor MTCK.
  • the element layer 660 has a light-emitting element 650 (light-emitting element 650R, light-emitting element 650G, and light-emitting element 650B in FIG. 22) and the like.
  • Transistor 400d is an example of a transistor included in element layer 620.
  • Transistor MTCK is an example of a transistor included in element layer 630.
  • the light-emitting elements (light-emitting element 650R, light-emitting element 650G, and light-emitting element 650B) are an example of a light-emitting element included in element layer 660.
  • the substrate 410 may be a semiconductor substrate (for example, a single crystal substrate made of silicon or germanium).
  • the substrate 410 may be, for example, an SOI (Silicon On Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film.
  • the substrate 410 is described as a semiconductor substrate having silicon as a material. Therefore, the transistors included in the element layer 620 may be Si transistors.
  • the transistor 400d has an element isolation layer 412, a conductive layer 416, an insulating layer 415, an insulating layer 417, a semiconductor region 413 formed of a part of the substrate 410, and a low-resistance region 414a and a low-resistance region 414b that function as a source region or a drain region. Therefore, the transistor 400d is a Si transistor. Note that although FIG. 22 shows a configuration in which one of the source and drain of the transistor 400d is electrically connected to the conductive layer 514 provided in the element layer 630 through the conductive layer 428, the conductive layer 430, and the conductive layer 456, the electrical connection configuration of the display device of one embodiment of the present invention is not limited thereto.
  • the transistor 400d can be a Fin type by, for example, covering the top surface and the side surface in the channel width direction of the semiconductor region 413 with the conductive layer 416 via the insulating layer 415 that functions as a gate insulating layer.
  • the transistor 400d By making the transistor 400d a Fin type, the effective channel width can be increased, and the on characteristics of the transistor 400d can be improved. In addition, the contribution of the electric field of the gate electrode can be increased, and therefore the off characteristics of the transistor 400d can be improved.
  • the transistor 400d may be a planar type instead of a Fin type.
  • the transistor 400d may be either a p-channel type or an n-channel type. Alternatively, multiple transistors 400d may be provided, and both p-channel and n-channel types may be used.
  • the region in which the channel of the semiconductor region 413 is formed, the region nearby, and the low resistance region 414a and low resistance region 414b that become the source region or drain region preferably contain a silicon-based semiconductor, specifically, single crystal silicon.
  • each of the above-mentioned regions may be formed using, for example, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride.
  • a configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used.
  • the transistor 400d may be, for example, a HEMT (High Electron Mobility Transistor) using gallium arsenide and aluminum gallium arsenide.
  • HEMT High Electron Mobility Transistor
  • the conductive layer 416 functioning as a gate electrode can be made of a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron or aluminum.
  • the conductive layer 416 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material.
  • the work function is determined by the material of the conductive layer, so the threshold voltage of the transistor can be adjusted by selecting the material of the conductive layer. Specifically, it is preferable to use one or both of titanium nitride and tantalum nitride as the conductive layer. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use one or both of tungsten and aluminum as a laminated layer for the conductive layer, and in particular, it is preferable to use tungsten in terms of heat resistance.
  • the element isolation layer 412 is provided to isolate multiple transistors formed on the substrate 410 from each other.
  • the element isolation layer can be formed, for example, by using a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a mesa isolation method.
  • LOC local oxidation of silicon
  • STI shallow trench isolation
  • an insulating layer 420 and an insulating layer 422 are stacked in this order from the substrate 410 side.
  • the insulating layer 420 and the insulating layer 422 for example, one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride can be used.
  • the insulating layer 422 may function as a planarizing film that planarizes steps caused by the insulating layer 420 and the transistor 400d covered by the insulating layer 422.
  • the top surface of the insulating layer 422 may be planarized by a planarization process using a CMP method or the like to improve the planarity.
  • a conductive layer 428 is embedded in the insulating layer 420 and the insulating layer 422, and connects to the transistor MTCK and the like that are provided above the insulating layer 422.
  • the conductive layer 428 functions as a plug or wiring.
  • a wiring layer 670 is provided on the transistor 400d.
  • the wiring layer 670 includes, for example, an insulating layer 424, an insulating layer 426, a conductive layer 430, an insulating layer 450, an insulating layer 452, an insulating layer 454, and a conductive layer 456.
  • An insulating layer 424 and an insulating layer 426 are stacked in this order on the insulating layer 422 and the conductive layer 428.
  • An opening is formed in the insulating layer 424 and the insulating layer 426 in the area overlapping the conductive layer 428.
  • a conductive layer 430 is embedded in the opening.
  • Insulating layer 450, insulating layer 452, and insulating layer 454 are stacked in this order on insulating layer 426 and conductive layer 430. In the region overlapping with conductive layer 430, openings are formed in insulating layer 450, insulating layer 452, and insulating layer 454. Conductive layer 456 is embedded in the opening.
  • the conductive layer 430 and the conductive layer 456 function as a plug or wiring that connects to the transistor 400d.
  • an insulating layer having a barrier property against one or more selected from hydrogen, oxygen, and water for the insulating layer 424 and the insulating layer 450, similar to the insulating layer 592 described later. It is also preferable to use an insulating layer having a relatively low relative dielectric constant for the insulating layer 426, the insulating layer 452, and the insulating layer 454, similar to the insulating layer 594 described later, in order to reduce parasitic capacitance generated between wirings.
  • the insulating layer 426, the insulating layer 452, and the insulating layer 454 function as an interlayer insulating film and a planarizing film.
  • the conductive layer 456 includes a conductive layer having barrier properties against one or more selected from hydrogen, oxygen, and water.
  • tantalum nitride may be used as the insulating layer having a barrier property against hydrogen.
  • tantalum nitride and tungsten which has high conductivity, it is possible to suppress diffusion of hydrogen from the transistor 400d while maintaining the conductivity of the wiring.
  • the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulating layer 450 having a barrier property against hydrogen.
  • An insulating layer 513 is provided above the insulating layer 454 and the conductive layer 456.
  • An insulating layer IS1 is provided on the insulating layer 513.
  • a conductive layer that functions as a plug or wiring is embedded in the insulating layer IS1 and the insulating layer 513. This allows the transistor 400d to be electrically connected to the conductive layer 514 provided in the element layer 630. Alternatively, one of the source or drain of the transistor MTCK and one of the source or drain of the transistor 400d may be electrically connected.
  • the transistor MTCK is provided on the insulating layer IS1. Also, on the transistor MTCK, an insulating layer IS3, an insulating layer IS4, an insulating layer 574, and an insulating layer 581 are laminated in this order. Also, a conductive layer MPG functioning as a plug or wiring is embedded in the insulating layer IS3, the insulating layer IS4, the insulating layer 574, and the insulating layer 581. As shown in the enlarged view of the area surrounded by the dashed line in FIG. 22, it is preferable that the conductive layer MPG directly contacts the conductive layer 240 through the openings provided in the insulating layer GI1, the insulating layer 250, and the oxide semiconductor layer 230.
  • the contact resistance can be reduced, which is preferable.
  • the conductive layer MPG and the oxide semiconductor layer 230 may be in contact with each other, and the conductive layer MPG and the conductive layer 240 may be electrically connected through the oxide semiconductor layer 230.
  • the insulating layer 574 preferably has a function of suppressing the diffusion of impurities such as water and hydrogen (e.g., hydrogen atoms and/or hydrogen molecules).
  • the insulating layer 574 preferably functions as a barrier insulating film that suppresses the impurities from being mixed into the transistor MTCK.
  • the insulating layer 574 also preferably has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and/or oxygen molecules).
  • the insulating layer 574 preferably has lower oxygen permeability than each of the insulating layer IS2, the insulating layer IS3, and the insulating layer IS4.
  • the insulating layer 574 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen. Therefore, the insulating layer 574 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O , NO, and NO2 ), and copper atoms (the impurities are unlikely to permeate through the insulating material). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and/or oxygen molecules) (the oxygen is unlikely to permeate through the insulating material).
  • oxygen e.g., oxygen atoms and/or oxygen molecules
  • the materials that can be used for insulating layers that have the function of suppressing the permeation of impurities and oxygen, as exemplified in embodiment 1, can be used.
  • the insulating layer 574 it is preferable to use aluminum oxide or silicon nitride for the insulating layer 574. This can prevent impurities such as water and hydrogen from diffusing from above the insulating layer 574 to the transistor MTCK. Alternatively, it can prevent oxygen contained in the insulating layer IS3, etc. from diffusing above the insulating layer 574.
  • the insulating layer 581 is a film that functions as an interlayer film, and preferably has a lower dielectric constant than the insulating layer 574.
  • the relative dielectric constant of the insulating layer 581 is preferably less than 4, and more preferably less than 3.
  • the relative dielectric constant of the insulating layer 581 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulating layer 574.
  • the concentration of impurities such as water and hydrogen in the insulating layer 581 is reduced.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used for the insulating layer 581.
  • silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies can be used for the insulating layer 581.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating.
  • resin can be used for the insulating layer 581.
  • the material that can be applied to the insulating layer 581 may be an appropriate combination of the above-mentioned materials.
  • Insulating layer 592 and insulating layer 594 are laminated in this order on insulating layer 574 and insulating layer 581.
  • an insulating film having a barrier property that prevents impurities such as water and hydrogen from diffusing from the substrate 410 and the transistor MTCK to a region above the insulating layer 592 (for example, a region where the light-emitting element 650R, the light-emitting element 650G, and the light-emitting element 650B are provided) is preferably used. Therefore, for the insulating layer 592, an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (through which the above impurities are unlikely to permeate) is preferably used.
  • an insulating material having a function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N 2 O, NO, and NO 2 ), and copper atoms (through which the above impurities are unlikely to permeate) is preferably used.
  • the insulating layer 592 has a function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules).
  • One example of a film that has barrier properties against hydrogen is silicon nitride formed by the CVD method.
  • the amount of desorption of hydrogen can be analyzed by, for example, thermal desorption spectrometry (TDS).
  • TDS thermal desorption spectrometry
  • the amount of desorption of hydrogen from the insulating layer 424, when the surface temperature of the film is in the range of 50° C. to 500° C. is preferably 10 ⁇ 10 15 atoms/cm 2 or less, and more preferably 5 ⁇ 10 15 atoms/cm 2 or less, per area of the insulating layer 424, as converted into hydrogen atoms, in TDS.
  • the insulating layer 594 is preferably an interlayer film with a low dielectric constant, similar to the insulating layer 581. For this reason, the insulating layer 594 can be made of a material that can be used for the insulating layer 581.
  • the insulating layer 594 preferably has a lower dielectric constant than the insulating layer 592.
  • the relative dielectric constant of the insulating layer 594 is preferably less than 4, and more preferably less than 3.
  • the relative dielectric constant of the insulating layer 594 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulating layer 592.
  • a conductive layer MPG functioning as a plug or wiring is embedded in the insulating layer GI1, the insulating layer IS3, the insulating layer IS4, the insulating layer 574, and the insulating layer 581, and a conductive layer 596 functioning as a plug or wiring is embedded in the insulating layer 592 and the insulating layer 594.
  • the conductive layer MPG and the conductive layer 596 are electrically connected to a light-emitting element provided above the insulating layer 594.
  • a conductive layer having a function as a plug or wiring may be given the same symbol as a group of multiple structures.
  • the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as a wiring, and cases where a part of the conductive layer functions as a plug.
  • each plug and wiring for example, conductive layer MPG, conductive layer 428, conductive layer 430, conductive layer 456, conductive layer 514, and conductive layer 596
  • one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials can be used in a single layer or a stacked layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferably used. Alternatively, it is preferable to form the wiring from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.
  • Insulating layer 598 and insulating layer 599 are formed in sequence on insulating layer 594 and conductive layer 596.
  • the insulating layer 598 it is preferable to use an insulating layer having barrier properties against one or more of hydrogen, oxygen, and water as the insulating layer 598, similar to the insulating layer 592.
  • the insulating layer 599 it is preferable to use an insulating layer having a relatively low relative dielectric constant in order to reduce parasitic capacitance generated between wirings, similar to the insulating layer 594.
  • the insulating layer 599 functions as an interlayer insulating film and a planarizing film.
  • a light-emitting element 650 and a connection portion 640 are formed on the insulating layer 599.
  • connection portion 640 may be called a cathode contact portion, and is electrically connected to the cathode electrodes of the light-emitting elements 650R, 650G, and 650B.
  • a conductive layer formed in the same process and from the same material as the conductive layers 611a to 611c is electrically connected to the common electrode 615, which will be described later.
  • FIG. 22 shows an example in which the conductive layer is electrically connected to the common electrode 615 via the common layer 614, which will be described later, but the conductive layer and the common electrode 615 may be in direct contact.
  • connection portion 640 may be provided so as to surround the four sides of the display portion in a plan view, or may be provided within the display portion (e.g., between adjacent light-emitting elements 650) (not shown).
  • Light-emitting element 650R has conductive layer 611a as a pixel electrode.
  • light-emitting element 650G has conductive layer 611b as a pixel electrode
  • light-emitting element 650B has conductive layer 611c as a pixel electrode.
  • the conductive layers 611a, 611b, and 611c are each connected to the conductive layer 596 embedded in the insulating layer 594 via a conductive layer (plug) embedded in the insulating layer 599.
  • Light-emitting element 650R has layer 613a, a common layer 614 on layer 613a, and a common electrode 615 on common layer 614.
  • Light-emitting element 650G has layer 613b, a common layer 614 on layer 613b, and a common electrode 615 on common layer 614.
  • Light-emitting element 650B has layer 613c, a common layer 614 on layer 613c, and a common electrode 615 on common layer 614.
  • a metal, an alloy, an electrically conductive compound, a mixture thereof, and the like can be appropriately used as a material for forming a pair of electrodes (pixel electrode and common electrode) of a light-emitting element.
  • the material include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations.
  • examples of the material include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide.
  • examples of the material include alloys containing aluminum (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and alloys containing silver, such as an alloy of silver and magnesium, and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC).
  • Such materials include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not listed above, rare earth metals such as europium and ytterbium, and alloys containing appropriate combinations of these, graphene, etc.
  • the display device 600A uses an SBS structure.
  • the SBS structure allows the material and configuration to be optimized for each light-emitting element, which increases the freedom of material and configuration selection and makes it easier to improve brightness and reliability.
  • the display device 600A is also a top emission type.
  • transistors and the like can be arranged so as to overlap the light emitting region of the light emitting element, so the aperture ratio of the pixel can be increased compared to a bottom emission type.
  • layer 613a is formed so as to cover the upper surface and side surfaces of conductive layer 611a.
  • layer 613b is formed so as to cover the upper surface and side surfaces of conductive layer 611b.
  • layer 613c is formed so as to cover the upper surface and side surfaces of conductive layer 611c. Therefore, the entire region in which conductive layer 611a, conductive layer 611b, and conductive layer 611c are provided can be used as the light-emitting region of light-emitting element 650R, light-emitting element 650G, and light-emitting element 650B, and the aperture ratio of the pixel can be increased.
  • layer 613a and common layer 614 can be collectively referred to as the EL layer.
  • layer 613b and common layer 614 can be collectively referred to as the EL layer.
  • layer 613c and common layer 614 can be collectively referred to as the EL layer.
  • the EL layer has at least a light-emitting layer.
  • the light-emitting layer has one or more types of light-emitting materials.
  • a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used.
  • a material that emits near-infrared light can also be used as the light-emitting material.
  • Examples of light-emitting materials that light-emitting elements have include fluorescent materials, phosphorescent materials, materials that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF materials), and inorganic compounds (quantum dot materials, etc.).
  • the light-emitting layer may have one or more organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material).
  • the one or more organic compounds one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) can be used.
  • a bipolar substance a substance with high electron transport properties and hole transport properties
  • a TADF material may be used as the one or more organic compounds.
  • the EL layer may have one or more of a layer containing a substance with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a substance with high electron blocking properties (electron blocking layer), a layer containing a substance with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a substance with high hole blocking properties (hole blocking layer).
  • the EL layer may contain one or both of a bipolar substance and a TADF material.
  • the light-emitting element can be made of either a low molecular weight compound or a high molecular weight compound, and may contain an inorganic compound.
  • the layers constituting the light-emitting element can be formed by a deposition method (including a vacuum deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
  • a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units) may be applied to the light-emitting element.
  • the light-emitting unit has at least one light-emitting layer.
  • the tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer has a function of injecting electrons into one of the two light-emitting units and injecting holes into the other.
  • the tandem structure can be used to make a light-emitting element capable of emitting high-luminance light. Furthermore, the tandem structure can reduce the current required to obtain the same luminance compared to a single structure, and therefore can improve reliability.
  • the tandem structure can be called a stack structure.
  • color purity can be improved by adding a microcavity structure to the light-emitting element.
  • Layers 613a, 613b, and 613c are processed into island shapes by photolithography. Therefore, layers 613a, 613b, and 613c have a shape in which the angle between the top surface and the side surface at the end is close to 90 degrees.
  • an organic film formed using FMM Fine Metal Mask
  • the top surface is formed in a slope shape over a range of 1 ⁇ m to 10 ⁇ m to the end, resulting in a shape in which it is difficult to distinguish between the top surface and the side surface.
  • top and side surfaces of layers 613a, 613b, and 613c are clearly distinguished. As a result, in adjacent layers 613a and 613b, one side surface of layer 613a and one side surface of layer 613b are arranged opposite each other. This is the same for any combination of layers 613a, 613b, and 613c.
  • Layer 613a, layer 613b, and layer 613c each have at least a light-emitting layer.
  • layer 613a has a light-emitting layer that emits red light
  • layer 613b has a light-emitting layer that emits green light
  • layer 613c has a light-emitting layer that emits blue light.
  • each light-emitting layer can be of a color other than cyan, magenta, yellow, or white.
  • the layers 613a, 613b, and 613c preferably have a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Since the surfaces of the layers 613a, 613b, and 613c may be exposed during the manufacturing process of the display device, providing a carrier transport layer on the light-emitting layer can prevent the light-emitting layer from being exposed to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting element.
  • a carrier transport layer electron transport layer or hole transport layer
  • the common layer 614 has, for example, an electron injection layer or a hole injection layer.
  • the common layer 614 may have a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer.
  • the common layer 614 is shared by the light-emitting element 650R, the light-emitting element 650G, and the light-emitting element 650B. Note that the common layer 614 does not have to be provided, and the entire EL layer of the light-emitting element may be provided in an island shape, such as the layer 613a, the layer 613b, and the layer 613c.
  • the common electrode 615 is shared by the light-emitting elements 650R, 650G, and 650B. As shown in FIG. 22, the common electrode 615 shared by the multiple light-emitting elements is electrically connected to a conductive layer included in the connection portion 640.
  • the insulating layer 625 preferably has a function as a barrier insulating layer against water and/or oxygen.
  • the insulating layer 625 preferably has a function of suppressing the diffusion of water and/or oxygen.
  • the insulating layer 625 preferably has a function of capturing or fixing (also referred to as gettering) water and/or oxygen.
  • the insulating layer 625 has a function as a barrier insulating layer or a gettering function, so that it is possible to suppress the intrusion of impurities (typically, water and/or oxygen) that may diffuse from the outside into each light-emitting element. With this structure, a highly reliable light-emitting element and a highly reliable display device can be provided.
  • the insulating layer 625 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 625 and causing deterioration of the EL layer. In addition, by lowering the impurity concentration in the insulating layer 625, the barrier properties against water and/or oxygen can be improved. For example, it is desirable that the insulating layer 625 has a sufficiently low hydrogen concentration or a sufficiently low carbon concentration, or preferably both.
  • an insulating layer containing an organic material can be suitably used.
  • the organic material it is preferable to use a photosensitive organic resin, for example, a photosensitive resin composition containing an acrylic resin.
  • acrylic resin does not only refer to polymethacrylic acid ester or methacrylic resin, but may refer to acrylic polymers in a broad sense.
  • the organic materials that can be used for the insulating layer 627 are not limited to those mentioned above.
  • the insulating layer 627 may be made of acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins.
  • the insulating layer 627 may be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral (PVB), polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin.
  • the insulating layer 627 may be made of, for example, a photoresist as a photosensitive resin. Examples of photosensitive resins include positive-type materials and negative-type materials.
  • the insulating layer 627 may be made of a material that absorbs visible light. By absorbing light emitted from the light-emitting element with the insulating layer 627, it is possible to suppress leakage of light from the light-emitting element to an adjacent light-emitting element through the insulating layer 627 (stray light). This can improve the display quality of the display device. In addition, since the display quality can be improved without using a polarizing plate in the display device, the display device can be made lighter and thinner.
  • Materials that absorb visible light include materials containing pigments such as black, materials containing dyes, resin materials with light absorbing properties (e.g., polyimide), and resin materials that can be used in color filters (color filter materials).
  • resin materials with light absorbing properties e.g., polyimide
  • color filter materials resin materials that can be used in color filters
  • by mixing three or more colors of color filter materials it is possible to create a resin layer that is black or close to black.
  • the insulating layer 627 can be formed using a wet film formation method such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • a wet film formation method such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • the insulating layer 627 is formed at a temperature lower than the heat resistance temperature of the EL layer.
  • the substrate temperature when forming the insulating layer 627 is typically 200°C or lower, preferably 180°C or lower, more preferably 160°C or lower, more preferably 150°C or lower, and more preferably 140°C or lower.
  • the insulating layer 627 preferably has a tapered shape on the side.
  • the side end of the insulating layer 627 into a forward tapered shape (less than 90°, preferably 60° or less, and more preferably 45° or less)
  • the common layer 614 and common electrode 615 provided on the side end of the insulating layer 627 can be formed with good coverage without causing discontinuities or localized thinning. This can improve the in-plane uniformity of the common layer 614 and common electrode 615, thereby improving the display quality of the display device.
  • the upper surface of the insulating layer 627 preferably has a convex curved shape.
  • the convex curved shape of the upper surface of the insulating layer 627 preferably has a shape that bulges gently toward the center.
  • Insulating layer 627 is also formed in the region between the two EL layers (e.g., the region between layers 613a and 613b). At this time, a portion of insulating layer 627 is disposed in a position sandwiched between a side edge of one EL layer (e.g., layer 613a) and a side edge of the other EL layer (e.g., layer 613b).
  • one end of the insulating layer 627 overlaps with the conductive layer 611a that functions as a pixel electrode, and the other end of the insulating layer 627 overlaps with the conductive layer 611b that functions as a pixel electrode.
  • the end of the insulating layer 627 can be formed on a flat or approximately flat region of the layer 613a (layer 613b). Therefore, it is relatively easy to process the tapered shape of the insulating layer 627 as described above.
  • the insulating layer 627, etc. it is possible to prevent the formation of discontinuities and locally thin areas in the common layer 614 and common electrode 615 from the flat or roughly flat area of the layer 613a to the flat or roughly flat area of the layer 613b. Therefore, it is possible to prevent connection failures caused by discontinuities and increases in electrical resistance caused by locally thin areas in the common layer 614 and common electrode 615 between each light-emitting element.
  • the display device of this embodiment can narrow the distance between light-emitting elements.
  • the distance between light-emitting elements, the distance between EL layers, or the distance between pixel electrodes can be less than 10 ⁇ m, 8 ⁇ m or less, 5 ⁇ m or less, 3 ⁇ m or less, 2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less.
  • the display device of this embodiment has an area where the distance between two adjacent island-shaped EL layers is 1 ⁇ m or less, preferably has an area where the distance is 0.5 ⁇ m (500 nm) or less, and more preferably has an area where the distance is 100 nm or less. In this way, by narrowing the distance between each light-emitting element, a display device with high definition and large aperture ratio can be provided.
  • a protective layer 631 is provided on the light-emitting element 650.
  • the protective layer 631 is a film that functions as a passivation film that protects the light-emitting element 650. By providing the protective layer 631 that covers the light-emitting element, impurities such as water and oxygen can be prevented from entering the light-emitting element, and the reliability of the light-emitting element 650 can be improved.
  • the protective layer 631 is preferably a single-layer structure or a laminated structure that includes at least an inorganic insulating film.
  • the inorganic insulating film examples include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film.
  • a semiconductor material such as indium gallium oxide or indium gallium zinc oxide (IGZO) may be used as the protective layer 631.
  • the protective layer 631 can be formed by an ALD method, a CVD method, a sputtering method, or the like. Note that, although a configuration including an inorganic insulating film has been exemplified as the protective layer 631, this is not limiting.
  • the protective layer 631 may be a laminated structure of an inorganic insulating film and an organic insulating film.
  • the protective layer 631 and the substrate 610 are bonded via an adhesive layer 607.
  • a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting element.
  • the space between the substrate 410 and the substrate 610 is filled with an adhesive layer 607, and a solid sealing structure is applied.
  • the space may be filled with an inert gas (such as nitrogen or argon) and a hollow sealing structure may be applied.
  • the adhesive layer 607 may be provided so as not to overlap with the light-emitting element.
  • the space may also be filled with a resin different from the adhesive layer 607 provided in a frame shape.
  • various types of curing adhesives can be used, such as ultraviolet-curing photocuring adhesives, reaction-curing adhesives, heat-curing adhesives, and anaerobic adhesives.
  • these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins.
  • epoxy resins with low moisture permeability are preferred.
  • Two-part mixed resins may also be used.
  • An adhesive sheet may also be used.
  • the display device 600A is a top emission type. Light emitted by the light emitting element is emitted to the substrate 610 side. For this reason, it is preferable to use a material that is highly transparent to visible light for the substrate 610. For example, it is preferable to select a substrate that is highly transparent to visible light for the substrate 610 from among the substrates that can be used for the substrate 410.
  • the pixel electrode contains a material that reflects visible light
  • the opposing electrode (common electrode 615) contains a material that transmits visible light.
  • the display device of one embodiment of the present invention may be a bottom emission type in which light emitted from a light-emitting element is emitted toward the substrate 410, rather than a top emission type.
  • a substrate that has high transparency to visible light is selected as the substrate 410.
  • FIG. 23 shows a cross-sectional view of the display device 600B.
  • the display device 600B can be a flexible display device (also called a flexible display) by using flexible substrates for the substrate 541 and the substrate 610.
  • the substrate 541 is attached to the insulating layer 545 by an adhesive layer 543.
  • the substrate 610 is attached to the protective layer 631 by an adhesive layer 607.
  • the element layer 660 of the display device 600B differs from the element layer 660 of the display device 600A mainly in that the same configuration is applied to the layers 613a, 613b, and 613c, and further in that the colored layers 628R, 628G, and 628B are provided.
  • Layer 613a, layer 613b, and layer 613c are formed in the same process and with the same material. In addition, layer 613a, layer 613b, and layer 613c are separated from each other.
  • leakage current sometimes called horizontal leakage current, horizontal leakage current, or lateral leakage current
  • the light-emitting elements 650R, 650G, and 650B shown in FIG. 23 emit white light.
  • the white light emitted by the light-emitting elements 650R, 650G, and 650B passes through the colored layers 628R, 628G, and 628B, thereby obtaining light of the desired color.
  • a light-emitting element configured to emit white light may emit light of a specific wavelength, such as red, green, or blue, with the light being enhanced.
  • the light emitted by the light-emitting element 650R is extracted as red light to the outside of the display device 600B via the colored layer 628R.
  • the light emitted by the light-emitting element 650G is extracted as green light to the outside of the display device 600B via the colored layer 628G.
  • the light emitted by the light-emitting element 650B is extracted as blue light to the outside of the display device 600B via the colored layer 628B.
  • the light-emitting elements 650R, 650G, and 650B shown in FIG. 23 emit blue light.
  • the layers 613a, 613b, and 613c each have one or more light-emitting layers that emit blue light.
  • the blue light emitted by the light-emitting element 650B can be extracted.
  • a color conversion layer is provided between the light-emitting element 650R and the coloring layer 628R and between the light-emitting element 650G and the coloring layer 628G, so that the blue light emitted by the light-emitting element 650R or the light-emitting element 650G can be converted into light with a longer wavelength, and red or green light can be extracted.
  • the coloring layer can absorb light other than the desired color, and the color purity of the light that the subpixel emits can be increased.
  • the colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges.
  • a red (R) color filter that transmits light in the red wavelength range
  • a green (G) color filter that transmits light in the green wavelength range
  • a blue (B) color filter that transmits light in the blue wavelength range
  • R red
  • G green
  • B blue
  • a metal material a resin material, a pigment, and a dye
  • the colored layers are formed at the desired positions by a printing method, an inkjet method, an etching method using photolithography, or the like.
  • the element layer 630 of the display device 600B has a similar configuration to the element layer 630 of the display device 600A, so a detailed description will be omitted.
  • Display device 600B differs from display device 600A in that it does not have element layer 620 but has element layer 635.
  • Element layer 635 has the same configuration as element layer 630.
  • At least a part of the transistor in the element layer 635 is electrically connected to the conductive layer or the transistor in the element layer 630 via a plug, a wiring, or the like. Note that a wiring layer 670 may be provided between the element layer 630 and the element layer 635.
  • the element layer 635 is preferably provided with one or both of a pixel circuit and a driver circuit of a display device.
  • element layer 630 and element layer 635 an example in which two element layers having OS transistors are stacked (element layer 630 and element layer 635) is shown, but the number of stacked element layers is not limited to this, and may be three or more layers.
  • the bottom layer is used for the driver circuit (one or both of the gate driver and source driver) of the display device
  • the top layer is used for the pixel circuit of the display device
  • the layers located between are used for the pixel circuit or the driver circuit, respectively.
  • Si transistors are typically formed on single crystal Si wafers, making it difficult to make them flexible.
  • FIG. 23 when a display device is constructed using only OS transistors without using Si transistors, a flexible configuration can be obtained using a relatively simple manufacturing process.
  • Figure 24A shows a schematic top view of a portion of a display unit having multiple light-emitting elements.
  • the display unit has multiple light-emitting elements 61R that emit red light, multiple light-emitting elements 61G that emit green light, and multiple light-emitting elements 61B that emit blue light.
  • the symbols R, G, and B are added within the light-emitting region of each light-emitting element to easily distinguish between the light-emitting elements.
  • Figure 24A illustrates a configuration having three light-emitting colors, red (R), green (G), and blue (B), but this is not limiting. For example, a configuration having four or more colors may be used.
  • Figure 24B is a cross-sectional view taken along dashed line A1-A2 in Figure 24A.
  • Light-emitting element 61R, light-emitting element 61G, and light-emitting element 61B shown in Figure 24B are each provided on insulating layer 363, and have conductive layer 171 functioning as a pixel electrode and conductive layer 173 functioning as a common electrode.
  • the light-emitting element 61R has an EL layer 172R between the conductive layer 171 functioning as a pixel electrode and the conductive layer 173 functioning as a common electrode.
  • the EL layer 172R has a light-emitting compound that emits light having a peak at least in the red wavelength range.
  • the EL layer 172G of the light-emitting element 61G has a light-emitting compound that emits light having a peak at least in the green wavelength range.
  • the EL layer 172B of the light-emitting element 61B has a light-emitting compound that emits light having a peak at least in the blue wavelength range.
  • the conductive layer 171 functioning as a pixel electrode is provided for each light-emitting element.
  • the conductive layer 173 functioning as a common electrode is provided as a continuous layer common to each light-emitting element.
  • a conductive film that is transparent to visible light is used for either the conductive layer 171 functioning as a pixel electrode or the conductive layer 173 functioning as a common electrode, and a conductive film that is reflective is used for the other.
  • the light-emitting element 61R is a top-emission type
  • the light 175R emitted from the light-emitting element 61R is emitted toward the conductive layer 173.
  • the light-emitting element 61R is a top-emission type
  • the light 175G emitted from the light-emitting element 61G is emitted toward the conductive layer 173.
  • the light-emitting element 61B is a top-emission type
  • the light 175B emitted from the light-emitting element 61B is emitted toward the conductive layer 173.
  • An insulating layer 272 is provided to cover the end of the conductive layer 171 that functions as a pixel electrode.
  • the end of the insulating layer 272 is preferably tapered.
  • the insulating layer 272 can be an inorganic insulating film or an organic insulating film, or both.
  • the insulating layer 272 is provided to prevent adjacent light-emitting elements from unintentionally shorting electrically and causing erroneous light emission. In addition, when a metal mask is used to form the EL layer, the insulating layer 272 also functions to prevent the metal mask from coming into contact with the conductive layer 171.
  • EL layer 172R, EL layer 172G, and EL layer 172B each have a region in contact with the top surface of conductive layer 171, which functions as a pixel electrode, and a region in contact with the surface of insulating layer 272.
  • the ends of EL layer 172R, EL layer 172G, and EL layer 172B are located on insulating layer 272.
  • a gap is provided between two EL layers between light-emitting elements that emit different light colors.
  • the EL layer 172R, the EL layer 172G, and the EL layer 172B are provided so as not to be in contact with each other. This makes it possible to preferably prevent current from flowing through two adjacent EL layers and causing unintended light emission (also called crosstalk). As a result, it is possible to increase the contrast and realize a display device with high display quality.
  • EL layer 172R, EL layer 172G, and EL layer 172B can be separately produced by a vacuum deposition method using a shadow mask such as a metal mask. Alternatively, they may be separately produced by a photolithography method. By using the photolithography method, it is possible to produce a high-definition display device that is difficult to achieve when using a metal mask.
  • a protective layer 271 is provided on the conductive layer 173, which functions as a common electrode, to cover the light-emitting elements 61R, 61G, and 61B.
  • the protective layer 271 has a function of preventing impurities such as water from diffusing from above to each light-emitting element.
  • the material of the protective layer 631 described above can be used as the material of the protective layer 271.
  • Figure 24C shows a light-emitting element 61W that emits white light.
  • the light-emitting element 61W has an EL layer 172W that emits white light between a conductive layer 171 that functions as a pixel electrode and a conductive layer 173 that functions as a common electrode.
  • the EL layer 172W can be configured, for example, by stacking two or more light-emitting layers selected so that the emitted colors are complementary to each other. Also, a tandem-type EL layer may be used in which a charge generating layer is sandwiched between the light-emitting layers.
  • Figure 24C shows three light-emitting elements 61W lined up.
  • a colored layer 264R is provided on the top of the left light-emitting element 61W.
  • the colored layer 264R functions as a bandpass filter that transmits red light.
  • a colored layer 264G that transmits green light is provided on the top of the center light-emitting element 61W
  • a colored layer 264B that transmits blue light is provided on the top of the right light-emitting element 61W. This allows the display device to display color images.
  • the EL layer 172W is separated between two adjacent light-emitting elements 61W. This makes it possible to prevent unintended light emission in two adjacent light-emitting elements 61W due to current flowing through the EL layer 172W.
  • a stacked EL layer in which a charge generating layer is provided between two light-emitting layers is used as the EL layer 172W.
  • the higher the resolution i.e., the smaller the distance between adjacent pixels, the more pronounced the effect of crosstalk becomes, resulting in a decrease in contrast. Therefore, by using such a configuration, a display device that combines high resolution and high contrast can be realized.
  • the separation of the EL layer 172W is preferably performed by photolithography. This allows the spacing between the light-emitting elements to be narrowed, resulting in a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.
  • the semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, large-scale computers, space equipment, data centers (also referred to as Data Centers: DCs), and various electronic devices.
  • DCs Data Centers
  • the semiconductor device of one embodiment of the present invention it is possible to achieve low power consumption and high performance in electronic components, large-scale computers, space equipment, data centers, and various electronic devices.
  • a display device including a semiconductor device of one embodiment of the present invention can be used as a display portion of various electronic devices.
  • a display device including a semiconductor device of one embodiment of the present invention can easily achieve high definition and high resolution.
  • Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of one embodiment of the present invention can be used favorably in electronic devices having a relatively small display unit, since it is possible to increase the resolution.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, glasses-type AR devices, and MR devices.
  • the display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • a resolution of 4K, 8K, or more is preferable.
  • the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, 5000 ppi or more, or 7000 ppi or more.
  • the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.
  • the electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • FIG. 25A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 700 is mounted.
  • the electronic component 700 shown in FIG. 25A has a semiconductor device 710 in a mold 711. In FIG. 25A, some parts are omitted in order to show the inside of the electronic component 700.
  • the electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714.
  • the electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
  • the semiconductor device 710 also has a drive circuit layer 715 and a memory layer 716.
  • the memory layer 716 is configured by stacking a plurality of memory cell arrays.
  • the stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, each layer can be connected without using a through electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding.
  • TSV Through Silicon Via
  • a bonding technology such as Cu-Cu direct bonding.
  • connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and it is therefore possible to increase the number of connection pins.
  • Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).
  • the memory cell arrays in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked.
  • OS transistors By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency.
  • the bandwidth is the amount of data transferred per unit time
  • the access latency is the time from access to the start of data exchange.
  • Si transistors when Si transistors are used for the memory layer 716, it is difficult to form a monolithic stacked configuration compared to OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.
  • the semiconductor device 710 may also be referred to as a die.
  • a die refers to a chip piece obtained during the manufacturing process of a semiconductor chip by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into a dice shape.
  • Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also called a silicon wafer
  • a silicon die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.
  • Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module).
  • Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.
  • Electronic component 730 shows an example in which semiconductor device 710 is used as a high bandwidth memory (HBM).
  • Semiconductor device 735 can be used in integrated circuits such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).
  • the package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.
  • the interposer 731 may be, for example, a silicon interposer or a resin interposer.
  • the interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732.
  • the interposer may be called a "rewiring substrate” or "intermediate substrate.”
  • a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode.
  • a TSV may be used as the through electrode.
  • the interposer on which the HBM is mounted is required to have fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.
  • silicon interposers In addition, in SiP and MCM using silicon interposers, deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. In addition, since the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.
  • a composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacking memory cell array.
  • a heat sink may be provided overlapping the electronic component 730.
  • electrodes 733 may be provided on the bottom of the package substrate 732.
  • FIG. 25B shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized.
  • the electrodes 733 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.
  • the electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA.
  • mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).
  • Fig. 26A shows a perspective view of a large scale computer 5600.
  • the large scale computer 5600 shown in Fig. 26A has a rack 5610 housing a plurality of rack-mounted computers 5620.
  • the large scale computer 5600 may also be called a supercomputer.
  • the computer 5620 can have the configuration shown in the perspective view of FIG. 26B, for example.
  • the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals.
  • a PC card 5621 is inserted into the slot 5631.
  • the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.
  • the PC card 5621 shown in FIG. 26C is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like.
  • the PC card 5621 has a board 5622.
  • the board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • FIG. 26C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for those semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be referred to.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • An example of the standard for the connection terminal 5629 is PCIe.
  • Connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be, for example, interfaces for outputting signals calculated by PC card 5621. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
  • the semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • the electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5628 include a memory device.
  • the electronic component 700 can be used as the semiconductor device 5628.
  • the mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment.
  • the semiconductor device of one embodiment of the present invention includes an OS transistor.
  • the OS transistor has small changes in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and can be suitably used in an environment where radiation may be incident.
  • the OS transistor can be suitably used when used in outer space.
  • the OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe.
  • Examples of radiation include X-rays and neutron rays.
  • outer space refers to an altitude of 100 km or higher, for example, and the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.
  • Figure 26D shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Figure 26D also shows a planet 6804 in space.
  • the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit.
  • BMS battery management system
  • the use of OS transistors in the battery management system or battery control circuit described above is preferable because it consumes low power and has high reliability even in space.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • the solar panel 6802 When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or where the amount of sunlight irradiating the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is advisable to provide the satellite 6800 with a secondary battery 6805. Note that the solar panel may be called a solar cell module.
  • the artificial satellite 6800 can generate a signal.
  • the signal is transmitted via the antenna 6803, and can be received, for example, by a receiver installed on the ground or by another artificial satellite.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device.
  • a semiconductor device including an OS transistor which is one embodiment of the present invention, is preferably used for the control device 6807.
  • the OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. In other words, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can also be configured to have a sensor.
  • the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground.
  • the artificial satellite 6800 can have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, and a space probe.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.
  • the semiconductor device can be suitably used in a storage system applied to a data center or the like.
  • the data center is required to perform long-term management of data, such as ensuring the immutability of the data.
  • it is necessary to increase the size of the building, for example, by installing storage and servers for storing a huge amount of data, securing a stable power source for holding the data, or securing cooling equipment required for holding the data.
  • a semiconductor device By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores the data. This makes it possible to miniaturize the storage system, miniaturize the power source for storing data, and reduce the scale of cooling equipment. This makes it possible to save space in the data center.
  • the semiconductor device of one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.
  • Figure 26E shows a storage system applicable to a data center.
  • the storage system 7010 shown in Figure 26E has multiple servers 7001sb as hosts 7001 (illustrated as Host Computer). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage).
  • the host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).
  • SAN Storage Area Network
  • the host 7001 corresponds to a computer that accesses data stored in the storage 7003.
  • the hosts 7001 may be connected to each other via a network.
  • Storage 7003 uses flash memory to reduce data access speed, i.e. the time required to store and output data, but this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage.
  • storage systems typically provide cache memory within the storage to reduce the time required to store and output data.
  • the above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.
  • OS transistors as transistors for storing data in the cache memory, which hold a potential corresponding to the data
  • the frequency of refreshing can be reduced and power consumption can be reduced.
  • miniaturization is possible.
  • FIG. 27A to 27F An example of a wearable device that can be worn on the head will be described with reference to Figures 27A to 27F.
  • These wearable devices have at least one of a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content.
  • the electronic device 700A shown in FIG. 27A has a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.
  • the display device of one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can display with extremely high resolution.
  • the semiconductor device of one embodiment of the present invention can be applied to the control unit (not shown). This can reduce the power consumption of the electronic device.
  • Electronic device 700A can project an image displayed on display panel 751 onto display area 756 of optical member 753. Because optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through optical member 753. Therefore, electronic device 700A is an electronic device capable of AR display.
  • the electronic device 700A may be provided with a camera capable of capturing an image in front of it as an imaging unit.
  • the electronic device 700A may be provided with an acceleration sensor such as a gyro sensor, so that the electronic device 700A can detect the orientation of the user's head and display an image corresponding to that orientation in the display area 756.
  • the communication unit has a wireless communication device, and can supply video signals and the like via the wireless communication device.
  • a connector can be provided to which a cable through which a video signal and a power supply potential can be connected.
  • the electronic device 700A is also provided with a battery, which can be charged wirelessly and/or wired.
  • the housing 721 may be provided with a touch sensor module.
  • the touch sensor module has a function of detecting that the outer surface of the housing 721 is touched.
  • the touch sensor module can detect a tap operation or a slide operation by the user and execute various processes. For example, a tap operation can execute processes such as pausing or resuming a video, and a slide operation can execute processes such as fast-forwarding or rewinding. Furthermore, by providing a touch sensor module on each of the two housings 721, the range of operations can be expanded.
  • Electronic device 800A shown in FIG. 27B and electronic device 800B shown in FIG. 27C each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.
  • a display device can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high resolution can be obtained. This allows a user to feel a high sense of immersion.
  • a semiconductor device can be applied to the control portion 824. This allows the power consumption of the electronic device to be reduced.
  • the display unit 820 is provided inside the housing 821 at a position that can be seen through the lens 832. In addition, by displaying different images on the pair of display units 820, it is also possible to perform three-dimensional display using parallax.
  • Each of the electronic devices 800A and 800B can be considered electronic devices for VR.
  • a user wearing the electronic device 800A or the electronic device 800B can view the image displayed on the display unit 820 through the lens 832.
  • Electric device 800A and electronic device 800B each preferably have a mechanism that can adjust the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that they have a mechanism that adjusts the focus by changing the distance between lens 832 and display unit 820.
  • the mounting unit 823 allows the user to mount the electronic device 800A or electronic device 800B on the head. Note that in FIG. 27B and other figures, the mounting unit 823 is shaped like the temples of glasses, but is not limited to this. The mounting unit 823 only needs to be wearable by the user, and may be shaped like a helmet or band, for example.
  • the imaging unit 825 has a function of acquiring external information.
  • the data acquired by the imaging unit 825 can be output to the display unit 820.
  • An image sensor can be used for the imaging unit 825.
  • multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.
  • a distance measuring sensor capable of measuring the distance to an object
  • the imaging unit 825 is one aspect of the detection unit.
  • the detection unit for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection and Ranging) can be used.
  • LIDAR Light Detection and Ranging
  • the electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone.
  • a vibration mechanism that functions as a bone conduction earphone.
  • a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This makes it possible to enjoy video and audio by simply wearing the electronic device 800A without the need for separate audio equipment such as headphones, earphones, or speakers.
  • Each of the electronic devices 800A and 800B may have an input terminal.
  • the input terminal can be connected to a cable that supplies a video signal from a video output device or the like, and power for charging a battery provided within the electronic device.
  • the electronic device of one embodiment of the present invention may have a function of wireless communication with the earphone 750.
  • the earphone 750 has a communication unit (not shown) and has a wireless communication function.
  • the earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function.
  • the electronic device 700A shown in FIG. 27A has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device may also have an earphone unit.
  • the electronic device 800B shown in FIG. 27C has an earphone unit 827.
  • the earphone unit 827 and the control unit 824 may be configured to be connected to each other by wire.
  • a portion of the wiring connecting the earphone unit 827 and the control unit 824 may be disposed inside the housing 821 or the mounting unit 823.
  • the earphone unit 827 and the mounting unit 823 may also have a magnet. This allows the earphone unit 827 to be fixed to the mounting unit 823 by magnetic force, which is preferable as it makes storage easier.
  • the electronic device may have an audio output terminal to which earphones or headphones can be connected.
  • the electronic device may also have one or both of an audio input terminal and an audio input mechanism.
  • a sound collection device such as a microphone can be used as the audio input mechanism.
  • the electronic device may be endowed with the functionality of a so-called headset.
  • Figures 27D and 27E show perspective views of a goggle-type electronic device 850A for VR.
  • Figures 27D and 27E show an example in which a pair of curved display devices 840 (display device 840_R and display device 840_L) are included in a housing 845.
  • Electronic device 850A also includes a motion detection unit 841, a gaze detection unit 842, a calculation unit 843, a communication unit 844, a lens 848, an operation button 851, a wearing device 854, a sensor 855, a dial 856, and the like.
  • the user can see one display device per eye. This allows high-resolution images to be displayed even when performing 3D display using parallax.
  • the display device 840 is curved in an arc shape roughly centered on the user's eye. This allows the user to see more natural images because the distance from the user's eye to the display surface of the display device 840 is constant.
  • the user's eyes can be configured to be located in the normal direction of the display surface of the display device 840, so that the effect can be essentially ignored, especially in the horizontal direction, and more realistic images can be displayed.
  • lens 848 is positioned between display device 840 and the user's eyes.
  • FIG. 27E shows an example having dial 856 for changing the position of the lens to adjust visibility. Note that if electronic device 850A has an autofocus function, it does not need to have dial 856 for adjusting visibility.
  • Figure 27F shows a goggle-type electronic device 850B that has one display device 840. This configuration makes it possible to reduce the number of parts.
  • the display device 840 can display two images, one for the right eye and one for the left eye, side by side in two left and right areas. This makes it possible to display a stereoscopic image using binocular parallax. Note that the display device 840 may display two different images side by side using parallax, or may display two identical images side by side without using parallax.
  • a single image visible to both eyes may be displayed across the entire area of the display device 840. This allows a panoramic image to be displayed across both ends of the field of view, enhancing realism.
  • a display device can be applied to the display device 840.
  • the display device according to one embodiment of the present invention has extremely high definition, so that even if the image is enlarged using the lens 848, the user cannot see the pixels, and a more realistic image can be displayed.
  • the electronic device 6500 shown in FIG. 28A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 has a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509.
  • the electronic device 6520 shown in FIG. 28B is a portable information terminal that can be used as a tablet terminal.
  • the electronic device 6520 has a housing 6501, a display unit 6502, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a control device 6509, and a connection terminal 6519.
  • the display portion 6502 has a touch panel function.
  • the control device 6509 has, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be used for one or both of the display portion 6502 and the control device 6509.
  • Figure 28C is a schematic cross-sectional view including the end of the housing 6501 of the electronic device 6500 or electronic device 6520 on the microphone 6506 side.
  • a transparent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.
  • the display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).
  • a part of the display panel 6511 is folded back, and the FPC 6515 is connected to the folded back part.
  • An IC 6516 is mounted on the FPC 6515.
  • the FPC 6515 is connected to a terminal provided on a printed circuit board 6517.
  • the flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized.
  • the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while keeping the thickness of the electronic device small.
  • a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.
  • Figure 28D shows an example of a television device.
  • a display unit 7000 is built into a housing 7101.
  • the housing 7101 is supported by a stand 7103.
  • a display device can be applied to the display portion 7000.
  • the television device 7100 shown in FIG. 28D can be operated using an operation switch provided on the housing 7101 and a separate remote control 7111.
  • the display unit 7000 may be provided with a touch sensor, and the television device 7100 may be operated by touching the display unit 7000 with a finger or the like.
  • the remote control 7111 may have a display unit that displays information output from the remote control 7111.
  • the channel and volume can be operated using the operation keys or touch panel provided on the remote control 7111, and the image displayed on the display unit 7000 can be operated.
  • the television device 7100 is configured to include a receiver and a modem.
  • the receiver can receive general television broadcasts.
  • by connecting to a wired or wireless communication network via the modem it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.
  • FIG. 28E shows an example of a laptop personal computer.
  • the laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and a control device 7215.
  • a display portion 7000 is incorporated in the housing 7211.
  • the control device 7215 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be used for one or both of the display portion 7000 and the control device 7215.
  • FIG. 28F and 28G An example of digital signage is shown in Figures 28F and 28G.
  • the digital signage 7300 shown in FIG. 28F has a housing 7301, a display unit 7000, a speaker 7303, and the like. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, and the like.
  • Figure 28G shows a digital signage 7400 attached to a cylindrical pole 7401.
  • the digital signage 7400 has a display unit 7000 that is provided along the curved surface of the pole 7401.
  • a display device of one embodiment of the present invention can be applied to the display portion 7000.
  • the larger the display unit 7000 the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of, for example, advertisements.
  • a touch panel By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 can be made to execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • the semiconductor device and display device of one embodiment of the present invention can be applied to the vicinity of the driver's seat of an automobile, which is a moving object.
  • Figure 29A is a diagram showing the area around the windshield inside the vehicle.
  • Figure 29A shows display panels 9001a, 9001b, and 9001c attached to the dashboard, and display panel 9001d attached to a pillar.
  • the display panels 9001a to 9001c can provide various information by displaying navigation information, a speedometer, a tachometer, mileage, a fuel gauge, gear status, air conditioning settings, and the like.
  • the display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, improving the design.
  • the display panels 9001a to 9001c can also be used as lighting devices.
  • the display panel 9001d can display images from an imaging means installed on the vehicle body to complement the field of view (blind spots) blocked by the pillars. In other words, by displaying images from an imaging means installed on the outside of the vehicle, blind spots can be complemented and safety can be increased. In addition, by displaying images that complement the invisible parts, safety can be confirmed more naturally and without any sense of discomfort.
  • the display panel 9001d can also be used as a lighting device.
  • FIG 29B is a perspective view showing a wristwatch-type mobile information terminal 9200.
  • the mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark).
  • the display surface of the display unit 9001 is curved, and display can be performed along the curved display surface.
  • the mobile information terminal 9200 can also perform hands-free conversation by communicating with, for example, a headset capable of wireless communication.
  • the mobile information terminal 9200 can also perform data transmission with other information terminals and charge itself via a connection terminal 9006. Note that charging may be performed by wireless power supply.
  • the mobile information terminal 9200 shown in FIG. 29B has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared), a microphone 9008, etc.
  • FIG 29C is a perspective view of a foldable mobile information terminal 9201.
  • the mobile information terminal 9201 has a housing 9000a, a housing 9000b, a display portion 9001, and an operation button 9056.
  • the housings 9000a and 9000b are connected by a hinge 9055, which allows the device to be folded in half.
  • the display portion 9001 of the mobile information terminal 9201 is supported by two housings (housing 9000a and housing 9000b) connected by a hinge 9055.
  • Figures 29D to 29F are perspective views showing a foldable mobile information terminal 9202. Also, Figure 29D is a perspective view of the mobile information terminal 9202 in an unfolded state, Figure 29F is a folded state, and Figure 29E is a perspective view of the mobile information terminal 9202 in the process of changing from one of Figures 29D and 29F to the other. In this way, the mobile information terminal 9202 can be folded into three.
  • the display unit 9001 of the mobile information terminal 9202 is supported by three housings 9000 connected by hinges 9055.
  • the display device of one embodiment of the present invention can be applied to the display portion 9001.
  • the display portion 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.
  • the portable information terminal 9201 and the portable information terminal 9202 each have excellent portability when folded, and excellent display visibility when unfolded due to their seamless, large display areas.
  • the semiconductor device of one embodiment of the present invention can be reduced by applying the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO 2 ). In addition, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming because of its low power consumption.
  • CO 2 greenhouse gases
  • ADDR signal, BIL: wiring, BILB: wiring, BRL: wiring, BW: signal, CA: capacitance element, CAL: wiring, CB: capacitance element, CC: capacitance element, CE: signal, CLK: signal, Da: width, Db: width, Dc: width, GNDL: wiring, GW: signal, M10: transistor, MPG: conductive layer, MTCK: transistor, RBL: wiring, RDA: signal, RWL: wiring, SL: wiring, VDL: wiring, WAKE: signal, WBL: wiring, WDA: signal, WOL: wiring, 61B: light-emitting element, 61G: light-emitting element, 61 R: light-emitting element, 61W: light-emitting element, 100a: capacitive element, 100b: capacitive element, 100: capacitive element, 110: conductive layer, 115: conductive layer, 120: conductive layer, 130B: subpixel, 130G: subpixel, 130R: subpixel,

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PCT/IB2024/052585 2023-03-24 2024-03-18 半導体装置、及び、半導体装置の作製方法 Ceased WO2024201207A1 (ja)

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JP2008135474A (ja) * 2006-11-27 2008-06-12 Rohm Co Ltd 半導体装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
CN114792735A (zh) * 2021-01-26 2022-07-26 华为技术有限公司 薄膜晶体管、存储器及制作方法、电子设备

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KR101809105B1 (ko) 2010-08-06 2017-12-14 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 집적 회로
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CN114424339A (zh) 2019-09-20 2022-04-29 株式会社半导体能源研究所 半导体装置及半导体装置的制造方法

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JP2008135474A (ja) * 2006-11-27 2008-06-12 Rohm Co Ltd 半導体装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
CN114792735A (zh) * 2021-01-26 2022-07-26 华为技术有限公司 薄膜晶体管、存储器及制作方法、电子设备

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