WO2024189455A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024189455A1
WO2024189455A1 PCT/IB2024/052047 IB2024052047W WO2024189455A1 WO 2024189455 A1 WO2024189455 A1 WO 2024189455A1 IB 2024052047 W IB2024052047 W IB 2024052047W WO 2024189455 A1 WO2024189455 A1 WO 2024189455A1
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Prior art keywords
insulator
conductor
oxide semiconductor
oxide
transistor
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PCT/IB2024/052047
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
方堂涼太
遠藤俊弥
菊池秋広
井本裕己
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to KR1020257031840A priority Critical patent/KR20250154458A/ko
Priority to CN202480016548.7A priority patent/CN120883746A/zh
Priority to JP2025506066A priority patent/JPWO2024189455A1/ja
Publication of WO2024189455A1 publication Critical patent/WO2024189455A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional [2D] radiating surfaces
    • H05B33/14—Light sources with substantially two-dimensional [2D] radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
    • H10K50/115—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers comprising active inorganic nanostructures, e.g. luminescent quantum dots
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing the semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, or manufacturing methods thereof.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices, are one embodiment of semiconductor devices.
  • Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be said to have semiconductor devices.
  • a CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) that are chipped by processing a semiconductor wafer and on which electrodes that serve as connection terminals are formed.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.
  • transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices).
  • ICs integrated circuits
  • image display devices also simply referred to as display devices.
  • Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.
  • Patent Document 1 discloses a low-power consumption CPU that utilizes the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by utilizing the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple overlapping memory cells.
  • Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.
  • An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated.
  • An object of one embodiment of the present invention is to provide a semiconductor device with a large on-state current.
  • An object of one embodiment of the present invention is to provide a semiconductor device with a high operating speed.
  • An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.
  • An object of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics.
  • An object of one embodiment of the present invention is to provide a semiconductor device with less variation in the electrical characteristics of transistors.
  • An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.
  • An object of one embodiment of the present invention is to provide a new semiconductor device.
  • An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity.
  • An object of one embodiment of the present invention is to provide a method for manufacturing a new semiconductor device.
  • An object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated.
  • An object of one embodiment of the present invention is to provide a memory device with a large storage capacity.
  • An object of one embodiment of the present invention is to provide a memory device with a high operating speed.
  • An object of one embodiment of the present invention is to provide a memory device with low power consumption.
  • An object of one embodiment of the present invention is to provide a novel memory device.
  • One embodiment of the present invention includes a transistor and first to third insulators, the second insulator being disposed on the first insulator, and the third insulator being disposed on the second insulator, the transistor having a first conductor on the second insulator, a second conductor on the third insulator, an oxide semiconductor, a fourth insulator, and a third conductor, the third insulator and the second conductor having openings reaching the first conductor, and the oxide semiconductor is disposed on the top surface of the first conductor and
  • the semiconductor device has a first layer and a second layer on the first layer, the first layer is more conductive than the second layer, and the second layer is made of a metal oxide.
  • the fourth insulator is disposed on the oxide semiconductor so that at least a portion of the third conductor is located in the opening.
  • the second insulator has a function of capturing or fixing hydrogen.
  • the second conductor has a first layer and a second layer on the first layer, the first layer is more conductive than the second layer, and the second layer has a metal oxide.
  • the first layer contains ruthenium or tungsten.
  • the second layer contains indium.
  • the second insulator contains hafnium, silicon, and oxygen.
  • the first insulator and the third insulator contain silicon and nitrogen.
  • the first conductor has a third layer and a fourth layer on the third layer, the third layer being more conductive than the fourth layer, and the fourth layer having a metal oxide.
  • the third layer contains tungsten.
  • the fourth layer contains indium.
  • the fourth layer contains tin and silicon, and that the fourth layer has an amorphous structure.
  • Another aspect of the present invention is a transistor having a first insulator and a second insulator, the transistor having a first conductor, a second conductor on the first conductor and the first insulator, an oxide semiconductor, a third insulator, and a third conductor, the third insulator and the second conductor having an opening reaching the first conductor, the oxide semiconductor being in contact with an upper surface of the first conductor and an upper surface of the second conductor, and the third insulator being arranged so that at least a portion of the third insulator is located in the opening.
  • a third conductor is disposed on the third insulator so that at least a portion of the third conductor is located in the opening, the second insulator is disposed between the first insulator and the second conductor and the oxide semiconductor in the opening, the second conductor has a first layer and a second layer on the first layer, the first layer has a higher conductivity than the second layer, the second layer has a metal oxide, and one side of the second insulator is in contact with at least a side of the first layer.
  • the first layer contains ruthenium or tungsten.
  • the second layer contains indium.
  • the second layer contains tin and silicon, and that the second layer has an amorphous structure.
  • the height of the upper end of the second insulator can be configured to be lower than the height of the upper surface of the second layer.
  • one side of the second insulator contacts the first insulator and the other side of the second insulator contacts the oxide semiconductor.
  • the second insulator contains silicon and nitrogen.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a semiconductor device with a large on-state current can be provided.
  • a semiconductor device with a high operating speed can be provided.
  • a semiconductor device with high reliability can be provided.
  • a semiconductor device with good electrical characteristics can be provided.
  • a semiconductor device with less variation in the electrical characteristics of transistors can be provided.
  • a semiconductor device with low power consumption can be provided.
  • a novel semiconductor device can be provided.
  • a method for manufacturing a semiconductor device with high productivity can be provided.
  • a method for manufacturing a novel semiconductor device can be provided.
  • a memory device that can be miniaturized or highly integrated can be provided.
  • a memory device with a large storage capacity can be provided.
  • a memory device with a high operating speed can be provided.
  • a memory device with low power consumption can be provided.
  • a novel memory device can be provided.
  • Fig. 1A is a plan view showing an example of a semiconductor device
  • Figs. 1B to 1D are cross-sectional views showing an example of the semiconductor device.
  • 2A and 2B are cross-sectional views showing an example of a semiconductor device.
  • 3A and 3B are cross-sectional views showing an example of a semiconductor device.
  • 4A to 4E are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 5A to 5D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 6A and 6B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 7A to 7D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • Fig. 1A is a plan view showing an example of a semiconductor device
  • Figs. 1B to 1D are cross-sectional views showing an example of the semiconductor device.
  • 2A and 2B are cross-sectional views
  • FIG. 8A is a plan view showing an example of a semiconductor device
  • Figs. 8B to 8D are cross-sectional views showing an example of the semiconductor device.
  • 9A is a plan view showing an example of a semiconductor device
  • FIGS. 9B to 9D are cross-sectional views showing an example of the semiconductor device.
  • 10A and 10B are cross-sectional views showing an example of a semiconductor device.
  • Fig. 11A is a plan view showing an example of a semiconductor device
  • Figs. 11B to 11D are cross-sectional views showing an example of the semiconductor device.
  • 12A and 12B are cross-sectional views showing an example of a semiconductor device.
  • Fig. 13A is a plan view showing an example of a semiconductor device
  • Figs. 13A is a plan view showing an example of a semiconductor device
  • Figs. 13A is a plan view showing an example of a semiconductor device
  • Figs. 13A is a plan view showing an example of a semiconductor
  • FIG. 13B to 13D are cross-sectional views showing an example of the semiconductor device.
  • 14A and 14B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • Fig. 15A is a plan view showing an example of a semiconductor device
  • Figs. 15B to 15D are cross-sectional views showing an example of the semiconductor device.
  • 16A and 16B are plan and cross-sectional views illustrating an example of a semiconductor device.
  • FIG. 17 is a block diagram illustrating a configuration example of a semiconductor device.
  • 18A to 18H are diagrams for explaining examples of the circuit configuration of a memory cell.
  • 19A and 19B are perspective views illustrating a configuration example of a semiconductor device.
  • FIG. 20 is a block diagram illustrating the CPU.
  • 21A and 21B are perspective views of a semiconductor device.
  • 22A and 22B are perspective views of a semiconductor device.
  • 23A and 23B are diagrams showing various storage devices by hierarchical level.
  • 24A and 24B are diagrams showing an example of electronic equipment
  • FIGS. 24C to 24E are diagrams showing an example of a mainframe computer.
  • FIG. 25 is a diagram showing an example of space equipment.
  • FIG. 26 is a diagram illustrating an example of a storage system that can be applied to a data center.
  • 27A and 27B show configuration examples of a display device.
  • FIG. 28 shows an example of the configuration of a display device.
  • FIG. 29 shows an example of the configuration of a display device.
  • 30A to 30C show configuration examples of the display device.
  • FIG. 31A and 31B show configuration examples of a display device.
  • 32A to 32D show configuration examples of electronic devices.
  • 33A to 33F show configuration examples of electronic devices.
  • 34A to 34G show configuration examples of electronic devices.
  • FIG. 35 is a diagram showing the measurement results of the contact resistance according to this example.
  • 36A and 36B are cross-sectional SEM images of a sample according to this example.
  • FIG. 37 shows a cross-sectional STEM image and an FFT image according to this embodiment.
  • FIG. 38 shows a cross-sectional STEM image and an FFT image according to this embodiment.
  • FIG. 39 is a cross-sectional STEM image of the sample according to this example.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking).
  • an ordinal number attached to a component in one place in this specification may not match an ordinal number attached to the same component in another place in this specification or in the claims.
  • film and “layer” can be interchanged depending on the circumstances.
  • the term “conductive layer” can be changed to the term “conductive film”.
  • the term “insulating film” can be changed to the term “insulating layer”.
  • the term “conductor” can be interchanged with the term “conductive layer” or the term “conductive film” depending on the circumstances.
  • the term “insulator” can be interchanged with the term “insulating layer” or the term “insulating film” depending on the circumstances.
  • oxide semiconductor can be interchanged with the term “oxide semiconductor layer” or the term “oxide semiconductor film” depending on the circumstances.
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less.
  • approximately parallel refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • Perfect refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less.
  • approximately perpendicular refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • Openings include, for example, grooves, slits, and recesses. Also, the area in which an opening is formed may be referred to as an opening.
  • the sidewalls of the opening of the insulator are shown as being perpendicular or approximately perpendicular to the substrate surface or the surface on which the insulator is formed, but they may also be tapered.
  • a tapered shape refers to a shape in which at least a portion of the side of a structure is inclined relative to the substrate surface or the surface on which the structure is to be formed.
  • a tapered structure has a region in which the angle between the inclined side and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°.
  • the side of the structure and the substrate surface do not necessarily need to be completely flat, but may be approximately planar with a slight curvature, or approximately planar with minute irregularities.
  • a reverse tapered shape refers to a shape having a side or top that protrudes in a direction parallel to the substrate more than the bottom.
  • “same height” refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are equal in cross-sectional view.
  • a planarization process typically a chemical mechanical polishing (CMP) process
  • CMP chemical mechanical polishing
  • the surfaces treated in the CMP process have a configuration in which the heights from the reference surface are equal.
  • the heights of multiple layers may differ depending on the processing device, processing method, or material of the processed surface during the CMP process. In this specification, this case is also treated as "same height".
  • first layer and a second layer when there are two layers (here, a first layer and a second layer) with different heights relative to the reference surface, and the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, this is also referred to as "same height”.
  • side edges coincide means that at least a portion of the contours of the stacked layers overlap when viewed in a plane. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer, in which case it is also referred to as "side edges coincide”.
  • the first film thickness and the second film thickness being the same means that the absolute value of the difference between the first film thickness and the second film thickness divided by the first film thickness is 0.1 or less. Alternatively, it means that the absolute value of the difference between the first film thickness and the second film thickness divided by the second film thickness is 0.1 or less.
  • distance A and distance B are the same means that the absolute value of the difference between distance A and distance B divided by distance A is 0.1 or less. Or, the absolute value of the difference between distance A and distance B divided by distance B is 0.1 or less.
  • FIGS. 1A to 1D are plan views and cross-sectional views of a semiconductor device including a transistor 200.
  • FIG. 1A is a plan view of the semiconductor device.
  • FIGS. 1B to 1D are cross-sectional views of the semiconductor device.
  • FIG. 1B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A.
  • FIG. 1C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1A. Note that some elements are omitted from the plan view of FIG. 1A for clarity.
  • FIGS. 3A and 3B are enlarged views corresponding to FIG. 1B.
  • arrows indicating the X-direction, Y-direction, and Z-direction may be used.
  • the "X-direction” refers to the direction along the X-axis, and may not distinguish between the forward direction and the reverse direction unless otherwise specified. The same applies to the "Y-direction” and "Z-direction”.
  • the X-direction, Y-direction, and Z-direction are directions that intersect with each other.
  • the X-direction, Y-direction, and Z-direction are directions that are perpendicular to each other.
  • one of the X-direction, Y-direction, and Z-direction may be called the "first direction” or “first direction”.
  • the other may be called the “second direction” or “second direction”.
  • the remaining one may be called the "third direction” or "third direction”.
  • the semiconductor device shown in Figures 1A to 1D has an insulator 210 on a substrate (not shown), an insulator 222 on the insulator 210, a transistor 200 on the insulator 222, an insulator 280 on the insulator 222, and an insulator 283 on the transistor 200.
  • the insulators 210, 222, and 280 function as interlayer films.
  • the transistor 200 has a conductor 220 on the insulator 222, a conductor 240 on the insulator 280, an oxide semiconductor 230 in contact with at least a portion of the top surface of the conductor 220, an insulator 250 on the oxide semiconductor 230, and a conductor 260 on the insulator 250.
  • the conductor 240 also has a conductor 240a and a conductor 240b on the conductor 240a.
  • the insulator 280 and the conductor 240 have openings 290 that reach the conductor 220.
  • the bottom of the opening 290 is the top surface of the conductor 220
  • the side walls of the opening 290 are the side surfaces of the insulator 280 and the conductor 240.
  • the opening 290 includes an opening in the insulator 280 and an opening in the conductor 240. In other words, the opening in the area where the insulator 280 overlaps with the conductor 220 is one part of the opening 290, and the opening in the area where the conductor 240 overlaps with the conductor 220 is another part of the opening 290.
  • At least some of the components of the transistor 200 are disposed in the opening 290.
  • the oxide semiconductor 230, the insulator 250, and the conductor 260 are each disposed such that at least a portion of each of them is located in the opening 290.
  • the portions of the oxide semiconductor 230 and the insulator 250 that are to be placed in the opening 290 are provided to reflect the shape of the opening 290.
  • the oxide semiconductor 230 is provided to cover the bottom and sidewalls of the opening 290
  • the insulator 250 is provided to cover the oxide semiconductor 230.
  • the conductor 260 is provided to fill the recess of the insulator 250 that reflects the shape of the opening 290.
  • the oxide semiconductor 230 functions as a semiconductor layer
  • the conductor 260 functions as a gate electrode
  • the insulator 250 functions as a gate insulator
  • the conductor 220 functions as one of the source electrode and drain electrode
  • the conductor 240 functions as the other of the source electrode and drain electrode.
  • the oxide semiconductor 230 is provided inside the opening of the insulator 280.
  • the transistor 200 has a configuration in which one of the source electrode and drain electrode (here, the conductor 220) is located on the bottom and the other of the source electrode and drain electrode (here, the conductor 240) is located on the top, so that current flows in the vertical direction. In other words, a channel is formed along the side of the opening of the insulator 280.
  • the transistor 200 preferably uses a metal oxide (also called an oxide semiconductor) that functions as a semiconductor for the oxide semiconductor 230 including the channel formation region. In this case, the transistor 200 becomes an OS transistor.
  • a metal oxide also called an oxide semiconductor
  • oxygen vacancies ( VO ) and impurities are present in a channel formation region in an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate and the reliability may be reduced. Hydrogen near the oxygen vacancies may form defects in which hydrogen is inserted into the oxygen vacancies (hereinafter, these may be referred to as VOH ), and may generate electrons that serve as carriers. For this reason, when the channel formation region in the oxide semiconductor contains oxygen vacancies, the OS transistor is likely to have normally-on characteristics. Therefore, in the channel formation region in the oxide semiconductor, oxygen vacancies and hydrogen, which is one of the impurities, are preferably reduced as much as possible.
  • the channel formation region in the oxide semiconductor is preferably made i-type (intrinsic) or substantially i-type by reducing the carrier concentration.
  • the oxide semiconductor when an excessive amount of oxygen is supplied to the oxide semiconductor, electron traps due to the excess oxygen are formed in the gate insulating film. This may cause the OS transistor to have excessively normally-off characteristics.
  • the normally-on characteristic refers to a state in which a channel exists even when no voltage is applied to the gate, and current flows between the source and drain of a transistor.
  • the normally-off characteristic refers to a state in which no current flows between the source and drain of a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.
  • the source and drain regions of an OS transistor are preferably regions having more oxygen vacancies, more VOH , or a higher concentration of impurities such as hydrogen, nitrogen, or metal elements than the channel formation region, thereby increasing the carrier concentration and lowering the resistance. That is, the source and drain regions of an OS transistor are preferably n-type regions having a higher carrier concentration and lower resistance than the channel formation region.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor measured by secondary ion mass spectrometry is preferably less than 1 ⁇ 10 20 atoms/cm 3 , more preferably less than 5 ⁇ 10 19 atoms/cm 3, still more preferably less than 1 ⁇ 10 19 atoms/cm 3 , still more preferably less than 5 ⁇ 10 18 atoms/cm 3 , still more preferably less than 1 ⁇ 10 18 atoms/cm 3 , and still more preferably less than 1 ⁇ 10 17 atoms/cm 3 .
  • the insulator 210 and the insulator 283 are preferably barrier insulators against hydrogen.
  • the insulator 210 and the insulator 283 are provided to sandwich the transistor 200 including the oxide semiconductor 230.
  • the insulator 210 and the insulator 283 provided on the outside of the oxide semiconductor 230 have a barrier property against hydrogen, the diffusion of hydrogen into the oxide semiconductor 230 can be suppressed.
  • a barrier insulator refers to an insulator having barrier properties.
  • the barrier properties refer to a property that a corresponding substance is difficult to diffuse (also referred to as a property that a corresponding substance is difficult to permeate, a property that the permeability of a corresponding substance is low, or a function of suppressing the diffusion of a corresponding substance).
  • hydrogen refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁇ .
  • impurities when impurities are described as a corresponding substance, they refer to impurities in a channel formation region or a semiconductor layer, unless otherwise specified, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2 , etc.), a copper atom, etc.
  • oxygen when oxygen is described as a corresponding substance, it refers to at least one of, for example, an oxygen atom, an oxygen molecule, etc.
  • Barrier insulators against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon oxide-nitride.
  • the insulator 210 and the insulator 283 contain silicon and nitrogen.
  • Silicon nitride which can be used as insulator 210 and insulator 283, has barrier properties against hydrogen if the film thickness is, for example, 2 nm or more.
  • the silicon nitride film thickness is preferably 3 nm or more, and more preferably 5 nm or more.
  • Silicon nitride has barrier properties against oxygen if the film thickness is, for example, 1 nm or more.
  • the silicon nitride film thickness is preferably 2 nm or more. In other words, silicon nitride formed with a film thickness that has barrier properties against hydrogen also has barrier properties against oxygen.
  • the insulator 222 is preferably an insulator having a function of trapping or fixing hydrogen.
  • the hydrogen concentration in the oxide semiconductor 230 located inside the insulator 210 and the insulator 283 can be reduced.
  • hydrogen in the oxide semiconductor 230 is trapped or fixed by the insulator 222, so that the hydrogen concentration in the insulator 222 is high.
  • the hydrogen concentration in at least a part of the insulator 222 obtained by SIMS may be 1 ⁇ 10 19 atoms/cm 3 or more or 1 ⁇ 10 20 atoms/cm 3 or more.
  • the hydrogen concentration in at least a part of the insulator 222 is higher than the hydrogen concentration in the oxide semiconductor 230.
  • the oxide semiconductor 230 has a region where the hydrogen concentration is lower than the hydrogen concentration in the insulator 222.
  • the ability to capture or adhere to a corresponding substance can also be said to be a property that makes it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or adhere to a corresponding substance can be rephrased as a barrier property.
  • a metal oxide containing hafnium or the like e.g., hafnium oxide, etc.
  • the above metal oxide preferably has oxygen atoms with dangling bonds.
  • Such metal oxides may have the property of capturing or fixing hydrogen with dangling bonds.
  • the above metal oxide preferably has an amorphous structure. This is because in metal oxides with an amorphous structure, some oxygen atoms have dangling bonds.
  • the above metal oxide preferably has an amorphous structure, but crystalline regions may be formed in some parts. Furthermore, the above metal oxide may have crystal grain boundaries in some parts.
  • hafnium silicate an oxide containing hafnium and silicon (hereinafter, sometimes referred to as hafnium silicate) tends to have an amorphous structure. Therefore, hafnium silicate has the property of capturing or adhering hydrogen, making it suitable as insulator 222. In this case, insulator 222 contains hafnium, silicon, and oxygen.
  • the ratio of silicon to hafnium and silicon in the insulator 222 is 0.1 atomic% or more and less than 100 atomic%, preferably 0.1 atomic% or more and 70 atomic% or less, more preferably 0.1 atomic% or more and 50 atomic% or less, more preferably 0.1 atomic% or more and 30 atomic% or less, more preferably 1 atomic% or more and 10 atomic% or less, and more preferably 3 atomic% or more and 8 atomic% or less.
  • the silicon composition ratio in the hafnium silicate can be quantified, for example, by X-ray photoelectron spectroscopy (XPS) measurement.
  • hafnium silicate may contain metals such as zirconium, and the metals may be included in the measurement. In this case, the sum of the composition ratios of hafnium, silicon, and zirconium may be normalized to be 100 atomic %.
  • oxides containing hafnium are listed as insulators having the function of capturing or fixing hydrogen, but the present invention is not limited to this.
  • oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), etc. may be listed.
  • the above metal oxides may further contain oxides containing zirconium.
  • oxides containing hafnium and zirconium, etc. it is preferable that these metal oxides have silicon added and have an amorphous structure.
  • the insulator 222 can capture or fix hydrogen released from the oxide semiconductor 230 by performing a heat treatment.
  • the insulator 222 and the oxide semiconductor 230 are preferably provided in a closed system consisting of the insulator 210 and the insulator 283, which have a barrier property against hydrogen. This makes it possible to prevent hydrogen from diffusing from the outside to the inside or from the inside to the outside of the closed system during the heat treatment, since the frequency of hydrogen movement between the inside and outside of the closed system is extremely low. Therefore, the hydrogen concentration in the oxide semiconductor 230 can be reduced by capturing or fixing hydrogen in the closed system to the insulator 222.
  • the closed system is a barrier insulator against hydrogen that covers at least a part of the oxide semiconductor and reduces hydrogen diffusing from the outside to the inside or from the inside to the outside of the closed system.
  • the part that functions as a channel formation region of the oxide semiconductor is located inside the barrier insulator against hydrogen.
  • the barrier insulator against hydrogen is preferably provided so as to extend in the channel length direction of the oxide semiconductor, and the oxide semiconductor is provided so as to be surrounded or sandwiched between the barrier insulator against hydrogen. Note that the above closed system does not completely block the movement of hydrogen, but only needs to reduce the frequency of hydrogen movement. Therefore, the above closed system is not completely closed, and there are cases where a part or multiple parts are open.
  • an oxide semiconductor with few oxygen vacancies and impurities can be provided. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved. In addition, a semiconductor device with little variation in the electrical characteristics of the transistor can be provided.
  • the above structure can suppress the formation of oxygen vacancies in the channel formation region and the diffusion of hydrogen into the channel formation region. This can suppress the variation in the amount of oxygen vacancies and hydrogen concentration in the channel formation region from transistor to transistor. Therefore, the variation in the electrical characteristics of the transistors can be reduced.
  • the insulator 280 may be a single layer or a stack of insulators described in the section [Insulators] described later.
  • the sidewalls of the opening 290 are preferably perpendicular to the top surface of the insulator 210. This configuration allows for miniaturization or high integration of the semiconductor device.
  • the opening 290 is provided so that the sidewall of the opening 290 is perpendicular to the top surface of the conductor 220, but the present invention is not limited to this.
  • the sidewall of the opening 290 may not be strictly perpendicular and may have a tapered shape.
  • the taper angle formed between the side surface of the insulator 280, which is part of the sidewall of the opening 290, and the top surface of the conductor 220 (which may be the top surface of the insulator 222 or the top surface of the insulator 210) is defined as angle ⁇ 1.
  • the angle ⁇ 1 is 90 degrees or close to 90 degrees.
  • the angle ⁇ 1 is 75 degrees or more and 90 degrees or less.
  • angle ⁇ 1 may be less than 75 degrees, less than 70 degrees, less than 65 degrees, or less than 60 degrees.
  • the oxide semiconductor 230 has a region that contacts the side surface of the conductor 240 in the opening 290, and a region that contacts at least a portion of the top surface of the conductor 240. In this way, the oxide semiconductor 230 contacts not only the side surface but also the top surface of the conductor 240, so that the area of contact between the oxide semiconductor 230 and the conductor 240 can be increased. In addition, the oxide semiconductor 230 has a region that contacts the top surface of the conductor 220 exposed in the opening 290, and a region that contacts the side surface of the insulator 280 in the opening 290.
  • a portion of the oxide semiconductor 230 is located outside the opening 290, i.e., above the conductor 240.
  • Figure 1B shows a configuration in which the oxide semiconductor 230 is divided in the X direction
  • the present invention is not limited to this.
  • the oxide semiconductor 230 may be provided extending in the X direction. Note that even in this case, the oxide semiconductor 230 is divided in the Y direction.
  • FIG. 1C also shows a configuration in which the side end of the oxide semiconductor 230 is located inside the side end of the conductor 240.
  • the present invention is not limited to this.
  • a structure in which the side end of the oxide semiconductor 230 and the side end of the conductor 240 coincide in the Y direction may be used.
  • a structure in which the side end of the oxide semiconductor 230 is located outside the side end of the conductor 240 may be used.
  • the insulator 250 is provided in contact with the upper surface of the oxide semiconductor 230.
  • the insulator 250 has a region in contact with the upper surface of the conductor 240, a region in contact with the side surface of the conductor 240, and a region in contact with the insulator 280.
  • a portion of the insulator 250 is located outside the opening 290, i.e., above the conductor 240 and the insulator 280. At this time, it is preferable that the insulator 250 covers the side end of the oxide semiconductor 230. This can prevent the conductor 260 and the oxide semiconductor 230 from shorting out. It is also preferable that the insulator 250 covers the side end of the conductor 240. This can prevent the conductor 260 and the conductor 240 from shorting out.
  • a portion of the conductor 260 is located outside the opening 290, that is, above the conductor 240 and the insulator 280.
  • the side end of the conductor 260 is located inside the side end of the oxide semiconductor 230. This makes it possible to prevent a short circuit between the conductor 260 and the oxide semiconductor 230.
  • the side end of the conductor 260 may coincide with the side end of the oxide semiconductor 230, or may be located outside the side end of the oxide semiconductor 230.
  • the conductor 260 is provided so as to fill the opening 290, but the present invention is not limited to this.
  • a recess reflecting the shape of the opening 290 may be formed in the conductor 260, and a part of the recess may be located in the opening 290.
  • the recess may be filled with an inorganic insulating material or the like.
  • the conductor 240 has an opening in a region overlapping with the conductor 220. Moreover, it is preferable that the conductor 240 is not provided inside the opening of the insulator 280. In other words, it is preferable that the conductor 240 does not have a region in contact with the side surface of the insulator 280 in the opening 290. With this configuration, the opening of the conductor 240 and the opening of the insulator 280 can be formed at the same time. Furthermore, by configuring the side surface of the conductor 240 in the opening 290 and the side surface of the insulator 280 in the opening 290 to be flush with each other, the film thickness distribution of the oxide semiconductor 230 provided inside the opening 290 can be made uniform. Furthermore, it is possible to prevent the oxide semiconductor 230 from being divided by the step between the conductor 240 and the insulator 280.
  • FIG. 1B and 1C show a configuration in which the side surface of the conductor 240 in the opening 290 and the side surface of the insulator 280 in the opening 290 are flush with each other, but the present invention is not limited to this.
  • the side surface of the conductor 240 in the opening 290 and the side surface of the insulator 280 in the opening 290 may be discontinuous.
  • the inclination of the side surface of the conductor 240 in the opening 290 and the inclination of the side surface of the insulator 280 in the opening 290 may be different from each other.
  • the angle formed between the side surface of the conductor 240 in the opening 290 and the upper surface of the insulator 210 is smaller than the angle formed between the side surface of the insulator 280 in the opening 290 and the upper surface of the insulator 210.
  • the conductor 240 preferably has a laminated structure.
  • the conductor 240 preferably has a laminated structure of a conductor 240a and a conductor 240b in contact with the upper surface of the conductor 240a.
  • the bottom surface of the conductor 240a is in contact with the insulator 280, one side surface is in contact with the oxide semiconductor 230, and the other side surface is in contact with the insulator 250.
  • the conductor 240a is preferably made of a metal having a higher conductivity than the conductor 240b.
  • the conductor 240a is preferably made of a metal having a lower sheet resistance than the conductor 240b. With this configuration, the conductor 240 including the conductor 240a can function as a wiring electrically connected to one of the source electrode or the drain electrode.
  • the conductor 240a may be one or more of ruthenium, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, aluminum, chromium, copper, silver, gold, platinum, zinc, manganese, iron, cobalt, magnesium, zirconium, beryllium, indium, iridium, strontium, and lanthanum, or an alloy containing one or more of the aforementioned metals.
  • the conductor 240b has one side and a part of the top surface in contact with the oxide semiconductor 230. The other side and another part of the top surface of the conductor 240b are in contact with the insulator 250.
  • the conductor 240b preferably has ohmic contact with the oxide semiconductor 230 and preferably has low contact resistance with the oxide semiconductor 230.
  • the contact resistance between the conductor 240b and the oxide semiconductor 230 is preferably lower than the contact resistance between the metal layer used in the conductor 240a and the oxide semiconductor 230.
  • the conductor 240b is preferably made of a metal oxide having conductivity (sometimes referred to as a conductive oxide).
  • Conductive oxides (OC: Oxide Conductor, also called conductive materials containing oxygen) used for the conductor 240b are preferably conductive oxides containing indium.
  • conductive oxides containing indium it is preferable to use indium oxide, indium tin oxide (sometimes called ITO), indium zinc oxide, indium tin oxide with added silicon (also called ITSO), etc.
  • Indium oxide may also contain tungsten or titanium, for example, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, etc.
  • Conductive oxides containing zinc may also be used, for example, zinc oxide, zinc oxide with added gallium, In-Ga-Zn oxide, etc.
  • Ruthenium oxide, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. can also be used as conductive oxides.
  • conductive oxides containing indium are preferable because of their high conductivity.
  • indium tin oxide with silicon added may be used for the conductor 240b.
  • the conductor 240b contains indium, tin, silicon, and oxygen.
  • silicon By adding silicon to the indium tin oxide, the polycrystallization of the indium tin oxide can be suppressed.
  • indium tin oxide with silicon added is likely to have an nc structure (nanocrystal structure) or an amorphous structure.
  • Polycrystallized indium tin oxide may also be used for the conductor 240b. In this case, the conductor 240b contains indium, tin, and oxygen.
  • oxygen in the conductor 240b diffuses to the vicinity of the interface with the conductor 240a, and oxygen vacancies (V O ) are formed in the conductor 240b. Furthermore, oxygen in the oxide semiconductor 230 near the conductor 240 diffuses to the vicinity of the interface with the conductor 240b and the conductor 240a where the oxygen vacancies (V O ) are formed, and oxygen vacancies (V O ) are formed in a region of the oxide semiconductor 230 near the conductor 240.
  • the reduced-resistance region functions as one of the source region and the drain region of the transistor 200.
  • silicon nitride for the insulator 280 the region in which VOH of the oxide semiconductor 230 is formed can be prevented from spreading excessively into the region below the conductor 240a. In other words, one of the source region and the drain region can be prevented from spreading excessively into the region below the conductor 240a.
  • the conductor 240 has a two-layer laminate structure of the conductor 240a and the conductor 240b, but the present invention is not limited to this.
  • the conductor 240 may have a laminate structure of three or more layers.
  • the conductor 220 may be any of the conductors described in the section below under [Conductor], in a single layer or in a multilayer configuration. It is preferable to use a conductive material that is not easily oxidized or a conductive material that has the function of suppressing the diffusion of oxygen as the conductor 220. For example, titanium nitride or tantalum nitride may be used.
  • the conductor 220 may have a layered structure of conductor 220a and conductor 220b on conductor 220a.
  • the conductor 220a is made of a metal with high conductivity similar to that of the conductor 240a. Therefore, the conductor 220a may be made of a metal that can be used for the conductor 240a. For example, tungsten may be used for the conductor 220a.
  • the conductor 220 including the conductor 220a can function as a wiring electrically connected to the other of the source electrode or the drain electrode.
  • the conductor 220b is preferably made of the same conductive oxide as the conductor 240b. Therefore, the conductor 220b may be made of a conductive oxide that can be used for the conductor 240b. For example, indium tin oxide with silicon added may be used for the conductor 220b. In this case, the conductor 220b contains indium, tin, silicon, and oxygen. With this configuration, the on-current, field effect mobility, and frequency characteristics of the transistor 200 can be improved.
  • oxygen in the conductor 220b diffuses to the vicinity of the interface with the conductor 220a, and oxygen vacancies (V O ) are formed in the conductor 220b. Furthermore, oxygen in the oxide semiconductor 230 near the conductor 220 diffuses to the vicinity of the interface with the conductor 220b and the conductor 220a where the oxygen vacancies (V O ) are formed, and oxygen vacancies (V O ) are formed in a region of the oxide semiconductor 230 near the conductor 220.
  • the reduced-resistance region functions as the other of the source region and drain region of the transistor 200.
  • the insulator 222 disposed under the conductor 220 captures hydrogen in the oxide semiconductor 230 through the conductor 220 by the heat treatment. At this time, hydrogen in the channel formation region of the oxide semiconductor 230 diffuses to the other of the source region and the drain region, so that VOH can be formed more efficiently in the other of the source region and the drain region.
  • the region of the oxide semiconductor 230 where VOH is formed can be prevented from spreading excessively into the region above the conductor 220b.
  • the other of the source region and the drain region can be prevented from spreading excessively into the region above the conductor 220b.
  • FIG. 1B and 1C show a configuration in which the upper surface of the conductor 220 is flat, but the present invention is not limited to this.
  • a configuration may be used in which a recess overlapping the opening 290 is formed on the upper surface of the conductor 220.
  • the oxide semiconductor 230 has a channel formation region between one of the source region and the drain region and the other.
  • one of the source region and the drain region includes at least a part of a region of the oxide semiconductor 230 that is in contact with the conductor 240.
  • the other of the source region and the drain region includes at least a part of a region of the oxide semiconductor 230 that is in contact with the conductor 220.
  • the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 between the conductor 220 and the conductor 240. It can also be said that the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 that is in contact with the insulator 280 or in a region nearby the region.
  • FIG. 1D shows a cross-sectional view in the XY plane including the insulator 280.
  • the insulator 280 contacts the entire outer periphery of the oxide semiconductor 230. Therefore, the channel formation region of the transistor 200 can be formed on the entire outer periphery of the portion of the oxide semiconductor 230 that is formed in the same layer as the insulator 280.
  • FIG. 1D can also be said to be a cross-sectional view in the XY plane including the channel formation region of the oxide semiconductor 230.
  • the channel length of the transistor 200 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulator 280 on the conductor 220.
  • the channel length L of the transistor 200 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L is the distance between the end of the region where the oxide semiconductor 230 and the conductor 220 contact each other and the end of the region where the oxide semiconductor 230 and the conductor 240 contact each other. In other words, the channel length L corresponds to the length of the side surface of the insulator 280 on the opening 290 side in a cross-sectional view.
  • the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult, but in the present invention, the channel length can be set by the film thickness of the insulator 280. Therefore, the channel length L of the transistor 200 can be made into a very fine structure below the exposure limit of photolithography (for example, 500 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-current of the transistor 200, improving the frequency characteristics.
  • the exposure limit of photolithography for example, 500 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 n
  • a channel formation region, a source region, and a drain region can be formed in the opening 290. This can reduce the area occupied by the transistor 200 compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This can enable high integration of the semiconductor device. Furthermore, when the semiconductor device of one embodiment of the present invention is used for a memory device, the memory capacity per unit area can be increased.
  • the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged concentrically. Therefore, the side surface of the conductor 260 arranged at the center faces the side surface of the oxide semiconductor 230 through the insulator 250. That is, in a plan view, the entire circumference of the oxide semiconductor 230 becomes a channel formation region.
  • the length of the outer circumference of the oxide semiconductor 230 determines the channel width of the transistor 200. That is, it can be said that the channel width of the transistor 200 is determined by the maximum width of the opening 290 (the diameter when the opening 290 is circular in a plan view).
  • the maximum width D of the opening 290 is indicated by a double-headed arrow of a two-dot chain line.
  • the channel width W of the transistor 200 is indicated by a double-dot chain line of a single-dot chain line.
  • the maximum width D of the opening 290 is limited by the exposure limit of photolithography.
  • the maximum width D of the opening 290 is set by the film thickness of each of the oxide semiconductor 230, the insulator 250, and the conductor 260 provided in the opening 290.
  • the maximum width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less.
  • the maximum width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D x ⁇ ".
  • the channel length L of the transistor 200 is preferably at least smaller than the channel width W of the transistor 200.
  • the channel length L of the transistor 200 according to one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a configuration, a transistor having good electrical characteristics and high reliability can be realized.
  • the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged concentrically. This makes the distance between the conductor 260 and the oxide semiconductor 230 roughly uniform, so that a gate electric field can be applied roughly uniformly to the oxide semiconductor 230.
  • the opening 290 is circular in plan view, but the present invention is not limited to this.
  • the opening 290 may be approximately circular such as an ellipse in plan view, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners.
  • the maximum width of the opening 290 can be calculated appropriately according to the shape of the top of the opening 290. For example, if the opening is rectangular in plan view, the maximum width of the opening 290 can be the length of the diagonal line at the top of the opening 290.
  • the metal oxides described in the section [Metal Oxides] below can be used in a single layer or a multilayer structure.
  • the composition close thereto includes a range of ⁇ 30% of the desired atomic ratio. It is also preferable to use one or more of gallium, aluminum, and tin as the element M.
  • the oxide semiconductor 230 may not contain the element M.
  • the metal oxide used as the oxide semiconductor 230 may be an In-Zn oxide.
  • indium oxide may be used as the oxide semiconductor 230.
  • the oxide semiconductor 230 may also have a composition containing a trace amount of the element M.
  • the composition of the metal oxide used in the oxide semiconductor 230 can be analyzed using, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES).
  • EDX energy dispersive X-ray spectroscopy
  • XPS X-ray photoelectron spectroscopy
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • a combination of these techniques may be used for the analysis.
  • the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • the metal oxide can be formed preferably by sputtering or atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the composition of the formed metal oxide may differ from the composition of the sputtering target.
  • the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.
  • Examples of the ALD method include the Thermal ALD method, in which the reaction between the precursor and reactant is carried out using only thermal energy, and the Plasma Enhanced ALD (PEALD) method, in which a plasma-excited reactant is used.
  • Thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy
  • PEALD Plasma Enhanced ALD
  • the ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios or surfaces with large steps; films can be formed with few defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures.
  • the PEALD method may be preferable because it uses plasma, which allows films to be formed at lower temperatures.
  • some precursors used in the ALD method contain elements such as carbon or chlorine.
  • films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Note that the quantification of these elements can be performed using XPS or SIMS.
  • the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but adopts one or both of the conditions of a high substrate temperature during film formation and the implementation of an impurity removal process, so the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without applying these.
  • the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece, unlike a film formation method in which particles released from a target are deposited. Therefore, it is a film formation method that is not easily affected by the shape of the workpiece and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as a sputtering method or a CVD method, which have a fast film formation speed.
  • the metal oxide has a layered structure of a first metal oxide and a second metal oxide
  • a method of forming a film of the first metal oxide using a sputtering method and forming a film of the second metal oxide on the first metal oxide using an ALD method can be mentioned.
  • the first metal oxide has a crystal part
  • the second metal oxide may grow as a crystal with the crystal part as a nucleus.
  • the ALD method can control the composition of the resulting film by adjusting the amount of source gas introduced.
  • the ALD method can form a film of any composition by adjusting the amount of source gas introduced, the number of times it is introduced (also called the number of pulses), the time required for one pulse (also called the pulse time), and the like.
  • the ALD method can form a film whose composition changes continuously by changing the source gas while forming the film.
  • the time required for film formation can be shortened compared to forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.
  • the method for forming the oxide semiconductor film that becomes the oxide semiconductor 230 is not particularly limited.
  • the oxide semiconductor film may be formed using a CVD method, an MBE method, a PLD method, or the like.
  • the oxide semiconductor 230 preferably has crystallinity.
  • oxide semiconductors having crystallinity include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductor, and single-crystalline oxide semiconductor. It is preferable to use CAAC-OS or nc-OS as the oxide semiconductor 230, and it is particularly preferable to use CAAC-OS.
  • the CAAC-OS preferably has multiple layered crystal regions with the c-axis oriented in the normal direction to the surface on which it is formed.
  • the oxide semiconductor 230 preferably has layered crystals that are approximately parallel to the sidewall of the opening 290, particularly to the side surface of the insulator 280. With this configuration, the layered crystals of the oxide semiconductor 230 are formed approximately parallel to the channel length direction of the transistor, thereby increasing the on-current of the transistor.
  • CAAC-OS is a metal oxide that has a highly crystalline and dense structure and has few impurities and defects (e.g., oxygen vacancies).
  • the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.
  • the oxide semiconductor 230 by using a crystalline oxide such as CAAC-OS as the oxide semiconductor 230, it is possible to suppress the extraction of oxygen from the oxide semiconductor 230 by the source electrode or the drain electrode. As a result, even when heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 230, and the transistor is stable against high temperatures (so-called thermal budget) in the manufacturing process.
  • a crystalline oxide such as CAAC-OS
  • the crystallinity of the oxide semiconductor 230 can be analyzed, for example, by X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • the oxide semiconductor 230 When the oxide semiconductor 230 is CAAC-OS, it is preferable that the oxide semiconductor 230 has a layered crystal part.
  • the crystal part is preferably oriented so that the c-axis is parallel to the normal direction of the surface on which it is formed.
  • FIGS. 2A and 2B show enlarged views of regions P and Q in FIG. 1B, respectively.
  • FIGS. 2A and 2B each show a schematic diagram of a crystal part 231 having a layered structure.
  • the c-axis of the crystal part 231 is perpendicular to the line segment showing the layered structure.
  • carriers tend to move more easily in the in-plane direction than in the stacking direction of the layers, and a current often flows easily. Therefore, by using an oxide semiconductor 230 having such an oriented crystal part 231, the direction of current flow in the oxide semiconductor 230 and the in-plane direction of the crystal are always parallel to each other, and a large current can flow.
  • the oxide semiconductor 230 in contact with the upper surfaces of the conductor 240b and the conductor 220b can be made into a CAAC-OS relatively easily. Therefore, it is preferable to use indium tin oxide with silicon added for the conductor 240b and the conductor 220b.
  • the oxide semiconductor 230 can be polycrystallized by using polycrystallized indium tin oxide for the conductor 240b.
  • the oxide semiconductor 230 may have a laminated structure of multiple oxide layers with different chemical compositions. For example, it may have a structure in which multiple types of metal oxides selected from those described in the [Metal Oxide] section below are appropriately laminated.
  • the oxide semiconductor 230 may have a layered structure of an oxide semiconductor 230a and an oxide semiconductor 230b on the oxide semiconductor 230a.
  • the electrical conductivity of the material used for oxide semiconductor 230a is preferably different from the electrical conductivity of the material used for oxide semiconductor 230b.
  • the oxide semiconductor 230a can be made of a material having a higher conductivity than the oxide semiconductor 230b.
  • a material having a high conductivity for the oxide semiconductor 230a in contact with the conductor 220 and the conductor 240, which function as a source electrode or a drain electrode the contact resistance between the oxide semiconductor 230 and the conductor 220 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, and a transistor with a large on-current can be obtained.
  • the threshold voltage of the transistor may shift, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may become large.
  • the threshold voltage may become low. Therefore, it is preferable to use a material with lower conductivity than the oxide semiconductor 230a for the oxide semiconductor 230b.
  • the threshold voltage can be increased, and the transistor can have a small cutoff current. Note that a small cutoff current may be referred to as a normally-off transistor.
  • the oxide semiconductor 230 As described above, by forming the oxide semiconductor 230 into a stacked structure and using a material for the oxide semiconductor 230a that has a higher electrical conductivity than the oxide semiconductor 230b, a transistor that is normally off and has a large on-current can be obtained. Therefore, a semiconductor device that achieves both low power consumption and high performance can be obtained.
  • the carrier concentration of the oxide semiconductor 230a is preferably higher than that of the oxide semiconductor 230b. Increasing the carrier concentration of the oxide semiconductor 230a increases the conductivity, and the contact resistance between the oxide semiconductor 230 and the conductor 220 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, resulting in a transistor with a large on-current. Reducing the carrier concentration of the oxide semiconductor 230b decreases the conductivity, resulting in a normally-off transistor.
  • the oxide semiconductor 230a is made of a material having a higher conductivity than the oxide semiconductor 230b, but the present invention is not limited to this.
  • the oxide semiconductor 230a may be made of a material having a lower conductivity than the oxide semiconductor 230b.
  • a configuration can be used in which the carrier concentration of the oxide semiconductor 230a is lower than the carrier concentration of the oxide semiconductor 230b.
  • the band gap of the first metal oxide used in the oxide semiconductor 230a is preferably different from the band gap of the second metal oxide used in the oxide semiconductor 230b.
  • the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
  • the band gap of the first metal oxide used in the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used in the oxide semiconductor 230b. This can reduce the contact resistance between the oxide semiconductor 230 and the conductor 220 and the contact resistance between the oxide semiconductor 230 and the conductor 240, and can provide a transistor with a large on-state current.
  • the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and the transistor can be a normally-off transistor.
  • the band gap of the first metal oxide is smaller than the band gap of the second metal oxide, but the present invention is not limited to this.
  • the band gap of the first metal oxide can be larger than the band gap of the second metal oxide.
  • the band gap of the first metal oxide used in the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used in the oxide semiconductor 230b.
  • the composition of the first metal oxide is preferably different from that of the second metal oxide.
  • the band gap can be controlled.
  • the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide.
  • the first metal oxide and the second metal oxide are In-M-Zn oxides
  • the first metal oxide may not contain the element M.
  • the first metal oxide used in the oxide semiconductor 230a may be an In-Zn oxide
  • the second metal oxide used in the oxide semiconductor 230b may be an In-M-Zn oxide.
  • the first metal oxide may be an In-Zn oxide
  • the second metal oxide may be an In-Ga-Zn oxide.
  • the first metal oxide may also have a composition containing a trace amount of the element M.
  • the content of element M in the first metal oxide is lower than the content of element M in the second metal oxide, but one embodiment of the present invention is not limited to this.
  • the content of element M in the first metal oxide may be higher than the content of element M in the second metal oxide. Note that it is sufficient that the first metal oxide and the second metal oxide have different compositions, and the contents of elements other than element M may be different.
  • the thickness of the oxide semiconductor 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
  • each layer (here, oxide semiconductor 230a and oxide semiconductor 230b) constituting oxide semiconductor 230 may be determined so that the thickness of oxide semiconductor 230 falls within the aforementioned range.
  • the thickness of oxide semiconductor 230a can be determined so that the contact resistance between oxide semiconductor 230a and conductor 220 and the contact resistance between oxide semiconductor 230a and conductor 240 fall within the required range.
  • the thickness of oxide semiconductor 230b can be determined so that the threshold voltage of the transistor falls within the required range. Note that the thickness of oxide semiconductor 230a may be the same as or different from the thickness of oxide semiconductor 230b.
  • the oxide semiconductor 230a and the oxide semiconductor 230b may have a different ratio of film thickness at the portion where the top surface of the conductor 240 is to be formed to the portion where the side surface of the conductor 240 and the side surface of the insulator 280 are to be formed.
  • the oxide semiconductor 230 is shown to have a two-layer structure of the oxide semiconductor 230a and the oxide semiconductor 230b, but the present invention is not limited to this.
  • the oxide semiconductor 230 may have a three or more layer structure.
  • the oxide semiconductor 230 may have a layered structure of an oxide semiconductor 230a, an oxide semiconductor 230b on the oxide semiconductor 230a, and an oxide semiconductor 230c on the oxide semiconductor 230b.
  • an oxide semiconductor 230c may be provided between the conductor 260 and the oxide semiconductor 230b.
  • the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide semiconductor 230b.
  • the oxide semiconductor 230a may not be provided.
  • the oxide semiconductor 230 may have a stacked structure of the oxide semiconductor 230b and the oxide semiconductor 230c on the oxide semiconductor 230b.
  • the oxide semiconductor 230a may not be provided.
  • the oxide semiconductor film that becomes the oxide semiconductor 230b is formed using an ALD method or a CVD method
  • the oxide semiconductor 230a may not be provided.
  • damage to the insulator 280 is reduced, and the diffusion of elements contained in the insulator 280 into the oxide semiconductor film can be suppressed.
  • the threshold voltage of the transistor 200 may shift and the cutoff current may become large. Specifically, when the transistor 200 is an n-channel transistor, the threshold voltage may become low. Therefore, it is preferable to use a material with lower conductivity than the oxide semiconductor 230b for the oxide semiconductor 230c. As a result, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased and the transistor can have a small cutoff current.
  • the oxide semiconductor 230b As described above, by using a material having a higher conductivity than the oxide semiconductor 230c as the oxide semiconductor 230b, a normally-off transistor with a large on-state current can be obtained. Therefore, a semiconductor device that achieves both low power consumption and high performance can be obtained.
  • the carrier concentration of the oxide semiconductor 230b is preferably higher than that of the oxide semiconductor 230c. Increasing the carrier concentration of the oxide semiconductor 230b increases the conductivity, and a transistor with a large on-state current can be obtained. In addition, decreasing the carrier concentration of the oxide semiconductor 230c decreases the conductivity, and a normally-off transistor can be obtained.
  • the oxide semiconductor 230b is made of a material having a higher conductivity than the oxide semiconductor 230c; however, one embodiment of the present invention is not limited to this.
  • the oxide semiconductor 230b may be made of a material having a lower conductivity than the oxide semiconductor 230c.
  • the carrier concentration of the oxide semiconductor 230b may be lower than the carrier concentration of the oxide semiconductor 230c.
  • the band gap of the second metal oxide used in the oxide semiconductor 230b is preferably different from the band gap of the third metal oxide used in the oxide semiconductor 230c.
  • the difference between the band gap of the second metal oxide and the band gap of the third metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
  • the band gap of the second metal oxide used in the oxide semiconductor 230b can be smaller than the band gap of the third metal oxide used in the oxide semiconductor 230c. This allows a transistor with a large on-state current to be obtained. Furthermore, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and the transistor can be a normally-off transistor.
  • the band gap of the second metal oxide is smaller than the band gap of the third metal oxide, but one embodiment of the present invention is not limited to this.
  • the band gap of the second metal oxide may be larger than the band gap of the third metal oxide.
  • the first metal oxide used in the oxide semiconductor 230a and the third metal oxide used in the oxide semiconductor 230c may have the same composition or different compositions.
  • indium oxide may be used as oxide semiconductor 230b
  • This configuration increases the on-state current of the transistor 200 and provides a highly reliable
  • a metal oxide having conductivity for the conductor 240b and the conductor 220b it is preferable to use a metal oxide having conductivity for the conductor 240b and the conductor 220b. This allows ohmic contact between the conductor 240b and the oxide semiconductor 230a, and between the conductor 220b and the oxide semiconductor 230a.
  • indium tin oxide with added silicon for the conductor 240b and the conductor 220b
  • a metal oxide having a relatively high conductivity of In:Ga:Zn 1:1:1 [atomic ratio] or a composition close to that for the oxide semiconductor 230a. This allows the on-current, field effect mobility, and frequency characteristics of the transistor 200 to be improved.
  • the insulator 250a is preferably an insulator having a function of capturing or fixing hydrogen.
  • hydrogen contained in the oxide semiconductor 230 can be captured or fixed more effectively.
  • the hydrogen concentration in the oxide semiconductor 230 can be reduced.
  • An insulator applicable to the insulator 222 can be used as the insulator 250a.
  • hafnium silicate or the like can be used as the insulator 250a.
  • the insulator 250a contains at least hafnium, silicon, and oxygen.
  • the insulator 250a preferably has an amorphous structure. Note that the insulators described in the [Insulator] section below may be used as the insulator 250a in a single layer or a stacked layer.
  • the insulator 250a By making the insulator 250a have an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the film of the insulator 250a. This makes the film thickness distribution of the insulator 250a uniform, and it is possible to reduce areas where the film thickness is extremely thin, thereby improving the withstand voltage of the insulator 250a. It is also possible to uniform the film thickness distribution of the film provided on the insulator 250a.
  • hafnium oxide is a high dielectric constant (high-k) material
  • hafnium silicate can also be a high dielectric constant (high-k) material depending on the silicon content. Therefore, when the insulator 250a is used as a gate insulator, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. It is also possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as a gate insulator.
  • EOT equivalent oxide thickness
  • the thickness of the insulator 250a is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm.
  • the insulator 250a only needs to have a region with the above thickness in at least a portion.
  • the insulator 250a has an amorphous structure, the formation of crystal grain boundaries is reduced, and the insulator 250a has high flatness. Therefore, the insulator 250a can be made into a thin film with high voltage resistance and reduced leakage current. Therefore, the insulator 250a is suitable as a gate insulator.
  • the insulator 250b is preferably a barrier insulator against hydrogen. This can suppress the diffusion of impurities contained in the conductor 260 into the oxide semiconductor 230.
  • an insulator applicable to the insulators 210 and 283 can be used.
  • silicon nitride has high barrier properties against hydrogen and is therefore suitable as the insulator 250b.
  • the insulator 250b contains at least nitrogen and silicon. Note that as the insulator 250b, the insulators described in the [Insulator] section below may be used in a single layer or a stacked layer.
  • the thickness of the insulator 250b is preferably 2 nm or more, and more preferably 3 nm or more. There is no particular upper limit to the thickness of the insulator 250b, but from the viewpoint of miniaturization or high integration of semiconductor devices and improvement of productivity of semiconductor devices, it is preferably 20 nm or less, 10 nm or less, or 5 nm or less. Therefore, the insulator 250b preferably has a region with a thickness of 2 nm or more and 10 nm or less, and more preferably has a region with a thickness of 2 nm or more and 5 nm or less. The insulator 250b preferably has a region with a thickness of 3 nm or more and 10 nm or less, and more preferably has a region with a thickness of 3 nm or more and 5 nm or less.
  • the insulator 250b When the insulator 250b has a barrier property against hydrogen, the insulator 250b also has a barrier property against oxygen. Furthermore, the insulator 250b has a region in contact with the conductor 260. Therefore, since the insulator 250b has a barrier property against oxygen, it is possible to prevent the oxygen contained in the oxide semiconductor 230 or the insulator 250a from diffusing into the conductor 260 and oxidizing the conductor 260. It is also possible to prevent the oxygen contained in the oxide semiconductor 230 from diffusing into the conductor 260 and forming oxygen vacancies in the oxide semiconductor 230.
  • the conductor 260 may be a single layer or a multilayer of the conductors described in the section below titled "Conductor.”
  • the conductor 260 may be a highly conductive material such as tungsten.
  • a conductive material that is difficult to oxidize, or a conductive material that has a function of suppressing the diffusion of oxygen as the conductor 260.
  • conductive materials include conductive materials that contain nitrogen (e.g., titanium nitride or tantalum nitride), and conductive materials that contain oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductor 260.
  • the conductor 260 may have a laminated structure.
  • the conductor 260 may have a laminated structure of a conductor 260a and a conductor 260b on the conductor 260a.
  • titanium nitride may be used as the conductor 260a
  • tungsten may be used as the conductor 260b.
  • the conductor 260 is shown as having a two-layer laminate structure of conductor 260a and conductor 260b, but the present invention is not limited to this.
  • the conductor 260 may also have a laminate structure of three or more layers.
  • the insulator 283 is preferably a barrier insulator against hydrogen. This can prevent hydrogen from diffusing from above the insulator 283 to the oxide semiconductor 230. Silicon nitride films and silicon nitride oxide films each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulator 283.
  • impurities e.g., water and hydrogen
  • the insulator 283 contains silicon and nitrogen.
  • the sputtering method does not require the use of molecules containing hydrogen in the deposition gas, and therefore the hydrogen concentration in the insulator 283 can be reduced. Furthermore, by depositing the insulator 283 by sputtering, silicon nitride with high density can be formed.
  • the insulator 283 may have a laminated structure of an insulator 283a and an insulator 283b on the insulator 283a.
  • an insulator having a function of capturing hydrogen or fixing hydrogen as the insulator 283a
  • an insulator that can be used for the insulator 222 may be used appropriately.
  • hafnium silicate may be used as the insulator 283a.
  • the insulator 283b has a laminated structure of the insulator 283a having a function of capturing hydrogen or fixing hydrogen, and the insulator 283b that is a barrier insulator against hydrogen.
  • This configuration can prevent hydrogen from diffusing from above the insulator 283 to the oxide semiconductor 230.
  • the insulator 283a and the insulator 222 which have the function of capturing or fixing hydrogen, are provided inside a closed system consisting of the insulator 283b, which has a barrier property against hydrogen, and the insulator 210, so that the hydrogen concentration in the oxide semiconductor 230 can be reduced.
  • FIGS. 4A to 4E correspond to FIG. 1B.
  • insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like, as appropriate.
  • CVD chemical vapor deposition
  • MBE molecular beam epitaxy
  • PLD pulsed laser deposition
  • ALD ALD method
  • Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner.
  • RF sputtering is mainly used when depositing insulating films
  • DC sputtering is mainly used when depositing metal conductive films.
  • Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using the reactive sputtering method.
  • CVD methods can be classified into plasma CVD (PECVD) methods, which use plasma, thermal CVD (TCVD: Thermal CVD) methods, which use heat, and photo CVD (Photo CVD) methods, which use light. They can also be further divided into metal CVD (MCVD: Metal CVD) methods and metal organic CVD (MOCVD: Metal CVD) methods, depending on the source gas used.
  • PECVD plasma CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal CVD
  • the plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can reduce plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, with the thermal CVD method, which does not use plasma, such plasma damage does not occur, and the yield of semiconductor devices can be increased. Furthermore, with the thermal CVD method, no plasma damage occurs during film formation, so films with fewer defects can be obtained.
  • the ALD method can be a thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy, or a PEALD method in which a plasma-excited reactant is used.
  • the CVD and ALD methods are different from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios.
  • the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a faster film formation speed.
  • a film of any composition can be formed by changing the flow rate ratio of the raw material gases.
  • a film with a continuously changing composition can be formed by changing the flow rate ratio of the raw material gases while forming the film.
  • a film of any composition can be formed by introducing multiple different types of precursors.
  • a film of any composition can be formed by controlling the number of cycles of each precursor.
  • the type of oxidizing agent may be changed depending on each precursor.
  • ozone (O 3 ) may be used as an oxidizing agent for the first precursor
  • oxygen (O 2 ) may be used as an oxidizing agent for the second precursor.
  • a heat treatment may be performed.
  • the heat treatment may be performed under reduced pressure, and the film may be formed continuously without exposure to the atmosphere. By performing such a treatment, it is possible to remove moisture and hydrogen adsorbed on the surface on which the film is to be formed, and further reduce the moisture concentration and hydrogen concentration in the structure on which the film is to be formed.
  • the temperature of the heat treatment is preferably 100°C or higher and 600°C or lower.
  • a substrate (not shown) is prepared, and an insulator 210 is formed on the substrate (see FIG. 4A).
  • the insulator 210 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate.
  • a silicon nitride film can be formed as the insulator 210 by a sputtering method.
  • the insulator 222 is formed on the insulator 210 (see FIG. 4A).
  • the insulator 222 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate.
  • a hafnium silicate film may be formed as the insulator 222 by a sputtering method.
  • a film formation target having hafnium and silicon may be used.
  • a co-sputtering method using a silicon oxide target and a hafnium oxide target may be used.
  • the insulator 222 may also be formed by a thermal ALD method.
  • hafnium tetrachloride and silicon tetrachloride may be used as precursors.
  • silicon may be added to the hafnium oxide film to form a hafnium silicate film.
  • Methods for adding silicon include, for example, ion implantation, in which the source gas is ionized and the ions are mass-separated before being added, or ion doping, in which the source gas is ionized and the ions are added without mass separation.
  • the conductor 220 is formed on the insulator 222 (see FIG. 4A).
  • the conductor 220 can be formed by depositing a conductive film on the insulator 222 and patterning the conductive film by lithography.
  • the conductive film can be formed by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film can be formed by depositing tungsten by sputtering, and then depositing ITSO on the tungsten by sputtering.
  • the insulator 280 is formed on the insulator 222 and the conductor 220 (see FIG. 4A).
  • the insulator 280 may be made of any of the insulating materials described above.
  • the insulator 280 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon nitride film may be formed as the insulator 280 by a sputtering method.
  • CMP chemical mechanical polishing
  • the upper surface of the insulator 280 has an upwardly convex curved shape. By not performing the planarization process, it is possible to reduce manufacturing costs and increase production yields.
  • the hydrogen concentration in the insulator 280 can be reduced.
  • hydrogen diffusing from the insulator 280 to the oxide semiconductor 230 can be reduced, and oxygen vacancies and VOH in the channel formation region can be reduced.
  • a conductive film 240A is formed on the insulator 280, and a conductive film 240B is formed on the conductive film 240A (see FIG. 4A).
  • the conductive film 240A and the conductive film 240B may be formed using the above-mentioned conductive materials as appropriate.
  • the conductive film 240A and the conductive film 240B may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • ruthenium can be formed as the conductive film 240A by a sputtering method.
  • ITSO can be formed as the conductive film 240B by a sputtering method.
  • a part of the conductive film 240A, a part of the conductive film 240B, and a part of the insulator 280 are processed to form an opening 290 that reaches the conductor 220 (see FIG. 4B).
  • the opening 290 may be formed using a lithography method.
  • a coating film 277 is formed on the conductive film 240B (see FIG. 5A).
  • the coating film 277 may be formed, for example, by a spin coating method.
  • a non-photosensitive organic resin may be used as the coating film 277.
  • the coating film 277 preferably contains silicon.
  • an SOG (Spin On Glass) film is formed as the coating film 277.
  • the coating film 277 contains an organic solvent such as alcohol when applied, but the organic matter contained therein may be reduced or removed during subsequent processes or when the semiconductor device is completed.
  • the coating film may be provided as needed, and may be configured to be laminated.
  • a SOG film may be laminated on a SOC (Spin On Carbon) film.
  • a coating film to improve adhesion between the SOC film and the surface to be formed may be provided under the SOC film.
  • a resist mask which will be described later, is sufficient, a configuration may be used in which no coating film is provided.
  • a resist mask 279 is formed on the coating film 277 using lithography (see FIG. 5A).
  • a photosensitive organic resin also called photoresist may be used as the resist mask 279.
  • an organic resin that is photosensitive to an electron beam may be used.
  • a positive photoresist or a negative photoresist may be used.
  • the photoresist that becomes the resist mask 279 can be formed to a uniform thickness by forming the film using, for example, a spin coating method.
  • the resist is first exposed through a mask.
  • the exposed area is removed or left using a developer to form a resist mask.
  • a conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask.
  • a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light.
  • a liquid immersion technique can be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed.
  • an electron beam or an ion beam can be used instead of the light described above.
  • a mask may not be used.
  • a dry etching method is used to perform an etching process to form the opening 290.
  • the dry etching method is suitable for forming the opening 290 with a high aspect ratio because it allows anisotropic etching.
  • oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be appropriately added to the above etching gas.
  • a gas containing no halogen gas and a hydrocarbon gas or a hydrogen gas can be used as the etching gas.
  • the hydrocarbon used in the etching gas may be one or more of methane ( CH4 ), ethane ( C2H6 ), propane ( C3H8 ), butane ( C4H10 ) , ethylene ( C2H4 ), propylene ( C3H6 ) , acetylene ( C2H2 ) , and propyne ( C3H4 ) .
  • the etching conditions may be appropriately set according to the object to be etched.
  • a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used as the dry etching apparatus.
  • a capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Or, it can be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Also, it can be configured to apply multiple different high-frequency voltages to the parallel plate electrodes.
  • Such a CCP etching apparatus is called a dual frequency capacitively coupled plasma (DF-CCP) etching apparatus. In the DF-CCP etching apparatus, it can be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes.
  • DF-CCP dual frequency capacitively coupled plasma
  • a configuration in which multiple different high-frequency voltages are applied to one of the parallel plate electrodes can be used.
  • a dry etching device having a high-density plasma source can be used.
  • ICP inductively coupled plasma
  • the etching device can be appropriately set according to the object to be etched.
  • reactive ion etching can be performed by applying a high-frequency voltage to the electrode on the substrate side in the above-mentioned dry etching device to generate a self-bias potential.
  • reactive ion etching etching is performed by accelerating ion species in the plasma and colliding them with the workpiece, so that highly anisotropic etching can be performed.
  • the following process for forming the opening 290 is performed continuously without exposure to the outside air.
  • a multi-chamber etching device can be used to perform the process without exposure to the outside air.
  • the coating film 277 is processed using a resist mask 279 to form an opening corresponding to the opening 290 in the coating film 277 (see FIG. 5B ).
  • the coating film 277 can be processed in a DF-CCP etching apparatus using CHF3 and oxygen gas as etching gas.
  • the resist mask 279 can be removed, for example, by performing a dry etching process such as ashing, a wet etching process, a dry etching process followed by a wet etching process, or a dry etching process followed by a wet etching process.
  • a dry etching process such as ashing, a wet etching process, a dry etching process followed by a wet etching process, or a dry etching process followed by a wet etching process.
  • the conductive film 240B is processed using the coating film 277 as a mask to form an opening 290B in the conductive film 240B corresponding to the opening 290 (see FIG. 5C ).
  • the conductive film 240B can be processed in a DF-CCP etching apparatus using CH 4 and argon gas as etching gases.
  • the conductive film 240A is processed using the coating film 277 as a mask to form an opening 290A in the conductive film 240A and the conductive film 240B corresponding to the opening 290 (see FIG. 5D).
  • the conductive film 240A can be treated by an ICP etching apparatus using Cl2 and oxygen gas as etching gas.
  • the insulator 280 is processed using the coating film 277 as a mask to form openings 290 in the insulator 280, the conductive film 240A, and the conductive film 240B (see FIG. 4B ).
  • the process can be performed with a DF-CCP etching apparatus using CH 2 F 2 , CHF 3 , CF 4 , oxygen gas, and argon gas as etching gases.
  • the coating film 277 may also be removed at the same time while processing the insulator 280.
  • the conductive film 240A and the conductive film 240B are exposed to the dry etching process. Therefore, it is preferable that at least one of the conductive film 240A and the conductive film 240B, for example, the conductive film 240A, functions as a hard mask during processing of the insulator 280.
  • the conductive film 240A functions as a hard mask during processing of the insulator 280.
  • the side of the insulator 280 which is part of the sidewall of the opening 290, can be formed perpendicular or approximately perpendicular to the upper surface of the insulator 222.
  • the taper angle ⁇ 1 of the insulator 280 can be set to 75 degrees or more and 90 degrees or less. This configuration prevents the opening 290 of the transistor 200 from becoming excessively large, and reduces the area it occupies. This allows for miniaturization or high integration of the semiconductor device.
  • the side surface of the conductive film 240B may have a tapered shape.
  • the taper angle between the side surface of the conductive film 240B and the top surface of the conductive film 240A (which may be the top surface of the insulator 222 or the top surface of the insulator 210) is angle ⁇ 2
  • the angle ⁇ 2 is smaller than the angle ⁇ 1.
  • the transistor 200 having the opening 290 with the shape of FIG. 6A becomes as shown in FIG. 6B.
  • the taper angle ⁇ 2 of the side surface of the conductor 240b is reflected in the oxide semiconductor 230, the insulator 250, and the conductor 260.
  • the method of forming the opening 290 is not limited to the above method.
  • the method shown in Figures 7A to 7D may be used.
  • the method shown in Figures 7A to 7D differs from the method shown in Figures 5A to 5D in that an inorganic film that functions as a hard mask is provided between the conductive film 240B and the coating film 277.
  • Another example of the method of forming the opening 290 will be described below with reference to Figures 7A to 7D.
  • an inorganic film 276 is formed on the conductive film 240B (see FIG. 7A).
  • the inorganic film 276 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.
  • the inorganic film 276 functions as a hard mask for forming an opening 290 in the insulator 280, the conductive film 240A, and the conductive film 240B in a later step.
  • the inorganic film 276 may be made of a metal material or an inorganic insulating material that can obtain an etching selectivity when processing the insulator 280, the conductive film 240A, and the conductive film 240B.
  • the inorganic film 276 may be made of tungsten formed by sputtering.
  • the inorganic film 276 may be formed continuously after the conductive film 240A and the conductive film 240B are formed without exposure to the atmosphere.
  • a coating film 277 is formed on the inorganic film 276, and a resist mask 279 is formed on the coating film 277.
  • the method for forming the coating film 277 and the resist mask 279 is the same as the method shown in FIG. 5A, so the above description can be referred to.
  • an etching process is performed using a dry etching method to form the opening 290.
  • the dry etching method is suitable for forming the opening 290 with a high aspect ratio because it allows anisotropic etching.
  • the coating film 277 is processed using a resist mask 279 to form an opening in the coating film 277 that corresponds to the opening 290 (see FIG. 7B).
  • the coating film 277 may be processed in a manner similar to that shown in FIG. 5B.
  • the inorganic film 276 is processed using the resist mask 279 to form an opening corresponding to the opening 290 in the inorganic film 276 (see FIG. 7B ).
  • the inorganic film 276 can be processed in a DF-CCP etching apparatus using Cl 2 , CF 4 , and oxygen gas as etching gases.
  • the conductive film 240B is processed using the inorganic film 276 as a mask to form an opening in the conductive film 240B corresponding to the opening 290 (see FIG. 7C).
  • the conductive film 240B may be processed in a manner similar to that shown in FIG. 5C.
  • the conductive film 240A is processed using the inorganic film 276 as a mask to form an opening 290A in the conductive film 240A and the conductive film 240B corresponding to the opening 290 (see FIG. 7C).
  • the conductive film 240A may be processed in a manner similar to that shown in FIG. 5D.
  • the insulator 280 is processed using the inorganic film 276 as a mask to form openings 290 in the insulator 280, the conductive film 240A, and the conductive film 240B (see FIG. 7D).
  • the insulator 280 may be processed in the same manner as described above.
  • the inorganic film 276 contains tungsten, it is difficult to be etched during processing of the conductive film 240B containing ITSO, the conductive film 240A containing ruthenium, and the insulator 280 containing silicon nitride, and can function as a hard mask.
  • the side of insulator 280, the side of conductive film 240A, and the side of conductive film 240B, which are part of the sidewall of opening 290, can be formed perpendicular or approximately perpendicular to the upper surface of insulator 222.
  • This configuration prevents opening 290 of transistor 200 from becoming excessively large, and reduces the area it occupies. This allows for miniaturization or high integration of the semiconductor device.
  • the inorganic film 276 is removed by dry etching (see FIG. 4B).
  • the inorganic film 276 can be processed by a DF-CCP etching apparatus using Cl2 , CF4 , and oxygen gas as etching gas.
  • the conductive film 240B has ITSO, it is hardly etched in the dry etching process of the inorganic film 276 containing tungsten. Note that if the material of the inorganic film 276 does not affect the subsequent process or can be used in the subsequent process, it is not necessarily necessary to remove the inorganic film 276.
  • the transistor 200 shown in FIG. 3A or 3B can be formed by forming a recess in the upper surface of the conductor 220 that overlaps with the opening 290.
  • a cleaning process in order to remove impurities that have adhered to the opening 290 during the etching process, it is preferable to perform a cleaning process.
  • a cleaning method wet cleaning (which can also be called a wet etching process) using a cleaning liquid or the like can be performed.
  • the wet cleaning can also be used to etch the upper surface of the conductor 220, forming a recess in the upper surface of the conductor 220 that overlaps with the opening 290.
  • the recess can also be included in the opening 290. Note that the wet cleaning can be performed not only after the opening 290 has been formed, but also during the process of forming the opening 290.
  • Wet cleaning may be performed using an aqueous solution in which one or more of oxalic acid, phosphoric acid, and hydrofluoric acid are diluted with carbonated water or pure water.
  • Wet cleaning may also be performed using an aqueous solution in which ammonia water is diluted with carbonated water or pure water.
  • Wet cleaning may also be performed using pure water or carbonated water.
  • ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water.
  • these cleaning methods may be combined as appropriate.
  • the above cleaning process may also be performed multiple times, and the cleaning liquid may be changed for each cleaning process.
  • wet cleaning may be performed using diluted hydrofluoric acid, which is hydrofluoric acid diluted with pure water.
  • a microwave treatment may be performed in an atmosphere containing oxygen to reduce the impurity concentration in the insulator 280.
  • the microwave treatment refers to, for example, a treatment using an apparatus having a power source that generates high-density plasma using microwaves.
  • the microwave refers to an electromagnetic wave having a frequency of 300 MHz to 300 GHz.
  • impurities include hydrogen and carbon.
  • oxygen gas By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied.
  • oxygen plasma By applying oxygen plasma to the insulator 280 in this manner, hydrogen contained in the insulator 280 can be released to the outside as H 2 O.
  • the oxygen plasma treatment may oxidize the side surface of the insulator 280 at the opening 290.
  • oxygen by forming the insulator 280 in contact with the oxide semiconductor 230, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230 by performing heat treatment or the like.
  • oxygen vacancies and VOH in the channel formation region of the oxide semiconductor 230 can be reduced. This can stabilize the electrical characteristics of the transistor 200 and improve its reliability.
  • oxygen acting on the insulator 280 can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also referred to as O radicals, which are atoms, molecules, or ions having an unpaired electron). Furthermore, the oxygen acting on the insulator 280 is preferably in one or more of the forms described above, and is particularly preferably an oxygen radical.
  • the microwave treatment when performing the microwave treatment in the above-mentioned oxygen-containing atmosphere, it is preferable to heat the substrate, since this can further reduce the impurity concentration in the insulator 280.
  • the temperature at which the above-mentioned substrate is heated may be 100°C or higher and 650°C or lower, preferably 200°C or higher and 600°C or lower, and more preferably 300°C or higher and 450°C or lower.
  • the microwave treatment is preferably performed under reduced pressure, with the pressure being preferably 10 Pa or higher and 1000 Pa or lower, and more preferably 300 Pa or higher and 700 Pa or lower.
  • the microwave treatment can be performed using oxygen gas and argon gas.
  • the oxygen flow ratio (O 2 /(O 2 +Ar)) is greater than 0% and less than or equal to 100%.
  • the oxygen flow ratio (O 2 /(O 2 +Ar)) is greater than 0% and less than or equal to 50%.
  • the oxygen flow ratio (O 2 /(O 2 +Ar)) is greater than 10% and less than or equal to 40%.
  • the oxygen flow ratio (O 2 /(O 2 +Ar)) is greater than 10% and less than or equal to 30%.
  • the frequency of the microwave processing device is preferably 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, and can be, for example, 2.45 GHz.
  • the power of the power source that applies microwaves in the microwave processing device is preferably 1000 W or more and 10,000 W or less, more preferably 2000 W or more and 5000 W or less.
  • the microwave processing device may have a power source that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the insulator 280.
  • a heat treatment may be performed.
  • the heat treatment may be performed continuously after the microwave treatment without exposing the substrate to the outside air.
  • the heat treatment may be performed at 250° C. to 650° C., preferably 300° C. to 500° C., and more preferably 320° C. to 450° C.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.
  • the oxygen gas can be about 20%.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more after the heat treatment in the nitrogen gas or inert gas atmosphere.
  • an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more after the heat treatment in the nitrogen gas or inert gas atmosphere.
  • impurities such as water contained in the insulator 280 and the like can be reduced before the formation of an oxide semiconductor film that becomes the oxide semiconductor 230 described later. It is preferable that the heat treatment be performed under conditions that do not excessively oxidize the conductor 220 and the conductor 240.
  • the gas used in the heat treatment is highly purified.
  • the amount of moisture contained in the gas used in the heat treatment can be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • an oxide semiconductor film that becomes the oxide semiconductor 230 is formed in contact with the upper surface of the conductor 220, the side surface of the insulator 280, the side surface of the conductive film 240A, and the upper surface and side surface of the conductive film 240B.
  • the oxide semiconductor film may be formed using any of the above-mentioned metal oxides that can be used for the oxide semiconductor 230.
  • the oxide semiconductor film may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide semiconductor film is preferably formed in contact with the upper surface of the conductor 220 and the side surface of the insulator 280. Therefore, the oxide semiconductor film is preferably formed by a film formation method that has good coverage, and more preferably by a CVD method, an ALD method, or the like.
  • an In-Ga-Zn oxide film can be formed by an ALD method.
  • the deposition method of the oxide semiconductor film that becomes the oxide semiconductor 230 is not limited to the CVD method or the ALD method.
  • a sputtering method may be used.
  • the deposition method of each layer included in the oxide semiconductor 230 may be the same or different.
  • the oxide semiconductor film that becomes the oxide semiconductor 230 is preferably formed in contact with the top surface of the conductor 220 in the opening 290, the side surface of the insulator 280 in the opening 290, the side surface of the conductive film 240A, and the top surface and side surface of the conductive film 240B.
  • the conductor 220 functions as one of the source electrode and drain electrode of the transistor 200.
  • the conductor 240 functions as the other of the source electrode and drain electrode of the transistor 200.
  • microwave treatment and heat treatment described above may be performed after the oxide semiconductor film is formed.
  • the oxide semiconductor film that will become the oxide semiconductor 230 is processed using lithography to form the oxide semiconductor 230 (see FIG. 4C). As a result, a part of the oxide semiconductor 230 is formed in the opening 290.
  • the oxide semiconductor 230 can be processed using a dry etching method or a wet etching method. Processing using the dry etching method is suitable for fine processing.
  • the conductive film 240A and the conductive film 240B are processed to form the conductor 240a and the conductor 240b (see FIG. 4C).
  • the formation of the conductor 240a and the conductor 240b may be performed using a lithography method.
  • the conductive film 240A and the conductive film 240B can be processed using a dry etching method or a wet etching method. Processing using a dry etching method is suitable for fine processing.
  • the insulator 250 is formed on the oxide semiconductor 230, the conductor 240a, the conductor 240b, and the insulator 280 (see FIG. 4D).
  • the insulator 250 may be formed using any of the insulating materials described above.
  • the insulator 250 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 250 is preferably formed in contact with the oxide semiconductor 230 provided in the opening 290. Therefore, the insulator 250 is preferably formed by a film formation method with good coverage, and more preferably by a CVD method, an ALD method, or the like.
  • silicon oxide can be formed as the insulator 250 by the PEALD method.
  • the method for forming the insulator 250 is not limited to the CVD method or the ALD method.
  • the sputtering method may be used.
  • the insulator 250 can have a laminated structure of the insulator 250a and the insulator 250b.
  • the insulator 250a can be formed as a film of hafnium silicate using the thermal ALD method.
  • the insulator 250b can be formed as a film of silicon nitride using the PEALD method.
  • the side end of the oxide semiconductor 230 is covered with the insulator 250. Therefore, it is possible to prevent a short circuit between the oxide semiconductor 230 and the conductor 260. Furthermore, by using the above configuration, the side end of the conductor 240 is covered with the insulator 250. Therefore, it is possible to prevent a short circuit between the conductor 240 and the conductor 260.
  • the microwave treatment and heat treatment described above may be performed after the formation of the insulator 250.
  • the heat treatment can be performed in a state where the insulators 222 and 250a are provided in a closed system consisting of the insulators 210 and 250b. This allows hydrogen in the closed system to be captured or fixed to the insulators 222 and 250a. This allows the hydrogen concentration in the channel formation region of the oxide semiconductor 230 to be reduced. This improves the electrical characteristics of the transistor, and improves the reliability of the transistor. In addition, a semiconductor device with less variation in the electrical characteristics of the transistor can be provided.
  • the microwave treatment by performing the microwave treatment, impurities such as carbon in the oxide semiconductor 230 can also be removed. By removing carbon, which is an impurity in the oxide semiconductor 230, the crystallinity of the oxide semiconductor 230 can be improved. As a result, the oxide semiconductor 230 can be made into a CAAC-OS. In particular, when the oxide semiconductor 230 is formed by an ALD method, carbon contained in the precursor may be taken into the oxide semiconductor 230, so it is preferable to remove carbon by the microwave treatment.
  • the microwave treatment is not necessarily performed after all of the insulators contained in the insulator 250 have been formed.
  • the microwave treatment may be performed after the insulator 250a is formed, and then the insulator 250b may be formed.
  • the microwave treatment may be performed after the insulator 250a is formed, and then the microwave treatment may be performed after the insulator 250b is formed. In this way, the microwave treatment in an atmosphere containing oxygen may be performed multiple times.
  • a conductive film that will become the conductor 260 is formed so as to fill the recess of the insulator 250.
  • the conductive film may be formed using any of the conductive materials described above.
  • the conductive film may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film is preferably formed in contact with the insulator 250 provided in the opening 290. Therefore, the conductive film is preferably formed using a film formation method that has good coverage or embedding properties, and it is more preferable to use a CVD method or an ALD method.
  • titanium nitride may be formed as the conductive film using a CVD method or an ALD method, and tungsten may be formed on the titanium nitride using a CVD method.
  • the conductive film that becomes the conductor 260 is provided so as to fill the opening 290, but the present invention is not limited to this.
  • a recess that reflects the shape of the opening 290 may be formed in the center of the conductive film.
  • the recess may also be filled with an inorganic insulating material or the like.
  • the conductor 260 may be formed by using a lithography method.
  • the above processing can be performed by a dry etching method or a wet etching method. Processing by the dry etching method is suitable for fine processing.
  • a film of insulator 283 is formed to cover conductor 260 and insulator 250.
  • the insulator 283 may be formed using any of the insulating materials described above.
  • the insulator 283 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As shown in FIG. 3B, the insulator 283 may have a layered structure of insulators 283a and 283b.
  • the microwave treatment and heat treatment described above may be performed after the formation of the insulator 283.
  • the heat treatment can be performed in a state where the insulators 222 and 283a are provided in a closed system consisting of the insulators 210 and 283b. This allows hydrogen in the closed system to be captured or fixed to the insulators 222 and 283a. This allows the hydrogen concentration in the channel formation region of the oxide semiconductor 230 to be reduced. This improves the electrical characteristics of the transistor, and improves the reliability of the transistor. In addition, a semiconductor device with less variation in the electrical characteristics of the transistor can be provided.
  • the transistor 200 shown in Figures 1A to 1D can be manufactured.
  • ⁇ Modifications of the Semiconductor Device> 1 illustrates a configuration in which the insulator 280 and the oxide semiconductor 230 are in contact with each other at the opening 290, the present invention is not limited to this.
  • an insulator having a function of capturing or fixing hydrogen may be provided between the insulator 280 and the oxide semiconductor 230.
  • FIGS. 8A to 8D show another example of a semiconductor device according to an embodiment of the present invention.
  • FIG. 8A is a plan view of the semiconductor device.
  • FIGS. 8B to 8D are cross-sectional views of the semiconductor device.
  • FIG. 8B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 8A.
  • FIG. 8C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 8A.
  • FIG. 8D is a cross-sectional view in the XY plane including the insulator 280. Note that some elements have been omitted from the plan view of FIG. 8A to clarify the drawing.
  • the semiconductor device shown in Figures 8A to 8D differs from the semiconductor device shown in Figures 1A to 1D in that it has an insulator 223.
  • differences from the content explained using Figures 1A to 1D will be mainly explained, and overlapping parts will be referred to and explanations may be omitted.
  • the insulator 223 is provided between the insulator 280 and the oxide semiconductor 230. Furthermore, the portions of the insulator 223, the oxide semiconductor 230, the insulator 250, and the conductor 260 that are arranged in the opening 290 are provided to reflect the shape of the opening 290.
  • the insulator 223 is provided to cover the sidewall of the opening 290
  • the oxide semiconductor 230 is provided to cover the side surface of the insulator 223 and the bottom of the opening 290
  • the insulator 250 is provided to cover the oxide semiconductor 230
  • the conductor 260 is provided to fill the recess of the insulator 250 that reflects the shape of the opening 290.
  • the semiconductor device shown in Figures 8A to 8D has a configuration in which an insulator 223, an oxide semiconductor 230, an insulator 250, and a conductor 260 are provided in this order inside an opening in an insulator 280.
  • the insulator 223 is preferably an insulator having a function of capturing or fixing hydrogen.
  • An insulator applicable to the insulator 222 can be used as the insulator 223.
  • hafnium silicate can be used. This allows a configuration in which the oxide semiconductor 230 is sandwiched between insulators (here, the insulator 250a and the insulator 223) having a function of capturing or fixing hydrogen, and a barrier insulator against hydrogen (here, the insulator 280) is provided on the outside. With this configuration, the diffusion of hydrogen into the oxide semiconductor 230 can be suppressed, and the hydrogen concentration in the oxide semiconductor 230 can be further reduced.
  • the film thickness of the insulator 223 (e.g., the width of the insulator 223 in the A1-A2 direction) is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm. It is sufficient that at least a portion of the insulator 223 has a region with the above width.
  • FIGS. 8A to 8D show a configuration in which the insulator 223 is provided between the insulator 280 and the oxide semiconductor 230.
  • this is not limited thereto, and the insulator 223 can be provided in contact with the oxide semiconductor 230 or in the vicinity of the oxide semiconductor 230.
  • FIGS. 8A to 8D show a configuration in which the insulator 223 is provided between the insulator 280 and the oxide semiconductor 230, but the present invention is not limited to this.
  • an insulator having a function of capturing or fixing hydrogen and a barrier insulator against hydrogen may be provided between the insulator 280 and the oxide semiconductor 230.
  • FIGS. 9A to 9D show another example of a semiconductor device according to an embodiment of the present invention.
  • FIG. 9A is a plan view of the semiconductor device.
  • FIGS. 9B to 9D are cross-sectional views of the semiconductor device.
  • FIG. 9B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 9A.
  • FIG. 9C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 9A.
  • FIG. 9D is a cross-sectional view in the XY plane including the insulator 280. Note that some elements have been omitted from the plan view of FIG. 9A to clarify the drawing.
  • the semiconductor device shown in Figures 9A to 9D differs from the semiconductor device shown in Figures 8A to 8D in that it has an insulator 221. Also, the semiconductor device shown in Figures 9A to 9D differs from the semiconductor device shown in Figures 1A to 1D in that it has an insulator 221 and an insulator 223.
  • differences from the contents explained using Figures 1A to 1D or Figures 8A to 8D will be mainly explained, and overlapping parts will be referred to and explanations may be omitted.
  • the insulator 221 is provided between the insulator 280 and the insulator 223. Furthermore, the portions of the insulator 221, the insulator 223, the oxide semiconductor 230, the insulator 250, and the conductor 260 that are arranged in the opening 290 are provided to reflect the shape of the opening 290.
  • the insulator 221 is provided to cover the side walls of the opening 290
  • the insulator 223 is provided to cover the side surfaces of the insulator 221
  • the oxide semiconductor 230 is provided to cover the side surfaces of the insulator 223 and the bottom of the opening 290
  • the insulator 250 is provided to cover the oxide semiconductor 230
  • the conductor 260 is provided to fill the recesses of the insulator 250 that reflect the shape of the opening 290.
  • the insulator 221 is preferably a barrier insulator against hydrogen.
  • An insulator applicable to the insulator 210 can be used as the insulator 221.
  • silicon nitride can be used. This allows a configuration in which the oxide semiconductor 230 is sandwiched between insulators (here, the insulator 250a and the insulator 223) that have a function of capturing or fixing hydrogen, and a barrier insulator against hydrogen (here, the insulator 221) is provided on the outside. With this configuration, the diffusion of hydrogen into the oxide semiconductor 230 can be suppressed, and the hydrogen concentration in the oxide semiconductor 230 can be further reduced.
  • the film thickness of the insulator 221 is preferably 2 nm or more, and more preferably 3 nm or more. Note that there is no particular upper limit to the film thickness of the insulator 221, but from the viewpoint of miniaturization or high integration of semiconductor devices and improvement of productivity of semiconductor devices, it is preferably 20 nm or less, 10 nm or less, or 5 nm or less.
  • the insulator 221 preferably has a region with a film thickness of 2 nm or more and 10 nm or less, and more preferably has a region with a film thickness of 2 nm or more and 5 nm or less. Furthermore, the insulator 221 preferably has a region with a film thickness of 3 nm or more and 10 nm or less, and more preferably has a region with a film thickness of 3 nm or more and 5 nm or less.
  • the material used for the insulator 280 is not limited to a material having a barrier property against hydrogen.
  • the insulator 280 may be formed using a material with a low relative dielectric constant. By forming the insulator 280 using a material with a low relative dielectric constant, the insulator 280 can function as an interlayer film. Therefore, the parasitic capacitance generated between the wirings can be reduced.
  • the insulator 280 is shown as a single layer in Figures 9B to 9D, the present invention is not limited to this.
  • the insulator 280 may have a laminated structure.
  • the insulator 280 may have a layered structure of an insulator 280a, an insulator 280b on the insulator 280a, and an insulator 280c on the insulator 280b.
  • the insulator 280b may be formed using, for example, a material having a low dielectric constant. By forming the insulator 280b using a material having a low dielectric constant, the parasitic capacitance generated between the wirings can be reduced.
  • the insulator 280b a single layer or a stack of insulators containing a material having a low dielectric constant, as described in the [Insulator] section below, can be used.
  • the insulator 280b can be made of silicon oxide or silicon oxynitride.
  • the concentration of impurities such as water and hydrogen in the insulator 280b is reduced. This can suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor 230.
  • insulator 280b When an insulator containing oxygen is used as insulator 280b, it is preferable to use a barrier insulator against oxygen, as described in the [Insulator] section below, for insulators 280a and 280c.
  • insulator 280a between insulator 280b and conductor 220, it is possible to prevent conductor 220 from being oxidized and the resistance of conductor 220 from increasing.
  • insulator 280c between insulator 280b and conductor 240, it is possible to prevent conductor 240 from being oxidized and the resistance of conductor 240 from increasing.
  • the insulator 280a and the insulator 280c may each be a barrier insulator against hydrogen. This allows the insulator 280b to be surrounded by barrier insulators against hydrogen (here, the insulators 280a, 280c, and 221). This prevents hydrogen from diffusing from the outside into the insulator 280b and the hydrogen from diffusing into the oxide semiconductor 230.
  • the silicon nitride film and the silicon nitride oxide film each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used for the insulator 280a and the insulator 280c. Note that the insulator 280a and the insulator 280c may be made of the same material or different materials.
  • an insulator having a function of capturing or fixing hydrogen may be used as the insulator 280a.
  • the insulator 280a magnesium oxide, aluminum oxide, hafnium oxide, or an oxide containing hafnium and silicon may be used.
  • a stacked film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 280a.
  • an insulator having a function of capturing or fixing hydrogen may be used as the insulator 280c.
  • silicon nitride can be used for insulators 280a and 280c
  • silicon oxide can be used for insulator 280b.
  • insulators 280a and 280c each contain at least silicon and nitrogen.
  • Insulator 280b contains at least silicon and oxygen.
  • FIG. 10A shows a configuration in which the insulator 280c is provided on the planarized insulator 280b, but the present invention is not limited to this.
  • the insulator 280c may be formed without performing a planarization process on the insulator 280b. By not performing a planarization process, the manufacturing cost can be reduced and the production yield can be increased.
  • the insulators 280a, 280b, and 280c can be formed successively without being exposed to the atmospheric environment.
  • the insulators 280a to 280c By forming the insulators 280a to 280c without exposing them to the atmospheric environment, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulators 280a to 280c, and it is possible to keep the vicinity of the interface between the insulators 280a and 280b, and the vicinity of the interface between the insulators 280b and 280c clean.
  • insulator 250a having a function of capturing or fixing hydrogen can be provided in contact with oxide semiconductor 230. Therefore, when insulators 280a, 280c, and 250b have barrier properties against hydrogen and the hydrogen concentration in insulator 280b is sufficiently reduced, insulators 221 and 223 may not be provided as shown in FIG. 10B.
  • oxygen can be supplied to the oxide semiconductor 230.
  • oxygen is supplied from the insulator 280b to the oxide semiconductor 230, particularly to the channel formation region of the oxide semiconductor 230, oxygen vacancies and VOH in the oxide semiconductor 230 can be reduced, and the transistor can have favorable electrical characteristics and high reliability.
  • the channel length of the transistor 200 when the channel length of the transistor 200 is short, the influence of oxygen vacancies in the channel formation region and VOH on the electrical characteristics and reliability is particularly large. Therefore, by sufficiently reducing the hydrogen concentration in the oxide semiconductor 230 and then optimizing the amount of oxygen supplied to the oxide semiconductor 230, a transistor with a short channel length having favorable electrical characteristics and high reliability can be realized.
  • the insulator 280b is preferably formed by a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • oxygen supplied to the oxide semiconductor 230 for example, after forming the insulator 280b, a heat treatment in an oxygen-containing atmosphere or a plasma treatment in an oxygen-containing atmosphere may be performed.
  • oxygen may be supplied by forming an oxide film in an oxygen atmosphere on the upper surface of the insulator 280b by a sputtering method. The oxide film may then be removed. By performing such a treatment, oxygen can be supplied to the insulator 280b, and the amount of oxygen supplied to the oxide semiconductor 230 can be increased.
  • the amount of oxygen supplied to the oxide semiconductor 230 is to be reduced, it is preferable to provide one or both of the insulators 221 and 223. With this configuration, even if the amount of oxygen released by the insulator 280b is large, it is possible to prevent an excessive amount of oxygen from being supplied to the oxide semiconductor 230.
  • the film thickness of the insulator 280c may be appropriately set according to the characteristics required for the transistor 200.
  • FIG. 11A to 11D show another example of a semiconductor device according to an embodiment of the present invention.
  • FIGS. 12A and 12B show enlarged views corresponding to FIG. 11B.
  • FIG. 11A is a plan view of the semiconductor device.
  • FIGS. 11B to 11D are cross-sectional views of the semiconductor device.
  • FIG. 11B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 11A.
  • FIG. 11C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 11A.
  • FIG. 11D is a cross-sectional view in the XY plane including the insulator 280. Note that some elements are omitted from the plan view of FIG. 11A for clarity.
  • FIG. 11A to 11D differs from the semiconductor device shown in Figures 9A to 9D in that it does not have an insulator 223.
  • Figures 9A to 9D differs from the semiconductor device shown in Figures 9A to 9D in that it does not have an insulator 223.
  • Figures 12A and 12B have the same configuration as Figure 3A, except that insulator 221 is provided and insulator 280 has a layered structure of insulators 280a to 280c. Therefore, explanations of the configuration related to Figure 3A may be omitted.
  • the insulator 221 is provided in the opening 290 between the insulator 280 and the conductor 240 (conductor 240a, conductor 240b) and the oxide semiconductor 230.
  • the side surface and upper end of the insulator 221 on the center side of the opening 290 contact the oxide semiconductor 230, the side surface of the insulator 221 on the outer side of the opening 290 contact the side surface of the insulator 280, the side surface of the conductor 240a, and the side surface of the conductor 240b, and the lower end of the insulator 221 preferably contacts the upper surface of the conductor 220.
  • the insulator 221 is formed in a sidewall shape in contact with the side wall of the opening 290.
  • the portions of the insulator 221, the oxide semiconductor 230, the insulator 250, and the conductor 260 arranged in the opening 290 are provided to reflect the shape of the opening 290. Therefore, an insulator 221 is provided to cover the sidewall of the opening 290, an oxide semiconductor 230 is provided to cover the side surface of the insulator 221 and the bottom of the opening 290, an insulator 250 is provided to cover the oxide semiconductor 230, and a conductor 260 is provided to fill the recess of the insulator 250 that reflects the shape of the opening 290.
  • the insulator 221 is preferably a barrier insulator against oxygen.
  • An insulator applicable to the insulator 210 can be used as the insulator 221.
  • silicon nitride may be used.
  • the insulator 221 contains silicon and nitrogen.
  • the upper part of the side of the insulator 221 may have a tapered shape. Furthermore, the upper part of the insulator 221 may have a curved surface. Here, the oxide semiconductor 230 may come into contact with the tapered part of the upper part of the insulator 221. In this case, if the upper part of the insulator 221 has a curved surface, the oxide semiconductor 230 can be formed with good coverage. Note that a tapered shape may also be formed on the upper part of the conductor 240b, continuing from the tapered part of the insulator 221.
  • a recess that overlaps with the opening 290 is formed on the upper surface of the conductor 220, a part of the insulator 221 may be formed in the recess.
  • the present invention is not limited to this.
  • the upper end of the insulator 221 can be configured to be lower than the upper surface of the conductor 240b.
  • the side surface of the conductor 240a on the opening 290 side is covered by the insulator 221.
  • the side surface of the conductor 240a which is made of a metal that is relatively easily oxidized, can be protected by the insulator 221.
  • a part of the side surface of the conductor 240b which is made of a metal oxide, may be exposed to an oxidizing atmosphere.
  • the conductor 240b is a metal oxide, the deterioration due to oxidation of the conductor 240b is smaller than that of the conductor 240a.
  • FIG. 12A shows a configuration in which the lower end of the insulator 221 and the lower surface of the oxide semiconductor 230 are at the same or approximately the same height, but the present invention is not limited to this.
  • the lower end of the insulator 221 may be higher than the lower surface of the oxide semiconductor 230. In this case, it can be said that the recess in the upper surface of the conductor 220 is formed in a stepped shape.
  • the film thickness of the insulator 221 (e.g., the width of the insulator 221 in the A1-A2 direction) is preferably 0.5 nm or more, and more preferably 2 nm or more.
  • the film thickness of the insulator 221 is preferably 20 nm or less, 10 nm or less, or 8 nm or less. Therefore, the insulator 221 preferably has a region with a film thickness of 0.5 nm or more and 20 nm or less, and more preferably has a region with a film thickness of 2 nm or more and 8 nm or less.
  • the insulator 221 preferably has barrier insulation properties against hydrogen.
  • silicon nitride may be used as the insulator 221. This allows the oxide semiconductor 230 to be sandwiched between the barrier insulators against hydrogen. With this configuration, the diffusion of hydrogen into the oxide semiconductor 230 can be suppressed, and the hydrogen concentration in the oxide semiconductor 230 can be further reduced.
  • Figs. 13A to 13D are shown as structures similar to Figs. 11A to 11D.
  • Figs. 13A to 13D correspond to Figs. 11A to 11D, respectively.
  • the side end of the oxide semiconductor 230 and the side end of the conductor 240 are aligned.
  • the oxide semiconductor 230, the conductor 240a, and the conductor 240b are processed using the same mask, so that the side end of the oxide semiconductor 230, the side end of the conductor 240a, and the side end of the conductor 240b can be aligned.
  • the conductor 220 is also configured to extend in the X direction, similar to the conductor 240. In this case, the conductor 220 can function as a wiring extending in the X direction.
  • FIGS. 4A to 4E may be performed between the process shown in FIG. 4B and the process shown in FIG. 4C. Therefore, the above description can be referred to for details of the process shown in FIGS. 4A to 4E.
  • an insulating film 221A is formed in contact with the upper surface of the conductor 220, the side surface of the insulator 280, the side surface of the conductive film 240A, and the upper surface and side surface of the conductive film 240B (see FIG. 14A). It is preferable that the insulating film 221A is formed so as to cover at least the side surface of the conductor 240, particularly the side surface of the conductive film 240A, in the opening 290.
  • the insulating film 221A is an insulating film that will become the insulator 221 in a later step, and the above-mentioned insulators can be used.
  • the insulating film 221A can be formed, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulating film 221A is formed along the sidewalls and bottom surface of the opening 290, it is preferable that the insulating film 221A has good coverage. Therefore, it is preferable that the insulating film 221A is formed using an ALD method or the like that has good coverage. For example, it is preferable to form a silicon nitride film as the insulating film 221A using the PEALD method.
  • insulating film 221A is removed by anisotropic etching to form a sidewall-shaped insulator 221 in contact with the side wall of the opening (see FIG. 14B).
  • insulator 221 is formed in contact with the side surface of insulator 280, the side surface of conductor 240a, and the side surface of conductor 240b.
  • insulator 221 is preferably formed to cover at least the side surface of conductor 240a.
  • the anisotropic etching it is preferable to perform reactive ion etching using a dry etching method.
  • a dry etching method The above description can be referred to for the conditions of the dry etching method and the dry etching device.
  • the etching process can be performed using a DF-CCP etching device with CH 2 F 2 , O 2 and Ar as etching gases.
  • the generated ions may collide with the corners of the edge of the opening in the insulator 221. This may cause the corners to be polished into a tapered shape, as shown in FIG. 12A, etc.
  • the corners may be easily removed by including an easily ionized gas such as argon in the etching gas, or by applying a bias voltage to the electrode on the substrate side.
  • the upper end of the insulator 221 may be etched, and the upper end of the insulator 221 may become lower than the upper surface of the conductive film 240B, as shown in FIG. 12B.
  • this etching process may remove a portion of the upper surface of the conductor 220.
  • the insulator 221 functions as a mask, so that the portion of the conductor 220 that overlaps with the insulator 221 becomes thicker than the portion of the conductor 220 that does not overlap with the insulator 221.
  • a stepped recess is formed on the upper surface of the conductor 220. In this way, as shown in FIG. 12B, a transistor 200 is formed in which the lower end of the insulator 221 is higher than the lower surface of the oxide semiconductor 230.
  • wet cleaning can be used as a cleaning method.
  • the above-mentioned method can also be used for wet cleaning.
  • wet cleaning can be performed with diluted hydrofluoric acid, which is obtained by diluting hydrofluoric acid with pure water.
  • the wet cleaning may remove part of the upper surface of the conductor 220.
  • the heat treatment in an oxygen-containing atmosphere and the microwave treatment in an oxygen-containing atmosphere after the formation of the opening 290 described in ⁇ Method of manufacturing a semiconductor device> are preferably performed after the formation of the insulator 221.
  • the heat treatment and microwave treatment may oxidize part of the insulator 221.
  • the insulator 221 may contain oxygen.
  • SIMS SIMS or the like
  • a region with a high oxygen concentration is observed in the insulator 221.
  • part of the insulator 221 may become silicon oxynitride or silicon nitride oxide after the transistor 200 is formed.
  • oxygen can be supplied to the oxide semiconductor 230 in some cases.
  • oxygen can be released from the insulator 280b and supplied to the oxide semiconductor 230 through part of the insulator 221.
  • oxygen vacancies and VOH in the oxide semiconductor 230 can be reduced, and a transistor with favorable electrical characteristics and high reliability can be obtained.
  • FIGS. 15A to 15D show another example of a semiconductor device according to one embodiment of the present invention.
  • FIGS. 15A to 15D are plan and cross-sectional views of a semiconductor device having a transistor 200E.
  • FIG. 15A is a plan view of the semiconductor device.
  • FIGS. 15B to 15D are cross-sectional views of the semiconductor device.
  • FIG. 15B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 15A.
  • FIG. 15C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 15A.
  • FIG. 15D is a cross-sectional view in the XY plane including the insulator 280. Note that some elements are omitted from the plan view of FIG. 15A for clarity.
  • the semiconductor device shown in Figures 15A to 15D has an insulator 210 on a substrate (not shown), an insulator 222 on the insulator 210, a transistor 200E on the insulator 222, an insulator 280 on the insulator 210, and an insulator 283 on the transistor 200E.
  • Transistor 200E has conductor 242 and conductor 243 on insulator 280, oxide semiconductor 230, insulator 250 on oxide semiconductor 230, and conductor 260 on insulator 250.
  • the semiconductor device shown in Figures 15A to 15D differs from the semiconductor device shown in Figures 8A to 8D in the shape of the oxide semiconductor 230.
  • the semiconductor device shown in Figures 15A to 15D also differs from the semiconductor device shown in Figures 8A to 8D in that it does not have conductor 220 and has conductors 242 and 243 instead of conductor 240.
  • differences from the content explained using Figures 8A to 8D will be mainly explained, and overlapping parts will be referred to and explanations may be omitted.
  • the oxide semiconductor 230, the insulator 250, and the conductor 260 are provided inside the opening 290 of the insulator 280.
  • the side surface of the insulator 280 has a region in contact with the oxide semiconductor 230 and a region in contact with the insulator 250.
  • the insulator 250 has a layered structure of the insulator 250a and the insulator 250b as in FIG. 3A etc.
  • a part of the side surface of the insulator 280 contacts the insulator 250a that has the function of capturing or fixing hydrogen.
  • the oxide semiconductor 230 has a region that contacts the bottom of the opening 290.
  • the bottom surface of the oxide semiconductor 230 in the opening 290 contacts the insulator 222.
  • the conductor 242 and the conductor 243 are separated by an opening 290.
  • the conductor 242 has a conductor 242a and a conductor 242b on the conductor 242a.
  • the conductor 243 has a conductor 243a and a conductor 243b on the conductor 243a.
  • the conductor 242a and the conductor 243a can have the same configuration as the conductor 240a described above.
  • the conductor 242b and the conductor 243b can have the same configuration as the conductor 240b described above.
  • oxide semiconductor 230 functions as a semiconductor layer
  • conductor 260 functions as a gate electrode
  • insulator 250 functions as a gate insulator
  • conductor 242 functions as one of the source electrode and drain electrode
  • conductor 243 functions as the other of the source electrode and drain electrode.
  • the semiconductor device shown in Figures 15A to 15D has a configuration in which an oxide semiconductor 230, an insulator 250, and a conductor 260 are provided in this order inside an opening in an insulator 280.
  • the oxide semiconductor 230 is provided so that at least a portion of it is located inside the opening 290.
  • the transistor 200E has a configuration in which a current flows from one of the source electrode and the drain electrode (e.g., the conductor 242) to the other of the source electrode and the drain electrode (e.g., the conductor 243). That is, the channel length of the transistor 200E (length L indicated by a double arrow in FIG. 15B) is the sum of twice the length of the sidewall of the opening 290 and the length of the bottom of the opening 290. The length of the sidewall of the opening 290 corresponds to the depth of the opening 290. The length of the bottom of the opening 290 is also the shortest distance from the conductor 242 to the conductor 243, for example.
  • the channel length (length L) of the transistor 200E can be adjusted by the depth of the opening 290 and the length of the bottom of the opening 290.
  • the channel length is to be increased while miniaturizing or increasing the integration density of a semiconductor device, it is preferable to increase the depth of the opening 290.
  • the channel width of transistor 200E (length W indicated by a double-headed arrow in FIG. 15C) corresponds to the width of oxide semiconductor 230 in the Y direction in a plan view. Therefore, it is preferable that the channel width of transistor 200E is smaller than the width of the bottom of opening 290.
  • the opening of the insulator 280 has a rectangular shape with rounded corners in plan view.
  • the maximum width of the opening may be calculated appropriately according to the shape of the top of the opening.
  • the maximum width of the opening may be the length of the diagonal or the distance between the opposing sides when the top of the opening is regarded as a rectangle.
  • the present invention is not limited to this.
  • the opening 290 may have a substantially circular shape such as a circle or an ellipse, a polygonal shape, or a polygonal shape with rounded corners in plan view.
  • the transistor 200E shown in FIG. 15A to FIG. 15D can be manufactured on the same layer (insulator 222 in this case) as the transistor 200 shown in FIG. 8A to FIG. 8D. That is, the transistor 200E can be manufactured in parallel with the manufacturing process of the transistor 200. Therefore, two transistors with different channel lengths and channel widths can be provided on the same layer. In this way, the semiconductor device of one embodiment of the present invention has an excellent effect that transistors with different channel lengths can be freely designed on the same layer by changing the thickness of the insulating layer and pattern formation.
  • FIG. 16A is a plan view of the semiconductor device.
  • FIG. 16B is a cross-sectional view of the semiconductor device, and is a cross-sectional view of a portion indicated by the dashed line A5-A6 in FIG. 16A.
  • the substrate on which the transistor is formed for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used.
  • a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), a resin substrate, etc. are available.
  • a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide, etc. are available.
  • a semiconductor substrate having an insulating region inside the aforementioned semiconductor substrate for example, an SOI (Silicon On Insulator) substrate, etc. are available.
  • the conductive substrate there is a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. are available.
  • a substrate having a metal nitride, a substrate having a metal oxide, etc. are available.
  • a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductive substrate, etc. are available.
  • a substrate provided with elements may be used.
  • the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.
  • Insulator examples include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.
  • Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.
  • Materials with a low relative dielectric constant include, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.
  • inorganic insulating materials with a low relative dielectric constant include, for example, silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen.
  • a material that can have ferroelectricity may be used as the insulator.
  • materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (where X is a real number greater than 0).
  • materials that can have ferroelectricity include materials in which an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide.
  • the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set appropriately, and for example, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set to 1:1 or close to 1:1.
  • materials that can have ferroelectricity include materials in which an element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide.
  • the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to or near 1: 1.
  • piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiO x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may be used.
  • the electrical characteristics of a transistor using a metal oxide can be stabilized by surrounding it with an insulator that has a function of suppressing the permeation of impurities and oxygen.
  • an insulator that has a function of suppressing the permeation of impurities and oxygen for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer.
  • metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide
  • metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • Insulators in contact with a semiconductor such as a gate insulator, or insulators provided near a semiconductor layer are preferably insulators having a region containing oxygen that is desorbed by heating (hereinafter, may be referred to as excess oxygen).
  • excess oxygen insulators having a region containing oxygen that is desorbed by heating
  • Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide with vacancies.
  • examples of the barrier insulator against oxygen include oxides containing either or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • examples of oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
  • the barrier insulator against oxygen and the barrier insulator against hydrogen can be said to be a barrier insulator against either or both of oxygen and hydrogen.
  • the conductor it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements.
  • a nitride of the alloy or an oxide of the alloy may be used.
  • tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum
  • conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel
  • materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing the diffusion of oxygen, or materials that maintain conductivity even when oxygen is absorbed.
  • examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide to which silicon has been added, indium zinc oxide, and indium zinc oxide containing tungsten oxide.
  • a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.
  • conductive materials primarily composed of tungsten, copper, or aluminum are preferred due to their high conductivity.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing nitrogen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen and a conductive material containing nitrogen.
  • a metal oxide is used for the channel formation region of a transistor, it is preferable to use a layered structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductor that functions as the gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.
  • a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor that functions as a gate electrode may also be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride, may also be used.
  • Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may also be used.
  • Indium gallium zinc oxide containing nitrogen may also be used.
  • Metal oxides may have lattice defects.
  • Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids.
  • Factors that cause the generation of lattice defects include a deviation in the ratio of the number of atoms of the constituent elements (an excess or deficiency of constituent atoms) and impurities.
  • the metal oxide used in the semiconductor layer of a transistor When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects.
  • the types of lattice defects likely to exist in metal oxides and the amount of lattice defects present vary depending on the structure of the metal oxide or the method of forming the metal oxide film.
  • Non-single crystal structures include, for example, CAAC structures, polycrystalline structures, nc structures, pseudo-amorphous (a-like: amorphous-like) structures, and amorphous structures.
  • A-like structures have a structure between the nc structure and the amorphous structure.
  • metal oxides having an a-like structure and metal oxides having an amorphous structure have voids or low-density regions. That is, metal oxides having an a-like structure and metal oxides having an amorphous structure have lower crystallinity than metal oxides having an nc structure and metal oxides having a CAAC structure. Also, metal oxides having an a-like structure have a higher hydrogen concentration in the metal oxide than metal oxides having an nc structure and metal oxides having a CAAC structure. Therefore, lattice defects are easily generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.
  • a metal oxide with high crystallinity for the semiconductor layer of a transistor.
  • a metal oxide having a CAAC structure or a metal oxide having a single crystal structure By using such a metal oxide for a transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.
  • a metal oxide for the channel formation region of a transistor, which increases the on-current of the transistor.
  • the crystal it is preferable to use a metal oxide with high crystallinity for the metal oxide including the channel formation region. Furthermore, it is preferable for the crystal to have a crystal structure in which multiple layers (e.g., a first layer, a second layer, and a third layer) are stacked. In other words, the crystal has a layered crystal structure (also called a layered crystal or layered structure). In this case, the c-axis of the crystal is oriented in the direction in which the multiple layers are stacked. Examples of metal oxides having the crystal include single crystal oxide semiconductors and CAAC-OS.
  • the c-axis of the crystal in the normal direction to the surface on which the metal oxide is formed or the film surface. This allows the multiple layers to be arranged parallel or approximately parallel to the surface on which the metal oxide is formed or the film surface. In other words, the multiple layers extend in the channel length direction.
  • the three-layered crystal structure described above will have the following structure.
  • the first layer has an atomic coordination structure in the form of an octahedron of oxygen with the metal of the first layer at the center.
  • the second layer has an atomic coordination structure in the form of a trigonal bipyramid or tetrahedron of oxygen with the metal of the second layer at the center.
  • the third layer has an atomic coordination structure in the form of a trigonal bipyramid or tetrahedron of oxygen with the metal of the third layer at the center.
  • Examples of the crystal structure of the above crystal include a YbFe 2 O 4 type structure, a Yb 2 Fe 3 O 7 type structure, and modified structures thereof.
  • each of the first to third layers is preferably composed of one metal element or multiple metal elements having the same valence, and oxygen.
  • the valence of the one or multiple metal elements constituting the first layer is preferably the same as the valence of the one or multiple metal elements constituting the second layer.
  • the first layer and the second layer may have the same metal element.
  • the valence of the one or multiple metal elements constituting the first layer is different from the valence of the one or multiple metal elements constituting the third layer.
  • the above structure improves the crystallinity of the metal oxide and increases the carrier mobility of the metal oxide. Therefore, by using the metal oxide in the channel formation region of a transistor, the on-state current of the transistor increases, and the electrical characteristics of the transistor can be improved.
  • Examples of the metal oxide of the present invention include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide of the present invention preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably contains two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or semi-metal element having a high bond energy with oxygen, for example, a metal element or semi-metal element having a bond energy with oxygen higher than that of indium.
  • the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • the metal oxide of one embodiment of the present invention preferably has one or more selected from indium, gallium, and zinc.
  • metal elements and metalloid elements may be collectively referred to as “metal elements", and the "metal element” described in this specification and the like may include metalloid elements.
  • Metal oxides according to one embodiment of the present invention include, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), and indium gallium oxide (In-Ga-Ga-Al ...
  • In-Zn oxide indium zinc oxide
  • In-Sn oxide indium titanium oxide
  • In-Ti oxide indium gallium oxide
  • In-Ga oxide indium gallium aluminum oxide
  • In-Ga-Al oxide indium gallium tin oxide
  • IGTO indium gallium tin oxide
  • GZO gallium zinc oxide
  • Indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), etc.
  • IAZO Indium aluminum zinc oxide
  • indium tin oxide containing silicon gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc.
  • indium tin oxide containing silicon gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc.
  • the field effect mobility of the transistor can be increased.
  • the metal oxide may have one or more metal elements having a higher period number in the periodic table instead of indium.
  • the metal oxide may have one or more metal elements having a higher period number in the periodic table in addition to indium.
  • the greater the overlap of the orbits of the metal elements the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a higher period number in the periodic table, the field effect mobility of the transistor may be increased.
  • Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium.
  • Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the field effect mobility of the transistor may be increased.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. This suppresses fluctuations in the electrical characteristics of the transistor, and increases its reliability.
  • the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, and a transistor with a small off-current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the transistor can obtain a large on-current and high frequency characteristics.
  • In-Ga-Zn oxide may be used as an example of a metal oxide.
  • the metal oxide film formation method of the present invention it is preferable to deposit atoms one layer at a time.
  • the ALD method is used, so that it is easy to form a metal oxide having the above-mentioned layered crystal structure.
  • a transistor with high field-effect mobility can be realized.
  • a highly reliable transistor can be realized.
  • a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of 2 nm or more and 30 nm or less can be manufactured.
  • an oxide semiconductor having a low carrier concentration is preferably used for the channel formation region of the transistor.
  • the carrier concentration of the channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably 1 ⁇ 10 17 cm ⁇ 3 or less, more preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ 10 13 cm ⁇ 3 or less, more preferably 1 ⁇ 10 11 cm ⁇ 3 or less, and further preferably less than 1 ⁇ 10 10 cm ⁇ 3 and 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more. Note that when the carrier concentration of the oxide semiconductor film is reduced, the impurity concentration in the oxide semiconductor film can be reduced to reduce the density of defect states.
  • a semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic.
  • an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film has a low density of defect states, and therefore may also have a low density of trap states.
  • the charge trapped in the trap states of the oxide semiconductor takes a long time to dissipate and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.
  • impurities in an oxide semiconductor refer to, for example, anything other than the main component that constitutes the oxide semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be considered an impurity.
  • the band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2 eV or more, more preferably 2.5 eV or more, and even more preferably 3.0 eV or more.
  • the off-current (also referred to as Ioff) of the transistor can be reduced.
  • OS transistors use oxide semiconductors, which are semiconductor materials with a wide band gap, and therefore the short channel effect can be suppressed. In other words, OS transistors are transistors that do not have the short channel effect or have an extremely small short channel effect.
  • the short channel effect is a degradation of electrical characteristics that becomes evident as transistors are miniaturized (channel length is reduced).
  • Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes written as S value), and an increase in leakage current.
  • the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.
  • Characteristic length is widely used as an index of resistance to short channel effects.
  • Characteristic length is an index of how easily the potential of the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to short channel effects.
  • OS transistors are accumulation-type transistors, while Si transistors are inversion-type transistors. Therefore, compared to Si transistors, OS transistors have smaller characteristic lengths between the source region and the channel-forming region, and between the drain region and the channel-forming region. Therefore, OS transistors are more resistant to the short-channel effect than Si transistors. In other words, when it is desired to manufacture a transistor with a short channel length, OS transistors are more suitable than Si transistors.
  • the OS transistor can also be regarded as having an n + /n ⁇ /n + accumulation-type junction-less transistor structure or an n + /n ⁇ / n + accumulation-type non-junction transistor structure in which the channel formation region is an n ⁇ type region and the source and drain regions are n + type regions.
  • the OS transistor can have good electrical characteristics even when miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the channel length or gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and 1 nm or more, 3 nm or more, or 5 nm or more.
  • the OS transistor can be preferably used as a transistor having a shorter channel length than that of a Si transistor.
  • the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region when the transistor is operating.
  • the cutoff frequency of the transistor can be improved.
  • the cutoff frequency of the transistor can be set to, for example, 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more in a room temperature environment.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the excellent advantages of having a smaller off-state current and being able to fabricate transistors with a short channel length.
  • the carbon concentration in a channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and further preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and still more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in a channel formation region of an oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, and further preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy.
  • an electron serving as a carrier may be generated.
  • some of the hydrogen may bond to oxygen bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable that hydrogen in a channel formation region of the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably less than 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , more preferably less than 1 ⁇ 10 18 atoms/cm 3 , and further preferably less than 1 ⁇ 10 17 atoms/cm 3 .
  • the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the oxide semiconductor 230 can be rephrased as a semiconductor layer including a channel formation region of a transistor.
  • a semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides.
  • a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the semiconductor layer.
  • a semiconductor of a single element, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, or the like) is preferably used for the semiconductor material.
  • layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Silicon and germanium are examples of elemental semiconductors that can be used in the semiconductor material.
  • Examples of silicon that can be used in the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • An example of polycrystalline silicon is low temperature polysilicon (LTPS).
  • Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide.
  • the boron nitride that can be used for the semiconductor layer preferably contains an amorphous structure.
  • the boron arsenide that can be used for the semiconductor layer preferably contains crystals with a cubic crystal structure.
  • Layered materials include graphene, silicene, boron carbonitride, and chalcogenides.
  • boron carbonitride carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane.
  • Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements that belong to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
  • Other examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenide that functions as a semiconductor.
  • transition metal chalcogenides that can be used as the semiconductor layer include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), and zirconium selenide (representatively ZrSe 2 ).
  • the semiconductor device 900 can function as a memory device.
  • FIG. 17 shows a block diagram illustrating an example of the configuration of a semiconductor device 900.
  • the semiconductor device 900 shown in FIG. 17 has a driver circuit 910 and a memory array 920.
  • the memory array 920 has one or more memory cells 950.
  • FIG. 17 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.
  • the transistors exemplified in the above embodiment can be applied to the memory cell 950.
  • the memory device can be miniaturized and highly integrated.
  • the capacity per area of the memory device can be increased.
  • the drive circuit 910 has a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915.
  • the peripheral circuit 915 has a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.
  • each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or other signals may be added.
  • Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signals PON1 and PON2 are signals for power gating control. Signals PON1 and PON2 may be generated by control circuit 912.
  • the control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.
  • the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900.
  • the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.
  • the voltage generation circuit 928 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.
  • the peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950.
  • the peripheral circuit 911 has a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.
  • the row decoder 941 and column decoder 942 have the function of decoding the signal ADDR.
  • the row decoder 941 is a circuit for specifying the row to be accessed
  • the column decoder 942 is a circuit for specifying the column to be accessed.
  • the row driver 923 has the function of selecting the row specified by the row decoder 941.
  • the column driver 924 has the function of writing data to the memory cell 950, the function of reading data from the memory cell 950, the function of retaining the read data, etc.
  • the input circuit 925 has a function of holding a signal WDA.
  • the data held by the input circuit 925 is output to the column driver 924.
  • the output data of the input circuit 925 is data (Din) to be written to the memory cell 950.
  • the data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926.
  • the output circuit 926 has a function of holding Dout.
  • the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900.
  • the data output from the output circuit 926 is the signal RDA.
  • the PSW 931 has a function of controlling the supply of V DD to the peripheral circuit 915.
  • the PSW 932 has a function of controlling the supply of V HM to the row driver 923.
  • the high power supply voltage of the semiconductor device 900 is V DD
  • the low power supply voltage is GND (ground potential).
  • V HM is a high power supply voltage used to set the word line to a high level, and is higher than V DD .
  • the signal PON1 controls the on/off of the PSW 931
  • the signal PON2 controls the on/off of the PSW 932.
  • the number of power supply domains to which V DD is supplied in the peripheral circuit 915 is one, but it may be more than one. In this case, a power switch may be provided for each power supply domain.
  • [DOSRAM] 18A shows an example of a circuit configuration of a memory cell of a DRAM.
  • a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM).
  • the memory cell 951 includes a transistor M1 and a capacitor CA.
  • Transistor M1 may have a front gate (sometimes simply called a gate) and a back gate.
  • the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected.
  • the first terminal of transistor M1 is connected to the first terminal of capacitance element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL.
  • the second terminal of capacitance element CA is connected to wiring CAL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.
  • Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and connecting the wiring BIL to the first terminal of the capacitance element CA.
  • the memory cell that can be used for memory cell 950 is not limited to memory cell 951, and the circuit configuration can be changed.
  • it can be configured as memory cell 952 as shown in FIG. 18B.
  • Memory cell 952 is an example in which no capacitance element CA or wiring CAL is included.
  • the first terminal of transistor M1 is in an electrically floating state.
  • the potential written through transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, as shown by the dashed line. This configuration can greatly simplify the configuration of the memory cell.
  • the OS transistor described in the above embodiment As the transistor M1.
  • the area occupied by the memory cell can be reduced.
  • the OS transistor has a characteristic of having an extremely small off-state current.
  • the leakage current of the transistor M1 can be made extremely low. In other words, since written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary.
  • the leakage current is extremely low, multi-value data or analog data can be held in the memory cell 951 and the memory cell 952.
  • [NOSRAM] 18C shows an example of a circuit configuration of a gain cell type memory cell having two transistors and one capacitor.
  • the memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB.
  • a storage device having a gain cell type memory cell using an OS transistor as the transistor M2 is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).
  • the first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL.
  • the second terminal of capacitance element CB is connected to wiring CAL.
  • the first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB.
  • a low-level potential sometimes called a reference potential
  • Data is written by applying a high-level potential to the wiring WOL, turning on transistor M2, and connecting wiring WBL to the first terminal of capacitance element CB.
  • transistor M2 when transistor M2 is on, a potential corresponding to the information to be recorded is applied to wiring WBL, and this potential is written to the first terminal of capacitance element CB and the gate of transistor M3.
  • a low-level potential is applied to wiring WOL, turning off transistor M2, thereby maintaining the potential of the first terminal of capacitance element CB and the potential of the gate of transistor M3.
  • Data is read by applying a predetermined potential to the wiring SL.
  • the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate of transistor M3 and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held in the first terminal of capacitance element CB (or the gate of transistor M3) can be read. In other words, the information written in this memory cell can be read from the potential held in the first terminal of capacitance element CB (or the gate of transistor M3).
  • the wiring WBL and the wiring RBL may be combined into a single wiring BIL.
  • FIG. 18D An example of the circuit configuration of such a memory cell is shown in FIG. 18D.
  • Memory cell 954 is configured such that the wiring WBL and the wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. In other words, memory cell 954 is configured to operate the write bit line and the read bit line as a single wiring BIL.
  • Memory cell 955 shown in FIG. 18E is an example in which the capacitance element CB and wiring CAL in memory cell 953 are omitted.
  • memory cell 956 shown in FIG. 18F is an example in which the capacitance element CB and wiring CAL in memory cell 954 are omitted.
  • the OS transistor described in the above embodiment for at least transistor M2.
  • the area occupied by the memory cell can be reduced.
  • the OS transistor Since the OS transistor has the characteristic of having an extremely small off-state current, written data can be held for a long time by the transistor M2, and therefore the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. In addition, since the leakage current is extremely low, multi-value data or analog data can be held in the memory cell 953, memory cell 954, memory cell 955, and memory cell 956.
  • Memory cell 953, memory cell 954, memory cell 955, and memory cell 956, in which an OS transistor is used as transistor M2, are one form of NOSRAM.
  • Si transistors may be used as transistor M3.
  • Si transistors can increase the field effect mobility and can also be used as p-channel transistors, allowing for greater freedom in circuit design.
  • the memory cell can be configured as a unipolar circuit.
  • FIG. 18G shows a 3-transistor, 1-capacitor gain cell type memory cell 957.
  • Memory cell 957 has transistors M4 to M6 and a capacitative element CC.
  • the first terminal of transistor M4 is connected to the first terminal of the capacitance element CC, the second terminal of transistor M4 is connected to the wiring BIL, and the gate of transistor M4 is connected to the wiring WOL.
  • the second terminal of the capacitance element CC is electrically connected to the first terminal of transistor M5 and the wiring GNDL.
  • the second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of the capacitance element CC.
  • the second terminal of transistor M6 is connected to the wiring BIL, and the gate of transistor M6 is connected to the wiring RWL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a write word line
  • the wiring RWL functions as a read word line.
  • the wiring GNDL is a wiring that provides a low-level potential.
  • Data is written by applying a high-level potential to the wiring WOL, turning on transistor M4, and connecting the wiring BIL to the first terminal of the capacitance element CC.
  • transistor M4 when transistor M4 is in a conductive state, a potential corresponding to the information to be recorded is applied to the wiring BIL, and this potential is written to the first terminal of the capacitance element CC and the gate of transistor M5.
  • a low-level potential is applied to the wiring WOL, turning off transistor M4, thereby maintaining the potential of the first terminal of the capacitance element CC and the potential of the gate of transistor M5.
  • Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Since the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5, and the potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5).
  • the potential held in the first terminal of the capacitance element CC or the gate of the transistor M5 can be read. In other words, the information written in this memory cell can be read from the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5).
  • the OS transistor described in the above embodiment as at least transistor M4.
  • the area occupied by the memory cell can be reduced.
  • Si transistors may be used as transistors M5 and M6. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystal state of the silicon used in the semiconductor layer.
  • the memory cell can be configured as a unipolar circuit.
  • OS-SRAM 18H shows an example of a static random access memory (SRAM) using an OS transistor.
  • SRAM static random access memory
  • OS-SRAM oxide semiconductor SRAM
  • a memory cell 958 shown in FIG. 18H is a memory cell of an SRAM capable of backing up data.
  • Memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitive elements CD1 and CD2. Note that transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.
  • the first terminal of transistor M7 is connected to the wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10.
  • the gate of transistor M7 is connected to the wiring WOL.
  • the first terminal of transistor M8 is connected to the wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9.
  • the gate of transistor M8 is connected to the wiring WOL.
  • the second terminal of the transistor MS1 is electrically connected to the wiring VDL.
  • the second terminal of the transistor MS2 is electrically connected to the wiring VDL.
  • the second terminal of the transistor MS3 is electrically connected to the wiring GNDL.
  • the second terminal of the transistor MS4 is electrically connected to the wiring GNDL.
  • the second terminal of transistor M9 is connected to the first terminal of capacitance element CD1, and the gate of transistor M9 is connected to wiring BRL.
  • the second terminal of transistor M10 is connected to the first terminal of capacitance element CD2, and the gate of transistor M10 is connected to wiring BRL.
  • the second terminal of the capacitance element CD1 is connected to the wiring GNDL, and the second terminal of the capacitance element CD2 is connected to the wiring GNDL.
  • the wiring BIL and the wiring BILB function as bit lines
  • the wiring WOL functions as a word line
  • the wiring BRL is a wiring that controls the conductive state and non-conductive state of the transistors M9 and M10.
  • the wiring VDL is a wiring that provides a high-level potential
  • the wiring GNDL is a wiring that provides a low-level potential.
  • Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is in a conductive state, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal side of the transistor M10.
  • the memory cell 958 forms an inverter loop with the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Since the transistor M8 is conductive, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Furthermore, since the transistors M9 and M10 are conductive, the potential of the second terminal of the transistor M7 and the potential of the second terminal of the transistor M8 are held in the first terminal of the capacitance element CD2 and the first terminal of the capacitance element CD1, respectively.
  • a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to make the transistors M7 to M10 non-conductive, thereby holding the potential of the first terminal of the capacitance element CD1 and the first terminal of the capacitance element CD2.
  • the wiring BIL and wiring BILB are precharged to a predetermined potential beforehand, and then a high-level potential is applied to the wiring WOL and a high-level potential is applied to the wiring BRL.
  • the potential of the first terminal of the capacitance element CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB.
  • the potential of the first terminal of the capacitance element CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL.
  • the wiring BIL and wiring BILB change from their precharged potentials to the potential of the first terminal of the capacitance element CD2 and the potential of the first terminal of the capacitance element CD1, respectively, so that the potential held in the memory cell can be read from the potential of the wiring BIL or wiring BILB.
  • OS transistors as the transistors M7 to M10. This allows the written data to be held for a long time by the transistors M7 to M10, so that the frequency of refreshing the memory cells can be reduced. Alternatively, the refresh operation of the memory cells can be made unnecessary. In addition, by using the OS transistors described in the above embodiment as the transistors M7 to M10, the area occupied by the memory cells can be reduced.
  • Si transistors may be used as transistors MS1 to MS4.
  • the driving circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Also, as shown in FIG. 19A, the driving circuit 910 and memory array 920 may be provided overlapping each other. By providing the driving circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Also, as shown in FIG. 19B, the memory array 920 may be provided in multiple layers on the driving circuit 910.
  • FIG. 20 shows a block diagram of the arithmetic unit 960.
  • the arithmetic unit 960 shown in FIG. 20 can be applied to a CPU, for example.
  • the arithmetic unit 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a large number (several tens to several hundreds) of processor cores capable of parallel processing more than a CPU.
  • processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a large number (several tens to several hundreds) of processor cores capable of parallel processing more than a CPU.
  • the arithmetic device 960 shown in FIG. 20 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990.
  • the substrate 990 is a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface.
  • the cache 999 and the cache interface 989 may also be provided on separate chips.
  • the cache 999 is connected to a main memory provided on a separate chip via a cache interface 989.
  • the cache interface 989 has a function of supplying a portion of the data held in the main memory to the cache 999.
  • the cache interface 989 also has a function of outputting a portion of the data held in the cache 999 to the ALU 991 or register 996, etc. via the bus interface 998.
  • a memory array 920 can be provided by stacking it on the arithmetic unit 960.
  • the memory array 920 can be used as a cache.
  • the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999.
  • a drive circuit 910 is provided as part of the cache interface 989.
  • the arithmetic device 960 shown in FIG. 20 is merely one example of a simplified configuration, and the actual arithmetic device 960 has a wide variety of configurations depending on the application.
  • the more cores there are, the more preferable it is, but for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more.
  • the number of bits that the arithmetic device 960 can handle in its internal arithmetic circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.
  • Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993, decoded, and then input to the ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995.
  • the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, while the arithmetic unit 960 is executing a program, the interrupt controller 994 determines and processes interrupt requests from external input/output devices, peripheral circuits, etc. based on their priority and mask state. The register controller 997 generates the address of the register 996, and reads or writes to the register 996 depending on the state of the arithmetic unit 960.
  • the timing controller 995 also generates signals that control the timing of the operations of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997.
  • the timing controller 995 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.
  • the register controller 997 selects the holding operation in the register 996 according to instructions from the ALU 991. That is, it selects whether the memory cells in the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, power supply voltage is supplied to the memory cells in the register 996. If holding data in capacitive elements is selected, data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.
  • Figs. 21A and 21B show perspective views of a semiconductor device 970A.
  • the semiconductor device 970A has a layer 930 in which a memory array is provided on the arithmetic device 960.
  • the layer 930 has memory arrays 920L1, 920L2, and 920L3.
  • the arithmetic device 960 and each memory array have overlapping areas.
  • Fig. 21B shows the arithmetic device 960 and layer 930 separated.
  • connection distance between them can be shortened. This allows the communication speed between them to be increased. In addition, the short connection distance allows for reduced power consumption.
  • a method for stacking the layer 930 having the memory array and the arithmetic device 960 As a method for stacking the layer 930 having the memory array and the arithmetic device 960, a method of stacking the layer 930 having the memory array directly on the arithmetic device 960 (also called monolithic stacking) may be used, or a method of forming the arithmetic device 960 and the layer 930 on different substrates, bonding the two substrates, and electrically connecting them using through-vias or conductive film bonding technology (such as Cu-Cu bonding) may be used.
  • the former method does not require consideration of misalignment during bonding, so not only can the chip size be reduced, but also the manufacturing costs can be reduced.
  • the arithmetic device 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache.
  • the memory array 920L1 can be used as an L1 cache (also called a level 1 cache)
  • the memory array 920L2 can be used as an L2 cache (also called a level 2 cache)
  • the memory array 920L3 can be used as an L3 cache (also called a level 3 cache).
  • the memory array 920L3 has the largest capacity and is accessed the least frequently.
  • the memory array 920L1 has the smallest capacity and is accessed the most frequently.
  • each memory array provided in the layer 930 can be used as a lower-level cache or a main memory.
  • the main memory has a larger capacity than the cache and is accessed less frequently.
  • a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided.
  • the driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1.
  • the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2
  • the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.
  • the drive circuit 910L1 may function as part of the cache interface 989, or the drive circuit 910L1 may be configured to be connected to the cache interface 989.
  • the drive circuit 910L2 and the drive circuit 910L3 may also function as part of the cache interface 989, or may be configured to be connected to it.
  • the control circuit 912 can cause some of the multiple memory cells 950 in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.
  • the semiconductor device 900 can cause some of the multiple memory cells 950 to function as a cache, and the other part to function as a main memory. In other words, the semiconductor device 900 can function as both a cache and a main memory.
  • the semiconductor device 900 according to one aspect of the present invention can function as, for example, a universal memory.
  • a layer 930 having one memory array 920 may be provided over the computing device 960.
  • Figure 22A shows a perspective view of the semiconductor device 970B.
  • one memory array 920 can be divided into multiple areas, each of which can be used for a different function.
  • Figure 22A shows an example in which area L1 is used as an L1 cache, area L2 as an L2 cache, and area L3 as an L3 cache.
  • the capacity of each of areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of area L1. With this configuration, it is possible to improve the efficiency of calculation processing and increase the processing speed.
  • Figure 22B shows a perspective view of semiconductor device 970C.
  • Semiconductor device 970C has a layer 930L1 having memory array 920L1 stacked on top of a layer 930L2 having memory array 920L2, and a layer 930L3 having memory array 920L3 stacked on top of that.
  • the memory array 920L1 which is physically closest to the arithmetic device 960, can be used as a higher-level cache, and the memory array 920L3, which is the furthest, can be used as a lower-level cache or main memory. With this configuration, the capacity of each memory array can be increased, thereby further improving processing power.
  • Figure 23A shows various storage devices used in semiconductor devices by hierarchy. The higher the storage device, the faster the operating speed is required, and the lower the storage device, the larger the storage capacity and the higher the recording density are required.
  • a processor such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, storage, etc. Note that, although an example having up to an L3 cache is shown here, it is also possible to have even lower-level caches.
  • Registers also have the function of storing setting information for the processor.
  • a cache has the function of duplicating and storing a portion of the data held in the main memory. By duplicating frequently used data and storing it in the cache, the speed of accessing the data can be increased.
  • the storage capacity required for a cache is less than that of main memory, but it is required to have a faster operating speed than main memory.
  • data that is rewritten in the cache is duplicated and supplied to the main memory.
  • Main memory has the function of holding programs, data, etc. read from storage.
  • Storage has the function of holding data that requires long-term storage, as well as various programs used by processing units. Therefore, storage requires a larger memory capacity and higher recording density than operating speed. For example, high-capacity, non-volatile storage devices such as 3D NAND can be used.
  • a storage device (OS memory) using an oxide semiconductor according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. Therefore, as shown in FIG. 23A, the storage device according to one embodiment of the present invention can be suitably used in both the hierarchy where the cache is located and the hierarchy where the main memory is located. In addition, the storage device according to one embodiment of the present invention can also be applied to the hierarchy where the storage is located.
  • FIG. 23B shows an example in which SRAM is used as part of the cache and an OS memory according to one aspect of the present invention is used as the other part.
  • the lowest level cache can be called an LLC (Last Level Cache).
  • An LLC is not required to operate faster than higher level caches, but it is desirable for it to have a large storage capacity.
  • the OS memory of one embodiment of the present invention is suitable for use as an LLC because it operates quickly and can retain data for long periods of time. Note that the OS memory of one embodiment of the present invention can also be applied to an FLC (Final Level Cache).
  • a configuration can be used in which SRAM is used for the higher-level cache (L1 cache, L2 cache, etc.), and the OS memory of one aspect of the present invention is used for the LLC. Also, as shown in FIG. 23B, not only the OS memory but also DRAM can be used for the main memory.
  • Embodiment 4 electronic components, electronic devices, large scale computers, space equipment, and data centers (also referred to as data centers (DCs)) in which the semiconductor device described in the above embodiment can be used will be described.
  • the electronic devices, large scale computers, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.
  • FIG. 24A a perspective view of an electronic device 6500 is shown in FIG. 24A.
  • the electronic device 6500 shown in FIG. 24A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like.
  • the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.
  • the electronic device 6600 shown in FIG. 24B is an information terminal that can be used as a notebook personal computer.
  • the electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like.
  • the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention for the above-described control device 6509 and control device 6616 is preferable because power consumption can be reduced.
  • Fig. 24C shows a perspective view of the large scale computer 5600.
  • the large scale computer 5600 shown in Fig. 24C has a rack 5610 housing a plurality of rack-mounted computers 5620.
  • the large scale computer 5600 may also be called a supercomputer.
  • Computer 5620 can be configured, for example, as shown in the perspective view of FIG. 24D.
  • computer 5620 has motherboard 5630, which has multiple slots 5631 and multiple connection terminals.
  • PC card 5621 is inserted into slot 5631.
  • PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to motherboard 5630.
  • PC card 5621 shown in FIG. 24E is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like.
  • PC card 5621 has board 5622.
  • Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629.
  • FIG. 24E illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for those semiconductor devices, the following description of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 can be referred to.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • An example of the standard for the connection terminal 5629 is PCIe.
  • Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), and SCSI (Small Computer System Interface). Examples of standards for outputting video signals from connection terminals 5623, 5624, and 5625 include HDMI (registered trademark), and the like.
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
  • the semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • the semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected to each other by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • An example of the semiconductor device 5628 is a memory device.
  • the mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment, such as equipment for processing and storing data.
  • the semiconductor device of one embodiment of the present invention can include an OS transistor.
  • the OS transistor has small changes in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and can be preferably used in an environment where radiation may be incident.
  • the OS transistor can be preferably used in outer space.
  • an artificial satellite 6800 is shown as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807.
  • a planet 6804 is shown as an example of outer space.
  • outer space refers to an altitude of 100 km or more, for example, but the outer space described in this specification may include the thermosphere, mesosphere, and stratosphere.
  • the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit.
  • BMS battery management system
  • the use of OS transistors in the above-mentioned battery management system or battery control circuit is preferable because it consumes low power and has high reliability even in space.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • the power required for the operation of the satellite 6800 is generated.
  • the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated.
  • the solar panel may be called a solar cell module.
  • Satellite 6800 can generate a signal.
  • the signal is transmitted via antenna 6803, and can be received, for example, by a receiver installed on the ground or by another satellite.
  • the position of the receiver that received the signal can be measured.
  • satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device.
  • a semiconductor device according to one embodiment of the present invention is preferably used for the control device 6807.
  • an OS transistor Compared to a Si transistor, an OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure. In other words, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can also be configured to have a sensor. For example, by configuring it to have a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground. Or, by configuring it to have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is given as an example of space equipment, but the present invention is not limited to this.
  • a semiconductor device according to one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.
  • the semiconductor device can be suitably used in a storage system applied to a data center or the like.
  • the data center is required to perform long-term management of data, such as ensuring the immutability of the data.
  • it is necessary to increase the size of the building, for example, to install storage and servers for storing a huge amount of data, to secure a stable power source for storing the data, or to secure cooling equipment required for storing the data.
  • a semiconductor device By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores the data. This makes it possible to miniaturize the storage system, miniaturize the power source for storing data, and reduce the scale of cooling equipment. This makes it possible to save space in the data center.
  • the semiconductor device of one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. This reduces adverse effects of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. This improves the reliability of the data center.
  • FIG. 26 shows a storage system applicable to a data center.
  • the storage system 6900 shown in FIG. 26 has multiple servers 6901sb as hosts 6901 (illustrated as Host Computer). It also has multiple storage devices 6903md as storage 6903 (illustrated as Storage).
  • the host 6901 and storage 6903 are shown connected via a storage area network 6904 (illustrated as SAN: Storage Area Network) and a storage control circuit 6902 (illustrated as Storage Controller).
  • SAN Storage Area Network
  • the host 6901 corresponds to a computer that accesses data stored in the storage 6903.
  • the hosts 6901 may be connected to each other via a network.
  • Storage 6903 uses flash memory to reduce data access speed, i.e. the time required to store and output data, but this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage.
  • cache memory is normally provided within the storage to reduce the time required to store and output data.
  • the above-mentioned cache memory is used in the storage control circuit 6902 and the storage 6903. Data exchanged between the host 6901 and the storage 6903 is stored in the cache memory in the storage control circuit 6902 and the storage 6903, and then output to the host 6901 or the storage 6903.
  • OS transistors as transistors for storing data in the above-mentioned cache memory and configuring it to hold a potential according to the data, it is possible to reduce the frequency of refreshing and lower power consumption.
  • configuring the memory cell array in a stacked structure it is possible to reduce the size.
  • the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO 2 ). In addition, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming because of its low power consumption.
  • CO 2 greenhouse gases
  • a display device to which the transistor of one embodiment of the present invention is applied can be a display device with extremely high resolution.
  • the display device of one embodiment of the present invention can be used in the display portion of a wristwatch-type or bracelet-type information terminal (wearable device), as well as in the display portion of a head-mounted display (HMD), a VR device such as a head-mounted display, and a glasses-type AR device.
  • Display module 27A shows a perspective view of a display module 580.
  • the display module 580 includes a display device 500A and an FPC 590. Note that the display panel included in the display module 580 is not limited to the display device 500A and may be a display device 500C described later.
  • Display module 580 has substrate 591 and substrate 592.
  • Display module 580 has display section 581.
  • Display section 581 is an area that displays an image.
  • FIG. 27B is a perspective view showing a schematic configuration on the substrate 591 side.
  • a circuit section 582, a pixel circuit section 583 on the circuit section 582, and a pixel section 584 on the pixel circuit section 583 are stacked.
  • a terminal section 585 for connecting to an FPC 590 is provided in a portion of the substrate 591 that does not overlap with the pixel section 584.
  • the terminal section 585 and the circuit section 582 are electrically connected by a wiring section 586 consisting of a plurality of wirings.
  • the pixel section 584 has a number of pixels 584a arranged periodically. An enlarged view of one pixel 584a is shown on the right side of FIG. 27B.
  • the pixel 584a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.
  • the pixel circuit section 583 has a number of pixel circuits 583a arranged periodically. Each pixel circuit 583a is a circuit that controls the light emission of three light-emitting devices in one pixel 584a.
  • One pixel circuit 583a may be configured to have three circuits that control the light emission of one light-emitting device.
  • the pixel circuit 583a may be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitance element for each light-emitting device. At this time, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.
  • the circuit portion 582 has a circuit that drives each pixel circuit 583a of the pixel circuit portion 583.
  • the circuit portion 582 has one or both of a gate line driver circuit and a source line driver circuit.
  • the circuit portion 582 may have at least one of an arithmetic circuit, a memory circuit, a power supply circuit, etc.
  • a transistor provided in the circuit portion 582 may constitute a part of the pixel circuit 583a.
  • the pixel circuit 583a may be constituted by a transistor included in the pixel circuit portion 583 and a transistor included in the circuit portion 582.
  • the FPC 590 functions as wiring for supplying video signals, power supply potential, etc. from the outside to the circuit section 582.
  • An IC may also be mounted on the FPC 590.
  • the display module 580 can be configured such that one or both of the pixel circuit section 583 and the circuit section 582 are provided overlappingly under the pixel section 584, so that the aperture ratio (effective display area ratio) of the display section 581 can be extremely high.
  • the aperture ratio of the display section 581 can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less.
  • the pixels 584a can be arranged at an extremely high density, so that the resolution of the display section 581 can be extremely high.
  • the pixels 584a are arranged in the display section 581 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20000 ppi or less, or 30000 ppi or less.
  • Such a display module 580 has extremely high resolution and can therefore be suitably used in VR devices such as head-mounted displays, or glasses-type AR devices. For example, even in a configuration in which the display section of the display module 580 is viewed through a lens, the display module 580 has an extremely high resolution display section 581, so that even if the display section is enlarged with a lens, the pixels are not visible, and a highly immersive display can be achieved.
  • the display module 580 is not limited to this, and can be suitably used in electronic devices with relatively small display sections.
  • the display module 580 can be suitably used in the display section of a wearable electronic device such as a wristwatch.
  • a display device 500A shown in FIG. 28 includes a substrate 201, a light-emitting element 110R, a light-emitting element 110G, a light-emitting element 110B, a capacitor 140, and a transistor 520.
  • Substrate 201 corresponds to substrate 591 in FIG. 27A.
  • the transistor 520 is a vertical channel transistor in which an oxide semiconductor is applied to the semiconductor layer in which the channel is formed.
  • the transistor 520 has an oxide semiconductor 230, an insulator 250, a conductor 260, and a conductor 240.
  • the various transistors exemplified in embodiment 2 can be used as the transistor 520.
  • the transistor 200E shown in FIGS. 15A to 15D may be used as the transistor 520.
  • FIGS. 16A and 16B a configuration in which a transistor 200 is further provided in the same layer may be used.
  • An insulator 210 is provided on the substrate 201.
  • the insulator 210 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 201 to the transistor 520 and prevents oxygen from being released from the oxide semiconductor 230 toward the insulator 210.
  • a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.
  • an insulator 222 is provided on the insulator 210.
  • the insulator 222 functions as an insulating film that captures or fixes hydrogen contained in the insulator 280, the oxide semiconductor 230, etc.
  • a hafnium silicate film or the like can be used as the insulator 222.
  • An insulator 280 is provided on the insulator 222, and a conductor 240 is provided on the insulator 280.
  • An opening is provided in the insulator 280, and an oxide semiconductor 230, an insulator 250, and a conductor 260 are provided in the opening.
  • An insulating layer 164 is provided to cover the conductor 260.
  • the insulating layer 164 functions as an interlayer insulating layer.
  • a barrier layer may be provided between the insulating layer 164 and the insulating layer 154 to prevent impurities such as water or hydrogen from diffusing from the insulating layer 164 to the transistor 520.
  • An insulating film similar to the insulator 210 can be used as the barrier layer.
  • the plug 174 which is electrically connected to one side of the conductor 240, is provided so as to be embedded in the insulating layer 164.
  • the plug 174 has a conductive layer 174a that covers the side of the opening in the insulating layer 164 and part of the upper surface of the conductor 240, and a conductive layer 174b that contacts the upper surface of the conductive layer 174a.
  • a capacitor 140 is provided on the insulating layer 164.
  • the capacitor 140 has a conductive layer 141, a conductive layer 145, and an insulating layer 143 located between them.
  • the conductive layer 141 functions as one electrode of the capacitor 140
  • the conductive layer 145 functions as the other electrode of the capacitor 140
  • the insulating layer 143 functions as a dielectric of the capacitor 140.
  • the conductive layer 141 is provided on the insulating layer 164 and is embedded in the insulating layer 154.
  • the conductive layer 141 is electrically connected to the conductor 240 of the transistor 520 by a plug 174.
  • the insulating layer 143 is provided to cover the conductive layer 141.
  • the conductive layer 145 is provided in a region that overlaps with the conductive layer 141 via the insulating layer 143.
  • An insulating layer 155a is provided covering the capacitor 140, an insulating layer 155b is provided on the insulating layer 155a, and an insulating layer 155c is provided on the insulating layer 155b.
  • Insulating layers 155a, 155b, and 155c can each preferably be made of an inorganic insulating film.
  • a silicon oxide film for insulating layers 155a and 155c and a silicon nitride film for insulating layer 155b. This allows insulating layer 155b to function as an etching protection film.
  • an example is shown in which part of insulating layer 155c is etched to form a recess, but insulating layer 155c does not necessarily have to have a recess.
  • Light emitting element 110R, light emitting element 110G, and light emitting element 110B are provided on insulating layer 155c.
  • Light-emitting element 110R has pixel electrode 111R, organic layer 112R, common layer 114, and common electrode 113.
  • Light-emitting element 110G has pixel electrode 111G, organic layer 112G, common layer 114, and common electrode 113.
  • Light-emitting element 110B has pixel electrode 111B, organic layer 112B, common layer 114, and common electrode 113.
  • Common layer 114 and common electrode 113 are provided in common to light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B.
  • the organic layer 112R of the light-emitting element 110R has a light-emitting organic compound that emits at least red light.
  • the organic layer 112G of the light-emitting element 110G has a light-emitting organic compound that emits at least green light.
  • the organic layer 112B of the light-emitting element 110B has a light-emitting organic compound that emits at least blue light.
  • the organic layer 112R, the organic layer 112G, and the organic layer 112B can each be called an EL layer, and have at least a layer (light-emitting layer) that contains a light-emitting organic compound.
  • display device 500A a separate light-emitting device is created for each emitted color, so there is little change in chromaticity between light emitted at low and high luminance.
  • organic layers 112R, 112G, and 112B are spaced apart from each other, crosstalk between adjacent subpixels can be suppressed even in a high-definition display panel. This makes it possible to realize a display panel that is both high-definition and has high display quality.
  • an insulating layer 125 In the area between adjacent light-emitting elements, an insulating layer 125, a resin layer 126, and a layer 128 are provided.
  • the pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to the conductor 240 of the transistor 520 by the plug 156 embedded in the insulating layers 155a, 155b, and 155c, the conductive layer 141 embedded in the insulating layer 154, and the plug 174.
  • the height of the top surface of the insulating layer 155c and the height of the top surface of the plug 156 are the same or approximately the same.
  • Various conductive materials can be used for the plug.
  • a protective layer 121 is provided on the light-emitting elements 110R, 110G, and 110B.
  • a substrate 170 is attached to the protective layer 121 by an adhesive layer 171.
  • a display device 500C shown in FIG. 29 has a stacked structure of a transistor 310 having a channel formed in a semiconductor substrate and a vertical channel transistor 520 .
  • the transistor 310 has a channel formation region in the substrate 311.
  • the substrate 311 can be a semiconductor substrate such as a single crystal silicon substrate.
  • the transistor 310 has a part of the substrate 311, a conductor 316, a low resistance region 314, an insulator 315, and an insulator 317.
  • the conductor 316 functions as a gate electrode.
  • the insulator 315 is located between the substrate 311 and the conductor 316, and functions as a gate insulating layer.
  • the low resistance region 314 is a region in which the substrate 311 is doped with impurities, and functions as either a source or a drain.
  • the insulator 317 is provided to cover the side surface of the conductor 316.
  • an element isolation layer 318 is provided between two adjacent transistors 310 so as to be embedded in the substrate 311.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments and examples described in this specification.
  • One embodiment of the present invention is a display device having a light-emitting element (also called a light-emitting device).
  • the display device has two or more pixels that emit different light colors.
  • Each pixel has a light-emitting element.
  • Each light-emitting element has a pair of electrodes and an EL layer between them.
  • the light-emitting element is preferably an organic EL element (organic electroluminescent element).
  • Two or more light-emitting elements that emit different light colors each have an EL layer that contains a different light-emitting material.
  • a full-color display device can be realized by having three types of light-emitting elements that emit red (R), green (G), or blue (B) light.
  • an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from the adjacent light-emitting layer.
  • the EL layer is processed into a fine pattern by photolithography without using a shadow mask such as a fine metal mask (FMM).
  • FMM fine metal mask
  • the EL layer can be made separately, it is possible to realize a display device that is extremely vivid, has high contrast, and has high display quality.
  • the EL layer may be processed into a fine pattern using both a metal mask and photolithography.
  • a part or the whole of the EL layer can be physically separated. This makes it possible to suppress leakage current between light-emitting elements via a layer shared between adjacent light-emitting elements (also called a common layer). This makes it possible to prevent unintended light emission due to crosstalk, and to realize a display device with extremely high contrast. In particular, it makes it possible to realize a display device with high current efficiency at low luminance.
  • One aspect of the present invention can be a display device that combines a white-emitting light-emitting element with a color filter.
  • light-emitting elements of the same configuration can be applied to light-emitting elements provided in pixels (subpixels) that emit light of different colors, and all layers can be common layers. Furthermore, a part or all of each EL layer can be divided by photolithography. This suppresses leakage current through the common layer, and a display device with high contrast can be realized.
  • leakage current through the intermediate layer can be effectively prevented, and a display device that combines high brightness, high definition, and high contrast can be realized.
  • the insulating layer that covers at least the side surface of the island-shaped light-emitting layer.
  • the insulating layer may be configured to cover a part of the top surface of the island-shaped EL layer.
  • a material that has barrier properties against water and oxygen For example, an inorganic insulating film that does not easily diffuse water or oxygen can be used. This makes it possible to suppress deterioration of the EL layer and realize a highly reliable display device.
  • FIG. 30A shows a schematic top view of a display device 100 according to one embodiment of the present invention.
  • the display device 100 includes a plurality of light-emitting elements 110R that exhibit red light, a plurality of light-emitting elements 110G that exhibit green light, and a plurality of light-emitting elements 110B that exhibit blue light, over a substrate 101.
  • the symbols R, G, and B are assigned within the light-emitting regions of the light-emitting elements in order to easily distinguish between the light-emitting elements.
  • Light emitting elements 110R, 110G, and 110B are each arranged in a matrix.
  • Figure 30A shows a so-called stripe arrangement in which light emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light emitting elements is not limited to this, and arrangement methods such as an S-stripe arrangement, a delta arrangement, a Bayer arrangement, or a zigzag arrangement may also be applied, and a pentile arrangement, diamond arrangement, etc. may also be used.
  • the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B for example, it is preferable to use an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode).
  • the light-emitting material possessed by the EL element include a material that emits fluorescence (fluorescent material), a material that emits phosphorescence (phosphorescent material), and a material that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material).
  • TADF thermally activated delayed fluorescence
  • the light-emitting material possessed by the EL element not only organic compounds but also inorganic compounds (such as quantum dot materials) can be used.
  • FIG. 30A also shows a connection electrode 111C that is electrically connected to the common electrode 113.
  • the connection electrode 111C is given a potential (e.g., an anode potential or a cathode potential) to be supplied to the common electrode 113.
  • the connection electrode 111C is provided outside the display area where the light-emitting elements 110R and the like are arranged.
  • connection electrode 111C can be provided along the outer periphery of the display area. For example, it may be provided along one side of the outer periphery of the display area, or it may be provided over two or more sides of the outer periphery of the display area. In other words, if the top surface shape of the display area is rectangular, the top surface shape of the connection electrode 111C can be strip-shaped (rectangular), L-shaped, U-shaped (square bracket shaped), square, or the like.
  • FIGS. 30B and 30C are schematic cross-sectional views corresponding to dashed lines A1-A2 and A3-A4 in FIG. 30A, respectively.
  • FIG. 30B shows schematic cross-sectional views of light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B
  • FIG. 30C shows a schematic cross-sectional view of connection portion 130 where connection electrode 111C and common electrode 113 are connected.
  • Light-emitting element 110R has pixel electrode 111R, organic layer 112R, common layer 114, and common electrode 113.
  • Light-emitting element 110G has pixel electrode 111G, organic layer 112G, common layer 114, and common electrode 113.
  • Light-emitting element 110B has pixel electrode 111B, organic layer 112B, common layer 114, and common electrode 113.
  • Common layer 114 and common electrode 113 are provided in common to light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B.
  • the organic layer 112R of the light-emitting element 110R has a light-emitting organic compound that emits at least red light.
  • the organic layer 112G of the light-emitting element 110G has a light-emitting organic compound that emits at least green light.
  • the organic layer 112B of the light-emitting element 110B has a light-emitting organic compound that emits at least blue light.
  • the organic layer 112R, the organic layer 112G, and the organic layer 112B can each be called an EL layer, and have at least a layer (light-emitting layer) that contains a light-emitting organic compound.
  • light-emitting element 110R when describing matters common to light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B, they may be referred to as light-emitting element 110.
  • components distinguished by alphabets such as organic layer 112R, organic layer 112G, and organic layer 112B, they may be described using symbols without the alphabet.
  • the organic layer 112 and the common layer 114 can each independently have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the organic layer 112 can have a laminated structure of a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer from the pixel electrode 111 side, and the common layer 114 can have an electron injection layer.
  • the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B are provided for each light-emitting element.
  • the common electrode 113 and common layer 114 are provided as a continuous layer common to each light-emitting element.
  • a conductive film having translucency to visible light is used for either one of the pixel electrodes or the common electrode 113, and a conductive film having reflective properties is used for the other.
  • a protective layer 121 is provided on the common electrode 113, covering the light-emitting elements 110.
  • the protective layer 121 has the function of preventing impurities such as water from diffusing from above to each light-emitting element.
  • the end of the pixel electrode 111 preferably has a tapered shape.
  • the organic layer 112 provided along the end of the pixel electrode 111 can also be tapered.
  • the coverage of the organic layer 112 provided over the end of the pixel electrode 111 can be improved.
  • foreign matter for example, also called dust or particles
  • the organic layer 112 is processed into an island shape by photolithography. Therefore, the angle between the top surface and the side surface of the organic layer 112 at its ends is close to 90 degrees.
  • organic films formed using FMM or the like tend to become gradually thinner the closer they are to the ends.
  • the top surface is formed in a slope over a range of 1 ⁇ m to 10 ⁇ m to the ends, resulting in a shape in which it is difficult to distinguish between the top surface and the side surface.
  • an insulating layer 125 Between two adjacent light-emitting elements are an insulating layer 125, a resin layer 126, and a layer 128.
  • the resin layer 126 is located between the two adjacent light-emitting elements and is provided so as to fill the ends of each organic layer 112 and the area between the two organic layers 112.
  • the resin layer 126 has a smooth convex upper surface, and a common layer 114 and a common electrode 113 are provided covering the upper surface of the resin layer 126.
  • the resin layer 126 functions as a planarizing film that fills in the step between two adjacent light-emitting elements. By providing the resin layer 126, it is possible to prevent the common electrode 113 from being cut off by the step at the end of the organic layer 112, and the common electrode on the organic layer 112 from being insulated.
  • the resin layer 126 functions as an LFP.
  • an insulating layer containing an organic material can be suitably used.
  • acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins can be applied.
  • organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can be used.
  • a photosensitive resin can be used as the resin layer 126.
  • a photoresist can be used as the photosensitive resin.
  • a positive type material or a negative type material can be used as the photosensitive resin.
  • the resin layer 126 may contain a material that absorbs visible light.
  • the resin layer 126 itself may be made of a material that absorbs visible light, or the resin layer 126 may contain a pigment that absorbs visible light.
  • the resin layer 126 may be, for example, a resin that can be used as a color filter that transmits red, blue, or green light and absorbs other light, or a resin that contains carbon black as a pigment and functions as a black matrix.
  • the insulating layer 125 is provided in contact with the side surface of the organic layer 112.
  • the insulating layer 125 is also provided to cover the upper end portion of the organic layer 112.
  • a portion of the insulating layer 125 is also provided in contact with the upper surface of the substrate 101.
  • the insulating layer 125 is located between the resin layer 126 and the organic layer 112, and functions as a protective film to prevent the resin layer 126 from coming into contact with the organic layer 112. If the organic layer 112 and the resin layer 126 come into contact with each other, the organic layer 112 may be dissolved by the organic solvent used in forming the resin layer 126. Therefore, by providing the insulating layer 125 between the organic layer 112 and the resin layer 126, it is possible to protect the side surface of the organic layer 112.
  • the insulating layer 125 may be an insulating layer containing an inorganic material.
  • an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film may be used for the insulating layer 125.
  • the insulating layer 125 may have a single layer structure or a laminated structure.
  • the oxide insulating film examples include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film.
  • the nitride insulating film include a silicon nitride film and an aluminum nitride film.
  • the oxynitride insulating film examples include a silicon oxynitride film and an aluminum oxynitride film.
  • nitride oxide insulating film examples include a silicon nitride oxide film and an aluminum nitride oxide film.
  • an inorganic insulating film such as an aluminum oxide film or a metal oxide film such as a hafnium oxide film or a silicon oxide film formed by the ALD method to the insulating layer 125, an insulating layer 125 with few pinholes and excellent function of protecting the EL layer can be formed.
  • oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • nitride oxide refers to a material whose composition contains more nitrogen than oxygen
  • silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen
  • the insulating layer 125 can be formed by sputtering, CVD, PLD, ALD, or the like. It is preferable to form the insulating layer 125 by the ALD method, which has good coating properties.
  • a reflective film e.g., a metal film containing one or more selected from silver, palladium, copper, titanium, aluminum, etc.
  • a reflective film may be provided between the insulating layer 125 and the resin layer 126, and the light emitted from the light-emitting layer may be reflected by the reflective film. This can improve the light extraction efficiency.
  • Layer 128 is a portion of a protective layer (also called a mask layer or a sacrificial layer) that protects organic layer 112 when the organic layer 112 is etched.
  • a protective layer also called a mask layer or a sacrificial layer
  • the material that can be used for insulating layer 125 can be used for layer 128. In particular, it is preferable to use the same material for layer 128 and insulating layer 125, since the same processing equipment can be used.
  • inorganic insulating films such as aluminum oxide films, metal oxide films such as hafnium oxide films, and silicon oxide films formed by the ALD method have few pinholes, so they have excellent functionality for protecting the EL layer and can be suitably used for insulating layer 125 and layer 128.
  • the protective layer 121 can have, for example, a single-layer structure or a laminated structure including at least an inorganic insulating film.
  • the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film.
  • a semiconductor material or a conductive material such as indium gallium oxide, indium zinc oxide, indium tin oxide, or indium gallium zinc oxide may be used as the protective layer 121.
  • the protective layer 121 may be a laminated film of an inorganic insulating film and an organic insulating film.
  • an organic insulating film is sandwiched between a pair of inorganic insulating films.
  • the organic insulating film it is preferable for the organic insulating film to function as a planarizing film. This allows the upper surface of the organic insulating film to be flat, improving the coverage of the inorganic insulating film thereon and enhancing the barrier properties.
  • the upper surface of the protective layer 121 is flat, it is preferable that when a structure (e.g., a color filter, an electrode of a touch sensor, or a lens array) is provided above the protective layer 121, the effect of uneven shapes caused by the structure below can be reduced.
  • a structure e.g., a color filter, an electrode of a touch sensor, or a lens array
  • FIG. 30C shows a connection portion 130 where the connection electrode 111C and the common electrode 113 are electrically connected.
  • an opening is provided in the insulating layer 125 and the resin layer 126 above the connection electrode 111C.
  • the connection electrode 111C and the common electrode 113 are electrically connected in the opening.
  • FIG. 30C shows connection portion 130 where connection electrode 111C and common electrode 113 are electrically connected
  • common electrode 113 may be provided on connection electrode 111C via common layer 114.
  • the electrical resistivity of the material used for common layer 114 is sufficiently low and it can be formed thin, so there are many cases where no problem occurs even if common layer 114 is located at connection portion 130. This allows common electrode 113 and common layer 114 to be formed using the same shielding mask, thereby reducing manufacturing costs.
  • FIG. 31A shows a schematic cross-sectional view of the display device 100a.
  • the display device 100a differs from the display device 100 described above mainly in that the light-emitting element has a different configuration and in that the display device 100a has a colored layer.
  • the display device 100a has a light-emitting element 110W that emits white light.
  • the light-emitting element 110W has a pixel electrode 111, an organic layer 112W, a common layer 114, and a common electrode 113.
  • the organic layer 112W emits white light.
  • the organic layer 112W can be configured to include two or more types of light-emitting materials whose emitted light colors are complementary to each other.
  • the organic layer 112W can be configured to include a light-emitting organic compound that emits red light, a light-emitting organic compound that emits green light, and a light-emitting organic compound that emits blue light. It may also be configured to include a light-emitting organic compound that emits blue light and a light-emitting organic compound that emits yellow light.
  • the organic layers 112W are separated between two adjacent light-emitting elements 110W. This makes it possible to suppress leakage current flowing between adjacent light-emitting elements 110W via the organic layers 112W, and to suppress crosstalk caused by the leakage current. This makes it possible to realize a display device with high contrast and color reproducibility.
  • An insulating layer 122 that functions as a planarizing film is provided on the protective layer 121, and colored layers 116R, 116G, and 116B are provided on the insulating layer 122.
  • the insulating layer 122 can be an organic resin film or an inorganic insulating film with a flattened upper surface.
  • the insulating layer 122 forms the surface on which the colored layers 116R, 116G, and 116B are formed. Therefore, by making the upper surface of the insulating layer 122 flat, the thickness of the colored layers 116R, etc. can be made uniform, thereby improving the color purity. Note that if the thickness of the colored layers 116R, etc. is not uniform, the amount of light absorbed will vary depending on the location of the colored layer 116R, which may result in a decrease in color purity.
  • FIG. 31B shows a schematic cross-sectional view of the display device 100b.
  • Light-emitting element 110R has pixel electrode 111, conductive layer 115R, organic layer 112W, and common electrode 113.
  • Light-emitting element 110G has pixel electrode 111, conductive layer 115G, organic layer 112W, and common electrode 113.
  • Light-emitting element 110B has pixel electrode 111, conductive layer 115B, organic layer 112W, and common electrode 113.
  • Conductive layer 115R, conductive layer 115G, and conductive layer 115B each have translucency and function as an optical adjustment layer.
  • a microresonator (microcavity) structure By using a film that reflects visible light for the pixel electrode 111 and a film that is both reflective and transparent to visible light for the common electrode 113, a microresonator (microcavity) structure can be realized.
  • a microresonator (microcavity) structure By adjusting the thicknesses of the conductive layers 115R, 115G, and 115B so as to provide optimal optical path lengths, it is possible to obtain intensified light of different wavelengths from the light-emitting elements 110R, 110G, and 110B, even when an organic layer 112 that emits white light is used.
  • colored layers 116R, 116G, and 116B are provided on the optical paths of light-emitting elements 110R, 110G, and 110B, respectively, to obtain light with high color purity.
  • an insulating layer 123 is provided to cover the ends of the pixel electrode 111 and the conductive layer 115.
  • the insulating layer 123 preferably has a tapered end.
  • the organic layer 112W and the common electrode 113 are each provided as a continuous film common to each light-emitting element. This configuration is preferable because it can greatly simplify the manufacturing process of the display device.
  • the pixel electrode 111 has an end shape that is nearly vertical. This allows a steeply inclined portion to be formed on the surface of the insulating layer 123, and a thin portion can be formed in the part of the organic layer 112W that covers this portion, or a part of the organic layer 112W can be separated. Therefore, it is possible to suppress leakage current that occurs through the organic layer 112W between adjacent light-emitting elements without processing the organic layer 112W by a photolithography method or the like.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments and examples described in this specification.
  • the electronic device of this embodiment has a display panel (display device) in which a transistor of one embodiment of the present invention is applied to a display portion.
  • the display device of one embodiment of the present invention can easily achieve high definition and high resolution, and can also achieve high display quality. Therefore, the display device can be used in the display portion of various electronic devices.
  • Electronic devices include, for example, electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display panel of one embodiment of the present invention is capable of increasing the resolution, and therefore can be suitably used in electronic devices having a relatively small display.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, glasses-type AR devices, and MR devices.
  • the display panel of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • HD 1280 x 720 pixels
  • FHD (1920 x 1080 pixels
  • WQHD 2560 x 1440 pixels
  • WQXGA 2560 x 1600 pixels
  • 4K 3840 x 2160 pixels
  • 8K 8K
  • the pixel density (resolution) of the display panel of one embodiment of the present invention is preferably 100 ppi or more, more preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more.
  • the screen ratio (aspect ratio) of the display panel of one embodiment of the present invention can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.
  • the electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • FIG. 32A to 32D An example of a wearable device that can be worn on the head will be described using Figures 32A to 32D.
  • These wearable devices have one or both of the functions of displaying AR content and VR content. Note that these wearable devices may also have the function of displaying SR or MR content in addition to AR and VR.
  • Electronic device 700A shown in FIG. 32A and electronic device 700B shown in FIG. 32B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.
  • a display panel according to one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can display images with extremely high resolution.
  • Electronic device 700A and electronic device 700B can each project an image displayed on display panel 751 onto display area 756 of optical member 753. Because optical member 753 is translucent, the user can see the image displayed in the display area superimposed on the transmitted image visible through optical member 753. Therefore, electronic device 700A and electronic device 700B are each electronic devices capable of AR display.
  • Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image of the front as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.
  • an acceleration sensor such as a gyro sensor
  • the communication unit has a wireless communication device, and can supply video signals and the like via the wireless communication device.
  • a connector can be provided to which a cable through which a video signal and power supply potential can be connected.
  • electronic device 700A and electronic device 700B are provided with batteries, and can be charged wirelessly and/or wired.
  • the housing 721 may be provided with a touch sensor module.
  • the touch sensor module has a function of detecting that the outer surface of the housing 721 is touched.
  • the touch sensor module can detect a tap operation or a slide operation by the user and execute various processes. For example, a tap operation can execute processes such as pausing or resuming a video, and a slide operation can execute processes such as fast-forwarding or rewinding. Furthermore, by providing a touch sensor module on each of the two housings 721, the range of operations can be expanded.
  • touch sensors can be used as the touch sensor module.
  • various types can be adopted, such as the capacitance type, resistive film type, infrared type, electromagnetic induction type, surface acoustic wave type, and optical type.
  • a photoelectric conversion device (also called a photoelectric conversion element) can be used as the light receiving device (also called a light receiving element).
  • the active layer of the photoelectric conversion device can be made of either or both of an inorganic semiconductor and an organic semiconductor.
  • Electronic device 800A shown in FIG. 32C and electronic device 800B shown in FIG. 32D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.
  • a display panel according to one embodiment of the present invention can be applied to the display portion 820. Therefore, the electronic device can display images with extremely high resolution. This allows the user to feel a high sense of immersion.
  • the display unit 820 is provided inside the housing 821 at a position that can be seen through the lens 832. In addition, by displaying different images on the pair of display units 820, it is also possible to perform a three-dimensional display using parallax.
  • the electronic device 800A and the electronic device 800B can each be considered electronic devices for VR.
  • a user wearing the electronic device 800A or the electronic device 800B can view the image displayed on the display unit 820 through the lens 832.
  • Electric device 800A and electronic device 800B each preferably have a mechanism that can adjust the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that they have a mechanism that can adjust the focus by changing the distance between lens 832 and display unit 820.
  • the attachment unit 823 allows the user to attach the electronic device 800A or electronic device 800B to the head. Note that in FIG. 32C and other figures, the attachment unit 823 is shaped like the temples of glasses, but is not limited to this. The attachment unit 823 only needs to be wearable by the user, and may be shaped like a helmet or band, for example.
  • the imaging unit 825 has a function of acquiring external information.
  • the data acquired by the imaging unit 825 can be output to the display unit 820.
  • An image sensor can be used for the imaging unit 825.
  • multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.
  • a distance measuring sensor capable of measuring the distance to an object
  • the imaging unit 825 is one aspect of the detection unit.
  • the detection unit for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection and Ranging) can be used.
  • LIDAR Light Detection and Ranging
  • the electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone.
  • a vibration mechanism that functions as a bone conduction earphone.
  • a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This makes it possible to enjoy video and audio by simply wearing the electronic device 800A without the need for separate audio equipment such as headphones, earphones, or speakers.
  • Each of the electronic devices 800A and 800B may have an input terminal.
  • the input terminal can be connected to a cable that supplies a video signal from a video output device or the like, and power for charging a battery provided within the electronic device.
  • the electronic device of one embodiment of the present invention may have a function of wireless communication with an earphone 750.
  • the earphone 750 has a communication unit (not shown) and has a wireless communication function.
  • the earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function.
  • the electronic device 700A shown in FIG. 32A has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device 800A shown in FIG. 32C has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device may also have an earphone unit.
  • Electronic device 700B shown in FIG. 32B has earphone unit 727.
  • earphone unit 727 and the control unit may be configured to be connected to each other by wire.
  • Part of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or attachment unit 723.
  • electronic device 800B shown in FIG. 32D has earphone unit 827.
  • earphone unit 827 and control unit 824 can be configured to be connected to each other by wire.
  • Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or mounting unit 823.
  • earphone unit 827 and mounting unit 823 may have magnets. This allows earphone unit 827 to be fixed to mounting unit 823 by magnetic force, which is preferable as it makes storage easier.
  • the electronic device may have an audio output terminal to which earphones or headphones can be connected.
  • the electronic device may also have one or both of an audio input terminal and an audio input mechanism.
  • a sound collection device such as a microphone can be used as the audio input mechanism.
  • the electronic device may be endowed with the functionality of a so-called headset.
  • both glasses-type devices such as electronic device 700A and electronic device 700B
  • goggle-type devices such as electronic device 800A and electronic device 800B
  • the electronic device 6500 shown in FIG. 33A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509.
  • the display portion 6502 has a touch panel function.
  • the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like. The use of the semiconductor device of one embodiment of the present invention for the control device 6509 is preferable because power consumption can be reduced.
  • a display panel according to one embodiment of the present invention can be applied to the display portion 6502.
  • FIG. 33B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.
  • a translucent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.
  • the display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).
  • a part of the display panel 6511 is folded back in the area outside the display unit 6502, and the FPC 6515 is connected to the folded back part.
  • An IC 6516 is mounted on the FPC 6515.
  • the FPC 6515 is connected to a terminal provided on a printed circuit board 6517.
  • the flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized.
  • the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small.
  • a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.
  • FIG. 33C shows an example of a television device.
  • a display unit 7000 is built into a housing 7101.
  • the housing 7101 is supported by a stand 7103.
  • the television device 7100 shown in FIG. 33C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111.
  • the display unit 7000 may be provided with a touch sensor, and the television device 7100 may be operated by touching the display unit 7000 with a finger or the like.
  • the remote control 7111 may have a display unit that displays information output from the remote control 7111.
  • the channel and volume can be operated using operation keys or a touch panel provided on the remote control 7111, and the image displayed on the display unit 7000 can be operated.
  • the television device 7100 is configured to include a receiver and a modem.
  • the receiver can receive general television broadcasts.
  • by connecting to a wired or wireless communication network via the modem it is also possible to carry out one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.
  • FIG. 33D shows an example of a notebook personal computer.
  • the notebook personal computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, and the like.
  • a display portion 7000 is incorporated in the housing 7211.
  • the control device 7216 has, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 7000, the control device 7216, and the like.
  • the use of the semiconductor device of one embodiment of the present invention for the control device 7216 is preferable because power consumption can be reduced.
  • Figures 33E and 33F show an example of digital signage.
  • the digital signage 7300 shown in FIG. 33E has a housing 7301, a display unit 7000, and a speaker 7303. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.
  • FIG. 33F shows digital signage 7400 attached to a cylindrical pole 7401.
  • Digital signage 7400 has a display unit 7000 that is provided along the curved surface of pole 7401.
  • the larger the display unit 7000 the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of an advertisement, for example.
  • a touch panel By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • a display panel according to one embodiment of the present invention can be applied to the display portion 7000.
  • the electronic device shown in Figures 34A to 34G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light), a microphone 9008, etc.
  • the electronic devices shown in Figures 34A to 34G have various functions. For example, they can have a function of displaying various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, etc.
  • the functions of the electronic devices are not limited to these, and they can have various functions.
  • the electronic devices may have multiple display units.
  • the electronic devices may have a function of providing a camera or the like to capture still images or videos and store them on a recording medium (external or built into the camera), a function of displaying the captured images on the display unit, etc.
  • FIG. 34A is a perspective view showing a mobile information terminal 9101.
  • the mobile information terminal 9101 can be used as a smartphone, for example.
  • the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like.
  • the mobile information terminal 9101 can display text and image information on multiple surfaces.
  • FIG. 34A shows an example in which three icons 9050 are displayed.
  • Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mail, SNS, telephone calls, etc., the title of e-mail or SNS, the sender's name, the date and time, the remaining battery level, and radio wave strength.
  • an icon 9050 or the like may be displayed at the position where the information 9051 is displayed.
  • Figure 34B is a perspective view showing a mobile information terminal 9102.
  • the mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001.
  • information 9052, information 9053, and information 9054 are each displayed on different sides.
  • a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether or not to answer a call.
  • FIG. 34C is a perspective view showing a tablet terminal 9103.
  • the tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, Internet communication, and computer games, for example.
  • the tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of the housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.
  • FIG. 34D is a perspective view showing a wristwatch-type mobile information terminal 9200.
  • the mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark).
  • the display surface of the display unit 9001 is curved, and display can be performed along the curved display surface.
  • the mobile information terminal 9200 can also make hands-free calls by communicating with, for example, a headset capable of wireless communication.
  • the mobile information terminal 9200 can also transmit data to and from other information terminals and charge itself via a connection terminal 9006. Charging may be performed by wireless power supply.
  • FIG. 34E to 34G are perspective views showing a foldable mobile information terminal 9201.
  • FIG. 34E is a perspective view of the mobile information terminal 9201 in an unfolded state
  • FIG. 34G is a perspective view of the mobile information terminal 9201 in a folded state
  • FIG. 34F is a perspective view of the mobile information terminal 9201 in a state in the middle of changing from one of FIG. 34E and FIG. 34G to the other.
  • the mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area that provides excellent viewability of the display when unfolded.
  • the display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055.
  • the display unit 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments and examples described in this specification.
  • the contact resistance between wiring containing ruthenium and wiring containing an oxide semiconductor was evaluated. Specifically, a sample was prepared in which wiring containing ruthenium and wiring containing an oxide semiconductor were in contact with each other, and the contact resistance was measured using the four-terminal method.
  • Each of Sample 1A and Sample 1B has a first wiring having a width of 5 ⁇ m and an element located on the first wiring and provided with a second wiring having a width of 5 ⁇ m.
  • the second wiring is provided by extending in a direction perpendicular to the first wiring.
  • 36 elements each having the above-mentioned first wiring and second wiring were provided.
  • the first wiring of sample 1A is a laminated film (referred to as W ⁇ ITSO film) of a tungsten film (referred to as W film) and an indium tin oxide film with added silicon (referred to as ITSO film) on the W film.
  • W ⁇ ITSO film a laminated film of a tungsten film (referred to as W film) and an indium tin oxide film with added silicon (referred to as ITSO film) on the W film.
  • the W film had a thickness of 50 nm and was deposited by sputtering using a tungsten target.
  • the deposition conditions were as follows: 10 sccm of Ar gas was used as the deposition gas, the pressure was 0.4 Pa, the deposition power was 1000 W using a DC power source, and the substrate temperature was 130°C.
  • the ITSO film had a thickness of 10 nm and was formed by sputtering using an indium tin oxide target containing SiO 2.
  • the indium tin oxide target containing SiO 2 contained 5 wt % of SiO 2 , 10 wt % of SnO 2 , and 85 wt % of In 2 O 3.
  • the film formation conditions were as follows: Ar gas 50 sccm and O 2 gas 1.5 sccm were used as the film formation gas, the pressure was 0.4 Pa, the film formation power was 1000 W with a DC power source, and the substrate temperature was room temperature.
  • the second wiring of sample 1A is a laminated film (referred to as IGZO ⁇ W film) of an In-Ga-Zn oxide film (referred to as IGZO film) and a W film on the IGZO film.
  • the W film was deposited under the same conditions as the first wiring.
  • the IGZO film had a thickness of 20 nm and was formed by sputtering using an oxide target with an In:Ga:Zn ratio of 1:1:1.2 [atomic ratio].
  • the film formation conditions were as follows: Ar gas 10 sccm and O2 gas 90 sccm were used as the film formation gas, the pressure was 0.5 Pa, the film formation power was 2000 W by RF power supply, and the substrate temperature was 250°C.
  • the first wiring of sample 1B is a laminated film (referred to as Ru film) of a ruthenium film (referred to as Ru film) and an ITSO film on the Ru film (referred to as Ru ⁇ ITSO film).
  • the ITSO film was formed under the same conditions as the first wiring of sample 1A.
  • the Ru film had a thickness of 20 nm and was deposited by sputtering using a ruthenium target.
  • the deposition conditions were: 50 sccm of Ar gas as deposition gas, 0.4 Pa pressure, 500 W deposition power from a DC power source, and room temperature substrate temperature.
  • the second wiring of sample 1B was subjected to the same conditions as the second wiring of sample 1A. Therefore, in samples 1A and 1B, the ITSO film and the IGZO film are in contact at the intersection of the first wiring and the second wiring.
  • Figure 35 The results of measuring the contact resistance of Sample 1A and Sample 1B using the four-terminal method are shown in Figure 35.
  • the vertical axis is contact resistance [ ⁇ ].
  • Figure 35 shows the contact resistance values of 36 elements of Sample 1A and Sample 1B (shown as white circles) and the median contact resistance values of 36 elements of Sample 1A and Sample 1B (shown as lines).
  • a voltage of 0.01 V was applied between one end of the first wiring and one end of the second wiring to calculate the contact resistance value.
  • the median contact resistance of sample 1A was 25 ⁇
  • the median contact resistance of sample 1B was 16 ⁇ .
  • sample 1B exhibited a contact resistance equal to or lower than that of sample 1A.
  • sample 2A was prepared by laminating a first conductive film, an interlayer film, a second conductive film, and an SOG film in this order on a silicon substrate on which a silicon oxide film was formed, and an opening was formed that reached the first conductive film of sample 2A.
  • Sample 2B was also prepared, which had a similar structure to sample 2A, but further had a tungsten film (referred to as W film) between the second conductive film and the SOG film, and an opening was formed that reached the first conductive film of sample 2B.
  • the diameter of the opening was 60 nm in samples 2A and 2B.
  • the first conductive film corresponds to the conductor 220 shown in FIG. 4B
  • the interlayer film corresponds to the insulator 280
  • the second conductive film corresponds to the conductive film 240A and the conductive film 240B
  • the SOG film corresponds to the coating film 277 shown in FIGS. 5A to 5D and 7A to 7D
  • the W film corresponds to the inorganic film 276 shown in FIGS. 7A to 7D.
  • Sample 2A was produced by the method shown in Figs. 5A to 5D
  • Sample 2B was produced by the method shown in Figs. 7A to 7D.
  • the method for producing Sample 2B is the same as the method for producing Sample 2A, except for the steps related to the W film. Below, the methods for producing Sample 2A and Sample 2B will be described in parallel.
  • the first conductive film was a laminated film (W ⁇ ITSO film) of a tungsten film (W film) and an indium tin oxide film with added silicon (ITSO film).
  • the W film had a thickness of 20 nm and was formed by a sputtering method using a tungsten target.
  • the ITSO film had a thickness of 10 nm and was formed by a sputtering method using an indium tin oxide target containing SiO 2.
  • the indium tin oxide target containing SiO 2 contained 5% by weight of SiO 2 , 10% by weight of SnO 2 , and 85% by weight of In 2 O 3 .
  • the interlayer film was a three-layer laminate film of a silicon nitride film (referred to as SiNx film), a silicon oxide film (referred to as SiOx film), and a SiNx film, as in FIG. 10B.
  • the first layer of SiNx film had a thickness of 5 nm and was formed by the PEALD method.
  • the second layer of SiOx film had a thickness of 20 nm and was formed by the sputtering method using a silicon target.
  • the third layer of SiNx film had a thickness of 10 nm and was formed by the sputtering method using a silicon target.
  • the second conductive film was a laminated film (referred to as Ru film) of a ruthenium film (referred to as Ru film) and an indium tin oxide film with added silicon (referred to as Ru ⁇ ITSO film).
  • Ru film had a thickness of 15 nm and was formed by a sputtering method using a ruthenium target.
  • ITSO film had a thickness of 10 nm and was formed under the same conditions as the above ITSO film.
  • the W film had a thickness of 10 nm and was formed by sputtering using a tungsten target.
  • a positive resist film was formed on the samples 2A and 2B prepared as described above, similar to Figs. 5A and 7A.
  • An electron beam was irradiated onto the resist film to form an opening with a diameter of 60 nm.
  • the SOG film was etched in the same manner as in Fig. 5B and Fig. 7B.
  • a DF-CCP etching device was used for etching the SOG film.
  • CHF3 gas 67 sccm and O2 gas 13 sccm were used as etching gas.
  • 550 W was supplied to the upper electrode using a 60 MHz RF power supply, and 350 W was supplied to the lower electrode using a 2 MHz RF power supply.
  • Other conditions were an electrode distance of 40 mm, a pressure of 5.3 Pa, and a lower electrode temperature of 20°C.
  • etching of the W film was performed in the same manner as in FIG. 7B.
  • a DF-CCP etching apparatus was used for etching the W film.
  • As etching gases Cl2 gas 11 sccm, O2 gas 22 sccm, and CF4 gas 22 sccm were used. 1000 W was supplied to the upper electrode using a 60 MHz RF power supply, and 25 W was supplied to the lower electrode using a 13.56 MHz RF power supply. Other conditions were an electrode distance of 80 mm, a pressure of 0.6 Pa, and a lower electrode temperature of 20°C.
  • the ITSO film was etched in the same manner as in Fig. 5C and Fig. 7C.
  • a DF-CCP etching device was used for etching the ITSO film.
  • CH4 gas 18 sccm and Ar gas 42 sccm were used as etching gas.
  • 1000 W was supplied to the upper electrode using a 60 MHz RF power supply, and 200 W was supplied to the lower electrode using a 13.56 MHz RF power supply.
  • Other conditions were an electrode distance of 120 mm, a pressure of 1.2 Pa, and a lower electrode temperature of 60°C.
  • the Ru film was etched in the same manner as in Fig. 5D and Fig. 7C.
  • An ICP etching device was used for etching the Ru film.
  • Cl2 gas 25 sccm and O2 gas 175 sccm were used as etching gas.
  • 3000 W was supplied to the upper electrode (antenna coil) using a 13.56 MHz RF power supply, and 200 W was supplied to the lower electrode using a 3.2 MHz RF power supply.
  • Other conditions were an electrode distance of 200 mm, a pressure of 0.67 Pa, and a lower electrode temperature of 40 °C.
  • the interlayer film was etched in the same manner as in Fig. 4B and Fig. 7D.
  • a DF-CCP etching device was used for etching the interlayer film.
  • CH2F2 gas 16 sccm, O2 gas 20 sccm, CHF3 gas 30 sccm, CF4 gas 30 sccm, and Ar gas 300 sccm were used as etching gas.
  • 300 W was supplied to the lower electrode using a 40 MHz RF power supply, and 600 W was simultaneously supplied using a 13 MHz RF power supply.
  • Other conditions were an electrode distance of 40 mm, a pressure of 4.6 Pa, and a lower electrode temperature of 30°C.
  • the W film was etched to remove the W film functioning as a hard mask.
  • a DF-CCP etching device was used to etch the W film.
  • the etching conditions for the W film were the same as those described above.
  • Cross-sectional SEM images were taken of Sample 2A and Sample 2B prepared as described above. Cross-sectional SEM images were taken using a Hitachi High-Tech "SU8030" at an accelerating voltage of 5 kV.
  • FIGS 36A and 36B Cross-sectional SEM images of sample 2A and sample 2B are shown in Figures 36A and 36B.
  • the taper angle of the sidewall of the opening in the interlayer film was 84°
  • sample 2B the taper angle of the sidewall of the opening in the interlayer film was 85°.
  • the taper angle of the sidewall of the ITSO film of the second conductive film was 45°, which was the same shape as the structure shown in Figure 6A.
  • the taper angle of the sidewall of the ITSO film of the second conductive film was also approximately the same as the taper angle of the sidewall of the opening in the interlayer film.
  • openings with roughly vertical sidewalls could be formed in the interlayer film. This is because the Ru film and W film on the interlayer film functioned as a hard mask in the dry etching process of the interlayer film. Furthermore, in sample 2B, the sidewalls of the ITSO film of the second conductive film could also be made roughly vertical. This is because the W film on the second conductive film functioned as a hard mask in the dry etching process of the second conductive film. Therefore, as shown in the above embodiment, it is preferable to provide a metal film that functions as a hard mask on the conductive layer that functions as the source electrode or drain electrode on the interlayer film.
  • the oxide semiconductor film formed on the metal oxide film was observed using STEM (Scanning Transmission Electron Microscopy).
  • Sample 3A and sample 3B each have a structure in which a metal oxide film and an oxide semiconductor film on the metal oxide film are formed on a silicon substrate on which a thermal oxide film has been formed.
  • ITSO film indium tin oxide film with added silicon
  • ITO film indium tin oxide film
  • ITO film indium tin oxide film
  • ITO film indium tin oxide film
  • IGZO film In-Ga-Zn oxide film
  • the ITSO film had a thickness of 10 nm and was formed by sputtering using an indium tin oxide target containing SiO 2.
  • the indium tin oxide target containing SiO 2 contained 5 wt % of SiO 2 , 10 wt % of SnO 2 , and 85 wt % of In 2 O 3.
  • the film formation conditions were as follows: Ar gas 50 sccm and O 2 gas 1.5 sccm were used as the film formation gas, the pressure was 0.4 Pa, the film formation power was 1000 W with a DC power source, and the substrate temperature was room temperature.
  • the ITO film had a thickness of 10 nm and was formed by sputtering using an indium tin oxide target.
  • the indium tin oxide target contained 10% by weight of SnO2 and 90% by weight of In2O3 .
  • the film formation conditions were as follows: Ar gas 50 sccm and O2 gas 1 sccm were used as the film formation gas, the pressure was 0.7 Pa, the film formation power was 500 W with a DC power source, and the substrate temperature was room temperature.
  • the IGZO film had a thickness of 10 nm and was formed by sputtering using an oxide target with an In:Ga:Zn ratio of 1:1:1.2 [atomic ratio].
  • the film formation conditions were as follows: Ar gas 10 sccm and O2 gas 90 sccm were used as the film formation gas, the pressure was 0.5 Pa, the film formation power was 2000 W by RF power supply, and the substrate temperature was 250°C.
  • Cross-sectional STEM images of the prepared samples 3A and 3B were taken using a Hitachi High-Tech HD-2700 with an acceleration voltage of 200 kV.
  • Figure 37 shows a cross-sectional STEM image of sample 3A
  • Figure 38 shows a cross-sectional STEM image of sample 3B.
  • FFT Fast Fourier Transform
  • the FFT image in Figure 37 confirmed that the IGZO film of sample 3A had two spots.
  • two spots of high intensity may be seen in the FFT image.
  • the angle of the line segment connecting these two spots represents the crystal orientation of the CAAC-OS. Therefore, it is considered that the IGZO film of sample 3A has become CAAC-OS.
  • no clear spots were confirmed in the ITSO film. Therefore, it is considered that the ITSO film has become amorphous.
  • the band offset ⁇ Ec was a very small value of 0.04 eV.
  • the band offset ⁇ Ec is the difference between the energy of the conduction band bottom of the ITSO film and the energy of the conduction band bottom of the IGZO film.
  • the IGZO film had a higher conduction band bottom energy than the ITSO film.
  • the band offset ⁇ Ec was calculated by measuring the energy of the valence band top of the ITSO film and the energy of the valence band top of the IGZO film by XPS measurement. In this way, the band offset of the ITSO film and the IGZO film is very small.
  • the ITSO film and the IGZO film are in almost ohmic contact.
  • the ITSO film having an amorphous structure of sample 3A and the IGZO film having a CAAC-OS structure are in almost ohmic contact.
  • a crystalline oxide semiconductor film can be formed by forming an oxide semiconductor film on a metal oxide film. Therefore, as shown in the above embodiment, by providing a metal oxide film on the upper layer of the source electrode and the drain electrode, the oxide semiconductor film in contact with the upper layer of the source electrode and the drain electrode can be made crystalline.
  • a CAAC-OS film with few crystal grain boundaries can be formed by forming an oxide semiconductor film on a metal oxide film with an amorphous structure. Therefore, as shown in the above embodiment, by providing a metal oxide film with an amorphous structure, such as an ITSO film, on the upper layer of the source electrode and the drain electrode, the oxide semiconductor film in contact with the upper layer of the source electrode and the drain electrode can be a CAAC-OS film. At this time, the source electrode and the drain electrode are in ohmic contact with the oxide semiconductor film, so that a transistor with good electrical characteristics can be provided.
  • a metal oxide film with an amorphous structure such as an ITSO film
  • sample 4A was prepared by laminating a first conductive film, an interlayer film, a second conductive film, an SOC film, and an SOG film in this order on a silicon substrate on which a silicon oxide film had been formed. An opening was formed that reached the first conductive film of sample 4A, and a sidewall-shaped insulator was then formed. The diameter of the opening in sample 4A was set to 60 nm.
  • the first conductive film corresponds to the conductor 220 shown in FIG. 14B
  • the interlayer film corresponds to the insulator 280
  • the second conductive film corresponds to the conductive film 240A and the conductive film 240B
  • the SOC film and the SOG film correspond to the coating film 277 shown in FIGS. 5A to 5D.
  • Sample 4A was produced by the method shown in Figures 5A to 5D, 14A, and 14B.
  • the first conductive film was a laminated film (W ⁇ ITSO film) of a tungsten film (W film) and an indium tin oxide film with added silicon (ITSO film).
  • the W film had a thickness of 20 nm, and was formed by a sputtering method using a tungsten target.
  • the ITSO film had a thickness of 20 nm, and was formed by a sputtering method using an indium tin oxide target containing SiO 2.
  • the indium tin oxide target containing SiO 2 contained 5% by weight of SiO 2 , 10% by weight of SnO 2 , and 85% by weight of In 2 O 3 .
  • the interlayer film was a three-layer laminate film of a silicon nitride film (referred to as SiNx film), a silicon oxide film (referred to as SiOx film), and a SiNx film, as in FIG. 14A.
  • the first layer of SiNx film had a thickness of 5 nm and was formed by the PEALD method.
  • the second layer of SiOx film had a thickness of 20 nm and was formed by the sputtering method using a silicon target.
  • the third layer of SiNx film had a thickness of 10 nm and was formed by the sputtering method using a silicon target.
  • the second conductive film was a laminated film of a W film and an ITSO film (referred to as a W ⁇ ITSO film).
  • the W film had a thickness of 15 nm
  • the ITSO film had a thickness of 10 nm.
  • the W ⁇ ITSO film was formed under the same conditions as the W ⁇ ITSO film of the first conductive film.
  • a positive resist film was formed on the sample 4A prepared as described above, similar to FIG. 5A.
  • the resist film was irradiated with an electron beam, and the electron beam irradiated area was removed with a developer to form an opening with a diameter of 60 nm in the resist film.
  • the SOG film and SOC film were etched in the same manner as in FIG. 5B.
  • a DF-CCP etching device was used to etch the SOG film and SOC film.
  • etching gas In the etching of the SOG film, 67 sccm of CHF3 gas and 13 sccm of O2 gas were used as etching gas. 550 W was supplied to the upper electrode using a 60 MHz RF power supply, and 350 W was supplied to the lower electrode using a 2 MHz RF power supply. Other conditions were: electrode distance 40 mm, pressure 5.3 Pa, and lower electrode temperature 20°C.
  • H3 gas 500 sccm and N2 gas 150 sccm were used as etching gas. 1000 W was supplied to the upper electrode using a 60 MHz RF power supply, and 200 W was supplied to the lower electrode using a 2 MHz RF power supply. Other conditions were: electrode distance 25 mm, pressure 6.6 Pa, and lower electrode temperature 20 °C.
  • the ITSO film was etched in the same manner as in FIG. 5C.
  • a DF-CCP etching apparatus was used for etching the ITSO film.
  • CH4 gas 18 sccm and Ar gas 42 sccm were used as etching gas.
  • 1000 W was supplied to the upper electrode using a 60 MHz RF power supply, and 600 W was supplied to the lower electrode using a 13.56 MHz RF power supply.
  • Other conditions were an electrode distance of 120 mm, a pressure of 1.2 Pa, and a lower electrode temperature of 60°C.
  • the W film was etched in the same manner as in FIG. 5D.
  • a DF-CCP etching device was used for etching the W film.
  • Cl2 gas 11 sccm, O2 gas 22 sccm, and CF4 gas 22 sccm were used as etching gas.
  • 1000 W was supplied to the upper electrode using a 60 MHz RF power supply, and 25 W was supplied to the lower electrode using a 13.56 MHz RF power supply.
  • Other conditions were an electrode distance of 80 mm, a pressure of 1.3 Pa, and a lower electrode temperature of 20°C.
  • the interlayer film was etched.
  • a DF-CCP etching device was used for etching the interlayer film.
  • CH2F2 gas 16 sccm , O2 gas 20 sccm, CHF3 gas 30 sccm, CF4 gas 30 sccm, and Ar gas 300 sccm were used as etching gas.
  • 300 W was supplied to the lower electrode using a 40 MHz RF power supply, and 600 W was simultaneously supplied using a 13 MHz RF power supply.
  • Other conditions were an electrode distance of 40 mm, a pressure of 4.6 Pa, and a lower electrode temperature of 30°C.
  • an insulating film was formed that would become a sidewall-shaped insulator in a later process.
  • the insulating film was a 5 nm-thick SiNx film, and was formed by the PEALD method.
  • anisotropic etching of the SiNx film was performed in the same manner as in FIG. 14B.
  • a DF-CCP etching apparatus was used for etching the SiNx film.
  • CH2F2 gas 25 sccm, O2 gas 5 sccm, and Ar gas 600 sccm were used as etching gas.
  • 100 W was supplied to the lower electrode using a 40 MHz RF power supply, and 50 W was simultaneously supplied using a 13 MHz RF power supply.
  • Other conditions were an electrode distance of 40 mm, a pressure of 6.6 Pa, and a lower electrode temperature of 30°C.
  • sample 4A was fabricated, which has an opening and a sidewall-shaped insulator.
  • Cross-sectional STEM images were taken of sample 4A prepared as described above.
  • Cross-sectional STEM images were taken using a Hitachi High-Tech HD-2700 at an accelerating voltage of 200 kV.
  • a cross-sectional STEM image of sample 4A is shown in Figure 39. From Figure 39, it can be seen that a SiNx film is formed in contact with the sidewall of the opening. It can also be seen that the SiNx film is not formed near the center of the bottom of the opening, or on the top surface of the ITSO film of the second conductive film. The SiNx film is formed in contact with the ITSO film and W film of the second conductive film. In particular, the side surface of the W film of the second conductive film is covered with the SiNx film up to its top end. A recess is formed in the ITSO film of the second conductive film so as to overlap the opening, and a part of the sidewall-shaped SiNx film is formed in the recess.
  • an opening and a sidewall-shaped insulator in contact with the sidewall of the opening could be formed.
  • a vertical transistor by providing a sidewall-shaped insulator in contact with the side of the electrode functioning as the upper source or drain, it is possible to prevent the side of the electrode from contacting the oxide semiconductor and being oxidized. This makes it possible to suppress a decrease in the conductivity of the electrode functioning as the upper source or drain, and to provide a transistor with good on-current, field effect mobility, S value, frequency characteristics, etc.

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JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2017168760A (ja) * 2016-03-18 2017-09-21 株式会社ジャパンディスプレイ 半導体装置
WO2018178793A1 (ja) * 2017-03-29 2018-10-04 株式会社半導体エネルギー研究所 半導体装置、半導体装置の作製方法

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KR101870119B1 (ko) 2009-12-25 2018-06-25 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
CN107947763B (zh) 2010-08-06 2021-12-28 株式会社半导体能源研究所 半导体集成电路
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CN114424339A (zh) 2019-09-20 2022-04-29 株式会社半导体能源研究所 半导体装置及半导体装置的制造方法

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JP2012174836A (ja) * 2011-02-21 2012-09-10 Fujitsu Ltd 縦型電界効果トランジスタとその製造方法及び電子機器
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2017168760A (ja) * 2016-03-18 2017-09-21 株式会社ジャパンディスプレイ 半導体装置
WO2018178793A1 (ja) * 2017-03-29 2018-10-04 株式会社半導体エネルギー研究所 半導体装置、半導体装置の作製方法

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