WO2024176851A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024176851A1
WO2024176851A1 PCT/JP2024/004262 JP2024004262W WO2024176851A1 WO 2024176851 A1 WO2024176851 A1 WO 2024176851A1 JP 2024004262 W JP2024004262 W JP 2024004262W WO 2024176851 A1 WO2024176851 A1 WO 2024176851A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
semiconductor element
thickness direction
main
sealing resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2024/004262
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English (en)
French (fr)
Japanese (ja)
Inventor
健生 高本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2025502267A priority Critical patent/JPWO2024176851A1/ja
Priority to CN202480012157.8A priority patent/CN120677566A/zh
Publication of WO2024176851A1 publication Critical patent/WO2024176851A1/ja
Priority to US19/302,622 priority patent/US20250372484A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/442—Shapes or dispositions of multiple leadframes in a single chip
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H10W70/417—Bonding materials between chips and die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H10W70/427—Bent parts
    • H10W70/429—Bent parts being the outer leads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/438—Shapes or dispositions of side rails, e.g. having holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • This disclosure relates to a semiconductor device.
  • Patent Document 1 discloses an example of a conventional semiconductor device.
  • the semiconductor device disclosed in this document includes leads, a semiconductor element, and a sealing resin.
  • the semiconductor element is supported by the leads.
  • the sealing resin covers a portion of the leads and the semiconductor element.
  • the semiconductor element is bonded to the leads via a bonding material.
  • each part thermally expands and contracts due to heat generated by the semiconductor element.
  • the linear expansion coefficient of the sealing resin is larger than that of the semiconductor element and the leads. Due to this difference in linear expansion coefficient, relatively large stress may act near the periphery of the semiconductor element due to thermal contraction of the sealing resin. In this case, there is a concern that problems such as poor bonding of the semiconductor element and cracks in the sealing resin may occur.
  • One of the objectives of this disclosure is to provide a semiconductor device that is an improvement over conventional devices.
  • this disclosure was conceived in light of the above-mentioned circumstances, and one of the objectives of this disclosure is to provide a semiconductor device that is suitable for reducing the stress acting near the periphery of a semiconductor element.
  • a semiconductor device provided by one aspect of the present disclosure includes a first conductive member having an island portion, a semiconductor element disposed on one side in a thickness direction of the island portion, and a sealing resin covering the semiconductor element and at least a part of the first conductive member.
  • the island portion includes a first edge portion located on one side in a first direction perpendicular to the thickness direction and extending in a second direction perpendicular to the thickness direction and the first direction.
  • the first edge portion is covered by the sealing resin and has a first step portion formed on one side of the second direction relative to the semiconductor element in the second direction.
  • the first step portion is recessed on one side in the second direction relative to the other side in the first direction relative to the other side in the second direction.
  • the above configuration can reduce the stress acting near the periphery of the semiconductor element.
  • FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 2 is a perspective view of a main part of the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 3 is a plan view showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 4 is a plan view showing a main part of the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 5 is a bottom view showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 6 is a bottom view showing a main part of the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 7 is a side view showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG.
  • FIG. 9 is a cross-sectional view taken along line IX-IX in FIG.
  • FIG. 10 is a cross-sectional view taken along line XX in FIG.
  • FIG. 11 is a cross-sectional view taken along line XI-XI in FIG.
  • FIG. 12 is a partially enlarged view of FIG.
  • FIG. 13 is a plan view of a main portion showing a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 14 is a bottom view of a main portion showing a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 15 is a cross-sectional view taken along line XV-XV in FIG.
  • FIG. 16 is a plan view of a main portion showing a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 17 is a bottom view of a main portion showing a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 18 is a plan view of a main portion showing a semiconductor device according to a fourth embodiment of the present disclosure.
  • FIG. 19 is a bottom view of a main portion showing a semiconductor device according to a fourth embodiment of the present disclosure.
  • FIG. 20 is a plan view of a main portion showing a semiconductor device according to a fifth embodiment of the present disclosure.
  • FIG. 21 is a bottom view of a main portion showing a semiconductor device according to a fifth embodiment of the present disclosure.
  • an object A is formed on an object B" and “an object A is formed on an object B” include “an object A is formed directly on an object B” and “an object A is formed on an object B with another object interposed between the object A and the object B” unless otherwise specified.
  • an object A is disposed on an object B” and “an object A is disposed on an object B” include “an object A is disposed directly on an object B” and “an object A is disposed on an object B with another object interposed between the object A and the object B" unless otherwise specified.
  • an object A is located on an object B includes “an object A is located on an object B in contact with an object B” and “an object A is located on an object B with another object interposed between the object A and the object B” unless otherwise specified.
  • an object A overlaps an object B when viewed in a certain direction includes “an object A overlaps the entire object B” and “an object A overlaps a part of an object B.”
  • a surface A faces (one side or the other side of) direction B” is not limited to the case where the angle of surface A with respect to direction B is 90 degrees, but also includes the case where surface A is tilted with respect to direction B.
  • First embodiment: 1 to 12 show a semiconductor device according to a first embodiment of the present disclosure.
  • the semiconductor device A1 of this embodiment includes a semiconductor element 1, a first conductive member 2, a second conductive member 3, a third conductive member 4, and a sealing resin 5.
  • the application of the semiconductor device A1 is not limited in any way, and it is used in electronic devices including a power conversion circuit, such as a DC-DC converter.
  • FIG. 1 is a perspective view of the semiconductor device A1.
  • FIG. 2 is a perspective view of the main part of the semiconductor device A1, omitting the sealing resin 5.
  • FIG. 3 is a plan view of the semiconductor device A1.
  • FIG. 4 is a plan view of the main part of the semiconductor device A1, seen through the sealing resin 5.
  • FIG. 5 is a bottom view of the semiconductor device A1.
  • FIG. 6 is a bottom view of the main part of the semiconductor device A1, seen through the sealing resin 5.
  • FIG. 7 is a side view of the semiconductor device A1.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 4.
  • FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 4.
  • FIG. 10 is a cross-sectional view taken along line X-X in FIG. 4.
  • FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 4.
  • FIG. 12 is a partially enlarged view of FIG. 4.
  • the sealing resin 5 seen through is shown by an imaginary line (two-dot chain line).
  • an example of the thickness direction of the present disclosure is the "thickness direction z".
  • the direction perpendicular to the thickness direction z (the left-right direction in Figures 3 and 4) is an example of the first direction of the present disclosure and is called the "first direction x".
  • the direction perpendicular to the thickness direction z and the first direction x (the up-down direction in Figures 3 and 4) is an example of the second direction of the present disclosure and is called the "second direction y".
  • the upper side in the figure is an example of “one side in the thickness direction” in this disclosure, and is referred to as the "z1 side in the thickness direction z,” and the lower side in the figure is an example of "the other side in the thickness direction” in this disclosure, and is referred to as the "z2 side in the thickness direction z.”
  • the semiconductor element 1 is an element that exerts the electrical function of the semiconductor device A1.
  • the semiconductor element 1 is a three-terminal element having three electrodes, for example a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
  • the semiconductor element 1 may be a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a diode.
  • the semiconductor element 1 is an n-channel type MOSFET with a vertical structure.
  • the semiconductor element 1 is rectangular when viewed in the thickness direction z.
  • the semiconductor element 1 has a first element surface 101, a second element surface 102, a first electrode 11, a second electrode 12, and a third electrode 13.
  • the first element surface 101 and the second element surface 102 are spaced apart in the thickness direction z and face opposite each other.
  • the first element surface 101 faces the z1 side in the thickness direction z.
  • the second element surface 102 faces the z2 side in the thickness direction z.
  • the first electrode 11 is disposed on the first surface 101 of the element. A current corresponding to the power converted by the semiconductor element 1 flows through the first electrode 11. In other words, the first electrode 11 corresponds to the source electrode of the semiconductor element 1.
  • the second electrode 12 is disposed on the second surface 102 of the element. A current corresponding to the power before being converted by the semiconductor element 1 flows through the second electrode 12. In other words, the second electrode 12 corresponds to the drain electrode of the semiconductor element 1.
  • the third electrode 13 is disposed on the first surface 101 of the element.
  • a gate voltage for driving the semiconductor element 1 is applied to the third electrode 13.
  • the third electrode 13 corresponds to the gate electrode of the semiconductor element 1.
  • the area of the third electrode 13 is smaller than the area of the first electrode 11.
  • the first conductive member 2 has an island portion 21, a first terminal portion 22, and a through hole 23.
  • the island portion 21 is a portion on which the entire or part of the semiconductor element 1 is mounted.
  • the island portion 21 includes a part of the first main surface 201 and a part of the second main surface 202. There are no limitations on the shape or size of the island portion 21, and in the illustrated example, it is substantially rectangular when viewed in the thickness direction z.
  • the island portion 21 has a first edge portion 211, a second edge portion 212, a third edge portion 213, and a groove 214.
  • the first edge portion 211 is located on the x1 side of the first direction x and extends in the second direction y.
  • the second edge portion 212 is located on the x2 side of the first direction x and extends in the second direction y.
  • the third edge portion 213 is located on the y2 side of the second direction y and extends in the first direction x.
  • the groove 214 is recessed from the first main surface 201 to the z2 side in the thickness direction z, and has a generally V-shaped cross section.
  • the groove 214 surrounds the semiconductor element 1 when viewed in the thickness direction z.
  • Each of the first edge portion 211, the second edge portion 212, the third edge portion 213, and the groove 214 is covered with the sealing resin 5.
  • the island portion 21 may be configured without the recessed groove 214.
  • the first edge portion 211 has a first step portion 211a, as shown in Figures 4 and 6.
  • the first step portion 211a is formed on the y1 side of the second direction y relative to the semiconductor element 1 in the second direction y.
  • the first step portion 211a is shaped so that the y1 side of the second direction y is recessed toward the x2 side of the first direction x relative to the y2 side of the second direction y.
  • the first step portion 211a is inclined with respect to the first direction x and the second direction y so that it is positioned on the x2 side of the first direction x as it moves toward the y1 side of the second direction y in the second direction y.
  • the second edge portion 212 has a second step portion 212a.
  • the second step portion 212a is formed on the y1 side of the second direction y relative to the semiconductor element 1 in the second direction y.
  • the second step portion 212a is shaped so that the y1 side of the second direction y is recessed toward the x1 side of the first direction x relative to the y2 side of the second direction y.
  • the second step portion 212a is inclined with respect to the first direction x and the second direction y so that it is positioned on the x1 side of the first direction x as it moves toward the y1 side of the second direction y in the second direction y.
  • the island portion 21 includes a main portion 21A, a first thin portion 21B, and a second thin portion 21C, as shown in Figures 4, 6, 10, and 11.
  • the main portion 21A has a portion of the first main surface 201 and a portion of the second main surface 202.
  • the first thin portion 21B is a portion that is connected to the x1 side of the main portion 21A in the first direction x.
  • the first thin portion 21B has a part of the first main surface 201 and a first intermediate surface 203.
  • the first thin portion 21B is a portion that does not have the second main surface 202.
  • the first intermediate surface 203 faces the z2 side in the thickness direction z.
  • the first intermediate surface 203 is located between the first main surface 201 and the second main surface 202 in the thickness direction z.
  • the first thin portion 21B has a shape that is recessed on the z2 side in the thickness direction z with respect to the main portion 21A.
  • the first thin portion 21B includes the entire first edge portion 211.
  • the first step portion 211a is formed in the first thin portion 21B.
  • the second thin portion 21C is a portion that is connected to the x2 side of the main portion 21A in the first direction x.
  • the second thin portion 21C has a part of the first main surface 201 and a second intermediate surface 204.
  • the second thin portion 21C is a portion that does not have the second main surface 202.
  • the second intermediate surface 204 faces the z2 side of the thickness direction z.
  • the second intermediate surface 204 is located between the first main surface 201 and the second main surface 202 in the thickness direction z.
  • the second thin portion 21C has a shape that is recessed on the z2 side of the thickness direction z with respect to the main portion 21A.
  • the second thin portion 21C includes the entire second edge portion 212.
  • the second step portion 212a is formed in the first thin portion 21B.
  • the semiconductor element 1 overlaps the main portion 21A and the first thin portion 21B when viewed in the thickness direction z. Also, the semiconductor element 1 overlaps the main portion 21A and the second thin portion 21C when viewed in the thickness direction z.
  • the semiconductor element 1 is bonded to the first main surface 201 of the island portion 21 via a conductive bonding material 19.
  • the second element surface 102 of the semiconductor element 1 faces the first main surface 201.
  • the second electrode 12 on the second element surface 102 and the first main surface 201 are conductively bonded via the conductive bonding material 19.
  • the specific configuration of the conductive bonding material 19 is not particularly limited, and may be, for example, solder (a metal containing tin and silver).
  • the conductive bonding material 19 may also be formed of a metal paste containing a metal such as silver (Ag).
  • a plating layer made of, for example, silver (Ag) may be formed on the region of the first main surface 201 of the island portion 21 where the semiconductor element 1 is bonded.
  • the first terminal portion 22 is a portion that is connected to the y1 side of the island portion 21 in the second direction y.
  • the first terminal portion 22 includes a portion of the first main surface 201 and a portion of the second main surface 202.
  • the first terminal portion 22 may be used as a terminal when mounting the semiconductor device A1.
  • the through hole 23 penetrates the first conductive member 2 in the thickness direction z.
  • the through hole 23 is filled with a portion of the sealing resin 5.
  • the size of the cross section of the through hole 23 perpendicular to the thickness direction z is larger on the z2 side of the thickness direction z than on the z1 side of the thickness direction z. This has the effect of, for example, preventing the first conductive member 2 from falling off the sealing resin 5.
  • a plating layer made of an alloy mainly composed of tin (Sn), for example, may be formed on the portion of the first conductive member 2 exposed from the sealing resin 5.
  • the second conductive member 3 includes a portion that is disposed on the z1 side of the semiconductor element 1 in the thickness direction z.
  • the second conductive member 3 includes a conductive material such as a metal, for example Cu (copper).
  • the second conductive member 3 has a pad portion 31 and a plurality of second terminal portions 32.
  • the pad portion 31 is a portion that is conductively joined to the first electrode 11 of the semiconductor element 1. There are no limitations on the shape or size of the pad portion 31, and in the illustrated example, it is shaped to overlap most of the first electrode 11 when viewed in the thickness direction z, and also to expose the third electrode 13.
  • the pad portion 31 is bonded to the first electrode 11 of the semiconductor element 1 via a conductive bonding material 39.
  • the pad portion 31 and the first electrode 11 are conductively bonded to each other via the conductive bonding material 39.
  • the specific configuration of the conductive bonding material 39 is not particularly limited, and may be, for example, solder (a metal containing tin and silver).
  • the conductive bonding material 39 may also be formed of a metal paste containing a metal such as silver (Ag).
  • a plating layer made of, for example, silver (Ag) may be formed on the area of the pad portion 31 that is bonded to the semiconductor element 1 (first electrode 11).
  • the second terminals 32 are connected to the pad 31 on the y2 side in the second direction y.
  • the second terminals 32 extend in the second direction y when viewed in the thickness direction z, and are arranged at intervals in the first direction x.
  • the number of the second terminals 32 is not limited, and may be three as in the illustrated example, or may be two, four or more. Also, the configuration may include only one second terminal 32.
  • the second terminal 32 has a portion connected to the pad 31 and covered by the sealing resin 5, a portion protruding from the sealing resin 5 to the y2 side in the second direction y, a portion folded back to the z2 side in the thickness direction z, and a portion located on the z2 side in the thickness direction z.
  • the second terminals 32 are used as terminals when mounting the semiconductor device A1.
  • a plating layer made of an alloy mainly composed of tin (Sn), for example, may be formed on the portion of the second conductive member 3 (the multiple second terminal portions 32) that is exposed from the sealing resin 5.
  • the third conductive member 4 includes a portion that is disposed on the z1 side of the semiconductor element 1 in the thickness direction z.
  • the third conductive member 4 includes a conductive material such as a metal, for example Cu (copper).
  • the second conductive member 3 has a pad portion 41 and a third terminal portion 42, as shown in Figures 1 to 7, 9, and 10.
  • the pad portion 41 is a portion that is conductively joined to the third electrode 13 of the semiconductor element 1. There are no limitations on the shape or size of the pad portion 41, and in the illustrated example, the pad portion 41 is shaped to overlap a portion of the third electrode 13 when viewed in the thickness direction z, and also to expose the third electrode 13.
  • the pad portion 41 is bonded to the third electrode 13 of the semiconductor element 1 via a conductive bonding material 49.
  • the pad portion 41 and the third electrode 13 are conductively bonded to each other via the conductive bonding material 49.
  • the specific configuration of the conductive bonding material 49 is not particularly limited, and may be, for example, solder (a metal containing tin and silver).
  • the conductive bonding material 49 may also be formed of a metal paste containing a metal such as silver (Ag).
  • a plating layer made of, for example, silver (Ag) may be formed on the area of the pad portion 41 that is bonded to the semiconductor element 1 (third electrode 13).
  • the third terminal portion 42 is connected to the pad portion 41 on the y2 side in the second direction y.
  • the third terminal portion 42 extends in the second direction y when viewed in the thickness direction z.
  • the third terminal portion 42 has a portion connected to the pad portion 41 and covered by the sealing resin 5, a portion protruding from the sealing resin 5 to the y2 side in the second direction y, a portion folded back to the z2 side in the thickness direction z, and a portion located on the z2 side in the thickness direction z.
  • the third terminal portion 42 When viewed in the first direction x, has a shape and size that roughly overlaps with the second terminal portion 32.
  • the third terminal portion 42 is used as a terminal when mounting the semiconductor device A1.
  • a plating layer made of an alloy mainly composed of tin (Sn), for example, may be formed on the portion of the third conductive member 4 (third terminal portion 42) exposed from the sealing resin 5.
  • the sealing resin 5 covers the semiconductor element 1 and a portion of each of the first conductive member 2, the second conductive member 3, and the third conductive member 4.
  • the sealing resin 5 has electrical insulation properties.
  • the sealing resin 5 includes, for example, a black epoxy resin containing a filler.
  • the shape of the sealing resin 5 is not limited in any way. As shown in Figures 1, 3 to 11, the sealing resin 5 of this embodiment has a first resin surface 51, a second resin surface 52, a third resin surface 53, a fourth resin surface 54, a fifth resin surface 55, and a sixth resin surface 56.
  • the first resin surface 51 faces the z1 side in the thickness direction z.
  • the second resin surface 52 faces the z2 side in the thickness direction z.
  • the second main surface 202 of the first conductive member 2 is exposed from the second resin surface 52.
  • the first resin surface 51 and the second resin surface 52 are flat surfaces, but are not limited to this and may be curved or bent surfaces, for example.
  • the second resin surface 52 and the second main surface 202 are flush with each other.
  • the third resin surface 53 is a surface facing the x1 side in the first direction x.
  • the fourth resin surface 54 is a surface facing the x2 side in the first direction x.
  • the third resin surface 53 and the fourth resin surface 54 are slightly curved surfaces, but are not limited to this and may be, for example, curved surfaces or flat surfaces.
  • the fifth resin surface 55 is a surface facing the y1 side in the second direction y.
  • the sixth resin surface 56 is a surface facing the y2 side in the second direction y.
  • the fifth resin surface 55 and the sixth resin surface 56 are slightly curved surfaces, but are not limited to this and may be, for example, curved surfaces or flat surfaces.
  • the first terminal portion 22 protrudes from the fifth resin surface 55, and multiple second terminal portions 32 and third terminal portions 42 protrude from the sixth resin surface 56.
  • the first edge 211 of the island portion 21 has a first step 211a.
  • the first edge 211 is located on the x1 side of the first direction x of the island portion 21 and extends in the second direction y.
  • the first step 211a is formed on the y1 side of the second direction y from the semiconductor element 1 in the second direction y, and is covered with the sealing resin 5.
  • the first step 211a is recessed on the x2 side of the first direction x from the y1 side of the second direction y more than the y2 side of the second direction y.
  • the first step 211a can receive the thermal contraction of the sealing resin 5 (represented by the arrow N1 in FIG. 12). Therefore, the stress acting near the periphery of the semiconductor element 1 (near the corners on the x1 side of the first direction x and the y1 side of the second direction y of the semiconductor element 1) can be reduced.
  • the second edge 212 of the island portion 21 has a second step portion 212a.
  • the second step portion 212a is located on the x2 side of the first direction x of the island portion 21 and extends in the second direction y.
  • the second step portion 212a is formed on the y1 side of the second direction y from the semiconductor element 1 in the second direction y, and is covered with the sealing resin 5.
  • the second step portion 212a is recessed on the x1 side of the first direction x from the y1 side of the second direction y more than the y2 side of the second direction y. With this configuration, the second step portion 212a can receive the thermal contraction of the sealing resin 5 (represented by the arrow N2 in FIG. 12). Therefore, the stress acting near the periphery of the semiconductor element 1 (near the corners on the x2 side of the first direction x and the y1 side of the second direction y of the semiconductor element 1) can be reduced.
  • the island portion 21 includes a main portion 21A, a first thin portion 21B, and a second thin portion 21C.
  • the main portion 21A has a portion of the first main surface 201 and a portion of the second main surface 202.
  • the first thin portion 21B is connected to the x1 side of the main portion 21A in the first direction x, and has a portion of the first main surface 201 and a first intermediate surface 203.
  • the first intermediate surface 203 faces the z2 side of the thickness direction z, and is located between the first main surface 201 and the second main surface 202 in the thickness direction z.
  • the second thin portion 21C is connected to the x2 side of the first direction x with respect to the main portion 21A, and has a portion of the first main surface 201 and a second intermediate surface 204.
  • the second intermediate surface 204 faces the z2 side of the thickness direction z, and is located between the first main surface 201 and the second main surface 202 in the thickness direction z.
  • the semiconductor element 1 overlaps the main portion 21A, the first thin portion 21B, and the second thin portion 21C when viewed in the thickness direction z. With this configuration, it is possible to increase the size of the semiconductor element 1 mounted on the island portion 21 while reducing the stress acting on the periphery of the semiconductor element 1 as described above.
  • FIGS. 13 to 21 show other embodiments of the present disclosure.
  • elements that are the same as or similar to those in the above embodiment are given the same reference numerals as in the above embodiment, and duplicated explanations will be omitted.
  • the configurations of the various parts in each embodiment can be combined with each other as appropriate to the extent that no technical contradictions arise.
  • FIG. 13 to 15 show a semiconductor device according to a second embodiment of the present disclosure.
  • Fig. 13 is a plan view of a main part of the semiconductor device A2 according to this embodiment, seen through the sealing resin 5.
  • Fig. 14 is a bottom view of a main part of the semiconductor device A2, seen through the sealing resin 5.
  • Fig. 15 is a cross-sectional view taken along line XV-XV in Fig. 13. Note that in Figs. 13 and 14, the see-through sealing resin 5 is shown by an imaginary line (two-dot chain line).
  • the semiconductor device A2 differs from the above embodiment in the formation areas of the main portion 21A, the first thin portion 21B, and the second thin portion 21C in the island portion 21. As shown in FIG. 14, in the semiconductor device A2, the formation area of the main portion 21A is larger than that of the semiconductor device A1 of the above embodiment.
  • the first step portion 211a and the second step portion 212a are formed in the main portion 21A.
  • the first step 211a of the island portion 21 is formed on the y1 side of the semiconductor element 1 in the second direction y, and is covered with the sealing resin 5.
  • the first step 211a is recessed on the x2 side of the first direction x on the y1 side of the second direction y more than on the y2 side of the second direction y.
  • the first step 211a can receive the thermal contraction of the sealing resin 5. This makes it possible to reduce the stress acting near the periphery of the semiconductor element 1 (near the corners on the x1 side of the first direction x and the y1 side of the second direction y of the semiconductor element 1).
  • the second step portion 212a of the island portion 21 is formed on the y1 side of the semiconductor element 1 in the second direction y, and is covered with the sealing resin 5.
  • the second step portion 212a is recessed more toward the x1 side of the first direction x on the y1 side of the second direction y than on the y2 side of the second direction y. With this configuration, the thermal contraction of the sealing resin 5 can be absorbed by the second step portion 212a. This makes it possible to reduce the stress acting near the periphery of the semiconductor element 1 (near the corners on the x2 side of the first direction x and the y1 side of the second direction y of the semiconductor element 1).
  • the first step portion 211a and the second step portion 212a are formed in the main portion 21A.
  • This configuration allows a larger area to withstand the thermal contraction of the sealing resin 5. This is preferable in terms of reducing the stress acting near the periphery of the semiconductor element 1.
  • the semiconductor element 1 overlaps the main portion 21A, the first thin portion 21B, and the second thin portion 21C when viewed in the thickness direction z. This configuration makes it possible to increase the size of the semiconductor element 1 mounted on the island portion 21 while reducing the stress acting near the periphery of the semiconductor element 1.
  • FIG. 16 and 17 show a semiconductor device according to a third embodiment of the present disclosure.
  • Fig. 16 is a plan view of a main part of a semiconductor device A3 according to this embodiment, seen through the sealing resin 5.
  • Fig. 17 is a bottom view of a main part of the semiconductor device A3, seen through the sealing resin 5.
  • the see-through sealing resin 5 is shown by an imaginary line (two-dot chain line).
  • the configuration of the first edge portion 211 and the second edge portion 212 of the semiconductor device A3 differs from that of the above embodiment.
  • the first edge portion 211 has a first recess 211b.
  • the first recess 211b is formed on the y1 side of the semiconductor element 1 in the second direction y.
  • the first recess 211b is recessed on the x2 side of the first direction x, and includes a first step portion 211a.
  • the second edge portion 212 has a second recess 212b.
  • the second recess 212b is formed on the y1 side of the semiconductor element 1 in the second direction y.
  • the second recess 212b is recessed on the x1 side in the first direction x, and includes a second step portion 212a.
  • the first step 211a of the island portion 21 is formed on the y1 side of the semiconductor element 1 in the second direction y, and is covered with the sealing resin 5.
  • the first step 211a is recessed on the x2 side of the first direction x on the y1 side of the second direction y more than on the y2 side of the second direction y.
  • the first step 211a can receive the thermal contraction of the sealing resin 5. This makes it possible to reduce the stress acting near the periphery of the semiconductor element 1 (near the corners on the x1 side of the first direction x and the y1 side of the second direction y of the semiconductor element 1).
  • the second step portion 212a of the island portion 21 is formed on the y1 side of the semiconductor element 1 in the second direction y, and is covered with the sealing resin 5.
  • the second step portion 212a is recessed more toward the x1 side of the first direction x on the y1 side of the second direction y than on the y2 side of the second direction y. With this configuration, the thermal contraction of the sealing resin 5 can be absorbed by the second step portion 212a. This makes it possible to reduce the stress acting near the periphery of the semiconductor element 1 (near the corners on the x2 side of the first direction x and the y1 side of the second direction y of the semiconductor element 1).
  • the semiconductor element 1 overlaps the main portion 21A, the first thin portion 21B, and the second thin portion 21C when viewed in the thickness direction z. This configuration makes it possible to increase the size of the semiconductor element 1 mounted on the island portion 21 while reducing the stress acting near the periphery of the semiconductor element 1.
  • FIG. 18 is a plan view of a main part of a semiconductor device A4 according to this embodiment, seen through the sealing resin 5.
  • Fig. 19 is a bottom view of a main part of the semiconductor device A4, seen through the sealing resin 5.
  • the see-through sealing resin 5 is shown by an imaginary line (two-dot chain line).
  • the semiconductor device A4 differs from the above embodiment in the configuration of the first step portion 211a and the second step portion 212a.
  • the first step portion 211a is perpendicular or approximately perpendicular to the second direction y when viewed in the thickness direction z.
  • the first recess portion 211b is perpendicular or approximately perpendicular to the second direction y when viewed in the thickness direction z.
  • the first step 211a of the island portion 21 is formed on the y1 side of the semiconductor element 1 in the second direction y, and is covered with the sealing resin 5.
  • the first step 211a is recessed on the x2 side of the first direction x on the y1 side of the second direction y more than on the y2 side of the second direction y.
  • the first step 211a can receive the thermal contraction of the sealing resin 5. This makes it possible to reduce the stress acting near the periphery of the semiconductor element 1 (near the corners on the x1 side of the first direction x and the y1 side of the second direction y of the semiconductor element 1).
  • the second step portion 212a of the island portion 21 is formed on the y1 side of the semiconductor element 1 in the second direction y, and is covered with the sealing resin 5.
  • the second step portion 212a is recessed more toward the x1 side of the first direction x on the y1 side of the second direction y than on the y2 side of the second direction y. With this configuration, the thermal contraction of the sealing resin 5 can be absorbed by the second step portion 212a. This makes it possible to reduce the stress acting near the periphery of the semiconductor element 1 (near the corners on the x2 side of the first direction x and the y1 side of the second direction y of the semiconductor element 1).
  • the semiconductor element 1 overlaps the main portion 21A, the first thin portion 21B, and the second thin portion 21C when viewed in the thickness direction z. This configuration makes it possible to increase the size of the semiconductor element 1 mounted on the island portion 21 while reducing the stress acting near the periphery of the semiconductor element 1.
  • FIG. 20 is a plan view of a main part of the semiconductor device A5 according to this embodiment, seen through the sealing resin 5.
  • Fig. 21 is a bottom view of a main part of the semiconductor device A5, seen through the sealing resin 5.
  • the see-through sealing resin 5 is shown by an imaginary line (two-dot chain line).
  • the semiconductor device A5 differs from the above embodiment in the configuration of the first edge portion 211 and the second edge portion 212.
  • the first edge portion 211 further has a first step portion 211c
  • the second edge portion 212 further has a second step portion 212c.
  • the first edge portion 211 has two first step portions 211a, 211c.
  • the first step portion 211c is adjacent to the first step portion 211a on the y1 side of the second direction y.
  • the first step portion 211c is shaped so that the y1 side in the second direction y is recessed toward the x2 side in the first direction x more than the y2 side in the second direction y. In this way, in semiconductor device A5, the first edge portion 211 has the first step portions 211a, 211c that are recessed in two stages.
  • the second edge portion 212 has two second step portions 212a, 212c.
  • the second step portion 212c is adjacent to the second step portion 212a on the y1 side of the second direction y.
  • the second step portion 212c is shaped so that the y1 side in the second direction y is recessed toward the x2 side in the first direction x more than the y2 side in the second direction y. In this way, the second edge portion 212 has the second step portions 212a, 212c that are recessed in two stages.
  • the grooves 214 are not formed near the first step portions 211a, 211c and near the second step portions 212a, 212c.
  • the first step portions 211a, 211c of the island portion 21 are formed on the y1 side of the semiconductor element 1 in the second direction y, and are covered with the sealing resin 5.
  • Each of the first step portions 211a, 211c is recessed on the x2 side of the first direction x on the y1 side of the second direction y, more than on the y2 side of the second direction y.
  • the thermal contraction of the sealing resin 5 can be received by the two first step portions 211a, 211c. This makes it possible to reduce the stress acting near the periphery of the semiconductor element 1 (near the corners on the x1 side of the first direction x and the y1 side of the second direction y of the semiconductor element 1).
  • the second step portions 212a, 212c of the island portion 21 are formed on the y1 side of the semiconductor element 1 in the second direction y, and are covered with the sealing resin 5.
  • Each of the second step portions 212a, 212c is recessed on the y1 side of the second direction y toward the x1 side of the first direction x, rather than on the y2 side of the second direction y.
  • the thermal contraction of the sealing resin 5 can be received by the two second step portions 212a, 212c. This makes it possible to reduce the stress acting near the periphery of the semiconductor element 1 (near the corners on the x2 side of the first direction x and the y1 side of the second direction y of the semiconductor element 1).
  • the semiconductor element 1 overlaps the main portion 21A, the first thin portion 21B, and the second thin portion 21C when viewed in the thickness direction z. This configuration makes it possible to increase the size of the semiconductor element 1 mounted on the island portion 21 while reducing the stress acting near the periphery of the semiconductor element 1.
  • the semiconductor device according to the present disclosure is not limited to the above-mentioned embodiment.
  • the specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways.
  • Appendix 1 a first conductive member having an island portion; a semiconductor element disposed on one side of the island in a thickness direction; a sealing resin that covers the semiconductor element and at least a portion of the first conductive member, the island portion includes a first edge portion located on one side in a first direction perpendicular to the thickness direction and extending in a second direction perpendicular to the thickness direction and the first direction; the first edge portion is covered with the sealing resin and has a first step portion formed on one side in the second direction relative to the semiconductor element, The first step portion is recessed toward one side in the first direction more than toward the other side in the second direction.
  • the island portion has a first main surface facing one side in the thickness direction and a second main surface facing the other side in the thickness direction, 2.
  • the semiconductor device according to claim 1 wherein the semiconductor element has a first surface facing one side in the thickness direction, and a second surface facing the other side in the thickness direction and opposed to the first main surface.
  • Appendix 3 The island portion includes a main portion, 3.
  • the island portion includes a first thin-walled portion connected to one side of the main portion in the first direction, the first thin portion has a part of the first main surface and a first intermediate surface facing the other side in the thickness direction and positioned between the first main surface and the second main surface in the thickness direction, 4.
  • the first step portion is formed in the first thin portion.
  • the semiconductor device according to claim 3, wherein the first step portion is formed in the main portion.
  • Appendix 7. 7.
  • the first edge portion includes the first step portion and has a first recess that is recessed toward the other side in the first direction.
  • Appendix 9. the island portion is located on the other side in the first direction and includes a second edge portion extending in the second direction, the second edge portion is covered with the sealing resin and has a second step portion formed on one side in the second direction relative to the semiconductor element, 9.
  • the second step portion is recessed toward one side in the first direction more on one side in the second direction than on the other side in the second direction. Appendix 10.
  • the island portion is located on the other side in the first direction and includes a second edge portion extending in the second direction, the second edge portion is covered with the sealing resin and has a second step portion formed on one side in the second direction relative to the semiconductor element, the second step portion is recessed toward one side in the first direction more than the other side in the second direction, the island portion includes a second thin portion connected to the other side of the main portion in the first direction, the second thin portion has a part of the first main surface and a second intermediate surface facing the other side in the thickness direction and positioned between the first main surface and the second main surface in the thickness direction,
  • the second thin portion includes at least a portion of the second edge portion.
  • A1, A2, A3, A4, A5 semiconductor device 1: semiconductor element 101: element first surface 102: element second surface 11: first electrode 12: second electrode 13: third electrode 19: conductive bonding material 2: first conductive member 201: first main surface 202: second main surface 203: first intermediate surface 204: second intermediate surface 21: island portion 21A: main portion 21B: first thin portion 21C: second thin portion 211: first edge portion 211a, 211c: first step portion 211b: first recess 212: second edge portion 212a, 212c: second step portion 212b: second recess 213: third edge portion 214: recessed groove 22: first terminal portion 23: through hole 3: second conductive member 31: pad portion 32: Second terminal portion 39: Conductive bonding material 4: Third conductive member 41: Pad portion 42: Third terminal portion 49: Conductive bonding material 5: Sealing resin 51: First resin surface 52: Second resin surface 53: Third resin surface 54: Fourth resin surface 55: Fifth resin surface 56: Sixth resin surface

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