WO2024174403A1 - 半导体器件及其制造方法、电子设备 - Google Patents

半导体器件及其制造方法、电子设备 Download PDF

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Publication number
WO2024174403A1
WO2024174403A1 PCT/CN2023/096885 CN2023096885W WO2024174403A1 WO 2024174403 A1 WO2024174403 A1 WO 2024174403A1 CN 2023096885 W CN2023096885 W CN 2023096885W WO 2024174403 A1 WO2024174403 A1 WO 2024174403A1
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Prior art keywords
layer
substrate
electrode
patterned
semiconductor device
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French (fr)
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WO2024174403A9 (zh
Inventor
艾学正
王祥升
王桂磊
桂文华
赵超
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of device design and manufacturing of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device.
  • Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non-ROM) based on application.
  • RAM volatile memory
  • SRAM static random access memory
  • ROM non-volatile memory
  • the traditional known DRAM has multiple repeated "storage cells", each of which has a capacitor and a transistor.
  • the capacitor can store 1 bit of data. After charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively.
  • the transistor is a switch that controls the charging and discharging of the capacitor.
  • Embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the same, and an electronic device.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a plurality of memory cells stacked in a direction perpendicular to a substrate and a word line extending in a direction perpendicular to the substrate, wherein the memory cell includes a transistor and a capacitor, wherein the transistor includes a first electrode, a second electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate electrode and insulated from the gate electrode, and the capacitor includes a first plate and a second plate.
  • the method for manufacturing a semiconductor device includes:
  • the stacked structure is formed into a patterned stacked structure and a through hole through a single composition process;
  • the patterned stacked structure includes a patterned conductive layer and a patterned insulating layer that are alternately arranged in sequence;
  • the through hole penetrates the patterned stacked structure in a direction perpendicular to the substrate, and the side wall of the through hole exposes the patterned conductive layer and the patterned insulating layer; the through hole is configured to accommodate the word line.
  • the forming of the stacked structure into a patterned stacked structure and the forming of the through hole by a single patterning process comprises: performing a patterning process on the stacked structure through a mask pattern on a film layer to form the stacked structure into a patterned stacked structure and the forming of the through hole.
  • the mask pattern is a pattern having both a structure and a hole structure.
  • the film layer is a photoresist.
  • the film layer is a hard mask layer.
  • the method for manufacturing a semiconductor device also includes: forming a first sacrificial layer filling the through hole; forming a filling layer surrounding the side wall of the patterned stacked structure; removing part of the filling layer and part of the patterned insulating layer, exposing part of the patterned conductive layer, so that the exposed patterned conductive layer serves as the first electrode, and forming the second electrode in the area where the filling layer and the patterned insulating layer are removed; etching to remove the first sacrificial layer; etching the patterned conductive layer in a plane parallel to the substrate in a direction away from the through hole, the through hole causing the patterned conductive layer to form a first electrode and a second electrode separated from each other; depositing mutually insulated semiconductor films and gate electrode films in sequence on the side walls of the through hole to form the semiconductor layer, the gate electrode and the word line.
  • forming a first sacrificial layer that fills the through hole comprises:
  • first sacrificial layer thin film on the substrate, wherein the first sacrificial layer thin film covers a portion of the surface of the substrate, covers the side surfaces and the upper surface of the patterned stacked structure, and fills the through hole;
  • the first sacrificial layer film is subjected to a composition process to remove the first sacrificial layer film covering the surface of the substrate and the first sacrificial layer film covering the side and upper surface of the patterned stacked structure, and the first sacrificial layer film filling the through hole is retained to form the first sacrificial layer.
  • the manufacturing method further includes: grinding a surface of the filling layer so that a surface of the filling layer away from the substrate is flush with a surface of the patterned stacked structure away from the substrate.
  • a portion of the filling layer and a portion of the patterned insulating layer are removed to expose a portion of the patterned conductive layer, so that the exposed patterned conductive layer serves as a first electrode plate.
  • the manufacturing method further comprises:
  • a support layer is formed on the exposed end of the patterned conductive layer, wherein the support layer comprises a fixing groove, and the fixing groove fixes the exposed end of the patterned conductive layer.
  • the support layer comprises an insulating material.
  • the disclosed embodiment also provides a semiconductor device manufactured by the manufacturing method of the semiconductor device as described above, comprising: a plurality of memory cells and word lines stacked in a direction perpendicular to the substrate, wherein the word lines extend in a direction perpendicular to the substrate and penetrate the memory cells of different layers.
  • the memory cell comprises: a transistor and a capacitor, wherein the transistor comprises a first electrode, a second electrode, a gate electrode extending in a direction perpendicular to the substrate, a semiconductor layer surrounding the gate electrode and insulated from the gate electrode, wherein the semiconductor layer extends on the side wall of the gate electrode to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate; the capacitor comprises a first plate and a second plate.
  • the semiconductor device further includes a supporting layer, wherein the supporting layer is located on a side of the first electrode away from the gate electrode, the supporting layer includes a fixing groove, the opening of the fixing groove faces one end of the first electrode plate, and one end of the first electrode plate extends into the fixing groove.
  • the second electrode plate is located between the support layer and the word line, the second electrode plate surrounds the first electrode plate, and the second electrode plate extends on the side wall of the first electrode plate to form a ring extending in a direction parallel to the substrate.
  • An embodiment of the present disclosure further provides an electronic device, comprising the semiconductor device described in any of the above embodiments.
  • the embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and an electronic device.
  • a patterned stacked structure and a through hole K1 are simultaneously formed, which simplifies the process flow, is easy to implement, and improves production efficiency. It has the advantages of easy process implementation, low production cost, and high yield rate.
  • FIG. 1A is a cross-sectional view of a semiconductor device provided by an exemplary embodiment along a direction perpendicular to a substrate;
  • 1B is a cross-sectional view of a semiconductor device provided by an exemplary embodiment along a direction parallel to a substrate;
  • 1C is a partially enlarged schematic cross-sectional view of a semiconductor device provided by an exemplary embodiment along a direction perpendicular to a substrate;
  • 1D is another partially enlarged schematic cross-sectional view of a semiconductor device along a direction perpendicular to a substrate provided by an exemplary embodiment
  • FIG. 2 is a schematic diagram of a semiconductor device after a stacked structure is formed in a manufacturing process provided by an exemplary embodiment
  • 3A is a schematic diagram of a semiconductor device manufacturing process after a first mask is placed according to an exemplary embodiment
  • 3B is a schematic diagram 1 of a semiconductor device after a patterned conductive layer, a patterned insulating layer and a through hole are formed in a manufacturing process provided by an exemplary embodiment
  • 3C is a second schematic diagram of a semiconductor device after a patterned conductive layer, a patterned insulating layer and a through hole are formed in a manufacturing process provided by an exemplary embodiment
  • 3D is a third schematic diagram of a semiconductor device after a patterned conductive layer, a patterned insulating layer and a through hole are formed in a manufacturing process provided by an exemplary embodiment
  • FIG. 4A is a schematic diagram of a semiconductor device after a first sacrificial layer film is formed in a manufacturing process provided by an exemplary embodiment
  • 4B is a schematic diagram of a semiconductor device after a first sacrificial layer is formed in a manufacturing process provided by an exemplary embodiment
  • FIG4C is a schematic diagram of a semiconductor device after a filling layer is formed in a manufacturing process provided by an exemplary embodiment
  • 5A is a schematic diagram of a semiconductor device manufacturing process after a second mask is placed according to an exemplary embodiment
  • FIG5B is a schematic diagram of a semiconductor device after a groove is formed in a manufacturing process provided by an exemplary embodiment
  • FIG5C is a schematic diagram 1 of a semiconductor device manufacturing process after a support layer is formed according to an exemplary embodiment
  • FIG5D is a second schematic diagram of a semiconductor device after a support layer is formed in a manufacturing process provided by an exemplary embodiment
  • FIG6A is a schematic diagram 1 of a semiconductor device after a first hollow portion and a second hollow portion are formed during manufacturing of the semiconductor device according to an exemplary embodiment
  • 6B is a second schematic diagram of a semiconductor device after a first hollow portion and a second hollow portion are formed during manufacturing of the semiconductor device according to an exemplary embodiment
  • FIG. 7A is a schematic diagram 1 of a semiconductor device after a second electrode plate is formed in a manufacturing process provided by an exemplary embodiment
  • FIG. 7B is a second schematic diagram of a semiconductor device after a second electrode plate is formed in a manufacturing process provided by an exemplary embodiment
  • FIG8 is a schematic diagram of a semiconductor device after removing a first sacrificial layer during manufacturing of the semiconductor device according to an exemplary embodiment
  • 9A is a schematic diagram 1 after forming a first electrode and a second electrode in a manufacturing process of a semiconductor device provided by an exemplary embodiment
  • 9B is a second schematic diagram after forming a first electrode and a second electrode in a manufacturing process of a semiconductor device provided by an exemplary embodiment
  • FIG. 10A is a schematic diagram of a semiconductor device after a semiconductor layer and a gate insulating layer are formed in a manufacturing process provided by an exemplary embodiment
  • 10B is a schematic diagram of a semiconductor device after a second sacrificial layer is formed in a manufacturing process provided by an exemplary embodiment
  • FIG. 11A is a schematic diagram of a semiconductor device after etching a second sacrificial layer in a manufacturing process provided by an exemplary embodiment
  • FIG. 11B is a schematic diagram of a semiconductor device after etching back the second sacrificial layer in a manufacturing process provided by an exemplary embodiment.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a physical connection or a signal connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed e.g., it can be a fixed connection, a detachable connection, or an integral connection; it can be a physical connection or a signal connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor may include a gate (also referred to as a gate electrode), a channel, and a first electrode (hereinafter referred to as the first electrode 51) and a second electrode (hereinafter referred to as the second electrode 52), wherein the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the source electrode may also be referred to as a drain electrode terminal, a drain region, or a drain electrode, and the drain electrode may also be referred to as a source electrode terminal, a source region, or a source electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in the present disclosure, the “source electrode” and the “drain electrode” may be interchanged.
  • connection or “electrical connection” includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit electrical signals between connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means approximately parallel or nearly parallel, for example, the angle formed by two straight lines is -10° or less.
  • vertical means approximately vertical, for example, the angle formed by two straight lines is 80° or more and 10° or less, and therefore, the angle is 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced with “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • the "A and B are arranged in the same layer" mentioned in the present disclosure includes film layers formed of the same material or different materials located on the same film layer.
  • a and B are formed by forming the same film layer with the same material and then undergoing the same patterning process or different patterning processes.
  • a and B arranged in the same layer may be located on the same horizontal plane but not necessarily on the same film layer, or located in different regions of the same film layer but not necessarily on the same horizontal plane.
  • a and B are an integrated structure may include a film layer patterned to form a connection as an integrated structure.
  • a and B are formed into a film layer using the same material and are formed into a structure having a connection relationship through the same patterning process.
  • the parasitic MOS tube (parasitic MOS for short) can be reduced or eliminated by removing the semiconductor layer between the layers through etching.
  • FIG1A is a schematic cross-sectional view of a semiconductor device provided by an exemplary embodiment along a direction perpendicular to the substrate;
  • FIG1C and FIG1D may be partial enlarged views of a schematic cross-sectional view of a semiconductor device provided by an exemplary embodiment along a direction perpendicular to the substrate.
  • FIG1C and FIG1D may be enlarged views of point a in FIG1A; the direction perpendicular to the substrate may be the third direction D3 in FIG1A.
  • the semiconductor device provided by this embodiment may include: multiple layers of memory cells stacked along a direction perpendicular to the substrate 1, and word lines 40, wherein the word lines 40 extend along a direction perpendicular to the substrate 1 and penetrate the memory cells of different layers.
  • the term "substrate” means and includes a base material or structure on which a material such as a vertical field effect transistor is formed.
  • the substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon.
  • the substrate can be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.
  • the memory cell may include: a transistor, the transistor including a first electrode 51, a second electrode 52, a gate electrode 26 extending in a direction perpendicular to the substrate, a semiconductor layer 23 surrounding the gate electrode 26 and insulated from the gate electrode 26, the semiconductor layer 23 extending on the sidewall of the gate electrode 26 to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate.
  • the first electrode 51 and the second electrode 52 are located on opposite sides of the gate electrode 26 in a first direction D1, and at least part of the semiconductor layer 23 is located between the first electrode 51 and the gate electrode 26, and between the second electrode 52 and the gate electrode 26.
  • the channel between the first electrode 51 and the second electrode 52 is a horizontal channel; the semiconductor layers 23 of the transistors of at least part of the adjacent layers of the memory cell are spaced in a direction perpendicular to the substrate, and the gate electrode 26 is connected to the word line 40.
  • the first direction D1 is parallel to the plane where the substrate is located.
  • the word line is a lead shared by multiple transistors stacked vertically, and the lead is connected to the gates of multiple transistors.
  • the word line 40 can be a line extending longitudinally and shared by three transistors.
  • the gate refers to the gate electrode of a transistor.
  • the gate 26 can be a part of the word line 40.
  • the word line 40 extends longitudinally (for example, the third direction D3) as a whole, but the cross-sectional sizes at different positions can be the same or different.
  • the area on the word line 40 corresponding to the effective channel of each transistor is the effective gate, and the cross-sectional area of the effective gate can be larger than other areas on the word line 40 (such as shown in Figure 1D) or smaller than other areas, which is not limited in this application.
  • the other areas may be areas that do not correspond to the effective channel of the transistor, for example, areas between two vertically stacked transistors.
  • the semiconductor device provided in this embodiment has a semiconductor layer of a transistor in an adjacent layer in a direction perpendicular to the substrate 1.
  • the spacing setting can reduce or eliminate at least part of the parasitic MOS between layers and improve the stability of the device.
  • the spacing setting can be understood as: the adjacent semiconductor layers of the transistors in adjacent layers are separated, for example, the semiconductor layer formed by the inner wall of the hole is hollowed out in the separation area, or is modified, so that the separation area cannot play the role of a semiconductor.
  • a horizontal channel is a channel in which the carrier transport direction is generally in a plane parallel to the substrate.
  • the semiconductor layers 23 of the transistors of the memory cells of different layers are spaced apart in a direction perpendicular to the substrate.
  • the semiconductor layers 23 of the transistors of the memory cells of all adjacent layers are spaced apart in a direction perpendicular to the substrate, thereby eliminating parasitic MOS between all adjacent layers and improving device stability.
  • the semiconductor layer 23 may be a fully surrounding type, and fully surrounds the side wall of the gate electrode 26, that is, the cross section of the semiconductor layer 23 along the direction parallel to the substrate is a closed loop.
  • the semiconductor layer 23 is annular, and the annular shape is adapted to the outer contour of the cross section of the gate electrode 26.
  • the cross section of the gate electrode 26 is, for example, a square structure.
  • the gate electrode 26 includes a middle portion 261 and a peripheral portion 262 located outside the middle portion 261, the middle portion 261 only extends in a direction perpendicular to the substrate 1, and the middle portion 261 can completely overlap with the orthographic projection of the word line 40 on the substrate 1.
  • the middle portion 261 can be integrally formed with the word line 40, and made of the same material and by the same manufacturing process.
  • the peripheral portion 262 surrounds the middle portion 261, and the peripheral portion 262 can completely surround the side wall of the middle portion 261, at least part of the peripheral portion 262 contacts the side wall of the middle portion 261, the peripheral portion 262 does not overlap with the orthographic projection of the word line 40 on the substrate 1, and overlaps with the orthographic projection of the semiconductor layer 23 on the substrate 1.
  • the transistor may further include a gate insulating layer 24 surrounding a sidewall of the gate electrode 26 .
  • the gate insulating layer 24 is located between the gate electrode 26 and the semiconductor layer 23 to insulate the gate electrode 26 from the semiconductor layer 23 .
  • transistors in different layers may share a ring-shaped gate insulating layer 24 extending in a direction perpendicular to the substrate.
  • the gate insulating layers 24 of at least some of the transistors in adjacent layers are spaced apart in a direction perpendicular to the substrate.
  • the gate insulating layers 24 of transistors in different layers are spaced apart from each other in a direction perpendicular to the substrate.
  • the first electrode 51 and the second electrode 52 of the same transistor may be located in the same conductive film layer.
  • the first electrode 51 and the second electrode 52 may be formed by patterning a conductive film layer, and the conductive film layer is approximately parallel to the upper surface of the substrate.
  • the first electrode 51 and the second electrode 52 may be arranged in the same layer. That is, the first electrode 51 and the second electrode 52 may be formed simultaneously by the same patterning process, but the embodiments of the present disclosure are not limited thereto, and the first electrode 51 and the second electrode 52 may be manufactured separately by different patterning processes.
  • the first electrode 51 or the second electrode 52 of different transistors may be located in different conductive film layers.
  • stacked transistors in different layers may share the word line 40 extending in a direction perpendicular to the substrate.
  • the semiconductor layers 23 corresponding to transistors of different layers may be located on the sidewalls of the word line 40 and respectively located in different regions extending in a direction perpendicular to the substrate.
  • an insulating layer is exposed between the semiconductor layers 23 arranged at intervals.
  • the gate insulating layer 24 is located between the gate electrode 26 and the semiconductor layer 23.
  • the solution provided in this embodiment isolates the first electrode 51 and the gate electrode 26 through the gate insulating layer 24 to avoid over-etching that causes the first electrode 51 to be exposed and causes a short circuit between the first electrode 51 and the gate electrode 26.
  • FIG1B is a cross-sectional view of a semiconductor device provided by an exemplary embodiment along a direction parallel to the substrate.
  • the memory cells in the same layer form an array distributed along a first direction D1 and a second direction D2, respectively, and each layer of the memory cells further includes: a bit line 30, and the bit line 30 is connected to the second electrode 52 of the transistor in the same layer and the same column.
  • FIG1B shows that each layer includes three rows and two columns of memory cells, but the embodiments of the present disclosure are not limited thereto, and each layer may include memory cells of other numbers of rows and columns, for example, may include only one memory cell.
  • the first direction D1 may be parallel to the substrate
  • the second direction D2 may be parallel to the substrate
  • the first direction D1 and the second direction D2 intersect.
  • the first direction D1 and the second direction D2 may be perpendicular.
  • the second electrodes 52 of the transistors of the memory cells in two adjacent columns are connected to the same bit line 30.
  • the second electrodes 52 of the transistors in two adjacent columns of the same layer and the bit line 30 may be an integrated structure.
  • the second electrode 52 of the transistor may be a portion of the bit line 30 to which the second electrode 52 is connected.
  • bit line 30 may extend along the second direction D2.
  • the first electrode 51 may extend along the first direction D1.
  • the semiconductor device may further include a data storage element.
  • the data storage element may be a capacitor, that is, forming a 1T1C storage structure.
  • the disclosed embodiment is not limited thereto, and may be combined with other transistors to form a 2T0C storage structure, and so on.
  • the capacitor may include a first plate 41 and a second plate 42, wherein the first plate 41 is connected to the first electrode 51.
  • the second plate 42 surrounds the first plate 41 and is insulated from the first plate 41, and the second plate 42 extends on the side wall of the first plate 41 to form a ring extending in a direction parallel to the substrate.
  • the semiconductor device may further include a support layer 43, the support layer 43 is located on a side of the first electrode 41 away from the gate electrode 26, and the second electrode 42 is located between the support layer 43 and the word line 40.
  • the support layer 43 includes a fixing groove 44, the opening of the fixing groove 44 faces one end of the first electrode 41, and one end of the first electrode 41 away from the bit line 30 extends into the fixing groove 44, so that the support layer 43 fixes the first electrode 41 to ensure the mechanical stability of the first electrode 41.
  • the first electrode 41 may be exposed first, and then the support layer 43 may be formed, and one end of the first electrode 41 may be fixed by the support layer 43 to ensure the mechanical stability of the first electrode 41, and finally, the second electrode 42 surrounding the first electrode 41 may be formed.
  • the first electrode plate 41 and the first electrode 51 may be an integrated structure.
  • the second plates 42 of the capacitors in the same column of different layers can be connected as an integrated structure. As shown in FIG1B , the second plates 42 of the capacitors in the first column of different layers are connected as an integrated structure. The second plates 42 of the capacitors in the second column of different layers are connected as an integrated structure, that is, the capacitors in the same column of different layers share the same plate as the second plate 42.
  • the capacitor may further include a third insulating layer 13 disposed between the first electrode plate 41 and the second electrode plate 42.
  • the third insulating layer 13 serves as a medium between the first electrode plate 41 and the second electrode plate 42.
  • the semiconductor device may further include a detection pin 61, the detection pin 61 being disposed at one side of the memory cell, the detection pin 61 being electrically connected to the bit line 30 of each layer of the memory cell, the detection unit may be electrically connected to the detection pin 61, and the detection pin 61 may be electrically connected to the bit line 30 of each layer of the memory cell. 61 inputs a detection signal to the bit line 30 of the memory cell to detect the memory cell.
  • the projections of the first electrodes of transistors adjacent to each other in a direction perpendicular to the substrate overlap in the direction perpendicular to the substrate
  • the projections of the second electrodes overlap in the direction perpendicular to the substrate
  • the projections of the gate electrodes overlap in the direction perpendicular to the substrate.
  • a multi-layer stacked first electrode, a second electrode, and a through hole K1 can be formed by relatively stacking a conductive layer and an insulating layer and then by a mask, so that the process is simple.
  • the structure of the semiconductor device can be made more compact.
  • the semiconductor device of the embodiment of the present application can form a 1T1C storage structure with a capacitor, or form a 2T0C storage structure with other transistors, and so on.
  • the technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment.
  • the "patterning process” mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies.
  • the "photolithography process” mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not limited here.
  • thin film refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film” does not require a patterning process or a photolithography process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” still requires a patterning process or a photolithography process during the entire manufacturing process, it is called a “thin film” before the patterning process and a "layer” after the patterning process. The "layer” after the patterning process or the photolithography process contains at least one "pattern".
  • each layer includes a plurality of storage units, but the embodiments of the present disclosure are not limited thereto, and each layer may include one storage unit.
  • a process for manufacturing a semiconductor device may include:
  • Step 101 alternately depositing a first insulating film 10 and a first conductive film 11 on a substrate 1 in sequence to form a stacked structure, as shown in FIG. 2 .
  • the first insulating film 10 and the first conductive film 11 may be deposited by a chemical vapor deposition (CVD) method.
  • CVD chemical vapor deposition
  • the term "substrate” means and includes a base material or structure on which a material such as a vertical field effect transistor is formed.
  • the substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon.
  • the substrate can be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.
  • the substrate can be a semiconductor substrate, such as a silicon substrate.
  • the first insulating film 10 may be a dielectric layer with a relatively small dielectric constant, such as silicon dioxide (SiO 2 ).
  • the first conductive film 11 may include, but is not limited to, a multi-layer structure of titanium nitride (TiN)/tungsten (W).
  • the stacked structure shown in FIG. 2 includes four layers of first insulating films 10 and three layers of first conductive films 11 , which is only an example. In other embodiments, the stacked structure may include more or fewer layers of first insulating films 10 and first conductive films 11 that are alternately arranged.
  • Step 102 on the basis of the substrate 1 formed with the aforementioned pattern, firstly form a first mask 2 (which can be understood as a mask pattern) on the surface of the stacked structure away from the substrate 1, as shown in FIG3A.
  • the mask pattern can be a pattern on a photoresist (PR) glue or a hard mask layer.
  • the hard mask layer can be made of SiO 2 , Si 3 N 4 , TiN, amorphous carbon (ACHM), etc., and is mainly used in multiple exposure processes, etc.
  • the first mask 2 (which can be understood as a mask pattern) can be formed on the surface of the stacked structure away from the substrate 1.
  • a photoresist is coated on the patterned substrate, and a mask pattern is formed by removing part of the photoresist.
  • the mask pattern may be a pattern having both an architecture and a hole structure.
  • the architecture of the mask pattern may be roughly in the shape of a fishbone.
  • the architecture of the mask pattern may include a " ⁇ "-shaped structure and a rectangular block connected to one end of the " ⁇ "-shaped structure.
  • the " ⁇ "-shaped structure may include six branches extending along a first direction D1 and a main branch extending along a second direction Y, the six branches may be symmetrically arranged on both sides of the main branch in the first direction D1, and the rectangular block may be connected to one end of the main branch.
  • the six branches may all be strips extending along the first direction D1, and the trunk may be a strip extending along the second direction Y.
  • the orthographic projection shape of the branches and the trunk on the substrate may be roughly rectangular, and the length of the rectangular block along the first direction D1 may be greater than the length of the trunk along the first direction D1.
  • the hole structure of the mask pattern may include six holes arranged in an array of three rows and two columns, two holes arranged along the first direction D1 form a row, and three holes arranged along the second direction D2 form a column.
  • the six holes are respectively located on the six branches of the " ⁇ "-shaped structure.
  • the orthographic projection shape of the hole may be a rectangle, such as a square. This embodiment is not limited to this. In other examples, the orthographic projection shape of the hole may be other shapes, such as a circle.
  • a mask pattern can be used to etch the architecture of the semiconductor device and the through holes for setting the word lines at one time, which can avoid the situation where the alignment deviation caused by etching the through holes separately affects the size, structure, electrical characteristics of the semiconductor device and the miniaturization effect of the entire structure, thereby ensuring the structural size stability of the semiconductor device, facilitating the miniaturization effect, and improving the yield of the semiconductor device; and by etching the architecture area of the semiconductor device and the through holes for setting the word lines at one time, the etching process can be reduced, the process can be simplified, and the cost can be reduced.
  • the stacked structure is subjected to a patterning process through the first mask 2, so that the stacked structure forms a patterned stacked structure, so that the plurality of first conductive films 11 form a patterned conductive layer 12, so that the plurality of first insulating films 10 form a patterned insulating layer 14, and a plurality of through holes K1 are formed.
  • the patterned stacked structure comprises patterned conductive layers 12 and patterned insulating layers 14 that are alternately arranged in sequence.
  • the through hole K1 extends in a direction perpendicular to the substrate and penetrates the patterned stacked structure in a direction perpendicular to the substrate, as shown in FIG. 3B and FIG. 3C.
  • the orthographic projections of the patterned conductive layer 12 and the patterned insulating layer 14 on the substrate 1 can completely overlap, that is, the size and shape of the patterned conductive layer 12 are the same as the size and shape of the patterned insulating layer 14.
  • FIG3C is a schematic diagram 2 of a semiconductor device manufacturing process provided by an exemplary embodiment after a patterned conductive layer, a patterned insulating layer and a through hole are formed.
  • FIG3C is a cross-sectional view parallel to the substrate direction.
  • the patterned conductive layer 12 may include a bit line 30, a plurality of first sub-portions 21 and a plurality of second sub-portions 22, the bit line 30 connecting the first sub-portion 21 and the second sub-portion 22, the first sub-portion 21 may extend along the first direction D1, the second sub-portion 22 may extend along the first direction D1, and the bit line 30 may extend along the second direction D2.
  • the plurality of first sub-portions 21 are arranged at intervals along the second direction D2, and one end of the plurality of first sub-portions 21 is connected to the bit line 30.
  • the plurality of second sub-portions 22 are arranged at intervals along the second direction D2, and one end of the plurality of second sub-portions 22 is connected to the bit line 30.
  • the first sub-portion 21 subsequently forms a first electrode 51 and a second electrode 52 of a transistor
  • the second sub-portion 22 subsequently forms a first electrode 51 and a second electrode 52 of another adjacent transistor.
  • FIG3D is a schematic diagram 3 after forming a patterned conductive layer, a patterned insulating layer and a through hole in the manufacturing process of a semiconductor device provided by an exemplary embodiment.
  • FIG3D is a cross-sectional view perpendicular to the direction of the substrate, and FIG3D may be a cross-sectional view in the aa' direction in FIG3C.
  • a through hole K1 passes through a plurality of patterned conductive layers 12 and a plurality of patterned insulating layers 14, and the side walls of the through hole K1 expose each patterned conductive layer 12 and each patterned insulating layer 14.
  • the first sub-portion 21 and the second sub-portion 22 are both provided with the through hole K1.
  • the through hole K1 may extend in a direction perpendicular to the substrate.
  • the bottom wall of the through hole K1 may expose or not expose the substrate.
  • the stacked structure may be dry-etched by using the first mask 2.
  • the etching is performed using a high aspect ratio etching (HAR ET) method.
  • HAR ET high aspect ratio etching
  • the aspect ratio is >6:1.
  • the orthographic projection of the through hole K1 on a plane parallel to the substrate may be a square.
  • this embodiment is not limited to this.
  • the orthographic projection of the through hole K1 on a plane parallel to the substrate is located within the orthographic projection of the patterned conductive layer 12.
  • the orthographic projection of the through hole K1 passing through the first sub-portion 21 is located within the orthographic projection of the first sub-portion 21
  • the orthographic projection of the through hole K1 passing through the second sub-portion 22 is located within the orthographic projection of the second sub-portion 22.
  • Step 103 based on the substrate 1 formed with the aforementioned pattern, a first sacrificial layer film 15 is deposited on the substrate 1, the first sacrificial layer film 15 covers part of the surface of the substrate 1, covers the side and upper surface of the patterned stacked structure, and fills the through hole K1.
  • the first sacrificial layer film 15 fills the through hole K1 so that the surface of the stacked structure away from the substrate 1 is flush, as shown in FIG. 4A.
  • Step 104 based on the substrate 1 formed with the aforementioned pattern, the first sacrificial layer film 15 is subjected to a composition process, the first sacrificial layer film 15 covering the surface of the substrate 1 and the first sacrificial layer film 15 covering the side and upper surface of the patterned stacked structure are etched away, and the first sacrificial layer film 15 filling the through hole K1 is retained to form a first sacrificial layer 16, and the first sacrificial layer 16 fills the through hole K1, as shown in FIG. 4B .
  • Step 105 based on the substrate 1 formed with the aforementioned pattern, a filling layer 17 is formed on the substrate 1 , wherein the filling layer 17 is arranged in the same layer as the patterned stacked structure, surrounds the side wall of the patterned stacked structure, and contacts the side wall of the patterned stacked structure.
  • the surface of the filling layer 17 is ground to make the surface of the filling layer 17 away from the substrate side flush with the surface of the patterned stacking structure away from the substrate side, and the filling layer 17 and the patterned stacking structure form a regularly shaped film layer pattern.
  • the regularly shaped film layer pattern can be a rectangular parallelepiped, as shown in FIG. 4C .
  • the filling layer 17 may be made of insulating material, such as oxide.
  • Step 106 on the basis of the substrate 1 with the aforementioned pattern formed thereon, a second mask 3 is placed on the surface of the film layer pattern which is away from the substrate 1 , as shown in FIG. 5A .
  • the film layer pattern is patterned by a second mask plate 3 to remove part of the filling layer 17 and part of the patterned insulating layer 14 on opposite sides of the film layer pattern to form a groove 18, wherein the groove 18 exposes part of the surface of the substrate 1, exposes one end of the first sub-portion 21 away from the bit line 30 (including the end face and part of the side face of the first sub-portion 21), and exposes one end of the second sub-portion 22 away from the bit line 30 (including the end face and part of the side face of the second sub-portion 22), as shown in FIG5B.
  • a second insulating film and a supporting layer material are sequentially deposited in the groove 18, so that the second insulating film forms a second insulating layer 19, and the supporting layer material forms a supporting layer 43.
  • the second insulating layer 19 covers the exposed area of the first sub-portion 21 and the exposed area of the second sub-portion 22, that is, the second insulating layer 19 covers the end surface and part of the side wall of the first sub-portion 21 away from the bit line 30, and the end surface and part of the side wall of the second sub-portion 22 away from the bit line 30, and the second insulating layer 19 is arranged between the supporting layer 43 and the exposed area of the first sub-portion 21, and between the exposed area of the second sub-portion 22.
  • the support layer 43 is formed at one end of the exposed first sub-portion 21 away from the bit line 30, and at one end of the exposed second sub-portion 22 away from the bit line 30.
  • the support layer 43 includes a fixing groove, and the fixing groove fixes the end of the exposed first sub-portion 21 away from the bit line 30, and the end of the exposed second sub-portion 22 away from the bit line 30.
  • the support layer 43 is used to support the first sub-portion 21 and the second sub-portion 22, and ensure the mechanical stability of the first sub-portion 21 and the second sub-portion 22 during the process of forming the second electrode plate 42, as shown in Figures 5C and 5D, FIG. 5D is a cross-sectional view parallel to the substrate direction.
  • the support layer 43 may be made of insulating material, such as oxide.
  • the support layer 43 may be made of insulating material to avoid generating capacitance with the second electrode plate 42 formed subsequently, thereby affecting the device performance.
  • Step 107 based on the substrate 1 formed with the aforementioned pattern, remove the filling layer 17 and the patterned insulating layer 14 located in the capacitor area.
  • Part of the side surface of the first sub-section 21 is exposed, and part of the side surface of the second sub-section 22 is exposed.
  • a first hollow portion 71 is formed between the exposed side surfaces of the adjacent first sub-sections 21 in the same layer, and between the exposed side surfaces of the first sub-sections 21 in the adjacent layers;
  • a second hollow portion 72 is formed between the exposed side surfaces of the adjacent second sub-sections 22 in the same layer, and between the exposed side surfaces of the second sub-sections 22 in the adjacent layers.
  • the capacitor area is the area of the capacitor formed by the first electrode 41 and the second electrode 42, and the capacitor area is located between the support layer 43 and the bit line 30.
  • first hollow portion 71 is located between the support layer 43 and the through hole K1, and the first hollow portion 71 surrounds the exposed side of the first sub-section 21;
  • second hollow portion 72 is located between the support layer 43 and the through hole K1, and the second hollow portion 72 surrounds the exposed side of the second sub-section 22, as shown in Figures 6A and 6B.
  • Figure 6B is a cross-sectional view parallel to the substrate direction.
  • Step 108 on the basis of the substrate 1 formed with the aforementioned pattern, a third insulating film and a conductive material are sequentially deposited in the first hollow portion 71 and the second hollow portion 72, so that the third insulating film forms a third insulating layer 13, and the conductive material forms a second electrode 42, and the third insulating layer 13 covers the exposed area of the first sub-portion 21 and the exposed area of the second sub-portion 22, as shown in Figures 7A and 7B, and Figure 7B is a cross-sectional view parallel to the direction of the substrate.
  • the second electrode plate 42 surrounds the first electrode plate 41 , is located between the support layer 43 and the gate electrode 26 , and extends on the side wall of the first electrode plate 41 to form a ring extending in a direction parallel to the substrate.
  • the third insulating layer 13 serves as a medium between the capacitor plates, the second plate 42 serves as one electrode of the capacitor, and the exposed first sub-portion 21 or the exposed second sub-portion 22 serves as the other electrode of the capacitor, namely, the first plate.
  • the third insulating film and the conductor material can be deposited by atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the third insulating film may be a High-K dielectric material, such as a dielectric material with a dielectric constant K ⁇ 3.9.
  • the High-K dielectric material may include but is not limited to at least one of the following: silicon oxide, aluminum oxide (Al 2 O 3 ), and hafnium oxide.
  • the conductor material includes but is not limited to at least one of the following: polysilicon, tungsten, and titanium nitride.
  • Step 108 based on the substrate 1 formed with the aforementioned pattern, the first sacrificial layer 16 located in the through hole K1 is removed by etching, as shown in Figure 8.
  • Figure 8 is a cross-sectional view parallel to the substrate direction.
  • Step 109 etching the patterned conductive layer 12 in a direction parallel to the substrate and away from the through hole K1, etching the through hole K1 on the first sub-portion 21 and the second sub-portion 22 of each layer of the patterned conductive layer 12 in a direction away from the through hole K1, expanding the area of the through hole K1 located in the patterned conductive layer 12 in a direction away from the through hole K1, so that the area of the orthographic projection of the through hole K1 on the substrate 1 is enlarged, so that each layer of the patterned conductive layer 12 forms a first electrode 51 and a second electrode 52 separated from each other, as shown in Figures 9A and 9B.
  • Figure 9A is a cross-sectional view parallel to the substrate direction
  • Figure 9B is a cross-sectional view perpendicular to the substrate direction
  • Figure 9B is a cross-sectional view in the bb' direction in Figure 9A.
  • the area where the through hole K1 is located in the patterned insulating layer 14 is not etched, so that on a plane parallel to the substrate, the orthographic projection of the through hole K1 located in the patterned insulating layer 14 on the substrate falls within the orthographic projection of the through hole K1 located in the patterned conductive layer 12 on the substrate, that is, the through hole K1 forms a plurality of dumbbell-shaped structures.
  • the D is, for example, 80nm to 110nm
  • the d is, for example, 50nm ⁇ 10%
  • the L is, for example, 15nm to 30nm
  • D can be 80nm
  • L can be 15nm
  • D is 90nm
  • L is 20nm
  • D is 100nm
  • L is 25nm
  • D is 110nm
  • L is 30nm.
  • Step 110 forming a semiconductor layer 23 , a gate insulating layer 24 and a second sacrificial layer 25 .
  • the formation of the semiconductor layer 23, the gate insulating layer 24 and the second sacrificial layer 25 includes: sequentially depositing a semiconductor film and a gate insulating film on the sidewall of the through hole K1 to form the semiconductor layer 23 and the gate insulating layer 24; after the semiconductor layer 23 and the gate insulating layer 24 are deposited, the size of the through hole K1 located in the parasitic MOS region 300 is smaller than the size of the through hole K1 located in the transistor channel region 200 in the first direction D1, as shown in FIG10A.
  • FIG10A is a cross-sectional view perpendicular to the substrate direction.
  • a second sacrificial layer film is deposited on the through hole K1 to form a second sacrificial layer 25, and the second sacrificial layer 25 fills the through hole K1.
  • the second sacrificial layer 25 serves as a protective layer for the semiconductor layer 23 of the transistor channel region 200 when the semiconductor layer 23 and the gate insulating layer 24 on the side wall of the parasitic MOS region 300 are subsequently etched.
  • the second sacrificial layer 25 fills the through hole K1, and the size of the second sacrificial layer 25 located in the transistor channel region 200 in the first direction D1 is larger than the size of the second sacrificial layer 25 located in the parasitic MOS region 300 in the first direction D1, so as to protect the semiconductor layer 23 of the transistor channel region 200 when the conductor 23 and the gate insulating layer 24 of the parasitic MOS region 300 are subsequently removed, as shown in FIG. 10B.
  • FIG. 10B is a cross-sectional view perpendicular to the substrate direction.
  • the material of the second sacrificial layer film may be a conductive material, for example, the same as the material of the subsequent gate electrode film, so that after the semiconductor layer 23 and the gate insulating layer 24 on the sidewalls of the parasitic MOS region 300 are etched away, the second sacrificial layer 25 does not need to be removed before the gate electrode film is deposited, and the gate electrode film can be directly deposited, and the second sacrificial layer 25 as a protective layer and the deposited gate electrode film together serve as the gate electrode of the final device.
  • the embodiments of the present disclosure are not limited thereto, and the material of the sacrificial layer film may be different from that of the gate electrode film, and after the semiconductor layer 23 and the gate insulating layer 24 on the sidewalls of the parasitic MOS region 300 are etched away, the second sacrificial layer 25 does not need to be removed before the gate electrode film is deposited.
  • the semiconductor film, the gate insulating film and the second sacrificial layer film may be deposited by ALD.
  • the semiconductor film includes but is not limited to at least one of the following: Indium Gallium Zinc Oxide (IGZO), Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO).
  • IGZO Indium Gallium Zinc Oxide
  • ITO Indium Tin Oxide
  • IZO Indium Zinc Oxide
  • the gate insulating film may be a High-K dielectric material, such as a dielectric material with a dielectric constant K ⁇ 3.9.
  • the High-K dielectric material may include but is not limited to at least one of the following: silicon oxide, aluminum oxide (Al 2 O 3 ), and hafnium oxide.
  • the second sacrificial layer film includes but is not limited to at least one of the following: indium tin oxide (ITO), TiN/W, aluminum doped zinc oxide (AZO), and indium zinc oxide (IZO).
  • ITO indium tin oxide
  • TiN/W titanium dioxide
  • AZO aluminum doped zinc oxide
  • IZO indium zinc oxide
  • Step 111 removing the semiconductor layer 23 and the gate insulating layer 24 located in the through hole K1 of the parasitic MOS region 300 .
  • a mask may be used to open the through hole K1, and a first dry etching (anisotropic dry etching), a wet etching (isotropic wet etching), and a second dry etching may be used in sequence.
  • the semiconductor layer 23 and the gate insulating layer 24 on the side wall of the parasitic MOS region 300 are removed by three-step etching of the first dry etching method (and the etching is anisotropic dry etching).
  • the removal of the semiconductor layer 23 and the gate insulating layer 24 on the parasitic MOS region 300 may include: etching the second sacrificial layer 25 by the first dry etching method, and due to the anisotropic etching, the second sacrificial layer 25 on the side wall of the through hole K1 in the parasitic MOS region 300 will be completely etched, and the second sacrificial layer 25 on the side wall of the through hole K1 in the transistor channel region 200 will be partially retained, as shown in FIG. 11A, which is a cross-sectional view perpendicular to the substrate direction.
  • the second sacrificial layer 25 remaining on the side wall of the through hole K1 located in the transistor channel region 200 is too thick, when the semiconductor layer 23 and the gate insulating layer 24 of the parasitic MOS region 300 are subsequently etched by dry etching, the etching of the semiconductor layer 23 and the gate insulating layer 24 of the next parasitic MOS region 300 may be blocked.
  • the second sacrificial layer 25 retained on the side wall of the through hole K1 located in the transistor channel region 200 is recessed by wet etching, and part of the second sacrificial layer 25 is retained during the recessing as a protective layer for the semiconductor layer 23 and the gate insulating layer 24 of the transistor channel region 200, so as to avoid damage to the semiconductor layer 23 and the gate insulating layer 24 of the transistor channel region 200 during the subsequent dry etching of the semiconductor layer 23 and the gate insulating layer 24 of the parasitic MOS region 300, that is, the second sacrificial layer 25 serves as an inner spacer to protect the semiconductor layer 23 and the gate insulating layer 24 of the transistor channel region 200.
  • FIG. 11B is a cross-sectional view perpendicular to the direction of the substrate.
  • the semiconductor layer 23 and the gate insulating layer 24 on the side wall of the through hole K1 in the parasitic MOS region 300 are completely etched away.
  • Step 112 forming a gate electrode 26 .
  • forming the gate electrode 26 includes: depositing a gate electrode film in the through hole K1 to form the gate electrode 26 , wherein the gate electrode 26 fills the through hole K1 , as shown in FIG. 1A .
  • the gate electrode thin film may be deposited by ALD.
  • the gate electrode film may include but is not limited to at least one of the following: indium tin oxide (ITO), TiN/W, aluminum doped zinc oxide (AZO), and indium zinc oxide (IZO).
  • ITO indium tin oxide
  • TiN/W titanium dioxide
  • AZO aluminum doped zinc oxide
  • IZO indium zinc oxide
  • Step 113 etching away the portion of the patterned stacked structure located on one side of the memory cell to form a through hole K2, depositing a conductive film in the through hole K2 so that the conductive film forms a detection pin 61, and the detection pin 61 is electrically connected to the bit line 30 of each layer of the memory cell, as shown in FIG. 1B.
  • the solution provided in this embodiment forms a patterned stacked structure and a through hole K1 simultaneously through a single patterning process, thereby simplifying the process flow, being easy to implement, and improving production efficiency. It has the advantages of easy process implementation, low production cost, and high yield rate.
  • the present disclosure also provides an electronic device, including the semiconductor device described in any of the above embodiments.
  • the electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
  • the storage device may include a memory in a computer, etc., which is not limited here.

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Abstract

一种半导体器件的制造方法，包括：通过一次构图工艺，使叠层结构形成图案化叠层结构，以及形成通孔，所述图案化叠层结构包括依次交替设置的图案化导电层和图案化绝缘层，所述通孔在垂直于衬底的方向上贯穿所述图案化叠层结构，所述通孔的侧壁露出所述图案化导电层和所述图案化绝缘层，所述通孔配置为容纳所述字线。

Description

半导体器件及其制造方法、电子设备
本申请要求于2023年2月20日提交中国专利局、申请号为202310137930.0、发明名称为“3D存储器及其制造方法、电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于半导体技术的器件设计和制造领域，尤指一种半导体器件及其制造方法、电子设备。
背景技术
半导体存储从应用上可划分为易失性存储器(RAM，包括DRAM和SRAM等)，以及非易失性存储器(ROM和非ROM)。以DRAM为例，传统已知的DRAM有多个重复的“存储单元”，每个存储单元有一个电容和晶体管。电容可以存储1位数据，充放电后，电容存储电荷的多少可以分别对应二进制数据“1”和“0”。晶体管是控制电容充放电的开关。
为了尽可能降低产品的成本，人们希望在有限的衬底上做出尽可能多的存储单元。自从摩尔定律问世以来，业界提出了各种半导体结构设计和工艺优化，以满足人们对当前产品的需求。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种半导体器件及其制造方法、电子设备。
一方面，本公开实施例提供一种半导体器件的制造方法，所述半导体器件包括多层沿垂直于衬底的方向堆叠的存储单元、沿垂直于所述衬底方向延伸的字线，所述存储单元包括：晶体管和电容，所述晶体管包括第一电极、第二电极、沿垂直于所述衬底的方向延伸的栅电极、环绕所述栅电极且与所述栅电极相绝缘的半导体层，所述电容包括第一极板和第二极板。所述半导体器件的制造方法包括：
提供衬底，在所述衬底上依次交替沉积第一绝缘薄膜和导电薄膜，形成叠层结构；
通过一次构图工艺，使所述叠层结构形成图案化叠层结构，以及形成通孔；所述图案化叠层结构包括依次交替设置的图案化导电层和图案化绝缘层；所述通孔在垂直于所述衬底的方向上贯穿所述图案化叠层结构，所述通孔的侧壁露出所述图案化导电层和所述图案化绝缘层；所述通孔配置为容纳所述字线。
在一些实施例中，所述通过一次构图工艺，使所述叠层结构形成图案化叠层结构，以及形成通孔，包括：通过一个膜层上的掩膜图形，对所述叠层结构进行构图工艺，使所述叠层结构形成图案化叠层结构，以及形成通孔。所述掩膜图形为同时具有架构和孔结构的图形。
在一些实施例中，所述膜层为光刻胶。
在一些实施例中，所述膜层为硬掩膜层。
在一些实施例中，半导体器件的制造方法，还包括：形成填满所述通孔的第一牺牲层；形成环绕所述图案化叠层结构侧壁的填充层；去除部分所述填充层以及部分所述图案化绝缘层，将部分所述图案化导电层暴露，使暴露的所述图案化导电层作为所述第一极板，在去除所述填充层和所述图案化绝缘层的区域形成所述第二极板；刻蚀去除所述第一牺牲层；在平行于所述衬底的平面上，朝远离所述通孔的方向刻蚀所述图案化导电层，所述通孔使得所述图案化导电层形成彼此分离的第一电极和第二电极；在所述通孔的侧壁依次沉积相互绝缘的半导体薄膜和栅电极薄膜，形成所述半导体层、所述栅电极和所述字线。
在一些实施例中，所述形成填满所述通孔的第一牺牲层包括：
在所述衬底上沉积第一牺牲层薄膜，所述第一牺牲层薄膜覆盖所述衬底的部分表面、覆盖所述图案化叠层结构的侧面和上表面以及将所述通孔填满；
对所述第一牺牲层薄膜进行构图工艺，将覆盖所述衬底表面的第一牺牲层薄膜以及覆盖所述图案化叠层结构的侧面和上表面的第一牺牲层薄膜去除，保留将所述通孔填满的第一牺牲层薄膜，形成所述第一牺牲层。
在一些实施例中，所述形成环绕所述图案化叠层结构侧壁的填充层之后，所述制造方法还包括：研磨所述填充层的表面，使所述填充层远离所述衬底一侧的表面与所述图案化叠层结构远离所述衬底一侧的表面平齐。
在一些实施例中，去除部分所述填充层以及部分所述图案化绝缘层，将部分所述图案化导电层暴露，使暴露的所述图案化导电层作为第一极板，在去除所述填充层和所述图案化绝缘层的区域形成第二极板之前，所述制造方法还包括：
去除所述膜层图案至少一侧的所述填充层以及所述图案化绝缘层，将所述图案化导电层的一端暴露；
在暴露的所述图案化导电层的一端上形成支撑层，所述支撑层包括固定槽，所述固定槽将暴露的所述图案化导电层的一端固定。
在一些实施例中，所述支撑层包括绝缘材料。
本公开实施例还提供一种如上所述的半导体器件的制造方法制造而成的半导体器件，包括：多层沿垂直于衬底的方向堆叠的存储单元、字线，其中，所述字线沿着垂直于所述衬底的方向延伸且贯穿不同层的所述存储单元。所述存储单元包括：晶体管和电容，所述晶体管包括第一电极、第二电极、沿垂直于所述衬底的方向延伸的栅电极、环绕所述栅电极且与所述栅电极相绝缘的半导体层，所述半导体层在所述栅电极的侧壁上延伸形成沿着垂直于所述衬底方向延伸的环形的半导体层；所述电容包括第一极板和第二极板。
在一些实施例中，半导体器件还包括支撑层，所述支撑层位于所述第一极板远离所述栅电极一侧，所述支撑层包括固定槽，所述固定槽的开口朝向所述第一极板的一端，所述第一极板的一端伸入所述固定槽中。
在一些实施例中，所述第二极板位于所述支撑层与所述字线之间，所述第二极板环绕所述第一极板，所述第二极板在所述第一极板的侧壁上延伸形成沿着平行于所述衬底方向延伸的环形。
本公开实施例还提供一种电子设备，包括上述任一实施例所述的半导体器件。
本公开实施例提供了一种半导体器件及其制造方法、电子设备，通过一次构图工艺，同时形成图案化叠层结构和通孔K1，简化了工艺流程，易于实施，提高生产效率，具有易于工艺实现、生产成本低和良品率高等优点。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开的技术方案，并不构成对技术方案的限制。
图1A为一示例性实施例提供的半导体器件沿垂直于衬底方向的截面图；
图1B为一示例性实施例提供的半导体器件沿平行于衬底方向的截面图；
图1C为一示例性实施例提供的半导体器件沿垂直于衬底方向的截面示意图的局部放大图；
图1D为一示例性实施例提供的半导体器件沿垂直于衬底方向的截面示意图的另一局部放大图；
图2为一示例性实施例提供的半导体器件的制造过程中形成堆叠结构后的示意图；
图3A为一示例性实施例提供的半导体器件的制造过程中放置第一掩膜版后的示意图；
图3B为一示例性实施例提供的半导体器件的制造过程中形成图案化导电层、图案化绝缘层以及通孔后的示意图一；
图3C为一示例性实施例提供的半导体器件的制造过程中形成图案化导电层、图案化绝缘层以及通孔后的示意图二；
图3D为一示例性实施例提供的半导体器件的制造过程中形成图案化导电层、图案化绝缘层以及通孔后的示意图三；
图4A为一示例性实施例提供的半导体器件的制造过程中形成第一牺牲层薄膜后的示意图；
图4B为一示例性实施例提供的半导体器件的制造过程中形成第一牺牲层后的示意图；
图4C为一示例性实施例提供的半导体器件的制造过程中形成填充层后的示意图；
图5A为一示例性实施例提供的半导体器件的制造过程中放置第二掩膜版后的示意图；
图5B为一示例性实施例提供的半导体器件的制造过程中形成凹槽后的示意图；
图5C为一示例性实施例提供的半导体器件的制造过程中形成支撑层后的示意图一；
图5D为一示例性实施例提供的半导体器件的制造过程中形成支撑层后的示意图二；
图6A为一示例性实施例提供的半导体器件的制造过程中形成第一镂空部分和第二镂空部分后的示意图一；
图6B为一示例性实施例提供的半导体器件的制造过程中形成第一镂空部分和第二镂空部分后的示意图二；
图7A为一示例性实施例提供的半导体器件的制造过程中形成第二极板后的示意图一；
图7B为一示例性实施例提供的半导体器件的制造过程中形成第二极板后的示意图二；
图8为一示例性实施例提供的半导体器件的制造过程中去除第一牺牲层后的示意图；
图9A为一示例性实施例提供的半导体器件的制造过程中形成第一电极和第二电极后的示意图一；
图9B为一示例性实施例提供的半导体器件的制造过程中形成第一电极和第二电极后的示意图二；
图10A为一示例性实施例提供的半导体器件的制造过程中形成半导体层和栅极绝缘层后的示意图；
图10B为一示例性实施例提供的半导体器件的制造过程中形成第二牺牲层后的示意图；
图11A为一示例性实施例提供的半导体器件的制造过程中刻蚀第二牺牲层后的示意图；
图11B为一示例性实施例提供的半导体器件的制造过程中回刻第二牺牲层后的示意图。
详述
下文中将结合附图对本公开实施例进行详细说明。在不冲突的情况下，本公开实施例及实施例中的特征可以相互任意组合。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。
本公开的实施方式并不一定限定附图所示尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，并不表示任何顺序、数量或者重要性。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在公开中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是物理连接或信号连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本公开中，晶体管可以包含栅极(还可以称为栅电极)、沟道以及第一极(下述中的第一电极51)和第二极(下述中的第二电极52)，其中，第一电极可以为漏电极、第二电极可以为源电极，或者第一电极可以为源电极、第二电极可以为漏电极。源电极还可以称为漏电极端子、漏区域或漏极，漏电极还可以称为源电极端子、源区域或源极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“连接”或“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本公开中，“平行”是指大约平行或几乎平行，比如，两条直线形成的角度为-10°以 上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指大约垂直，比如，两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本公开中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开所说的“A和B同层设置”包含位于同一个膜层上的相同材料或不同材料形成的膜层。示例性的，A和B通过同一种材料形成同一个膜层后经同一次图案化工艺或不同的图案化工艺形成。同层设置的A和B可以是位于一个水平面上但是不必须位于同一个膜层上，或位于同一个膜层的不同区域但是不必须位于相同的水平面上。
本公开实施例中的“A和B为一体式结构”可以包含在一个膜层上图案化形成连接的膜层为一体式。比如A和B使用相同的材料成一个膜层并通过同一次图案化工艺同时形成具有连接关系的结构。
本公开实施例中，通过刻蚀去除层间的半导体层，可以降低或消除寄生MOS管(简称寄生MOS)。
图1A为一示例性实施例提供的半导体器件沿垂直于衬底方向的截面示意图；图1C和图1D可以为一示例性实施例提供的半导体器件沿垂直于衬底方向的截面示意图的局部放大图。其中，图1C和图1D可以为图1A中a处的放大图；垂直于衬底的方向可以为图1A中的第三方向D3。如图1A和图1C所示，本实施例提供的半导体器件可以包括：多层沿垂直于衬底1的方向堆叠的存储单元、字线40，其中，所述字线40沿着垂直于所述衬底1的方向延伸且贯穿不同层的所述存储单元。
如本文所用,术语“衬底”意指并包括其上形成诸如垂直场效应晶体管的材料的基底材料或构造。衬底可以是半导体衬底、支撑结构上的基础半导体层、金属电极或具有形成在其上的一个或多个层、结构或区域的半导体衬底。衬底可以是常规的硅衬底或包括半导体材料层的其他体衬底。
所述存储单元可以包括：晶体管，所述晶体管包括第一电极51、第二电极52、沿垂直于所述衬底的方向延伸的栅电极26，环绕所述栅电极26且与所述栅电极26相绝缘的半导体层23，所述半导体层23在所述栅电极26的侧壁上延伸形成沿着垂直于所述衬底方向延伸的环形的半导体层。第一电极51和第二电极52位于栅电极26在第一方向D1的相对两侧，至少部分半导体层23分别位于第一电极51与栅电极26之间，以及第二电极52与栅电极26之间。其中，所述第一电极51和所述第二电极52之间的沟道为水平沟道；至少部分相邻层的所述存储单元的所述晶体管的半导体层23在垂直于所述衬底的方向上间隔设置，所述栅电极26连接所述字线40。其中，第一方向D1平行于衬底所在平面。
其中，字线为垂直堆叠的多个晶体管共用的引线，该引线与多个晶体管的栅极连接。在图1A所示的叠层结构中，字线40可以为纵向延伸的一根线，被三个晶体管共用。栅极是指一个晶体管的栅电极，在图1A中，栅极26可以为字线40的一部分。字线40整体上沿着纵向(例如第三方向D3)延伸，但是其不同位置的横截面大小可以相同或不同，比如，字线40上与每个晶体管的有效沟道对应的区域为有效栅极，该有效栅极的横截面可以大于字线40上的其他区域(比如图1D所示)或小于其他区域，本申请不做限定。所述的其他区域可以是不与晶体管的有效沟道对应的区域，比如，为两个纵向堆叠的晶体管之间的区域。
本实施例提供的半导体器件，在垂直于所述衬底1方向，相邻层的晶体管的半导体层 间隔设置，可以降低或消除至少部分层间的寄生MOS，提高器件稳定性。所述的间隔设置可以理解为：相邻层的晶体管的相邻半导体层之间是隔断的，比如孔内壁形成的半导体层在隔断区域被挖空，或被改性，使得隔断区域无法起到半导体的作用。
水平沟道为沟道中载流子传输方向整体上在平行于衬底的平面内。
在一示例性实施例中，不同层的所述存储单元的所述晶体管的半导体层23在垂直于所述衬底的方向上间隔设置。例如，全部相邻层的所述存储单元的所述晶体管的半导体层23在垂直于所述衬底的方向上间隔设置，从而可以消除全部相邻层间的寄生MOS，提高器件稳定性。
在一示例性实施例中，所述半导体层23可以为全环绕型，在栅电极26的侧壁上全环绕，即，半导体层23沿平行于衬底的方向的横截面为闭环。示例性的，所述半导体层23为环形，且环形形状与栅电极26的横截面外轮廓形状相适应。示例性的，所述栅电极26的横截面比如为方形等结构。
在一示例性实施例中，如图1A和图1C所示，所述栅电极26包括中间部分261和位于所述中间部分261外侧的周边部分262，中间部分261仅沿垂直于所述衬底1的方向延伸，中间部分261可以与字线40在所述衬底1的正投影完全交叠。中间部分261可以与字线40一体成型，采用相同的材料通过同一制造工艺制造而成。周边部分262环绕中间部分261的四周，周边部分262可以在中间部分261的侧壁上全环绕，至少部分周边部分262与中间部分261的侧壁接触，周边部分262与字线40在所述衬底1的正投影不交叠，与半导体层23在所述衬底1的正投影存在交叠。
在一示例性实施例中，所述晶体管还可以包括环绕所述栅电极26侧壁的栅极绝缘层24，所述栅极绝缘层24位于栅电极26与半导体层23之间，将栅电极26与半导体层23绝缘。
在一示例性实施例中，不同层的晶体管可以共用一个沿着垂直所述衬底方向延伸的环状的栅极绝缘层24。
在一示例性实施例中，至少部分相邻层的晶体管的栅极绝缘层24在垂直于所述衬底的方向上间隔设置。
在一示例性实施例中，不同层晶体管的栅极绝缘层24在垂直于所述衬底的方向上间隔设置。
在一示例性实施例中，沿垂直于所述衬底方向，同一晶体管的所述第一电极51和第二电极52可以位于同一导电膜层。所述第一电极51和第二电极52可以由一个导电膜层图案化形成，所述导电膜层与所述衬底的上表面大约平行。第一电极51和第二电极52可以同层设置。即所述第一电极51和所述第二电极52可以通过同一次图案化工艺同时形成，但本公开实施例不限于此，可以通过不同图案化工艺分别制造所述第一电极51和所述第二电极52。
在一示例性实施例中，不同晶体管的所述第一电极51或所述第二电极52可以位于不同的导电膜层。
在一示例性实施例中，不同层的堆叠的晶体管可以共用一条沿着垂直所述衬底方向延伸的所述字线40。
在一示例性实施例中，不同层的晶体管对应的半导体层23可以位于所述字线40的侧壁且分别位于沿垂直所述衬底的方向延伸的不同区域。
在一示例性实施例中，所述间隔设置的所述半导体层23之间露出绝缘层，所述绝缘 层为位于所述栅电极26和所述半导体层23之间的栅极绝缘层24。本实施例提供的方案，通过栅极绝缘层24隔离第一电极51和栅电极26，避免过刻导致第一电极51暴露，导致第一电极51和栅电极26之间发生短路。
图1B为一示例性实施例提供的半导体器件沿平行于衬底方向的截面图。在一示例性实施例中，如图1B所示，同层的所述存储单元形成分别沿第一方向D1和第二方向D2分布的阵列，每层所述存储单元还包括：位线30，所述位线30与同层同一列的晶体管的所述第二电极52连接。图1B中示出了每层包括三行两列存储单元，但本公开实施例不限于此，每层可以包括其他行数和列数的存储单元，比如，可以只包括一个存储单元。所述第一方向D1可以平行于所述衬底，所述第二方向D2可以平行于所述衬底，第一方向D1和第二方向D2交叉。在一些实施例中，所述第一方向D1和第二方向D2可以垂直。
在一示例性实施例中，相邻两列的存储单元的晶体管的第二电极52连接到同一位线30。同层相邻两列的晶体管的所述第二电极52与所述位线30可以为一体式结构。
在一示例性实施例中，所述晶体管的第二电极52可以是该第二电极52所连接的位线30的一部分。
在一示例性实施例中，所述位线30可以沿第二方向D2延伸。
在一示例性实施例中，所述第一电极51可以沿第一方向D1延伸。
在一示例性实施例中，所述半导体器件还可以包括数据存储元件。
在一示例性实施例中，所述数据存储元件可以为电容，即形成1T1C的存储结构。但本公开实施例不限于此，可以和其他晶体管组成2T0C的存储结构，等等。
在一示例性实施例中，如图1A和图1B所示，所述电容可以包括第一极板41和第二极板42，所述第一极板41与所述第一电极51连接。所述第二极板42环绕第一极板41，且与所述第一极板41相绝缘，所述第二极板42在所述第一极板41的侧壁上延伸形成沿着平行于所述衬底方向延伸的环形。
在一示例性实施例中，如图1A和图1B所示，所述半导体器件还可以包括支撑层43，所述支撑层43位于第一极板41远离所述栅电极26一侧，所述第二极板42位于所述支撑层43与所述字线40之间。所述支撑层43包括固定槽44，所述固定槽44的开口朝向所述第一极板41的一端，所述第一极板41远离所述位线30的一端伸入所述固定槽44中，使所述支撑层43将所述第一极板41固定，以保证第一极板41的机械稳定性。所述半导体器件在制造过程中，可以先将第一极板41暴露，然后，形成支撑层43，通过支撑层43将第一极板41的一端固定，保证第一极板41的机械稳定性，最后，形成环绕第一极板41的第二极板42。
在一示例性实施例中，所述第一极板41与所述第一电极51可以为一体式结构。
在一示例性实施例中，不同层的相同列的所述电容的所述第二极板42可以连接为一体式结构。如图1B所示，不同层的第一列的所述电容的所述第二极板42连接为一体式结构。不同层的第二列的所述电容的所述第二极板42连接为一体式结构，即，不同层的相同列的所述电容共用同一极板作为第二极板42。
在一示例性实施例中，所述电容还可以包括设置在所述第一极板41和第二极板42之间的第三绝缘层13。第三绝缘层13作为第一极板41和第二极板42之间的介质。
在一示例性实施例中，如图1B所示，在平行于衬底方向的截面上，所述半导体器件还可以包括检测引脚61，所述检测引脚61设置在所述存储单元的一侧，检测引脚61与每层所述存储单元的位线30电连接，检测单元可以与检测引脚61电连接，通过检测引脚 61向所述存储单元的位线30输入检测信号，检测存储单元。
在一示例性实施例中，沿垂直于衬底方向相邻的晶体管的所述第一电极在垂直衬底的方向的投影重叠，所述第二电极在垂直衬底的方向的投影重叠，所述栅电极在垂直衬底的方向的投影重叠。本实施例提供的方案，在工艺过程中，可以通过导电层和绝缘层的相对堆叠再通过一个掩膜形成多层堆叠的第一电极、第二电极以及通孔K1，实现工艺简单。另外，可以使得半导体器件的结构更为紧凑。
本申请实施例的半导体器件可以和电容器组成1T1C的存储结构，或者，和其他晶体管组成2T0C的存储结构，等等。
下面通过本实施例半导体器件的制造过程进一步说明本实施例的技术方案。本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是相关技术中成熟的制造工艺。本实施例中所说的“光刻工艺”包括涂覆膜层、掩模曝光和显影，是相关技术中成熟的制造工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做限定。在本实施例的描述中，需要理解的是，“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺或光刻工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”还需构图工艺或光刻工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺或光刻工艺后的“层”中包含至少一个“图案”。
本实施例中，每层包括多个存储单元，但本公开实施例不限于此，每层可以包括一个存储单元。
在一示例性实施例中，半导体器件的制造过程可以包括：
步骤101，在衬底1上依次交替沉积第一绝缘薄膜10和第一导电薄膜11形成叠层结构，如图2所示。
在一示例性实施例中，可以利用化学气相沉积(Chemical Vapor Deposition，CVD)方法沉积所述第一绝缘薄膜10和第一导电薄膜11。
如本文所用,术语“衬底”意指并包括其上形成诸如垂直场效应晶体管的材料的基底材料或构造。衬底可以是半导体衬底、支撑结构上的基础半导体层、金属电极或具有形成在其上的一个或多个层、结构或区域的半导体衬底。衬底可以是常规的硅衬底或包括半导体材料层的其他体衬底。在一示例性实施例中，所述衬底可以为半导体衬底，比如可以是硅衬底。
在一示例性实施例中，所述第一绝缘薄膜10可以是介质常数较小的介质层，比如二氧化硅(SiO2)等。
在一示例性实施例中，所述第一导电薄膜11可以包括但不限于氮化钛(TiN)/钨(W)的多层结构。
图2中示出的叠层结构包括四层第一绝缘薄膜10和三层第一导电薄膜11，仅为示例，在其他实施例中，所述叠层结构可以包括更多或更少层交替设置的第一绝缘薄膜10和第一导电薄膜11。
步骤102，在形成前述图案的衬底1的基础上，先将第一掩膜版2(可以理解为掩膜图形)形成在所述叠层结构远离衬底1一侧的表面上，如图3A所示。掩膜图形可以是光刻(PR，Photoresist)胶或硬掩膜层上的图形。硬掩膜(Hardmask)层可以使用SiO2、Si3N4、TiN、非晶碳(ACHM)等，主要用于多重曝光工艺等。在一些示例中，可以在形成前述 图案的衬底上涂覆光刻胶，通过将光刻胶的部分去除，形成掩膜图形。
在一些示例中，如图3A至图3C所示，掩膜图形可以为同时具有架构和孔结构的图形。掩膜图形的架构可以大致为鱼骨形状。例如，掩膜图形的架构可以包括“丰”字型结构以及与“丰”字型结构的一端连接的矩形块。比如，“丰”字型结构可以包括沿第一方向D1延伸的六个分支以及沿第二方向Y延伸的一个主支，六个分支可以在第一方向D1上对称地设置在主支的两侧，矩形块可以与主支的一端连接。六个分支可以均为沿第一方向D1延伸的条状，主干可以为沿第二方向Y延伸的条状。分支和主干在衬底的正投影形状可以大致为矩形，矩形块沿第一方向D1的长度可以大于主干沿第一方向D1的长度。
在一些示例中，掩膜图形的孔结构可以包括按照三行两列阵列排布的六个孔，沿第一方向D1排布的两个孔为一行，沿第二方向D2排布的三个孔为一列。六个孔分别位于“丰”字型结构的六个分支上。在一些示例中，在平行于衬底的平面上，孔的正投影形状可以为矩形，比如可以为方形。本实施例对此并不限定。在另一些示例中，孔的正投影形状可以为其他形状，比如可以为圆形等。
本示例通过一个掩膜图形可以一次性刻蚀形成半导体器件的架构部分和设置字线的通孔，可以避免单独刻蚀通孔产生对位偏差影响半导体器件的尺寸结构电学特性以及整个结构的微缩效果的情况，从而保证半导体器件的结构尺寸稳定性，有利于实现微缩效果，可以提升半导体器件的良率；而且通过一次性刻蚀形成半导体器件的架构区域和设置字线的通孔，可以减少刻蚀工艺，简化工艺，降低成本。
随后，通过第一掩膜版2，对所述叠层结构进行构图工艺，使所述叠层结构形成图案化叠层结构，使多个第一导电薄膜11形成图案化导电层12，使多个第一绝缘薄膜10形成图案化绝缘层14，以及形成多个通孔K1。所述图案化叠层结构包括依次交替设置的图案化导电层12和图案化绝缘层14。所述通孔K1沿着垂直于所述衬底方向延伸，在垂直于所述衬底的方向上贯穿所述图案化叠层结构，如图3B和图3C所示。其中，图案化导电层12与图案化绝缘层14在衬底1的正投影可以完全交叠，即图案化导电层12的尺寸和形状与图案化绝缘层14的尺寸和形状相同。
图3C为一示例性实施例提供的半导体器件的制造过程中形成图案化导电层、图案化绝缘层以及通孔后的示意图二。图3C为平行于所述衬底方向的截面图。在一示例性实施例中，如图3C所示，图案化导电层12可以包括位线30、多个第一子部21和多个第二子部22，位线30连接第一子部21和第二子部22，所述第一子部21可以沿第一方向D1延伸，所述第二子部22可以沿第一方向D1延伸，所述位线30可以沿第二方向D2延伸。多个第一子部21沿着第二方向D2间隔排布，多个第一子部21的一端均与位线30连接。多个第二子部22沿着第二方向D2间隔排布，多个第二子部22的一端均与位线30连接。所述第一子部21在后续形成一个晶体管的第一电极51和第二电极52，所述第二子部22在后续形成相邻的另一晶体管的第一电极51和第二电极52。
图3D为一示例性实施例提供的半导体器件的制造过程中形成图案化导电层、图案化绝缘层以及通孔后的示意图三。图3D为垂直于所述衬底方向的截面图，图3D可以为图3C中aa’方向的截面图。在一示例性实施例中，如图3D所示，通孔K1贯穿多个图案化导电层12和多个图案化绝缘层14，所述通孔K1的侧壁露出每层图案化导电层12和每层图案化绝缘层14。其中，所述第一子部21和所述第二子部22均设置有所述通孔K1。所述通孔K1可以沿垂直于所述衬底的方向延伸。所述通孔K1的底壁可以暴露或不暴露所述衬底。
在一示例性实施例中，可以通过第一掩膜版2对所述叠层结构进行干法刻蚀，可以采 用高深宽比刻蚀(High Aspect ratio Etch，HAR ET)方式进行刻蚀，在一示例性实施例中，深宽比(Aspect ratio)>6:1。
在一示例性实施例中，所述通孔K1在平行于所述衬底的平面上的正投影可以是方形。然而，本实施例对此并不限定。
在一示例性实施例中，所述通孔K1在平行于所述衬底的平面上的正投影位于所述图案化导电层12的正投影内。比如，在平行于所述衬底的平面上，贯穿第一子部21的通孔K1的正投影位于所述第一子部21的正投影内，贯穿第二子部22的通孔K1的正投影位于所述第二子部22的正投影内。
步骤103，在形成前述图案的衬底1的基础上，在衬底1上沉积第一牺牲层薄膜15，第一牺牲层薄膜15覆盖衬底1的部分表面、覆盖所述图案化叠层结构的侧面和上表面以及将通孔K1填满，第一牺牲层薄膜15将通孔K1填满，使所述叠层结构远离衬底1一侧的表面平齐，如图4A所示。
步骤104，在形成前述图案的衬底1的基础上，对第一牺牲层薄膜15进行构图工艺，将覆盖衬底1表面的第一牺牲层薄膜15以及覆盖所述图案化叠层结构的侧面和上表面的第一牺牲层薄膜15刻蚀去除，保留将通孔K1填满的第一牺牲层薄膜15，形成第一牺牲层16，第一牺牲层16将通孔K1填满，如图4B所示。
步骤105，在形成前述图案的衬底1的基础上，在衬底1上形成填充层17，填充层17与所述图案化叠层结构同层设置，环绕所述图案化叠层结构的侧壁，与图案化叠层结构的侧壁接触。
研磨所述填充层17的表面，使所述填充层17远离所述衬底一侧的表面与所述图案化叠层结构远离所述衬底一侧的表面平齐，填充层17与所述图案化叠层结构组成形状规则的膜层图案，示例的，形状规则的膜层图案可以为长方体形状，如图4C所示。
其中，填充层17可以采用绝缘材料，例如氧化物。
步骤106，在形成前述图案的衬底1的基础上，将第二掩膜版3放置在所述膜层图案远离衬底1一侧的表面上，如图5A所示。
随后，通过第二掩膜版3对所述膜层图案进行构图工艺，去除所述膜层图案相对两侧的部分填充层17以及部分所述图案化绝缘层14，形成凹槽18，凹槽18暴露出部分衬底1的表面，暴露出所述第一子部21远离所述位线30的一端(包括第一子部21的端面和部分侧面)，以及，暴露出所述第二子部22远离所述位线30的一端(包括第二子部22的端面和部分侧面)，如图5B所示。
随后，在所述凹槽18内依次沉积第二绝缘薄膜和支撑层材料，使第二绝缘薄膜形成第二绝缘层19，使支撑层材料形成支撑层43。第二绝缘层19覆盖所述第一子部21暴露出的区域以及所述第二子部22暴露出的区域，即第二绝缘层19覆盖所述第一子部21远离所述位线30的端面以及部分侧壁，以及所述第二子部22远离所述位线30的端面以及部分侧壁，第二绝缘层19设置在支撑层43与所述第一子部21暴露出的区域之间，以及与所述第二子部22暴露出的区域之间。
支撑层43形成在暴露的所述第一子部21远离所述位线30的一端，以及暴露的所述第二子部22远离所述位线30的一端。支撑层43包括固定槽，所述固定槽将暴露的所述第一子部21远离所述位线30的一端，以及暴露的所述第二子部22远离所述位线30的一端固定。支撑层43用于支撑所述第一子部21和所述第二子部22，在形成第二极板42的过程中，保证所述第一子部21和所述第二子部22的机械稳定性，如图5C和图5D所示， 其中，图5D为平行于所述衬底方向的截面图。
其中，支撑层43可以采用绝缘材料，例如氧化物。支撑层43采用绝缘材料可以避免与后续形成的第二极板42产生电容，影响器件性能。
步骤107，在形成前述图案的衬底1的基础上，去除位于电容区域的填充层17以及图案化绝缘层14。暴露出所述第一子部21的部分侧面，以及，暴露出所述第二子部22的部分侧面。在同层相邻的第一子部21暴露的侧面之间，以及，相邻层中第一子部21暴露的侧面之间形成第一镂空部分71；在同层相邻的第二子部22暴露的侧面之间，以及，相邻层中第二子部22暴露的侧面之间形成第二镂空部分72。其中，电容区域为第一极板41和第二极板42所形成电容的区域，电容区域位于支撑层43与位线30之间。
在平行于衬底方向，第一镂空部分71位于支撑层43与通孔K1之间，第一镂空部分71环绕第一子部21暴露的侧面；第二镂空部分72位于支撑层43与通孔K1之间，第二镂空部分72环绕第二子部22暴露的侧面，如图6A和图6B所示。其中，图6B为平行于所述衬底方向的截面图。
步骤108，在形成前述图案的衬底1的基础上，在第一镂空部分71和第二镂空部分72中依次沉积第三绝缘薄膜和导体材料，使第三绝缘薄膜形成第三绝缘层13，使导体材料形成第二极板42，第三绝缘层13覆盖所述第一子部21暴露出的区域以及所述第二子部22暴露出的区域，如图7A和图7B所示，图7B为平行于所述衬底方向的截面图。
其中，所述第二极板42环绕所述第一极板41，所述第二极板42位于支撑层43与栅电极26之间，所述第二极板42在所述第一极板41的侧壁上延伸形成沿着平行于所述衬底方向延伸的环形。
第三绝缘层13作为电容极板间的介质，第二极板42作为电容的一个电极，暴露的第一子部21或者暴露的第二子部22作为电容的另一个电极，即第一极板。
在一示例性实施例中，可以通过原子层沉积(Atomic Layer Deposition，ALD)方式沉积所述第三绝缘薄膜和导体材料。
在一示例性实施例中，所述第三绝缘薄膜可以是High-K介质材料，比如介电常数K≥3.9的介质材料。所述High-K介质材料可以包括但不限于以下至少之一：氧化硅，三氧化二铝(Al2O3)，氧化铪。
在一示例性实施例中，所述导体材料包括但不限于以下至少之一：多晶硅，钨，氮化钛。
步骤108，在形成前述图案的衬底1的基础上，刻蚀去除位于通孔K1中的第一牺牲层16，如图8所示。图8为平行于所述衬底方向的截面图。
步骤109，在平行于所述衬底方向，朝远离所述通孔K1的方向刻蚀所述图案化导电层12，将每层的所述图案化导电层12的第一子部21和第二子部22上的所述通孔K1朝远离所述通孔K1的方向刻蚀，对所述通孔K1位于图案化导电层12的区域向远离所述通孔K1的方向扩充，使所述通孔K1在衬底1的正投影的面积扩大，使得每层所述图案化导电层12形成彼此分离的第一电极51和第二电极52，如图9A和图9B所示。其中，图9A为平行于所述衬底方向的截面图，图9B为垂直于所述衬底方向的截面图，图9B为图9A中bb’方向的截面图。
不对所述通孔K1位于图案化绝缘层14的区域进行刻蚀，使得在平行于所述衬底的平面上，位于图案化绝缘层14的通孔K1在衬底的正投影落入位于图案化导电层12的通孔K1在衬底的正投影内，即，所述通孔K1形成多个哑铃型的结构。
在一示例性实施例中，可以利用湿法刻蚀，选用对图案化绝缘层14和图案化导电层12的刻蚀选择比很高的酸溶液，将图案化导电层12向远离通孔K1的方向横向蚀刻一定厚度L。由于高刻蚀选择比，对图案化绝缘层14几乎没有蚀刻。以通孔K1平行于衬底的截面为正方形为例，此时，位于图案化导电层12的通孔K1的边长为D，位于图案化绝缘层14的通孔K1的边长为d，且D＝d+2*L。在一示例性实施例中，所述D比如为80nm至110nm，所述d比如为50nm±10％，所述L比如为15nm至30nm，比如D可以为80nm，L可以是15nm，或者，D为90nm，L为20nm，或者，D为100nm，L为25nm，或者，D为110nm，L为30nm。
步骤110，形成半导体层23、栅极绝缘层24和第二牺牲层25。
所述形成半导体层23、栅极绝缘层24和第二牺牲层25包括：在所述通孔K1的侧壁依次沉积半导体薄膜和栅绝缘薄膜，形成半导体层23和栅极绝缘层24；沉积完半导体层23和栅极绝缘层24之后，位于寄生MOS区域300的通孔K1的尺寸比位于晶体管沟道区域200的通孔K1在第一方向D1的尺寸小，如图10A所示。图10A为垂直于所述衬底方向的截面图。
随后，在所述通孔K1沉积第二牺牲层薄膜，形成第二牺牲层25，第二牺牲层25将通孔K1填满。所述第二牺牲层25作为后续刻蚀寄生MOS区域300侧壁的半导体层23和栅极绝缘层24时对晶体管沟道区域200的半导体层23的保护层。所述第二牺牲层25填充所述通孔K1，位于晶体管沟道区域200中的第二牺牲层25在第一方向D1的尺寸，比位于寄生MOS区域300中的第二牺牲层25在第一方向D1的尺寸大，便于在后续去除寄生MOS区域300的导体23和栅极绝缘层24时保护晶体管沟道区域200的半导体层23，如图10B所示。图10B为垂直于所述衬底方向的截面图。
在一示例性实施例中，所述第二牺牲层薄膜的材料可以是导电材料，比如和后续的栅电极薄膜的材料一致，从而在刻蚀去除所述寄生MOS区域300侧壁的半导体层23和栅极绝缘层24之后，沉积栅电极薄膜之前不用再去除所述第二牺牲层25，可直接沉积栅电极薄膜，作为保护层的第二牺牲层25和沉积的栅电极薄膜一起作为最终器件的栅电极。但本公开实施例不限于此，牺牲层薄膜的材料可以和栅电极薄膜不一致，在刻蚀去除所述寄生MOS区域300侧壁的半导体层23和栅极绝缘层24之后，沉积栅电极薄膜之前不用去除所述第二牺牲层25即可。
在一示例性实施例中，可以通过ALD方式沉积所述半导体薄膜、所述栅绝缘薄膜和所述第二牺牲层薄膜。
在一示例性实施例中，所述半导体薄膜包括但不限于以下至少之一：铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)、氧化铟锡(Indium Tin Oxide，ITO)、氧化铟锌(Indium Zinc Oxide，IZO)。使用IGZO作为半导体层时，具备低漏电，刷新时间短的优势。
在一示例性实施例中，所述栅绝缘薄膜可以是High-K介质材料，比如介电常数K≥3.9的介质材料。所述High-K介质材料可以包括但不限于以下至少之一：氧化硅，三氧化二铝(Al2O3)，氧化铪。
在一示例性实施例中，所述第二牺牲层薄膜包括但不限于以下至少之一：氧化铟锡(Indium Tin Oxide，ITO)、TiN/W、掺铝氧化锌(Aluminum doped Zinc Oxide，AZO)，氧化铟锌(Indium Zinc Oxide，IZO)。
步骤111，去除位于寄生MOS区域300的通孔K1的半导体层23和栅极绝缘层24。
在一示例性实施例中，可以利用掩模版(mask)，打开通孔K1，依次利用第一干法刻蚀(且为各向异性的干法刻蚀)、湿法刻蚀(且为各向同性的湿法刻蚀)和第二干法刻 蚀(且为各向异性的干法刻蚀)的三步刻蚀进行寄生MOS区域300侧壁的半导体层23和栅极绝缘层24的去除。即，所述去除寄生MOS区域300的半导体层23和栅极绝缘层24可以包括：利用第一干法刻蚀刻蚀所述第二牺牲层25，由于各向异性刻蚀，位于寄生MOS区域300的通孔K1侧壁的第二牺牲层25会被完全刻蚀，位于晶体管沟道区域200的通孔K1侧壁的第二牺牲层25会保留部分，如图11A所示，图11A为垂直于所述衬底方向的截面图。
由于位于晶体管沟道区域200的通孔K1侧壁剩余的第二牺牲层25太厚，导致在后续利用干法刻蚀寄生MOS区域300的半导体层23和栅极绝缘层24时，可能会挡住下一层寄生MOS区域300的半导体层23和栅极绝缘层24的刻蚀，因此，利用湿法刻蚀，对位于晶体管沟道区域200的通孔K1侧壁保留的第二牺牲层25进行回刻(recess)，且回刻时保留部分第二牺牲层25作为晶体管沟道区域200的半导体层23和栅极绝缘层24的保护层，避免后续干法刻蚀寄生MOS区域300的半导体层23和栅极绝缘层24时对晶体管沟道区域200的半导体层23和栅极绝缘层24造成损坏，即第二牺牲层25作为内侧墙(inner spacer)保护晶体管沟道区域200的半导体层23和栅极绝缘层24。如图11B所示，图11B为垂直于所述衬底方向的截面图。
利用干法刻蚀，从顶层刻蚀到底层，将位于所述寄生MOS区域300的通孔K1的侧壁的半导体层23和栅极绝缘层24完全刻蚀掉。
步骤112，形成栅电极26。
在一些示例中，形成栅电极26包括：在所述通孔K1内沉积栅电极薄膜，形成所述栅电极26，所述栅电极26填充所述通孔K1，如图1A所示。
在一示例性实施例中，可以通过ALD沉积所述栅电极薄膜。
在一示例性实施例中，所述栅电极薄膜可以包括但不限于以下至少之一：氧化铟锡(Indium Tin Oxide，ITO)、TiN/W、掺铝氧化锌(Aluminum doped Zinc Oxide，AZO)，氧化铟锌(Indium Zinc Oxide，IZO)。
步骤113，刻蚀去除图案化叠层结构位于存储单元一侧的部分，形成通孔K2，在所述通孔K2内沉积导电薄膜，使导电薄膜形成检测引脚61，检测引脚61与每层所述存储单元的位线30电连接，如图1B所示。
本实施例提供的方案，通过一次构图工艺，同时形成图案化叠层结构和通孔K1，简化了工艺流程，易于实施，提高生产效率，具有易于工艺实现、生产成本低和良品率高等优点。
本公开实施例还提供了一种电子设备，包括前述任一实施例所述的半导体器件。所述电子设备可以为：存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源等。存储装置可以包括计算机中的内存等，此处不作限定。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (13)

  1. 一种半导体器件的制造方法，所述半导体器件包括多层沿垂直于衬底的方向堆叠的存储单元、沿垂直于所述衬底方向延伸的字线，所述存储单元包括：晶体管和电容，所述晶体管包括第一电极、第二电极、沿垂直于所述衬底的方向延伸的栅电极、环绕所述栅电极且与所述栅电极相绝缘的半导体层，所述电容包括第一极板和第二极板；所述半导体器件的制造方法包括：
    提供衬底，在所述衬底上依次交替沉积第一绝缘薄膜和导电薄膜，形成叠层结构；
    通过一次构图工艺，使所述叠层结构形成图案化叠层结构，以及形成通孔；所述图案化叠层结构包括依次交替设置的图案化导电层和图案化绝缘层；所述通孔在垂直于所述衬底的方向上贯穿所述图案化叠层结构，所述通孔的侧壁露出所述图案化导电层和所述图案化绝缘层，所述通孔配置为容纳所述字线。
  2. 根据权利要求1所述的半导体器件的制造方法，其中，所述通过一次构图工艺，使所述叠层结构形成图案化叠层结构，以及形成通孔，包括：通过一个膜层上的掩膜图形，对所述叠层结构进行构图工艺，使所述叠层结构形成图案化叠层结构，以及形成通孔；所述掩膜图形为同时具有架构和孔结构的图形。
  3. 根据权利要求2所述的半导体器件的制造方法，其中，所述膜层为光刻胶。
  4. 根据权利要求2所述的半导体器件的制造方法，其中，所述膜层为硬掩膜层。
  5. 根据权利要求1至4中任一项所述的半导体器件的制造方法，还包括：
    形成填满所述通孔的第一牺牲层；
    形成环绕所述图案化叠层结构侧壁的填充层；
    去除部分所述填充层以及部分所述图案化绝缘层，将部分所述图案化导电层暴露，使暴露的所述图案化导电层作为所述第一极板，在去除所述填充层和所述图案化绝缘层的区域形成所述第二极板；
    刻蚀去除所述第一牺牲层；
    在平行于所述衬底的平面上，朝远离所述通孔的方向刻蚀所述图案化导电层，所述通孔使得所述图案化导电层形成彼此分离的第一电极和第二电极；
    在所述通孔的侧壁依次沉积相互绝缘的半导体薄膜和栅电极薄膜，形成所述半导体层、所述栅电极和所述字线。
  6. 根据权利要求5所述的半导体器件的制造方法，其中，所述形成填满所述通孔的第一牺牲层包括：
    在所述衬底上沉积第一牺牲层薄膜，所述第一牺牲层薄膜覆盖所述衬底的部分表面、覆盖所述图案化叠层结构的侧面和上表面以及将所述通孔填满；
    对所述第一牺牲层薄膜进行构图工艺，将覆盖所述衬底表面的第一牺牲层薄膜以及覆盖所述图案化叠层结构的侧面和上表面的第一牺牲层薄膜去除，保留将所述通孔填满的第一牺牲层薄膜，形成所述第一牺牲层。
  7. 根据权利要求5所述的半导体器件的制造方法，所述形成环绕所述图案化叠层结构侧壁的填充层之后，所述制造方法还包括：研磨所述填充层的表面，使所述填充层远离所述衬底一侧的表面与所述图案化叠层结构远离所述衬底一侧的表面平齐。
  8. 根据权利要求5所述的半导体器件的制造方法，所述去除部分所述填充层以及部 分所述图案化绝缘层，将部分所述图案化导电层暴露，使暴露的所述图案化导电层作为第一极板，在去除所述填充层和所述图案化绝缘层的区域形成第二极板之前，所述制造方法还包括：
    去除所述膜层图案至少一侧的所述填充层以及所述图案化绝缘层，将所述图案化导电层的一端暴露；
    在暴露的所述图案化导电层的一端上形成支撑层，所述支撑层包括固定槽，所述固定槽将暴露的所述图案化导电层的一端固定。
  9. 根据权利要求8所述的半导体器件的制造方法，其中，所述支撑层包括绝缘材料。
  10. 一种根据权利要求1至9中任一项所述的半导体器件的制造方法制造而成的半导体器件，包括：多层沿垂直于衬底的方向堆叠的存储单元、字线，其中，所述字线沿着垂直于所述衬底的方向延伸且贯穿不同层的所述存储单元；
    所述存储单元包括：晶体管和电容，所述晶体管包括第一电极、第二电极、沿垂直于所述衬底的方向延伸的栅电极、环绕所述栅电极且与所述栅电极相绝缘的半导体层，所述半导体层在所述栅电极的侧壁上延伸形成沿着垂直于所述衬底方向延伸的环形的半导体层；所述电容包括第一极板和第二极板。
  11. 根据权利要求10所述的半导体器件，还包括：支撑层，所述支撑层位于所述第一极板远离所述栅电极的一侧，所述支撑层包括固定槽，所述固定槽的开口朝向所述第一极板的一端，所述第一极板的一端伸入所述固定槽中。
  12. 根据权利要求11所述的半导体器件，其中，所述第二极板位于所述支撑层与所述字线之间，所述第二极板环绕所述第一极板，所述第二极板在所述第一极板的侧壁上延伸形成沿着平行于所述衬底方向延伸的环形。
  13. 一种电子设备，包括如权利要求10至12任一所述的半导体器件。
PCT/CN2023/096885 2023-02-20 2023-05-29 半导体器件及其制造方法、电子设备 Ceased WO2024174403A1 (zh)

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