WO2024159668A1 - 3d堆叠的半导体器件、阵列及其制造方法、电子设备 - Google Patents

3d堆叠的半导体器件、阵列及其制造方法、电子设备 Download PDF

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Publication number
WO2024159668A1
WO2024159668A1 PCT/CN2023/097242 CN2023097242W WO2024159668A1 WO 2024159668 A1 WO2024159668 A1 WO 2024159668A1 CN 2023097242 W CN2023097242 W CN 2023097242W WO 2024159668 A1 WO2024159668 A1 WO 2024159668A1
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Prior art keywords
layer
electrode
semiconductor device
region
stacked
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English (en)
French (fr)
Inventor
桂文华
戴瑾
王桂磊
王祥升
艾学正
毛淑娟
于伟
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a 3D stacked semiconductor device, array, manufacturing method thereof, and electronic device.
  • RAM volatile memory
  • ROM non-volatile memory
  • the traditional known DRAM has multiple repeated "storage cells", each of which has a capacitor and a transistor.
  • the capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively.
  • the transistor is the switch that controls the charging and discharging of the capacitor.
  • the present disclosure provides a 3D stacked semiconductor device, including:
  • Multiple transistors are distributed in different layers and stacked in a direction perpendicular to the substrate;
  • a bit line passing through the transistors of the different layers
  • the transistor includes a first electrode, a second electrode, a gate electrode extending in a direction parallel to a substrate, a semiconductor layer partially surrounding the side wall of the gate electrode so that the semiconductor layer has an opening in a cross section perpendicular to the substrate, and a gate insulating layer arranged between the side wall of the gate electrode and the semiconductor layer.
  • the bit line is disposed on a side of the gate electrode facing the opening of the semiconductor layer, and the bit line is connected to an end of the opening of the semiconductor layer.
  • an isolation layer is disposed between the bit line and the gate electrode, and the isolation layer is connected to the gate insulating layer.
  • the ends of the semiconductor layer include a first end and a second end that are independent of each other, and the semiconductor layer also includes side walls located at the first end and the second end, and the first end and the second end are connected to the bit line.
  • the sidewall of the semiconductor layer includes a first sub-sidewall, a second sub-sidewall, and a third sub-sidewall distributed in sequence, the first electrode is connected to the second sub-sidewall, and the first sub-sidewall and the third sub-sidewall are located between the first electrode and the bit line as a channel of the transistor.
  • the first sub-sidewall and the third sub-sidewall are arranged facing each other.
  • the semiconductor layers of transistors of different layers are disconnected from each other.
  • the gate insulating layers of transistors at different layers are disconnected.
  • the sidewall of the gate electrode includes an upper surface, a lower surface, a first side surface and a second side surface connecting the upper surface and the lower surface and oppositely disposed;
  • the semiconductor layer extends from the upper surface of the gate electrode to the lower surface through the first side surface.
  • the cross section of the semiconductor layer along a direction perpendicular to the substrate and parallel to the first electrode and the bit line arrangement direction is U-shaped, and the cross section along a direction perpendicular to the substrate and parallel to the first electrode and the bit line arrangement direction is two independent lines.
  • the semiconductor device also includes a capacitor, the first electrode is one of the electrodes of the capacitor, the first electrode is connected to the area of the semiconductor layer surrounding the first side surface of the gate electrode, and the second electrode is located on the second side surface of the gate electrode away from the first electrode and is connected to the end face of the U-shaped semiconductor layer.
  • An embodiment of the present disclosure provides a 3D stacked semiconductor device array, comprising: a multi-layer memory cell array, the multi-layer memory cell array comprising a plurality of the above-mentioned 3D stacked semiconductor devices, each layer of the memory cell array comprising a plurality of transistors distributed in an array and a plurality of word lines; each of the word lines corresponds to a plurality of memory cells, and each of the word lines extends in a direction parallel to the substrate, wherein each word line is connected to each transistor in the corresponding plurality of memory cells, and a gate electrode of each of the transistors is a portion of the connected word line.
  • semiconductor layers of multiple transistors connected to the same word line are connected as an integrated structure; or,
  • the semiconductor layers of a plurality of transistors connected to the same word line are disconnected from each other.
  • gate insulation layers of a plurality of transistors connected to a same word line are connected as an integrated structure.
  • the plurality of 3D stacked semiconductor devices include a plurality of bit lines, the plurality of bit lines are arrayed along a first direction and a second direction, the first direction is consistent with an extension direction of the word line, and the second direction is perpendicular to the first direction;
  • the plurality of bit lines correspond one-to-one to different memory cells in the same layer, and the transistors of each memory cell at the same position in different layers are connected to the same bit line;
  • the 3D stacked semiconductor device array also includes: a plurality of bit line selection transistors respectively corresponding to the plurality of bit lines and arranged on a side close to the substrate, and a plurality of common bit lines arranged on a side close to the substrate of the bit line selection transistors, each row of bit lines corresponds to a common bit line, the bit line selection transistors are connected to the corresponding bit lines, the bit lines in the same row are connected to the corresponding common bit lines, and the bit line selection transistors are configured to load the signals of the common bit lines to the corresponding bit lines when turned on.
  • An embodiment of the present disclosure provides an electronic device, comprising any of the 3D stacked semiconductor devices described above, or any of the 3D stacked semiconductor device arrays described above.
  • the present disclosure provides a method for manufacturing a 3D stacked semiconductor device, wherein the 3D stacked semiconductor device comprises a plurality of transistors distributed in different layers and stacked in a direction perpendicular to a substrate; and a bit line running through the transistors in the different layers.
  • the method for manufacturing the 3D stacked semiconductor device comprises:
  • the stacked structure comprises a stack of alternately arranged first insulating layers and conductive layers, wherein the conductive layer comprises a preset electrode pattern; the preset electrode pattern comprises the bit line to be formed and the first electrode of the transistor;
  • a groove is formed by patterning from the top of the stacked structure through the entire conductive layer, the diameter of the groove corresponding to the first region of the conductive layer is larger than the diameter of the groove corresponding to the second region of the first insulating layer, the sidewall of the groove exposes the conductive layer and the first insulating layer, and the groove enables the preset electrode pattern to form a first electrode of the transistor;
  • the first region includes a second sub-region overlapping with the orthographic projection of the second region on the substrate and a first sub-region arranged on a side of the second sub-region facing the first electrode;
  • a through hole is formed in the second region from the top of the stacked structure through all the conductive layers, the through hole exposes the semiconductor layer and the gate insulating layer, and a conductive film filling the through hole is deposited in the through hole to form the bit line.
  • the present disclosure provides a method for manufacturing a 3D stacked semiconductor device array, wherein the 3D stacked semiconductor device array comprises a plurality of 3D stacked semiconductor devices.
  • the body device includes a plurality of transistors distributed in different layers and stacked in a direction perpendicular to the substrate; a bit line runs through the transistors in the different layers, and the manufacturing method of the 3D stacked semiconductor device array includes:
  • the stacked structure comprises a stack of alternately arranged first insulating layers and conductive layers, wherein the conductive layer comprises a plurality of preset electrode patterns; the preset electrode patterns comprise the bit line to be formed and the first electrode of the transistor;
  • a groove is formed by patterning and penetrating all the conductive layers from the top of the stacked structure, wherein the diameter of the groove corresponding to the first region of the conductive layer is larger than the diameter of the groove corresponding to the second region of the first insulating layer, and the sidewall of the groove exposes each of the preset electrode patterns and the first insulating layer, and the groove enables the plurality of preset electrode patterns to respectively form the first electrodes of transistors in the same layer of the plurality of 3D stacked semiconductor devices;
  • the first region includes a second sub-region overlapping with the orthographic projection of the second region on the substrate and a first sub-region arranged on a side of the second sub-region facing the first electrode;
  • a plurality of through holes arranged at intervals are formed in the second region from the top of the stacked structure through all the conductive layers, the through holes exposing the semiconductor layer and the gate insulating layer, and a conductive film filling the through holes is deposited in the through holes to form the bit lines.
  • FIG1A is a schematic cross-sectional view of a 3D stacked semiconductor device provided by an exemplary embodiment along a direction perpendicular to a substrate;
  • 1B is a schematic cross-sectional view of a 3D stacked semiconductor device provided by an exemplary embodiment along a direction parallel to a substrate;
  • FIG2 is a cross-sectional schematic diagram of a stacked structure provided by an exemplary embodiment
  • FIG3A is a schematic diagram along the C direction after a preset electrode pattern is formed, provided by an exemplary embodiment
  • FIG3B is a schematic diagram of the semiconductor device shown in FIG3A along the aa′ direction;
  • FIG3C is a schematic diagram of the semiconductor device shown in FIG3A along the bb′ direction;
  • FIG4A is a schematic diagram of an exemplary embodiment provided along the C direction after exposing the first pole
  • FIG4B is a schematic diagram of the semiconductor device shown in FIG4A along the aa′ direction;
  • FIG5A is a schematic diagram of an exemplary embodiment provided along the C direction after a capacitor is formed
  • FIG5B is a schematic diagram of the semiconductor device shown in FIG5A along the aa′ direction;
  • 6A is a schematic diagram along the C direction after etching the second conductive portion and the bit line region provided by an exemplary embodiment
  • FIG6B is a schematic diagram of the semiconductor device shown in FIG6A along the aa′ direction;
  • FIG. 7A is a schematic diagram along the C direction after a capacitor is formed, provided by an exemplary embodiment
  • FIG7B is a schematic diagram of the semiconductor device shown in FIG7A along the C' direction;
  • FIG7C is a schematic diagram of the semiconductor device shown in FIG7A along the aa′ direction;
  • FIG8A is a schematic diagram along the C direction after etching the bit line region provided by an exemplary embodiment
  • FIG8B is a schematic diagram of the semiconductor device shown in FIG8A along the aa′ direction;
  • FIG9 is a schematic diagram of a gate electrode along the aa' direction after partial etching provided by an exemplary embodiment
  • FIG10 is a schematic diagram along the aa′ direction after a gate insulating film is deposited in an etched region of a gate electrode, provided by an exemplary embodiment
  • FIG. 11A is a schematic diagram along the C direction after forming a through hole provided by an exemplary embodiment
  • FIG11B is a schematic diagram of the semiconductor device shown in FIG11A along the aa′ direction;
  • FIG12A is a schematic diagram along the C direction after forming a bit line provided by an exemplary embodiment
  • FIG12B is a schematic diagram of the semiconductor device shown in FIG12A along the aa′ direction;
  • FIG. 13 is a schematic diagram of a semiconductor device array provided by an exemplary embodiment.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • a channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in the present disclosure, the "source electrode” and the “drain electrode” may be interchanged.
  • connection includes the case where components are connected together through an element having some kind of electrical function.
  • element having some kind of electrical function there is no particular limitation on the "element having some kind of electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • Examples of “element having some kind of electrical function” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°.
  • perpendicular means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.
  • the "A and B are arranged in the same layer" mentioned in the present disclosure includes film layers formed of the same material or different materials located on the same film layer.
  • a and B are formed by forming the same film layer with the same material and then undergoing the same patterning process or different patterning processes.
  • a and B arranged in the same layer may be located on the same horizontal plane but not necessarily on the same film layer, or located in different regions of the same film layer but not necessarily on the same horizontal plane.
  • the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the exemplary embodiments of the present disclosure provide a novel 3D stacked semiconductor device, which may include a word line and a semiconductor layer extending in a horizontal direction, and a bit line extending in a vertical direction, wherein the word line and the semiconductor layer are arranged in a lateral groove between insulating layers, and the semiconductor layer surrounds the sidewall of the word line on three sides.
  • the end surface of the semiconductor layer is connected to the bit line to form a double-sided channel structure.
  • the bit line can be connected to the semiconductor layer near the middle area of the three-sided semiconductor layer, and other circuits or capacitors are connected to the end surface of the semiconductor layer.
  • FIG1A is a schematic cross-sectional view of a 3D stacked semiconductor device provided by an exemplary embodiment along a direction perpendicular to a substrate.
  • FIG1B is a schematic cross-sectional view of a 3D stacked semiconductor device provided by an exemplary embodiment along a direction parallel to a substrate.
  • the 3D stacked semiconductor device provided by this embodiment may include:
  • a plurality of transistors are distributed in different layers and stacked in a direction perpendicular to a substrate (the substrate is not shown in FIGS. 1A and 1B );
  • the transistor includes a horizontal transistor relative to the substrate, or a lateral transistor, including a first electrode 51 and a second electrode 52 arranged in sequence along the horizontal direction, a channel region between the first electrode 51 and the second electrode 52; a gate electrode 26 extending in a direction parallel to the substrate (horizontal direction), a semiconductor layer 23 partially surrounding the side wall of the gate electrode 26, and a gate insulating layer 24 disposed between the side wall of the gate electrode 26 and the semiconductor layer 23.
  • the semiconductor layer 23 is a hollow structure, and a longitudinal section (a section along a direction perpendicular to the substrate) of the semiconductor layer 23 has an opening.
  • transistors in different layers share the same bit line.
  • the bit line extending in the vertical direction saves space and can form the bit line and the second electrode of each transistor in one process, thereby reducing the number of masks, effectively simplifying the process and reducing costs.
  • the second electrode 52 or the first electrode 51 of each of the transistors may be a portion of the bit line 30 .
  • the bit line 30 may extend in a direction perpendicular to the substrate.
  • the bit line 30 includes a side surface and end surfaces at the upper and lower ends.
  • the side surface is perpendicular to the substrate as a whole. In the actual process of manufacturing products, the area where there may be local bending is also included in the above-mentioned situation of the present application.
  • the side surface of the bit line 30 is connected to the semiconductor layer 23 of the transistor.
  • the bit line 30 may extend in a straight line direction when extending in a direction perpendicular to the substrate.
  • the second electrode 52 extending in the vertical direction of each transistor may be a straight line, and the orthographic projection on the substrate may be at the same position, so that the second electrode 52 of each transistor is connected to form a straight line.
  • the cross-section of the straight bit line along the direction parallel to the substrate may be the same everywhere, or may be different.
  • the embodiment of the present application does not limit the cross-sectional characteristics of the straight line.
  • the cross section of the bit line 30 may be square, circular or other shapes.
  • the gate electrode 26 may extend only in a direction parallel to the substrate.
  • the gate electrode 26 is a part of a word line 40, the word line 40 extends in a direction parallel to the substrate, and the semiconductor layer 23 partially wraps the sidewall of the word line 40 and extends in the direction in which the word line 40 extends.
  • the bit line 30 may be disposed on a side of the gate electrode 26 facing the opening of the semiconductor layer 23, and the bit line 30 may be connected to an end of the opening of the semiconductor layer 23.
  • the bit line 30 may be disposed on a side of the gate electrode 26 away from the opening of the semiconductor layer 23 , and the semiconductor layer 23 may be connected to a sidewall of the semiconductor layer 23 away from the end.
  • an isolation layer 242 is disposed between the bit line 30 and the gate electrode 26 , and the isolation layer 242 is connected to the gate insulating layer 24 .
  • the gate insulating layer 24 and the isolation layer 242 may be made of different materials.
  • the isolation layer 242 is a low dielectric constant film layer, which can reduce the parasitic capacitance between the bit line 30 and the gate electrode 26.
  • the isolation layer 242 is a Low-K film layer, such as silicon oxide.
  • the gate insulating layer 24 is, for example, a High-k material, such as a dielectric material with a dielectric constant K>3.9. This type of film layer can improve the gate control capability.
  • the High-k material may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2).
  • the gate insulating layer 24 may be integrally disposed between the sidewalls of the gate electrode 26 and the sidewalls of the bit line 30. In a direction perpendicular to the substrate, the cross section of the gate insulating layer 24 may be a closed loop. In this case, the gate insulating layer 24 is located between the gate electrode 26 and the semiconductor layer 23, and between the gate electrode 26 at the opening of the semiconductor layer 23 and the bit line 30. The gate insulating layer 24 may be formed in one process, thereby simplifying the process flow.
  • the semiconductor layer 23 may include two main surfaces and end surfaces between the main surfaces; the end surfaces include end surfaces facing the bit line 30 or the capacitor, such as the first end 231 and the second end 232 in FIG. 1A, wherein one of the main surfaces is an outer surface, such as the side wall 233 connecting the first end 231 and the second end 232 in FIG. 1A.
  • the first end 231 and the second end 232 are connected to the bit line 30.
  • the semiconductor layer 23 surrounds the gate electrode 26 along the direction from the first end 231 to the second end 232. In this embodiment, the semiconductor layer 23 partially surrounds the gate electrode 26, which can be understood as not completely surrounding the gate electrode, but surrounding a portion of the sidewall of the gate electrode 26. In some embodiments, the semiconductor layer 23 can surround the gate electrode 26. Around at least half of the circumference of the gate electrode 26. In some embodiments, it can surround three side walls of the gate electrode 26. It can be understood that the cross section of the semiconductor layer 23 is a ring with an opening along the direction perpendicular to the substrate and parallel to the extension direction of the gate electrode 26.
  • the first end 231 can be an end face
  • the second end 232 can be another end face independent of the first end 231.
  • an orthographic projection of the first end portion 231 on the substrate and an orthographic projection of the second end portion 232 on the substrate may overlap.
  • the material composition of different regions of the bit line 30 extending in a direction perpendicular to the substrate is the same, which can be understood as being formed using the same film manufacturing process.
  • the same material composition can be understood as the same main elements tested in the material, for example, they are all made of transparent conductive materials such as metal or ITO, but the atomic number ratio of different regions is not limited.
  • the sidewall 233 of the semiconductor layer may only include a first sub-sidewall 233_1, a second sub-sidewall 233_2, and a third sub-sidewall 233_3 that are sequentially and continuously distributed, and the first electrode 51 is connected to the second sub-sidewall 233_2, for example, the first electrode 51 is in contact with the second sub-sidewall 233_2.
  • the solution provided in this embodiment is a double-sided channel, one side is the first sub-sidewall 233_1, and the other side is the third sub-sidewall 233_3.
  • the first sub-sidewall 233_1 and the third sub-sidewall 233_3 may be disposed opposite to each other and may be upper and lower sidewalls relative to the substrate.
  • a surface of the first sub-sidewall 233_1 away from the substrate may be parallel to the substrate; and a surface of the third sub-sidewall 233_3 close to the substrate may be parallel to the substrate.
  • the semiconductor layers 23 of transistors at different layers may be disconnected, which may be understood as being physically not in contact with each other, or may be electrically insulated.
  • the gate insulating layers 24 of transistors at different layers may be disconnected.
  • a surface of the first electrode 51 facing the bit line 30 may be recessed toward a side away from the bit line 30 .
  • the sidewall of the gate electrode 26 may include an upper surface (a surface away from the substrate), a lower surface (a surface close to the substrate) and two side surfaces, the two side surfaces are respectively referred to as a first side surface and a second side surface; the first side surface and the second side surface connect the upper surface and the lower surface and are arranged opposite to each other;
  • the semiconductor layer 23 may extend from the upper surface of the gate electrode 26 through the first side surface to the lower surface.
  • the cross section of the semiconductor layer 23 (taken in parallel with the substrate direction) is a line; the cross section taken along the direction perpendicular to the substrate and perpendicular to the extension direction of the gate electrode 26 may be U-shaped.
  • the cross section taken along the direction perpendicular to the substrate and parallel to the extension direction of the gate electrode 26 may be two independent Alternatively, the cross section of the semiconductor layer 23 along the direction perpendicular to the substrate and parallel to the arrangement direction of the first electrode 51 and the bit line 30 is U-shaped, and the cross section along the direction perpendicular to the substrate and perpendicular to the arrangement direction of the first electrode 51 and the bit line 30 is two independent lines.
  • the arrangement direction of the first electrode 51 and the bit line 30 may be perpendicular to the extension direction of the gate electrode 26.
  • the extension direction of the gate electrode 26 is the second direction Y
  • the first direction X is perpendicular to the second direction Y, that is, the cross section taken along the first direction X may be U-shaped.
  • the semiconductor device may further include a capacitor, and the first electrode 51 or the second electrode 52 is one of the electrodes of the capacitor.
  • the first electrode 51 is connected to the region of the semiconductor layer 23 surrounding the first side surface of the gate electrode 26 (i.e., connected to the second sub-sidewall 233_2), and the second electrode 52 is located on the second side surface of the gate electrode 26 away from the first electrode 51, and is connected to the end surface of the U-shaped semiconductor layer 23.
  • the semiconductor layer 23 is U-shaped, and the end surface of the semiconductor layer 23 is the surface at the opening of the U-shape, i.e., the first end 231 and the second end 232.
  • the orthographic projections of the first electrodes 51 of the transistors of different layers may overlap.
  • the overlapping orthographic projections of the first electrodes 51 can make the 3D stacked semiconductor device compact, and electrodes of different layers can be manufactured at one time during manufacturing, which simplifies the process.
  • the orthographic projections of the semiconductor layer 23 or the gate insulating layer 24 or the gate electrode 26 of the transistors of different layers may overlap.
  • the orthographic projections of the semiconductor layer 23 or the gate insulating layer 24 or the gate electrode 26 overlap, which can make the 3D stacked semiconductor device compact.
  • An embodiment of the present disclosure provides a 3D stacked semiconductor device array, which may include: a plurality of 3D stacked semiconductor devices as described in any of the above embodiments, and a word line 40 extending in a direction parallel to the substrate, wherein the plurality of 3D stacked semiconductor devices may be distributed in a direction parallel to the substrate, and the gate electrodes 26 of transistors in the same layer of the plurality of 3D stacked semiconductor devices are part of the word line 40.
  • the semiconductor layers 23 of the transistors in the same layer of the multiple 3D stacked semiconductor devices are connected as an integrated structure, or the semiconductor layers 23 of the transistors in the same layer of the multiple 3D stacked semiconductor devices are disconnected from each other.
  • the semiconductor layers 23 when the semiconductor layers 23 are connected as an integrated structure, the semiconductor layers of multiple transistors in the same layer can be formed through a single manufacturing process, and the process is simple.
  • the gate insulating layers 24 of transistors in the same layer of the plurality of 3D stacked semiconductor devices are connected into an integrated structure.
  • the solution provided in this embodiment can form the gate insulating layers of multiple transistors in the same layer through a single preparation process, which is simple in process.
  • the word line 40 extends in a direction parallel to the substrate and may be along
  • the gate electrode 26 extending horizontally of each transistor may be a straight line, and its orthographic projection on a plane perpendicular to the substrate may be at the same position, so that the gate electrodes 26 of each transistor in the same layer are connected to form a straight word line 40 .
  • the cross section of the linear word line 40 along the direction perpendicular to the substrate may be the same everywhere, or may be different.
  • the embodiment of the present application does not limit the cross section characteristics of the straight line.
  • An embodiment of the present disclosure provides a 3D stacked semiconductor device array, comprising: a multi-layer memory cell array, wherein the multi-layer memory cell array includes a plurality of the above-mentioned 3D stacked semiconductor devices, each layer of the memory cell array includes a plurality of memory cells, and a plurality of word lines 40, each memory cell includes a transistor; each of the word lines 40 corresponds to a plurality of memory cells in the layer where the word line 40 is located, and each of the word lines 40 extends in a direction parallel to the substrate, wherein each word line 40 is connected to each transistor in the corresponding plurality of memory cells, and the gate electrode 26 of each of the transistors is a portion of the connected word line 40.
  • the plurality of word lines 40 in the same layer may be parallel.
  • the semiconductor layers 23 of multiple transistors connected to the same word line 40 are connected as an integrated structure; or,
  • the semiconductor layers 23 of the plurality of transistors connected to the same word line 40 are disconnected from each other.
  • the gate insulating layers 24 of multiple transistors connected to the same word line 40 may be connected into an integrated structure.
  • the isolation layers 242 of multiple transistors connected to the same word line 40 may be connected as an integrated structure.
  • the plurality of 3D stacked semiconductor devices include a plurality of bit lines 30, the plurality of bit lines 30 are arrayed along a first direction X and a second direction Y, the second direction is consistent with an extension direction of the word line 40, the first direction X is perpendicular to the second direction Y; the first direction X is a row direction, the second direction Y is a column direction, a row of bit lines 30 is distributed along the first direction X, and a column of bit lines 30 is distributed along the second direction;
  • the plurality of bit lines 30 correspond one-to-one to different memory cells in the same layer, and the transistors of each memory cell at the same position in different layers are connected to the same bit line 30 .
  • the 3D stacked semiconductor device array may further include: a plurality of bit line selection transistors 300 corresponding to the plurality of bit lines 30, and a plurality of common bit lines 200 arranged on the side of the bit line selection transistors 300 close to the substrate, each row of bit lines 30 corresponding to a common bit line 200, the bit line selection transistors 300 are respectively connected to the corresponding bit lines 30, the bit line selection transistors 300 connected to the bit lines 30 in the same row are connected to the corresponding common bit lines 200, and the bit line selection transistors 300 are configured to load the signals of the common bit lines 200 to the corresponding bit lines 30 when turned on, thereby realizing the selection of the bit lines 30.
  • the bit line selection transistors 300 may correspond one-to-one to the bit lines 30, but Without being limited thereto, a plurality of bit lines 30 may be connected to the same bit line gate transistor 300 .
  • the bit line selection transistor 300 may be disposed on a side of the bit line 30 close to the substrate.
  • the present disclosure is not limited thereto, and the bit line selection transistor 300 may be disposed on a side of the bit line 30 far from the substrate.
  • the common bit line 200 may be disposed on a side of the bit line selection transistor 300 close to the substrate.
  • the disclosed embodiment is not limited thereto, and the common bit line 200 may be disposed on a side of the bit line selection transistor 300 far from the substrate.
  • the 3D stacked semiconductor device can form a 1T1C storage structure with a capacitor, or form a 2T0C storage structure with other transistors, etc. 1T1C is used as an example for description.
  • an embodiment of the present disclosure provides a 3D memory, including: the above-mentioned 3D stacked semiconductor device, and may further include: a data storage element.
  • the data storage element is, for example, a capacitor, that is, a 1T1C storage structure is formed.
  • the embodiments of the present disclosure are not limited thereto, and other transistors may be combined to form a 2T0C storage structure, and so on.
  • the capacitor may include a first pole 41 and a second pole 42 , wherein the first pole 41 is connected to the first electrode 51 .
  • the first pole 41 and the first electrode 51 may be connected into an integrated structure.
  • the second electrodes 42 of the capacitors in the same column of different layers can be connected as an integrated structure. As shown in FIG1A , the second electrodes 42 of the capacitors in the first column of different layers are connected as an integrated structure. The second electrodes 42 of the capacitors in the second column of different layers are connected as an integrated structure, that is, the capacitors in the same column of different layers share the same electrode as the second electrode 42.
  • the capacitor may further include a second insulating layer 13 disposed between the first electrode 41 and the second electrode 42.
  • the second insulating layer 13 serves as a medium between the first electrode 41 and the second electrode 42.
  • the second insulating layer 13 of the capacitors in the same column of different layers can be connected as an integrated structure. As shown in FIG1A , the second insulating layer 13 of the capacitors in the first column of different layers is connected as an integrated structure. The second insulating layer 13 of the capacitors in the second column of different layers is connected as an integrated structure, that is, the capacitors in the same column of different layers share the same insulating layer as a medium between electrodes.
  • a transistor and a data storage element constitute a memory cell.
  • the memory cells in the same layer form an array distributed along a first direction X and a second direction Y, respectively, and each layer of the memory cells further includes: a word line 40.
  • FIG1B shows that each layer includes four rows and two columns of memory cells, but the embodiments of the present disclosure are not limited thereto, and each layer may include memory cells of other numbers of rows and columns, for example, may include only one memory cell.
  • the first direction X may be parallel to the first direction X.
  • the first direction X and the second direction Y may be parallel to the substrate, and the first direction X and the second direction Y may intersect. In some embodiments, the first direction X and the second direction Y may be perpendicular.
  • the gate electrodes 26 of the transistors of the memory cells in the same layer and the same column are connected to form the word line 40. That is, the gate electrodes 26 of the transistors of the memory cells in the same layer and the same column are part of the word line 40.
  • the word line 40 may extend along the second direction Y. As shown in FIG.
  • the first electrode 51 may extend along a first direction X.
  • the first direction X and the second direction Y may be perpendicular.
  • the technical solution of this embodiment is further explained below through the preparation process of the semiconductor device of this embodiment.
  • the "patterning process” mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature preparation process in the relevant technology.
  • the "photolithography process” mentioned in this embodiment includes coating of film layer, mask exposure and development, which is a mature preparation process in the relevant technology.
  • Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here.
  • thin film refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film” does not require a patterning process or a photolithography process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” still requires a patterning process or a photolithography process during the entire production process, it is called a “thin film” before the patterning process and a "layer” after the patterning process. The "layer” after the patterning process or the photolithography process contains at least one "pattern".
  • a manufacturing process of a 3D stacked semiconductor device may include:
  • a first insulating film 9 and a first conductive film 11 are alternately deposited on a substrate to form a laminated structure, as shown in FIG2 , wherein FIG2 is a cross-sectional view along a direction perpendicular to the substrate.
  • the substrate is not shown in FIG2 .
  • the substrate is disposed at the bottom of the film layer shown in FIG2 .
  • the first insulating film 9 may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K ⁇ 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.
  • the first conductive film 11 may be made of the following conductive materials:
  • it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;
  • it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);
  • it may be polysilicon material, conductive doped semiconductor material, etc., for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that embody conductivity, etc.
  • the first conductive film 11 may include but is not limited to titanium nitride (TiN), Tungsten (W), metal oxide conductive layer, such as ITO, etc., single layer or multi-layer structure.
  • the stacked structure shown in FIG. 2 includes five layers of first insulating films 9 and four layers of first conductive films 11 , which is only an example. In other embodiments, the stacked structure may include more or fewer layers of first insulating films 9 and first conductive films 11 that are alternately arranged.
  • FIG. 3A is a schematic cross-sectional view of the 3D stacked semiconductor device along the C direction
  • Figure 3B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in Figure 3A along the aa’ direction
  • Figure 3C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in Figure 3A along the bb’ direction, wherein the C direction is parallel to the substrate, the aa’ direction is perpendicular to the substrate, the bb’ direction is perpendicular to the substrate, and the aa’ direction and the bb’ direction may be perpendicular.
  • the step of patterning the stacked structure to form a stacked structure including a conductive layer 12 and a first insulating layer 10 may include:
  • the stacked structure is etched by dry etching to form a groove, and after patterning the conductive layer 12, an insulating film is filled in the groove area to isolate different devices;
  • the conductive layer 12 may include a preset electrode pattern, as shown in FIG3A, the preset electrode pattern may include a first conductive portion 121 and a second conductive portion 122, wherein the first conductive portion 121 may extend along a first direction X, and the second conductive portion 122 may extend along a second direction Y, wherein the preset electrode pattern shown in FIG3A is only an example, and the preset electrode pattern may be other shapes.
  • the first conductive film 11 of the bit line region 200 is removed to facilitate the subsequent formation of multiple bit lines extending along the substrate direction in this region.
  • the insulating film may be deposited by chemical vapor deposition (CVD).
  • the insulating film and the first insulating film 9 may be made of the same material, or different materials. Both may be Low-K materials. The following description will be made by taking the insulating film and the first insulating film 9 as an example.
  • the exposing the first pole 41 may include: after filling the insulating film, using dry etching to etch from the top layer to the bottom layer to form a groove, the groove is formed by removing the first insulating layer between two adjacent groups of storage cells, that is, removing the first insulating film between two adjacent groups of capacitor regions 100, and then using wet etching in the groove to laterally etch the first insulating layer 10 exposed in the interlayer groove through an acid solution, etching a preset length to expose a partial area of the first conductive part 121 to obtain the first pole 41, that is, exposing the end face of the first conductive part 121 and a portion of the side wall adjacent to the end face, as shown in Figures 4A and 4B, wherein Figure 4A is a cross-sectional schematic diagram of a 3D stacked semiconductor device along the C direction, and Figure 4B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 4A along the aa’ direction.
  • the forming of the second insulating layer 13 and the second electrode 42 may include: A second insulating film and a conductor material are deposited to form a second insulating layer 13 and a second electrode 42, respectively.
  • the second insulating layer 13 covers the exposed area of the conductive layer 12, as shown in Figures 5A and 5B, wherein Figure 5A is a cross-sectional schematic diagram of the 3D stacked semiconductor device along the C direction, and Figure 5B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 5A along the aa' direction.
  • the second insulating layer 13 serves as a medium between the capacitor electrodes, and the second electrode 42 serves as an electrode of the capacitor.
  • the second insulating film and the conductor material can be deposited by atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the second insulating film may be a High-K dielectric material, i.e., a dielectric material with a dielectric constant K ⁇ 3.9.
  • it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc.
  • it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.
  • the conductor material includes but is not limited to at least one of the following: metal, metal alloy, polysilicon, silicon-doped conductive layer, and metal oxide conductive layer.
  • the second electrode 42 may be a plate-shaped structure extending in a direction perpendicular to the substrate, and is connected to the first electrode of the capacitor of each layer of storage cells exposed by the trench through an insulating layer to form a common electrode plate.
  • TiN or the like may be deposited in the capacitor region 100, and together with the electrode exposed by the conductive layer 12, serve as the first electrode 41 of the capacitor, that is, an adhesive film layer such as TiN is provided between the first electrode 41 and the second insulating layer 13 to enhance the adhesion between the first electrode 41 and the second insulating layer 13.
  • the adhesive film layer covers the exposed region of the conductive layer 12, and the adhesive film layers attached to the conductive layers 12 of different layers are disconnected, that is, after depositing the adhesive film layer, before depositing the second insulating film, the adhesive film layer may be etched to disconnect the adhesive film layers attached to the conductive layers 12 of different layers.
  • the first insulating film in the stacked structure located in the bit line region 200 is removed by etching, and the second conductive portion 122 is removed to form a trench.
  • the etching to remove the first insulating film located in the bit line region 200 and the removal of the second conductive film 122 may include: etching away all the first insulating film filling the bit line region 200 from the top layer to the bottom layer by dry etching; and, by wet etching, by selecting an acid solution with a high selectivity ratio between the first insulating film and the first conductive film, the second conductive parts 122 on both sides of the bit line region 200 are laterally etched, while the first insulating film is basically not etched.
  • the first conductive part 121 may be lost, that is, a part of the first conductive part 121 is etched away, so as to ensure that each horizontal second conductive part 122 film on both sides of the middle bit line region 200 is completely etched.
  • a horizontal U-shaped groove will be formed between any adjacent first insulating films (such as interlayer SiO2).
  • Figure 6A is a schematic cross-sectional view of a 3D stacked semiconductor device along the C direction
  • Figure 6B is a cross-sectional view of the 3D stacked semiconductor device shown in Figure 6A along the aa' direction. Schematic diagram.
  • the formation of the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26 may include: sequentially depositing a semiconductor film, a gate insulating film and a gate electrode film on the U-shaped groove area formed by etching in step 5) and the sidewall of the entire groove, and sequentially forming the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26, as shown in Figures 7A, 7B and 7C, wherein Figure 7A is a schematic cross-sectional view of the 3D stacked semiconductor device along the C direction, Figure 7B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in Figure 7A along the C' direction, and Figure 7C is a schematic cross-sectional view of the 3D stacked semiconductor device shown in Figure 7A along the aa' direction. The C' direction is parallel to the substrate.
  • the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26 are located in the entire U-shaped groove, and the U-shaped groove corresponds to a column of memory cells in a two-dimensional plane.
  • the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26 in each U-shaped groove in the same groove are connected.
  • the material of the semiconductor layer 23 may be silicon or polysilicon with a band gap less than 1.65 eV, or may be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.
  • the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc.
  • the metal oxide does not exclude compounds containing other elements, such as N, Si, etc., nor does it exclude the presence of other small amounts of doping elements.
  • the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide
  • the metal oxide material is IGZO
  • the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the operating performance of the dynamic memory.
  • the material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.
  • the material of the gate insulating layer 24 may include one or more layers of High-K dielectric material, such as a dielectric material with a dielectric constant K ⁇ 3.9. It may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.
  • HfO2O2O3 hafnium aluminum oxide
  • HfAlO hafnium aluminum oxide
  • HfLaO hafnium lanthanum oxide
  • ZrO2 zirconium oxide
  • the gate insulating film may have a thickness of 10 nm to 15 nm.
  • the gate electrode film may be one or more of the following different types of materials.
  • it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;
  • it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);
  • it may be polysilicon material, conductive doped semiconductor material, etc., for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that embody conductivity, etc.
  • the gate electrode film includes but is not limited to at least one of the following: tin-doped indium oxide (Indium Tin Oxide, ITO), titanium nitride/tungsten (TiN/W), aluminum-doped zinc oxide (Al-doped ZnO, AZO), and indium-doped zinc oxide (Indium Zinc Oxide, IZO).
  • the etching and removal of the semiconductor film, gate insulating film and gate electrode film located in the bit line region 200 may include: removing the semiconductor film, gate insulating film and gate electrode film located in the bit line region 200 by dry etching, as shown in Figures 8A and 8B, wherein Figure 8A is a schematic cross-sectional view of the 3D stacked semiconductor device along the C direction, and Figure 8B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in Figure 8A along the aa' direction.
  • Figure 8A is a schematic cross-sectional view of the 3D stacked semiconductor device along the C direction
  • Figure 8B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in Figure 8A along the aa' direction.
  • the etching of the gate electrode 26 includes: etching the gate electrode 26 to a preset thickness, such as 5nm to 10nm, in a direction away from the bit line region 200 to prevent the subsequently formed bit line from contacting the gate electrode 26, as shown in Figure 9, wherein Figure 9 is a cross-sectional schematic diagram of the 3D stacked semiconductor device along the aa’ direction.
  • a fourth insulating film is deposited in the bit line region 200 and in the region where the gate electrode 26 is etched, and the fourth insulating film in the bit line region 200 is removed by etching, while the fourth insulating film in the region where the gate electrode 26 is etched is retained to form an isolation layer 242.
  • the gate electrode 26 and the subsequently formed bit line are isolated by the isolation layer 242, as shown in FIG. 10 , which is a schematic cross-sectional view of the 3D stacked semiconductor device along the aa’ direction.
  • the fourth insulating film may include one or more layers of High-K dielectric material, such as The gate insulating film is consistent, or the fourth insulating film can be a Low-K material, such as silicon oxide.
  • the forming of the through hole K1 includes: depositing a third insulating film filling the bit line region 200 in the bit line region 200, etching the third insulating film to form a plurality of through holes K1, the sidewalls of the through holes K1 exposing the gate insulating layer 24 and the semiconductor layer 23, as shown in FIG11A and FIG11B, wherein FIG11A is a schematic cross-sectional view of a 3D stacked semiconductor device along the C direction, and FIG11B is a schematic cross-sectional view of the 3D stacked semiconductor device shown in FIG11A along the aa' direction.
  • Different through holes K1 are isolated by the third insulating film.
  • the orthographic projection of the through hole K1 may be a square, but the embodiments of the present disclosure are not limited thereto, and the orthographic projection of the through hole K1 may be a circle or the like.
  • bit line 30
  • the forming of the bit line 30 may include: depositing a second conductive film filling the through hole K1 in the through hole K1 to form the bit line 30, as shown in Figures 12A and 12B, wherein Figure 12A is a cross-sectional schematic diagram of the 3D stacked semiconductor device along the C direction, and Figure 12B is a cross-sectional schematic diagram of the 3D stacked semiconductor device shown in Figure 12A along the aa’ direction.
  • bit line material may be one or more of the following different types of materials:
  • it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;
  • it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO, etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;
  • it may be polysilicon material, conductive doped semiconductor material, etc., for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that embody conductivity, etc.
  • the second conductive film includes but is not limited to transparent conductive oxides such as ITO and IZO or other conductive materials.
  • FIG13 is a schematic cross-sectional view of a 3D stacked semiconductor device array provided by another exemplary embodiment along a direction perpendicular to the substrate.
  • the 3D stacked semiconductor device array provided by this embodiment may include multiple rows and columns of memory cells distributed in an array, and the memory cells may include transistors and capacitors. In the direction perpendicular to the substrate, two adjacent columns of memory cells form a group, and memory cells in different rows of the same group may share a bit line 30, and two adjacent groups of memory cells may share an electrode as a second electrode 42.
  • the 3D stacked semiconductor device array may also include a bit line selection transistor 300 corresponding to the bit line 30, and a plurality of common bit lines 200, one of which is a common bit line 200.
  • the bit line selection transistor 300 connected to the bit line 30 of the same row is connected to the corresponding bit line 30.
  • the signal of the common bit line 200 can be loaded or not loaded to the bit line 30, so as to realize the gating of the bit line 30.
  • the present disclosure also provides an electronic device, including the 3D stacked semiconductor device or 3D stacked semiconductor device array described in the above embodiment.
  • the electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
  • the storage device may include a memory in a computer, etc., which is not limited here.
  • the present disclosure provides a method for manufacturing a 3D stacked semiconductor device, wherein the 3D stacked semiconductor device comprises a plurality of transistors distributed in different layers and stacked in a direction perpendicular to a substrate; and a bit line running through the transistors in the different layers.
  • the method for manufacturing the 3D stacked semiconductor device comprises:
  • the stacked structure comprises a stack of alternately arranged first insulating layers and conductive layers, wherein the conductive layer comprises a preset electrode pattern; the preset electrode pattern comprises the bit line to be formed and the first electrode of the transistor;
  • a groove is formed by patterning and penetrating all the conductive layers from the top of the stacked structure, wherein the diameter of the groove corresponding to the first region of the conductive layer is larger than the diameter of the groove corresponding to the second region of the first insulating layer, the sidewall of the groove exposes the conductive layer and the first insulating layer, and the groove enables the preset electrode pattern to form a first electrode of the transistor;
  • the first region includes a second sub-region overlapping with the orthographic projection of the second region on the substrate and a first sub-region arranged on a side of the second sub-region facing the first electrode;
  • a through hole is formed in the second region from the top of the stacked structure through all the conductive layers, the through hole exposes the semiconductor layer and the gate insulating layer, and a conductive film filling the through hole is deposited in the through hole to form the bit line.
  • the present disclosure provides a method for manufacturing a 3D stacked semiconductor device array, wherein the 3D stacked semiconductor device array includes a plurality of 3D stacked semiconductor devices, wherein the 3D stacked semiconductor devices include a plurality of transistors distributed in different layers and stacked in a direction perpendicular to a substrate; and a bit line running through the transistors in the different layers, including:
  • a substrate on which a first insulating film and a conductive film are alternately deposited in sequence, and patterned to form a stacked structure, wherein the stacked structure comprises a stack of alternately arranged first insulating layers and conductive layers, wherein the conductive layer comprises a plurality of preset electrode patterns; the preset electrode patterns comprise the bit line to be formed and the first electrode of the transistor;
  • a groove is formed by patterning and penetrating all the conductive layers from the top of the stacked structure, wherein the diameter of the groove corresponding to the first region of the conductive layer is larger than the diameter of the groove corresponding to the second region of the first insulating layer, and the sidewall of the groove exposes each of the preset electrode patterns and the first insulating layer, and the groove enables the plurality of preset electrode patterns to respectively form the first electrodes of transistors in the same layer of the plurality of 3D stacked semiconductor devices;
  • the first region includes a second sub-region overlapping with the orthographic projection of the second region on the substrate and a first sub-region arranged on a side of the second sub-region facing the first electrode;
  • a plurality of through holes arranged at intervals are formed in the second region from the top of the stacked structure through all the conductive layers, the through holes exposing the semiconductor layer and the gate insulating layer, and a conductive film filling the through holes is deposited in the through holes to form the bit lines.

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Abstract

一种3D堆叠的半导体器件、阵列及其制造方法、电子设备，所述3D堆叠的半导体器件包括：多个晶体管，分布于不同层沿垂直于衬底方向堆叠；位线(30)，贯穿所述不同层的所述晶体管；所述晶体管包括第一电极(51)，第二电极(52)，沿平行于衬底方向延伸的栅电极(26)，部分环绕所述栅电极侧壁的半导体层(23)，设置在所述栅电极(26)的侧壁和所述半导体层(23)之间的栅极绝缘层(24)。

Description

3D堆叠的半导体器件、阵列及其制造方法、电子设备
本申请要求于2023年1月31日提交中国专利局、申请号为2023101186948、发明名称为“一种3D堆叠的半导体器件、阵列及其制造方法、电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于半导体技术领域的器件设计及其制造，尤指一种3D堆叠的半导体器件、阵列及其制造方法、电子设备。
背景技术
半导体存储从应用上可划分为易失性存储器(RAM，包括DRAM和SRAM等)，以及非易失性存储器(ROM和非ROM)。
以DRAM为例，传统已知的DRAM有多个重复的“存储单元”，每个存储单元有一个电容和晶体管。电容可以存储1位数据，充放电后，电容存储电荷的多少可以分别对应二进制数据“1”和“0”。晶体管是控制电容充放电的开关。
为了尽可能降低产品的成本，人们希望在有限的衬底上做出尽可能多的存储单元。自从摩尔定律问世以来，业界提出了各种半导体结构设计和工艺优化，以满足人们对当前产品的需求。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种3D堆叠的半导体器件，包括：
多个晶体管，分布于不同层沿垂直于衬底方向堆叠；
位线，贯穿所述不同层的所述晶体管；
所述晶体管包括第一电极，第二电极，沿平行于衬底方向延伸的栅电极，部分环绕所述栅电极侧壁的半导体层使得所述半导体层在垂直于所述衬底上的截面具有开口，设置在所述栅电极的侧壁和所述半导体层之间的栅极绝缘层。
在一些实施例中，所述位线设置在所述栅电极朝向所述半导体层的开口的一侧，所述位线与所述半导体层的开口的端部连接。在一些实施例中，所述位线与所述栅电极之间设置有隔离层，所述隔离层与所述栅极绝缘层连接。
在一些实施例中，沿所述半导体层的环绕方向，所述半导体层的端部包括相互独立的第一端部、第二端部，所述半导体层还包括位于所述第一端部和第二端部的侧壁，所述第一端部和第二端部与所述位线连接。
在一些实施例中，从所述半导体层的所述第一端部至所述第二端部，所述半导体层的侧壁包括依次连续分布的第一子侧壁、第二子侧壁和第三子侧壁，所述第一电极与所述第二子侧壁连接，所述第一子侧壁和第三子侧壁位于所述第一电极和所述位线之间作为所述晶体管的沟道。
在一些实施例中，所述第一子侧壁和所述第三子侧壁相向设置。
在一些实施例中，不同层的晶体管的所述半导体层之间断开。
在一些实施例中，不同层的晶体管的所述栅极绝缘层之间断开。
在一些实施例中，所述栅电极的侧壁包含上表面、下表面、连接所述上表面和下表面且相对设置的第一侧表面和第二侧表面；
所述半导体层从所述栅电极的所述上表面经所述第一侧表面延伸到所述下表面。
在一些实施例中，所述半导体层的沿着垂直于所述衬底且平行于所述第一电极和位线排列方向的截面为U型，沿着垂直于所述衬底且垂直于第一电极和位线排列方向的截面为两条独立的线。
在一些实施例中，所述半导体器件还包括电容，所述第一电极为所述电容的其中一个电极，所述第一电极与所述半导体层环绕在所述栅电极的第一侧表面的区域连接，所述第二电极位于所述栅电极的第二侧表面远离所述第一电极一侧，且与U型的所述半导体层的端面连接。
本公开实施例提供一种3D堆叠的半导体器件阵列，包括：多层存储单元阵列，所述多层存储单元阵列包含多个上述3D堆叠的半导体器件，每层所述存储单元阵列包括阵列分布的多个晶体管，多条字线；每条所述字线对应多个存储单元，每条所述字线沿平行于所述衬底方向延伸，其中，每条字线与对应的多个存储单元中的每个晶体管连接，每个所述晶体管的栅电极为所连接的所述字线的一部分。
在一些实施例中，与同一字线连接的多个晶体管的半导体层连接为一体式结构；或者，
与同一字线连接的多个晶体管的半导体层之间相互断开。
在一些实施例中，与同一条字线连接的多个晶体管的栅极绝缘层连接为一体式结构。
在一些实施例中，所述多个3D堆叠的半导体器件包括多条位线，所述多条位线沿第一方向和第二方向阵列分布，所述第一方向与所述字线的延伸方向一致，所述第二方向垂直于所述第一方向；
多条位线与同一层不同存储单元一一对应，不同层中同一位置的每个存储单元的所述晶体管与同一条位线连接；
所述3D堆叠的半导体器件阵列还包括：与所述多条位线分别对应的设置在靠近所述衬底一侧的多个位线选通晶体管，以及，设置在所述位线选通晶体管靠近所述衬底一侧的多条公共位线，每行位线对应一条公共位线，所述位线选通晶体管连接对应的所述位线，同一行的位线连接到对应的所述公共位线，所述位线选通晶体管被配置为在开启时将所述公共位线的信号加载到对应的所述位线。
本公开实施例提供一种电子设备，包括上述任一所述的3D堆叠的半导体器件，或者，上述任一所述的3D堆叠的半导体器件阵列。
本公开实施例提供一种3D堆叠的半导体器件的制造方法，所述3D堆叠的半导体器件包括多个晶体管，分布于不同层沿垂直于衬底方向堆叠；位线，贯穿所述不同层的所述晶体管；所述3D堆叠的半导体器件的制造方法包括：
提供衬底，在所述衬底上依次交替沉积第一绝缘薄膜和导电薄膜，进行构图形成堆叠结构，所述堆叠结构包括交替设置的第一绝缘层和导电层的堆叠，所述导电层包括预设电极图形；所述预设电极图形包含待形成的所述位线和所述晶体管的第一电极；
构图形成从所述堆叠结构的顶部贯穿全部导电层的沟槽，所述沟槽对应所述导电层的第一区域的口径大于对应所述第一绝缘层的第二区域的口径，所述沟槽的侧壁露出所述导电层和所述第一绝缘层，所述沟槽使得所述预设电极图形形成所述晶体管的第一电极；所述第一区域包括与所述第二区域在所述衬底的正投影重叠的第二子区域和设置在所述第二子区域朝向所述第一电极一侧的第一子区域；
在所述沟槽的侧壁依次沉积半导体薄膜、栅绝缘薄膜和栅电极薄膜，刻蚀去除位于所述第二区域和第二子区域的半导体薄膜、栅绝缘薄膜和栅电极薄膜，以及，朝远离所述第二子区域的方向刻蚀所述栅电极薄膜预设厚度，且在所述第一子区域中所述栅电极薄膜被刻蚀的区域填充栅绝缘薄膜，以分别形成所述晶体管的半导体层、栅极绝缘层和栅电极；
在所述第二区域形成从所述堆叠结构的顶部贯穿全部导电层的通孔，所述通孔露出所述半导体层和所述栅极绝缘层，在所述通孔内沉积填充所述通孔的导电薄膜形成所述位线。
本公开实施例提供一种3D堆叠的半导体器件阵列的制造方法，所述3D堆叠的半导体器件阵列包括多个3D堆叠的半导体器件，所述3D堆叠的半导 体器件包括多个晶体管，分布于不同层沿垂直于衬底方向堆叠；位线，贯穿所述不同层的所述晶体管，所述3D堆叠的半导体器件阵列的制造方法包括：
提供衬底，在所述衬底上依次交替沉积第一绝缘薄膜和导电薄膜，进行构图形成堆叠结构，所述堆叠结构包括交替设置的第一绝缘层和导电层的堆叠，所述导电层包括多个预设电极图形；所述预设电极图形包含待形成的所述位线和所述晶体管的第一电极；
构图形成从所述堆叠结构的顶部贯穿全部导电层的沟槽，所述沟槽对应所述导电层的第一区域的口径大于对应所述第一绝缘层的第二区域的口径，所述沟槽的侧壁露出每个所述预设电极图形和所述第一绝缘层，所述沟槽使得所述多个预设电极图形分别形成所述多个3D堆叠的半导体器件同层的晶体管的第一电极；所述第一区域包括与所述第二区域在所述衬底的正投影重叠的第二子区域和设置在所述第二子区域朝向所述第一电极一侧的第一子区域；
在所述沟槽的侧壁依次沉积半导体薄膜、栅绝缘薄膜和栅电极薄膜，刻蚀去除位于所述第二区域和所述第二子区域的半导体薄膜、栅绝缘薄膜和栅电极薄膜，以及，朝远离所述第二子区域的方向刻蚀所述栅电极薄膜预设厚度，且在所述第一子区域中所述栅电极薄膜被刻蚀的区域填充栅绝缘薄膜，以分别形成所述多个3D堆叠的半导体器件同层的晶体管的半导体层、栅极绝缘层和字线；
在所述第二区域形成从所述堆叠结构的顶部贯穿全部导电层的多个间隔设置的通孔，所述通孔露出所述半导体层和所述栅极绝缘层，在所述通孔内沉积填充所述通孔的导电薄膜形成所述位线。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的目的和优点可通过在说明书以及附图中所特别指出的结构来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释技术方案，并不构成对技术方案的限制。
图1A为一示例性实施例提供的3D堆叠的半导体器件沿垂直于衬底方向的截面示意图；
图1B为一示例性实施例提供的3D堆叠的半导体器件沿平行于衬底方向的截面示意图；
图2为一示例性实施例提供的形成堆叠结构后的截面示意图；
图3A为一示例性实施例提供的形成预设电极图形后沿C方向的示意图；
图3B为图3A所示的半导体器件沿aa’方向的示意图；
图3C为图3A所示的半导体器件沿bb’方向的示意图；
图4A为一示例性实施例提供的暴露第一极后沿C方向的示意图；
图4B为图4A所示的半导体器件沿aa’方向的示意图；
图5A为一示例性实施例提供的形成电容后沿C方向的示意图；
图5B为图5A所示的半导体器件沿aa’方向的示意图；
图6A为一示例性实施例提供的刻蚀第二导电部和位线区域后沿C方向的示意图；
图6B为图6A所示的半导体器件沿aa’方向的示意图；
图7A为一示例性实施例提供的形成电容后沿C方向的示意图；
图7B为图7A所示的半导体器件沿C’方向的示意图；
图7C为图7A所示的半导体器件沿aa’方向的示意图；
图8A为一示例性实施例提供的刻蚀位线区域后沿C方向的示意图；
图8B为图8A所示的半导体器件沿aa’方向的示意图；
图9为一示例性实施例提供的对栅电极部分刻蚀后沿aa’方向的示意图；
图10为一示例性实施例提供的在栅电极被刻蚀区域沉积栅绝缘薄膜后沿aa’方向的示意图；
图11A为一示例性实施例提供的形成通孔后沿C方向的示意图；
图11B为图11A所示的半导体器件沿aa’方向的示意图；
图12A为一示例性实施例提供的形成位线后沿C方向的示意图；
图12B为图12A所示的半导体器件沿aa’方向的示意图；
图13为一示例性实施例提供的半导体器件阵列示意图。
具体实施方式
下文中将结合附图对本公开实施例进行详细说明。在不冲突的情况下，本公开实施例及实施例中的特征可以相互任意组合。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。
本公开的实施方式并不一定限定附图所示尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，并不表示任何顺序、数量或者重要性。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在公开中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是物理连接或信号连接，可以是接触连接或一体地连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本公开中，可以是第一电极为漏电极、第二电极为源电极，或者可以是第一电极为源电极、第二电极为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本公开中，“平行”是指大约平行或几乎平行，比如，两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指大约垂直，比如，两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开所说的“A和B同层设置”包含位于同一个膜层上的相同材料或不同材料形成的膜层。示例性的，A和B通过同一种材料形成同一个膜层后经同一次图案化工艺或不同的图案化工艺形成。同层设置的A和B可以是位于一个水平面上但是不必须位于同一个膜层上，或位于同一个膜层的不同区域但是不必须位于相同的水平面上。
“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
本公开示例性实施例提供一种新型的3D堆叠的半导体器件，可以包括水平方向延伸的字线和半导体层，垂直方向延伸的位线，其中，字线和半导体层设置在绝缘层之间的横向凹槽中，半导体层三面环绕字线的侧壁。一些实施例中半导体层的端面连接位线，形成一种双面沟道的结构。当然，位线可以与三面半导体层中靠近中间区域的半导体层连接，其他电路或电容与半导体层的端面连接。
图1A为一示例性实施例提供的3D堆叠的半导体器件沿垂直于衬底方向的截面示意图。图1B为一示例性实施例提供的3D堆叠的半导体器件沿平行于衬底方向的截面示意图。如图1A和图1B所示，本实施例提供的3D堆叠的半导体器件可以包括：
多个晶体管，分布于不同层沿垂直于衬底(图1A和图1B中未示出衬底)方向堆叠；
位线30，贯穿所述不同层的所述晶体管；
所述晶体管包括相对于衬底而言的水平晶体管，或横向晶体管，包括沿着水平方向依次排列的第一电极51，第二电极52，位于第一电极51和第二电极52之间的沟道区；沿平行于衬底方向(水平方向)延伸的栅电极26，部分环绕所述栅电极26侧壁的半导体层23，设置在所述栅电极26的侧壁和所述半导体层之23间的栅极绝缘层24。所述半导体层23为中空结构，所述半导体层23的纵截面(沿垂直于衬底方向的截面)具有开口。
本实施例提供的方案，不同层的晶体管共用同一条位线，垂直方向延伸的位线节约空间且可以一次工艺形成每个晶体管的位线和第二电极，减少掩模罩的数量，有效简化工艺制程，降低成本。
在一示例性实施例中，每个所述晶体管的所述第二电极52或第一电极51可以为所述位线30的一部分。
在一示例性实施例中，所述位线30可以沿垂直于所述衬底的方向延伸。其中，该位线30包括侧表面和上下两端的端面，侧表面整体上与衬底垂直，在实际制作产品过程中局部可能存在弯曲的区域也包含在本申请上述所述的情况中。位线30的侧表面与所述晶体管的半导体层23连接。所述位线30在沿垂直于衬底的方向延伸可以是沿着直线方向延伸，一些实施例中，每个晶体管的垂直方向延伸的第二电极52可以为直线，且在衬底上的正投影可以在相同位置，则每个晶体管的第二电极52连接后形成直线型位线。
所述直线型位线的沿平行于衬底方向的横截面可以处处相同，或不完全相同。本申请实施例不对该直线的横截面特点做限定。
在一示例性实施例中，沿平行于所述衬底的方向，所述位线30的截面可以是方形、圆形或者其他形状。
在一示例性实施例中，所述栅电极26可以仅沿平行于所述衬底的方向延伸。
在一示例性实施例中，所述栅电极26为字线40的一部分，所述字线40沿平行于衬底的方向延伸，所述半导体层23部分包裹字线40的侧壁，沿所述字线40延伸的方向延伸。在一示例性实施例中，所述位线30可以设置在所述栅电极26朝向所述半导体层23的开口的一侧，所述位线30可以与所述半导体层23的开口的端部连接。
在一示例性实施例中，所述位线30可以设置在所述栅电极26背离所述半导体层23的开口的一侧，所述半导体层23可以所述位线30可以与所述半导体层23的远离所述端部的侧壁连接。
在一示例性实施例中，所述位线30与所述栅电极26之间设置有隔离层242，所述隔离层242与所述栅极绝缘层24连接。
一些实施例中，栅极绝缘层24和隔离层242的膜层材料可以不同，比如，隔离层242为低介电常数的膜层，可以降低位线30与所述栅电极26之间的寄生电容。示例性的，隔离层242比如为Low-K膜层，如氧化硅。
栅极绝缘层24比如为High-k材料，比如介电常数K＞3.9的介质材料。该类膜层可以提高栅控能力。一些实施例中，High-k材料可以包括铪、铝、镧、锆等一个或多个的氧化物。示例性的，比如，可以包括但不限于以下至少之一：氧化铪(HfO2)、氧化铝(Al2O3)，铪铝氧化物(HfAlO)，铪镧氧化物(HfLaO)、锆的氧化物(ZrO2)。
在一示例性实施例中，所述栅极绝缘层24还可以一体式的设置在所述栅电极26的侧壁和所述位线30的侧壁之间。沿垂直于所述衬底的方向，所述栅极绝缘层24的截面可以为闭环。此时栅极绝缘层24位于栅电极26与半导体层23之间，以及半导体层23的开口处的栅电极26与位线30之间，可一次工艺形成栅极绝缘层24，简化工艺流程。
在一示例性实施例中，沿所述半导体层23的环绕方向(即环绕栅电极26的方向)，所述半导体层23可以包括两个主表面和主表面之间的端面；所述端面包括朝向位线30或电容的端面，如附图1A中的第一端部231、第二端部232，其中一个主表面为外表面，如附图1A中连接所述第一端部231和第二端部232的侧壁233。
一些实施例中，所述第一端部231和第二端部232与所述位线30连接。所述半导体层23沿从所述第一端部231至第二端部232的方向环绕所述栅电极26。本实施例中，半导体层23部分环绕所述栅电极26，可以理解为，不是全环绕栅电极，而是环绕栅电极26的部分侧壁。在一些实施例中，可以环 绕栅电极26的周向至少一半的区域。一些实施例中，可以环绕栅电极26的三个侧壁。可以理解为沿垂直于所述衬底且平行于26栅电极延伸方向，所述半导体层23的截面为具有开口的环形。第一端部231可以是一个端面，第二端部232可以是与第一端部231独立的另一个端面。
在一示例性实施例中，所述第一端部231在所述衬底的正投影和所述第二端部232在所述衬底的正投影可以重叠。
在一示例性实施例中，沿着垂直所述衬底的方向延伸的所述位线30不同区域的材料组分相同，可以理解为使用同一次膜层制作工艺形成，所述材料的组分相同可以理解为材料中测试出的主要元素相同，比如，都是通过金属或ITO等透明导电材料制作而成，但是不限制其不同区域的原子数比。
在一示例性实施例中，从所述第一端部231至所述第二端部232，所述半导体层的侧壁233可以仅包括依次连续分布的第一子侧壁233_1、第二子侧壁233_2和第三子侧壁233_3，所述第一电极51与所述第二子侧壁233_2连接，比如，所述第一电极51与所述第二子侧壁233_2接触。本实施例提供的方案，为双面沟道，一面为第一子侧壁233_1，另一面为第三子侧壁233_3。
在一示例性实施例中，所述第一子侧壁233_1和所述第三子侧壁233_3可以相向设置，相对于衬底而言为上下两个侧壁。
在一示例性实施例中，第一子侧壁233_1远离所述衬底一侧的表面可以平行于所述衬底；所述第三子侧壁233_3靠近所述衬底一侧的表面可以平行于所述衬底。
在一示例性实施例中，不同层的晶体管的所述半导体层23之间可以断开，可以理解为物理上不接触，或者，可以是电学上绝缘。
在一示例性实施例中，不同层的晶体管的所述栅极绝缘层24之间可以断开。
在一示例性实施例中，所述第一电极51朝向所述位线30一侧的表面可以向远离所述位线30一侧凹陷。
在一示例性实施例中，所述栅电极26的侧壁可以包含上表面(远离所述衬底一侧的表面)、下表面(靠近所述衬底一侧的表面)和两个侧表面，两个侧表面分别称为第一侧表面和第二侧表面；第一侧表面和第二侧表面连接所述上表面和下表面且相对设置；
所述半导体层23可以从所述栅电极26的所述上表面经所述第一侧表面延伸到所述下表面。
在一示例性实施例中，所述半导体层23的横截面(平行衬底方向截取)为一条线；沿着垂直于衬底且垂直于栅电极26延伸方向截取的截面可以为U型。沿着垂直于衬底且平行于栅电极26延伸方向截取的截面可以为两条独立 的线。或者，所述半导体层23的沿着垂直于所述衬底且平行于所述第一电极51和位线30排列方向的截面为U型，沿着垂直于所述衬底且垂直于第一电极51和位线30排列方向的截面为两条独立的线。第一电极51和位线30的排列方向可以垂直于栅电极26的延伸方向。栅电极26延伸方向为第二方向Y，第一方向X垂直于第二方向Y时，即，沿第一方向X截取的截面可以为U型。
在一示例性实施例中，所述半导体器件还可以包括电容，所述第一电极51或第二电极52，为所述电容的其中一个电极。
以第一电极51为电容电极为例，所述第一电极51与所述半导体层23环绕在所述栅电极26的第一侧表面的区域连接(即与第二子侧壁233_2连接)，所述第二电极52位于所述栅电极26的第二侧表面远离所述第一电极51一侧，且与U型的所述半导体层23的端面连接。本实施例中，半导体层23为U型，半导体层23的端面即该U型的开口处的表面，即第一端部231和第二端部232。
在一示例性实施例中，在平行于所述衬底的平面上，不同层的所述晶体管的所述第一电极51的正投影可以重叠。第一电极51的正投影重叠，可以使得3D堆叠的半导体器件紧凑，且制造时可以一次制造不同层的电极，工艺简便。
在一示例性实施例中，在平行于所述衬底的平面上，不同层的所述晶体管的所述半导体层23或者栅极绝缘层24或者栅电极26的正投影可以重叠。半导体层23或者栅极绝缘层24或者栅电极26的正投影重叠，可以使得3D堆叠的半导体器件紧凑。
本公开实施例提供一种3D堆叠的半导体器件阵列，可以包括：多个上述任一实施例所述的3D堆叠的半导体器件，沿平行于所述衬底方向延伸的字线40，其中，所述多个3D堆叠的半导体器件可以沿平行于所述衬底方向分布，所述多个3D堆叠的半导体器件同层的晶体管的栅电极26为所述字线40的一部分。
在一示例性实施例中，所述多个3D堆叠的半导体器件同层的晶体管的半导体层23连接为一体式结构，或者，所述多个3D堆叠的半导体器件同层的晶体管的半导体层23之间相互断开。本实施例提供的方案，半导体层23连接为一体式结构时，可以通过一次制造工艺形成同层多个晶体管的半导体层，工艺简便。
在一示例性实施例中，所述多个3D堆叠的半导体器件同层的晶体管的栅极绝缘层24连接为一体式结构。本实施例提供的方案，可以通过一次制备工艺形成同层多个晶体管的栅极绝缘层，工艺简便。
在一示例性实施例中，所述字线40在平行于衬底的方向延伸可以是沿着 直线方向延伸。一些实施例中，每个晶体管的水平方向延伸的栅电极26可以为直线，且在垂直于衬底的平面上的正投影可以在相同位置，则同层的每个晶体管的栅电极26连接后形成直线型字线40。
所述直线型字线40的沿垂直于衬底方向的横截面可以处处相同，或不完全相同。本申请实施例不对该直线的横截面特点做限定。
本公开实施例提供一种3D堆叠的半导体器件阵列，包括：多层存储单元阵列，所述多层存储单元阵列包含多个上述的3D堆叠的半导体器件，每层所述存储单元阵列包括多个存储单元，以及多条字线40，每个存储单元包括一个晶体管；每条所述字线40对应所述字线40所在层的多个存储单元，每条所述字线40沿平行于所述衬底方向延伸，其中，每条字线40与对应的多个存储单元中的每个晶体管连接，每个所述晶体管的栅电极26为所连接的所述字线40的一部分。
在一些实施例中，同层的所述多条字线40可以平行。
在一些实施例中，与同一字线40连接的多个晶体管的半导体层23连接为一体式结构；或者，
与同一字线40连接的多个晶体管的半导体层23之间相互断开。
在一些实施例中，与同一条字线40连接的多个晶体管的栅极绝缘层24可以连接为一体式结构。
在一些实施例中，与同一条字线40连接的多个晶体管的隔离层242可以连接为一体式结构。
在一些实施例中，所述多个3D堆叠的半导体器件包括多条位线30，所述多条位线30沿第一方向X和第二方向Y阵列分布，所述第二方向与所述字线40的延伸方向一致，所述第一方向X垂直于所述第二方向Y；第一方向X为行方向，第二方向Y为列方向，一行位线30沿第一方向X分布，一列位线30沿第二方向分布；
多条位线30与同一层不同存储单元一一对应，不同层中同一位置的每个存储单元的所述晶体管与同一条位线30连接。
在一示例性实施例中，如图13所示的一行存储单元的纵截面示意图，所述3D堆叠的半导体器件阵列还可以包括：与与所述多条位线30分别对应的多个位线选通晶体管300，以及，设置在所述位线选通晶体管300靠近所述衬底一侧的多条公共位线200，每行位线30对应一条公共位线200，所述位线选通晶体管300分别连接对应的所述位线30，同一行的位线30所连接的位线选通晶体管300连接到对应的所述公共位线200，所述位线选通晶体管300被配置为在开启时将所述公共位线200的信号加载到对应的所述位线30，从而实现位线30的选通。位线选通晶体管300可以和位线30一一对应，但 不限于此，可以多条位线30连接到同一位线选通晶体管300。
在一示例性实施例中，所述位线选通晶体管300可以设置在所述位线30靠近所述衬底一侧。但本公开实施例不限于此，所述位线选通晶体管300可以设置在所述位线30远离所述衬底一侧。
在一示例性实施例中，所述公共位线200可以设置在所述位线选通晶体管300靠近所述衬底一侧。但本公开实施例不限于此，所述公共位线200可以设置在所述位线选通晶体管300远离所述衬底一侧。
上述3D堆叠的半导体器件可以和电容器组成1T1C的存储结构，或者，和其他晶体管组成2T0C的存储结构，等等。下面以1T1C为例进行说明。
如图1A和图1B所示，本公开实施例提供一种3D存储器，包括：上述3D堆叠的半导体器件，还可以包括：数据存储元件。
在一示例性实施例中，所述数据存储元件比如为电容，即形成1T1C的存储结构。但本公开实施例不限于此，可以和其他晶体管组成2T0C的存储结构，等等。
在一示例性实施例中，所述电容可以包括第一极41和第二极42，所述第一极41与所述第一电极51连接。
在一示例性实施例中，所述第一极41与所述第一电极51可以连接为一体式结构。
在一示例性实施例中，不同层的相同列的所述电容的所述第二极42可以连接为一体式结构。如图1A所示，不同层的第一列的所述电容的所述第二极42连接为一体式结构。不同层的第二列的所述电容的所述第二极42连接为一体式结构，即，不同层的相同列的所述电容共用同一电极作为第二极42。
在一示例性实施例中，所述电容还可以包括设置在所述第一极41和第二极42之间的第二绝缘层13。第二绝缘层13作为第一极41和第二极42之间的介质。
在一示例性实施例中，不同层的相同列的所述电容的所述第二绝缘层13可以连接为一体式结构。如图1A所示，不同层的第一列的所述电容的所述第二绝缘层13连接为一体式结构。不同层的第二列的所述电容的所述第二绝缘层13连接为一体式结构，即，不同层的相同列的所述电容共用同一绝缘层作为电极间的介质。
一个晶体管和一个数据存储元件构成一个存储单元。在一示例性实施例中，如图1B所示，同层的所述存储单元形成分别沿第一方向X和第二方向Y分布的阵列，每层所述存储单元还包括：字线40。图1B中示出了每层包括四行两列存储单元，但本公开实施例不限于此，每层可以包括其他行数和列数的存储单元，比如，可以只包括一个存储单元。所述第一方向X可以平 行于所述衬底，所述第二方向Y可以平行于所述衬底，第一方向X和第二方向Y交叉。在一些实施例中，所述第一方向X和第二方向Y可以垂直。
在一示例性实施例中，相同层同一列的存储单元的晶体管的栅电极26连接形成字线40。即，相同层同一列的存储单元的晶体管的栅电极26为字线40的一部分。
在一示例性实施例中，所述字线40可以沿第二方向Y延伸。
在一示例性实施例中，所述第一电极51可以沿第一方向X延伸。所述第一方向X和第二方向Y可以垂直。
下面通过本实施例半导体器件的制备过程进一步说明本实施例的技术方案。本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是相关技术中成熟的制备工艺。本实施例中所说的“光刻工艺”包括涂覆膜层、掩模曝光和显影，是相关技术中成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做具体的限定。在本实施例的描述中，需要理解的是，“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺或光刻工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”还需构图工艺或光刻工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺或光刻工艺后的“层”中包含至少一个“图案”。
在一示例性实施例中，3D堆叠的半导体器件的制造过程可以包括：
1)在衬底上依次交替沉积第一绝缘薄膜9和第一导电薄膜11形成叠层结构，如图2所示，其中，图2为沿垂直于衬底方向的截面图。图2中未示出衬底。衬底设置在图2所示的膜层的底部。
在一示例性实施例中，所述第一绝缘薄膜9可以是low-K介质层，即介电常数K<3.9的介质层，包括但不限于硅氧化物，比如二氧化硅(SiO2)等。
在一示例性实施例中，所述第一导电薄膜11可以是如下导电材料：
比如，含有钨、铝、钛、铜、镍、铂、钌、钼、金、铱、铑、钽、钴等金属；可以是含有前述提到的这些金属中的金属合金；
或者，可以是金属氧化物、金属氮化物、金属硅化物、金属碳化物等，如铟锡氧化物(ITO)、铟锌氧化物(IZO)、铟的氧化物(InO)等导电性较高的金属氧化物材料；比如，氮化钛(TiN)、氮化钽(TaN)、氮化钨(WN)、氮化钛铝(TiAlN)等金属氮化物材料；
或者，可以是多晶硅材料、导电掺杂半导体材料等，比如，导电掺杂后的硅、导电掺杂后的锗、导电掺杂后的硅锗等；体现导电性的其他材料等。
一些实施例中，所述第一导电薄膜11可以包括但不限于氮化钛(TiN)、 钨(W)、金属氧化物导电层，如ITO等单层或多层结构。
图2中示出的叠层结构包括5层第一绝缘薄膜9和4层第一导电薄膜11，仅为示例，在其他实施例中，所述叠层结构可以包括更多或更少层交替设置的第一绝缘薄膜9和第一导电薄膜11。
2)对所述叠层结构进行构图形成包括交替堆叠的导电层12和第一绝缘层10的堆叠结构；如图3A、图3B、图3C所示，其中，图3A为3D堆叠的半导体器件沿C方向的截面示意图，图3B为图3A所示3D堆叠的半导体器件沿aa’方向的截面示意图，图3C为图3A所示3D堆叠的半导体器件沿bb’方向的截面示意图，所述C方向平行于所述衬底，所述aa’方向垂直于所述衬底，所述bb’方向垂直于所述衬底，所述aa’方向和bb’方向可以垂直。
所述对所述叠层结构进行构图形成包括导电层12和第一绝缘层10的堆叠结构可以包括：
利用干法刻蚀方法刻蚀所述叠层结构形成沟槽，构图形成所述导电层12后再在沟槽区域填充绝缘薄膜，以隔离不同器件；所述导电层12可以包括预设电极图形，如图3A所示，所述预设电极图形可以包括第一导电部121和第二导电部122，其中，第一导电部121可以沿第一方向X延伸，第二导电部122可以沿第二方向Y延伸，其中，图3A所示的预设电极图形仅为示例，所述预设电极图形可以是其他形状。其中，刻蚀所述叠层结构时，去除位线区域200的第一导电薄膜11，便于后续在该区域形成多条沿着衬底方向延伸的位线。
在一示例性实施例中，可以使用化学气相沉积(Chemical Vapor Deposition，CVD)方式沉积所述绝缘薄膜。所述绝缘薄膜与所述第一绝缘薄膜9可以是相同的材料，当然也可以是不同的材料，二者都可以是Low-K材料，后续以绝缘薄膜与第一绝缘薄膜9一致为例进行说明。
3)暴露第一极41；
所述暴露第一极41可以包括：填充所述绝缘薄膜之后，利用干法刻蚀从顶层刻蚀到底层，形成沟槽，该沟槽是通过去除相邻两组存储单元之间的第一绝缘层形成的，也就是去除相邻两组电容区域100之间的第一绝缘薄膜形成的，在所述沟槽内再利用湿法刻蚀，通过酸溶液将层间沟槽内暴露出得第一绝缘层10进行横向刻蚀，刻蚀预设长度，以暴露第一导电部121的部分区域得到第一极41，即暴露第一导电部121的端面和与端面相邻的部分侧壁，如图4A，图4B所示，其中，图4A为3D堆叠的半导体器件沿C方向的截面示意图，图4B为图4A所示3D堆叠的半导体器件沿aa’方向的截面示意图。
4)形成第二绝缘层13和第二极42；
所述形成第二绝缘层13和第二极42可以包括：在所述电容区域100依 次沉积第二绝缘薄膜和导体材料，分别形成第二绝缘层13和第二极42，所述第二绝缘层13覆盖导电层12暴露出的区域，如图5A、图5B所示，其中，图5A为3D堆叠的半导体器件沿C方向的截面示意图，图5B为图5A所示3D堆叠的半导体器件沿aa’方向的截面示意图。
其中，第二绝缘层13作为电容电极之间的介质，第二极42作为电容的一个电极。
在一示例性实施例中，可以通过原子层沉积(Atomic Layer Deposition，ALD)方式沉积所述第二绝缘薄膜和导体材料。
在一示例性实施例中，所述第二绝缘薄膜可以是High-K介质材料，即介电常数K≥3.9的介质材料。一些实施例中，可以包括铪、铝、镧、锆等一个或多个的氧化物。示例性的，比如，可以包括但不限于以下至少之一：氧化铪(HfO2)、氧化铝(Al2O3)，铪铝氧化物(HfAlO)，铪镧氧化物(HfLaO)、锆的氧化物(ZrO2)等高K材料。
在一示例性实施例中，所述导体材料包括但不限于以下至少之一：金属、金属合金、多晶硅、硅掺杂导电层，金属氧化物导电层。
所述第二极42可以为沿着垂直衬底方向延伸的板状结构，通过绝缘层与上述沟槽露出的每层存储单元的电容的第一电极连接，形成公共电极板。
在一示例性实施例中，在沉积所述第二绝缘薄膜之前，可以在所述电容区域100沉积TiN等，与导电层12暴露的电极一起作为电容的第一极41，即在第一极41与第二绝缘层13之间设置有比如为TiN的粘合膜层，以增强第一极41与第二绝缘层13之间的粘合性。所述粘合膜层覆盖所述导电层12暴露出的区域，不同层的导电层12上附着的粘合膜层之间断开，即沉积粘合膜层后，在沉积所述第二绝缘薄膜之前，可以对粘合膜层进行刻蚀以断开不同层的导电层12上附着的粘合膜层。
5)刻蚀去除堆叠结构中位于位线区域200的第一绝缘薄膜，以及，去除第二导电部122，形成沟槽。
所述刻蚀去除位于位线区域200的第一绝缘薄膜，以及，去除第二导电122可以包括：通过干法刻蚀，从顶层到底层将位线区域200填充的第一绝缘薄膜全部刻蚀掉；以及，利用湿法刻蚀，通过选择第一绝缘薄膜和第一导电薄膜高选择比的酸溶液，将位线区域200两侧的第二导电部122进行横向刻蚀，而第一绝缘薄膜基本不会有所刻蚀，刻蚀时，可以使得第一导电部121有所损失，即刻蚀掉第一导电部121的部分区域，以此保证中间的位线区域200两侧水平的每个第二导电部122薄膜刻蚀完全。横向刻蚀水平的导电层12之后，会在任意相邻的第一绝缘薄膜之间(如层间SiO2)之间形成水平的U型槽。如图6A和图6B所示，图6A为3D堆叠的半导体器件沿C方向的截面示意图，图6B为图6A所示3D堆叠的半导体器件沿aa’方向的截面 示意图。
6)形成半导体层23、栅极绝缘层24和栅电极26；
所述形成半导体层23、栅极绝缘层24和栅电极26可以包括：在步骤5)刻蚀形成的U型槽区域以及整个沟槽的侧壁依次沉积半导体薄膜、栅绝缘薄膜和栅电极薄膜，依次形成半导体层23、栅极绝缘层24和栅电极26，如图7A、图7B和图7C所示，其中，图7A为3D堆叠的半导体器件沿C方向的截面示意图，图7B为图7A所示3D堆叠的半导体器件沿C’方向的截面示意图，图7C为图7A所示3D堆叠的半导体器件沿aa’方向的截面示意图。所述C’方向平行于所述衬底。
此时，半导体层23、栅极绝缘层24和栅电极26位于整个U型凹槽中，该U型凹槽对应二维平面内的一列存储单元。当然，同一个沟槽内的每个U型凹槽中的半导体层23连接、栅极绝缘层24连接，栅电极26连接。
在本公开的示例性实施例中，所述半导体层23的材料可以为带隙小于1.65eV的硅或多晶硅等材料，或者，可以是宽带隙材料，比如带隙大于1.65eV的金属氧化物材料。
举例来说，金属氧化物半导体层或沟道的材料可包括如下金属中的至少之一的金属氧化物：铟、镓、锌、锡、钨、镁、锆、铝、铪等材料。当然，该金属氧化物中也不排除含有其他元素的化合物，比如，N、Si等元素；也不排除含有其他少量掺杂元素。
一些实施例中，金属氧化物半导体层或沟道的材料可以包含以下中的一或多者：铟镓锌氧化物(InGaZnO)、氧化铟锌(InZnO)、氧化铟镓(InGaO)、氧化铟锡(InSnO)、氧化铟镓锡(InGaSnO)、氧化铟镓锌锡(InGaZnSnO)、氧化铟(InO)、氧化锡(SnO)、氧化锌锡(ZnSnO，ZTO)、氧化铟铝锌金(InAlZnO)、氧化锌(ZnO)、铟镓硅氧化物(InGaSiO)、氧化铟钨(InWO，IWO)、氧化钛(TiO)、氮氧化锌(ZnON)、氧化镁锌(MgZnO)、锆铟锌氧化物(ZrInZnO)、铪铟锌氧化物(HfInZnO)、锡铟锌氧化物(SnInZnO)、铝锡铟锌氧化物(AlSnInZnO)、硅铟锌氧化物(SiInZnO)、铝锌锡氧化物(AlZnSnO)、镓锌锡氧化物(GaZnSnO)、锆锌锡氧化物(ZrZnSnO)等材料，只要保证晶体管的漏电流能满足要求即可，具体可根据实际情况进行调整。
这些材料的带隙较宽，具有较低的漏电流，比如，当金属氧化物材料为IGZO时，晶体管的漏电流小于或者等于10-15A，由此可以改善动态存储器的工作性能。
上述金属氧化物半导体层或沟道的材料仅强调材料的元素类型，不强调材料中原子占比以及材料的膜质。
在本公开的示例性实施例中，所述栅极绝缘层24的材料可以包含一层或多层High-K介质材料，比如介电常数K≥3.9的介质材料。一些实施例中， 可以包括铪、铝、镧、锆等一个或多个的氧化物。示例性的，比如，可以包括但不限于以下至少之一：氧化铪(HfO2)、氧化铝(Al2O3)，铪铝氧化物(HfAlO)，铪镧氧化物(HfLaO)、锆的氧化物(ZrO2)等高K材料。
在一示例性实施例中，所述栅绝缘薄膜厚度可以为10nm至15nm。
在一示例性实施例中，栅电极薄膜可以是如下不同类型材料中的一种或多种。
比如，含有钨、铝、钛、铜、镍、铂、钌、钼、金、铱、铑、钽、钴等金属；可以是含有前述提到的这些金属中的金属合金；
或者，可以是金属氧化物、金属氮化物、金属硅化物、金属碳化物等，如铟锡氧化物(ITO)、铟锌氧化物(IZO)、铟的氧化物(InO)等导电性较高的金属氧化物材料；比如，氮化钛(TiN)、氮化钽(TaN)、氮化钨(WN)、氮化钛铝(TiAlN)等金属氮化物材料；
或者，可以是多晶硅材料、导电掺杂半导体材料等，比如，导电掺杂后的硅、导电掺杂后的锗、导电掺杂后的硅锗等；体现导电性的其他材料等。
在一示例性实施例中，所述栅电极薄膜包括但不限于以下至少之一：掺锡的氧化铟(Indium Tin Oxide，ITO)、氮化钛/钨(TiN/W)、掺铝氧化锌(Al-doped ZnO，AZO)，掺铟的氧化锌(Indium Zinc Oxide，IZO)。
7)刻蚀去除位于位线区域200的半导体薄膜、栅绝缘薄膜和栅电极薄膜；
所述刻蚀去除位于位线区域200(可以理解为沟槽区域)的半导体薄膜、栅绝缘薄膜和栅电极薄膜可以包括：通过干法刻蚀去除位于位线区域200的半导体薄膜、栅绝缘薄膜和栅电极薄膜，如图8A和图8B所示，其中，图8A为3D堆叠的半导体器件沿C方向的截面示意图，图8B为图8A所示3D堆叠的半导体器件沿aa’方向的截面示意图。刻蚀时，完全去除位于第一绝缘层10侧壁的半导体薄膜。
8)刻蚀栅电极26；
所述刻蚀栅电极26包括：将所述栅电极26向远离所述位线区域200的方向刻蚀预设厚度，比如5nm至10nm，避免后续形成的位线与栅电极26接触，如图9所示，其中，图9为3D堆叠的半导体器件沿aa’方向的截面示意图。
9)在位线区域200以及栅电极26被刻蚀的区域沉积第四绝缘薄膜，刻蚀去除位线区域200的第四绝缘薄膜，保留位于栅电极26被刻蚀的区域的第四绝缘薄膜，形成隔离层242，此时，栅电极26与后续形成的位线由隔离层242进行隔离，如图10所示，图10为3D堆叠的半导体器件沿aa’方向的截面示意图。
所述第四绝缘薄膜可以包含一层或多层High-K介质材料，比如可以和 栅绝缘薄膜一致，或者，所述第四绝缘薄膜可以是Low-K材料，比如氧化硅。
10)形成通孔K1；
所述形成通孔K1包括：在位线区域200沉积填充所述位线区域200的第三绝缘薄膜，刻蚀所述第三绝缘薄膜形成多个通孔K1，所述通孔K1的侧壁暴露所述栅极绝缘层24和所述半导体层23，如图11A、图11B所示，其中，图11A为3D堆叠的半导体器件沿C方向的截面示意图，图11B为图11A所示3D堆叠的半导体器件沿aa’方向的截面示意图。不同的通孔K1之间通过第三绝缘薄膜进行隔离。
在一示例性实施例中，在平行于所述衬底的平面上，所述通孔K1的正投影可以为方形，但本公开实施例不限于此，所述通孔K1的正投影可以是圆形等。
12)形成位线30；
所述形成位线30可以包括：在所述通孔K1中沉积填充所述通孔K1的第二导电薄膜，形成位线30，如图12A、图12B所示，其中，图12A为3D堆叠的半导体器件沿C方向的截面示意图，图12B为图12A所示3D堆叠的半导体器件沿aa’方向的截面示意图。
在一示例性实施例中，位线材料可以是如下不同类型材料中的一种或多种：
比如，含有钨、铝、钛、铜、镍、铂、钌、钼、金、铱、铑、钽、钴等金属；可以是含有前述提到的这些金属中的金属合金；
或者，可以是金属氧化物、金属氮化物、金属硅化物、金属碳化物等，如铟锡氧化物ITO、铟锌氧化物IZO、铟的氧化物InO等导电性较高的金属氧化物材料；比如，氮化钛(TiN)、氮化钽(TaN)、氮化钨(WN)、氮化钛铝(TiAlN)等金属氮化物材料；
或者，可以是多晶硅材料、导电掺杂半导体材料等，比如，导电掺杂后的硅、导电掺杂后的锗、导电掺杂后的硅锗等；体现导电性的其他材料等。
在一示例性实施例中，所述第二导电薄膜包括但不限于ITO、IZO等透明导电氧化物或其他导电材料。
图13为另一示例性实施例提供的3D堆叠的半导体器件阵列沿垂直于衬底方向的截面示意图。如图13所示，本实施例提供的3D堆叠的半导体器件阵列可以包括阵列分布的多行和多列存储单元，所述存储单元可以包括晶体管和电容，沿垂直于衬底的方向，相邻两列存储单元为一组，同组不同行的存储单元可以共用一条位线30，相邻两组存储单元可以共用一个电极作为第二极42。所述3D堆叠的半导体器件阵列还可以包括与所述位线30一一对应的位线选通晶体管300，以及，多条公共位线200，一条所述公共位线200 连接到同一行的位线30连接的所述位线选通晶体管300，所述位线选通晶体管300连接到对应的位线30。可以通过位线选通晶体管300的开启和关断，将公共位线200的信号加载或不加载到位线30，实现位线30的选通。
本公开实施例还提供了一种电子设备，包括前述实施例所述的3D堆叠的半导体器件或者3D堆叠的半导体器件阵列。所述电子设备可以为：存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源等。存储装置可以包括计算机中的内存等，此处不作限定。
本公开实施例提供一种3D堆叠的半导体器件的制造方法，所述3D堆叠的半导体器件包括多个晶体管，分布于不同层沿垂直于衬底方向堆叠；位线，贯穿所述不同层的所述晶体管；所述3D堆叠的半导体器件的制造方法包括：
提供衬底，在所述衬底上依次交替沉积第一绝缘薄膜和导电薄膜，进行构图形成堆叠结构，所述堆叠结构包括交替设置的第一绝缘层和导电层的堆叠，所述导电层包括预设电极图形；所述预设电极图形包含待形成的所述位线和所述晶体管的第一电极；
构图形成从所述堆叠结构的顶部贯穿全部导电层的沟槽，所述沟槽对应所述导电层的第一区域的口径大于对应所述第一绝缘层的第二区域的口径，所述沟槽的侧壁露出所述导电层和所述第一绝缘层，所述沟槽使得所述预设电极图形形成所述晶体管的第一电极；所述第一区域包括与所述第二区域在所述衬底的正投影重叠的第二子区域和设置在所述第二子区域朝向所述第一电极一侧的第一子区域；
在所述沟槽的侧壁依次沉积半导体薄膜、栅绝缘薄膜和栅电极薄膜，刻蚀去除位于所述第二区域和第二子区域的半导体薄膜、栅绝缘薄膜和栅电极薄膜，以及，朝远离所述第二子区域的方向刻蚀所述栅电极薄膜预设厚度，且在所述第一子区域中所述栅电极薄膜被刻蚀的区域填充栅绝缘薄膜，以分别形成所述晶体管的半导体层、栅极绝缘层和栅电极；
在所述第二区域形成从所述堆叠结构的顶部贯穿全部导电层的通孔，所述通孔露出所述半导体层和所述栅极绝缘层，在所述通孔内沉积填充所述通孔的导电薄膜形成所述位线。
本公开实施例提供一种3D堆叠的半导体器件阵列的制造方法，所述3D堆叠的半导体器件阵列包括多个3D堆叠的半导体器件，所述3D堆叠的半导体器件包括多个晶体管，分布于不同层沿垂直于衬底方向堆叠；位线，贯穿所述不同层的所述晶体管，包括：
提供衬底，在所述衬底上依次交替沉积第一绝缘薄膜和导电薄膜，进行构图形成堆叠结构，所述堆叠结构包括交替设置的第一绝缘层和导电层的堆叠，所述导电层包括多个预设电极图形；所述预设电极图形包含待形成的所述位线和所述晶体管的第一电极；
构图形成从所述堆叠结构的顶部贯穿全部导电层的沟槽，所述沟槽对应所述导电层的第一区域的口径大于对应所述第一绝缘层的第二区域的口径，所述沟槽的侧壁露出每个所述预设电极图形和所述第一绝缘层，所述沟槽使得所述多个预设电极图形分别形成所述多个3D堆叠的半导体器件同层的晶体管的第一电极；所述第一区域包括与所述第二区域在所述衬底的正投影重叠的第二子区域和设置在所述第二子区域朝向所述第一电极一侧的第一子区域；
在所述沟槽的侧壁依次沉积半导体薄膜、栅绝缘薄膜和栅电极薄膜，刻蚀去除位于所述第二区域和第二子区域的半导体薄膜、栅绝缘薄膜和栅电极薄膜，以及，朝远离所述第二子区域的方向刻蚀所述栅电极薄膜预设厚度，且在所述第一子区域中所述栅电极薄膜被刻蚀的区域填充栅绝缘薄膜，以分别形成所述多个3D堆叠的半导体器件同层的晶体管的半导体层、栅极绝缘层和字线；
在所述第二区域形成从所述堆叠结构的顶部贯穿全部导电层的多个间隔设置的通孔，所述通孔露出所述半导体层和所述栅极绝缘层，在所述通孔内沉积填充所述通孔的导电薄膜形成所述位线。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (18)

  1. 一种3D堆叠的半导体器件，包括：
    多个晶体管，分布于不同层沿垂直于衬底方向堆叠；
    位线，贯穿所述不同层的所述晶体管；
    所述晶体管包括第一电极，第二电极，沿平行于衬底方向延伸的栅电极，部分环绕所述栅电极侧壁的半导体层使得所述半导体层在垂直于所述衬底上的截面具有开口，设置在所述栅电极的侧壁和所述半导体层之间的栅极绝缘层。
  2. 根据权利要求1所述的3D堆叠的半导体器件，其中，所述位线设置在所述栅电极朝向所述半导体层的开口的一侧，所述位线与所述半导体层的开口的端部连接。
  3. 根据权利要求2所述的3D堆叠的半导体器件，其中，所述位线与所述栅电极之间设置有隔离层，所述隔离层与所述栅极绝缘层连接。
  4. 根据权利要求2所述的3D堆叠的半导体器件，其中，沿所述半导体层的环绕方向，所述半导体层的端部包括相互独立的第一端部、第二端部，所述半导体层还包括位于所述第一端部和第二端部之间的侧壁，所述第一端部和第二端部与所述位线连接。
  5. 根据权利要求4所述的3D堆叠的半导体器件，其中，从所述半导体层的所述第一端部至所述第二端部，所述半导体层的侧壁包括依次连续分布的第一子侧壁、第二子侧壁和第三子侧壁，所述第一电极与所述第二子侧壁连接，所述第一子侧壁和第三子侧壁位于所述第一电极和所述位线之间作为所述晶体管的沟道。
  6. 根据权利要求5所述的3D堆叠的半导体器件，其中，所述第一子侧壁和所述第三子侧壁相向设置。
  7. 根据权利要求1至6任一所述的3D堆叠的半导体器件，其中，不同层的晶体管的所述半导体层之间断开。
  8. 根据权利要求1至6任一所述的3D堆叠的半导体器件，其中，不同层的晶体管的所述栅极绝缘层之间断开。
  9. 根据权利要求1所述的3D堆叠的半导体器件，其中，所述栅电极的侧壁包含上表面、下表面、连接所述上表面和下表面且相对设置的第一侧表面和第二侧表面；
    所述半导体层从所述栅电极的所述上表面经所述第一侧表面延伸到所述下表面。
  10. 根据权利要求9所述的3D堆叠的半导体器件，其中，所述半导体层 的沿着垂直于所述衬底且平行于所述第一电极和位线排列方向的截面为U型，沿着垂直于所述衬底且垂直于第一电极和位线排列方向的截面为两条独立的线。
  11. 根据权利要求10所述的3D堆叠的半导体器件，其中，所述半导体器件还包括电容，所述第一电极为所述电容的其中一个电极，所述第一电极与所述半导体层环绕在所述栅电极的第一侧表面的区域连接，所述第二电极位于所述栅电极的第二侧表面远离所述第一电极一侧，且与U型的所述半导体层的端面连接。
  12. 一种3D堆叠的半导体器件阵列，包括：多层存储单元阵列，所述多层存储单元阵列包含多个如权利要求1至10任一所述的3D堆叠的半导体器件，每层所述存储单元阵列包括多个存储单元，以及多条字线，每个存储单元包括一个晶体管；每条所述字线对应所述字线所在层的多个存储单元，每条所述字线沿平行于所述衬底方向延伸，其中，每条所述字线与对应的多个存储单元中的每个晶体管连接，每个所述晶体管的栅电极为所连接的所述字线的一部分。
  13. 根据权利要求12所述的3D堆叠的半导体器件阵列，其中，与同一字线连接的多个晶体管的半导体层连接为一体式结构；或者，
    与同一字线连接的多个晶体管的半导体层之间相互断开。
  14. 根据权利要求12或13所述的3D堆叠的半导体器件阵列，其中，与同一条字线连接的多个晶体管的栅极绝缘层连接为一体式结构。
  15. 根据权利要求12或13所述的3D堆叠的半导体器件阵列，其中，所述多个3D堆叠的半导体器件包括多条位线，所述多条位线沿第一方向和第二方向阵列分布，所述第二方向与所述字线的延伸方向一致，所述第一方向垂直于所述第二方向；
    多条位线与同一层不同存储单元一一对应，不同层中同一位置的每个存储单元的所述晶体管与同一条位线连接；
    所述3D堆叠的半导体器件阵列还包括：与所述多条位线分别对应的设置在靠近所述衬底一侧的多个位线选通晶体管，以及，设置在所述位线选通晶体管靠近所述衬底一侧的多条公共位线，沿第一方向分布的每行位线对应一条公共位线，所述位线选通晶体管连接对应的所述位线，同一行的位线所连接的位线选通晶体管连接到对应的所述公共位线，所述位线选通晶体管被配置为在开启时将所述公共位线的信号加载到对应的所述位线。
  16. 一种电子设备，其中，包括如权利要求1至11任一所述的3D堆叠的半导体器件，或者，如权利要求12至15任一所述的3D堆叠的半导体器件阵列。
  17. 一种3D堆叠的半导体器件的制造方法，所述3D堆叠的半导体器件包括多个晶体管，分布于不同层沿垂直于衬底方向堆叠；位线，贯穿所述不同层的所述晶体管；所述3D堆叠的半导体器件的制造方法包括：
    提供衬底，在所述衬底上依次交替沉积第一绝缘薄膜和导电薄膜，进行构图形成堆叠结构，所述堆叠结构包括交替设置的第一绝缘层和导电层的堆叠，所述导电层包括预设电极图形；所述预设电极图形包含待形成的所述位线和所述晶体管的第一电极；
    构图形成从所述堆叠结构的顶部贯穿全部导电层的沟槽，所述沟槽对应所述导电层的第一区域的口径大于对应所述第一绝缘层的第二区域的口径，所述沟槽的侧壁露出所述导电层和所述第一绝缘层，所述沟槽使得所述预设电极图形形成所述晶体管的第一电极；所述第一区域包括与所述第二区域在所述衬底的正投影重叠的第二子区域和设置在所述第二子区域朝向所述第一电极一侧的第一子区域；
    在所述沟槽的侧壁依次沉积半导体薄膜、栅绝缘薄膜和栅电极薄膜，刻蚀去除位于所述第二区域和第二子区域的半导体薄膜、栅绝缘薄膜和栅电极薄膜，以及，朝远离所述第二子区域的方向刻蚀所述栅电极薄膜预设厚度，且在所述第一子区域中所述栅电极薄膜被刻蚀的区域填充栅绝缘薄膜，以分别形成所述晶体管的半导体层、栅极绝缘层和栅电极；
    在所述第二区域形成从所述堆叠结构的顶部贯穿全部导电层的通孔，所述通孔露出所述半导体层和所述栅极绝缘层，在所述通孔内沉积填充所述通孔的导电薄膜形成所述位线。
  18. 一种3D堆叠的半导体器件阵列的制造方法，所述3D堆叠的半导体器件阵列包括多个3D堆叠的半导体器件，所述3D堆叠的半导体器件包括多个晶体管，分布于不同层沿垂直于衬底方向堆叠；位线，贯穿所述不同层的所述晶体管，所述3D堆叠的半导体器件阵列的制造方法包括：
    提供衬底，在所述衬底上依次交替沉积第一绝缘薄膜和导电薄膜，进行构图形成堆叠结构，所述堆叠结构包括交替设置的第一绝缘层和导电层的堆叠，所述导电层包括多个预设电极图形；所述预设电极图形包含待形成的所述位线和所述晶体管的第一电极；
    构图形成从所述堆叠结构的顶部贯穿全部导电层的沟槽，所述沟槽对应所述导电层的第一区域的口径大于对应所述第一绝缘层的第二区域的口径，所述沟槽的侧壁露出每个所述预设电极图形和所述第一绝缘层，所述沟槽使得所述多个预设电极图形分别形成所述多个3D堆叠的半导体器件同层的晶体管的第一电极；所述第一区域包括与所述第二区域在所述衬底的正投影重叠的第二子区域和设置在所述第二子区域朝向所述第一电极一侧的第一子区域；
    在所述沟槽的侧壁依次沉积半导体薄膜、栅绝缘薄膜和栅电极薄膜，刻蚀去除位于所述第二区域和所述第二子区域的半导体薄膜、栅绝缘薄膜和栅电极薄膜，以及，朝远离所述第二子区域的方向刻蚀所述栅电极薄膜预设厚度，且在所述第一子区域中所述栅电极薄膜被刻蚀的区域填充栅绝缘薄膜，以分别形成所述多个3D堆叠的半导体器件同层的晶体管的半导体层、栅极绝缘层和字线；
    在所述第二区域形成从所述堆叠结构的顶部贯穿全部导电层的多个间隔设置的通孔，所述通孔露出所述半导体层和所述栅极绝缘层，在所述通孔内沉积填充所述通孔的导电薄膜形成所述位线。
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