WO2024143947A1 - Tantalum carbide-coated material - Google Patents

Tantalum carbide-coated material Download PDF

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WO2024143947A1
WO2024143947A1 PCT/KR2023/019663 KR2023019663W WO2024143947A1 WO 2024143947 A1 WO2024143947 A1 WO 2024143947A1 KR 2023019663 W KR2023019663 W KR 2023019663W WO 2024143947 A1 WO2024143947 A1 WO 2024143947A1
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tantalum carbide
substrate
buffer layer
carbide film
carbide composite
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PCT/KR2023/019663
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French (fr)
Korean (ko)
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조동완
김정일
노형일
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주식회사 티씨케이
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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/32Carbides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02Pretreatment of the material to be coated
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02Pretreatment of the material to be coated
    • C23C16/0272Deposition of sub-layers, e.g. to promote the adhesion of the main coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68757Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material

Definitions

  • a tantalum carbide composite material coated with tantalum carbide (TaC) on the surface of a carbon material generates stress due to the difference in thermal expansion coefficient between the carbon material and the tantalum carbide film, causing cracks and warping, which can cause damage and affect the lifespan of the parts to which it is applied.
  • tantalum carbide Parts coated with tantalum carbide (TaC) use a tantalum carbide composite material coated with tantalum carbide (TaC) on the surface of the carbon material.
  • tantalum carbide (TaC) and tantalum carbide (TaC) are used.
  • Carbon base materials with similar thermal expansion coefficients have been used.
  • the types of carbon substrates with a coefficient of thermal expansion similar to tantalum carbide are limited, so there are problems in applying them to tantalum carbide coating materials.
  • problems such as stress generation, bending, cracking, and peeling may occur.
  • the present disclosure introduces a buffer layer for stress relief between the substrate and the tantalum carbide film to reduce stress, bending, cracking, peeling, etc. of the tantalum carbide coating layer and the carbon substrate.
  • a relaxed tantalum carbide composite can be provided.
  • the present disclosure can provide a semiconductor manufacturing component that includes a tantalum carbide composite incorporating a buffer layer for stress relief and can improve life stability and the stability and process efficiency of the semiconductor manufacturing process.
  • the tantalum carbide composite includes a substrate; and a tantalum carbide film formed on at least one surface of the substrate. It includes a buffer layer between the substrate and the tantalum carbide film; It includes, and the buffer layer may include a material of van der Waals bond.
  • the thickness of the buffer layer may be 1 ⁇ m to 50 ⁇ m.
  • the thickness of the tantalum carbide film may be 10 ⁇ m to 100 ⁇ m.
  • the substrate may include at least one selected from the group consisting of graphene, graphite, and fullerene.
  • the warpage of the tantalum carbide composite may be 10 ⁇ m to 50 ⁇ m.
  • a method of measuring warpage of the tantalum carbide composite (a) Manufacturing a tantalum carbide coated product measuring 200 mm x 3 mm; (b) measuring the height of the product based on the upper half of a CMM measuring machine ( Coordinate Measuring Machine, 3D shape measuring machine); and (c) measuring 10 points at equal intervals of 0°, 60°, and 120°; It is a measurement method that includes a total of 30 points, which may include expressing the deviation of the measured value as bending.
  • the tantalum carbide film may be crack-free or may include cracks with a width of 0.3 ⁇ m to 0.6 ⁇ m.
  • the tantalum carbide composite may reduce the width size of cracks in the tantalum carbide film and reduce the occurrence of warpage by introducing a buffer layer for stress relief between the substrate (e.g., carbon substrate) and the tantalum carbide film.
  • components for semiconductor manufacturing have improved lifetime stability by applying a tantalum carbide composite material that introduces a buffer layer for stress relief between a substrate (e.g., carbon substrate) and a tantalum carbide film, and process stability in the semiconductor manufacturing process. And process efficiency can be improved.
  • Figure 2 exemplarily shows the configuration of a tantalum carbide composite material in which a tantalum carbide film is formed on the entire surface of the substrate, according to one embodiment.
  • Figure 3 shows a cross-sectional SEM image of a tantalum carbide composite, according to one embodiment.
  • FIGS. 4A, 4B, and 4C are SEM images of the surface of the tantalum carbide layer in a tantalum carbide composite, according to an embodiment.
  • FIG. 4A is an SEM image of Comparative Example 1
  • FIG. 4B is a SEM image of Example 4. This is an SEM image
  • Figure 4c is an SEM image of Example 1.
  • the buffer layer 200 may include one or two or more types of van der Waals bond materials.
  • the buffer layer 200 using a material of Van der Waals bond can alleviate the difference in physical properties (e.g., stress due to difference in thermal expansion coefficient) between the substrate 100 and the tantalum carbide film 300.
  • the occurrence of cracks (eg, bending) and peeling can be reduced by relieving stress caused by a difference in thermal expansion coefficient between the substrate 100 and the tantalum carbide film 300.
  • the thickness of the buffer layer 200 may be 1 ⁇ m to 50 ⁇ m.
  • the thickness of the buffer layer is 1 ⁇ m to 5 ⁇ m; 1 ⁇ m to 10 ⁇ m; 1 ⁇ m to 15 ⁇ m; 1 ⁇ m to 20 ⁇ m; 1 ⁇ m to 25 ⁇ m; 1 ⁇ m to 30 ⁇ m; 1 ⁇ m to 35 ⁇ m; 1 ⁇ m to 40 ⁇ m; 1 ⁇ m to 45 ⁇ m; Or it may be 1 ⁇ m to 50 ⁇ m.
  • the atomic ratio of Ta to C in the tantalum carbide film 300 may be 0.9 to 1.34:1, and by adjusting the atomic ratio, the surface energy of the tantalum carbide film is lowered to prevent contaminants from attaching to the process. It is possible to prevent damage to the substrate 100 due to plasma and corrosive gases in the environment (e.g., semiconductor manufacturing process) and improve the lifespan and process stability of parts using tantalum carbide composites.
  • the tantalum carbide film 300 may be heat treated after synthesis and/or deposition (e.g., CVD deposition), for example, at a temperature of 2000 °C to 2500 °C, in an inert gas (e.g., Ar gas) atmosphere. and heat treatment for 1 hour to 20 hours.
  • CVD deposition e.g., CVD deposition
  • an inert gas e.g., Ar gas
  • the tantalum carbide film 300 may have a thickness of 10 ⁇ m to 100 ⁇ m. in some examples 10 ⁇ m to 100 ⁇ m; 10 ⁇ m to 80 ⁇ m; 10 ⁇ m to 60 ⁇ m; 10 ⁇ m to 40 ⁇ m; Or it may be 10 ⁇ m to 20 ⁇ m.
  • the tantalum carbide film 300 may include cracks in at least one of the surface, interior, or contact surface with the buffer layer.
  • the surface of the tantalum carbide film 300 may include cracks.
  • the tantalum carbide film 300 may include microcracks with a width of 0.3 ⁇ m to 0.6 ⁇ m. For example, 0.3 ⁇ m to 0.55 ⁇ m; 0.3 ⁇ m to 0.5 ⁇ m; 0.3 ⁇ m to 0.4 ⁇ m; Alternatively, it may include fine cracks having a width of 0.3 ⁇ m to 0.35 ⁇ m.
  • the crack width refers to measuring the width of a fine crack occurring in a carbon material containing a tantalum carbide coating layer, and images of the crack area are obtained using SEM analysis equipment (e.g. SEM model name: JEOL, JSM-6390). It is observed at 2000x magnification and represents the average of the values measured at 10 points in the vertical direction of the gap between cracks.
  • the tantalum carbide film 300 may be crack-free in at least one of the surface, interior, or contact surface with the buffer layer.
  • the warpage of the tantalum carbide composite may be 10 ⁇ m to 50 ⁇ m. in some examples 10 ⁇ m to 50 ⁇ m; 10 ⁇ m to 40 ⁇ m; 10 ⁇ m to 30 ⁇ m; Or it may be 10 ⁇ m to 20 ⁇ m.
  • the method for measuring warpage of the tantalum carbide composite according to a preferred embodiment of the present invention is (a) Manufacturing a tantalum carbide coated product with a size of 200
  • a measurement method including the step of measuring 10 points at equal intervals may include expressing the deviation of the measured value of a total of 30 points as bending.
  • the coefficient of thermal expansion (CTE) of the tantalum carbide film 300 exceeds 6 x 10 -6 /K; 7 x 10 -6 /K; Or it may be more than 8 x 10 -6 /K.
  • the coefficient of thermal expansion (CTE) of the tantalum carbide film 300 is greater than 6 x 10 -6 /K to 7 x 10 -6 /K; 6.1 x 10 -6 /K to 7 x 10 -6 /K; Or it may be 6.3 x 10 -6 /K to 7 x 10 -6 /K.
  • the coefficient of thermal expansion (CTE) of the substrate 100 is 6 x 10 -6 /K or less; 5 x 10 -6 /K or less; Or it may be 4 x 10 -6 /K or less. In some examples, the coefficient of thermal expansion (CTE) of the substrate 100 may be 4 x 10 -6 /K to 6 x 10 -6 /K.
  • the tantalum carbide composite may include the content mentioned in the description of the tantalum carbide composite mentioned above.
  • the component may be a component used in a semiconductor process.
  • the component may be a component of single crystal SiC/AlN Epitaxy and SiC/AlN Growth process equipment.
  • the thermal expansion coefficient of the graphite substrate is 4.5x10 -6 /K, and a 15 ⁇ m thick pyrolytic carbon layer was deposited on the substrate by CVD deposition, and then a TaC layer was formed on the pyrolytic carbon layer by CVD deposition.
  • the thermal expansion coefficient of the graphite substrate is 4.5x10 -6 /K, and a pyrolytic carbon layer was deposited on the substrate to a thickness of 25 ⁇ m by CVD deposition, and then a TaC layer was formed on the pyrolytic carbon layer by CVD deposition.
  • the thermal expansion coefficient of the graphite substrate is 5.5x10 -6 /K, and a pyrolytic carbon layer was deposited on the substrate to a thickness of 5 ⁇ m by CVD deposition, and then a TaC layer was formed on the pyrolytic carbon layer by CVD deposition.
  • a TaC composite was prepared in the same manner as in Example 4 except that the buffer layer was not formed.

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Abstract

The present disclosure relates to a tantalum carbide-coated material, which may comprise a buffer layer formed on a substrate, and a tantalum carbide film.

Description

탄화탄탈 복합재Tantalum carbide composite
본 개시는 실시 예들에 따른 탄화탄탈 복합재(tantalum carbide coated- material)에 관한 것이다. The present disclosure relates to a tantalum carbide coated-material according to embodiments.
반도체 제조장비에 사용되는 서셉터 부품은, 기존의 반도체 공정에서 사용하던 탄소 소재를 그대로 사용하게 되면, 부식성 가스에 의해 탄소 소재가 식각되는 문제점이 있는바, 탄소 소재의 구조물의 표면에 실리콘카바이드(SiC)나 탄화탄탈(TaC)를 코팅한 부품이 사용되고 있다.Susceptor parts used in semiconductor manufacturing equipment have the problem that the carbon material is etched by corrosive gas when the carbon material used in the existing semiconductor process is used as is, so silicon carbide (silicon carbide) is added to the surface of the carbon material structure. Parts coated with SiC) or tantalum carbide (TaC) are used.
탄소 재료 표면에 탄화탄탈(TaC)을 코팅한 탄화탄탈 복합소재는 탄소 소재와 탄화탄탈막의 열팽차 계수 차이로 인하여 응력이 발생하고 크랙, 휨 등의 발생되어 이를 적용한 부품의 손상, 수명에 영향을 주고 있다.A tantalum carbide composite material coated with tantalum carbide (TaC) on the surface of a carbon material generates stress due to the difference in thermal expansion coefficient between the carbon material and the tantalum carbide film, causing cracks and warping, which can cause damage and affect the lifespan of the parts to which it is applied. is giving
탄화탄탈(TaC)을 코팅한 부품은 탄소 재료 표면에 탄화탄탈(TaC)을 코팅한 탄화탄탈 복합재를 사용하는데, 탄소 기재와 탄화탄탈(TaC)의 응력 감소 및 코팅층 박리를 방지하기 위해서 탄화탄탈과 유사한 열팽창계수를 가지는 탄소 모재를 적용하여 사용해왔다. 하지만, 탄화탄탈과 유사한 열팽창계수를 가지는 탄소 기재의 종류는 제한적이어서 탄화탄탈 코팅 재료에 적용하는데 문제점이 있다. 또한, 탄화탄탈과 유사한 열팽창계수를 가지는 탄소 기재를 적용하더라도, 응력 발생, 휨, 크랙, 박리 등의 문제점이 발생할 수 있다. Parts coated with tantalum carbide (TaC) use a tantalum carbide composite material coated with tantalum carbide (TaC) on the surface of the carbon material. To reduce the stress between the carbon substrate and tantalum carbide (TaC) and prevent peeling of the coating layer, tantalum carbide (TaC) and tantalum carbide (TaC) are used. Carbon base materials with similar thermal expansion coefficients have been used. However, the types of carbon substrates with a coefficient of thermal expansion similar to tantalum carbide are limited, so there are problems in applying them to tantalum carbide coating materials. In addition, even if a carbon substrate having a coefficient of thermal expansion similar to that of tantalum carbide is applied, problems such as stress generation, bending, cracking, and peeling may occur.
이에 상기 언급된 문제점을 해결하기 위해서, 일 실시 예에 따라, 본 개시는 기재 및 탄화탄탈막 간의 응력완화를 위한 버퍼층을 도입하여 탄화탄탈 코팅층과 탄소 기재의 응력 감소, 휨, 크랙, 박리 등이 완화된 탄화탄탈 복합재를 제공할 수 있다. 일 실시 예에 따라, 본 개시는 응력완화를 위한 버퍼층을 도입한 탄화탄탈 복합재를 포함하고, 수명 안정성 및 반도체 제조 공정의 안정성 및 공정 효율을 개선시킬 수 있는, 반도체 제조용 부품을 제공할 수 있다. Accordingly, in order to solve the above-mentioned problem, according to one embodiment, the present disclosure introduces a buffer layer for stress relief between the substrate and the tantalum carbide film to reduce stress, bending, cracking, peeling, etc. of the tantalum carbide coating layer and the carbon substrate. A relaxed tantalum carbide composite can be provided. According to one embodiment, the present disclosure can provide a semiconductor manufacturing component that includes a tantalum carbide composite incorporating a buffer layer for stress relief and can improve life stability and the stability and process efficiency of the semiconductor manufacturing process.
그러나, 본 발명이 해결하고자 하는 과제는 이상에서 언급한 것들로 제한되지 않으며, 언급되지 않은 또 다른 과제들은 아래의 기재로부터 해당 분야 통상의 기술자에게 명확하게 이해될 수 있을 것이다. However, the problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.
일 실시 예에 따라, 탄화탄탈 복합재는 기재; 및 상기 기재의 적어도 일면에 형성된 탄화탄탈막; 을 포함하고, 상기 기재 및 상기 탄화탄탈막 사이에 버퍼층; 을 포함하고, 상기 버퍼층은, 반 데르 발스 결합의 물질을 포함하는 것일 수 있다.According to one embodiment, the tantalum carbide composite includes a substrate; and a tantalum carbide film formed on at least one surface of the substrate. It includes a buffer layer between the substrate and the tantalum carbide film; It includes, and the buffer layer may include a material of van der Waals bond.
일 실시 예에 따라, 상기 반 데르 발스 결합의 물질은 열분해 탄소(Pyrolytic Carbon), BN(Boron Nitride), MoS2, WSe2, ReS2, MoTe2 및 이들의 조합으로 이루어진 군에서 선택된 적어도 하나 이상을 포함하는 것일 수 있다. According to one embodiment, the van der Waals bond material is at least one selected from the group consisting of pyrolytic carbon, BN (Boron Nitride), MoS 2 , WSe 2 , ReS 2 , MoTe 2 , and combinations thereof. It may include.
일 실시 예에 따라, 상기 버퍼층의 두께는 1 ㎛ 내지 50 ㎛인 것일 수 있다. According to one embodiment, the thickness of the buffer layer may be 1 ㎛ to 50 ㎛.
일 실시 예에 따라, 상기 탄화탄탈막 중 Ta 대 C의 원자비는 0.9 내지 1.34인 것일 수 있다. According to one embodiment, the atomic ratio of Ta to C in the tantalum carbide film may be 0.9 to 1.34.
일 실시 예에 따라, 상기 탄화탄탈막은 CVD로 형성된 것일 수 있다. According to one embodiment, the tantalum carbide film may be formed by CVD.
일 실시 예에 따라, 상기 탄화탄탈막의 두께는 10 ㎛ 내지 100 ㎛인 것일 수 있다. According to one embodiment, the thickness of the tantalum carbide film may be 10 ㎛ to 100 ㎛.
일 실시 예에 따라, 상기 기재는, 그래핀, 흑연 및 플러렌으로 이루어진 군으로부터 선택된 적어도 하나 이상을 포함하는 것일 수 있다. According to one embodiment, the substrate may include at least one selected from the group consisting of graphene, graphite, and fullerene.
일 실시 예에 따라, 상기 탄화탄탈 복합재의 휨은 10 ㎛ 내지 50 ㎛인 것일 수 있다. 일 실시 예에 따라, 상기 탄화탄탈 복합재의 휨 측정방법으로서 (a)
Figure PCTKR2023019663-appb-img-000001
200 mm X 3 mm 크기의 탄화탄탈 코팅 제품 제작하는 단계; (b) CMM 측정기(Coordinate Measuring Machine, 3차원 형상 측정기)의 상반을 기준으로 제품의 높이를 측정하는 단계; 및 (c) 0°, 60° 및 120° 간격으로 동일 간격으로 10 point 씩 측정하는 단계; 를 포함하는 측정방법이며, 이는 총 30 point 측정된 값의 편차를 휨으로 표현하는 것을 포함할 수 있다.
According to one embodiment, the warpage of the tantalum carbide composite may be 10 ㎛ to 50 ㎛. According to one embodiment, as a method of measuring warpage of the tantalum carbide composite, (a)
Figure PCTKR2023019663-appb-img-000001
Manufacturing a tantalum carbide coated product measuring 200 mm x 3 mm; (b) measuring the height of the product based on the upper half of a CMM measuring machine ( Coordinate Measuring Machine, 3D shape measuring machine); and (c) measuring 10 points at equal intervals of 0°, 60°, and 120°; It is a measurement method that includes a total of 30 points, which may include expressing the deviation of the measured value as bending.
일 실시 예에 따라, 상기 탄화탄탈막은 크랙-프리 또는 폭이 0.3 ㎛ 내지 0.6 ㎛의 크랙을 포함하는 것일 수 있다. According to one embodiment, the tantalum carbide film may be crack-free or may include cracks with a width of 0.3 ㎛ to 0.6 ㎛.
일 실시 예에 따라, 상기 탄화탄탈막의 열팽창계수(CTE)는 6 x 10-6/K 초과이고, 상기 기재의 열팽창계수(CTE)는 6 x 10-6/K 이하인 것일 수 있다. According to one embodiment, the coefficient of thermal expansion (CTE) of the tantalum carbide film may be greater than 6 x 10 -6 /K, and the coefficient of thermal expansion (CTE) of the substrate may be 6 x 10 -6 /K or less.
일 실시 예에 따라, 탄화탄탈 복합재는 기재(예: 탄소 기재)와 탄화탄탈막 사이에 응력완화를 위한 버퍼층을 도입하여 탄화탄탈막의 크랙의 폭 크기를 줄이고, 휨 발생을 낮출 수 있다. According to one embodiment, the tantalum carbide composite may reduce the width size of cracks in the tantalum carbide film and reduce the occurrence of warpage by introducing a buffer layer for stress relief between the substrate (e.g., carbon substrate) and the tantalum carbide film.
일 실시 예에 따라, 반도체 제조용 부품은 기재(예: 탄소 기재)와 탄화탄탈막 사이에 응력완화를 위한 버퍼층을 도입한 탄화탄탈 복합재를 적용하여 수명 안정성이 향상되고, 및 반도체 제조 공정에서 공정 안정성 및 공정 효율을 개선시킬 수 있다. According to one embodiment, components for semiconductor manufacturing have improved lifetime stability by applying a tantalum carbide composite material that introduces a buffer layer for stress relief between a substrate (e.g., carbon substrate) and a tantalum carbide film, and process stability in the semiconductor manufacturing process. And process efficiency can be improved.
도 1은, 일 실시 예에 따라, 기재의 일면에 탄화탄탈막이 형성된 탄화탄탈 복합재의 구성을 예시적으로 나타낸 것이다.Figure 1 exemplarily shows the configuration of a tantalum carbide composite material in which a tantalum carbide film is formed on one surface of a substrate, according to one embodiment.
도 2는, 일 실시 예에 따라, 기재의 전체 면에 탄화탄탈막이 형성된 탄화탄탈 복합재의 구성을 예시적으로 나타낸 것이다.Figure 2 exemplarily shows the configuration of a tantalum carbide composite material in which a tantalum carbide film is formed on the entire surface of the substrate, according to one embodiment.
도 3은, 일 실시 예에 따라, 탄화탄탈 복합재의 단면 SEM 이미지를 나타낸 것이다. Figure 3 shows a cross-sectional SEM image of a tantalum carbide composite, according to one embodiment.
도 4a, 도 4b 및 도 4c는, 일 실시 예에 따라, 탄화탄탈 복합재에서 탄화탄탈층 표면에 대한 SEM 이미지를 측정한 것으로 도 4a는 비교예 1의 SEM 이미지이며, 도 4b는 실시예 4의 SEM 이미지이고, 도 4c는 실시예 1의 SEM 이미지이다. FIGS. 4A, 4B, and 4C are SEM images of the surface of the tantalum carbide layer in a tantalum carbide composite, according to an embodiment. FIG. 4A is an SEM image of Comparative Example 1, and FIG. 4B is a SEM image of Example 4. This is an SEM image, and Figure 4c is an SEM image of Example 1.
도 5는, 일 실시 예에 따라, 탄화탄탈 복합재의 미세 크랙의 폭 크기를 나타낸 것이다. Figure 5 shows the width size of fine cracks in a tantalum carbide composite material, according to one embodiment.
도6은, 일 실시 예에 따라, 탄화탄탈 복합재의 미세 크랙의 휨(Warpage) 크기를 나타낸 것이다. Figure 6 shows the warpage size of micro cracks in a tantalum carbide composite material, according to one embodiment.
이하 첨부된 도면을 참조하여 본 발명의 실시예들을 상세히 설명한다. 본 발명을 설명함에 있어서, 관련된 공지 기능 또는 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략할 것이다. 또한, 본 명세서에서 사용되는 용어들은 본 발명의 바람직한 실시예를 적절히 표현하기 위해 사용된 용어들로서, 이는 사용자, 운용자의 의도 또는 본 발명이 속하는 분야의 관례 등에 따라 달라질 수 있다. 따라서, 본 용어들에 대한 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다. 각 도면에 제시된 동일한 참조 부호는 동일한 부재를 나타낸다.Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. In describing the present invention, if a detailed description of a related known function or configuration is judged to unnecessarily obscure the gist of the present invention, the detailed description will be omitted. Additionally, the terms used in this specification are terms used to appropriately express preferred embodiments of the present invention, and may vary depending on the intention of the user, operator, or customs in the field to which the present invention belongs. Therefore, definitions of these terms should be made based on the content throughout this specification. The same reference numerals in each drawing indicate the same members.
명세서 전체에서, 어떤 부재가 다른 부재 "상에" 위치하고 있다고 할 때, 이는 어떤 부재가 다른 부재에 접해 있는 경우뿐 아니라 두 부재 사이에 또 다른 부재가 존재하는 경우도 포함한다.Throughout the specification, when a member is said to be located “on” another member, this includes not only cases where a member is in contact with another member, but also cases where another member exists between the two members.
명세서 전체에서, 어떤 부분이 어떤 구성요소를 "포함"한다고 할 때, 이는 다른 구성요소를 제외하는 것이 아니라 다른 구성 요소를 더 포함할 수 있는 것을 의미한다. Throughout the specification, when a part “includes” a certain component, this does not mean excluding other components, but rather means that it can further include other components.
이하, 본 발명의 탄화탄탈 복합재에 대하여 실시예 및 도면을 참조하여 구체적으로 설명하도록 한다. 그러나, 본 발명이 이러한 실시예 및 도면에 제한되는 것은 아니다. Hereinafter, the tantalum carbide composite material of the present invention will be described in detail with reference to examples and drawings. However, the present invention is not limited to these examples and drawings.
일 실시 예에 따라, 도 1은 탄화탄탈 복합재를 나타낸 것으로, 도 1에서 탄화탄탈 복합재는 기재(100); 및 기재(100)의 적어도 일면에 형성된 탄화탄탈막(300); 을 포함하고, 기재(100) 및 탄화탄탈막(300) 사이에 버퍼층(200); 을 포함할 수 있다. 일 예로, 도 1을 참조하면, 탄화탄탈막(300)은 기재(100)의 상단면, 하단면 또는 이 둘에 형성될 수 있다. 일 예로, 도 2를 참조하면, 탄화탄탈막(300)은 기재(100)의 전체 면에 형성될 수 있다. According to one embodiment, Figure 1 shows a tantalum carbide composite. In Figure 1, the tantalum carbide composite includes a substrate 100; and a tantalum carbide film 300 formed on at least one surface of the substrate 100; It includes a buffer layer 200 between the substrate 100 and the tantalum carbide film 300; may include. As an example, referring to FIG. 1, the tantalum carbide film 300 may be formed on the top surface, the bottom surface, or both of the substrate 100. As an example, referring to FIG. 2, the tantalum carbide film 300 may be formed on the entire surface of the substrate 100.
일 실시 예에 따라, 기재(100)는 탄화탄탈 복합재의 용도에 따라 적절하게 선택될 수 있으며, 예를 들어, 탄화탄탈막(300)과 열팽창계수를 고려하여 탄소 기재일 수 있다. 어떤 예에서, 기재(100)는 그래핀, 흑연 및 플러렌으로 이루어진 군으로부터 선택된 적어도 하나 이상을 포함할 수 있다. According to one embodiment, the substrate 100 may be appropriately selected depending on the purpose of the tantalum carbide composite material, and for example, may be a carbon substrate in consideration of the tantalum carbide film 300 and the thermal expansion coefficient. In some examples, the substrate 100 may include at least one selected from the group consisting of graphene, graphite, and fullerene.
일 실시 예에 따라, 기재(100)의 두께는 1 mm(밀리미터) 내지 10 mm일 수 있다. 어떤 예에서 1 mm 내지 10 mm; 1 mm 내지 8 mm; 1 mm 내지 6 mm; 1 mm 내지 4 mm; 또는 1 mm 내지 2 mm일 수 있다. 어떤 예에서, 언급된 기재(100)의 두께의 범위 내에 포함되면 탄화탄탈막(300) 증착 후 기재(100)의 변형을 최소화시키고, 버퍼층(200)을 도입한 탄화탄탈 복합재를 적용한 부품의 수명 및 공정 안정성을 향상시킬 수 있다. According to one embodiment, the thickness of the substrate 100 may be 1 mm (millimeter) to 10 mm. in some examples 1 mm to 10 mm; 1 mm to 8 mm; 1 mm to 6 mm; 1 mm to 4 mm; Or it may be 1 mm to 2 mm. In some examples, if the thickness of the substrate 100 is within the mentioned range, deformation of the substrate 100 after deposition of the tantalum carbide film 300 is minimized, and the lifespan of the component using the tantalum carbide composite incorporating the buffer layer 200 is increased. And process stability can be improved.
일 실시 예에 따라, 버퍼층(200)은 반 데르 발스(Van der Waals) 결합의 물질을 1종 또는 2종 이상을 포함할 수 있다. 어떤 예에서 반 데르 발스(Van der Waals) 결합의 물질을 적용한 버퍼층(200)은 기재(100) 및 탄화탄탈막(300) 간의 물성 차이(예: 열팽창 계수 차이에 따른 응력)를 완화시킬 수 있다. 예를 들어, 기재(100) 및 탄화탄탈막(300) 간의 열팽창 계수 차이에 따른 응력을 완화시켜 크랙(예: 휨) 및 박리의 발생을 감소시킬 수 있다. According to one embodiment, the buffer layer 200 may include one or two or more types of van der Waals bond materials. In some examples, the buffer layer 200 using a material of Van der Waals bond can alleviate the difference in physical properties (e.g., stress due to difference in thermal expansion coefficient) between the substrate 100 and the tantalum carbide film 300. . For example, the occurrence of cracks (eg, bending) and peeling can be reduced by relieving stress caused by a difference in thermal expansion coefficient between the substrate 100 and the tantalum carbide film 300.
일 실시 예에 따라, 반 데르 발스(Van der Waals) 결합의 물질은 열분해탄소(Pyrolytic Carbon), BN(예: 육방정계 질화붕소(hexagonal boron nitride, h-BN)), MoS2, WSe2, ReS2, MoTe2 및 이들의 조합으로 이루어진 군에서 선택된 적어도 하나 이상을 포함할 수 있다. 어떤 예에서 열분해 탄소는 탄화수소(CxHy)(여기서 x와 y는 자연수이고 x는 1<x<6)에서 선택된 적어도 하나 이상을 포함하는 탄소계 물질을 열분해하여 형성된 것일 수 있다. 예를 들어, 탄화수소는 프로판(C3H8), 부탄(C4H10), 프로필렌(C3H6), 아세틸렌(C2H2) 및 이들의 조합에서 선택될 수 있다. 예를 들어, 열분해 탄소는 1100 ℃ 내지 1800 ℃의 온도(예: 증착 온도, CVD 증착 온도, 또는 열처리 온도)에서 탄화수소 가스를 열분해시켜 생성된 탄소계 물질일 수 있다. According to one embodiment, the material of Van der Waals bond is Pyrolytic Carbon, BN (e.g., hexagonal boron nitride (h-BN)), MoS 2 , WSe 2 , It may include at least one selected from the group consisting of ReS 2 , MoTe 2 and combinations thereof. In some examples, pyrolytic carbon may be formed by pyrolyzing a carbon-based material containing at least one selected from hydrocarbons (C x H y ) (where x and y are natural numbers and x is 1<x<6). For example, the hydrocarbon may be selected from propane (C 3 H 8 ), butane (C 4 H 10 ), propylene (C 3 H 6 ), acetylene (C 2 H 2 ), and combinations thereof. For example, pyrolytic carbon may be a carbon-based material produced by pyrolyzing hydrocarbon gas at a temperature of 1100°C to 1800°C (e.g., deposition temperature, CVD deposition temperature, or heat treatment temperature).
일 실시 예에 따라, 버퍼층(200)의 두께는 1 ㎛ 내지 50 ㎛일 수 있다. 어떤 예에서 버퍼층의 두께는 1 ㎛ 내지 5 ㎛; 1 ㎛ 내지 10 ㎛; 1 ㎛ 내지 15 ㎛; 1 ㎛ 내지 20 ㎛; 1 ㎛ 내지 25 ㎛; 1 ㎛ 내지 30 ㎛; 1 ㎛ 내지 35 ㎛; 1 ㎛ 내지 40 ㎛; 1 ㎛ 내지 45 ㎛; 또는 1 ㎛ 내지 50 ㎛일 수 있다. 어떤 예에서 버퍼층의 두께는 2 ㎛ 내지 5 ㎛; 2 ㎛ 내지 10 ㎛; 2 ㎛ 내지 13 ㎛; 2 ㎛ 내지 17 ㎛; 2 ㎛ 내지 25 ㎛; 2 ㎛ 내지 32 ㎛; 2 ㎛ 내지 41 ㎛; 또는 2 ㎛ 내지 48 ㎛일 수 있다. 어떤 예에서 5 ㎛ 내지 12 ㎛; 5 ㎛ 내지 23 ㎛; 5 ㎛ 내지 34 ㎛; 또는 5 ㎛ 내지 43 ㎛일 수 있다. 어떤 예에서 버퍼층의 두께는 상기 범위 내에서 기재(100)과 탄화탄탈막(300) 사이의 열팽창계면 차이에 의한 응력을 감소시켜 탄화탄탈막(300)에서 크랙, 핀홀 등의 발생을 방지하고, 탄화탄탈 복합재가 적용된 부품의 수명 및 공정 안정성을 향상시킬 수 있다. According to one embodiment, the thickness of the buffer layer 200 may be 1 ㎛ to 50 ㎛. In some examples the thickness of the buffer layer is 1 μm to 5 μm; 1 μm to 10 μm; 1 μm to 15 μm; 1 μm to 20 μm; 1 μm to 25 μm; 1 μm to 30 μm; 1 μm to 35 μm; 1 μm to 40 μm; 1 μm to 45 μm; Or it may be 1 μm to 50 μm. In some examples the thickness of the buffer layer is 2 μm to 5 μm; 2 μm to 10 μm; 2 μm to 13 μm; 2 μm to 17 μm; 2 μm to 25 μm; 2 μm to 32 μm; 2 μm to 41 μm; or 2 μm to 48 μm. in some examples 5 μm to 12 μm; 5 μm to 23 μm; 5 μm to 34 μm; Or it may be 5 μm to 43 μm. In some examples, the thickness of the buffer layer is within the above range to reduce the stress caused by the difference in thermal expansion interface between the substrate 100 and the tantalum carbide film 300 to prevent the occurrence of cracks, pinholes, etc. in the tantalum carbide film 300, The lifespan and process stability of parts using tantalum carbide composites can be improved.
일 실시 예에 따라, 버퍼층(200) 대 탄화탄탈막(300)의 두께비는 0.1 : 1 내지 0.01 : 1인 것일 수 있다. 어떤 예에서 버퍼층(200) 대 탄화탄탈막(300)의 두께비는, 바람직하게는 0.08 : 1 내지 0.05 : 1일 수 있다. 어떤 예에서 언급된 두께비 범위에 포함되면 기재(100)과 탄화탄탈막(300) 사이의 열팽창계면 차이에 의한 응력을 감소시켜 탄화탄탈막(300)에서 크랙, 핀홀 등의 발생을 방지하고, 탄화탄탈 복합재가 적용된 부품의 수명 및 공정 안정성을 향상시킬 수 있다. According to one embodiment, the thickness ratio of the buffer layer 200 to the tantalum carbide film 300 may be 0.1:1 to 0.01:1. In some examples, the thickness ratio of the buffer layer 200 to the tantalum carbide film 300 may preferably be 0.08:1 to 0.05:1. If it is within the thickness ratio range mentioned in some examples, the stress caused by the difference in thermal expansion interface between the substrate 100 and the tantalum carbide film 300 is reduced to prevent the occurrence of cracks, pinholes, etc. in the tantalum carbide film 300, and carbonization is prevented. The lifespan and process stability of parts using tantalum composites can be improved.
일 예로, 탄화탄탈막(300) 중 Ta 대 C의 원자비는, 0.9 내지 1.34 : 1일 수 있으며, 상기 원자비를 조절하여 탄화탄탈막의 표면 에너지를 낮추어 오염물질이 부착되는 것을 방지하고, 공정 환경(예: 반도체 제조 공정)에서 플라즈마, 부식성 가스에 의한 기재(100)의 손상을 방지하고 탄화탄탈 복합재를 적용한 부품의 수명 및 공정 안정성을 향상시킬 수 있다. As an example, the atomic ratio of Ta to C in the tantalum carbide film 300 may be 0.9 to 1.34:1, and by adjusting the atomic ratio, the surface energy of the tantalum carbide film is lowered to prevent contaminants from attaching to the process. It is possible to prevent damage to the substrate 100 due to plasma and corrosive gases in the environment (e.g., semiconductor manufacturing process) and improve the lifespan and process stability of parts using tantalum carbide composites.
일 예로, 탄화탄탈막(300)은 합성 및/또는 증착(예: CVD 증착) 이후에 열처리될 수 있으며, 예를 들어, 2000 °C 내지 2500 °C 온도, 비활성 가스(예: Ar 가스) 분위기 및 1 시간 내지 20 시간 동안 열처리될 수 있다. As an example, the tantalum carbide film 300 may be heat treated after synthesis and/or deposition (e.g., CVD deposition), for example, at a temperature of 2000 °C to 2500 °C, in an inert gas (e.g., Ar gas) atmosphere. and heat treatment for 1 hour to 20 hours.
일 예로, 탄화탄탈막(300)은, 10 ㎛ 내지 100 ㎛ 두께를 포함할 수 있다. 어떤 예에서 10 ㎛ 내지 100 ㎛; 10 ㎛ 내지 80 ㎛; 10 ㎛ 내지 60 ㎛; 10 ㎛ 내지 40 ㎛; 또는 10 ㎛ 내지 20 ㎛일 수 있다. As an example, the tantalum carbide film 300 may have a thickness of 10 ㎛ to 100 ㎛. in some examples 10 μm to 100 μm; 10 μm to 80 μm; 10 μm to 60 μm; 10 μm to 40 μm; Or it may be 10 μm to 20 μm.
일 예로, 탄화탄탈막(300)의 표면, 내부 또는 버퍼층과 접촉 면 중 적어도 하나 이상에서 크랙을 포함할 수 있다. 어떤 예에서 탄화탄탈막(300)의 표면면에서 크랙을 포함할 수 있다. 어떤 예에서 탄화탄탈막(300)은 0.3 ㎛ 내지 0.6 ㎛의 폭을 갖는 미세 크랙을 포함할 수 있다. 예를 들어, 0.3 ㎛ 내지 0.55 ㎛; 0.3 ㎛ 내지 0.5 ㎛; 0.3 ㎛ 내지 0.4 ㎛; 또는 0.3 ㎛ 내지 0.35 ㎛의 폭을 갖는 미세 크랙을 포함할 수 있다. 어떤 예에서 크랙의 폭은 탄화탄탈 코팅층이 포함된 탄소재료에서 발생되는 미세 크랙의 폭을 측정하는 것을 말하며 SEM 분석 설비(예: SEM 모델명 : JEOL, JSM-6390)를 이용하여 크랙 부위의 이미지를 2000배율로 관찰하고 크랙 사이 갭(Gap)을 수직 방향으로 10 Point 측정한 값의 평균을 나타낸다. 어떤 예에서 탄화탄탈막(300)의 표면, 내부 또는 버퍼층과 접촉 면 중 적어도 하나 이상에서 크랙 프리일 수 있다. For example, the tantalum carbide film 300 may include cracks in at least one of the surface, interior, or contact surface with the buffer layer. In some examples, the surface of the tantalum carbide film 300 may include cracks. In some examples, the tantalum carbide film 300 may include microcracks with a width of 0.3 ㎛ to 0.6 ㎛. For example, 0.3 μm to 0.55 μm; 0.3 μm to 0.5 μm; 0.3 μm to 0.4 μm; Alternatively, it may include fine cracks having a width of 0.3 ㎛ to 0.35 ㎛. In some examples, the crack width refers to measuring the width of a fine crack occurring in a carbon material containing a tantalum carbide coating layer, and images of the crack area are obtained using SEM analysis equipment (e.g. SEM model name: JEOL, JSM-6390). It is observed at 2000x magnification and represents the average of the values measured at 10 points in the vertical direction of the gap between cracks. In some examples, the tantalum carbide film 300 may be crack-free in at least one of the surface, interior, or contact surface with the buffer layer.
일 실시 예에 따라, 탄화탄탈 복합재의 휨은 10 ㎛ 내지 50 ㎛일 수 있다. 어떤 예에서 10 ㎛ 내지 50 ㎛; 10 ㎛ 내지 40 ㎛; 10 ㎛ 내지 30 ㎛; 또는 10 ㎛ 내지 20 ㎛일 수 있다. 본 발명의 바람직한 실시예에 따른 상기 탄화탄탈 복합재의 휨 측정 방법은 (a)
Figure PCTKR2023019663-appb-img-000002
200 X 3mm 크기의 탄화탄탈 코팅 제품 제작하는 단계;와 (b) CMM(3차원 형상) 측정기의 상반을 기준으로 제품의 높이를 측정하는 단계;와 (c) 0°, 60°, 120° 간격으로 동일 간격으로 10 point 씩 측정하는 단계;를 포함하는 측정방법으로 총 30 point 측정된 값의 편차를 휨으로 표현하는 것을 포함하는 것일 수 있다.
According to one embodiment, the warpage of the tantalum carbide composite may be 10 ㎛ to 50 ㎛. in some examples 10 μm to 50 μm; 10 μm to 40 μm; 10 μm to 30 μm; Or it may be 10 μm to 20 μm. The method for measuring warpage of the tantalum carbide composite according to a preferred embodiment of the present invention is (a)
Figure PCTKR2023019663-appb-img-000002
Manufacturing a tantalum carbide coated product with a size of 200 A measurement method including the step of measuring 10 points at equal intervals may include expressing the deviation of the measured value of a total of 30 points as bending.
일 실시예에 따라, 탄화탄탈막(300)의 열팽창계수(CTE, Coefficient of Thermal Expansion)는 6 x 10-6/K 초과; 7 x 10-6/K; 또는 8 x 10-6/K이상일 수 있다. 어떤 예에서 탄화탄탈막(300)의 열팽창계수(CTE)는 6 x 10-6/K 초과 내지 7 x 10-6/K; 6.1 x 10-6/K 내지 7 x 10-6/K; 또는 6.3 x 10-6/K 내지 7 x 10-6/K일 수 있다. According to one embodiment, the coefficient of thermal expansion (CTE) of the tantalum carbide film 300 exceeds 6 x 10 -6 /K; 7 x 10 -6 /K; Or it may be more than 8 x 10 -6 /K. In some examples, the coefficient of thermal expansion (CTE) of the tantalum carbide film 300 is greater than 6 x 10 -6 /K to 7 x 10 -6 /K; 6.1 x 10 -6 /K to 7 x 10 -6 /K; Or it may be 6.3 x 10 -6 /K to 7 x 10 -6 /K.
일 실시예에 따라, 기재(100)의 열팽창계수(CTE)는 6 x 10-6/K 이하; 5 x 10-6/K 이하; 또는 4 x 10-6/K 이하인 것일 수 있다. 어떤 예에서 기재(100)의 열팽창계수(CTE)는 4 x 10-6/K 내지 6 x 10-6/K일 수 있다. According to one embodiment, the coefficient of thermal expansion (CTE) of the substrate 100 is 6 x 10 -6 /K or less; 5 x 10 -6 /K or less; Or it may be 4 x 10 -6 /K or less. In some examples, the coefficient of thermal expansion (CTE) of the substrate 100 may be 4 x 10 -6 /K to 6 x 10 -6 /K.
일 실시 예에 따라, 기재(100)와 탄화탄탈막(300) 사이의 열팽창계수(CTE) 차이를 조절하여 탄화탄탈 복합재가 적용된 부품(예: 반도체 제조 부품)(예: 플라즈마 공정용 부품)의 고온, 플라즈마, 부식 가스 등과 같은 극한 환경에서 기재를 보호하고 부품의 수명 및 공정 안정성을 향상시킬 수 있다. 어떤 예에서, 기재(100)와 탄화탄탈막(300) 사이의 열팽창계수차이가 있으나, 버퍼층(200)의 도입으로 응력 완화를 유도하여 탄화탄탈막(300)의 크랙, 박리 등을 방지하고, 이를 적용된 부품(예: 반도체 제조 부품)(예: 플라즈마 공정용 부품)의 고온, 플라즈마, 부식 가스 등을 포함하는 공정 환경에서 기재를 보호하고 부품의 수명 및 공정 안정성을 향상시킬 수 있다. According to one embodiment, the difference in coefficient of thermal expansion (CTE) between the substrate 100 and the tantalum carbide film 300 is adjusted to control the size of parts (e.g., semiconductor manufacturing parts) (e.g., plasma process parts) to which the tantalum carbide composite is applied. It can protect substrates in extreme environments such as high temperatures, plasma, and corrosive gases, and improve component lifespan and process stability. In some examples, there is a difference in thermal expansion coefficient between the substrate 100 and the tantalum carbide film 300, but the introduction of the buffer layer 200 induces stress relief to prevent cracking and peeling of the tantalum carbide film 300, It can protect the substrate of the applied parts (e.g. semiconductor manufacturing parts) (e.g. plasma process parts) in a process environment containing high temperature, plasma, corrosive gas, etc. and improve the lifespan and process stability of the parts.
일 실시 예에 따라, 본 개시의 탄화탄탈 복합재를 포함하는 부품을 제공할 수 있다. 일 예로, 탄화탄탈 복합재는 앞서 언급한 탄화탄탈 복합재에 대한 설명에서 언급한 내용을 포함할 수 있다. 일 예로, 부품은, 반도체 공정에 사용되는 부품 일 수 있다. 예를 들어, 상기 부품은, 단결정 SiC/AlN Epitaxy 및 SiC/AlN Growth 공정 설비의 부품인 것일 수 있다. According to one embodiment, a part containing the tantalum carbide composite material of the present disclosure may be provided. As an example, the tantalum carbide composite may include the content mentioned in the description of the tantalum carbide composite mentioned above. As an example, the component may be a component used in a semiconductor process. For example, the component may be a component of single crystal SiC/AlN Epitaxy and SiC/AlN Growth process equipment.
본 문서에서 기재된 수치 범위는 본 발명의 목적 및 범위를 벗어나지 않는다면 상기 범위 내에 특정 수치에 대해 이하, 이상, 미만 및/또는 초과로 표시 또는 해석될 수 있다. 본 문서에서 기재된 "적어도 하나 이상"은 하나 또는 둘 이상의 혼합을 의미할 수 있다. The numerical range described in this document may be expressed or interpreted as less than, more than, less than, and/or more than a specific value within the range, as long as it does not deviate from the purpose and scope of the present invention. As used herein, “at least one or more” may mean one or a mixture of two or more.
이하, 실시예 및 비교예에 의하여 본 발명을 더욱 상세히 설명하고자 한다. 단, 하기 실시예는 본 발명을 예시하기 위한 것일 뿐, 본 발명의 내용이 하기 실시예에 한정되는 것은 아니다.Hereinafter, the present invention will be described in more detail through examples and comparative examples. However, the following examples are only for illustrating the present invention, and the content of the present invention is not limited to the following examples.
실시예 1 Example 1
그라파이트 기재의 열팽창계수는 4.5x10-6/K이고 기재 상에 열분해 탄소층을 CVD 증착법으로 5 ㎛ 두께로 증착한 이후 열분해 탄소층 상에 CVD 증착법으로 TaC층을 형성하였다. The thermal expansion coefficient of the graphite substrate is 4.5x10 -6 /K, and a pyrolytic carbon layer was deposited on the substrate to a thickness of 5 ㎛ by CVD deposition, and then a TaC layer was formed on the pyrolytic carbon layer by CVD deposition.
실시예 2Example 2
그라파이트 기재의 열팽창계수는 4.5x10-6/K이고 기재 상에 열분해 탄소층을 CVD 증착법으로 15㎛ 두께로 증착한 이후 열분해 탄소층 상에 CVD 증착법으로 TaC층을 형성하였다. The thermal expansion coefficient of the graphite substrate is 4.5x10 -6 /K, and a 15㎛ thick pyrolytic carbon layer was deposited on the substrate by CVD deposition, and then a TaC layer was formed on the pyrolytic carbon layer by CVD deposition.
실시예 3Example 3
그라파이트 기재의 열팽창계수는 4.5x10-6/K이고 기재 상에 열분해 탄소층을 CVD 증착법으로 25㎛ 두께로 증착한 이후 열분해 탄소층 상에 CVD 증착법으로 TaC층을 형성하였다. The thermal expansion coefficient of the graphite substrate is 4.5x10 -6 /K, and a pyrolytic carbon layer was deposited on the substrate to a thickness of 25㎛ by CVD deposition, and then a TaC layer was formed on the pyrolytic carbon layer by CVD deposition.
실시예 4Example 4
그라파이트 기재의 열팽창계수는 5.5x10-6/K이고 기재 상에 열분해 탄소층을 CVD 증착법으로 5 ㎛ 두께로 증착한 이후 열분해 탄소층 상에 CVD 증착법으로 TaC층을 형성하였다.The thermal expansion coefficient of the graphite substrate is 5.5x10 -6 /K, and a pyrolytic carbon layer was deposited on the substrate to a thickness of 5 ㎛ by CVD deposition, and then a TaC layer was formed on the pyrolytic carbon layer by CVD deposition.
비교예 1Comparative Example 1
실시예 1에서 버퍼층을 형성하지 않는 것 외에는 동일한 방법으로 TaC 복합재를 제조하였다. A TaC composite was prepared in the same manner as in Example 1 except that the buffer layer was not formed.
비교예 2Comparative Example 2
실시예 4에서 버퍼층을 형성하지 않는 것 외에는 동일한 방법으로 TaC 복합재를 제조하였다.A TaC composite was prepared in the same manner as in Example 4 except that the buffer layer was not formed.
실시예 1에서 제조된 TaC 복합재의 단면 관찰은 SEM(Scanning Electron Microscope) 이미지를 측정하여 관찰하였다. 그 결과는 도 3에 나타내었다. 도 3에서 그라파이트 기재 상에 열분해 탄소층/TaC층이 형성된 것을 확인할 수 있다. The cross-section of the TaC composite prepared in Example 1 was observed by measuring SEM ( Scanning Electron Microscope) images. The results are shown in Figure 3. In Figure 3, it can be seen that a pyrolytic carbon layer/TaC layer was formed on the graphite substrate.
표면 미세구조 분석Surface microstructure analysis
실시예 및 비교예에서 제조된 TaC의 표면 미세구조를 SEM으로 관찰하였으며, 크랙 폭에 대한 결과는 도 4a, 도 4b, 도 4c 및 표 1에 나타내었다The surface microstructure of TaC prepared in Examples and Comparative Examples was observed using SEM, and the crack width results are shown in Figures 4a, 4b, 4c, and Table 1.
구분division 비교예 1Comparative Example 1 비교예 2Comparative Example 2 실시예 1Example 1 실시예 2Example 2 실시예 3Example 3 실시예 4Example 4
기재 열팽창계수Substrate thermal expansion coefficient 4.5x10-6/K4.5x10 -6 /K 5.5x10-6/K5.5x10 -6 /K 4.5x10-6/K4.5x10 -6 /K 4.5x10-6/K4.5x10 -6 /K 4.5x10-6/K4.5x10 -6 /K 5.5x10-6/K5.5x10 -6 /K
버퍼층buffer layer 없음doesn't exist 없음doesn't exist 있음has exist 있음has exist 있음has exist 있음has exist
버퍼층의 두께Buffer layer thickness -- -- 5㎛5㎛ 10㎛10㎛ 25㎛25㎛ 5㎛5㎛
TaC 결정립계 표면 상에 발생한 크랙의 평균 폭(㎛)Average width of cracks occurring on the TaC grain boundary surface (㎛) 3.33.3 1.11.1 0.360.36 0.510.51 0.550.55 Crack FreeCrack Free
휨 측정Deflection measurement
실시예 및 비교예의 복합재의 휨을 측정하였다. 그 결과는 표 2에 나타내었다. The warpage of the composite materials of Examples and Comparative Examples was measured. The results are shown in Table 2.
휨 측정 방법How to measure warpage
Figure PCTKR2023019663-appb-img-000003
200 X 3mm 크기의 탄화탄탈 코팅 제품 제작하고, CMM 측정기의 상반을 기준으로 제품의 높이를 측정하였다. 즉, 제품의 높이는 0°, 60° 및 120° 간격에서 각각 동일 간격으로 10 point 씩 측정하였다. 30 point 측정된 값의 편차를 Warpage로 표현하였다.
Figure PCTKR2023019663-appb-img-000003
A tantalum carbide coated product measuring 200 That is, the height of the product was measured at 10 points at equal intervals of 0°, 60°, and 120°. The deviation of the 30 point measured value was expressed as warpage.
구분division 비교예 1Comparative Example 1 실시예 1Example 1 실시예 2Example 2 실시예 3Example 3
기재 열팽창계수Substrate thermal expansion coefficient 4.5x10-6/K4.5x10 -6 /K 4.5x10-6/K4.5x10 -6 /K 4.5x10-6/K4.5x10 -6 /K 4.5x10-6/K4.5x10 -6 /K
버퍼층buffer layer 없음doesn't exist 있음has exist 있음has exist 있음has exist
버퍼층의 두께Buffer layer thickness -- 5㎛5㎛ 15㎛15㎛ 25㎛25㎛
warp Warpage
(㎛)
Warpage
(㎛)
198198 1414 2727 4040
도 4a, 도 4b 및 도 4c는 TaC 복합재에서 TaC층 표면에 대한 SEM 이미지를 측정한 것으로 도 4a는 비교예 1의 SEM 이미지이며, 도 4b는 실시예 4의 SEM 이미지이며, 도 4c는 실시예 1의 SEM 이미지이다. Figures 4a, 4b, and 4c are SEM images of the surface of the TaC layer in the TaC composite. Figure 4a is the SEM image of Comparative Example 1, Figure 4b is the SEM image of Example 4, and Figure 4c is the example. This is the SEM image of 1.
도 4a, 도 4b 및 도 4c에서 실시예 및 비교예의 복합재의 SEM 이미지를 통해 표면 상의 크랙을 관찰하였으며, 비교예 1에서 TaC 표면의 크랙 폭(Crack Width)이 크게 발생하고 크랙 사이의 갭(Gap)을 수직 방향으로 측정했을 때, 최대 3.0 ㎛ 내지 3.6 ㎛ 수준에 해당된다. 이는 그라파이트 기재와 TaC 간 내부 응력 발생에 의한 것이다. 버퍼층이 도입된 실시예 1 및 실시예 3는 크랙 사이 갭을 수직 방향으로 측정했을 때, 최대 0.2 ㎛ 내지 0.4 ㎛ 폭 수준(실시예 1)의 미세 크랙이 발생하거나 크랙이 관찰되지 않는다(실시예 4). 즉, 그라파이트 기재 및 TaC 간의 열팽창 계수의 차이가 발생하지만, 버퍼층의 도입으로 이들 간의 응력을 완화시켜 TaC 층의 표면에서 크랙 폭을 감소시키거나 크랙 및 휨 발생을 낮추어 박리 가능성을 줄일 수 있다. Cracks on the surface were observed through SEM images of the composite materials of Examples and Comparative Examples in FIGS. 4A, 4B, and 4C. In Comparative Example 1, the crack width of the TaC surface was large and the gap between cracks was large. ), when measured in the vertical direction, corresponds to a maximum level of 3.0 ㎛ to 3.6 ㎛. This is due to the occurrence of internal stress between the graphite substrate and TaC. In Examples 1 and 3, in which a buffer layer was introduced, when the gap between cracks was measured in the vertical direction, fine cracks with a maximum width of 0.2 ㎛ to 0.4 ㎛ (Example 1) occurred or no cracks were observed (Example 4). That is, although there is a difference in thermal expansion coefficient between the graphite substrate and TaC, the introduction of a buffer layer can relieve the stress between them and reduce the crack width on the surface of the TaC layer or reduce the occurrence of cracks and warping, thereby reducing the possibility of delamination.
도 5에서 버퍼층을 적용할 경우 TaC 층의 표면에서 미세 크랙의 폭이 최대 2.8배 (예: 실시예 1 및 비교예 1의 비교) 감소하는 효과를 제공할 수 있다. 또한, 버퍼층의 두께에 따라 미세 크랙의 폭 크기가 변화되는 것을 확인할 수 있다. 도 6에서 버퍼층을 적용할 경우 TaC층의 표면에서 휨(Warpage)은 최대 14배 감소 효과(예: 실시예 1 및 비교예 1의 비교)를 제공할 수 있다. 또한, 버퍼층의 두께에 따라 휨(Warpage)이 변화되는 것을 확인할 수 있다. 표 3는 열분해 탄소층 및 TaC층의 두께에 따른 응력 변화를 측정한 결과이다. In Figure 5, when the buffer layer is applied, the width of micro cracks on the surface of the TaC layer can be reduced by up to 2.8 times (e.g., comparison of Example 1 and Comparative Example 1). In addition, it can be seen that the width size of the micro crack changes depending on the thickness of the buffer layer. When applying the buffer layer in FIG. 6, warpage on the surface of the TaC layer can be reduced by up to 14 times (e.g., comparison of Example 1 and Comparative Example 1). Additionally, it can be seen that warpage changes depending on the thickness of the buffer layer. Table 3 shows the results of measuring stress changes according to the thickness of the pyrolytic carbon layer and TaC layer.
Graphite
(㎛)
Graphite
(㎛)
Pyrolytic Carbon
(㎛)
Pyrolytic Carbon
(㎛)
TaC
(㎛)
TaC
(㎛)
Von mises stress
(Mpa)
Von mises stress
(Mpa)
Crack Free
(665Mpa)
Crack Free
(665Mpa)
30003000 55 1010 665.3763665.3763 OO
2020 665.3780665.3780 OO
3030 665.3812665.3812 OO
4040 665.3952665.3952 O O
5050 665.4037665.4037 OO
1515 1010 665.3799665.3799 OO
2020 665.3800665.3800 OO
3030 665.3813665.3813 OO
4040 665.3983665.3983 O O
5050 665.4058665.4058 OO
2020 1010 791.1817791.1817 XX
2020 791.1818791.1818 XX
3030 791.1819791.1819 XX
4040 791.1820791.1820 XX
5050 791.1822791.1822 XX
(표 3에서 "O"는 크랙-프리(free)이고, "x"는 미세 크랙 발생이다.)(In Table 3, “O” means crack-free, and “x” means micro-crack occurrence.)
표 3에서 열분해 탄소층(버퍼층)의 두께가 낮을수록 그라파이트 기재와 TaC층 간의 응력 완화 효과가 크고 크랙 발생을 낮추거나 미세 크랙의 폭 크기를 줄일 수 있다. In Table 3, the lower the thickness of the pyrolytic carbon layer (buffer layer), the greater the stress alleviation effect between the graphite substrate and the TaC layer, which can lower the occurrence of cracks or reduce the width size of micro cracks.
이상과 같이 실시예들이 비록 한정된 실시예와 도면에 의해 설명되었으나, 해당 기술분야에서 통상의 지식을 가진 자라면 상기의 기재로부터 다양한 수정 및 변형이 가능하다. 예를 들어, 설명된 기술들이 설명된 방법과 다른 순서로 수행되거나, 및/또는 설명된 구성요소들이 설명된 방법과 다른 형태로 결합 또는 조합되거나, 다른 구성요소 또는 균등물에 의하여 대치되거나 치환되더라도 적절한 결과가 달성될 수 있다. 그러므로, 다른 구현들, 다른 실시예들 및 특허청구범위와 균등한 것들도 후술하는 특허청구범위의 범위에 속한다.As described above, although the embodiments have been described with limited examples and drawings, various modifications and variations can be made by those skilled in the art from the above description. For example, even if the described techniques are performed in a different order than the described method, and/or the described components are combined or combined in a different form than the described method, or are replaced or substituted by other components or equivalents. Adequate results can be achieved. Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

Claims (9)

  1. 기재; 및 write; and
    상기 기재의 적어도 일면에 형성된 탄화탄탈막; 을 포함하고,A tantalum carbide film formed on at least one surface of the substrate; Including,
    상기 기재 및 상기 탄화탄탈막 사이에 버퍼층;a buffer layer between the substrate and the tantalum carbide film;
    을 포함하고,Including,
    상기 버퍼층은,The buffer layer is,
    반 데르 발스 결합의 물질을 포함하는 것인,Containing a material of van der Waals bond,
    탄화탄탈 복합재.Tantalum carbide composite.
  2. 제1항에 있어서,According to paragraph 1,
    상기 반 데르 발스 물질은 열분해 탄소(Pyrolytic Carbon), BN, MoS2, WSe2, ReS2, MoTe2 및 이들의 조합으로 이루어진 군에서 선택된 적어도 하나 이상을 포함하는 것인, The van der Waals material includes at least one selected from the group consisting of pyrolytic carbon, BN, MoS 2 , WSe 2 , ReS 2 , MoTe 2 , and combinations thereof,
    탄화탄탈 복합재.Tantalum carbide composite.
  3. 제1항에 있어서,According to paragraph 1,
    상기 버퍼층의 두께는 1 ㎛ 내지 50 ㎛인 것인,The thickness of the buffer layer is 1 ㎛ to 50 ㎛,
    탄화탄탈 복합재.Tantalum carbide composite.
  4. 제1항에 있어서,According to paragraph 1,
    상기 탄화탄탈막 중 Ta 대 C의 원자비는 0.9 내지 1.34인 것인, The atomic ratio of Ta to C in the tantalum carbide film is 0.9 to 1.34,
    탄화탄탈 복합재.Tantalum carbide composite.
  5. 제1항에 있어서,According to paragraph 1,
    상기 탄화탄탈막의 두께는 10 ㎛ 내지 100 ㎛인 것인,The thickness of the tantalum carbide film is 10 ㎛ to 100 ㎛,
    탄화탄탈 복합재.Tantalum carbide composite.
  6. 제1항에 있어서,According to paragraph 1,
    상기 기재는,The above description,
    그래핀, 흑연, 플러렌 및 이들의 조합으로 이루어진 군으로부터 선택된 적어도 하나 이상을 포함하는 것인, Containing at least one selected from the group consisting of graphene, graphite, fullerene, and combinations thereof,
    탄화탄탈 복합재.Tantalum carbide composite.
  7. 제1항에 있어서,According to paragraph 1,
    상기 탄화탄탈 복합재의 휨은 10 ㎛ 내지 50 ㎛인 것인, 탄화탄탈 복합재.A tantalum carbide composite, wherein the deflection of the tantalum carbide composite is 10 ㎛ to 50 ㎛.
  8. 제1항에 있어서,According to paragraph 1,
    상기 탄화탄탈막은 크랙-프리 또는 폭이 0.3 ㎛ 내지 0.6 ㎛의 크랙을 포함하는 것인, The tantalum carbide film is crack-free or contains cracks with a width of 0.3 ㎛ to 0.6 ㎛,
    탄화탄탈 복합재.Tantalum carbide composite.
  9. 제1항에 있어서,According to paragraph 1,
    상기 탄화탄탈막의 열팽창계수(CTE)는 6 x10-6/K 초과이고,The coefficient of thermal expansion (CTE) of the tantalum carbide film is greater than 6 x10 -6 /K,
    상기 기재의 열팽창계수(CTE)는 6 x 10-6/K 이하인 것인,The coefficient of thermal expansion (CTE) of the substrate is 6 x 10 -6 /K or less,
    탄화탄탈 복합재.Tantalum carbide composite.
PCT/KR2023/019663 2022-12-29 2023-12-01 Tantalum carbide-coated material WO2024143947A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10506677A (en) * 1994-09-28 1998-06-30 アドヴァンスト・セラミックス・コーポレイション Multilayer flash evaporator
KR20070020225A (en) * 2005-02-14 2007-02-20 토요 탄소 가부시키가이샤 Tantalum carbide-covered carbon material and process for producing the same
JP2014133919A (en) * 2013-01-10 2014-07-24 Shin Etsu Chem Co Ltd Member coated with thermal decomposition carbon
KR20200067781A (en) * 2020-05-27 2020-06-12 주식회사 티씨케이 Manufacturing method for carbonized tantalum coating layer using chemical vapor deposition and property of carbonized tantalum using the same
WO2021117498A1 (en) * 2019-12-12 2021-06-17 信越化学工業株式会社 Tantalum carbonate-coated graphite member and method for producing same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10506677A (en) * 1994-09-28 1998-06-30 アドヴァンスト・セラミックス・コーポレイション Multilayer flash evaporator
KR20070020225A (en) * 2005-02-14 2007-02-20 토요 탄소 가부시키가이샤 Tantalum carbide-covered carbon material and process for producing the same
JP2014133919A (en) * 2013-01-10 2014-07-24 Shin Etsu Chem Co Ltd Member coated with thermal decomposition carbon
WO2021117498A1 (en) * 2019-12-12 2021-06-17 信越化学工業株式会社 Tantalum carbonate-coated graphite member and method for producing same
KR20200067781A (en) * 2020-05-27 2020-06-12 주식회사 티씨케이 Manufacturing method for carbonized tantalum coating layer using chemical vapor deposition and property of carbonized tantalum using the same

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