Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N60/00—Superconducting devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N60/00—Superconducting devices
  • H10N60/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N60/00—Superconducting devices
  • H10N60/10—Junction-based devices
  • H10N60/12—Josephson-effect devices

Definitions

• the disclosed technology relates to a stacked structure and a quantum bit device.
• Patent Document 1 describes a quantum bit circuit that includes a Majorana carrier that includes a topological insulator layer and an s-wave superconductor layer in contact with the Majorana carrier.
• Patent Document 2 describes a semiconductor device that includes a sapphire substrate whose main surface is inclined from the (0001) plane, a (0001) plane region partially provided on the sapphire substrate whose surface is the (0001) plane, and a layered chalcogenide film formed on the (0001) plane region.
• Topological quantum computers have been attracting attention in recent years. Topological quantum computers use Majorana quasiparticles that follow non-Abelian statistics as quantum bits. Quantum computers that use Majorana quasiparticles perform calculations by physically swapping the positions of Majorana quasiparticles, a process known as braiding. This makes them highly resistant to noise, and it is expected that practical quantum computing can be realized with fewer resources, even when redundant bits for error correction are included.
• a hybrid structure combining a two-dimensional topological insulator and an s-wave superconductor has been proposed as a system in which Majorana quasiparticles are expected to appear (J. Alicea, Rep. Prog. Phys. 75, 076501 (2012)), and research into this is being conducted both theoretically and experimentally.
• a two-dimensional topological insulator has an insulating interior on the two-dimensional plane, and a gapless helical channel that circles around the edge of the insulator.
• the helical channel is a one-dimensional conductive channel formed by up-spin electrons with positive momentum and down-spin electrons with negative momentum.
• WTe 2 multilayers with a Td-type crystal structure are higher-order topological insulators (Y.-B. Choi et al., Nat. Mater 19, 974 (2020)).
• Td-WTe 2 multilayers are more chemically stable than monolayers and have the advantage of being easier to handle in the fabrication of quantum bit devices.
• the disclosed technology has been developed in consideration of the above points, and aims to stably express Majorana quasiparticles in a stacked structure in which an s-wave superconductor and a higher-order topological insulator are stacked, by controlling the crystal orientation of the higher-order topological insulator.
• the laminated structure according to the disclosed technology has a sapphire substrate having a step-and-terrace periodic structure on its surface parallel to the [-12-10] direction, an s-wave superconductor film which is a layered first transition metal dichalcogenide film provided on the surface of the sapphire substrate, and a higher-order topological insulator film which is a layered second transition metal dichalcogenide film provided on the s-wave superconductor multilayer film.
• the disclosed technology makes it possible to control the crystal orientation of the higher-order topological insulator in a stacked structure in which an s-wave superconductor and a higher-order topological insulator are stacked, and to stably express Majorana quasiparticles.
• FIG. 1 is a perspective view illustrating an example of a conceptual structure of a quantum bit device according to an embodiment of the disclosed technique.
• 1 is a perspective view showing an example of a configuration of a laminated structure according to an embodiment of the disclosed technique; 2B is a cross-sectional view taken along line 2B-2B in FIG. 2A.
• FIG. 1 is a perspective view showing an example of a configuration of a sapphire substrate according to an embodiment of the disclosed technique.
• 3B is a cross-sectional view taken along line 3B-3B in FIG. 3A.
• the left is a plan view of the sapphire substrate, and the right is a diagram showing the crystal structure of the 2H- NbSe2 multilayer film.
• the left side is a cross-sectional view taken along line 4B-4B in FIG. 4A
• the right side is a diagram showing the crystal structure of the 2H—NbSe 2 multilayer film.
• the left side is a plan view of the sapphire substrate, and the right side is a diagram showing the crystal structure of the Td-WTe bilayer film.
• the left side is a cross-sectional view taken along line 5B-5B in FIG. 5A, and the right side is a diagram showing the crystal structure of the Td-WTe bilayer film.
• 1A to 1C are cross-sectional views showing an example of a method for manufacturing a laminated structure according to an embodiment of the disclosed technique.
• FIG. 1 is a plan view illustrating an example of a configuration of a quantum bit device according to an embodiment of the disclosed technique.
• 7B is a cross-sectional view taken along line 7B-7B in FIG. 7A.
• 7C is a cross-sectional view taken along line 7C-7C in FIG. 7A.
• 1 is a plan view illustrating an example of a method for manufacturing a quantum bit device according to an embodiment of the disclosed technique.
• FIG. 8B is a cross-sectional view taken along line 8B-8B in FIG. 8A.
• 8C is a cross-sectional view taken along line 8C-8C in FIG. 8A.
• 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a quantum bit device according to an embodiment of the disclosed technique.
• 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a quantum bit device according to an embodiment of the disclosed technique.
• [First embodiment] 1 is a perspective view showing an example of a conceptual structure of a quantum bit device 10 according to an embodiment of the disclosed technique.
• the quantum bit device 10 includes an s-wave superconductor multilayer 20 and a high-order topological insulator multilayer 30.
• the s-wave superconductor multilayer 20 and the high-order topological insulator multilayer 30 are each composed of a layered transition metal dichalcogenide.
• the high-order topological insulator multilayer 30 is typically a Td-WTe bilayer .
• a helical channel 31 called a hinge state, shown by a thick line in FIG. 1, is formed at the edge in the b-axis ([010]) direction.
• the helical channel 31 is a one-dimensional conductive channel formed by up-spin electrons with positive momentum and down-spin electrons with negative momentum.
• the substrate on which the high-order topological insulator multilayer film 30 is formed is required to be free of lattice mismatch and contamination with impurity elements, and further to be free of non-essential chemical bonds between the high-order topological insulator multilayer film 30 and the substrate elements.
• WTe 2 a candidate material for the high-order topological insulator multilayer film 30, is deposited on the surface of a van der Waals layered material having an inactive surface (no dangling bonds) such as graphene (L. A. Walsh et al., 2D Mater. 4, 025044 (2017)).
• a van der Waals layered material having an inactive surface no dangling bonds
• graphene Li. A. Walsh et al., 2D Mater. 4, 025044 (2017).
• a technique is required to deposit a high-order topological insulator multilayer film on an s-wave superconductor of a van der Waals layered material having an inactive surface by heteroepitaxial growth while controlling the crystal orientation.
• FIG. 2A is a perspective view showing an example of the configuration of a laminated structure 11 according to an embodiment of the disclosed technology.
• FIG. 2B is a cross-sectional view taken along line 2B-2B in FIG. 2A.
• the laminated structure 11 is a structure intended for application to a quantum bit device that utilizes Majorana quasiparticles.
• the laminated structure 11 has a sapphire substrate 60, an s-wave superconductor multilayer film 20, and a high-order topological insulator multilayer film 30.
• the s-wave superconductor multilayer film 20 is provided on the surface of the sapphire substrate 60
• the high-order topological insulator multilayer film 30 is provided on the surface of the s-wave superconductor multilayer film 20.
• FIG. 3A is a perspective view showing an example of the configuration of a sapphire substrate 60.
• FIG. 3B is a cross-sectional view taken along line 3B-3B in FIG. 3A.
• the sapphire substrate 60 is a substrate made of ⁇ -Al 2 O 3 with a c-plane as the main surface.
• the sapphire substrate 60 is inclined in the [10-10] direction from the (0001) plane as the main surface, and has a step-and-terrace periodic structure parallel to the [-12-10] direction on the main surface.
• the step-and-terrace periodic structure being parallel to the [-12-10] direction means that the direction in which the steps of the step-and-terrace periodic structure are connected is the [-12-10] direction.
• the step-and-terrace periodic structure can be obtained by cutting the sapphire substrate 60 at a predetermined miscut angle (for example, 0.3° or more and 10° or less).
• the s-wave superconductor multilayer film 20 is formed along the step-and-terrace periodic structure of the main surface of the sapphire substrate 60 by heteroepitaxial growth.
• the s-wave superconductor multilayer film 20 is a multilayer film made of layered transition metal dichalcogenides having a 2H type crystal structure.
• the number of layers of the s-wave superconductor multilayer film 20 is, for example, 20 ML (monolayers).
• the s-wave superconductor multilayer film 20 is made of 2H-NbSe 2 , 1 ML is about 0.7 nm. It is also possible to use NbS 2 or NbTe 2 as the material of the s-wave superconductor multilayer film 20.
• the left side of FIG. 4A is a plan view of a sapphire substrate 60 having a step-and-terrace periodic structure viewed from the direction of viewing the (0001) plane.
• the right side of FIG. 4A is a diagram showing the crystal structure of a 2H-NbSe 2 multilayer film 20A, which is an example of an s-wave superconductor multilayer film formed on the (0001) plane of the sapphire substrate 60, viewed from the same line of sight as the left side of FIG. 4A.
• the left side of FIG. 4B is a cross-sectional view taken along line 4B-4B in the left side of FIG. 4A.
• FIG. 4B is a diagram showing the crystal structure of a 2H-NbSe 2 multilayer film 20A viewed from the same line of sight as the left side of FIG.
• the [010] direction which is the b-axis of the 2H-NbSe 2 multilayer film 20A, is parallel to the [-12-10] direction, which is the direction in which the steps of the step-and-terrace periodic structure of the sapphire substrate 60 are connected.
• the [210] direction of the 2H-NbSe 2 multilayer film 20A is parallel to the [10-10] direction in which the steps of the step-and-terrace periodic structure of the sapphire substrate 60 are arranged.
• the [001] direction which is the c-axis of the 2H-NbSe 2 multilayer film 20A, is perpendicular to the (0001) plane, which is the main surface of the sapphire substrate 60.
• the s-wave superconductor multilayer film 20 is formed on the surface of the sapphire substrate 60 having a step-and-terrace periodic structure by a heteroepitaxial growth method, it is possible to control the crystal orientation of the s-wave superconductor multilayer film 20.
• the high-order topological insulator multilayer film 30 is formed on the surface of the s-wave superconductor multilayer film 20 by heteroepitaxial growth.
• the high-order topological insulator multilayer film 30 is formed along the step-and-terrace periodic structure of the main surface of the sapphire substrate 60, similar to the s-wave superconductor multilayer film 20.
• the high-order topological insulator multilayer film 30 is a multilayer film made of layered transition metal dichalcogenides having a Td-type crystal structure.
• the number of layers of the high-order topological insulator multilayer film 30 is, for example, 5 ML.
• 1 ML is about 0.7 nm.
• the left side of FIG. 5A is a plan view of a sapphire substrate 60 having a step-and-terrace periodic structure, viewed from the direction of the (0001) plane.
• the right side of FIG. 5A is a diagram showing the crystal structure of a Td-WTe 2 multilayer film 30A, which is an example of a high-order topological insulator multilayer film formed on the (0001) plane of the sapphire substrate 60, viewed from the same line of sight as the left side of FIG. 5A.
• the left side of FIG. 5B is a cross-sectional view taken along line 5B-5B in the left side of FIG. 5A.
• FIG. 5B is a diagram showing the crystal structure of a Td-WTe 2 multilayer film 30A, viewed from the same line of sight as the left side of FIG. 5B.
• the [010] direction which is the b-axis of the Td-WTe 2 multilayer film 30A, is parallel to the [-12-10] direction, which is the direction in which the steps of the step-and-terrace periodic structure of the sapphire substrate 60 are arranged.
• the [100] direction which is the a-axis of the Td-WTe 2 multilayer film 30A, is parallel to the [10-10] direction, which is the direction in which the steps of the step-and-terrace periodic structure of the sapphire substrate 60 are arranged.
• the [001] direction which is the c-axis of the Td-WTe 2 multilayer film 30A, is perpendicular to the (0001) plane, which is the main surface of the sapphire substrate 60.
• the high-order topological insulator multilayer film 30 is formed on the sapphire substrate 60 having the step-and-terrace periodic structure by the heteroepitaxial growth method, it is possible to control the crystal orientation of the high-order topological insulator multilayer film 30.
• a sapphire substrate 60 ( ⁇ -Al 2 O 3 ) is prepared, which is inclined from the (0001) plane in the [10-10] direction and has a step-and-terrace periodic structure on its main surface parallel to the [-12-10] direction (FIG. 6A).
• the step-and-terrace periodic structure can be formed by cutting the sapphire substrate 60 at a predetermined miscut angle.
• the step height h and step width w can be controlled by the miscut angle.
• a step-and-terrace periodic structure with a step height h of 1.3 nm and a step width w of 50 nm can be obtained.
• the miscut of the sapphire substrate 60 can be performed, for example, by CMP (Chemical Mechanical Polishing) or Ar ion milling. After the miscut, the sapphire substrate 60 is annealed for about 3 to 5 hours in the atmosphere at about 1200° C. or in an oxygen atmosphere at atmospheric pressure. After the annealing process, the sapphire substrate 60 is immersed in methanol for about 20 to 30 minutes, and then rinsed with ultrapure water.
• a uniform step-and-terrace periodic structure is formed on the main surface of the sapphire substrate 60.
• a uniform step-and-terrace periodic structure means that there is little variation in the direction in which the steps are connected, and the steps are connected in an approximately straight line.
• an s-wave superconductor multilayer film 20 made of layered transition metal dichalcogenide is formed on the main surface of the sapphire substrate 60 by heteroepitaxial growth (FIG. 6B).
• the s-wave superconductor multilayer film 20 can be formed by, for example, MBE (Molecular Beam Epitaxy).
• MBE Molecular Beam Epitaxy
• a 2H-NbSe 2 multilayer film is formed by MBE.
• Nb is deposited on the surface of the sapphire substrate 60 by electron beam deposition
• Se is deposited on the surface of the sapphire substrate 60 by a K-cell type evaporator (heating temperature 180°C).
• the deposition rate of Nb is, for example, 0.1 ⁇ /min
• the deposition rate of Se is, for example, 10 ⁇ /min.
• the deposition time is adjusted so that the number of layers of NbSe 2 is, for example, about 20 ML. It is known that the superconducting critical temperature of 2H-NbSe 2 increases with the increase in the number of layers.
• the superconducting critical temperature of the 2H-NbSe 2 multilayer film can be set to a temperature close to 7.2 K, which is the superconducting critical temperature of the NbSe 2 bulk crystal.
• post-annealing is performed at 950 ° C. for 30 minutes while continuing only the deposition of Se. This makes it possible to improve the crystallinity and surface roughness inside the 2H-NbSe 2 multilayer film at the atomic level.
• PLD method Pulsed Laser Deposition
• sputtering method as a deposition method for the s-wave superconductor multilayer film 20.
• a high-order topological insulator multilayer 30 made of layered transition metal dichalcogenide is formed on the surface of the s-wave superconductor multilayer by heteroepitaxial growth (FIG. 6C).
• the high-order topological insulator multilayer 30 can be formed, for example, by MBE.
• the s-wave superconductor multilayer 20 and the high-order topological insulator multilayer 30 can be formed in situ in the same vacuum chamber.
• a Td-WTe 2 multilayer is formed by MBE.
• W is deposited on the surface of the s-wave superconductor multilayer film 20 by electron beam deposition
• Te is deposited on the surface of the s-wave superconductor multilayer film 20 by a K-cell type evaporator (heating temperature 300° C.) by co-deposition.
• the deposition rate of W is, for example, 0.05 ⁇ /min
• the deposition rate of Te is, for example, 10 ⁇ /min.
• the deposition time is adjusted so that the number of layers of WTe 2 is, for example, about 5 ML.
• post-annealing is performed at 400° C. for 30 minutes while continuing only the deposition of Te. This makes it possible to improve the crystallinity and surface roughness inside the Td-WTe 2 multilayer film at the atomic level. It is also possible to use the PLD method or the sputtering method as the deposition method of the high-order topological insulator multilayer film 30.
• the s-wave superconductor multilayer 20 and the high-order topological insulator multilayer 30 are successively formed by heteroepitaxial growth on the surface of the sapphire substrate 60 having a step-and-terrace structure on its main surface, thereby making it possible to control the crystal orientation of these multilayers. That is, the helical channel along the b-axis ([010]) of the Td-WTe 2 multilayer can be oriented parallel to the [-12-10] direction, which is the direction in which the steps of the step-and-terrace periodic structure are arranged.
• the orientation of the helical channel formed in the highly-ordered topological insulator multilayer film 30 reflects the step-and-terrace periodic structure formed in the sapphire substrate 60. This makes it possible to uniformly orient the helical channel formed in the highly-ordered topological insulator multilayer film 30, and when the laminated structure 11 is applied to a quantum bit device, it is possible to stably express Majorana quasiparticles.
• Fig. 7A is a plan view showing an example of a configuration of a quantum bit device 10 according to an embodiment of the disclosed technique
• Fig. 7B is a cross-sectional view taken along line 7B-7B in Fig. 7A
• Fig. 7C is a cross-sectional view taken along line 7C-7C in Fig. 7A.
• the quantum bit device 10 includes a stacked structure 11 according to the first embodiment of the disclosed technology.
• the quantum bit device 10 has three gates 70A, 70B, and 70C provided on the surface of the high-order topological insulator multilayer film 30. Of these three gates, the gates 70A and 70C are provided at positions straddling two adjacent steps ST1 and ST2 of the step-and-terrace periodic structure of the sapphire substrate 60.
• the gate 70B is provided at a position straddling the step ST1 between the gates 70A and 70B.
• the gates 70A, 70B, and 70C are provided on helical channels formed along the steps of the step-and-terrace periodic structure of the sapphire substrate 60.
• Each of the gates 70A, 70B , and 70C is formed by stacking a ferromagnetic film 71 and a conductive film 72.
• the material of the ferromagnetic film 71 may be, for example, Cr2Ga2Te6 .
• the ferromagnetic film 71 may be any material as long as it has ferromagnetic and insulating properties, and it is also possible to use a diluted magnetic semiconductor as the material of the ferromagnetic film 71.
• the material of the conductive film 72 may be, for example, Au. It is also possible to use other metals that have good adhesion to the ferromagnetic film 71 as the material of the conductive film 72.
• the surface of the laminated structure 11 is covered with an insulating film 90.
• the insulating film 90 has an opening 91 that exposes the surfaces of the gates 70A , 70B, and 70C.
• Examples of materials that can be used for the insulating film 90 include HfO2 , Al2O3 , Si3N4 , HfSiO , HfAlON , Y2O3 , SrTiO3 , PbZrTiO3 , and BaTiO3 .
• the quantum bit device 10 has superconducting quantum interferometers (SQUIDs) 80A, 80B, and 80C provided corresponding to the gates 70A, 70B, and 70C.
• the superconducting quantum interferometers 80A, 80B, and 80C are each provided on the surface of the insulator film 90.
• the superconducting quantum interferometer 80A has a ring-shaped pattern surrounding the gate 70A.
• the superconducting quantum interferometer 80B has a ring-shaped pattern surrounding the gate 70B.
• the superconducting quantum interferometer 80C has a ring-shaped pattern surrounding the gate 70C.
• the superconducting quantum interference meters 80A, 80B, and 80C each have a lower electrode 81 made of a superconductor occupying about half the area of the ring-shaped pattern, and an upper electrode 82 made of a superconductor occupying the remaining area of the ring-shaped pattern.
• the superconducting quantum interference meters 80A, 80B, and 80C each have a tunnel barrier layer 83 sandwiched between the upper electrode 82 and the lower electrode 81 at the connection portion of these electrodes.
• a Josephson junction is formed by a laminated structure of a superconductor, a tunnel barrier layer, and a superconductor.
• Al can be used as the material of the lower electrode 81 and the upper electrode 82.
• An AlOx film having a thickness of about several nm can be used as the material of the tunnel barrier layer 83.
• Nb or Pb can also be used as the material of the lower electrode 81 and the upper electrode 82, and oxides of these can also be used as the material of the tunnel barrier layer 83.
• a copper oxide-based high temperature superconductor can also be used as the material of the lower electrode 81 and the upper electrode 82.
• the helical channel formed in the high-order topological insulator multilayer film 30 is oriented along the steps of the step-and-terrace structure of the sapphire substrate 60.
• the gates 70A, 70B, and 70C including the ferromagnetic film 71 at positions straddling the steps, respectively four Majorana quasiparticles ⁇ 1 , ⁇ 2 , ⁇ 3 , and ⁇ 4 can be manifested in the vicinity of the gates 70A, 70B, and 70C on the helical channel of the high-order topological insulator multilayer film 30.
• the braiding of the Majorana quasiparticles can be performed by changing the electrostatic potential by applying voltages to the gates 70A, 70B, and 70C.
• the exchange of the Majorana quasiparticles ⁇ 1 and ⁇ 2 can be performed by applying a voltage to the gate 70A.
• the minute magnetic flux change accompanying the exchange of the Majorana quasiparticles ⁇ 1 and ⁇ 2 can be detected as a minute voltage signal change by the superconducting quantum interference meter 80A.
• the Majorana quasiparticles ⁇ 2 and ⁇ 3 can be exchanged by applying a voltage to gate 70B.
• the minute change in magnetic flux accompanying the exchange of Majorana quasiparticles ⁇ 2 and ⁇ 3 can be detected as a minute voltage signal change by superconducting quantum interferometer 80B.
• the Majorana quasiparticles ⁇ 3 and ⁇ 4 can be exchanged by applying a voltage to gate 70C.
• the minute change in magnetic flux accompanying the exchange of Majorana quasiparticles ⁇ 3 and ⁇ 4 can be detected as a minute voltage signal change by superconducting quantum interferometer 80C.
• Figure 8A is a plan view showing an example of a method for manufacturing the quantum bit device 10
• Figure 8B is a cross-sectional view taken along line 8B-8B in Figure 8A
• Figure 8C is a cross-sectional view taken along line 8C-8C in Figure 8A
• Figures 8D and 8E are cross-sectional views corresponding to Figure 8C.
• the laminated structure 11 is fabricated by the method shown in Figures 6A to 6C.
• gates 70A, 70B, and 70C are formed on the surface of the highly-ordered topological insulator multilayer film 30 at positions that straddle the steps of the step-and-terrace periodic structure of the sapphire substrate 60.
• a mask (not shown) is formed on the surface of the laminated structure 11 for patterning the gates 70A, 70B, and 70C by lift-off.
• the mask is formed, for example, by forming an electron beam resist on the surface of the laminated structure 11 by spin coating, and then patterning this by electron beam lithography.
• a ferromagnetic film 71 and a conductive film 72 are sequentially formed on the surface of the laminated structure 11 through the mask by PLD.
• Cr 2 Ga 2 Te 6 is used as the material of the ferromagnetic film 71 and Au is used as the conductive film 72.
• the substrate temperature is set to 200° C.
• the laser energy density is set to 1.0 J/cm 2
• the laser irradiation frequency is set to 1 Hz
• the substrate-target distance is set to 5 cm
• the film formation rate is set to 1 nm/min
• the thickness of Cr 2 Ga 2 Te 6 is set to 50 nm.
• the substrate temperature is set to room temperature
• the laser energy density is set to 1.0 J/cm 2
• the laser irradiation frequency is set to 5 Hz
• the substrate-target distance is set to 5 cm
• the film formation rate is set to 5 nm/min
• the thickness of Au is set to 30 nm.
• gates 70A, 70B and 70C including a ferromagnetic film 71 By locating gates 70A, 70B and 70C including a ferromagnetic film 71 at positions spanning the steps, four Majorana quasiparticles ⁇ 1 , ⁇ 2 , ⁇ 3 and ⁇ 4 can be manifested in the vicinity of gates 70A, 70B and 70C on the helical channel.
• an insulating film 90 is formed to cover the entire surface of the laminated structure 11 (FIG. 8D).
• HfO 2 is used as the material for the insulating film 90.
• HfO 2 can be deposited by ALD using tetrakis(dimethylamino)hafnium and H 2 O as precursors.
• the deposition temperature is, for example, 250° C.
• openings 91 that expose the surfaces of gates 70A, 70B, and 70C are formed in the insulator film 90.
• a mask (not shown) for forming the openings 91 is formed by electron beam lithography, and the insulator film 90 is etched through the mask by Ar ion milling to form the openings 91.
• the beam acceleration voltage in the Ar ion milling is, for example, 280 V, and the beam current is, for example, 150 mA.
• a plurality of superconducting quantum interferometers 80A, 80B, and 80C including a superconductor having a ring-shaped pattern surrounding the gates 70A, 70B, and 70C are formed on the surface of the insulator film 90 (FIG. 8E).
• the superconducting quantum interferometers 80A, 80B, and 80C are formed by sequentially forming a lower electrode 81, a tunnel barrier layer 83 (FIG. 7B), and an upper electrode 82 on the surface of the insulator film 90 by electron lithography and lift-off.
• Al is used as the material for the lower electrode 81 and the upper electrode 82
• AlOx is used as the material for the tunnel barrier layer 83.
• a mask (not shown) is formed for patterning the lower electrode 81 by lift-off.
• the mask is formed, for example, by forming an electron beam resist on the surface of the laminated structure 11 by spin coating, and then patterning it by electron beam lithography.
• Al constituting the lower electrode 81 is deposited on the surface of the insulator film 90 through the mask by a vapor deposition method.
• the substrate temperature is set to room temperature
• the film formation rate is set to 5 nm/min
• the film thickness is set to 50 nm.
• the Al deposited on the mask is removed together with the mask to form the lower electrode 81.
• a mask (not shown) is formed for patterning the tunnel barrier layer 83 by lift-off.
• the mask is formed, for example, by forming an electron beam resist on the surface of the laminated structure 11 by spin coating, and patterning it by electron beam lithography.
• AlO X constituting the tunnel barrier layer 83 is deposited on the surface of the lower electrode 81 through the mask by a deposition method.
• the substrate temperature is set to room temperature
• the oxygen partial pressure of the vacuum chamber is set to 50 Pa
• the film thickness is set to 1 nm or more and 5 nm or less.
• a mask (not shown) is formed for patterning the upper electrode 82 by lift-off.
• the mask is formed, for example, by forming an electron beam resist on the surface of the laminated structure 11 by spin coating, and then patterning it by electron beam lithography.
• Al constituting the upper electrode 82 is deposited on the surface of the insulator film 90 through the mask by a vapor deposition method. In depositing Al, the substrate temperature is set to room temperature, the film formation rate is set to 5 nm/min, and the film thickness is set to 50 nm. After depositing Al, the Al deposited on the mask is removed together with the mask, thereby forming the upper electrode 82.
• a quantum bit device 10 is manufactured that utilizes Majorana quasiparticles that appear on the helical channels of the high-order topological insulator multilayer film 30 that are oriented along the steps of the step-and-terrace structure of the sapphire substrate 60.
• Quantum bit device 11 Stacked structure 20 S-wave superconductor multilayer film 30 High-order topological insulator multilayer film 31 Helical channel 40, 71 Ferromagnetic film 60 Sapphire substrate 70A, 70B, 70C Gate 80A, 80B, 80C Superconducting quantum interference meter

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