WO2024124763A1 - Optoisolator and packaging process therefor - Google Patents

Optoisolator and packaging process therefor Download PDF

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Publication number
WO2024124763A1
WO2024124763A1 PCT/CN2023/089365 CN2023089365W WO2024124763A1 WO 2024124763 A1 WO2024124763 A1 WO 2024124763A1 CN 2023089365 W CN2023089365 W CN 2023089365W WO 2024124763 A1 WO2024124763 A1 WO 2024124763A1
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Prior art keywords
integrated circuit
chip
passivation layer
layer
transmitting
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PCT/CN2023/089365
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French (fr)
Chinese (zh)
Inventor
姚玉峰
陶骞
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莱弗利科技(苏州)有限公司
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Publication of WO2024124763A1 publication Critical patent/WO2024124763A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the technical field of isolators, and in particular to an optocoupler isolator and a packaging process thereof.
  • the optocoupler isolation circuit makes the two isolated circuits have no direct electrical connection, mainly to prevent interference caused by electrical connection, especially between the low-voltage control circuit and the external high-voltage circuit.
  • the main components of the optocoupler are light-emitting devices and photosensitive devices.
  • the light-emitting devices are generally IRLEDs, and the light receiving devices are photodiodes, phototransistors, Darlington tubes, optical integrated circuits, etc.
  • the response speed of the optocoupler is very high, so a high-speed type with a faster response is generally used, and the delay time is within 500nS.
  • linear optocouplers should be used to reduce distortion, while when transmitting digital switching signals, the requirements for its linearity are not too strict.
  • the traditional optocoupler packaging process generally includes the following steps: Step 1: Solidify the die on the metal frame; Step 2: Solder gold wires on the metal frame; Step 3: Apply silicone gel above and around the chip and solder wires; Step 4: Place a polyimide film (Kapton Tape) on the silicone gel; Step 5: Flip the metal frame that fixes the LED chip so that the LED is facing the photosensitive area PD of the chip below (this process is a non-standard process and requires the development of a customized machine to perform, or manual flipping, which is inefficient and has a low yield); Step 6: Injection molding; Step 7: Bending the output pin into shape.
  • Step 1 Solidify the die on the metal frame
  • Step 2 Solder gold wires on the metal frame
  • Step 3 Apply silicone gel above and around the chip and solder wires
  • Step 4 Place a polyimide film (Kapton Tape) on the silicone gel
  • Step 5 Flip the metal frame that fixes the LED chip so that the LED is facing the photosensitive area PD of the chip
  • the technical problem to be solved by the present invention is to overcome the technical defects existing in the prior art, and propose an optocoupler isolator and its packaging process, which can conveniently package the optocoupler isolator without requiring special processes, significantly reducing production costs, and achieving complete physical isolation, with higher isolation performance, small size, and higher reliability.
  • the present invention provides a packaging process for an optocoupler isolator, wherein the optocoupler isolator comprises a receiving integrated circuit and a transmitting integrated circuit, wherein the receiving integrated circuit comprises a receiving chip with a photodiode sensor, and the transmitting integrated circuit comprises a photodiode transmitting chip and an ASIC chip, wherein the ASIC chip is connected to the photodiode transmitting chip;
  • the packaging process of the optical coupler isolator comprises the following steps:
  • a first passivation layer, a first redistribution layer, and a second passivation layer are sequentially arranged from top to bottom at the bottom of the receiving integrated circuit, and a third passivation layer is arranged at the top of the receiving integrated circuit, a hole is opened and filled with copper on the third passivation layer, and a fourth redistribution layer is arranged on the third passivation layer, and the output of the photodiode receiving chip is connected to the first redistribution layer at the bottom through the hole filled with copper;
  • S40 a fifth passivation layer, a second redistribution layer and a fourth passivation layer are sequentially arranged on the upper surface of the optical coupling isolation module from top to bottom.
  • the method for manufacturing a receiving integrated circuit includes:
  • the receiving chip with photodiode sensing is arranged on the carrier substrate and injection molded;
  • the carrier substrate is removed, and then through holes are opened in the first injection molded body and filled with copper.
  • the method for manufacturing a transmitting integrated circuit includes:
  • the photodiode emission chip and the ASIC chip are arranged on a carrier substrate and injection molded;
  • the carrier substrate is removed, and then through holes are opened in the second injection molded body and filled with copper;
  • a sixth passivation layer is arranged on the upper surfaces of the photodiode emission chip, the ASIC chip and the second injection molding body, and a third rewiring layer is arranged on the sixth passivation layer.
  • the two electrodes of the photodiode emission chip and the driving output of the ASIC chip are connected through the copper-filled openings on the second injection molding body and the second rewiring layer, and the output of the ASIC chip is connected to the first rewiring layer at the bottom through the copper-filled through holes at the edge of the isolation layer and the copper-filled through holes of the third passivation layer and the first injection molding body; wherein the copper-filled through holes at the edge of the isolation layer do not affect the isolation performance of the isolation layer for transmission and reception.
  • the transmitting integrated circuit and the receiving integrated circuit are bonded together by heat pressing or other bonding methods to form an optocoupler isolation module.
  • the signal emitted by the photodiode transmitting chip passes through the isolation layer and is received by the receiving chip with photodiode sensing.
  • the through hole of the emission integrated circuit does not penetrate the isolation layer, and the through hole penetrates the second injection molded body, connecting the two electrodes of the photodiode emission chip and the driving output of the ASIC chip.
  • partition walls are provided on the isolation layer, the third passivation layer and the sixth passivation layer, and the light interference of the photodiode emission chip of the adjacent channel is isolated by the partition wall.
  • the partition cavity is filled with an organic material capable of blocking light.
  • the present invention also provides an optocoupler isolator, which is manufactured according to the above-mentioned optocoupler isolator packaging process.
  • optical coupler isolator and its packaging process described in the present invention can be easily
  • the packaging of the optocoupler isolator does not require special processes, which significantly reduces the production cost and achieves complete physical isolation. It has higher isolation performance, small size and higher reliability.
  • optical coupler isolator and packaging process thereof described in the present invention allow one or more optical coupler channels to be packaged inside a device, and optical crosstalk isolation between the channels can be effectively achieved.
  • FIG. 1 is a schematic diagram of an optocoupler isolator packaging process proposed by the present invention.
  • FIG. 2 is a schematic diagram of the structure of an optical coupler isolator proposed by the present invention.
  • FIG. 3 is a schematic diagram of the structure of an optical coupler isolator proposed by the present invention.
  • FIG. 4 is a schematic diagram of the product structure of the optical coupling isolation module of the present invention using traditional packaging.
  • an embodiment of the present invention provides an optocoupler isolator packaging process
  • the optocoupler isolator includes a receiving integrated circuit 1 and a transmitting integrated circuit 3
  • the receiving integrated circuit 1 includes a receiving chip 2 with a photodiode sensor
  • the transmitting integrated circuit 3 includes a photodiode transmitting chip 4 and an ASIC chip 5, the ASIC chip 5 is connected to the photodiode transmitting chip 4; wherein the optocoupler
  • the packaging process of the isolator includes the following steps:
  • a first passivation layer 6, a first rewiring layer 12 and a second passivation layer 7 are sequentially arranged at the bottom of the receiving integrated circuit 1 from top to bottom, and a third passivation layer 8 is arranged at the top of the receiving integrated circuit 1, and a hole is opened on the third passivation layer 8 and filled with copper, and a fourth rewiring layer 15 is arranged on the third passivation layer 8, and the output of the receiving chip 2 with photodiode sensing is connected to the first rewiring layer 12 at the bottom through the hole filling with copper;
  • S40 a fifth passivation layer 10, a second redistribution layer 13 and a fourth passivation layer 9 are sequentially arranged on the upper surface of the optical coupling isolation module from top to bottom.
  • the optocoupler isolator packaging process described in the present invention can conveniently package the optocoupler isolator without requiring special processes, significantly reducing production costs, and achieving complete physical isolation, with higher isolation performance, small size, and higher reliability.
  • the method for manufacturing the receiving integrated circuit 1 includes: placing the receiving chip 2 with photodiode sensing on a carrier substrate and performing injection molding; removing the carrier substrate after injection molding, and then opening holes in the first injection molded body 17 and filling copper.
  • the method for manufacturing the emission integrated circuit 3 includes: arranging the photodiode emission chip 4 and the ASIC chip 5 on the carrier substrate and performing injection molding; removing the carrier substrate after the injection molding, and then opening holes and filling copper on the second injection molding body 19; arranging a sixth passivation layer 11 on the upper surface of the photodiode emission chip 4, the ASIC chip 5 and the second injection molding body 19, and arranging a third redistribution layer 14 on the sixth passivation layer 11, connecting the two electrodes of the photodiode emission chip 4 and the driving output of the ASIC chip 5 through the openings and copper filling on the second injection molding body 19 and the second redistribution layer 13, and connecting the ASIC 5 through the through-holes and copper filling on the edges of the isolation layer 16 and the openings and copper filling on the third passivation layer 8 and the first injection molding body 17.
  • the output of the chip is connected to the first redistribution layer 12 at the bottom; wherein the copper filling of the through hole at the edge
  • the transmitting integrated circuit 3 and the receiving integrated circuit 1 are bonded together by heat pressing or other bonding methods to form an optical coupling isolation module.
  • the signal emitted by the photodiode transmitting chip 4 passes through the isolation layer 16 and is received by the receiving chip 2 with photodiode sensing.
  • the isolation layer 16 is a transparent isolation layer 16, the through hole of the transmitting integrated circuit 3 does not penetrate the transparent isolation layer 16, and the through hole penetrates the second injection molded body 19 of the transmitting integrated circuit 3, bringing the pad signal of the ASIC chip 5 to the top of the entire optocoupler isolation module.
  • This structure ensures the integrity of the transparent isolation layer 16, and no metal passes through the transparent isolation layer 16, thereby achieving higher voltage isolation performance.
  • the above-mentioned redistribution layers form pads at different levels, which will be connected to the metal frame through gold wires, so that the optocoupler isolation module can be made using traditional packaging processes.
  • the pins of the metal frame are made relatively high, which can reduce the length of the gold wire, thereby increasing stability and reducing costs, as shown in Figure 4.
  • a connected partition wall 18 is provided on the isolation layer 16 and the third passivation layer 8.
  • the partition wall 18 is an organic material capable of blocking light.
  • the partition wall 18 is used to isolate the light interference of the photodiode emission chip 4 of the adjacent channel, thereby realizing multi-channel isolation.
  • the optocoupler isolator packaging process described in the present invention allows one or more optocoupler channels to be packaged inside a device, and optical crosstalk isolation can be effectively achieved between the channels.
  • the present invention further provides an optocoupler isolator, which is manufactured according to the above-mentioned optocoupler isolator packaging process.
  • the receiving integrated circuit 1 includes a receiving chip 2 with a photodiode sensor, and the receiving chip 2 with a photodiode sensor is arranged on a carrier substrate and injection molded. The carrier substrate is then removed, and holes are opened in the first injection molded body 17 and filled with copper.
  • the method for making the transmitting integrated circuit 3 includes: placing the photodiode transmitting chip 4 and the ASIC chip 5 on the carrier substrate and performing injection molding; removing the carrier substrate after injection molding, and then opening holes and filling copper on the second injection molding body 19; setting the sixth passivation layer 11 on the upper surface of the photodiode transmitting chip 4, the IC chip 5 and the second injection molding body 19, and setting the third rewiring layer 14 on the sixth passivation layer 11, connecting the two poles of the photodiode transmitting chip 4 and the driving output of the ASIC chip 5 through the openings and copper filling on the second injection molding body 19 and the second rewiring layer 13.
  • the output of the ASIC chip is connected to the first rewiring layer 12 at the bottom through the copper filling of the through holes at the edge of the isolation layer and the openings and copper filling of the third passivation layer 8 and the first injection molding body 17.
  • the copper filling of the through holes at the edge of the isolation layer does not affect the isolation performance of the isolation layer for transmission and reception.
  • the transmitting integrated circuit 3 and the receiving integrated circuit 1 are bonded together by heat pressing or other bonding methods to form an optical coupling isolation module.
  • the signal emitted by the photodiode transmitting chip 4 passes through the isolation layer 16 and is received by the receiving chip 2 with photodiode sensing.
  • the isolation layer 16 is a transparent isolation layer 16, the through hole of the transmitting integrated circuit 3 does not penetrate the transparent isolation layer 16, and the through hole penetrates the second injection molded body 19 of the transmitting integrated circuit 3, bringing the pad signal of the ASIC chip 5 to the top of the entire optocoupler isolation module block.
  • This structure ensures the integrity of the transparent isolation layer 16, and no metal passes through the transparent isolation layer 16, thereby achieving higher voltage isolation performance.
  • the above-mentioned redistribution layers form pads at different levels, which will be connected to the metal frame through gold wires, so that the optocoupler isolation module can be made using traditional packaging processes.
  • the pins of the metal frame are made relatively high, which can reduce the length of the gold wire, thereby increasing stability and reducing costs, as shown in Figure 4.
  • a connected partition wall 18 is provided on the isolation layer 16 and the third passivation layer 8.
  • the partition wall 18 is made of an organic material capable of blocking light, such as epoxy resin, and the adjacent channels are isolated by the partition wall 18. The light interference of the photodiode emission chip 4 is eliminated, thereby achieving multi-channel isolation.
  • An optocoupler isolator of the present embodiment is manufactured by the aforementioned optocoupler isolator packaging process, so the specific implementation of the optocoupler isolator can be seen in the embodiment section of the optocoupler isolator packaging process in the previous text. Therefore, its specific implementation can refer to the description of the corresponding embodiments of each part, which will not be introduced in detail here.

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Abstract

The present invention relates to an optoisolator and a packaging process therefor. The optoisolator comprises a receiving integrated circuit and a transmitting integrated circuit. The packaging process for the optoisolator comprises: providing a first passivation layer, a first redistribution layer and a second passivation layer at the bottom of the receiving integrated circuit from top to bottom, providing a third passivation layer at the top of the receiving integrated circuit, and forming a hole on the third passivation layer and filling same with copper; bonding the transmitting integrated circuit and the receiving integrated circuit into a whole to form an optoisolator module, wherein an isolation layer is provided between the transmitting integrated circuit and the receiving integrated circuit; and sequentially providing a fifth passivation layer, a second redistribution layer and a fourth passivation layer on the surface of the optoisolator module from top to bottom. According to the present invention, the optoisolator can be conveniently packaged, no special process is needed, the production cost is remarkably reduced, complete physical isolation is implemented, and higher isolation performance, a small size, and higher reliability are achieved.

Description

光耦隔离器及其封装工艺Optocoupler isolator and its packaging process 技术领域Technical Field
本发明涉及隔离器技术领域，尤其是指一种光耦隔离器及其封装工艺。The present invention relates to the technical field of isolators, and in particular to an optocoupler isolator and a packaging process thereof.
背景技术Background technique
光耦隔离电路使被隔离的两部分电路之间没有电的直接连接，主要是防止因有电的连接而引起的干扰，特别是低压的控制电路与外部高压电路之间。光耦的主要构件是发光器件和光敏器件，发光器件一般都是IRLED，而光接受器件有光敏二极管、光敏三极管、达林顿管、光集成电路等类型，在高频开关电源中，对光耦的响应速度要求很高，故一般采用响应较快的高速型，延迟时间在500nS以内。用于模拟信号或直流信号传输时，应采用线性光耦以减小失真，而传输数字开关信号时，对其线性度的要求不太严格。The optocoupler isolation circuit makes the two isolated circuits have no direct electrical connection, mainly to prevent interference caused by electrical connection, especially between the low-voltage control circuit and the external high-voltage circuit. The main components of the optocoupler are light-emitting devices and photosensitive devices. The light-emitting devices are generally IRLEDs, and the light receiving devices are photodiodes, phototransistors, Darlington tubes, optical integrated circuits, etc. In high-frequency switching power supplies, the response speed of the optocoupler is very high, so a high-speed type with a faster response is generally used, and the delay time is within 500nS. When used for analog signal or DC signal transmission, linear optocouplers should be used to reduce distortion, while when transmitting digital switching signals, the requirements for its linearity are not too strict.
传统的光耦封装工艺一般包括以下步骤：步骤一：在金属框架上固晶；步骤二：在金属框架上焊金线；步骤三：在芯片及焊线上方及四周点上硅胶；步骤四：在硅胶上方放置聚酰亚胺薄膜(Kapton Tape)；步骤五：翻转固定LED芯片的金属框架，使LED正对于下方芯片的感光区域PD(该工艺为非标准工艺，需开发定制化的机器来执行，或手动翻转，效率低，良率也低)；步骤六：注塑成型；步骤七：将输出引脚弯曲成型，上述七个步骤工艺比较复杂，其中步骤三、步骤四和步骤五均为非标准工艺，要么需要开发定制化的机器来执行该工艺，生产成本高，要么需要手动操作，工作效率低，产品良率低。The traditional optocoupler packaging process generally includes the following steps: Step 1: Solidify the die on the metal frame; Step 2: Solder gold wires on the metal frame; Step 3: Apply silicone gel above and around the chip and solder wires; Step 4: Place a polyimide film (Kapton Tape) on the silicone gel; Step 5: Flip the metal frame that fixes the LED chip so that the LED is facing the photosensitive area PD of the chip below (this process is a non-standard process and requires the development of a customized machine to perform, or manual flipping, which is inefficient and has a low yield); Step 6: Injection molding; Step 7: Bending the output pin into shape. The above seven steps are relatively complicated, among which steps 3, 4 and 5 are all non-standard processes. Either a customized machine needs to be developed to perform the process, which has high production costs, or manual operation is required, which has low work efficiency and low product yield.
因此，迫切需要提供一种光耦隔离器及其封装工艺以克服现有技术存在的上述技术缺陷。 Therefore, there is an urgent need to provide an optical coupler isolator and a packaging process thereof to overcome the above-mentioned technical defects in the prior art.
发明内容Summary of the invention
为此，本发明所要解决的技术问题在于克服现有技术中存在的技术缺陷，而提出一种光耦隔离器及其封装工艺，其可以很方便的进行光耦隔离器的封装，并不需要特殊的工艺，显著降低了生产成本，并且实现了完全的物理隔离，具有更高的隔离性能，尺寸小，可靠性更高。To this end, the technical problem to be solved by the present invention is to overcome the technical defects existing in the prior art, and propose an optocoupler isolator and its packaging process, which can conveniently package the optocoupler isolator without requiring special processes, significantly reducing production costs, and achieving complete physical isolation, with higher isolation performance, small size, and higher reliability.
为解决上述技术问题，本发明提供了一种光耦隔离器封装工艺，该光耦隔离器包括接收集成电路和发射集成电路，所述接收集成电路包括具有光电二极管感应的接收芯片，所述发射集成电路包括光电二极管发射芯片和ASIC芯片，所述ASIC芯片连接所述光电二极管发射芯片；In order to solve the above technical problems, the present invention provides a packaging process for an optocoupler isolator, wherein the optocoupler isolator comprises a receiving integrated circuit and a transmitting integrated circuit, wherein the receiving integrated circuit comprises a receiving chip with a photodiode sensor, and the transmitting integrated circuit comprises a photodiode transmitting chip and an ASIC chip, wherein the ASIC chip is connected to the photodiode transmitting chip;
所述光耦隔离器的封装工艺包括以下步骤：The packaging process of the optical coupler isolator comprises the following steps:
S10：制作接收集成电路和发射集成电路；S10: making a receiving integrated circuit and a transmitting integrated circuit;
S20：在接收集成电路的底部从上至下依次设置有第一钝化层、第一重布线层和第二钝化层，同时在接收集成电路的顶部设置有第三钝化层，在第三钝化层上开孔填铜，并在第三钝化层上设置第四重布线层，通过开孔填铜将光电二极管接收芯片的输出连接底部的第一重布线层；S20: a first passivation layer, a first redistribution layer, and a second passivation layer are sequentially arranged from top to bottom at the bottom of the receiving integrated circuit, and a third passivation layer is arranged at the top of the receiving integrated circuit, a hole is opened and filled with copper on the third passivation layer, and a fourth redistribution layer is arranged on the third passivation layer, and the output of the photodiode receiving chip is connected to the first redistribution layer at the bottom through the hole filled with copper;
S30：将发射集成电路倒置于接收集成电路上，并将发射集成电路和接收集成电路粘接为一体，构成光耦隔离模块，其中所述发射集成电路与所述接收集成电路之间设置有隔离层；S30: placing the transmitting integrated circuit upside down on the receiving integrated circuit, and bonding the transmitting integrated circuit and the receiving integrated circuit together to form an optical coupling isolation module, wherein an isolation layer is provided between the transmitting integrated circuit and the receiving integrated circuit;
S40：在所述光耦隔离模块上表面从上至下依次设置有第五钝化层、第二重布线层和第四钝化层。S40: a fifth passivation layer, a second redistribution layer and a fourth passivation layer are sequentially arranged on the upper surface of the optical coupling isolation module from top to bottom.
在本发明的一个实施例中，在S10中，制作接收集成电路的方法包括：In one embodiment of the present invention, in S10, the method for manufacturing a receiving integrated circuit includes:
将具有光电二极管感应的接收芯片设置于载体基板上，并进行注塑成型；The receiving chip with photodiode sensing is arranged on the carrier substrate and injection molded;
在注塑成型后去除载体基板，然后在第一注塑体上开通孔填铜。 After injection molding, the carrier substrate is removed, and then through holes are opened in the first injection molded body and filled with copper.
在本发明的一个实施例中，在S10中，制作发射集成电路的方法包括：In one embodiment of the present invention, in S10, the method for manufacturing a transmitting integrated circuit includes:
将光电二极管发射芯片和ASIC芯片设置于载体基板上，并进行注塑成型；The photodiode emission chip and the ASIC chip are arranged on a carrier substrate and injection molded;
在注塑成型后去除载体基板，然后在第二注塑体上开通孔填铜；After injection molding, the carrier substrate is removed, and then through holes are opened in the second injection molded body and filled with copper;
在光电二极管发射芯片、ASIC芯片及第二注塑体的上表面设置第六钝化层，并在所述第六钝化层上设置第三重布线层，通过第二注塑体上的开孔填铜以及第二重布线层将光电二极管发射芯片的两极和ASIC芯片的驱动输出相连，并通过隔离层边缘的通孔填铜及第三钝化层和第一注塑体开孔填铜将ASIC芯片的输出连接底部的第一重布线层；其中隔离层边缘的通孔填铜并不影响隔离层对发射和接收的隔离性能。A sixth passivation layer is arranged on the upper surfaces of the photodiode emission chip, the ASIC chip and the second injection molding body, and a third rewiring layer is arranged on the sixth passivation layer. The two electrodes of the photodiode emission chip and the driving output of the ASIC chip are connected through the copper-filled openings on the second injection molding body and the second rewiring layer, and the output of the ASIC chip is connected to the first rewiring layer at the bottom through the copper-filled through holes at the edge of the isolation layer and the copper-filled through holes of the third passivation layer and the first injection molding body; wherein the copper-filled through holes at the edge of the isolation layer do not affect the isolation performance of the isolation layer for transmission and reception.
在本发明的一个实施例中，在S30中，通过热压的方式或其它接合方式将发射集成电路和接收集成电路粘接为一体，构成光耦隔离模块，在光耦隔离模块中，由光电二极管发射芯片发射的信号穿过所述隔离层被所述具有光电二极管感应的接收芯片接收。In one embodiment of the present invention, in S30, the transmitting integrated circuit and the receiving integrated circuit are bonded together by heat pressing or other bonding methods to form an optocoupler isolation module. In the optocoupler isolation module, the signal emitted by the photodiode transmitting chip passes through the isolation layer and is received by the receiving chip with photodiode sensing.
在本发明的一个实施例中，所述发射集成电路的通孔没有穿透隔离层，且通孔穿透了第二注塑体，将光电二极管发射芯片的两极和ASIC芯片的驱动输出相连。In one embodiment of the present invention, the through hole of the emission integrated circuit does not penetrate the isolation layer, and the through hole penetrates the second injection molded body, connecting the two electrodes of the photodiode emission chip and the driving output of the ASIC chip.
在本发明的一个实施例中，封装多个光耦通道时，在所述隔离层、第三钝化层和第六钝化层上设置具有连通的隔断墙，通过隔断墙隔绝临近通道的光电二极管发射芯片的光线干扰。In one embodiment of the present invention, when packaging multiple optical coupling channels, connected partition walls are provided on the isolation layer, the third passivation layer and the sixth passivation layer, and the light interference of the photodiode emission chip of the adjacent channel is isolated by the partition wall.
在本发明的一个实施例中，所述隔断腔填充有能够阻挡光线的有机材料。In one embodiment of the present invention, the partition cavity is filled with an organic material capable of blocking light.
此外，本发明还提供一种光耦隔离器，该光耦隔离器根据上述所述的一种光耦隔离器封装工艺制得。In addition, the present invention also provides an optocoupler isolator, which is manufactured according to the above-mentioned optocoupler isolator packaging process.
本发明的上述技术方案相比现有技术具有以下优点：The above technical solution of the present invention has the following advantages compared with the prior art:
1、本发明所述的一种光耦隔离器及其封装工艺，其可以很方便的进行 光耦隔离器的封装，并不需要特殊的工艺，显著降低了生产成本，并且实现了完全的物理隔离，具有更高的隔离性能，尺寸小，可靠性更高；1. The optical coupler isolator and its packaging process described in the present invention can be easily The packaging of the optocoupler isolator does not require special processes, which significantly reduces the production cost and achieves complete physical isolation. It has higher isolation performance, small size and higher reliability.
2、本发明所述的一种光耦隔离器及其封装工艺，其允许一个器件内部封装一个或者多个光耦通道，通道之间可以有效的实现光线串扰的隔离。2. The optical coupler isolator and packaging process thereof described in the present invention allow one or more optical coupler channels to be packaged inside a device, and optical crosstalk isolation between the channels can be effectively achieved.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
为了使本发明的内容更容易被清楚的理解，下面根据本发明的具体实施例并结合附图，对本发明作进一步详细的说明，其中In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments of the present invention in conjunction with the accompanying drawings, wherein
图1是本发明提出的一种光耦隔离器封装工艺的示意图。FIG. 1 is a schematic diagram of an optocoupler isolator packaging process proposed by the present invention.
图2是本发明提出的一种光耦隔离器的结构示意图。FIG. 2 is a schematic diagram of the structure of an optical coupler isolator proposed by the present invention.
图3是本发明提出的一种光耦隔离器的结构示意图。FIG. 3 is a schematic diagram of the structure of an optical coupler isolator proposed by the present invention.
图4是本发明光耦隔离模块采用传统封装的产品结构示意图。FIG. 4 is a schematic diagram of the product structure of the optical coupling isolation module of the present invention using traditional packaging.
其中，附图标记说明如下：1、接收集成电路；2、接收芯片；3、发射集成电路；4、光电二极管发射芯片；5、ASIC芯片；6、第一钝化层；7、第二钝化层；8、第三钝化层；9、第四钝化层；10、第五钝化层；11、第六钝化层；12、第一重布线层；13、第二重布线层；14、第三重布线层；15、第四重布线层；16、隔离层；17、第一注塑体；18、隔断墙；19、第二注塑体。Among them, the figure marks are explained as follows: 1. receiving integrated circuit; 2. receiving chip; 3. transmitting integrated circuit; 4. photodiode transmitting chip; 5. ASIC chip; 6. first passivation layer; 7. second passivation layer; 8. third passivation layer; 9. fourth passivation layer; 10. fifth passivation layer; 11. sixth passivation layer; 12. first redistribution layer; 13. second redistribution layer; 14. third redistribution layer; 15. fourth redistribution layer; 16. isolation layer; 17. first injection molding body; 18. partition wall; 19. second injection molding body.
具体实施方式Detailed ways
下面结合附图和具体实施例对本发明作进一步说明，以使本领域的技术人员可以更好地理解本发明并能予以实施，但所举实施例不作为对本发明的限定。The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.
参照图1所示，本发明实施例提供了一种光耦隔离器封装工艺，该光耦隔离器包括接收集成电路1和发射集成电路3，接收集成电路1包括具有光电二极管感应的接收芯片2，发射集成电路3包括光电二极管发射芯片4和ASIC芯片5，所述ASIC芯片5连接所述光电二极管发射芯片4；；其中，所述光耦 隔离器的封装工艺包括以下步骤：1, an embodiment of the present invention provides an optocoupler isolator packaging process, the optocoupler isolator includes a receiving integrated circuit 1 and a transmitting integrated circuit 3, the receiving integrated circuit 1 includes a receiving chip 2 with a photodiode sensor, the transmitting integrated circuit 3 includes a photodiode transmitting chip 4 and an ASIC chip 5, the ASIC chip 5 is connected to the photodiode transmitting chip 4; wherein the optocoupler The packaging process of the isolator includes the following steps:
S10：制作接收集成电路1和发射集成电路3；S10: manufacturing a receiving integrated circuit 1 and a transmitting integrated circuit 3;
S20：在接收集成电路1的底部从上至下依次设置有第一钝化层6、第一重布线层12和第二钝化层7，同时在接收集成电路1的顶部设置有第三钝化层8，并在第三钝化层8上开孔填铜，并在第三钝化层8上设置第四重布线层15，通过开孔填铜将具有光电二极管感应的接收芯片2的输出连接底部的第一重布线层12；；S20: A first passivation layer 6, a first rewiring layer 12 and a second passivation layer 7 are sequentially arranged at the bottom of the receiving integrated circuit 1 from top to bottom, and a third passivation layer 8 is arranged at the top of the receiving integrated circuit 1, and a hole is opened on the third passivation layer 8 and filled with copper, and a fourth rewiring layer 15 is arranged on the third passivation layer 8, and the output of the receiving chip 2 with photodiode sensing is connected to the first rewiring layer 12 at the bottom through the hole filling with copper;
S30：将发射集成电路3倒置于接收集成电路1上，并将发射集成电路3和接收集成电路1粘接为一体，构成光耦隔离模块，其中所述发射集成电路3与所述接收集成电路1之间设置有隔离层16；S30: Invert the transmitting integrated circuit 3 onto the receiving integrated circuit 1, and bond the transmitting integrated circuit 3 and the receiving integrated circuit 1 together to form an optical coupling isolation module, wherein an isolation layer 16 is provided between the transmitting integrated circuit 3 and the receiving integrated circuit 1;
S40：在所述光耦隔离模块上表面从上至下依次设置有第五钝化层10、第二重布线层13和第四钝化层9。S40: a fifth passivation layer 10, a second redistribution layer 13 and a fourth passivation layer 9 are sequentially arranged on the upper surface of the optical coupling isolation module from top to bottom.
本发明所述的一种光耦隔离器封装工艺，其可以很方便的进行光耦隔离器的封装，并不需要特殊的工艺，显著降低了生产成本，并且实现了完全的物理隔离，具有更高的隔离性能，尺寸小，可靠性更高。The optocoupler isolator packaging process described in the present invention can conveniently package the optocoupler isolator without requiring special processes, significantly reducing production costs, and achieving complete physical isolation, with higher isolation performance, small size, and higher reliability.
其中，在S10中，制作接收集成电路1的方法包括：将具有光电二极管感应的接收芯片2设置于载体基板上，并进行注塑成型；在注塑成型后去除载体基板，然后在第一注塑体17上开孔填铜。In S10 , the method for manufacturing the receiving integrated circuit 1 includes: placing the receiving chip 2 with photodiode sensing on a carrier substrate and performing injection molding; removing the carrier substrate after injection molding, and then opening holes in the first injection molded body 17 and filling copper.
同样地，在S10中，制作发射集成电路3的方法包括：将光电二极管发射芯片4和ASIC芯片5设置于载体基板上，并进行注塑成型；在注塑成型后去除载体基板，然后在第二注塑体19上开孔填铜；在光电二极管发射芯片4、ASIC芯片5及第二注塑体19的上表面设置第六钝化层11，并在所述第六钝化层11上设置第三重布线层14，通过第二注塑体19上的开孔填铜及第二重布线层13将光电二极管发射芯片4的两极和ASIC芯片5的驱动输出相连，并通过隔离层16边缘的通孔填铜及第三钝化层8和第一注塑体17开孔填铜将ASIC 芯片的输出连接底部的第一重布线层12；其中隔离层边缘的通孔填铜并不影响隔离层对发射和接收的隔离性能。Similarly, in S10, the method for manufacturing the emission integrated circuit 3 includes: arranging the photodiode emission chip 4 and the ASIC chip 5 on the carrier substrate and performing injection molding; removing the carrier substrate after the injection molding, and then opening holes and filling copper on the second injection molding body 19; arranging a sixth passivation layer 11 on the upper surface of the photodiode emission chip 4, the ASIC chip 5 and the second injection molding body 19, and arranging a third redistribution layer 14 on the sixth passivation layer 11, connecting the two electrodes of the photodiode emission chip 4 and the driving output of the ASIC chip 5 through the openings and copper filling on the second injection molding body 19 and the second redistribution layer 13, and connecting the ASIC 5 through the through-holes and copper filling on the edges of the isolation layer 16 and the openings and copper filling on the third passivation layer 8 and the first injection molding body 17. The output of the chip is connected to the first redistribution layer 12 at the bottom; wherein the copper filling of the through hole at the edge of the isolation layer does not affect the isolation performance of the isolation layer for transmission and reception.
其中，在S30中，通过热压的方式或其它接合方式将发射集成电路3和接收集成电路1粘接为一体，构成光耦隔离模块。在光耦隔离模块中，由光电二极管发射芯片4发射的信号穿过所述隔离层16被所述具有光电二极管感应的接收芯片2接收。In S30, the transmitting integrated circuit 3 and the receiving integrated circuit 1 are bonded together by heat pressing or other bonding methods to form an optical coupling isolation module. In the optical coupling isolation module, the signal emitted by the photodiode transmitting chip 4 passes through the isolation layer 16 and is received by the receiving chip 2 with photodiode sensing.
请参阅图2所示，作为优选地的一个实施方案，所述隔离层16为透明隔离层16，上述所述发射集成电路3的通孔没有穿透透明隔离层16，且通孔穿透了发射集成电路3的第二注塑体19，将ASIC芯片5的焊盘信号带到整个光耦隔离模块的上方，这个结构保证了透明隔离层16的完整性，没有任何金属穿越这个透明隔离层16，从而可以实现更高电压的隔离性能。Please refer to FIG. 2 , as a preferred embodiment, the isolation layer 16 is a transparent isolation layer 16, the through hole of the transmitting integrated circuit 3 does not penetrate the transparent isolation layer 16, and the through hole penetrates the second injection molded body 19 of the transmitting integrated circuit 3, bringing the pad signal of the ASIC chip 5 to the top of the entire optocoupler isolation module. This structure ensures the integrity of the transparent isolation layer 16, and no metal passes through the transparent isolation layer 16, thereby achieving higher voltage isolation performance.
上述重布线层分别在不同的层面形成了焊盘,这些焊盘之后会通过金线连接金属框架,从而也可以让光耦隔离模块采用传统的封装工艺制成。金属框架的管脚做的比较高，这样可以减少金线的长度，从而增加稳定性，降低成本，请参照图4所示。The above-mentioned redistribution layers form pads at different levels, which will be connected to the metal frame through gold wires, so that the optocoupler isolation module can be made using traditional packaging processes. The pins of the metal frame are made relatively high, which can reduce the length of the gold wire, thereby increasing stability and reducing costs, as shown in Figure 4.
请参阅图3所示，在本发明的一个实施例中，封装多个光耦通道时，在所述隔离层16和第三钝化层8上设置具有连通的隔断墙18，所述隔断墙18是具有能够阻挡光线的有机材料，通过隔断墙18隔绝临近通道的光电二极管发射芯片4的光线干扰，从而实现多通道隔离。Please refer to FIG. 3 . In one embodiment of the present invention, when encapsulating multiple optocoupler channels, a connected partition wall 18 is provided on the isolation layer 16 and the third passivation layer 8. The partition wall 18 is an organic material capable of blocking light. The partition wall 18 is used to isolate the light interference of the photodiode emission chip 4 of the adjacent channel, thereby realizing multi-channel isolation.
本发明所述的一种光耦隔离器封装工艺，其允许一个器件内部封装一个或者多个光耦通道，通道之间可以有效的实现光线串扰的隔离。The optocoupler isolator packaging process described in the present invention allows one or more optocoupler channels to be packaged inside a device, and optical crosstalk isolation can be effectively achieved between the channels.
相应于上述一种光耦隔离器封装工艺的实施例，本发明还提供一种光耦隔离器，该光耦隔离器根据上述所述的一种光耦隔离器封装工艺制得。Corresponding to the embodiment of the above-mentioned optocoupler isolator packaging process, the present invention further provides an optocoupler isolator, which is manufactured according to the above-mentioned optocoupler isolator packaging process.
其中，所述接收集成电路1包括具有光电二极管感应的接收芯片2，具有光电二极管感应的接收芯片2设置于载体基板上并进行注塑成型，在注塑成型 后去除载体基板，然后在第一注塑体17上开孔填铜。The receiving integrated circuit 1 includes a receiving chip 2 with a photodiode sensor, and the receiving chip 2 with a photodiode sensor is arranged on a carrier substrate and injection molded. The carrier substrate is then removed, and holes are opened in the first injection molded body 17 and filled with copper.
同样地，在S10中，制作发射集成电路3的方法包括：将光电二极管发射芯片4和ASIC芯片5设置于载体基板上，并进行注塑成型；在注塑成型后去除载体基板，然后在第二注塑体19上开孔填铜；在光电二极管发射芯片4、IC芯片5及第二注塑体19的上表面设置第六钝化层11，并在所述第六钝化层11上设置第三重布线层14，通过第二注塑体19上的开孔填铜及第二重布线层13将光电二极管发射芯片4的两极和ASIC芯片5的驱动输出相连。并通过隔离层边缘的通孔填铜及第三钝化层8和第一注塑体17开孔填铜将ASIC芯片的输出连接底部的第一重布线层12。其中隔离层边缘的通孔填铜并不影响隔离层对发射和接收的隔离性能。Similarly, in S10, the method for making the transmitting integrated circuit 3 includes: placing the photodiode transmitting chip 4 and the ASIC chip 5 on the carrier substrate and performing injection molding; removing the carrier substrate after injection molding, and then opening holes and filling copper on the second injection molding body 19; setting the sixth passivation layer 11 on the upper surface of the photodiode transmitting chip 4, the IC chip 5 and the second injection molding body 19, and setting the third rewiring layer 14 on the sixth passivation layer 11, connecting the two poles of the photodiode transmitting chip 4 and the driving output of the ASIC chip 5 through the openings and copper filling on the second injection molding body 19 and the second rewiring layer 13. And the output of the ASIC chip is connected to the first rewiring layer 12 at the bottom through the copper filling of the through holes at the edge of the isolation layer and the openings and copper filling of the third passivation layer 8 and the first injection molding body 17. The copper filling of the through holes at the edge of the isolation layer does not affect the isolation performance of the isolation layer for transmission and reception.
其中，通过热压的方式或其它接合方式将发射集成电路3和接收集成电路1粘接为一体，构成光耦隔离模块。在光耦隔离模块中，由光电二极管发射芯片4发射的信号穿过所述隔离层16被所述具有光电二极管感应的接收芯片2接收。The transmitting integrated circuit 3 and the receiving integrated circuit 1 are bonded together by heat pressing or other bonding methods to form an optical coupling isolation module. In the optical coupling isolation module, the signal emitted by the photodiode transmitting chip 4 passes through the isolation layer 16 and is received by the receiving chip 2 with photodiode sensing.
请参阅图2所示，作为优选地的一个实施方案，所述隔离层16为透明隔离层16，上述所述发射集成电路3的通孔没有穿透透明隔离层16，且通孔穿透了发射集成电路3的第二注塑体19，将ASIC芯片5的焊盘信号带到整个光耦隔离模块块的上方，这个结构保证了透明隔离层16的完整性，没有任何金属穿越这个透明隔离层16，从而可以实现更高电压的隔离性能。Please refer to FIG. 2 , as a preferred embodiment, the isolation layer 16 is a transparent isolation layer 16, the through hole of the transmitting integrated circuit 3 does not penetrate the transparent isolation layer 16, and the through hole penetrates the second injection molded body 19 of the transmitting integrated circuit 3, bringing the pad signal of the ASIC chip 5 to the top of the entire optocoupler isolation module block. This structure ensures the integrity of the transparent isolation layer 16, and no metal passes through the transparent isolation layer 16, thereby achieving higher voltage isolation performance.
上述重布线层分别在不同的层面形成了焊盘,这些焊盘之后会通过金线连接金属框架,从而也可以让光耦隔离模块采用传统的封装工艺制成。金属框架的管脚做的比较高，这样可以减少金线的长度，从而增加稳定性，降低成本，请参照图4所示。The above-mentioned redistribution layers form pads at different levels, which will be connected to the metal frame through gold wires, so that the optocoupler isolation module can be made using traditional packaging processes. The pins of the metal frame are made relatively high, which can reduce the length of the gold wire, thereby increasing stability and reducing costs, as shown in Figure 4.
请参阅图3所示，在本发明的一个实施例中，封装多个光耦通道时，在所述隔离层16和第三钝化层8上设置具有连通的隔断墙18，所述隔断墙18是具有能够阻挡光线的有机材料，如环氧树脂等，通过隔断墙18隔绝临近通道 的光电二极管发射芯片4的光线干扰，从而实现多通道隔离。Please refer to FIG. 3 . In one embodiment of the present invention, when encapsulating multiple optical coupling channels, a connected partition wall 18 is provided on the isolation layer 16 and the third passivation layer 8. The partition wall 18 is made of an organic material capable of blocking light, such as epoxy resin, and the adjacent channels are isolated by the partition wall 18. The light interference of the photodiode emission chip 4 is eliminated, thereby achieving multi-channel isolation.
本实施例的一种光耦隔离器由前述的光耦隔离器封装工艺制得，因此该光耦隔离器的具体实施方式可见前文中的光耦隔离器封装工艺的实施例部分，所以，其具体实施方式可以参照相应的各个部分实施例的描述，在此不再展开介绍。An optocoupler isolator of the present embodiment is manufactured by the aforementioned optocoupler isolator packaging process, so the specific implementation of the optocoupler isolator can be seen in the embodiment section of the optocoupler isolator packaging process in the previous text. Therefore, its specific implementation can refer to the description of the corresponding embodiments of each part, which will not be introduced in detail here.
显然，上述实施例仅仅是为清楚地说明所作的举例，并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引申出的显而易见的变化或变动仍处于本发明创造的保护范围之中。 Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims (8)

  1. 一种光耦隔离器封装工艺，其特征在于：该光耦隔离器包括接收集成电路和发射集成电路，所述接收集成电路包括具有光电二极管感应的接收芯片，所述发射集成电路包括光电二极管发射芯片和ASIC芯片，所述ASIC芯片连接所述光电二极管发射芯片；A packaging process for an optocoupler isolator, characterized in that: the optocoupler isolator comprises a receiving integrated circuit and a transmitting integrated circuit, the receiving integrated circuit comprises a receiving chip with a photodiode sensor, the transmitting integrated circuit comprises a photodiode transmitting chip and an ASIC chip, and the ASIC chip is connected to the photodiode transmitting chip;
    所述光耦隔离器的封装工艺包括以下步骤：The packaging process of the optical coupler isolator comprises the following steps:
    S10：制作接收集成电路和发射集成电路；S10: making a receiving integrated circuit and a transmitting integrated circuit;
    S20：在接收集成电路的底部从上至下依次设置有第一钝化层、第一重布线层和第二钝化层，同时在接收集成电路的顶部设置有第三钝化层，在第三钝化层上开孔填铜，并在第三钝化层上设置第四重布线层，通过开孔填铜将具有光电二极管感应的接收芯片的输出连接底部的第一重布线层；S20: a first passivation layer, a first redistribution layer, and a second passivation layer are sequentially arranged from top to bottom at the bottom of the receiving integrated circuit, and a third passivation layer is arranged at the top of the receiving integrated circuit, a hole is opened and copper is filled in the third passivation layer, and a fourth redistribution layer is arranged on the third passivation layer, and the output of the receiving chip with photodiode sensing is connected to the first redistribution layer at the bottom through the hole filled with copper;
    S30：将发射集成电路倒置于接收集成电路上，并将发射集成电路和接收集成电路粘接为一体，构成光耦隔离模块，其中所述发射集成电路与所述接收集成电路之间设置有隔离层；S30: placing the transmitting integrated circuit upside down on the receiving integrated circuit, and bonding the transmitting integrated circuit and the receiving integrated circuit together to form an optical coupling isolation module, wherein an isolation layer is provided between the transmitting integrated circuit and the receiving integrated circuit;
    S40：在所述光耦隔离模块上表面从上至下依次设置有第五钝化层、第二重布线层和第四钝化层。S40: a fifth passivation layer, a second redistribution layer and a fourth passivation layer are sequentially arranged on the upper surface of the optical coupling isolation module from top to bottom.
  2. 根据权利要求1所述的一种光耦隔离器封装工艺，其特征在于：在S10中，制作接收集成电路的方法包括：The optical coupler isolator packaging process according to claim 1 is characterized in that: in S10, the method for manufacturing a receiving integrated circuit comprises:
    将具有光电二极管感应的接收芯片设置于载体基板上，并进行注塑成型；The receiving chip with photodiode sensing is arranged on the carrier substrate and injection molded;
    在注塑成型后去除载体基板，然后在第一注塑体上开通孔填铜。After injection molding, the carrier substrate is removed, and then through holes are opened in the first injection molded body and filled with copper.
  3. 根据权利要求2所述的一种光耦隔离器封装工艺，其特征在于：在S10中，制作发射集成电路的方法包括： The optical coupler isolator packaging process according to claim 2 is characterized in that: in S10, the method for manufacturing the transmitting integrated circuit comprises:
    将光电二极管发射芯片和ASIC芯片设置于载体基板上，并进行注塑成型；The photodiode emission chip and the ASIC chip are arranged on a carrier substrate and injection molded;
    在注塑成型后去除载体基板，然后在第二注塑体上开通孔填铜；After injection molding, the carrier substrate is removed, and then through holes are opened in the second injection molded body and filled with copper;
    在光电二极管发射芯片、ASIC芯片及第二注塑体的上表面设置第六钝化层，并在所述第六钝化层上设置第三重布线层，通过第二注塑体上的开通孔填铜以及第二重布线层将光电二极管发射芯片的两极和ASIC芯片的驱动输出相连，并通过隔离层边缘的通孔填铜及第三钝化层和第一注塑体开孔填铜将ASIC芯片的输出连接底部的第一重布线层。A sixth passivation layer is arranged on the upper surfaces of the photodiode emission chip, the ASIC chip and the second injection molding body, and a third rewiring layer is arranged on the sixth passivation layer. The two electrodes of the photodiode emission chip and the driving output of the ASIC chip are connected through the copper-filled through-holes on the second injection molding body and the second rewiring layer, and the output of the ASIC chip is connected to the first rewiring layer at the bottom through the copper-filled through-holes at the edge of the isolation layer and the copper-filled through-holes of the third passivation layer and the first injection molding body.
  4. 根据权利要求1所述的一种光耦隔离器封装工艺，其特征在于：在S30中，将发射集成电路和接收集成电路粘接为一体，构成光耦隔离模块，在光耦隔离模块中，由光电二极管发射芯片发射的信号穿过所述隔离层被所述具有光电二极管感应的接收芯片接收。According to the optocoupler isolator packaging process described in claim 1, it is characterized in that: in S30, the transmitting integrated circuit and the receiving integrated circuit are bonded together to form an optocoupler isolation module, in which the signal emitted by the photodiode transmitting chip passes through the isolation layer and is received by the receiving chip with photodiode sensing.
  5. 根据权利要求4所述的一种光耦隔离器封装工艺，其特征在于：所述发射集成电路的通孔没有穿透隔离层，且通孔穿透了第二注塑体，将光电二极管发射芯片的两极和ASIC芯片的驱动输出相连。According to the optocoupler isolator packaging process described in claim 4, it is characterized in that: the through hole of the transmitting integrated circuit does not penetrate the isolation layer, and the through hole penetrates the second injection molded body, connecting the two poles of the photodiode transmitting chip and the driving output of the ASIC chip.
  6. 根据权利要求1所述的一种光耦隔离器封装工艺，其特征在于：封装多个光耦通道时，在所述隔离层、第三钝化层和第六钝化层上设置具有连通的隔断墙，通过隔断墙隔绝临近通道的光电二极管发射芯片的光线干扰。According to the optocoupler isolator packaging process described in claim 1, it is characterized in that: when packaging multiple optocoupler channels, a connected partition wall is set on the isolation layer, the third passivation layer and the sixth passivation layer, and the light interference of the photodiode emission chip of the adjacent channel is isolated by the partition wall.
  7. 根据权利要求6所述的一种光耦隔离器封装工艺，其特征在于：所述隔断墙是具有能够阻挡光线的有机材料。According to the optocoupler isolator packaging process of claim 6, it is characterized in that the partition wall is made of an organic material capable of blocking light.
  8. 一种光耦隔离器，其特征在于：该光耦隔离器根据权利要求1至7任一项所述的一种光耦隔离器封装工艺制得。 An optocoupler isolator, characterized in that the optocoupler isolator is manufactured according to the optocoupler isolator packaging process according to any one of claims 1 to 7.
PCT/CN2023/089365 2022-12-14 2023-04-20 Optoisolator and packaging process therefor WO2024124763A1 (en)

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