WO2024124494A1 - 一种显示装置 - Google Patents

一种显示装置 Download PDF

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Publication number
WO2024124494A1
WO2024124494A1 PCT/CN2022/139390 CN2022139390W WO2024124494A1 WO 2024124494 A1 WO2024124494 A1 WO 2024124494A1 CN 2022139390 W CN2022139390 W CN 2022139390W WO 2024124494 A1 WO2024124494 A1 WO 2024124494A1
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WIPO (PCT)
Prior art keywords
data
data line
sub
gate
groups
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PCT/CN2022/139390
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English (en)
French (fr)
Inventor
向建民
肖利军
江鹏
李冰
张峻敏
冯蒙
江峰
程凯
帅孟超
陈航宇
白鋆
杨子铭
项玉溪
袁东旭
付伟
Original Assignee
京东方科技集团股份有限公司
武汉京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 武汉京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280005074.7A priority Critical patent/CN118575214A/zh
Priority to PCT/CN2022/139390 priority patent/WO2024124494A1/zh
Publication of WO2024124494A1 publication Critical patent/WO2024124494A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present application relates to the field of display technology, and in particular to a display device.
  • V-Block Uneven brightness in horizontal and vertical areas is a common defect in large-size display devices, especially in large-size display devices with low charging rates such as Dualgate, high refresh rate, and 8K resolution.
  • the main methods to solve the above problems include Fanout area resistance compensation and GDE (Gate Discharge Equilibrium)/PPCC (Programmable Panel Charging Compensation) compensation.
  • GDE Gate Discharge Equilibrium
  • PPCC Protein Panel Charging Compensation
  • an embodiment of the present application provides a display device, including:
  • the display panel comprises a plurality of gate lines and a plurality of data lines, wherein the gate lines intersect and are insulated from the data lines; the display panel further comprises a plurality of sub-pixels arranged in an array, wherein the gate lines and the data lines define areas where the sub-pixels are located;
  • a gate driver electrically connected to the plurality of gate lines in the display panel
  • a source driver is bound to the display panel and electrically connected to the multiple data lines in the display panel; the source driver is configured to: set the data transmission start time of each data line so that the effective charging time of each sub-pixel formed by multiple data lines and the same gate line is the same.
  • the source driver comprises a source driving unit
  • the gate driver is configured to: transmit a gate signal of a first preset time range to the gate line;
  • the source driving unit is configured to: transmit data signals to the plurality of data lines; wherein, among the plurality of data lines intersecting with the same gate line, any one of the data lines is used as a first reference data line, and the data transmission start time of the first reference data line is used as a reference time;
  • the gate signal at the intersection of the gate line with the first reference data line is transmitted earliest
  • the data transmission start time of the data lines other than the first reference data line among the plurality of data lines is later than the reference time, so that the effective charging time of each sub-pixel formed by the plurality of data lines electrically connected to the source driving unit and the same gate line is the same;
  • the gate signal at the intersection of the gate line with the first reference data line is transmitted latest, the data transmission start time of the data lines other than the first reference data line among the plurality of data lines is earlier than the reference time, so that the effective charging time of each sub-pixel formed by the plurality of data lines electrically connected to the source driving unit and the same gate line is the same;
  • the data transmission start time of the data line that is transmitted earlier than the gate signal at the intersection of the gate line with the first reference data line among the multiple data lines is earlier than the reference time; the data transmission start time of the data line that is transmitted later than the gate signal at the intersection of the gate line with the first reference data line among the multiple data lines is later than the reference time, so that the effective charging time of each sub-pixel formed by the multiple data lines electrically connected to the source driving unit and the same gate line is the same.
  • all the data lines include a plurality of first data line groups, and each of the first data line groups includes a plurality of data lines;
  • the source driving unit is configured to: among a plurality of first data line groups intersecting with the same gate line, use any one of the first data line groups as a first reference data line group, and use the data transmission start time of the first reference data line group as a reference time;
  • the gate signal at the intersection of the gate line and the first reference data line group is transmitted earliest
  • the data transmission start time of the first data line groups other than the first reference data line group among the plurality of first data line groups is later than the reference time, so that the effective charging time of each sub-pixel formed by the data lines in the plurality of first data line groups electrically connected to the source driving unit and the same gate line is the same;
  • the gate signal at the intersection of the gate line with the first reference data line group is transmitted latest, the data transmission start time of the first data line groups other than the first reference data line group among the plurality of first data line groups is earlier than the reference time, so that the effective charging time of each sub-pixel formed by the data lines in the plurality of first data line groups electrically connected to the source driving unit and the same gate line is the same;
  • the data transmission start time of the first data line group among the multiple first data line groups that is transmitted earlier than the gate signal at the intersection of the gate line and the first reference data line group is earlier than the reference time; the data transmission start time of the first data line group among the multiple first data line groups that is transmitted later than the gate signal at the intersection of the gate line and the first reference data line group is later than the reference time, so that the effective charging time of each sub-pixel formed by the data lines in the multiple first data line groups electrically connected to the source driving unit and the same gate line is the same.
  • a quotient of the number of all the data lines and the number of all the first data line groups is an integer, and the number of data lines in each of the first data line groups is the same.
  • the source driving unit is configured as follows: all the data lines in each of the first data line groups include a plurality of first sub-data line groups, each of which includes at least one data line; among the plurality of first sub-data line groups intersecting the same gate line, any one of the first sub-data line groups is used as a second reference data line group, and the data transmission start time of the second reference data line group is used as a reference time;
  • the gate signal at the intersection of the gate line and the second reference data line group is transmitted earliest
  • the data transmission start time of the first sub-data line groups other than the second reference data line group among the plurality of first sub-data line groups is later than the reference time, so that the effective charging time of each sub-pixel formed by the data lines in the plurality of first sub-data line groups electrically connected to the source driving unit and the same gate line is the same;
  • the gate signal at the intersection of the gate line with the second reference data line group is transmitted latest, the data transmission start time of the first sub-data line groups other than the second reference data line group among the plurality of first sub-data line groups is earlier than the reference time, so that the effective charging time of each sub-pixel formed by the data lines in the plurality of first sub-data line groups electrically connected to the source driving unit and the same gate line is the same;
  • the data transmission start time of the first sub-data line group among the plurality of first sub-data line groups that is transmitted earlier than the gate signal at the intersection of the gate line and the second reference data line group is earlier than the reference time; the data transmission start time of the first sub-data line group among the plurality of first sub-data line groups that is transmitted later than the gate signal at the intersection of the gate line and the second reference data line group is later than the reference time, so that the effective charging time of each sub-pixel formed by the data lines in the plurality of first sub-data line groups electrically connected to the source driving unit and the same gate line is the same.
  • data transmission start time of all the data lines in each of the first sub-data line groups is the same.
  • a plurality of the first sub-data line groups are arranged in a direction away from the gate driver in sequence; the source driving unit is configured to: among the plurality of the first sub-data line groups intersecting the same gate line, use any one of the first sub-data line groups as a third reference data line group, and the data transmission start time of the third reference data line group as a reference time;
  • the data transmission start time of the first sub-data line groups other than the third reference data line group among the plurality of first sub-data line groups is later than the reference time, so that the effective charging time of each sub-pixel formed by the data lines in the plurality of first sub-data line groups electrically connected to the source driving unit and the same gate line is the same;
  • the data transmission start time of the first sub-data line groups other than the third reference data line group among the plurality of first sub-data line groups is earlier than the reference time, so that the effective charging time of each sub-pixel formed by the data lines in the plurality of first sub-data line groups electrically connected to the source driving unit and the same gate line is the same;
  • the data transmission start time of the first sub-data line group that is closer to the source driver than the third reference data line group among the multiple first sub-data line groups is earlier than the reference time
  • the data transmission start time of the first sub-data line group that is farther from the source driver than the third reference data line group is later than the reference time
  • all the data lines intersecting the same gate line include M first data line groups, and the M first data line groups are arranged in a direction away from the gate driver in sequence;
  • the number of data lines in the first data line group of the Nth sequence is the same as the number of data lines in the first data line group of the M-N+1th sequence, and both are even numbers; wherein M is an even number greater than or equal to 2, and N is an integer greater than or equal to 1.
  • data transmission start times of the first data line groups increase sequentially.
  • each of the first data line groups includes an even number of first sub-data line groups
  • the number of the first sub-data line groups in each of the first data line groups increases sequentially.
  • data transmission start times of the first sub-data line groups in each of the first data line groups increase in sequence by the same multiple.
  • the source driver includes a plurality of source driving units
  • the gate driver is configured to: transmit a gate signal of a first preset time range to the gate line;
  • the plurality of data lines are divided into a plurality of groups, and each of the source driving units is electrically connected to a group of data lines; among the plurality of source driving units, any one of the source driving units is used as a reference source driving unit, and the remaining source driving units except the reference source driving unit are adjustment source driving units; among the plurality of groups of data lines intersecting the same gate line, any one of the data lines electrically connected to the reference source driving unit is used as a second reference data line, and the data transmission start time of the second reference data line is used as a reference time; among the data lines electrically connected to the reference source driving unit, the data line closest to the adjacent adjustment source driving unit is the first data line, and the data line closest to the reference source driving unit in the adjustment source driving unit is the second data line;
  • the data transmission start time of the first data line is later than the reference time, and the data transmission start time of the first data line is the same as the data transmission start time of the second data line, so that the effective charging time of each sub-pixel formed by the data lines in the plurality of groups of data lines electrically connected to the source driving unit and the same gate line is the same.
  • all the data lines electrically connected to the reference source driving unit are divided into a first part and a second part, the first part includes the second reference data line, and the data transmission delay time of all the data lines in the first part is different from the data transmission delay time of all the data lines in the second part.
  • a data transmission delay time of all data lines in the first part is greater than a data transmission delay time of all data lines in the second part.
  • the source driving unit includes a data input module, a multi-channel delay control module, a digital-to-analog conversion module, an output module and a logic control module;
  • the data input module is electrically connected to the logic control module and the multi-channel delay control module, and is configured to: receive and analyze the video signal under the control of the first control signal of the logic control module to obtain the first data of the video signal; and transmit the first data to the multi-channel delay control module;
  • the multi-channel delay control module is electrically connected to the logic control module and the digital-to-analog conversion module, and is configured to: receive and analyze the first data under the control of the second control signal of the logic control module to obtain second data with different starting times for each data line; and transmit the second data to the digital-to-analog conversion module;
  • the digital-to-analog conversion module is also electrically connected to the output module and is configured to: receive and convert the second data to obtain third data; and transmit the third data to the output module;
  • the output module is configured to receive and output the third data.
  • the multi-channel delay control module includes a mode selection submodule, a data selection submodule, a first grouping control submodule, a second grouping control submodule and a delay submodule;
  • the mode selection submodule is electrically connected to the data selection submodule and is configured to: receive the first data and select a delay mode under the control of the second control signal of the logic control module; and transmit the first data to the data selection submodule;
  • the data line selection submodule is also electrically connected to the first group control unit and is configured to: receive the first data under the control of the second control signal of the logic control module, determine the delay mode, and select the starting data line according to the delay mode; transmit the first data to the first group control submodule;
  • the first grouping control submodule is also electrically connected to the second grouping control unit and is configured to: receive the first data under the control of the second control signal of the logic control module, and determine a first data line group according to the starting data line;
  • the second grouping control submodule is also electrically connected to the delay unit and is configured to: receive the first data under the control of the second control signal of the logic control module, and determine a first sub-data line group according to the first data line group;
  • the delay submodule is configured to: receive the first data under the control of the second control signal of the logic control module, and parse the first data according to the first sub-data line group to obtain second data with different starting times for the data lines in the first sub-data line group.
  • FIG1 is a schematic diagram of a V-Block problem in a display panel of a related technology provided by an embodiment of the present application;
  • FIG2 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.
  • FIG3 is a schematic structural diagram of a display device in a related art provided by an embodiment of the present application.
  • FIG4 is a schematic diagram of a USI-T protocol provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of a V-Block problem in a display panel of another related technology provided by an embodiment of the present application.
  • FIG6 is a schematic diagram of a delay time of a data line in a source driving unit provided by an embodiment of the present application.
  • FIG7 is a schematic diagram of the structure of another display device provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of a delay time of a data line in a source driving unit according to a related technology provided by an embodiment of the present application;
  • FIG9 is a schematic diagram of a delay time of a data line between adjacent source driving units provided by an embodiment of the present application.
  • FIG10 is a schematic diagram of a delay time of a data line between adjacent source driving units in a related art provided by an embodiment of the present application;
  • FIG11 is a schematic diagram of the structure of a source driving unit provided in an embodiment of the present application.
  • FIG. 12 is a schematic diagram of the structure of a multi-channel control delay module provided in an embodiment of the present application.
  • plural means two or more; the orientation or positional relationship indicated by the term “on” and the like is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the structure or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.
  • the term “including” is to be interpreted as an open, inclusive meaning, that is, “including, but not limited to”.
  • the terms “one embodiment”, “some embodiments”, “exemplary embodiment”, “example”, “specific example” or “some examples” and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application.
  • the schematic representation of the above terms does not necessarily refer to the same embodiment or example.
  • the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.
  • V-Block is a common defect in large-size display devices, especially in large-size display devices with low charging rates such as dual-gate, high refresh rate, and 8K resolution.
  • the turn-on time of a row of pixels is short, and because each row of Data signals output by the source driver IC (Integrated Circuit) is jumping, the pixels are not pre-charged, resulting in less actual effective pixel charging time.
  • the resolution of the display device increases, more pixels need to be driven per unit area, resulting in the display device being unable to charge effectively, and it is easy to have the V-Block problem shown in Figure 1, where part of the screen is undercharged due to short charging time.
  • Fanout resistance compensation is the Fanout compensation of the pre-designed source driver IC, that is, by designing the routing of different channels (i.e., Data lines) on the source driver IC, the impedance difference between different Data lines matches the impedance difference of the display panel in the display device, thereby achieving the purpose of compensation charging.
  • the main disadvantages of this method are: the routing of the Data line cannot be adjusted once it is done, the display panel matching is single, the materials cannot be shared, and the compensation and display panel matching are unstable.
  • the current GDE/PPCC compensation is to improve the V-Block by controlling the source driver IC.
  • the main disadvantages of this method are: the compensation setting method is single, and the uneven differences between the Data lines cannot be compensated.
  • An embodiment of the present application provides a display device, as shown in FIG2 , including:
  • the display panel 1 includes a plurality of gate lines 8 and a plurality of data lines 9, wherein the gate lines 8 and the data lines 9 intersect and are insulated from each other; the display panel 1 also includes a plurality of sub-pixels P arranged in an array, wherein the gate lines 8 and the data lines 9 define the area where the sub-pixels P are located.
  • the gate driver 6 is electrically connected to a plurality of gate lines 8 in the display panel 1 .
  • the source driver 2 is bound to the display panel 1 and electrically connected to multiple data lines 9 in the display panel 1; the source driver 2 is configured to: set the data transmission start time of each data line 9 so that the effective charging time of each sub-pixel P formed by multiple data lines 9 and the same gate line 8 is the same.
  • the type of the above-mentioned display panel which can be an LCD (Liquid Crystal Display) or an OLED (Organic Light Emitting Diode) display panel.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • the quantitative relationship between the above-mentioned gate lines and data lines is not specifically limited here.
  • the number of gate lines and data lines can be the same; or, the number of gate lines and data lines can be different.
  • the actual number of gate lines and data lines can be determined according to the number of sub-pixels, the area of the display panel, etc.
  • FIG. 2 is illustrated by taking the display panel including three gate lines 8 and four data lines 9 as an example, in which the number of gate lines 8 and data lines 9 is different. It should be noted that, for example, for large-size products, the number of gate lines and data lines is large, and FIG. 2 fails to show all the gate lines and data lines.
  • the number of the above sub-pixels is not specifically limited here.
  • the number of the above sub-pixels may be one; or the number of the above sub-pixels may be multiple.
  • the number of sub-pixels may be determined according to the number of gate lines and data lines.
  • FIG. 2 is illustrated by taking the display panel including twelve sub-pixels P as an example.
  • the colors of the above sub-pixels are not specifically limited here.
  • the colors of the above sub-pixels may be all the same; or, the colors of the above sub-pixels may be partially the same; or, the colors of the above sub-pixels may be all different.
  • the display panel may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • the gate driver 6 can be arranged on one side of the display panel 1 as shown in FIG. 2 ; or, the gate driver can also be arranged around the display panel; of course, other arrangements are also possible, which are not listed here one by one and can be determined according to actual requirements.
  • the gate driver 6 can be set to be a single one as shown in FIG. 2 ; of course, it can also be set to be multiple.
  • the gate driver may be a GOA (Gate Driver On Array) circuit.
  • the source driver 2 can be arranged on one side of the display panel 1 and bound to one side of the display panel 1 as shown in FIG. 2 ; or, the source driver can also be arranged around the display panel and bound to the surrounding side of the display panel; of course, other settings are also possible, which are not listed here one by one and can be determined according to actual requirements.
  • the number of the above-mentioned source drivers is not specifically limited.
  • the source driver 2 can be set to be a single one as shown in FIG. 2 ; of course, it can also be set to be multiple.
  • the specific manner in which the source driver is electrically connected to the data line is not limited.
  • the source driver may be directly electrically connected to the data line; or, the source driver may be electrically connected to the data line via other structures.
  • the type of the source driver is not specifically limited.
  • the source driver may be COF (Chip On Film).
  • the display panel and the source driver can be directly bound; or, the display panel can be bound to the source driver through an FPC (Flexible Printed Circuit).
  • FPC Flexible Printed Circuit
  • the data transmission start time of each of the above data lines is the start time of transmission of the image data signal received by each of the data lines.
  • the transmission process of the image data signal is shown in FIG. 3 .
  • the front-end system (not shown in FIG3 ) is electrically connected to the interface 11 of the timing control unit 3, the timing control unit 3 is electrically connected to the flexible circuit board 4 through the interface 12, the flexible circuit board 4 is electrically connected to the printed circuit board 5 through the interface 13, the printed circuit board 5 is electrically connected to the driver chip 21-driver chip 32, and the driver chip 21-driver chip 32 is arranged on one side of the display panel 1 and bound to one side of the display panel 1.
  • FIG3 is illustrated by taking the driver chip 21-driver chip 32 as an example in which twelve rows are arranged sequentially from the left side to the right side of the display panel 1.
  • the front-end system transmits the image data signal to the timing control unit 3 through the interface 11
  • the timing control unit 3 receives the image data signal and transmits the image data signal to the flexible circuit board 4 through the interface 12
  • the flexible circuit board 4 receives the image data signal and transmits the image data signal to the printed circuit board 5 through the interface 13
  • the printed circuit board 5 transmits the image data signal to the driver chip 21-driver chip 32 respectively
  • the driver chip 21-driver chip 32 transmits the image data signal to the display panel 1 for display.
  • the above-mentioned image data signal can be transmitted according to the USI-T (Unified Standard Interface) protocol as shown in FIG4.
  • the USI-T protocol includes Frame Configuration Data, in which AD represents a flag bit, D0-D8 represents data lines 0-8, N/A represents an unused register, PPCC_M[0], PPCC_M[1], and PPCC_B[0] and PPCC_B[1] are registers for setting a multiple of the delay or advance of the start time of image data signal transmission, PPCC_SHIFT[0] and PPCC_SHIFT[1] are registers for adjusting the data transmission start time of the data line through different modes, wherein [0] represents a low level, [1] represents a high level, and Reserved represents a reserved bit, which can be used by any register.
  • image data signal can also be transmitted according to the CEDS (Clock Embedded Differential Singaling) protocol, and can be obtained according to relevant technologies, which will not be repeated here.
  • CEDS Chip Embedded Differential Singaling
  • Figure 1 is a picture of the display device without charging compensation turned on. From Figure 1, we can see a very serious V-Block split screen phenomenon. The pattern presented in each source driver IC is: the sides of the display panel are darker, the middle is brighter, and the brightness transition is uneven. The closer to the center of the display panel, the brighter the overall brightness.
  • Figure 5 is a picture of the preferred compensation method turned on within the adjustable range in the related art. From Figure 5, we can see that the middle area of the display panel after compensation is slightly improved, but there is still an obvious black block on both sides, and there are still obvious vertical dark stripes and other problems.
  • the effective charging time of the signal on the portion of the gate line far from the gate driver is shorter than the effective charging time of the signal on the portion of the gate line close to the gate driver
  • the effective charging area of the data signal and the signal on the portion of the gate line close to the gate driver is larger than the effective charging area of the data signal and the signal on the portion of the gate line far from the gate driver, thereby causing the charging time of the sub-pixel corresponding to the portion of the gate line far from the gate driver to be shorter than the charging time of the sub-pixel corresponding to the portion of the gate line close to the gate driver, and the charging effect is quite different, resulting in the V-Block phenomenon.
  • the source driver is configured to set the data transmission start time of each data line, that is, the data transmission start time of each data line can be set to be different, for example, the data transmission start time of the data line closer to the gate driver can be set to be earlier than the data transmission start time of the data line farther from the gate driver, and the data transmission start time of the data line farther from the gate driver can be set to be later than the data transmission start time of the data line closer to the gate driver.
  • each data line and the gate line define different sub-pixels
  • the data of the data lines that are closer to the gate driver can be transmitted to the corresponding sub-pixels earlier than the data of the data lines that are farther away from the gate driver, and the data of the data lines that are farther away from the gate driver can be transmitted to the corresponding sub-pixels later than the data of the data lines that are closer to the gate driver, thereby making the effective charging time of the sub-pixels formed by multiple data lines and the same gate line the same, thereby improving the display effect and providing a good user experience.
  • the source driver includes a source driving unit.
  • the gate driver is configured to transmit a gate signal within a first preset time range to the gate line.
  • the source driving unit is configured to: transmit data signals to a plurality of data lines; wherein, among the plurality of data lines intersecting with the same gate line, any data line is used as a first reference data line, and the data transmission start time of the first reference data line is used as the reference time; among the plurality of data lines intersecting with the same gate line, in the case where the gate signal at the intersection of the gate line and the first reference data line is transmitted earliest, the data transmission start time of the data lines other than the first reference data line among the plurality of data lines is later than the reference time, so that the effective charging time of each sub-pixel formed by the plurality of data lines electrically connected to the source driving unit and the same gate line is the same; among the plurality of data lines intersecting with the same gate line, the gate signal at the intersection of the gate line and the first reference data line is transmitted latest In the case where, among the multiple data lines, the data transmission start time of the data lines other than the first reference data line is earlier than the reference time, so that the effective charging time of each sub-
  • the source driver 2 includes a source driving unit, and the source driving unit is located at the left end of the display panel 1.
  • the source driving units located at other positions of the display panel can also be taken as an example, and will not be described in detail here.
  • the source driving unit may include a source driving chip, and the source driving chip may be a COF.
  • FIG2 is illustrated by taking the gate driver 6 connected to three gate lines 81, 82 and 83, and the source driving unit connected to four data lines 91, 92, 93 and 94 as an example, wherein the gate signal at the intersection of the gate line with the data line 91 is transmitted first, the gate signal at the intersection of the gate line with the data line 94 is transmitted last, and the gate signal at the intersection of the gate line with the data lines 92 and 93 is transmitted later than the gate signal at the intersection of the gate line with the data line 91, and earlier than the gate signal at the intersection of the gate line with the data line 94.
  • the gate driver is configured to transmit gate signals of a first preset time range to the gate lines 81, 82 and 83; the source driving unit is configured to transmit data signals to the data lines 91, 92, 93 and 94.
  • the gate signal is configured to control each sub-pixel to turn on.
  • the first preset time range is the duration range of the gate signal transmitted on the gate line. There is no specific limitation on the first preset time range.
  • the first preset time range can be determined according to the refresh frequency, etc.
  • the first preset time range can be in the microsecond level.
  • the data transmission start times of the data lines 92, 93 and 94 are all later than the reference time, thereby ensuring that the data signals of the data lines 91, 92, 93 and 94 are not transmitted to the sub-pixels of the display panel at the same time, specifically, the data signals of the data lines 91, 92, 93 and 94 are delayed and transmitted to the sub-pixels P1, P2, P3 and P4 in sequence.
  • the data transmission start times of the data lines 91, 92 and 93 are earlier than the reference time, thereby ensuring that the data signals of the data lines 91, 92, 93 and 94 are not transmitted to the sub-pixels of the display panel at the same time, specifically, the data signals of the data lines 91, 92, 93 and 94 are transmitted to the sub-pixels P1, P2, P3 and P4 in advance, respectively.
  • the data transmission start time of data line 91 is earlier than the reference time; since the gate signal at the intersection of gate line 81 with data lines 93 and 94 is transmitted later than the gate signal at the intersection of gate line 81 with data line 92, the data transmission start time of data lines 93 and 94 is later than the reference time, thereby ensuring that the data signals of data lines 91, 92, 93 and 94 are not transmitted to the sub-pixels of the display panel at the same time, specifically, the data signal of data line 91 is transmitted to sub-pixel P1 in advance, then the data signal of data line 92 is transmitted to sub-pixel P2, then the data signal of data line 93 is delayed and transmitted to sub-pixel P3, and finally the
  • the first reference data line among data lines 91, 92, 93 and 94 is data line 93 and its data transmission start time is the reference time
  • the gate signal at the intersection of gate line 81 with data lines 91 and 92 is transmitted earlier than the gate signal at the intersection of gate line 81 with data lines 91 and 92
  • the data transmission start time of data lines 91 and 92 is earlier than the reference time
  • the gate signal at the intersection of gate line 81 with data line 94 is transmitted later than the gate signal at the intersection of gate line 81 with data line 94
  • the data transmission start time of data line 94 is later than the reference time, thereby ensuring that the data signals of data lines 91, 92, 93 and 94 are not transmitted to the sub-pixels of the display panel at the same time
  • the data signal of data line 91 is transmitted to sub-pixel P1 in advance
  • the data signal of data line 92 is transmitted to sub-pixel P2 in advance
  • the data signal of the first data line 93 is transmitted to sub-
  • the data transmission start time is earlier than the reference time, or the data transmission start time being later than the reference time.
  • the data transmission start time may be earlier than the reference time by 2UI (Unit Delay), or the data transmission start time may be later than the reference time by -4UI.
  • the above data transmission start time can be achieved through GDE/PPCC compensation.
  • the above-mentioned data transmission start time can have three modes, namely the first mode (V-Shift mode), the second mode (L-Shift mode) and the third mode (R-Shift mode).
  • the three modes are illustrated by taking the data lines 91, 92, 93 and 94 shown in Figure 2 as an example.
  • the data transmission start time of the data line 91 and the data line 94 shown in Figure 2 is the same, and the data transmission start time of the data line 92 and the data line 93 is the same.
  • the data transmission start time of the data lines 91, 92, 93 and 94 shown in Figure 2 increases in sequence.
  • the data transmission start time of the data lines 94, 93, 92 and 91 shown in Figure 2 increases in sequence. The same can be said for other numbers of data lines, which will not be repeated here.
  • the unit delay time and multiple of the above data transmission start time that can be earlier than the reference time can be any value, such as 1UI, 2UI, 3UI, etc.
  • the above data transmission start time can be earlier than the reference time by 2UI, 4UI, 6UI, 8UI, and can also be multiplied by the delay multiples 1, 2, 3, 4 respectively, for example, 8UI can be multiplied by the delay multiples 1, 2, 3, 4 to obtain 8UI, 16UI, 24UI, 32UI.
  • the V-Block problem caused by uneven impedance changes in some areas of the source driving unit, gate signal transmission delay at the intersection of the gate line with different data lines, etc. can be well improved, thereby improving the debugging flexibility and compensation degree.
  • all the data lines include a plurality of first data line groups, and each first data line group includes a plurality of data lines.
  • the source driving unit is configured to: use any first data line group among a plurality of first data line groups intersecting the same gate line as a first reference data line group, and use the data transmission start time of the first reference data line group as the reference time.
  • the data transmission start time of the first data line groups other than the first reference data line group among the plurality of first data line groups is later than the reference time, so that the effective charging time of each sub-pixel formed by the data lines in the plurality of first data line groups electrically connected to the source driving unit and the same gate line is the same; in the case where, among the plurality of first data line groups intersecting the same gate line, the gate signal at the intersection of the gate line and the first reference data line group is transmitted latest, the data lines in the plurality of first data line groups other than the first reference data line group are transmitted later than the reference time.
  • the data transmission start time of the first data line group is earlier than the reference time, so that the effective charging time of each sub-pixel formed by the data lines in the multiple first data line groups electrically connected to the source driving unit and the same gate line is the same; in the multiple first data line groups intersecting with the same gate line, when the gate signal at the intersection of the gate line and the first reference data line group is in the middle of transmission, the data transmission start time of the first data line group in the multiple first data line groups that is transmitted earlier than the gate signal at the intersection of the gate line and the first reference data line group is earlier than the reference time; the data transmission start time of the first data line group in the multiple first data line groups that is transmitted later than the gate signal at the intersection of the gate line and the first reference data line group is later than the reference time, so that the effective charging time of each sub-pixel formed by the data lines in the multiple first data line groups electrically connected to the source driving unit and the same gate line is the same.
  • FIG6 is an example of a display device including 960 data lines, wherein the horizontal axis of FIG6 is the data line, and the vertical axis is the output delay time, and the unit is UI.
  • the 960 data lines are divided into eight first data line groups, and each first data line group includes 120 data lines.
  • the 960 data lines include a first data line group consisting of Y1-120, a first data line group consisting of Y121-240, a first data line group consisting of Y241-360, a first data line group consisting of Y361-480, a first data line group consisting of Y600-481, a first data line group consisting of Y720-601, a first data line group consisting of Y840-721, and a first data line group consisting of Y960-841.
  • the first reference data line group is the first data line group Y1-120 and Y960-841
  • the data transmission start time is the reference time, the first data line group Y121-240, Y241-360, Y361-480, Y600-481, Y720-601, Y840-721 and Y960-841.
  • the data transmission start time of Y0-601 and Y840-721 is later than the reference time, so as to ensure that the data signals of the eight first data line groups are not transmitted to the sub-pixels of the display panel at the same time.
  • the data signals of the first data line group Y1-120 and Y960-841 are transmitted to the sub-pixels, and then the data signals of the first data line group Y121-240, Y241-360, Y361-480, Y600-481, Y720-601 and Y840-721 are transmitted to the sub-pixels with delay.
  • the data signals of the first data line group Y121-240 and Y840-721 are transmitted to the sub-pixels, followed by the data signals of Y241-360 and Y720-601, and finally the data signals of Y361-480 and Y600-481 are transmitted to the sub-pixels.
  • the first reference data line group is the first data line group Y361-480 and Y600-481
  • the data transmission start time is the reference time
  • the data transmission start time of Y1-721 and Y960-841 is earlier than the reference time, so as to ensure that the data signals of the eight first data line groups are not transmitted to the sub-pixels of the display panel at the same time.
  • the data signals of the first data line groups Y1-120, Y121-240, Y241-360, Y720-601, Y840-721 and Y960-841 are transmitted to the sub-pixels in advance, and then the data signals of the first data line groups Y361-480 and Y600-481 are transmitted to the sub-pixels.
  • the data signals of Y1-120 and Y960-841 are transmitted to the sub-pixels first, then the data signals of the first data line groups Y121-240 and Y840-721 are transmitted to the sub-pixels, and finally the data signals of Y241-360 and Y720-601 are transmitted to the sub-pixels.
  • the data transmission start time of the first data line group Y1-120 and Y960-841 are both earlier than the reference time.
  • the data transmission start time of the first data line group Y241-360, Y361-480, Y600-481 and Y720-601 are all later than the reference time, thereby ensuring that the data signals of the first data line group Y241-360, Y361-480, Y600-481 and Y720-601 are delayed in transmission to the sub-pixels of the display panel.
  • the first reference data line group is the first data line group Y241-360 and Y720-601
  • the data transmission start time is the reference time, the first data line group Y1-120, Y241-360, Y840-721 and Y960-841
  • the data transmission start time of the first data line group Y361-480 and Y600-481 is later than the reference time, thereby ensuring that the data signals of the first data line group Y361-480 and Y600-481 are transmitted to the sub-pixels of the display panel in advance; the data transmission start time of the first data line group Y361-480 and Y600-481 is later than the reference time, thereby ensuring that the data signals of the first data line group Y361-480 and Y600-481 are transmitted to the sub-pixels of the display panel with delay.
  • ch in FIG. 6 represents a channel (ie, a data line).
  • the display device provided by the embodiment of the present application, by dividing all the data lines in a source driving unit into a plurality of first data line groups, and setting the data transmission start time of the plurality of first data line groups to be adjustable, the V-Block problem caused by the uneven impedance change in some areas of the source driving unit, the gate signal transmission delay at the intersection of the gate line with different data lines, etc. can be well improved, thereby improving the debugging flexibility and compensation degree.
  • the quotient of the number of all data lines and the number of all first data line groups is an integer, and the number of data lines in each first data line group is the same, which is more conducive to practical application.
  • the number of all the data lines and the number of all the first data line groups there is no specific limitation on the number of all the data lines and the number of all the first data line groups.
  • the number of all the data lines may be 960 and the number of all the first data line groups may be 8, so that the quotient of the number of all the data lines and the number of all the first data line groups is 120, that is, the number of data lines in each first data line group is 120.
  • the number of all other data lines and the number of all the first data line groups can be deduced in the same manner, and will not be described in detail here.
  • each first data line group may also be different, which is not specifically limited here.
  • the source driving unit is configured as follows: all data lines in each first data line group include multiple first sub-data line groups, and the first sub-data line group includes at least one data line; among the multiple first sub-data line groups intersecting the same gate line, any first sub-data line group is used as the second reference data line group, and the data transmission start time of the second reference data line group is used as the reference time.
  • the gate signal at the intersection of the gate line and the second reference data line group is transmitted earliest, the data transmission start time of the first sub-data line group other than the second reference data line group among the plurality of first sub-data line groups is later than the reference time, so that the effective charging time of each sub-pixel formed by the data lines in the plurality of first sub-data line groups electrically connected to the source driving unit and the same gate line is the same; in the case where, among the plurality of first sub-data line groups intersecting the same gate line, the gate signal at the intersection of the gate line and the second reference data line group is transmitted latest, the data transmission start time of the first sub-data line group other than the second reference data line group among the plurality of first sub-data line groups is earlier than the reference time, so that the data lines in the plurality of first sub-data line groups electrically connected to the source driving unit
  • the number of first sub-data line groups included in all the data lines in each of the first data line groups is not specifically limited, and by way of example, the number of first sub-data line groups included in all the data lines in each of the first data line groups may be two, three, four, etc. Further optionally, the number of first sub-data line groups may be divisible by the number of all the data lines in each of the first data line groups.
  • the number of data lines included in the first data line sub-group is not specifically limited.
  • the number of data lines included in the first data line sub-group may be one, two, three, etc.
  • the display device shown in FIG6 includes 960 data lines, and the 960 data lines are divided into eight first data line groups, specifically first data line groups Y1-120, Y121-240, Y241-360, Y361-480, Y600-481, Y720-601, Y840-721 and Y960-841.
  • the first data line group Y1-120 may be divided into four first sub-data line groups, that is, each first sub-data line group includes 30 data lines, that is, the first data line group Y1-120 includes first sub-data line groups Y1-30, Y31-60, Y61-90 and Y91-120.
  • the data transmission start time of the first sub-data line group Y31-60, Y61-90 and Y91-120 is later than the reference time, thereby ensuring that the data signals of the four first sub-data line groups are not transmitted to the sub-pixels of the display panel at the same time, specifically, the data signals of the first sub-data line groups Y31-60, Y61-90 and Y91-120 are transmitted to the sub-pixels in sequence with delayed transmission.
  • the data transmission start time of the first sub-data line group Y1-30, Y31-60 and Y61-90 are all earlier than the reference time, thereby ensuring that the data signals of the four first sub-data line groups are not transmitted to the sub-pixels of the display panel at the same time, specifically, the data signals of the first sub-data line groups Y1-30, Y31-60 and Y61-90 are transmitted to the sub-pixels in advance in sequence.
  • the data transmission start time of the first sub-data line group Y1-30 is earlier than the reference time, thereby ensuring that the data signals of the four first sub-data line groups are not transmitted to the sub-pixels of the display panel at the same time, specifically, the data signals of the first sub-data line group Y1-30 are transmitted to the sub-pixels in advance; the data transmission start times of the first sub-data line groups Y61-90 and Y91-120 are later than the reference time, thereby ensuring that the data signals of the four first sub-data line groups are not transmitted to the sub-pixels of the display panel at the same time, specifically, the data delays of the first sub-data line groups Y61-90 and Y91-120 are transmitted to the sub-pixels in advance.
  • the data transmission start time of the first sub-data line groups Y1-30 and Y31-60 are earlier than the reference time, thereby ensuring that the data signals of the four first sub-data line groups are not transmitted to the sub-pixels of the display panel at the same time, specifically, the data signals of the first sub-data line groups Y1-30 and Y31-60 are transmitted to the sub-pixels in advance; the data transmission start time of the first sub-data line group Y91-120 is later than the reference time, thereby ensuring that the data signals of the four first sub-data line groups are not transmitted to the sub-pixels of the display panel at the same time, specifically, the data delay of the first sub-data line group Y91-120 is transmitted to the sub-pixels in advance.
  • the display device by dividing all the data lines in a source driving unit into a plurality of first data line groups, and then dividing each first data line group into a plurality of first sub-data line groups, and setting the data transmission start time of the plurality of first sub-data line groups to be adjustable, the V-Block problem caused by uneven impedance changes in some areas of the source driving unit, gate signal transmission delay at the intersection of the gate line with different data lines, etc. can be well improved, thereby improving the debugging flexibility and compensation degree.
  • the data transmission start time of all data lines in each first sub-data line group is the same, so that it is easier to set up and simple to implement.
  • first sub-data line groups are arranged in a direction away from the gate driver in sequence; the source driving unit is configured as: among the multiple first sub-data line groups intersecting the same gate line, any first sub-data line group is used as a third reference data line group, and the data transmission start time of the third reference data line group is used as the reference time.
  • the third reference data line group is at the closest distance to the gate driver, the data transmission start time of the first sub-data line groups other than the third reference data line group among the plurality of first sub-data line groups is later than the reference time, so that the effective charging time of each sub-pixel formed by the data lines in the plurality of first sub-data line groups electrically connected to the source driving unit and the same gate line is the same; in the case where, among the plurality of first sub-data line groups intersecting the same gate line, the third reference data line group is at the farthest distance from the gate driver, the data transmission start time of the first sub-data line groups other than the third reference data line group among the plurality of first sub-data line groups is earlier than the reference time, so that the data lines in the plurality of first sub-data line groups electrically connected to the source driving unit and the same gate line are at the same effective charging time of each sub-pixel formed by the same gate line; The effective charging time of
  • the first data line groups Y1-120, Y121-240, Y241-360, Y361-480, Y600-481, Y720-601, Y840-721 and Y960-841 are arranged in a direction away from the gate driver 6 on the left side of the display panel 1, or the first data line groups Y960-841, Y840-721, Y720-601, Y600-481, Y361-480, Y241-360, Y121-240 and Y1-120 are arranged in a direction away from the gate driver 6 on the right side of the display panel 1, that is, the distance from Y1-120 to the gate driver 6 on the left side of the display panel 1 is the same as the distance from Y960-841 to the gate driver 6 on the right side of the display panel 1, and the same can be said for other first data line groups.
  • the first sub data line groups Y1 - 30 , Y31 - 60 , Y61 - 90 and Y91 - 120 are arranged in a direction away from the gate driver 6 on the left side of the display panel 1 in sequence.
  • the data transmission start time of the first sub-data line group Y31-60, Y61-90 and Y91-120 is later than the reference time, thereby ensuring that the data signals of the four first sub-data line groups are not transmitted to the sub-pixels of the display panel at the same time, specifically, the data signals of the first sub-data line groups Y31-60, Y61-90 and Y91-120 are delayed and transmitted to the sub-pixels in sequence.
  • the data transmission start time of the first sub-data line group Y1-30, Y31-60 and Y61-90 are all earlier than the reference time, thereby ensuring that the data signals of the four first sub-data line groups are not transmitted to the sub-pixels of the display panel at the same time, specifically, the data signals of the first sub-data line groups Y1-30, Y31-60 and Y61-90 are transmitted to the sub-pixels in advance in sequence.
  • the data transmission start time of the first sub-data line group Y1-30 is earlier than the reference time, thereby ensuring that the data signals of the four first sub-data line groups are not transmitted to the sub-pixels of the display panel at the same time, specifically, the data signals of the first sub-data line group Y1-30 are transmitted to the sub-pixels in advance; the data transmission start times of the first sub-data line groups Y61-90 and Y91-120 are both later than the reference time, thereby ensuring that the data signals of the four first sub-data line groups are not transmitted to the sub-pixels of the display panel at the same time, specifically, the data delays of the first sub-data line groups Y61-90 and Y91-120 are transmitted to the sub-pixels in advance.
  • the data transmission start time of the first sub-data line groups Y1-30 and Y31-60 are both earlier than the reference time, thereby ensuring that the data signals of the four first sub-data line groups are not transmitted to the sub-pixels of the display panel at the same time, specifically, the data signals of the first sub-data line groups Y1-30 and Y31-60 are transmitted to the sub-pixels in advance; the data transmission start time of the first sub-data line group Y91-120 is later than the reference time, thereby ensuring that the data signals of the four first sub-data line groups are not transmitted to the sub-pixels of the display panel at the same time, specifically, the data delay of the first sub-data line group Y91-120 is transmitted to the sub-pixels in advance.
  • all data lines intersecting the same gate line include M first data line groups, and the M first data line groups are arranged in a direction away from the gate driver; in a first mode, among the M first data line groups, the number of data lines in the first data line group of the Nth sequence is the same as the number of data lines in the first data line group of the M-N+1th sequence, and both are even numbers; wherein M is an even number greater than or equal to 2, and N is an integer greater than or equal to 1.
  • the first mode mentioned above is the V-Shift mode.
  • the 960 data lines include the first data line group Y1-120, Y121-240, Y241-360, Y361-480, Y600-481, Y720-601, Y840-721, and Y960-841
  • the number of data lines in the first data line group of the first sequence is the same as the number of data lines in the first data line group of the eighth sequence
  • the number of data lines in the first data line group of the second sequence is the same as the number of data lines in the first data line group of the seventh sequence
  • the number of data lines in the first data line group of the third sequence is the same as the number of data lines in the first data line group of the sixth sequence
  • the number of data lines in the first data line group of the fourth sequence is the same as the number of data lines in the first data line group of the fifth sequence, and all of them are 120.
  • the data transmission start time of each first data line group increases in sequence, so that it is easier to set up and simple to implement.
  • each first data line group includes an even number of first sub-data line groups; and the number of first sub-data line groups in each first data line group increases in sequence in a direction away from the gate driver, thereby making it easier to set up and simple to implement.
  • the data transmission start time of the first sub-data line groups in each first data line group increases in sequence by the same multiple, so that it is easier to set and simple to implement.
  • first sub-data line group Y1-120 and the first data line group Y960-841 30 data lines are used as a first sub-data line group.
  • the data transmission start time between each first sub-data line group is delayed by 8UI, and then multiplied by 1, that is, the delay between each first sub-data line group is 8UI.
  • the data transmission start time of the first data line group Y1-120 is delayed by 32UI in total, and the data transmission start time of the first data line group Y960-721 is delayed by 32UI in total.
  • first data line group Y121-240 and the first data line group Y840-721 20 data lines are used as a first sub-data line group, and the data transmission start time between each first sub-data line group is delayed by 6UI, and then multiplied by 2, that is, the delay between each first sub-data line group is 12UI. Then the data transmission start time of the first data line group Y121-240 is delayed by 72UI in total, and the data transmission start time of the first data line group Y840-721 is delayed by 72UI in total.
  • first data line group Y241-360 and the first data line group Y720-601 12 data lines are used as a first sub-data line group.
  • the data transmission start time between each first sub-data line group is delayed by 8UI, and then multiplied by 2, that is, the delay between each first sub-data line group is 16UI. Then the data transmission start time of the first data line group Y241-360 is delayed by 160UI in total, and the data transmission start time of the first data line group Y720-601 is delayed by 160UI in total.
  • first data line group Y361-480 and the first data line group Y600-481 6 data lines are used as a first sub-data line group.
  • the data transmission start time between each first sub-data line group is delayed by 6UI, and then multiplied by 3, that is, the delay between each first sub-data line group is 18UI.
  • the data transmission start time of the first data line group Y361-480 is delayed by 360UI in total
  • the data transmission start time of the first data line group Y600-481 is delayed by 360UI in total.
  • the display device provided in the embodiment of the present application adopts a multi-group adjustable solution when, for example, the V-Shift method is used for adjustment.
  • 960 data lines can be divided into 8 first data line groups, and the 120 data lines in each first data line group can be divided into 4 first sub-data line groups.
  • 6/12/20/30 lines can be selected as a group, so that the delay time of each 120 data lines can be adjusted to an uneven transition method.
  • the present application sets a delay time grouping within different channel ranges in a source driving unit, the delay time is adjustable, and Y1ch/Y960 is used as the starting point, so that the problem of a certain area being too dark or too bright caused by uneven impedance changes in some areas of the source driving unit, delays in gate signal transmission at the intersection of different data lines on the gate line, etc., can be well improved, thereby improving the debugging flexibility and compensation degree.
  • the source driver includes a plurality of source driving units.
  • the gate driver is configured to transmit a gate signal within a first preset time range to the gate line.
  • a plurality of data lines are divided into a plurality of groups, and each source driving unit is electrically connected to a group of data lines; among the plurality of source driving units, any one source driving unit is used as a reference source driving unit, and the remaining source driving units except the reference source driving unit are adjustment source driving units; among the plurality of groups of data lines intersecting with the same gate line, any one data line electrically connected to the reference source driving unit is used as a second reference data line, and the data transmission start time of the second reference data line is used as the reference time; among the data lines electrically connected to the reference source driving unit, the data line closest to the adjacent adjustment source driving unit is the first data line, and the data line closest to the reference source driving unit in the adjustment source driving unit is the second data line.
  • the data transmission start time of the first data line is later than the reference time, and the data transmission start time of the first data line is the same as the data transmission start time of the second data line, so that the effective charging time of each sub-pixel formed by the data lines in the plurality of groups of data lines electrically connected to the source driving unit and the same gate line is the same.
  • the source driver may include two source driving units; or, the source driver may include three or more source driving units.
  • the number of groups into which the above-mentioned multiple data lines are divided can be divided into two groups.
  • the above-mentioned multiple data lines can also be divided into three groups or more.
  • the number of groups into which the data lines are divided can be determined according to the number of source driving units.
  • FIG9 is a diagram showing a display device including two source driving units, namely COF1 and COF2, each of which includes 960 data lines.
  • COF1 is a reference source driving unit
  • COF2 is an adjustment source driving unit.
  • the first data line is Y960 in COF1
  • the second data line is Y1 in COF2.
  • the data transmission start time of the data lines Y2-960 in COF1 and the data lines Y1-960 in COF2 are both later than the reference time, and the data transmission start time of the data lines Y960 in COF1 is the same as the data line Y1 in COF2, and the data transmission start time of the data line Y2-960 in COF2 is later than the data transmission start time of the data line Y1 in COF2, thereby ensuring that the data signals of all data lines in COF1 and COF2 are not transmitted to the sub-pixels of the display panel at the same time.
  • the delay of the gate signal on the overall horizontal gate line of the large-size display panel results in better charging of pixels closer to the center of the display panel.
  • the Delay setting of the COF closer to the middle of the display panel often needs to be larger.
  • the Y1 and Y960 of two adjacent COFs may have a brightness difference due to the Delay setting, and the Delay between COFs cannot be effectively connected. Therefore, the charging difference of the display panel is also reflected in the source driver unit and the source driver unit, that is, between COFs.
  • an embodiment of the present application proposes a display device that can select one of Y1 or Y960 as a starting point ( Figure 9 takes 1ch in COF1 as the starting point), and the other channel is delayed relative to the starting point to complete the Delay matching between COF1 and COF2.
  • COF1 selects 1ch as the starting point output.
  • Y1-480 in COF1 has a total delay of 624UI
  • Y960-481 in COF1 has a total delay of 512UI (here the delay times of Y1-480 and Y960-481 in COF1 need to be different)
  • the starting output time of Y960 in COF1 is adjusted to Delay240UI relative to the output moment of Y1.
  • COF2 is Delay240UI relative to COF1
  • Y960 in COF1 and 1 in COF2 are output simultaneously, thereby effectively improving the problem that a bright and dark dividing line is easily formed at the junction of COF and COF, and the delay within and between COFs cannot be effectively connected.
  • the compensation setting method is more flexible and effective.
  • Delay time of Y1-480 and Y960-481 in the above COF1 depends on the Delay time set between COF1 and COF2.
  • all data lines electrically connected to the reference source driving unit are divided into a first part and a second part, the first part includes the second reference data line, and the data transmission delay time of all data lines in the first part is different from the data transmission delay time of all data lines in the second part.
  • FIG9 takes COF1 as the reference source driving unit, and the data line Y1-Y960 in FIG9 is divided into a first part Y1-480 and a second part Y960-481.
  • Y1-120 has a total delay of 32UI
  • Y121-240 has a total delay of 72UI
  • Y241-360 has a total delay of 160UI
  • Y361-480 has a total delay of 360UI
  • the first part Y1-480 has a total delay of 624UI
  • Y960-841 has a total delay of 24UI
  • Y840-721 has a total delay of 48UI
  • Y720-601 has a total delay of 120UI
  • Y600-481 has a total delay of 320UI
  • the second part Y960-481 has a total delay of 512UI.
  • the data transmission delay time of all data lines in the first part is greater than the data transmission delay time of all data lines in the second part, thereby making the control more convenient and easy to implement.
  • FIG9 takes COF1 as the reference source driving unit, and the data line Y1-Y960 in FIG9 is divided into a first part Y1-480 and a second part Y960-481.
  • Y1-120 has a total delay of 32UI
  • Y121-240 has a total delay of 72UI
  • Y241-360 has a total delay of 160UI
  • Y361-480 has a total delay of 360UI
  • the first part Y1-480 has a total delay of 624UI
  • Y960-841 has a total delay of 24UI
  • Y840-721 has a total delay of 48UI
  • Y720-601 has a total delay of 120UI
  • Y600-481 has a total delay of 320UI
  • the second part Y960-481 has a total delay of 512UI.
  • the first part Y1-480 and the second part Y960-481 differ by 112UI.
  • the source driving unit includes a data input module 101 , a multi-channel delay control module 102 , a digital-to-analog conversion module 103 , an output module 104 and a logic control module 105 .
  • the data input module 101 is electrically connected to the logic control module 105 and the multi-channel delay control module 102, and is configured to: receive and parse the video signal under the control of the first control signal of the logic control module 105 to obtain the first data of the video signal; and transmit the first data to the multi-channel delay control module 102.
  • the multi-channel delay control module 102 is electrically connected to the logic control module 105 and the digital-to-analog conversion module 103, and is configured to: receive and parse the first data under the control of the second control signal of the logic control module 105 to obtain the second data with different starting times for each data line; and transmit the second data to the digital-to-analog conversion module 103.
  • the digital-to-analog conversion module 103 is also electrically connected to the output module and is configured to: receive and convert the second data to obtain third data; and transmit 104 the third data to the output module.
  • the output module 104 is configured to receive and output third data.
  • the interface of the data input module 101 can be under the control of the first control signal of the logic control module 105, for example, receiving the video signal transmitted from the timing control 7 at the SOE_S moment, and the video signal can include the first data and the transmission protocol, etc.
  • the first data can be image data
  • the interface of the data input module 101 can be a CEDS/USIT interface.
  • the multi-channel delay control module 102 can receive the image data under the control of the second control signal of the logic control module 105, for example, in the GDE/PPCC mode, and process it.
  • the digital-to-analog conversion module 103 receives the processed image data and performs digital-to-analog conversion, for example, the analog voltage after the digital-to-analog conversion can be determined under the control of the gamma voltage GMA1-18.
  • the output module 104 receives the aforementioned analog voltage and outputs the image data to each data line at different times.
  • the logic control module 105 will output a synchronization signal to the multi-channel delay control module 102 and the output module 104 to control the analog signal output by the output module after digital-to-analog conversion to be synchronized with the digital signal processed by the multi-channel delay control module 102.
  • the embodiments of the present application provide a novel display device having a programmable charging compensation mode and a debugging method, which can improve the compensation flexibility and compensation degree, improve the V-Block problem to the greatest extent, and provide a good user experience.
  • the multi-channel delay control module includes a mode selection submodule 201 , a data selection submodule 202 , a first grouping control submodule 203 , a second grouping control submodule 204 and a delay submodule 205 .
  • the mode selection submodule 201 is electrically connected to the data selection submodule 202 and is configured to: receive the first data and select a delay mode under the control of the second control signal of the logic control module; and transmit the first data to the data selection submodule.
  • the data line selection submodule 202 is also electrically connected to the first group control unit 203 and is configured to: receive the first data under the control of the second control signal of the logic control module, determine the delay mode, and select the starting data line according to the delay mode; transmit the first data to the first group control submodule.
  • the first grouping control submodule 203 is also electrically connected to the second grouping control unit 204 and is configured to: receive the first data under the control of the second control signal of the logic control module, and determine the first data line group according to the start data line.
  • the second grouping control submodule 204 is also electrically connected to the delay unit 205 and is configured to receive the first data under the control of the second control signal of the logic control module and determine the first sub-data line group according to the first data line group.
  • the delay submodule 205 is configured to receive the first data under the control of the second control signal of the logic control module, and parse the first data according to the first sub-data line group to obtain second data with different start times for the data lines in the first sub-data line group.
  • the mode selection submodule 201 can receive image data under the control of the second control signal of the logic control module 105, for example, in the GDE/PPCC mode, and determine a mode, such as the V-shift mode; then, the data line selection submodule 202 receives the image data and determines the data line that first transmits the image data signal according to the V-shift mode; then, the first grouping control submodule 203 divides the data line into a plurality of first data line groups, for example, 960ch in a COF can be divided into eight groups, each with 120ch; then, the second grouping control submodule 204 divides each first data line group into a plurality of first sub-data line groups, for example, a group of 120ch can be divided into four first sub-data line groups; finally, the Delay time and the Delay time multiple between each first sub-data line group are set.

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Abstract

提供一种显示装置，显示装置包括显示面板（1），包括多条栅线（8）和多条数据线（9），栅线（8）与数据线（9）相交且绝缘设置；显示面板（1）还包括阵列排布的多个子像素（P），栅线（8）和数据线（9）限定出子像素（P）所在的区域；栅极驱动器（6），与显示面板（1）绑定且与显示面板（1）中的多条栅线（8）电连接；源极驱动器（2），与显示面板（1）绑定且与显示面板（1）中的多条数据线（9）电连接；源极驱动器（2）被配置为设定各数据线（9）的数据传输起始时刻，以使得多条数据线（9）与同一条栅线（8）形成的各子像素（P）的有效充电时间相同，从而改善V-Block问题。

Description

一种显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示装置。
背景技术
横向竖状区域亮度不均(V-Block)是大尺寸显示装置常见的不良，尤其在Dualgate(双栅)、高刷新率、8K分辨率等充电率较低的大尺寸显示装置上尤为明显。
目前解决上述问题的主要方式包括Fanout(扇出区)区电阻补偿、GDE(Gate Discharge Equilibrium，横向充电平衡)/PPCC(Programmable Panel Charging Compensation，可编程的面板充电补偿方式)补偿，然而目前的补偿方式均存在诸多问题，导致无法有效解决V-Block问题，用户体验差。
发明内容
本申请的实施例采用如下技术方案：
一方面，本申请的实施例提供了一种显示装置，包括：
显示面板，包括多条栅线和多条数据线，所述栅线与所述数据线相交且绝缘设置；所述显示面板还包括阵列排布的多个子像素，所述栅线和所述数据线限定出所述子像素所在的区域；
栅极驱动器，与所述显示面板中的所述多条栅线电连接；
源极驱动器，与所述显示面板绑定、且与所述显示面板中的所述多条数据线电连接；所述源极驱动器被配置为：设定各所述数据线的数据传输起始时刻，以使得多条所述数据线与同一条栅线形成的各子像素的有效充电时间相同。
可选地，所述源极驱动器包括源极驱动单元；
所述栅极驱动器被配置为：向所述栅线传输第一预设时间范围的栅极信号；
所述源极驱动单元被配置为：向多条所述数据线传输数据信号；其中，在与同一条栅线相交的多条数据线中，以任一条所述数据线为第一基准数据线，所述第一基准数据线的数据传输起始时刻为基准时刻；
在与同一条所述栅线相交的多条所述数据线中，所述栅线上与所述 第一基准数据线相交处的栅极信号最早传输的情况下，多条所述数据线中除所述第一基准数据线以外的数据线的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多条数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
在与同一条所述栅线相交的多条所述数据线中，所述栅线上与所述第一基准数据线相交处的栅极信号最晚传输的情况下，多条所述数据线中除所述第一基准数据线以外的数据线的数据传输起始时刻早于所述基准时刻，以使得和所述源极驱动单元电连接的所述多条数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
在与同一条所述栅线相交的多条所述数据线中，所述栅线上与所述第一基准数据线相交处的栅极信号处于中间传输的情况下，多条所述数据线中，比所述栅线上与所述第一基准数据线相交处的栅极信号早传输的数据线的数据传输起始时刻早于所述基准时刻；多条所述数据线中，比所述栅线上与所述第一基准数据线相交处的栅极信号晚传输的数据线的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多条数据线与同一条所述栅线形成的各子像素的有效充电时间相同。
可选地，所有所述数据线包括多个第一数据线组，各所述第一数据线组包括多条数据线；
所述源极驱动单元被配置为：在与同一条栅线相交的多个第一数据线组中，以任一个所述第一数据线组为第一基准数据线组，所述第一基准数据线组的数据传输起始时刻为基准时刻；
在与同一条所述栅线相交的多个所述第一数据线组中，所述栅线上与所述第一基准数据线组相交处的栅极信号最早传输的情况下，多个所述第一数据线组中除所述第一基准数据线组以外的第一数据线组的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
在与同一条所述栅线相交的多个所述第一数据线组中，所述栅线上与所述第一基准数据线组相交处的栅极信号最晚传输的情况下，多个所述第一数据线组中除所述第一基准数据线组以外的第一数据线组的数据传输起始时刻早于所述基准时刻，以使得和所述源极驱动单元电连接 的所述多个第一数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
在与同一条所述栅线相交的多个所述第一数据线组中，所述栅线上与所述第一基准数据线组相交处的栅极信号处于中间传输的情况下，多个所述第一数据线组中，比所述栅线与所述第一基准数据线组相交处的栅极信号早传输的第一数据线组的数据传输起始时刻早于所述基准时刻；多个所述第一数据线组中，比所述栅线与所述第一基准数据线组相交处的栅极信号晚传输的第一数据线组的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同。
可选地，所有所述数据线的数量与所有所述第一数据线组的数量的商值为整数、且各所述第一数据线组中的数据线的数量相同。
可选地，所述源极驱动单元被配置为：各所述第一数据线组中所有所述数据线包括多个第一子数据线组，所述第一子数据线组包括至少一条数据线；在与同一条栅线相交的多个第一子数据线组中，以任一个所述第一子数据线组为第二基准数据线组，所述第二基准数据线组的数据传输起始时刻为基准时刻；
在与同一条所述栅线相交的多个所述第一子数据线组中，所述栅线上与所述第二基准数据线组相交处的栅极信号最早传输的情况下，多个所述第一子数据线组中除所述第二基准数据线组以外的第一子数据线组的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一子数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
在与同一条所述栅线相交的多个所述第一子数据线组中，所述栅线上与所述第二基准数据线组相交处的栅极信号最晚传输的情况下，多个所述第一子数据线组中除所述第二基准数据线组以外的第一子数据线组的数据传输起始时刻早于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一子数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
在与同一条所述栅线相交的多个所述第一子数据线组中，所述栅线上与所述第二基准数据线组相交处的栅极信号处于中间传输的情况下，多个所述第一子数据线组中，比所述栅线与所述第二基准数据线组相交 处的栅极信号早传输的第一子数据线组的数据传输起始时刻早于所述基准时刻；多个所述第一子数据线组中，比所述栅线与所述第二基准数据线组相交处的栅极信号晚传输的第一子数据线组的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一子数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同。
可选地，各所述第一子数据线组中的所有所述数据线的数据传输起始时刻相同。
可选地，多个所述第一子数据线组沿依次远离所述栅极驱动器的方向排列；所述源极驱动单元被配置为：在与同一条栅线相交的多个所述第一子数据线组中，以任一个所述第一子数据线组为第三基准数据线组，所述第三基准数据线组的数据传输起始时刻为基准时刻；
在与同一条所述栅线相交的多个所述第一子数据线组中，所述第三基准数据线组处于与所述栅极驱动器距离最近的情况下，多个所述第一子数据线组中除所述第三基准数据线组以外的第一子数据线组的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一子数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
在与同一条所述栅线相交的多个所述第一子数据线组中，所述第三基准数据线组处于与所述栅极驱动器距离最远的情况下，多个所述第一子数据线组中除所述第三基准数据线组以外的第一子数据线组的数据传输起始时刻早于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一子数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
在与同一条所述栅线相交的多个所述第一子数据线组中，所述第三基准数据线组处于与所述栅极驱动器距离中间的情况下，多个所述第一子数据线组中，比所述第三基准数据线组与所述源极驱动器的距离近的第一子数据线组的数据传输起始时刻早于所述基准时刻，比所述第三基准数据线组与所述源极驱动器的距离远的第一子数据线组的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一子数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同。
可选地，与同一条所述栅线相交的所有所述数据线包括M个第一数据线组，M个所述第一数据线组沿依次远离所述栅极驱动器的方向排序；
在第一模式下，M个所述第一数据线组中，第N序列的第一数据线组中的数量线的数量与第M-N+1序列的第一数据线组中的数量线的数量相同、且均为偶数；其中，M为大于或等于2的偶数，N为大于或等于1的整数。
可选地，沿远离所述栅极驱动器的方向，各所述第一数据线组的数据传输起始时刻依次递增。
可选地，在与同一条所述栅线相交的多个所述第一数据线组中，各所述第一数据线组包括偶数个第一子数据线组；
沿远离所述栅极驱动器的方向，各所述第一数据线组中的所述第一子数据线组的数量依次递增。
可选地，沿远离所述栅极驱动器的方向，各所述第一数据线组中的所述第一子数据线组的数据传输起始时刻以相同倍数依次递增。
可选地，所述源极驱动器包括多个源极驱动单元；
所述栅极驱动器被配置为：向所述栅线传输第一预设时间范围的栅极信号；
所述多条数据线分为多组，各所述源极驱动单元电连接一组数据线；多个所述源极驱动单元中，以任一个所述源极驱动单元为基准源极驱动单元，除所述基准源极驱动单元以外的其余源极驱动单元为调节源极驱动单元；在与同一条栅线相交的多组数据线中，以与所述基准源极驱动单元电连接的任一条所述数据线为第二基准数据线，所述第二基准数据线的数据传输起始时刻为基准时刻；所述基准源极驱动单元电连接的数据线中与相邻调节源极驱动单元距离最近的数据线为第一数据线，所述调节源极驱动单元中与所述基准源极驱动单元距离最近的数据线为第二数据线；
在与同一条栅线相交的多组数据线中，所述栅线上与所述第二基准数据线相交处的栅极信号最早传输的情况下，所述第一数据线的数据传输起始时刻迟于所述基准时刻、且所述第一数据线的数据传输起始时刻与所述第二数据线的数据传输起始时刻相同，以使得和所述源极驱动单元电连接的多组数据线组中的数据线与同一条所述栅线形成的各子像 素的有效充电时间相同。
可选地，与所述基准源极驱动单元电连接的所有所述数据线分为第一部分和第二部分，所述第一部分包括所述第二基准数据线，所述第一部分中的所有数据线的数据传输延迟时间与所述第二部分中的所有数据线的数据传输延迟时间不同。
可选地，在第一模式下，所述第一部分中的所有数据线的数据传输延迟时间大于所述第二部分中的所有数据线的数据传输延迟时间。
可选地，所述源极驱动单元包括数据输入模块、多通道延迟控制模块、数模转换模块、输出模块和逻辑控制模块；
所述数据输入模块与所述逻辑控制模块和所述多通道延迟控制模块均电连接、且被配置为：在所述逻辑控制模块的第一控制信号的控制下，接收并解析视频信号，得到所述视频信号的第一数据；向所述多通道延迟控制模块传输所述第一数据；
所述多通道延迟控制模块与所述逻辑控制模块和所述数模转换模块均电连接、且被配置为：在所述逻辑控制模块的第二控制信号的控制下，接收并解析所述第一数据，得到各数据线的具有不同起始时刻的第二数据；向所述数模转换模块传输所述第二数据；
所述数模转换模块还与所述输出模块电连接、且被配置为：接收并转换所述第二数据，得到第三数据；向所述输出模块传输所述第三数据；
所述输出模块被配置为：接收并输出所述第三数据。
可选地，所述多通道延迟控制模块包括方式选择子模块、数据选择子模块、第一分组控制子模块、第二分组控制子模块和延迟子模块；
所述方式选择子模块与所述数据选择子模块电连接、且被配置为：在所述逻辑控制模块的所述第二控制信号的控制下，接收所述第一数据，并选择一种延迟模式；向所述数据选择子模块传输所述第一数据；
所述数据线选择子模块还与所述第一分组控制单元电连接、且被配置为：在所述逻辑控制模块的所述第二控制信号的控制下，接收所述第一数据，并确定所述延迟模式，根据所述延迟模式选择起始数据线；向所述第一分组控制子模块传输所述第一数据；
所述第一分组控制子模块还与所述第二分组控制单元电连接、且被配置为：在所述逻辑控制模块的所述第二控制信号的控制下，接收所述第一数据，并根据所述起始数据线确定第一数据线组；
所述第二分组控制子模块还与所述延迟单元电连接、且被配置为：在所述逻辑控制模块的所述第二控制信号的控制下，接收所述第一数据，并根据所述第一数据线组确定第一子数据线组；
所述延迟子模块被配置为：在所述逻辑控制模块的所述第二控制信号的控制下，接收所述第一数据，并根据所述第一子数据线组解析第一数据，得到第一子数据线组中数据线的具有不同起始时刻的第二数据。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本申请实施例提供的一种相关技术的显示面板出现V-Block问题的示意图；
图2为本申请实施例提供的一种显示装置的结构示意图；
图3为本申请实施例提供的一种相关技术中的一种显示装置的结构示意图；
图4为本申请实施例提供的一种USI-T协议示意图；
图5为本申请实施例提供的另一种相关技术的显示面板出现V-Block问题的示意图；
图6为本申请实施例提供的一种一个源极驱动单元内的数据线的延迟时间示意图；
图7为本申请实施例提供的另一种显示装置的结构示意图；
图8为本申请实施例提供的一种相关技术中的一个源极驱动单元内的数据线的延迟时间示意图；
图9为本申请实施例提供的一种相邻源极驱动单元间的数据线的延迟时间示意图；
图10为本申请实施例提供的一种相关技术中的相邻源极驱动单元间的数据线的延迟时间示意图；
图11为本申请实施例提供的一种源极驱动单元的结构示意图；
图12为本申请实施例提供的一种多通道控制延迟模块的结构示意图。
具体实施例
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的实施例中，除非另有说明，“多个”的含义是两个或两个以上；术语“上”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的结构或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”、“特定示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在本申请的实施例中，采用“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分，仅为了清楚描述本申请实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
随着科技的发展，Dualgate、高分辨率(例如8K分辨率)、高刷新率(例如240Hz)的显示装置受到越来越多的喜爱。V-Block是大尺寸显示装 置常见的不良，尤其在Dualgate、高刷新率、8K分辨率等充电率较低的大尺寸显示装置上尤为明显。以8K分辨率大尺寸显示装置为例，一行像素的开启时间较短，又由于源极驱动IC(Integrated Circuit，集成电路)输出的每一行Data(数据)信号都在跳变，像素没有预充电，导致实际有效的像素充电时间更少，且随着显示装置分辨率增大，单位面积内要驱动的像素更多，从而导致显示装置无法有效充电，容易出现如图1所示的由于充电时间短而导致部分画面充电不足的V-Block问题。
相关技术中，Fanout电阻补偿为预先设计源极驱动IC的Fanout补偿，即通过设计不同通道(即Data线)在源极驱动IC上的走线，使得不同Data线间的阻抗差异与显示装置中显示面板的阻抗差异匹配，从而达到补偿充电的目的，该方法的弊端主要有：Data线的布线一旦做好就无法调整、显示面板匹配性单一、无法共用资材、补偿与显示面板匹配度不稳定等。当前的GDE/PPCC补偿为通过控制源极驱动IC来改善V-Block，该方法的弊端主要有：补偿设定方式单一、无法补偿Data线间的不均匀差异等。
本申请的实施例提供了一种显示装置，参考图2所示，包括：
显示面板1，包括多条栅线8和多条数据线9，栅线8与数据线9相交且绝缘设置；显示面板1还包括阵列排布的多个子像素P，栅线8和数据线9限定出子像素P所在的区域。
栅极驱动器6，与显示面板1中的多条栅线8电连接。
源极驱动器2，与显示面板1绑定、且与显示面板1中的多条数据线9电连接；源极驱动器2被配置为：设定各数据线9的数据传输起始时刻，以使得多条数据线9与同一条栅线8形成的各子像素P的有效充电时间相同。
这里对于上述显示面板的类型不做具体限定，其可以是LCD(Liquid Crystal Display，液晶显示面板)，还可以是OLED(Organic Light Emitting Diode,有机发光二极管)显示面板。
这里对于上述栅线和数据线的数量关系不做具体限定，示例的，栅线和数据线的数量可以相同；或者，栅线和数据线的数量可以不同。栅线和数据线的实际数量可以根据子像素的数量、显示面板的面积等确定。图2以显示面板包括三条栅线8和四条数据线9为例进行绘示，此时栅线8和数据线9的数量不同。需要说明的是，实际产品例如对于大尺寸产品，栅线和数据线的数量很多，图2未能示出全部的栅线和数据线。
这里对于上述子像素的数量不做具体限定。示例的，上述子像素的数量 可以为一个；或者，上述子像素的数量可以为多个。子像素的数量可以根据栅线和数据线的数量确定。图2以显示面板包括十二个子像素P为例进行绘示。
这里对于上述子像素的颜色不做具体限定。在显示面板包括多个子像素的情况下，上述子像素的颜色可以全部相同；或者，上述子像素的颜色可以部分相同；或者，上述子像素的颜色可以均不同。示例的，显示面板可以包括红色子像素、绿色子像素和蓝色子像素。
对于上述栅极驱动器和显示面板的具体位置关系不做限定，示例的，栅极驱动器6可以如图2所示，设置在显示面板1的一侧；或者，栅极驱动器还可以围绕显示面板设置；当然，还可以是其它设置方式，这里不再一一列举，具体可以根据实际要求确定。
上述栅极驱动器的数量不做具体限定，示例的，栅极驱动器6可以如图2所示，设置为单个；当然也可以设置为多个。
上述栅极驱动器的类型不做具体限定，示例的，栅极驱动器可以为GOA(Gate Driver On Array，阵列基板行驱动)电路。
对于上述源极驱动器和显示面板的具体位置关系不做限定，示例的，源极驱动器2可以如图2所示，设置在显示面板1的一侧、且与显示面板1的一侧绑定；或者，源极驱动器还可以围绕显示面板设置、与显示面板的周侧均绑定；当然，还可以是其它设置方式，这里不再一一列举，具体可以根据实际要求确定。
上述源极驱动器的数量不做具体限定，示例的，源极驱动器2可以如图2所示，设置为单个；当然也可以设置为多个。
上述源极驱动器与数据线电连接的具体方式不做限定，示例的，上述源极驱动器可以与数据线直接电连接；或者，上述源极驱动器可以与数据线通过其它结构电连接。
上述源极驱动器的类型不做具体限定，示例的，源极驱动器可以为COF(Chip On Film，覆晶薄膜)。
上述对于显示面板与源极驱动器绑定的具体方式不做限定，示例的，显示面板与源极驱动器可以直接绑定；或者，显示面板可以通过FPC(Flexible Printed Circuit，柔性电路板)与源极驱动器绑定。
上述各数据线的数据传输起始时刻为各数据线接收的图像数据信号传输的起始时刻，图像数据信号的传输过程如图3所示。
参考图3所示，前端系统(图3中未示出)与时序控制单元3的接口11电连接，时序控制单元3通过接口12与柔性电路板4电连接，柔性电路板4通过接口13与印刷电路板5电连接，印刷电路板5与驱动芯片21-驱动芯片32均电连接，驱动芯片21-驱动芯片32设置在显示面板1的一侧、且与显示面板1的一侧绑定。图3以驱动芯片21-驱动芯片32从显示面板1的左侧向右侧依次排布十二列为例进行绘示。
参考图3所示，前端系统通过接口11向时序控制单元3传输图像数据信号，时序控制单元3接收图像数据信号、并通过接口12向柔性电路板4传输图像数据信号，柔性电路板4接收图像数据信号、并通过接口13向印刷电路板5传输图像数据信号，印刷电路板5向驱动芯片21-驱动芯片32分别传输图像数据信号，驱动芯片21-驱动芯片32向显示面板1传输图像数据信号，用于显示。
上述图像数据信号可以按照如图4所示的USI-T(Unified Standard Interface，通用串行接口)协议进行传输。参考图4所示，USI-T协议包括Frame Configureration Data(帧配置数据)，Frame Configureration Data中的AD表示标志位，D0-D8表示数据线0-8，N/A表示不用的寄存器，PPCC_M[0]、PPCC_M[1]、和PPCC_B[0]和PPCC_B[1]均为用于设定图像数据信号传输起始时刻延迟或提前的倍数的寄存器，PPCC_SHIFT[0]和PPCC_SHIFT[1]为用于通过不同模式调整数据线的数据传输起始时刻的寄存器，其中[0]代表低电平、[1]代表高电平，Reserved代表保留位，该保留位可以被任一寄存器使用。
需要说明的是，上述图像数据信号也可以按照CEDS(Clock Embedded Differential Singaling，时钟嵌入数据)协议进行传输，可以根据相关技术获得，这里不再赘述。
图1是显示装置未开启充电补偿的画面，从图1可以看到相当严重的V-Block分屏现象，在每个源极驱动IC内呈现的规律为：显示面板两侧较暗、中间较亮，且为不均匀亮度过渡，越靠近显示面板中央整体的亮度越亮。图5是在相关技术中可调范围内开启的较优补偿方式的画面，从图5可以看到，补偿后的显示面板的中间区域略有改善，而两侧仍留有一块明显的黑色Block、仍存在明显的竖状暗条纹等问题。
由于栅线上远离栅极驱动器的部分上的信号的有效充电时间小于栅线上靠近栅极驱动器的部分上的信号的有效充电时间，这样当通过源极驱动器向数据线输入数据信号时，该数据信号与栅线上靠近栅极驱动器的部分上的 信号的有效充电面积大于该数据信号与栅线上远离栅极驱动器的部分上的信号的有效充电面积，从而导致栅线上远离栅极驱动器的部分对应的子像素的充电时间比栅线上靠近栅极驱动器的部分对应的子像素的充电时间短，充电效果差异较大，导致出现V-Block现象。本申请实施例提供的显示装置中，对于与同一条栅线相交的多条数据线而言，源极驱动器被配置为设定各数据线的数据传输起始时刻，即可以通过设定各数据线的数据传输起始时刻不同，例如可以设定与栅极驱动器距离较近的数据线的数据传输起始时刻早于与栅极驱动器距离较远的数据线的数据传输起始时刻，与栅极驱动器距离较远的数据线的数据传输起始时刻迟于与栅极驱动器距离较近的数据线的数据传输起始时刻。又由于各数据线与该栅线限定出不同的子像素，那么与栅极驱动器距离较近的数据线的数据可以早于与栅极驱动器距离较远的数据线的数据传输至各自对应的子像素，与栅极驱动器距离较远的数据线的数据可以迟于与栅极驱动器距离较近的数据线的数据传输至各自对应的子像素，从而使得多条数据线与同一条栅线形成的各子像素的有效充电时间相同，以提高显示效果，用户体验佳。
可选地，源极驱动器包括源极驱动单元。
栅极驱动器被配置为：向栅线传输第一预设时间范围的栅极信号。
源极驱动单元被配置为：向多条数据线传输数据信号；其中，在与同一条栅线相交的多条数据线中，以任一条数据线为第一基准数据线，第一基准数据线的数据传输起始时刻为基准时刻；在与同一条栅线相交的多条数据线中，栅线上与第一基准数据线相交处的栅极信号最早传输的情况下，多条数据线中除第一基准数据线以外的数据线的数据传输起始时刻迟于基准时刻，以使得和源极驱动单元电连接的多条数据线与同一条栅线形成的各子像素的有效充电时间相同；在与同一条栅线相交的多条数据线中，栅线上与第一基准数据线相交处的栅极信号最晚传输的情况下，多条数据线中除第一基准数据线以外的数据线的数据传输起始时刻早于基准时刻，以使得和源极驱动单元电连接的多条数据线与同一条栅线形成的各子像素的有效充电时间相同；在与同一条栅线相交的多条数据线中，栅线上与第一基准数据线相交处的栅极信号处于中间传输的情况下，多条数据线中，比栅线上与第一基准数据线相交处的栅极信号早传输的数据线的数据传输起始时刻早于基准时刻；多条数据线中，比栅线上与第一基准数据线相交处的栅极信号晚传输的数据线的数据传输起始时刻迟于基准时刻，以使得和源极驱动单元电连接的多条 数据线与同一条栅线形成的各子像素的有效充电时间相同。
图2以源极驱动器2包括一个源极驱动单元、且源极驱动单元位于显示面板1左端为例进行绘示。对于位于显示面板其它位置的源极驱动单元均可以以此为例，这里不再赘述。
这里对于上述源极驱动单元的类型不做具体限定。示例的，源极驱动单元可以包括源极驱动芯片，该源极驱动芯片可以为COF。
图2以栅极驱动器6连接三条栅线81、82和83，且源极驱动单元连接四条数据线91、92、93和94为例进行绘示，其中，栅线上与数据线91相交处的栅极信号最早传输，栅线上与数据线94相交处的栅极信号最晚传输，栅线上与数据线92和93相交处的栅极信号迟于栅线上与数据线91相交处的栅极信号传输、且早于栅线上与数据线94相交处的栅极信号传输。该栅极驱动器被配置为：向栅线81、栅线82和栅线83传输第一预设时间范围的栅极信号；该源极驱动单元被配置为：向数据线91、92、93和94传输数据信号。
需要说明的是，上述栅极信号被配置为能够控制各子像素开启。上述第一预设时间范围为栅极信号在栅线上传输的持续时间范围，对于上述第一预设时间范围不做具体限定，该第一预设时间范围可以根据刷新频率等确定，例如第一预设时间范围可以为微秒级别。
下面以与栅线81相交的数据线91、92、93和94为例进行说明，与栅线82、83相交的数据线91、92、93和94的数据传输与此类似，这里不再赘述。
在数据线91、92、93和94中，第一基准数据线为数据线91、且其数据传输起始时刻为基准时刻的情况下，由于栅线81上与数据线92、93和94相交处的栅极信号均迟于栅线81上与数据线91相交处的栅极信号传输，那么数据线92、93和94的数据传输起始时刻均迟于基准时刻，从而保证数据线91、92、93和94的数据信号不同时传输至显示面板的子像素，具体为数据线91、92、93和94的数据信号依次延迟传输至子像素P1、P2、P3和P4。
在数据线91、92、93和94中，第一基准数据线为数据线94、且其数据传输起始时刻为基准时刻的情况下，由于栅线81上与数据线91、92和93相交处的栅极信号均早于栅线81上与数据线94相交处的栅极信号传输，那么数据线91、92和93的数据传输起始时刻均早于基准时刻，从而保证数据线91、92、93和94的数据信号不同时传输至显示面板的子像素，具体为数 据线91、92、93和94的数据信号依次提前传输至子像素P1、P2、P3和P4。
在数据线91、92、93和94中，第一基准数据线为数据线92、且其数据传输起始时刻为基准时刻的情况下，由于栅线81上与数据线91相交处的栅极信号早于栅线81上与数据线92相交处的栅极信号传输，那么数据线91的数据传输起始时刻早于基准时刻；由于栅线81上与数据线93和94相交处的栅极信号迟于栅线81上与数据线92相交处的栅极信号传输，那么数据线93和94的数据传输起始时刻迟于基准时刻，从而保证数据线91、92、93和94的数据信号不同时传输至显示面板的子像素，具体为数据线91的数据信号提前传输至子像素P1、再是数据线92的数据信号传输至子像素P2、然后是数据线93的数据信号延迟传输至子像素P3、最后是数据线94的数据信号延迟传输至子像素P4。其中，数据线94的数据信号较数据线93的数据信号延迟传输至子像素。
在数据线91、92、93和94中，第一基准数据线为数据线93、且其数据传输起始时刻为基准时刻的情况下，由于栅线81上与数据线91和92相交处的栅极信号早于栅线81上与数据线91和92相交处的栅极信号传输，那么数据线91和92的数据传输起始时刻早于基准时刻；由于栅线81上与数据线94相交处的栅极信号迟于栅线81上与数据线94相交处的栅极信号传输，那么数据线94的数据传输起始时刻迟于基准时刻从而保证数据线91、92、93和94的数据信号不同时传输至显示面板的子像素，具体为数据线91的数据信号提前传输至子像素P1、再是数据线92的数据信号提前传输至子像素P2、然后是第一数据线93的数据信号传输至子像素P3、最后是数据线94的数据信号延迟传输至子像素P4。其中，数据线91的数据信号较数据线92的数据信号提前传输至子像素。
对于上述数据传输起始时刻早于基准时刻，或者数据传输起始时刻迟于基准时刻都不做具体限定，示例的，数据传输起始时刻可以早于基准时刻2UI(Unit Delay，单位延迟)，数据传输起始时刻可以迟于基准时刻-4UI。
需要说明的是，对于任意条数的数据线和栅线均可以以此为例类推，这里不再赘述。
上述数据传输起始时刻可以通过GDE/PPCC补偿实现。
上述数据传输起始时刻可以有三种模式，即第一模式(V-Shift模式)、第二模式(L-Shift模式)和第三模式(R-Shift模式)。以图2所示的数据线91、92、93和94为例说明三种模式。具体的，在V-Shift模式下，图2 所示的数据线91和数据线94的数据传输起始时刻相同，数据线92和数据线93的数据传输起始时刻相同。在L-Shift模式下，图2所示的数据线91、92、93和94的数据传输起始时刻依次递增。在R-Shift模式下，图2所示的数据线94、93、92和91的数据传输起始时刻依次递增。其它数量的数据线均可以以此类推，这里不再赘述。
上述数据传输起始时刻可以早于基准时刻的单位延迟时间和倍数可以为任意值，例如1UI、2UI、3UI等等。考虑到实际应用，进一步可选地，上述数据传输起始时刻可以早于基准时刻2UI、4UI、6UI、8UI，同时还可以分别与延迟倍数1、2、3、4相乘，例如8UI与延迟倍数1、2、3、4相乘后可以得到8UI、16UI、24UI、32UI。
本申请的实施例提供的显示装置中，通过设置一个源极驱动单元内不同数据线的数据传输起始时刻可调，从而可以很好的改善由于源极驱动单元内部分区域阻抗变化不均匀、栅线上与不同数据线相交处的栅极信号传输延迟等引起的V-Block问题，提高调试灵活性与补偿程度。
可选地，所有数据线包括多个第一数据线组，各第一数据线组包括多条数据线。
源极驱动单元被配置为：在与同一条栅线相交的多个第一数据线组中，以任一个第一数据线组为第一基准数据线组，第一基准数据线组的数据传输起始时刻为基准时刻。
在与同一条栅线相交的多个第一数据线组中，栅线上与第一基准数据线组相交处的栅极信号最早传输的情况下，多个第一数据线组中除第一基准数据线组以外的第一数据线组的数据传输起始时刻迟于基准时刻，以使得和源极驱动单元电连接的多个第一数据线组中的数据线与同一条栅线形成的各子像素的有效充电时间相同；在与同一条栅线相交的多个第一数据线组中，栅线上与第一基准数据线组相交处的栅极信号最晚传输的情况下，多个第一数据线组中除第一基准数据线组以外的第一数据线组的数据传输起始时刻早于基准时刻，以使得和源极驱动单元电连接的多个第一数据线组中的数据线与同一条栅线形成的各子像素的有效充电时间相同；在与同一条栅线相交的多个第一数据线组中，栅线上与第一基准数据线组相交处的栅极信号处于中间传输的情况下，多个第一数据线组中，比栅线与第一基准数据线组相交处的栅极信号早传输的第一数据线组的数据传输起始时刻早于基准时刻；多个第一数据线组中，比栅线与第一基准数据线组相交处的栅极信号晚传输的 第一数据线组的数据传输起始时刻迟于基准时刻，以使得和源极驱动单元电连接的多个第一数据线组中的数据线与同一条栅线形成的各子像素的有效充电时间相同。
图6以显示装置包括960条数据线为例进行说明，其中，图6的横坐标为数据线，纵坐标为输出延迟时间、单位是UI。参考图6所示，960条数据线分为八个第一数据线组，各第一数据线组包括120条数据线。具体的，960条数据线包括Y1-120构成的第一数据线组、Y121-240构成的第一数据线组、Y241-360构成的第一数据线组、Y361-480构成的第一数据线组、Y600-481构成的第一数据线组、Y720-601构成的第一数据线组、Y840-721构成的第一数据线组、Y960-841构成的第一数据线组。
在第一数据线组Y1-120、Y121-240、Y241-360、Y361-480、Y600-481、Y720-601、Y840-721和Y960-841中，第一基准数据线组为第一数据线组Y1-120和Y960-841、且数据传输起始时刻为基准时刻的情况下，第一数据线组Y121-240、Y241-360、Y361-480、Y600-481、Y720-601和Y840-721数据传输起始时刻均迟于基准时刻，从而保证八个第一数据线组的数据信号不同时传输至显示面板的子像素，具体为第一数据线组Y1-120和Y960-841的数据信号传输至子像素、再是第一数据线组Y121-240、Y241-360、Y361-480、Y600-481、Y720-601和Y840-721的数据信号延迟传输至子像素。其中，在其它六个第一数据线组中，第一数据线组Y121-240和Y840-721的数据信号传输至子像素、接着是Y241-360和Y720-601的数据信号传输至子像素、最后是Y361-480和Y600-481的数据信号传输至子像素。
在第一数据线组Y1-120、Y121-240、Y241-360、Y361-480、Y600-481、Y720-601、Y840-721和Y960-841中，第一基准数据线组为第一数据线组Y361-480和Y600-481、且数据传输起始时刻为基准时刻的情况下，第一数据线组Y1-120、Y121-240、Y241-360、Y720-601、Y840-721和Y960-841的数据传输起始时刻均早于基准时刻，从而保证八个第一数据线组的数据信号不同时传输至显示面板的子像素，具体为第一数据线组Y1-120、Y121-240、Y241-360、Y720-601、Y840-721和Y960-841的数据信号提前传输至子像素、再是第一数据线组Y361-480和Y600-481的数据信号传输至子像素。其中，在其它六个第一数据线组中，先是Y1-120和Y960-841的数据信号传输至子像素、然后是第一数据线组Y121-240和Y840-721的数据信号传输至子像素、最后是Y241-360和Y720-601的数据信号传输至子像素。
在第一数据线组Y1-120、Y121-240、Y241-360、Y361-480、Y600-481、Y720-601、Y840-721和Y960-841中，第一基准数据线组为第一数据线组Y121-240和Y840-721、且数据传输起始时刻为基准时刻的情况下，第一数据线组Y1-120和Y960-841的数据传输起始时刻均早于基准时刻，从而保证第一数据线组Y1-120和Y960-841的数据信号提前传输至显示面板的子像素；第一数据线组Y241-360、Y361-480、Y600-481和Y720-601的数据传输起始时刻均迟于基准时刻，从而保证第一数据线组Y241-360、Y361-480、Y600-481和Y720-601的数据信号延迟传输至显示面板的子像素。
在第一数据线组Y1-120、Y121-240、Y241-360、Y361-480、Y600-481、Y720-601、Y840-721和Y960-841中，第一基准数据线组为第一数据线组Y241-360和Y720-601、且数据传输起始时刻为基准时刻的情况下，第一数据线组Y1-120、Y241-360、Y840-721和Y960-841的数据传输起始时刻均早于基准时刻，从而保证第一数据线组Y1-120、Y241-360、Y840-721和Y960-841的数据信号提前传输至显示面板的子像素；第一数据线组Y361-480和Y600-481的数据传输起始时刻均迟于基准时刻，从而保证第一数据线组Y361-480和Y600-481的数据信号延迟传输至显示面板的子像素。
需要说明的是，图6中的ch代表通道(即数据线)。
本申请的实施例提供的显示装置中，通过将一个源极驱动单元内的所有数据线分为多个第一数据线组，并设置多个第一数据线组的数据传输起始时刻可调，从而可以很好的改善由于源极驱动单元内部分区域阻抗变化不均匀、栅线上与不同数据线相交处的栅极信号传输延迟等引起的V-Block问题，提高调试灵活性与补偿程度。
可选地，所有数据线的数量与所有第一数据线组的数量的商值为整数、且各第一数据线组中的数据线的数量相同。从而更有利于实际应用。
对于上述所有数据线的数量、所有第一数据线组的数量均不做具体限定，示例的，上述所有数据线的数量可以为960条、所有第一数据线组的数量可以为8组，从而使得所有数据线的数量与所有第一数据线组的数量的商值为120，即各第一数据线组中的数据线的数量均为120条。其它所有数据线的数量、所有第一数据线组的数量均可以依次类推，这里不再赘述。
当然，也可以设置各第一数据线组中的数据线的数量不同，这里不做具体限定。
可选地，源极驱动单元被配置为：各第一数据线组中所有数据线包括多 个第一子数据线组，第一子数据线组包括至少一条数据线；在与同一条栅线相交的多个第一子数据线组中，以任一个第一子数据线组为第二基准数据线组，第二基准数据线组的数据传输起始时刻为基准时刻。
在与同一条栅线相交的多个第一子数据线组中，栅线上与第二基准数据线组相交处的栅极信号最早传输的情况下，多个第一子数据线组中除第二基准数据线组以外的第一子数据线组的数据传输起始时刻迟于基准时刻，以使得和源极驱动单元电连接的多个第一子数据线组中的数据线与同一条栅线形成的各子像素的有效充电时间相同；在与同一条栅线相交的多个第一子数据线组中，栅线上与第二基准数据线组相交处的栅极信号最晚传输的情况下，多个第一子数据线组中除第二基准数据线组以外的第一子数据线组的数据传输起始时刻早于基准时刻，以使得和源极驱动单元电连接的多个第一子数据线组中的数据线与同一条栅线形成的各子像素的有效充电时间相同；在与同一条栅线相交的多个第一子数据线组中，栅线上与第二基准数据线组相交处的栅极信号处于中间传输的情况下，多个第一子数据线组中，比栅线与第二基准数据线组相交处的栅极信号早传输的第一子数据线组的数据传输起始时刻早于基准时刻；多个第一子数据线组中，比栅线与第二基准数据线组相交处的栅极信号晚传输的第一子数据线组的数据传输起始时刻迟于基准时刻，以使得和源极驱动单元电连接的多个第一子数据线组中的数据线与同一条栅线形成的各子像素的有效充电时间相同。
上述各第一数据线组中所有数据线包括的第一子数据线组的数量不做具体限定，示例的，上述各第一数据线组中所有数据线包括的第一子数据线组的数量可以为两个、三个、四个等等。进一步可选地，第一子数据线组的数量能够被各第一数据线组中所有数据线的数量整除。
上述第一子数据线组包括的数据线的数量不做具体限定，示例的，上述第一子数据线组包括的数据线的数量可以为一条、两条、三条等等。
以图6所示的显示装置包括960条数据线，960条数据线分为八个第一数据线组，具体为第一数据线组Y1-120、Y121-240、Y241-360、Y361-480、Y600-481、Y720-601、Y840-721和Y960-841为例进行说明。
示例的，在第一数据线组Y1-120的120可以分为四个第一子数据线组，即各第一子数据线组包括30条数据线，即第一数据线组Y1-120包括第一子数据线组Y1-30、Y31-60、Y61-90和Y91-120。
在第一子数据线组Y1-30、Y31-60、Y61-90和Y91-120中，第二基准数 据线组为第一子数据线组Y1-30、且数据传输起始时刻为基准时刻的情况下，第一子数据线组Y31-60、Y61-90和Y91-120的数据传输起始时刻均迟于基准时刻，从而保证四个第一子数据线组的数据信号不同时传输至显示面板的子像素，具体为第一子数据线组Y31-60、Y61-90和Y91-120的数据信号依次延迟传输至子像素。
在第一子数据线组Y1-30、Y31-60、Y61-90和Y91-120中，第二基准数据线组为第一子数据线组Y91-120、且数据传输起始时刻为基准时刻的情况下，第一子数据线组Y1-30、Y31-60和Y61-90的数据传输起始时刻均早于基准时刻，从而保证四个第一子数据线组的数据信号不同时传输至显示面板的子像素，具体为第一子数据线组Y1-30、Y31-60和Y61-90的数据信号依次提前传输至子像素。
在第一子数据线组Y1-30、Y31-60、Y61-90和Y91-120中，第二基准数据线组为第一子数据线组Y31-60、且数据传输起始时刻为基准时刻的情况下，第一子数据线组Y1-30的数据传输起始时刻均早于基准时刻，从而保证四个第一子数据线组的数据信号不同时传输至显示面板的子像素，具体为第一子数据线组Y1-30的数据信号提前传输至子像素；第一子数据线组Y61-90和Y91-120的数据传输起始时刻均迟于基准时刻，从而保证四个第一子数据线组的数据信号不同时传输至显示面板的子像素，具体为第一子数据线组Y61-90和Y91-120的数据延迟提前传输至子像素。
在第一子数据线组Y1-30、Y31-60、Y61-90和Y91-120中，第二基准数据线组为第一子数据线组Y61-90、且数据传输起始时刻为基准时刻的情况下，第一子数据线组Y1-30和Y31-60的数据传输起始时刻均早于基准时刻，从而保证四个第一子数据线组的数据信号不同时传输至显示面板的子像素，具体为第一子数据线组Y1-30和Y31-60的数据信号提前传输至子像素；第一子数据线组Y91-120的数据传输起始时刻均迟于基准时刻，从而保证四个第一子数据线组的数据信号不同时传输至显示面板的子像素，具体为第一子数据线组Y91-120的数据延迟提前传输至子像素。
本申请的实施例提供的显示装置中，通过将一个源极驱动单元内的所有数据线分为多个第一数据线组，再将各第一数据线组分为多个第一子数据线组，并设置多个第一子数据线组的数据传输起始时刻可调，从而可以很好的改善由于源极驱动单元内部分区域阻抗变化不均匀、栅线上与不同数据线相交处的栅极信号传输延迟等引起的V-Block问题，提高调试灵活性与补偿程 度。
可选地，各第一子数据线组中的所有数据线的数据传输起始时刻相同。从而更易进行设置，简单易实现。
可选地，多个第一子数据线组沿依次远离栅极驱动器的方向排列；源极驱动单元被配置为：在与同一条栅线相交的多个第一子数据线组中，以任一个第一子数据线组为第三基准数据线组，第三基准数据线组的数据传输起始时刻为基准时刻。
在与同一条栅线相交的多个第一子数据线组中，第三基准数据线组处于与栅极驱动器距离最近的情况下，多个第一子数据线组中除第三基准数据线组以外的第一子数据线组的数据传输起始时刻迟于基准时刻，以使得和源极驱动单元电连接的多个第一子数据线组中的数据线与同一条栅线形成的各子像素的有效充电时间相同；在与同一条栅线相交的多个第一子数据线组中，第三基准数据线组处于与栅极驱动器距离最远的情况下，多个第一子数据线组中除第三基准数据线组以外的第一子数据线组的数据传输起始时刻早于基准时刻，以使得和源极驱动单元电连接的多个第一子数据线组中的数据线与同一条栅线形成的各子像素的有效充电时间相同；在与同一条栅线相交的多个第一子数据线组中，第三基准数据线组处于与栅极驱动器距离中间的情况下，多个第一子数据线组中，比第三基准数据线组与源极驱动器的距离近的第一子数据线组的数据传输起始时刻早于基准时刻，比第三基准数据线组与源极驱动器的距离远的第一子数据线组的数据传输起始时刻迟于基准时刻，以使得和源极驱动单元电连接的多个第一子数据线组中的数据线与同一条栅线形成的各子像素的有效充电时间相同。
结合图6和图7所示，第一数据线组Y1-120、Y121-240、Y241-360、Y361-480、Y600-481、Y720-601、Y840-721和Y960-841沿依次远离显示面板1左侧的栅极驱动器6的方向排列，或者是第一数据线组Y960-841、Y840-721、Y720-601、Y600-481、Y361-480、Y241-360、Y121-240和Y1-120沿依次远离显示面板1右侧的栅极驱动器6的方向排列，也即Y1-120到显示面板1左侧的栅极驱动器6的距离和Y960-841到显示面板1右侧的栅极驱动器6的距离相同，其它第一数据线组可以依次类推。在此基础上，第一子数据线组Y1-30、Y31-60、Y61-90和Y91-120沿依次远离显示面板1左侧的栅极驱动器6的方向排列。
在第一子数据线组Y1-30、Y31-60、Y61-90和Y91-120中，第三基准数 据线组为第一子数据线组Y1-30、且数据传输起始时刻为基准时刻的情况下，第一子数据线组Y31-60、Y61-90和Y91-120的数据传输起始时刻均迟于基准时刻，从而保证四个第一子数据线组的数据信号不同时传输至显示面板的子像素，具体为第一子数据线组Y31-60、Y61-90和Y91-120的数据信号依次延迟传输至子像素。
在第一子数据线组Y1-30、Y31-60、Y61-90和Y91-120中，第三基准数据线组为第一子数据线组Y91-120、且数据传输起始时刻为基准时刻的情况下，第一子数据线组Y1-30、Y31-60和Y61-90的数据传输起始时刻均早于基准时刻，从而保证四个第一子数据线组的数据信号不同时传输至显示面板的子像素，具体为第一子数据线组Y1-30、Y31-60和Y61-90的数据信号依次提前传输至子像素。
在第一子数据线组Y1-30、Y31-60、Y61-90和Y91-120中，第三基准数据线组为第一子数据线组Y31-60、且数据传输起始时刻为基准时刻的情况下，第一子数据线组Y1-30的数据传输起始时刻早于基准时刻，从而保证四个第一子数据线组的数据信号不同时传输至显示面板的子像素，具体为第一子数据线组Y1-30的数据信号提前传输至子像素；第一子数据线组Y61-90和Y91-120的数据传输起始时刻均迟于基准时刻，从而保证四个第一子数据线组的数据信号不同时传输至显示面板的子像素，具体为第一子数据线组Y61-90和Y91-120的数据延迟提前传输至子像素。
在第一子数据线组Y1-30、Y31-60、Y61-90和Y91-120中，第三基准数据线组为第一子数据线组Y61-90、且数据传输起始时刻为基准时刻的情况下，第一子数据线组Y1-30和Y31-60的数据传输起始时刻均早于基准时刻，从而保证四个第一子数据线组的数据信号不同时传输至显示面板的子像素，具体为第一子数据线组Y1-30和Y31-60的数据信号提前传输至子像素；第一子数据线组Y91-120的数据传输起始时刻迟于基准时刻，从而保证四个第一子数据线组的数据信号不同时传输至显示面板的子像素，具体为第一子数据线组Y91-120的数据延迟提前传输至子像素。
可选地，与同一条栅线相交的所有数据线包括M个第一数据线组，M个第一数据线组沿依次远离栅极驱动器的方向排序；在第一模式下，M个第一数据线组中，第N序列的第一数据线组中的数量线的数量与第M-N+1序列的第一数据线组中的数量线的数量相同、且均为偶数；其中，M为大于或等于2的偶数，N为大于或等于1的整数。
上述第一模式为V-Shift模式。
下面以与同一条栅线相交的所有数据线数量为960条、且M为8、N为1为例进行说明。结合图6和图7所示，960条数据线包括第一数据线组Y1-120、Y121-240、Y241-360、Y361-480、Y600-481、Y720-601、Y840-721和Y960-841，第1序列的第一数据线组中的数量线的数量与第8序列的第一数据线组中的数量线的数量相同、第2序列的第一数据线组中的数量线的数量与第7序列的第一数据线组中的数量线的数量相同、第3序列的第一数据线组中的数量线的数量与第6序列的第一数据线组中的数量线的数量相同、第4序列的第一数据线组中的数量线的数量与第5序列的第一数据线组中的数量线的数量相同，且均为120条。
可选地，沿远离栅极驱动器的方向，各第一数据线组的数据传输起始时刻依次递增。从而更易进行设置，简单易实现。
可选地，在与同一条栅线相交的多个第一数据线组中，各第一数据线组包括偶数个第一子数据线组；沿远离栅极驱动器的方向，各第一数据线组中的第一子数据线组的数量依次递增。从而更易进行设置，简单易实现。
可选地，沿远离栅极驱动器的方向，各第一数据线组中的第一子数据线组的数据传输起始时刻以相同倍数依次递增。从而更易进行设置，简单易实现。
下面结合图6和图7，以960条数据线分为8个第一数据线组，且960条数据线采用V-Shift模式(即Y480/Y481为最后传输数据的数据线)为例进行说明。
在第一数据线组Y1-120间和第一数据线组Y960-841间，均采用30条数据线为一个第一子数据线组，各第一子数据线组之间的数据传输起始时刻延迟8UI，再乘以1倍，即各第一子数据线组之间延迟8UI。那么第一数据线组Y1-120的数据传输起始时刻共延迟32UI、第一数据线组Y960-721的数据传输起始时刻共延迟32UI。
在第一数据线组Y121-240间和第一数据线组Y840-721间，均采用20条数据线为一个第一子数据线组，各第一子数据线组之间的数据传输起始时刻延迟6UI，再乘以2倍，即各第一子数据线组之间延迟12UI。那么第一数据线组Y121-240的数据传输起始时刻共延迟72UI、第一数据线组Y840-721的数据传输起始时刻共延迟72UI。
在第一数据线组Y241-360间和第一数据线组Y720-601间，均采用12 条数据线为一个第一子数据线组，各第一子数据线组之间的数据传输起始时刻延迟8UI，再乘以2倍，即各第一子数据线组之间延迟16UI。那么第一数据线组Y241-360的数据传输起始时刻共延迟160UI、第一数据线组Y720-601的数据传输起始时刻共延迟160UI。
在第一数据线组Y361-480间和第一数据线组Y600-481间，均采用6条数据线为一个第一子数据线组，各第一子数据线组之间的数据传输起始时刻延迟6UI，再乘以3倍，即各第一子数据线组之间延迟18UI。那么第一数据线组Y361-480的数据传输起始时刻共延迟360UI、第一数据线组Y600-481的数据传输起始时刻共延迟360UI。
相关技术中对于960条数据线例如进行图8所示的V-Shift调节时，参考图8所示，对各数据线的延迟时间调整是固定且均匀的，且整个源极驱动单元内的延迟时间分组也是固定的。但由于显示装置中各数据线的阻抗差异不均匀(位于显示面板中间的数据线的阻抗小，从位于显示面板中间的数据线向位于显示面板两端的数据线的阻抗逐步增大)，故造成调试完成后仍出现大区域适当均匀、小区域内Block仍无改善的问题，如图5所示。参考图5所示，中间区域Block调试较优后，Y1与Y960附近由于阻抗过大，仍留有一块明显的黑色Block无法解决，且源极驱动单元内横向仍存在亮度不均匀问题。
针对上述问题，本申请的实施例提供的显示装置例如采用V-Shift方式调节时，采用多分组可调方案，例如可以将960条数据线分为8个第一数据线组，每个第一数据线组中的120条数据线又可以分为4个第一子数据线组，例如可选择6/12/20/30条为一组，这样每120条数据线的延迟时间可调整为不均匀的过渡方式。即本申请通过设置一个源极驱动单元内不同通道范围内延迟时间分组、延迟时间可调，且Y1ch/Y960作为起始点的方式，从而可以很好的改善由于源极驱动单元内部分区域阻抗变化不均匀、栅线上与不同数据线相交处的栅极信号传输延迟等引起的某区域过黑或过亮等问题，提高调试灵活性与补偿程度。
可选地，源极驱动器包括多个源极驱动单元。
栅极驱动器被配置为：向栅线传输第一预设时间范围的栅极信号。
多条数据线分为多组，各源极驱动单元电连接一组数据线；多个源极驱动单元中，以任一个源极驱动单元为基准源极驱动单元，除基准源极驱动单元以外的其余源极驱动单元为调节源极驱动单元；在与同一条栅线相交的多 组数据线中，以与基准源极驱动单元电连接的任一条数据线为第二基准数据线，第二基准数据线的数据传输起始时刻为基准时刻；基准源极驱动单元电连接的数据线中与相邻调节源极驱动单元距离最近的数据线为第一数据线，调节源极驱动单元中与基准源极驱动单元距离最近的数据线为第二数据线。
在与同一条栅线相交的多组数据线中，栅线上与第二基准数据线相交处的栅极信号最早传输的情况下，第一数据线的数据传输起始时刻迟于基准时刻、且第一数据线的数据传输起始时刻与第二数据线的数据传输起始时刻相同，以使得和源极驱动单元电连接的多组数据线组中的数据线与同一条栅线形成的各子像素的有效充电时间相同。
这里对于上述源极驱动器包括的源极驱动单元的数量不做具体限定，示例的，上述源极驱动器可以包括两个源极驱动单元；或者，上述源极驱动器可以包括三个及以上源极驱动单元。
这里对于上述多条数据线分成的组数不做具体限定，示例的，上述多条数据线可以分为两组，当然，上述多条数据线还可以分为三组及以上，可以根据源极驱动单元的数量确定数据线分成的组数。
图9以显示装置包括两个源极驱动单元，即COF1和COF2，各COF内均包括960条数据线为例进行绘示。参考图9所示，以COF1为基准源极驱动单元，COF2则为调节源极驱动单元。在COF1中，第二基准数据线为数据线Y1、且数据传输起始时刻为基准时刻的情况下，第一数据线为COF1中的Y960，第二数据线为COF2中的Y1。在COF1的数据线Y1-960和COF2的数据线Y1-960中，第二基准数据线为COF1中的Y1、且其数据传输起始时刻为基准时刻的情况下，COF1中的数据线Y2-960和COF2中的数据线Y1-960的数据传输起始时刻均迟于基准时刻、且COF1中的数据线Y960与COF2中的数据线Y1的数据传输起始时刻相同，同时COF2中的数据线Y2-960的数据传输起始时刻均迟于COF2中的数据线Y1的数据传输起始时刻，从而保证COF1和COF2内的所有数据线的数据信号不同时传输至显示面板的子像素。
大尺寸显示面板整体横向栅线上栅极信号的延迟，导致越靠近显示面板中央的像素充电越好，越靠近显示面板中间的COF的Delay设定往往需要更大，而当COF与COF间设定一个整体Delay时间时，相邻两个COF的Y1和Y960可能由于Delay设定有一个亮度差，COF与COF间的Delay无法有效衔接，故而显示面板充电差异还体现在源极驱动单元和源极驱动单元， 即COF与COF之间。相关技术中例如对于多个COF使用V-Shift模式驱动时，参考图10所示，由于COF1与COF2之间的Delay设定，即固定为Y1和Y960起始同时输出，Y480和Y481需保证最后同一时刻输出，导致Y1-480与Y960-481无法调试不同的Delay方式，此时再配合上COF1和COF2间的整体Delay，COF1与COF2交界处容易形成亮暗分界线，无法有效衔接COF1内与COF2间的Delay。
针对上述问题，本申请的实施例提出了一种显示装置，该显示装置可以选择Y1或Y960其中一个为起始点(图9以COF1中的1ch作为起始点)，另一个通道则相对于起始点进行Delay，以完成COF1与COF2间的Delay匹配。具体的，参考图4所示，COF1选择1ch为起始点输出，假设COF1内的Y1-480共Delay624UI、且COF1内的Y960-481共Delay512UI(此处需要COF1内的Y1-480与Y960-481的Delay时间不同)，则COF1内的Y960起始输出时间调整为相对于Y1输出时刻Delay240UI，此时当COF2相对COF1Delay240UI时，COF1中的Y960与COF2中的1为同时输出，从而可以有效的改善COF与COF交界处易形成亮暗分界线，无法有效衔接COF内与COF间的Delay的问题，补偿设定方式更加灵活与有效。
需要说明的是，在上述COF1内的Y1-480与Y960-481的Delay时间取决于COF1与COF2间设定的Delay时间。
可选地，与基准源极驱动单元电连接的所有数据线分为第一部分和第二部分，第一部分包括第二基准数据线，第一部分中的所有数据线的数据传输延迟时间与第二部分中的所有数据线的数据传输延迟时间不同。从而使得控制较为方便，简单易实现。
图9以COF1为基准源极驱动单元，图9中数据线Y1-Y960分为第一部分Y1-480、第二部分Y960-481。示例的，可以通过设置第一部分Y1-480中，Y1-120共delay32UI、Y121-240共delay72UI、Y241-360共delay160UI、和Y361-480共delay360UI，则第一部分Y1-480共delay624UI；可以通过设置第二部分Y960-481中，Y960-841共delay24UI、Y840-721共delay48UI、Y720-601共delay120UI和Y600-481共delay320UI，则第二部分Y960-481共delay512UI。
可选地，在第一模式下，第一部分中的所有数据线的数据传输延迟时间大于第二部分中的所有数据线的数据传输延迟时间。从而使得控制较为方便，简单易实现。
图9以COF1为基准源极驱动单元，图9中数据线Y1-Y960分为第一部分Y1-480、第二部分Y960-481。示例的，可以通过设置第一部分Y1-480中，Y1-120共delay32UI、Y121-240共delay72UI、Y241-360共delay160UI、和Y361-480共delay360UI，则第一部分Y1-480共delay624UI；可以通过设置第二部分Y960-481中，Y960-841共delay24UI、Y840-721共delay48UI、Y720-601共delay120UI和Y600-481共delay320UI，则第二部分Y960-481共delay512UI。第一部分Y1-480和第二部分Y960-481相差112UI。
可选地，参考图11所示，源极驱动单元包括数据输入模块101、多通道延迟控制模块102、数模转换模块103、输出模块104和逻辑控制模块105。
数据输入模块101与逻辑控制模块105和多通道延迟控制模块102均电连接、且被配置为：在逻辑控制模块105的第一控制信号的控制下，接收并解析视频信号，得到视频信号的第一数据；向多通道延迟控制模块102传输第一数据。
多通道延迟控制模块102与逻辑控制模块105和数模转换模块103均电连接、且被配置为：在逻辑控制模块105的第二控制信号的控制下，接收并解析第一数据，得到各数据线的具有不同起始时刻的第二数据；向数模转换模块103传输第二数据。
数模转换模块103还与输出模块电连接、且被配置为：接收并转换第二数据，得到第三数据；向输出模块传输104第三数据。
输出模块104被配置为：接收并输出第三数据。
下面结合图2，说明图11所示的源极驱动单元的具体工作流程。
数据输入模块101的接口可以在逻辑控制模块105的第一控制信号的控制下，例如在SOE_S时刻接收从时序控制7传输的视频信号，该视频信号可以包括第一数据和传输协议等。其中第一数据可以为图像数据，数据输入模块101的接口可以为CEDS/USIT接口。接着，多通道延迟控制模块102可以在逻辑控制模块105的第二控制信号的控制下，例如在GDE/PPCC模式下接收图像数据，并进行处理。然后，数模转换模块103接收处理后的图像数据，并进行数模转换，例如可以在伽马电压GMA1-18的控制下确定数模转换后的模拟电压。最后，输出模块104接收前述的模拟电压，并向各数据线在不同时刻输出图像数据。
需要说明的是，逻辑控制模块105会向多通道延迟控制模块102和输出模块104输出一个同步信号，以控制输出模块输出的经过数模转换后的模拟 信号，与多通道延迟控制模块102处理后的数字信号同步。
本申请的实施例提供了一种新型的显示装置，该显示装置具有可编程充电补偿方式与调试方法，能够提高补偿灵活性和补偿程度，最大程度改善V-Block问题，用户体验佳。
可选地，参考图12所示，多通道延迟控制模块包括方式选择子模块201、数据选择子模块202、第一分组控制子模块203、第二分组控制子模块204和延迟子模块205。
方式选择子模块201与数据选择子模块202电连接、且被配置为：在逻辑控制模块的第二控制信号的控制下，接收第一数据，并选择一种延迟模式；向数据选择子模块传输第一数据。
数据线选择子模块202还与第一分组控制单元203电连接、且被配置为：在逻辑控制模块的第二控制信号的控制下，接收第一数据，并确定延迟模式，根据延迟模式选择起始数据线；向第一分组控制子模块传输第一数据。
第一分组控制子模块203还与第二分组控制单元204电连接、且被配置为：在逻辑控制模块的第二控制信号的控制下，接收第一数据，并根据起始数据线确定第一数据线组。
第二分组控制子模块204还与延迟单元205电连接、且被配置为：在逻辑控制模块的第二控制信号的控制下，接收第一数据，并根据第一数据线组确定第一子数据线组。
延迟子模块205被配置为：在逻辑控制模块的第二控制信号的控制下，接收第一数据，并根据第一子数据线组解析第一数据，得到第一子数据线组中数据线的具有不同起始时刻的第二数据。
下面结合图11，说明图12所示的多通道延迟控制模块的具体工作流程。
方式选择子模块201可以在逻辑控制模块105的第二控制信号的控制下，例如在GDE/PPCC模式下接收图像数据，并确定一种模式，如V-shift模式；接着，数据线选择子模块202接收图像数据，并根据V-shift模式确定最先传输图像数据信号的数据线；然后，第一分组控制子模块203将数据线分为多个第一数据线组，例如可以将一个COF内的960ch分为八组，每120ch一组；接着，第二分组控制子模块204将各第一数据线组分为多个第一子数据线组，例如可以将120ch一组分为四个第一子数据线组；最后，设定各第一子数据线组间的Delay时间与Delay时间倍数。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本 申请的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (16)

  1. 一种显示装置，其中，包括：
    显示面板，包括多条栅线和多条数据线，所述栅线与所述数据线相交且绝缘设置；所述显示面板还包括阵列排布的多个子像素，所述栅线和所述数据线限定出所述子像素所在的区域；
    栅极驱动器，与所述显示面板中的所述多条栅线电连接；
    源极驱动器，与显示面板绑定、且与所述显示面板中的所述多条数据线电连接；所述源极驱动器被配置为：设定各所述数据线的数据传输起始时刻，以使得多条所述数据线与同一条栅线形成的各子像素的有效充电时间相同。
  2. 根据权利要求1所述的显示装置，其中，所述源极驱动器包括源极驱动单元；
    所述栅极驱动器被配置为：向所述栅线传输第一预设时间范围的栅极信号；
    所述源极驱动单元被配置为：向多条所述数据线传输数据信号；其中，在与同一条栅线相交的多条数据线中，以任一条所述数据线为第一基准数据线，所述第一基准数据线的数据传输起始时刻为基准时刻；
    在与同一条所述栅线相交的多条所述数据线中，所述栅线上与所述第一基准数据线相交处的栅极信号最早传输的情况下，多条所述数据线中除所述第一基准数据线以外的数据线的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多条数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
    在与同一条所述栅线相交的多条所述数据线中，所述栅线上与所述第一基准数据线相交处的栅极信号最晚传输的情况下，多条所述数据线中除所述第一基准数据线以外的数据线的数据传输起始时刻早于所述基准时刻，以使得和所述源极驱动单元电连接的所述多条数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
    在与同一条所述栅线相交的多条所述数据线中，所述栅线上与所述第一基准数据线相交处的栅极信号处于中间传输的情况下，多条所述数据线中，比所述栅线上与所述第一基准数据线相交处的栅极信号早传输的数据线的数据传输起始时刻早于所述基准时刻；多条所述数据线中，比所述栅线上与所述第一基准数据线相交处的栅极信号晚传输的数据 线的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多条数据线与同一条所述栅线形成的各子像素的有效充电时间相同。
  3. 根据权利要求2所述的显示装置，其中，所有所述数据线包括多个第一数据线组，各所述第一数据线组包括多条数据线；
    所述源极驱动单元被配置为：在与同一条栅线相交的多个第一数据线组中，以任一个所述第一数据线组为第一基准数据线组，所述第一基准数据线组的数据传输起始时刻为基准时刻；
    在与同一条所述栅线相交的多个所述第一数据线组中，所述栅线上与所述第一基准数据线组相交处的栅极信号最早传输的情况下，多个所述第一数据线组中除所述第一基准数据线组以外的第一数据线组的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
    在与同一条所述栅线相交的多个所述第一数据线组中，所述栅线上与所述第一基准数据线组相交处的栅极信号最晚传输的情况下，多个所述第一数据线组中除所述第一基准数据线组以外的第一数据线组的数据传输起始时刻早于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
    在与同一条所述栅线相交的多个所述第一数据线组中，所述栅线上与所述第一基准数据线组相交处的栅极信号处于中间传输的情况下，多个所述第一数据线组中，比所述栅线与所述第一基准数据线组相交处的栅极信号早传输的第一数据线组的数据传输起始时刻早于所述基准时刻；多个所述第一数据线组中，比所述栅线与所述第一基准数据线组相交处的栅极信号晚传输的第一数据线组的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同。
  4. 根据权利要求3所述的显示装置，其中，所有所述数据线的数量与所有所述第一数据线组的数量的商值为整数、且各所述第一数据线组中的数据线的数量相同。
  5. 根据权利要求4所述的显示装置，其中，所述源极驱动单元被 配置为：各所述第一数据线组中所有所述数据线包括多个第一子数据线组，所述第一子数据线组包括至少一条数据线；在与同一条栅线相交的多个第一子数据线组中，以任一个所述第一子数据线组为第二基准数据线组，所述第二基准数据线组的数据传输起始时刻为基准时刻；
    在与同一条所述栅线相交的多个所述第一子数据线组中，所述栅线上与所述第二基准数据线组相交处的栅极信号最早传输的情况下，多个所述第一子数据线组中除所述第二基准数据线组以外的第一子数据线组的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一子数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
    在与同一条所述栅线相交的多个所述第一子数据线组中，所述栅线上与所述第二基准数据线组相交处的栅极信号最晚传输的情况下，多个所述第一子数据线组中除所述第二基准数据线组以外的第一子数据线组的数据传输起始时刻早于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一子数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
    在与同一条所述栅线相交的多个所述第一子数据线组中，所述栅线上与所述第二基准数据线组相交处的栅极信号处于中间传输的情况下，多个所述第一子数据线组中，比所述栅线与所述第二基准数据线组相交处的栅极信号早传输的第一子数据线组的数据传输起始时刻早于所述基准时刻；多个所述第一子数据线组中，比所述栅线与所述第二基准数据线组相交处的栅极信号晚传输的第一子数据线组的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一子数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同。
  6. 根据权利要求5所述的显示装置，其中，各所述第一子数据线组中的所有所述数据线的数据传输起始时刻相同。
  7. 根据权利要求5所述的显示装置，其中，多个所述第一子数据线组沿依次远离所述栅极驱动器的方向排列；所述源极驱动单元被配置为：在与同一条栅线相交的多个所述第一子数据线组中，以任一个所述第一子数据线组为第三基准数据线组，所述第三基准数据线组的数据传输起始时刻为基准时刻；
    在与同一条所述栅线相交的多个所述第一子数据线组中，所述第三基准数据线组处于与所述栅极驱动器距离最近的情况下，多个所述第一子数据线组中除所述第三基准数据线组以外的第一子数据线组的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一子数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
    在与同一条所述栅线相交的多个所述第一子数据线组中，所述第三基准数据线组处于与所述栅极驱动器距离最远的情况下，多个所述第一子数据线组中除所述第三基准数据线组以外的第一子数据线组的数据传输起始时刻早于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一子数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同；
    在与同一条所述栅线相交的多个所述第一子数据线组中，所述第三基准数据线组处于与所述栅极驱动器距离中间的情况下，多个所述第一子数据线组中，比所述第三基准数据线组与所述源极驱动器的距离近的第一子数据线组的数据传输起始时刻早于所述基准时刻，比所述第三基准数据线组与所述源极驱动器的距离远的第一子数据线组的数据传输起始时刻迟于所述基准时刻，以使得和所述源极驱动单元电连接的所述多个第一子数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同。
  8. 根据权利要求7所述的显示装置，其中，与同一条所述栅线相交的所有所述数据线包括M个第一数据线组，M个所述第一数据线组沿依次远离所述栅极驱动器的方向排序；
    在第一模式下，M个所述第一数据线组中，第N序列的第一数据线组中的数量线的数量与第M-N+1序列的第一数据线组中的数量线的数量相同、且均为偶数；其中，M为大于或等于2的偶数，N为大于或等于1的整数。
  9. 根据权利要求8所述的显示装置，其中，沿远离所述栅极驱动器的方向，各所述第一数据线组的数据传输起始时刻依次递增。
  10. 根据权利要求9所述的显示装置，其中，在与同一条所述栅线相交的多个所述第一数据线组中，各所述第一数据线组包括偶数个第一子数据线组；
    沿远离所述栅极驱动器的方向，各所述第一数据线组中的所述第一子数据线组的数量依次递增。
  11. 根据权利要求10所述的显示装置，其中，沿远离所述栅极驱动器的方向，各所述第一数据线组中的所述第一子数据线组的数据传输起始时刻以相同倍数依次递增。
  12. 根据权利要求1所述的显示装置，其中，所述源极驱动器包括多个源极驱动单元；
    所述栅极驱动器被配置为：向所述栅线传输第一预设时间范围的栅极信号；
    所述多条数据线分为多组，各所述源极驱动单元电连接一组数据线；多个所述源极驱动单元中，以任一个所述源极驱动单元为基准源极驱动单元，除所述基准源极驱动单元以外的其余源极驱动单元为调节源极驱动单元；在与同一条栅线相交的多组数据线中，以与所述基准源极驱动单元电连接的任一条所述数据线为第二基准数据线，所述第二基准数据线的数据传输起始时刻为基准时刻；所述基准源极驱动单元电连接的数据线中与相邻调节源极驱动单元距离最近的数据线为第一数据线，所述调节源极驱动单元中与所述基准源极驱动单元距离最近的数据线为第二数据线；
    在与同一条栅线相交的多组数据线中，所述栅线上与所述第二基准数据线相交处的栅极信号最早传输的情况下，所述第一数据线的数据传输起始时刻迟于所述基准时刻、且所述第一数据线的数据传输起始时刻与所述第二数据线的数据传输起始时刻相同，以使得和所述源极驱动单元电连接的多组数据线组中的数据线与同一条所述栅线形成的各子像素的有效充电时间相同。
  13. 根据权利要求12所述的显示装置，其中，与所述基准源极驱动单元电连接的所有所述数据线分为第一部分和第二部分，所述第一部分包括所述第二基准数据线，所述第一部分中的所有数据线的数据传输延迟时间与所述第二部分中的所有数据线的数据传输延迟时间不同。
  14. 根据权利要求13所述的显示装置，其中，在第一模式下，所述第一部分中的所有数据线的数据传输延迟时间大于所述第二部分中的所有数据线的数据传输延迟时间。
  15. 根据权利要求2或12所述的显示装置，其中，所述源极驱动 单元包括数据输入模块、多通道延迟控制模块、数模转换模块、输出模块和逻辑控制模块；
    所述数据输入模块与所述逻辑控制模块和所述多通道延迟控制模块均电连接、且被配置为：在所述逻辑控制模块的第一控制信号的控制下，接收并解析视频信号，得到所述视频信号的第一数据；向所述多通道延迟控制模块传输所述第一数据；
    所述多通道延迟控制模块与所述逻辑控制模块和所述数模转换模块均电连接、且被配置为：在所述逻辑控制模块的第二控制信号的控制下，接收并解析所述第一数据，得到各数据线的具有不同起始时刻的第二数据；向所述数模转换模块传输所述第二数据；
    所述数模转换模块还与所述输出模块电连接、且被配置为：接收并转换所述第二数据，得到第三数据；向所述输出模块传输所述第三数据；
    所述输出模块被配置为：接收并输出所述第三数据。
  16. 根据权利要求15所述的显示装置，其中，所述多通道延迟控制模块包括方式选择子模块、数据选择子模块、第一分组控制子模块、第二分组控制子模块和延迟子模块；
    所述方式选择子模块与所述数据选择子模块电连接、且被配置为：在所述逻辑控制模块的所述第二控制信号的控制下，接收所述第一数据，并选择一种延迟模式；向所述数据选择子模块传输所述第一数据；
    所述数据线选择子模块还与所述第一分组控制单元电连接、且被配置为：在所述逻辑控制模块的所述第二控制信号的控制下，接收所述第一数据，并确定所述延迟模式，根据所述延迟模式选择起始数据线；向所述第一分组控制子模块传输所述第一数据；
    所述第一分组控制子模块还与所述第二分组控制单元电连接、且被配置为：在所述逻辑控制模块的所述第二控制信号的控制下，接收所述第一数据，并根据所述起始数据线确定第一数据线组；
    所述第二分组控制子模块还与所述延迟单元电连接、且被配置为：在所述逻辑控制模块的所述第二控制信号的控制下，接收所述第一数据，并根据所述第一数据线组确定第一子数据线组；
    所述延迟子模块被配置为：在所述逻辑控制模块的所述第二控制信号的控制下，接收所述第一数据，并根据所述第一子数据线组解析第一数据，得到第一子数据线组中数据线的具有不同起始时刻的第二数据。
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CN113570997A (zh) * 2021-07-30 2021-10-29 北京京东方显示技术有限公司 一种显示装置
CN115188312A (zh) * 2022-07-27 2022-10-14 Tcl华星光电技术有限公司 显示面板、驱动方法及显示装置

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KR20040035276A (ko) * 2002-10-19 2004-04-29 엘지.필립스 엘시디 주식회사 액정표시장치
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