WO2024119613A1 - 存储器及其控制方法、存储器系统 - Google Patents

存储器及其控制方法、存储器系统 Download PDF

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Publication number
WO2024119613A1
WO2024119613A1 PCT/CN2023/075741 CN2023075741W WO2024119613A1 WO 2024119613 A1 WO2024119613 A1 WO 2024119613A1 CN 2023075741 W CN2023075741 W CN 2023075741W WO 2024119613 A1 WO2024119613 A1 WO 2024119613A1
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WIPO (PCT)
Prior art keywords
signal
circuit
output
error bit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/075741
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English (en)
French (fr)
Inventor
陈腾
乔梁
栗山正男
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to US18/326,750 priority Critical patent/US20240194276A1/en
Publication of WO2024119613A1 publication Critical patent/WO2024119613A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory

Definitions

  • the present application relates to the field of semiconductor technology, and relates to but is not limited to a memory and a control method thereof, and a memory system.
  • VFC Verify Failbit Count
  • the circuit that performs VFC is correspondingly called a VFC circuit.
  • the operation of the VFC circuit consumes the power consumption of the 3D NAND memory and the VFC circuit occupies the space of the memory. In order to save power consumption and reduce the space occupied by VFC, the VFC circuit needs to be optimized.
  • embodiments of the present application provide a memory and a control method thereof, and a memory system.
  • an embodiment of the present application provides a memory, wherein the memory includes a storage unit element array and peripheral circuit; the peripheral circuit at least includes:
  • a trigger circuit comprising a reference signal output circuit and an error bit signal output circuit
  • the error bit signal output circuit is configured to: generate an error bit signal according to a detection signal obtained by verifying the memory;
  • the reference signal output circuit is configured to: output at least one reference signal
  • a comparator is coupled to the trigger circuit; the comparator is configured to:
  • the error bit signal is compared with at least one of the reference signals, and a verification result is output.
  • the reference signal output circuit comprises:
  • a plurality of parallel branches each branch comprising at least one controlled switch; the plurality of parallel branches are respectively configured to output at least one of the reference signals.
  • the controlled switch is configured to:
  • the controlled switch that receives the first enable signal switches to a conducting state, so that the corresponding branch is turned on and provides the reference signal.
  • the comparator includes at least two; the reference signal output circuit includes at least two sub-output circuits; each of the sub-output circuits includes at least one branch, and one sub-output circuit is connected to one comparator, wherein the number of the sub-output circuits is the same as the number of the comparators.
  • the input terminal of the comparator is connected to the trigger circuit and is configured as follows:
  • the comparison parameter indicates that the error bit signal is less than or equal to the reference signal, the comparison is stopped and the verification result is output.
  • the peripheral circuit further includes:
  • a delay circuit is coupled to the comparator; the delay circuit is configured as follows:
  • the multiple comparison parameters output by the comparator are delayed respectively, and the delayed comparison parameters are output.
  • the peripheral circuit further includes:
  • the latch circuit includes a plurality of latches coupled to the delay circuit, wherein the latches are configured to store the delay comparison parameters; wherein the number of the latches is the same as the number of the reference signals.
  • the latch circuit is further coupled to the trigger circuit, wherein the latch is configured to:
  • a feedback signal is output according to the latch signal; wherein the feedback signal is configured to trigger the trigger circuit to switch the reference signal to be compared.
  • the memory further comprises:
  • a code conversion circuit is coupled to the latch circuit; the code conversion circuit is configured as follows:
  • the latch signal is converted into a binary code; the binary code is configured to calculate the verification result.
  • the peripheral circuit further includes:
  • An accumulator is coupled to the code conversion circuit; the accumulator is configured as follows:
  • the plurality of binary codes obtained from the code conversion circuit are accumulated to obtain the verification result of the error bit count.
  • the latch circuit is further configured to:
  • a reset signal is received to reset the latch signal.
  • the peripheral circuit further includes:
  • a reference circuit is connected to the trigger circuit and is configured to trigger the trigger circuit based on an external input signal.
  • the trigger circuit outputs a control signal; the control signal is configured to enable the trigger circuit.
  • control signal includes a first control signal and a second control signal; wherein the first control signal is configured to enable the reference signal output circuit to output multiple reference signals; and the second control signal is configured to enable the error bit signal output circuit to receive the detection signal.
  • an embodiment of the present disclosure further provides a control method for a memory, and the control method should be configured as a peripheral circuit of the memory, including:
  • the error bit signal is compared with at least one of the reference signals, and a verification result is output.
  • control method further includes:
  • a plurality of first enable signals are received in sequence; wherein the controlled switch receiving the first enable signal is switched to an on state; and the branch connected to the controlled switch in the on state is turned on and configured to provide the reference signal.
  • comparing the error bit signal with the plurality of reference signals and outputting a verification result comprises:
  • the latch signal indicates that the error bit signal is greater than the reference signal, comparing the error bit signal with a next reference signal until the delay comparison parameter indicates that the error bit signal is less than or equal to the reference signal;
  • comparing the error bit signal with a next reference signal comprises:
  • the latch outputs a feedback signal according to the latch signal
  • the first enable signal is output to the next controlled switch, wherein the controlled switch receiving the first enable signal is switched to an on state, and the trigger circuit generates a next reference signal and compares it with the error bit signal.
  • the method further comprises:
  • a reset signal is received to reset the latch signal.
  • the method further comprises:
  • a control signal is output; wherein the control signal includes: a first control signal configured to enable output of the plurality of reference signals and a second control signal configured to enable reception of the detection signal.
  • an embodiment of the present disclosure provides a memory system, including:
  • a memory controller and a memory as described in any of the above embodiments.
  • the memory provided in the embodiment of the present application utilizes a reusable comparator coupled to a trigger circuit, and sequentially compares the error bit signal generated by the trigger circuit with a plurality of reference signals outputted.
  • FIG1A is a schematic diagram of the structure of an exemplary system provided in an embodiment of the present application.
  • FIG1B is a schematic diagram of the structure of a memory card provided in an embodiment of the present application.
  • FIG1C is a schematic diagram of the structure of a solid state drive (SSD) provided in an embodiment of the present application.
  • SSD solid state drive
  • FIGS. 1D and 1E are schematic diagrams of a structure of a memory including a memory cell array and a peripheral circuit provided in an embodiment of the present application;
  • FIG. 1F is a schematic diagram of a memory including a VFC circuit provided in an embodiment of the present application. picture;
  • FIGS. 2A to 2C are schematic diagrams of the structure of a VFC circuit provided in an embodiment of the present application.
  • FIG3 is a schematic structural diagram of a trigger circuit connected to a comparator provided in an embodiment of the present application
  • FIG4 is a schematic structural diagram of a controlled switch provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of the structure of a plurality of groups of controlled switches provided in an embodiment of the present application.
  • 6A and 6B are schematic diagrams of the structure of a delay circuit provided in an embodiment of the present application.
  • FIG6C is a schematic diagram of the structure of an input delay comparison parameter provided in an embodiment of the present application.
  • FIGS. 7A to 7C are schematic diagrams of the structure of a latch circuit provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of the structure of a code conversion circuit provided in an embodiment of the present application.
  • FIG9 is a schematic diagram of the structure of an accumulator provided in an embodiment of the present application.
  • FIG10 is a schematic diagram of the structure of a latch provided in an embodiment of the present application.
  • FIG11 is a flow chart of a control method for a VFC circuit provided in an embodiment of the present application.
  • FIG. 12 is a timing diagram of a VFC circuit provided in an embodiment of the present application.
  • an embodiment of the present application shows an exemplary system 10, which may include a host 20 and a storage system 30.
  • the exemplary system 10 may include but is not limited to: Limited to mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having a memory 34;
  • the host 20 can be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of the electronic device.
  • CPU central processing unit
  • SoC system on a chip
  • AP application processor
  • the host 20 may be configured to send data to the storage system 30 or receive data from the storage system 30.
  • the storage system 30 may include a controller 32 and one or more memories 34.
  • the memory 34 may include, but is not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc.
  • the controller 32 can be coupled to the memory 34 and the host 20 and configured to control the memory 34.
  • the controller can be designed to be configured to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media configured for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.
  • the controller can also be designed to be configured to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, and enterprise storage arrays. Further, the controller can manage data in the memory and communicate with the host.
  • SSD secure digital
  • CF compact flash
  • USB universal serial bus
  • eMMC embedded multimedia card
  • the controller can be configured to control operations such as memory reading, erasing, and programming; it can also be configured to manage various functions regarding data stored or to be stored in the memory, including but not limited to Limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc.; it can also be configured to process error correction code (ECC) on data read from or written to the memory.
  • ECC error correction code
  • the controller can also perform any other suitable functions, such as formatting the memory, or communicating with an external device (e.g., host 20 in Figure 1A) according to a specific communication protocol.
  • the controller can communicate with the external device through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.
  • various interface protocols such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.
  • the controller and one or more memories can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the storage system can be implemented and packaged into different types of terminal electronic products.
  • the controller 32 and a single memory 34 can be integrated into a memory card 40.
  • the memory card 40 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc.
  • the memory card 40 may also include a memory card connector 42 that couples the memory card 40 to a host (e.g., the host 20 in FIG. 1A).
  • the controller 32 and multiple memories 34 may be integrated into an SSD 50.
  • the SSD 50 may also include an SSD connector 52 that couples the SSD 50 to a host (e.g., the host 20 in FIG. 1A).
  • the storage capacity and/or operating speed of SSD 50 is greater than the storage capacity and/or operating speed of memory card 40.
  • FIG. 1D is a schematic diagram of an optional memory 60 in the embodiment of the present application.
  • the memory 60 It may be the memory 34 in FIGS. 1A to 1C .
  • the memory 60 may be composed of a memory cell array 62 and a peripheral circuit 64 coupled to the memory cell array 62, etc.
  • the memory cell array may be a NAND flash memory cell array, wherein the memory cells are provided in the form of an array of NAND memory strings 66, each NAND memory string 66 extending vertically above a substrate (not shown).
  • each NAND memory string 66 may include a plurality of memory cells coupled in series and stacked vertically. Wherein, each memory cell is to maintain a continuous analog value, such as a voltage or charge, which depends on the number of electrons captured in the memory cell area.
  • each memory cell in the above-mentioned memory cell array 62 may be a floating gate type memory cell including a floating gate transistor, or a charge capture type memory cell including a charge capture transistor.
  • the above-mentioned memory cell may be a single-level memory cell (SLC) having two possible storage states and thus being able to store one bit of data.
  • the first storage state "0" may correspond to a first voltage range
  • the second storage state "1" may correspond to a second voltage range.
  • each memory cell is a multi-level memory cell (MLC) capable of storing more than a single bit of data in more than four memory states.
  • MLC multi-level memory cell
  • an MLC may store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)).
  • TLC triple-level cell
  • QLC quad-level cell
  • Each MLC may be programmed to take a range of possible nominal storage values.
  • the MLC may be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values to the memory cell.
  • the fourth nominal storage value may be configured as an erased state.
  • the above peripheral circuit can be coupled to the memory cell array through the bit line (Bit Line, BL), word line (Word Line, WL), source (Source Line), source select gate (Source Select Gate, SSG) and drain select gate (Drain Select Gate, DSG).
  • the peripheral circuit may include any suitable analog, digital and mixed signal circuits to configure To facilitate the operation of the memory cell array by applying a voltage signal and/or a current signal to each target memory cell via a bit line, a word line, a source, an SSG, and a DSG, and sensing a voltage signal and/or a current signal from each target memory cell.
  • a bit line Bit Line
  • word line a source
  • SSG source select gate
  • Drain Select Gate DSG
  • the peripheral circuit may include any suitable analog, digital and mixed signal circuits to configure To facilitate the operation of the memory cell array by applying a voltage signal and/or a current signal to each target memory cell via a bit line, a word line, a source, an SSG, and a D
  • the peripheral circuit may also include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. Exemplarily, as shown in FIG. 1E.
  • the peripheral circuit 70 includes a page buffer (Page Buffer)/sense amplifier 71, a VFC circuit/column decoder/bit line driver 72, a row decoder/word line driver 73, a voltage generator 74, a control logic unit 75, a register 76, an interface 77, and a data bus 78. It should be understood that the above-mentioned peripheral circuit 70 may be the same as the peripheral circuit 64 in FIG. 1D, and in some other embodiments, the peripheral circuit 70 may also include additional circuits not shown in FIG. 1E.
  • the memory cell array 80 can be connected to the page buffer 90 through the bit line, and the page buffer 90 is connected to the VFC circuit 100.
  • the memory cell array may include multiple memory cells (Cell), and after the programming operation, the page buffer outputs a current signal to the VFC circuit.
  • Cell multiple memory cells
  • the page buffer of the bit line branch corresponding to the memory cell will output the corresponding current signal, and the output current signals on multiple bit lines are accumulated, which is the detection signal obtained by verifying the memory.
  • an embodiment of the present application provides a memory, which includes a memory cell array 80 and a peripheral circuit, wherein the peripheral circuit includes at least a VFC circuit 100, wherein the VFC circuit specifically includes:
  • the trigger circuit 120 includes a reference signal output circuit 121 and an error bit signal output circuit 122;
  • the error bit signal output circuit 122 is configured to: generate an error bit signal Vero according to a detection signal obtained by verifying the memory;
  • the reference signal output circuit 121 is configured to: output at least one reference signal Inp;
  • the comparator 130 is coupled to the trigger circuit 120; the comparator 130 is configured as follows:
  • the error bit signal Vero is compared with the plurality of reference signals Inp in sequence to obtain a verification result.
  • the VFC circuit 100 may further include a reference circuit 110.
  • the reference circuit may be configured to receive an external input signal, such as a clock signal, an enable signal, or a voltage or current signal, to enable the VFC circuit to start the verification error bit count.
  • the reference circuit 110 is connected to the trigger circuit 120 and is configured to output a control signal to the trigger circuit 120 based on an external input signal; the control signal is configured to enable the trigger circuit.
  • the reference circuit 110 may include a comparator 111, which is configured to receive an external input signal Vref and output an enable signal to the trigger circuit 120 according to the magnitude thereof, and the signal is used to turn on some control switches in the trigger circuit 120, thereby enabling the trigger circuit 120.
  • the output signal of the reference circuit 110 is configured to provide a gate control signal for the P1, P2, and P3 transistors.
  • P1, P2, and P3 can be turned on.
  • the paths where P1 and P2 are located are turned on, generating a first control signal e1 and a second control signal e2.
  • the first control signal e1 is configured to enable the reference signal output circuit 121 to output a plurality of the reference signals Inp;
  • the second control signal e2 is configured to enable the error bit signal output circuit 122 to receive the detection signal Iero.
  • the PB node can receive the detection signal corresponding to the PB side, thereby transmitting the voltage value Vero corresponding to the detection signal Iero to the trigger circuit 120 as one of the signals to be compared.
  • the first control signal e1 enables the reference signal output circuit 121 to start outputting the first reference signal Inp(1), and then can continue to output different reference signals Inp(i) in sequence until the comparison is completed.
  • the reference signal output circuit 121 of the trigger circuit 120 may include multiple branches 123 configured to generate corresponding multiple reference signals Inp. As shown in FIG2B , each branch can provide a signal i when turned on, and the total signal obtained by connecting multiple branches in parallel is the above-mentioned reference signal Inp.
  • the control signals E1, E2, ..., Ei, etc. of the switches on the branches are configured to turn on or off the multiple branches 123 in the trigger circuit 120, which can change the total resistance, so as to generate multiple reference signals Inp of different sizes. Exemplarily, if the multiple branches 123 in the trigger circuit 120 are turned on, the total resistance becomes smaller, the total current output by the multiple branches 123 in parallel is larger, and the corresponding reference signal Inp has a smaller input voltage value for the comparator.
  • the trigger circuit 120 can also be coupled to the memory cell array through other circuits. As shown in FIG. 2B , the trigger circuit 120 is connected to the page buffer through the PB node (only the PB node is shown in FIG. 2B , and the page buffer is not shown), and the page buffer is then connected to the memory cell array. After the data stored in the memory cell array is verified, the corresponding detection signal Iero can be obtained through the page buffer. The detection signal Iero can carry error information of the verification data. Therefore, the trigger circuit 120 can receive the detection signal and generate a corresponding error bit signal Vero (i.e., the voltage of the PB node).
  • Vero i.e., the voltage of the PB node
  • the error bit signal Vero is applied to the control electrode of the power supply end PMOS switch connected to each branch 123 in the trigger circuit 120, and is configured to provide current to these branches 123 by turning on the path of the power supply end, and at the same time serves as the input signal of the comparator 130, i.e., the signal to be compared.
  • the size range of the error bit signal Vero can be obtained, and the range can reflect the range of the number of error bits, and then the verification result of the error bit count can be determined using the comparison result.
  • the comparator 130 can be coupled to the above-mentioned trigger circuit 120.
  • the comparator 130 here refers to a circuit element that compares two voltage signals (error bit signal Vero and reference signal Inp) to determine whether the two voltage signals are equal or have a magnitude relationship.
  • the two inputs of the comparator 130 are analog signals, and the output is a binary signal "0" or "1" (represented by a low level and a high level).
  • the comparison result of the comparator can be represented by the symbol Ver_out ⁇ 13:0>.
  • FIG2B is a schematic diagram of a VFC circuit according to an embodiment of the present application, wherein the trigger circuit 120 is configured to generate a plurality of reference signals Inp, which can be provided to the same comparator 130 in sequence in a time-sharing manner, and the comparator 130 compares the error bit signal Vero with the plurality of reference signals Inp in sequence until the range of the error bit signal Vero is determined.
  • the trigger circuit 120 is configured to generate a plurality of reference signals Inp, which can be provided to the same comparator 130 in sequence in a time-sharing manner, and the comparator 130 compares the error bit signal Vero with the plurality of reference signals Inp in sequence until the range of the error bit signal Vero is determined.
  • the error bit signal Vero can be compared with the first reference signal Inp first. If the comparator outputs a binary signal "1", it means that the error bit signal is greater than the first reference signal. Then the error bit signal Vero is compared with the second reference signal (the second reference signal is greater than the first reference signal) until the output of the comparator 130 is a binary signal "0". The voltage range of the error bit signal Vero can be determined, thereby obtaining a verification result. Therefore, the embodiment of the present application can reuse comparators for different reference signals Inp, thereby reducing the occupied area of redundant circuit elements, saving memory space, and reducing power consumption and improving memory reliability.
  • the trigger circuit of the VFC circuit (the portion in the dotted box) includes a plurality of branches connected to the PB side and a plurality of branches outputting reference signals Inp arranged in parallel (the three-dimensional structure shown in FIG3 ), and each branch is connected to a comparator.
  • Each group of branches is controlled by a group of controlled switches, and when turned on, a reference signal Inp is output to compare with the error bit signal Vero, and different comparators are required.
  • the error bit signal and the first reference signal are input into a first comparator.
  • the output comparison result is a high level, it represents a binary signal "1", and the error bit signal and the second reference signal need to be input into a second comparator different from the first comparator.
  • the trigger circuit in FIG3 uses a separate comparator for each comparison process, which will occupy a larger area; on the other hand, in the second When the comparator is turned on, the first comparator remains on, which causes excess power consumption and increases the probability of device damage.
  • the reference signal output circuit 121 includes:
  • a plurality of parallel branches 123 each branch comprising at least one controlled switch 410; the plurality of parallel branches 123 are respectively configured to output the plurality of reference signals.
  • the trigger circuit 120 can control the opening of multiple branches 123 respectively through multiple controlled switches 410, and the reference signal Inp can be the main current after the multiple branches are connected in parallel. Therefore, the total current in parallel is numerically equal to the sum of the currents of the multiple branches, and different total current values correspond to different voltage values of the reference signal Inp.
  • the controlled switches can be turned on in sequence so that the number of branches turned on increases in sequence, thereby obtaining a plurality of different reference signals Inp. It is understandable that if more controlled switches are turned on, the number of branches connected to the trigger circuit will be more, so that the current on the main road is larger and the voltage value of the output reference signal is smaller; vice versa, if fewer controlled switches are turned on, the number of branches connected to the trigger circuit will be smaller, so that the current on the main road is smaller and the voltage value of the output reference signal is larger.
  • the first controlled switch corresponds to the opening of the first branch
  • the second controlled switch corresponds to the opening of the second branch
  • each controlled switch corresponds to each branch
  • the number of controlled switches and branches needs to be determined according to actual production requirements.
  • the above-mentioned controlled switches include but are not limited to three-terminal devices such as triodes and field effect transistors or other circuit elements that can realize switching functions.
  • the controlled switches on the branches 123 may have different resistance values, so that different reference signals may be provided when turned on. Therefore, in this case, different branches 123 may be turned on in sequence, and only one branch 123 may be turned on each time.
  • each branch may also have another controlled switch, and the controlled switch of each branch is controlled by the e1 signal as shown in FIG. 4 .
  • the e1 signal may be obtained by triggering the transistor P1 to turn on by the reference circuit 110 involved in the above embodiment, thereby achieving the function of enabling the trigger circuit. use.
  • the embodiment of the present application can control the opening or closing of the controlled switch according to the control signal of the reference circuit, and one controlled switch corresponds to the opening of one branch, so that the value of the reference signal can be accurately adjusted, thereby improving the reliability of the comparison result.
  • the plurality of controlled switches 410 are configured such that: the controlled switch 410 receiving the first enable signal Ei is switched to a conducting state, so that the corresponding branch 123 is turned on and provides the reference signal Inp.
  • first enable signals E1, E2...Ei can be received to control the opening or closing of the controlled switch 410.
  • multiple first enable signals E1, E2...Ei can be sequentially input to the controlled switch 410, that is, the above-mentioned controlled switch 410 can be triggered sequentially with a certain delay.
  • the controlled switch 410 can be a transistor, and the first enable signals E1, E2...Ei are voltage signals applied to the control electrode of the transistor.
  • the first enable signal can be a high level, and when the corresponding branch receives the above-mentioned high-level signal, the controlled switch on the branch can be turned on.
  • the first enable signals E1, E2, ... Ei may be the result of the comparison performed by the previous branch 123 fed back to the current branch 123 to enable the next branch 123, thereby achieving sequential comparison.
  • the comparator 130 includes at least two; the reference signal output circuit 121 includes at least two sub-output circuits; each of the sub-output circuits includes at least one branch 123, and one sub-output circuit is connected to one comparator 130, wherein the number of the sub-output circuits is the same as the number of the comparators 130.
  • the error bit signal Vero can be compared with multiple different reference signals Inp in time-sharing order, so that only one comparator is needed.
  • multiple comparators 130 can also be used.
  • the multiple branches in the above trigger circuit 120 can be grouped, and each group shares one comparator 130.
  • the reference signal Inp to be compared can be divided into two groups (low bit group and high bit group) or three groups (low bit group, middle bit group and high bit group) through branches. The number of groups here can be determined according to the accuracy of the actual verification error bit count.
  • the multiple branches of the trigger circuit 120 can be divided into two sub-output circuits, including: a low bit group 510 and a high bit group 520.
  • the low bit group 510 can represent the error bit as a range of 1 to 9 bits
  • the high bit group 520 can represent the error bit as a range of 10 to 25 bits.
  • the reference signals provided by the two groups of branches are different.
  • the reference signal Inp and the error bit signal Vero output by the two groups of branches are respectively input into different comparators 130, so that corresponding comparison parameters can be obtained respectively.
  • the upper limit of the number of bits can be determined according to the number of storage cells in the storage cell array that have not passed the programming verification.
  • the above-mentioned bit refers to the smallest storage unit of the memory, that is, the data stored in a storage unit in the storage unit array.
  • the programming state of the storage unit can be binary information "0" or "1", wherein the binary information "1" can indicate that the storage unit has not been programmed or programming failed (failed to pass programming verification), and the binary information "0" can indicate that the storage unit has been programmed and verified.
  • the number of storage units that failed programming will be locked in the page buffer in the form of the above-mentioned number of bits, and then counted by the VFC circuit in the form of electrical signals.
  • the page buffer input VFC circuit detection signal Iero can be converted into an error bit signal Vero via the VFC circuit and compared with multiple reference signals Inp output by the internal trigger circuit of the VFC circuit in turn. Since different numbers of conductive branches can provide different multiple reference signals Inp, the above-mentioned grouping of controlled switches based on the number of bits can intuitively determine the range of the number of error bits.
  • each sub-output circuit reuses the same comparator.
  • the controlled switches can be divided into a first group (low bit group) and a second group (high bit group).
  • the first group can use the first comparator to compare whether the error bit is within the low bit range
  • the second group can use the second comparator to compare whether the error bit is within the high bit range.
  • the low bit range and high bit range are The error range can be changed according to the number of sub-output circuits.
  • the corresponding error bit range of the sub-output circuits is smaller, the determined error bit number is more accurate, and more comparators need to be set; if the number of groups is smaller, the corresponding error bit range is larger, the determined error bit number is wider, and fewer comparators need to be set.
  • the embodiment of the present application can set up multiple sub-output circuits, and each branch in each sub-output circuit reuses the corresponding comparator to compare the error bit signal and multiple reference signals in sequence; on the other hand, the comparators can compare each other independently each time, which can not only reduce the occupied area of circuit elements and save space, but also improve the comparison efficiency and the reliability of the VFC circuit.
  • the input terminal of the comparator is connected to the trigger circuit and is configured as follows:
  • the comparison parameter indicates that the error bit signal is less than or equal to the reference signal, the comparison is stopped and the verification result is output.
  • the comparator may have at least two input terminals and one output terminal, wherein the two input terminals are configured to respectively receive an error bit signal generated by a trigger circuit and an output reference signal, and one output terminal is configured to output the result after comparison, i.e., the comparison parameter.
  • the comparison parameter here may be a binary signal "0" or "1".
  • a binary signal "1" is output, indicating that the number of storage cells that have not passed the programming verification is greater than the number of bits corresponding to the current reference signal, and the next round of comparison needs to be continued; if the error bit signal is less than or equal to the compared reference signal, a binary signal "0" is output, indicating that the number of storage cells that have not passed the programming verification is less than or equal to the number of bits corresponding to the current reference signal or is within the range of the number of bits corresponding to the current reference signal, so that the comparison can be stopped to obtain the corresponding verification result.
  • the comparator in the embodiment of the present application can sequentially compare the error bit signal and multiple reference signals, thereby determining step by step whether the number of storage cells that have not passed the programming verification is within the bit number range corresponding to the current reference signal. This can improve the efficiency and accuracy of the comparison and increase the reliability of the VFC current.
  • the VFC circuit 100 in the memory peripheral circuit further includes:
  • the delay circuit 140 is coupled to the comparator 130; the delay circuit 140 is configured as follows:
  • the multiple comparison parameters output by the comparator are delayed respectively, and the delayed comparison parameters are output.
  • the comparator can be configured to compare the error bit signal and multiple reference signals in sequence, thereby achieving multiplexing, so that the same comparator 130 will output multiple comparison parameters.
  • the embodiment of the present application can couple the comparator 130 with the delay circuit 140, so that the distinction can be made by applying the corresponding delay. It should be noted that, as shown in Figure 6B, the above-mentioned delay circuit 140 can receive the second enable signal en0...en6 to output the corresponding delay signal a0...a6 before the comparator 130 outputs the comparison parameter.
  • the second enable signal here can be a high-level signal, configured to trigger the delay circuit 140 to output the corresponding delay signal; the delay signal here can be a high-level signal within a time ⁇ t.
  • the second enable signal en0...en6 can be provided to the delay circuit 140 in sequence according to the clock signal or other external signals in a preset order.
  • the delay circuit 140 involved in the embodiment of the present application may have multiple delay branches, where the multiple branches correspond to the multiple comparison parameters, that is, they are configured to delay the comparison parameters after each reference signal is compared with the error bit signal.
  • the multiple delay branches of the delay circuit 140 can reuse a delay module, which can output corresponding delay signals corresponding to the second enable signals en0...en6 of each branch, thereby reducing the power consumption of redundant delay modules. It should be noted that Other technical solutions such as setting a delay module for each delay branch, or setting a delay module for multiple delay branches are also within the scope of protection required by the embodiments of the present application.
  • the delay circuit 140 may receive the second enable signal en0, thereby triggering the corresponding delay branch to generate the first delay signal a0, and the first comparison parameter out0 may be delayed through an AND gate 610, and finally the first delay comparison parameter a0_1 may be output.
  • the multiple output ends of the delay unit 140 may be respectively connected to the multiple AND gates 610. Since the multiple output ends of the delay unit 140 output the delay signal in time-sharing, the delay comparison parameters a0_1 to ax_1 output by the multiple AND gates 610 are also output in time-sharing. In this way, the same comparator may be used to process different reference signals respectively, and the comparison results corresponding to each reference signal may be obtained in time-sharing, thereby realizing the multiplexing of the comparator.
  • the above-mentioned delay signal is at a high level. If the comparison parameter is at a high level, the delayed comparison parameter after passing through the AND gate is also at a high level. Conversely, if the comparison parameter is at a low level, the delayed comparison parameter after passing through the AND gate is also at a low level. Therefore, the above-mentioned delay circuit does not change the binary information corresponding to the comparison parameter output by the comparator, and can distinguish multiple comparison parameters.
  • the delay circuit used in the embodiment of the present application can effectively distinguish the comparison parameters of the comparator, thereby improving the accuracy of the verification error bit count and enhancing product reliability.
  • the VFC circuit 100 further includes:
  • the latch circuit 150 includes a plurality of latches, coupled to the delay circuit 140; the latches are configured to store the delay comparison parameters; wherein the number of the latches is the same as the number of the reference signals.
  • the multiplexed comparator generates multiple comparison parameters, and each comparison parameter is relatively independent and needs to be delayed by a delay circuit and the number of error bits is calculated to obtain a verification result. Therefore, a latch circuit can be coupled to the above delay circuit to latch multiple delayed comparison parameters and then configure them for subsequent calculations.
  • the latch here can store binary information "0" Or "1" is converted into a level signal latch and maintains its level state.
  • Each delay comparison parameter can correspond to a latch, thereby forming the above latch circuit. Therefore, the number of latches can be the same as the number of reference signals, so that the delay comparison parameters obtained after each comparison can be stored in separate latches.
  • the latch circuit is further coupled to the trigger circuit, wherein the latch is configured to:
  • a feedback signal is output according to the latch signal; wherein the feedback signal is configured to trigger the trigger circuit to switch the reference signal to be compared.
  • FIG. 7B it is a schematic diagram of the structure of a latch 151 in the latch circuit 150.
  • the latch 151 here may have a field effect transistor 710 and a latch unit 720, wherein the control end of the field effect transistor 710 receives the delay comparison parameter, such as ax_1, that is, the control end is connected to the output end of the AND gate 610, so that it can be configured to turn on the latch unit 720 to realize the latching of data.
  • the delay comparison parameter such as ax_1
  • the delay comparison parameter is binary information "1"
  • the binary information can be converted into a level signal (e.g., a high level) inside the latch, and latched as an input of the latch unit 720.
  • the delay comparison parameter is binary information "1”, that is, a high level voltage signal
  • the field effect transistor 710 is turned on, the ground voltage reaches the latch unit 720 through the field effect transistor 710, and the latch unit 720 performs an inversion process on the ground voltage signal, and the obtained latch signal b_0 is a high level voltage signal, thereby realizing latching.
  • the structure of the latch unit 720 can be as shown in FIG7C .
  • the control terminal Y of the latch unit 720 is "1".
  • the delay comparison parameter is input into the latch through the above-mentioned turned-on field effect transistor 710, it needs to be latched into the corresponding latch unit 720.
  • the control terminal Y of the latch unit changes from "1” to "0”, and the high-level signal converted from the binary information "1" is input from the other input terminal A of the latch unit, thereby latching the signal.
  • the latch can output a corresponding feedback signal according to the latched level information
  • the feedback signal here can be a level signal, a clock signal or other feedback signal.
  • the latched information is a high level, it means that the delay comparison parameter input to the latch is a binary information "1", which further indicates that the error bit circuit is greater than the current reference signal, that is, the number of error bits is not within the range of the number of bits currently compared.
  • the embodiment of the present application can latch the above-mentioned delay comparison parameter through a latch circuit, and output a feedback signal to the trigger circuit, which is configured to determine whether to perform the next round of comparison according to the latch information.
  • the delay comparison parameter can be effectively saved, data loss can be reduced, and the feedback signal is added to change the opening condition of the controlled switch in the trigger circuit, thereby increasing the reliability of the VFC circuit.
  • the VFC circuit 100 in the memory further includes:
  • the code conversion circuit 160 is coupled to the latch circuit 150 ; the code conversion circuit 160 is configured to: convert the latch signal into a binary code; the binary code is configured to calculate and obtain the verification result.
  • the latch circuit can be coupled to a code conversion circuit to convert the level signal corresponding to the latch information into a more recognizable binary code.
  • the high level can be converted into binary code "1”
  • the low level can be converted into binary code "0”.
  • converting the electrical signal into a numerical signal can express the verification result more conveniently, concisely and intuitively, thereby improving the reliability of the VFC current.
  • the VFC circuit 100 in the memory further includes:
  • the accumulator 170 is coupled to the code conversion circuit 160; the accumulator 170 is configured as follows:
  • the plurality of binary codes obtained from the code conversion circuit are accumulated to obtain the verification result of the error bit count.
  • the above binary codes can also be accumulated to obtain the number of error bits of the entire storage cell array. Therefore, the above code conversion circuit can be coupled to an accumulator, and the accumulator here can be a register. The accumulator can be initialized before calculating the verification result, and the multiple binary codes obtained by the code conversion circuit can be accumulated to obtain the sum of the number of error bits after multiple comparisons of the VFC circuit, and finally obtain the verification result of the error bit count.
  • the latch circuit 150 is further configured to:
  • a reset signal is received to reset the latch signal.
  • each latch 151 in the above-mentioned memory circuit may further include a field effect transistor 730 configured to receive a reset signal, and the input terminals of these field effect transistors 730 may be the same circuit node, that is, when the latch circuit receives a reset signal, all latches in the circuit will also receive the reset signal accordingly, and reset the latch information in the latch unit.
  • a field effect transistor 730 configured to receive a reset signal
  • the input terminals of these field effect transistors 730 may be the same circuit node, that is, when the latch circuit receives a reset signal, all latches in the circuit will also receive the reset signal accordingly, and reset the latch information in the latch unit.
  • one latch latches a high level
  • one latch latches a low level After receiving the reset signal, all latches will be reset to a low level, and the control terminal in the latch unit will be reset to "1".
  • the embodiment of the present application can input a reset signal to the latch circuit after the reference circuit outputs a control signal to the trigger circuit, so that the latch is kept open before the latch delay comparison parameter is latched.
  • the triggering mode of the VFC circuit is changed, and the accuracy of the latch information can be increased, thereby improving the The accuracy of the feedback signal is improved, thereby improving the reliability of the memory.
  • an embodiment of the present application further provides a control method for a verification error bit counting circuit of a semiconductor memory, comprising:
  • Step S10 outputting at least one reference signal
  • Step S20 generating an error bit signal according to a detection signal obtained by verifying the memory
  • Step S30 Compare the error bit signal with the multiple reference signals in sequence to obtain a verification result.
  • the reference circuit can be configured to receive an external control signal, such as a clock signal or an enable signal, so that the VFC circuit starts to verify the error bit count.
  • the reference circuit can convert the external signal into an internal control signal and output it, and is configured to control the corresponding unit in the VFC circuit to output multiple reference signals.
  • the multiple reference signals here can be controlled by multiple controlled switches on the trigger circuit, and the controlled switches can be turned on or off according to the control signal of the reference circuit. Therefore, if more controlled switches are turned on, the more branches are connected to the trigger circuit, so that the reference signal on the main road is larger; if fewer controlled switches are turned on, the fewer branches are connected to the trigger circuit, so that the reference signal on the main road is smaller.
  • the VFC circuit After the VFC circuit is started, it can receive a detection signal and generate an error bit signal according to a control signal output by a reference circuit.
  • the error bit signal here is a current corresponding to the number of error bits received in the page buffer, and is configured to indicate the number of memory cells in the memory cell array that have not passed programming verification.
  • the memory cell array can be coupled to the page buffer through a bit line. If the memory cell fails to pass programming verification, the page buffer of the bit line branch corresponding to the memory cell will output a corresponding current signal.
  • the VFC circuit can obtain the number of memory cells that have not passed programming verification and output the number by counting the current signal, thereby realizing the counting of error bits during the verification process. It should be noted that the above-mentioned steps S10 and S20 are two independent steps, which can be implemented sequentially or synchronously in actual operation.
  • the comparator in the VFC circuit can sequentially compare the error bit signal and multiple It should be noted that, in the embodiment of the present application, the comparison can be performed sequentially to realize the reuse of the comparator, thereby reducing the occupied area of the circuit elements, saving space, and at the same time reducing power consumption and improving the reliability of the memory.
  • control method further includes:
  • a plurality of first enable signals are received in sequence; wherein the controlled switch receiving the first enable signal is switched to the on state; the branch connected to the controlled switch in the on state is turned on and configured to provide the reference signal.
  • the VFC circuit can receive multiple first enable signals according to the control signal of the reference circuit, thereby controlling the opening or closing of the controlled switch.
  • multiple enable signals can be input to the controlled switch in sequence, that is, the above-mentioned controlled switch can be triggered in sequence with a certain delay.
  • the enable signal here can be added as an electrical signal to the branch corresponding to the controlled switch, thereby controlling the opening of the controlled switch.
  • the first enable signal can be a high level, and when the corresponding branch receives the above-mentioned high level signal, the controlled switch on the branch can be turned on.
  • the sequentially comparing the error bit circuit and the plurality of reference signals to obtain a verification result includes:
  • the latch signal indicates that the error bit signal is greater than the reference signal, comparing the error bit signal with a next reference signal until the delay comparison parameter indicates that the error bit signal is less than or equal to the reference signal;
  • a plurality of the binary codes are accumulated to obtain the verification result of the error bit count.
  • the above error codes can be compared in sequence by the comparator in the VFC circuit. Specifically, after comparing the error bit signal with a reference signal, a corresponding comparison parameter can be output, where the comparison parameter can be a binary signal "0" or "1".
  • the VFC circuit in the embodiment of the present application may include a delay circuit configured to output a preset delay signal, configured to delay the multiple comparison parameters output by the above comparator, so as to distinguish the multiple comparison parameters output by the same comparator.
  • the delay signal here can be a high-level signal within a time ⁇ t.
  • the delayed comparison parameter after passing through the AND gate is also a high level; conversely, if the comparison parameter is a low level, the delayed comparison parameter after passing through the AND gate is also a low level, so that the above delay circuit does not change the binary information corresponding to the comparison parameter output by the comparator.
  • each delay comparison parameter can correspond to a latch, thereby forming a latch circuit inside the VFC circuit.
  • the comparator if the error bit signal is greater than the compared reference signal, the comparator outputs a binary signal "1" and the latch latches the corresponding high level, thereby indicating that the number of storage cells that have not passed the programming verification is greater than the number of bits corresponding to the current reference signal, and the next round of comparison needs to be continued; if the error bit signal is less than or equal to the compared reference signal, the comparator outputs a binary signal "0" and the latch latches the corresponding low level, thereby indicating that the number of storage cells that have not passed the programming verification is less than or equal to the number of bits corresponding to the current reference signal or is within the range of the number of bits corresponding to the current reference signal, so that the comparison can be stopped and the corresponding verification result can be obtained through subsequent calculations.
  • the level signal latched by the latch can be converted into a more recognizable binary code through the code conversion circuit in the VFC circuit.
  • the high level can be converted into the binary code "1”
  • the low level can be converted into the binary code "0”.
  • the accumulator is then initialized before calculating the verification result, and the multiple binary codes obtained by the code conversion circuit are accumulated to obtain the VFC circuit. The sum of the number of error bits after multiple comparisons is finally used to obtain the verification result of the error bit count.
  • comparing the error bit signal with a next reference signal comprises:
  • the latch outputs a feedback signal according to the latch signal
  • the first enable signal is output to the next controlled switch; wherein the controlled switch receiving the first enable signal is switched to an on state, and the trigger circuit generates a next reference signal and compares it with the error bit signal.
  • the latched information is at a high level, it indicates that the delay comparison parameter input to the latch is at a high level, further indicating that the error bit circuit is greater than the current reference signal, that is, the number of error bits is not within the range of the number of bits currently compared. Therefore, it is necessary to output high-level feedback information according to the latched high-level information, and input it into the trigger circuit coupled to the above-mentioned latch circuit, so that the trigger circuit generates a new first enable signal, configured to turn on the corresponding controlled switch, thereby triggering a new reference signal, configured to perform a new round of comparison with the error bit signal.
  • a control timing diagram of a memory provided in an embodiment of the present application is provided.
  • the reference circuit can receive an external control signal En_ref (a total enable signal, not shown in the figure) to start the VFC circuit.
  • En_ref an external control signal
  • a reset signal Rst_latch (not shown in the figure) needs to be applied to the latch circuit so that the current latch maintains a low level and restores the latched state.
  • the control signal output by the reference circuit turns on the PMOS tubes P1, P2, and P3 in the trigger circuit 120 shown in FIG. 4.
  • enable signals e1 and e2 are generated.
  • the trigger circuit 120 generates the corresponding error bit signal Vero and reference signal Inp at time T2.
  • the controlled switch on the trigger circuit branch 123 receives the corresponding first enable signal E1 at time T3, and the delay circuit 140 shown in FIG6C receives the corresponding second enable signal en0.
  • the first comparison parameter output by the comparator 130 is delayed by the preset delay signal a0 output by the delay circuit, and is delayed from time T3 to time T4, and the delayed comparison parameter ax_1 (at this time a0_1) shown in FIG6C is output.
  • the binary information corresponding to the corresponding delayed comparison parameter a0_1 is "1", which is transmitted to the latch 151 shown in FIG7B.
  • the level signal b_0 latched in the corresponding latch 151 is a high level, which is a feedback signal and will be used as the first enable signal E2 of the next branch 123. Therefore, the error bit signal will continue to be compared with the next reference signal.
  • the feedback signal b_0 output by the latch 151 causes the trigger circuit to receive the first enable signal E2 again, thereby turning on the controlled switch of the next branch 123 and outputting the next reference signal Inp.
  • the reference signal Inp at this time has a different voltage value from the reference signal Inp output last time.
  • the delay circuit 140 will also trigger a new second enable signal en1 and output a preset delay signal a1. From this cycle, until the moment T6, the first comparison parameter output by the comparator 130 is the binary information "0", so that the corresponding delay comparison parameter is also "0", and the corresponding latch latches a low level, so that the feedback signal no longer triggers the corresponding enable signal, and the verification ends.
  • the code conversion unit will convert the level information latched in the latch circuit into a binary code, and then input it into the accumulator, so as to obtain the final verification result, that is, the number of storage cells that have not passed the verification in this programming is the bit number range corresponding to the third reference signal.
  • the timing diagram shown in Figure 12 is based on the comparison result obtained after three comparisons. That is, after the third comparison, the latch delay comparison parameter a2_1 obtained is a low level, indicating that the current error bit signal is greater than the reference signal. At this time, the level signal b_2 in the latch 151 is a low level, and the first enable signal E4 that feeds it back to the next branch 123 cannot turn on the next branch 123, so the subsequent comparison is stopped.
  • the level signals stored in the subsequent latches, such as b_3 to b_12 are also low levels.

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Abstract

本申请实施例提供一种存储器及其控制方法、存储器系统。所述存储器包括存储单元阵列和外围电路；所述外围电路至少包括：触发电路，包括基准信号输出电路和错误位信号输出电路；其中，所述错误位信号输出电路被配置为：根据对存储器进行验证得到的检测信号，产生错误位信号；所述基准信号输出电路被配置为：输出多个基准信号；比较器，与所述触发电路耦接；所述比较器被配置为：比较所述错误位信号和至少一个所述基准信号，输出验证结果。

Description

存储器及其控制方法、存储器系统
相关申请的交叉引用
本申请基于申请号为202211563081.7、申请日为2022年12月7日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体技术领域，涉及但不限于一种存储器及其控制方法、存储器系统。
背景技术
为了克服二维存储器件的限制，业界已经研发并大规模量产了具有三维(3D)结构的存储器件，其通过将存储器单元三维地布置在衬底之上来提高集成密度。在3D NAND存储器的生产制造中，需要对存储单元进行写入验证，以统计写入失败或错误的存储单元的个数，该过程被称为验证错误位计数(Verify Failbit Count，VFC)。执行VFC的电路相应的被称为VFC电路，VFC电路的运行需要消耗3D NAND存储器的功耗且VFC电路占用存储器的空间，为了节省功耗并减少VFC的占用空间，需要对VFC电路进行优化设计。
申请内容
有鉴于此，本申请实施例提供了一种存储器及其控制方法、存储器系统。
第一方面，本申请实施例提供了一种存储器，所述存储器包括存储单 元阵列和外围电路；所述外围电路至少包括：
触发电路，包括基准信号输出电路和错误位信号输出电路；
其中，所述错误位信号输出电路被配置为：根据对存储器进行验证得到的检测信号，产生错误位信号；
所述基准信号输出电路被配置为：输出至少一个基准信号；
比较器，与所述触发电路耦接；所述比较器被配置为：
比较所述错误位信号和至少一个所述基准信号，输出验证结果。
在一些实施例中，所述基准信号输出电路，包括：
多条并联的支路，每条支路包括至少一个受控开关；所述多条并联的支路分别配置为输出至少一个所述基准信号。
在一些实施例中，所述受控开关被配置为：
接收到第一使能信号的所述受控开关切换为导通状态，使对应的所述支路导通并提供所述基准信号。
在一些实施例中，所述比较器包括至少两个；所述基准信号输出电路包括至少两个子输出电路；每个所述子输出电路包括至少一条所述支路，且一个所述子输出电路连接一个所述比较器，其中，所述子输出电路的个数与所述比较器的个数相同。
在一些实施例中，所述比较器的输入端连接所述触发电路，并被配置为：
比较所述错误位信号和一个基准信号，输出比较参数；
如果所述比较参数指示所述错误位信号大于所述基准信号，则继续比较下一个基准信号；
如果所述比较参数指示所述错误位信号小于或等于所述基准信号，则停止比较并输出所述验证结果。
在一些实施例中，所述外围电路中，还包括：
延时电路，与所述比较器耦接；所述延时电路被配置为：
依次接收多个第二使能信号，输出延迟信号；
根据接收到的多个所述延迟信号，分别延迟所述比较器输出的多个所述比较参数，输出延迟比较参数。
在一些实施例中，所述外围电路，还包括：
锁存器电路，包括多个锁存器，与所述延时电路耦接，所述锁存器配置为存储所述延迟比较参数；其中，所述所述锁存器的个数与所述基准信号的个数相同。
在一些实施例中，所述锁存器电路还与所述触发电路耦接，其中所述锁存器被配置为：
将所述延迟比较参数转换为锁存信号，并锁存到对应的所述锁存器中；
根据所述锁存信号，输出反馈信号；其中，所述反馈信号配置为触发所述触发电路切换待比较的所述基准信号。
在一些实施例中，所述存储器还包括：
码制转换电路，与所述锁存器电路耦接；所述码制转换电路被配置为：
将所述锁存信号转换为二进制码；所述二进制码配置为计算得到所述验证结果。
在一些实施例中，所述外围电路还包括：
累加器，与所述码制转换电路耦接；所述累加器被配置为：
累加从所述码制转换电路获得的多个所述二进制码，得到错误位计数的所述验证结果。
在一些实施例中，所述锁存器电路还被配置为：
接收重置信号，重置所述锁存信号。
在一些实施例中，所述外围电路还包括：
参考电路，与所述触发电路连接，并被配置为基于外部输入信号向所 述触发电路输出控制信号；所述控制信号配置为使能所述触发电路。
在一些实施例中，所述控制信号，包括第一控制信号和第二控制信号；其中，所述第一控制信号配置为使能所述基准信号输出电路输出多个所述基准信号；所述第二控制信号配置为使能所述错误位信号输出电路接收所述检测信号。
第二方面，本公开实施例还提供一种存储器的控制方法，所述控制方法应配置为所述存储器的外围电路，包括：
输出至少一个基准信号；
根据对存储器进行验证得到的检测信号，产生错误位信号；
比较所述错误位信号和至少一个所述基准信号，输出验证结果。
在一些实施例中，所述控制方法还包括：
依次接收多个第一使能信号；其中，接收到所述第一使能信号的受控开关切换为导通状态；连接开启状态的所述受控开关的支路导通并配置为提供所述基准信号。
在一些实施例中，所述比较所述错误位信号和所述多个基准信号，输出验证结果，包括：
比较所述错误位信号和一个基准信号，输出比较参数；
根据与所述比较参数对应的延迟信号，延迟所述比较参数，输出延迟比较参数；
将所述延迟比较参数转换为锁存信号，锁存到对应的锁存器中；
若所述锁存信号指示所述错误位信号大于所述基准信号，则比较所述错误位信号和下一个基准信号，直至所述延迟比较参数指示所述错误位信号小于或等于所述基准信号；
将多个锁存器中锁存的所述锁存信号分别转换为二进制码；
累加多个所述二进制码，得到配置为表示错误位计数的所述验证结果 并输出所述验证结果。
在一些实施例中，所述若所述锁存信号指示所述错误位信号大于所述基准信号，则比较所述错误位信号和下一个基准信号，包括：
所述锁存器根据所述锁存信号，输出反馈信号；
若所述反馈信号指示所述错误位信号大于所述基准信号，则向下一个所述受控开关输出的所述第一使能信号，其中，接收到所述第一使能信号的所述受控开关切换为开启状态，且触发电路产生下一个基准信号并与所述错误位信号进行比较。
在一些实施例中，所述方法还包括：
接收重置信号，重置所述锁存信号。
在一些实施例中，所述方法还包括：
基于外部输入信号，输出控制信号；其中，所述控制信号包括：配置为使能输出多个所述基准信号的第一控制信号和配置为使能接收所述检测信号的第二控制信号。
第三方面，本公开实施例提供一种存储器系统，包括：
存储器控制器，以及如上述任一实施例所述的存储器。
本申请实施例提供的存储器，利用可复用的比较器耦接触发电路，并依次比较触发电路产生的错误位信号和输出的多个基准信号。
附图说明
图1A为本申请实施例提供的一种示例性系统的结构示意图；
图1B为本申请实施例提供的一种存储器卡的结构示意图；
图1C为本申请实施例提供的一种固态驱动器(SSD)的结构示意图；
图1D和图1E为本申请实施例提供的一种包括存储单元阵列和外围电路的存储器的结构示意图；
图1F为本申请实施例提供的一种包括VFC电路的存储器的结构示意 图；
图2A至2C为本申请实施例提供的一种VFC电路的结构示意图；
图3为本申请实施例提供的一种触发电路与比较器连接的结构示意图；
图4为本申请实施例提供的一种受控开关的结构示意图；
图5为本申请实施例提供的一种多组受控开关的结构示意图；
图6A和图6B为本申请实施例提供的一种延时电路的结构示意图；
图6C为本申请实施例提供的一种输入延迟比较参数的结构示意图；
图7A至图7C为本申请实施例提供的一种锁存器电路的结构示意图；
图8为本申请实施例提供的一种码制转换电路的结构示意图；
图9为本申请实施例提供的一种累加器的结构示意图；
图10为本申请实施例提供的一种锁存器的结构示意图；
图11为本申请实施例提供的一种VFC电路的控制方法步骤流程图；
图12为本申请实施例提供的一种VFC电路的时序图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
如图1A所示，本申请实施例示出了一种示例性系统10，该示例性系统10可以包括主机20和存储系统30。其中，示例性系统10可以包括但不 限于移动电话、台式计算机、膝上型计算机、平板计算机、车辆计算机、游戏控制台、打印机、定位设备、可穿戴电子设备、智能传感器、虚拟现实(VR)设备、增强现实(AR)设备或者其中具有存储器34的任何其他合适的电子设备；主机20可以是电子设备的处理器(例如，中央处理单元(CPU))或者片上系统(SoC)(例如，应用处理器(AP))。
在本申请实施例中，主机20可以被配置为将数据发送到存储系统30或者从存储系统30接收数据。这里，存储系统30可以包括控制器32和一个或多个存储器34。其中，存储器34可以包括但不限于NAND闪存(NAND Flash Memory)、垂直NAND闪存(Vertical NAND Flash Memory)、NOR闪存(NOR Flash Memory)、动态随机存储器(Dynamic Random Access Memory，DRAM)、铁电随机存储器(Ferroelectric Random Access Memory，FRAM)、磁性随机存储器(Magnetoresistive Random Access Memory，MRAM)、相变随机存储器(Phase Change Random Access Memory，PCRAM)、阻变随机存储器(Resistive Random Access Memory，RRAM)、纳米随机存储器(Nano Random Access Memory，NRAM)等。
另一方面，控制器32可以耦合到存储器34和主机20，且配置为控制存储器34。示例性地，控制器可以被设计为配置为在低占空比环境中操作，如安全数字(SD)卡、紧凑型闪存(CF)卡、通用串行总线(USB)闪存驱动器或者配置为在诸如个人计算器、数字相机、移动电话等电子设备中使用的其他介质。在一些实施例中，控制器还可以被设计为配置为在高占空比环境SSD或嵌入式多媒体卡(eMMC)中操作，SSD或eMMC用作诸如智能电话、平板计算机、膝上型计算机等移动设备的数据储存器以及企业存储阵列。进一步地，控制器可以管理存储器中的数据，并且与主机通信。控制器可以被配置为控制存储器读取、擦除和编程等操作；还可以被配置为管理关于存储在或要存储在存储器中的数据的各种功能，包括但不 限于坏块管理、垃圾收集、逻辑到物理地址转换、损耗均衡等；还可以被配置为处理关于从存储器读取的或者被写入到存储器中的数据的纠错码(ECC)。此外，控制器还可以执行任何其他合适的功能，例如格式化存储器，或者根据特定通信协议与外部设备(例如，图1A中主机20)通信。示例性地，控制器可以通过各种接口协议中的至少一种与外部设备通信，接口协议例如USB协议、MMC协议、外围部件互连(PCI)协议、PCI高速(PCI-E)协议、高级技术附件(ATA)协议、串行ATA协议、并行ATA协议、小型计算机小型接口(SCSI)协议、增强型小型磁盘接口(ESDI)协议、集成驱动电子设备(IDE)协议、Firewire协议等。
在本申请实施例中，控制器和一个或多个存储器可以集成到各种类型的存储设备中，例如，包括在相同封装(例如，通用闪存存储(UFS)封装或eMMC封装)中。也就是说，存储系统可以实施并且封装到不同类型的终端电子产品中。如图1B所示，控制器32和单个存储器34可以集成到存储器卡40中。存储器卡40可以包括PC卡(PCMCIA，个人计算机存储器卡国际协会)、CF卡、智能媒体(SM)卡、存储器棒、多媒体卡(MMC、RS-MMC、MMCmicro)、SD卡(SD、miniSD、microSD、SDHC)、UFS等。存储器卡40还可以包括将存储器卡40与主机(例如，图1A中的主机20)耦合的存储器卡连接器42。在如图1C中所示的另一实施例中，控制器32和多个存储器34可以集成到SSD 50中。SSD 50还可以包括将SSD 50与主机(例如，图1A中的主机20)耦合的SSD连接器52。在一些实施方式中，SSD 50的存储容量和/或操作速度大于存储器卡40的存储容量和/或操作速度。
需要说明的是，本申请实施例涉及的存储器可以是半导体存储器，是用半导体集成电路工艺制成的存储数据信息的固态电子器件。示例性地，图1D为本申请实施例中一种可选的存储器60的示意图。其中，存储器60 可以是图1A至图1C中的存储器34。如图1D所示，存储器60可以由存储单元阵列62和耦合到存储单元阵列62的外围电路64等组成。这里，存储单元阵列可以是NAND闪存存储单元阵列，其中，存储单元以NAND存储串66阵列的形式提供，每个NAND存储串66在衬底(未示出)上方垂直地延伸。在一些实施例中，每个NAND存储串66可以包括串联耦合并且垂直地堆叠的多个存储单元。其中，每个存储单元以保持连续模拟值，例如，电压或电荷，其取决于在存储单元区域内捕获的电子的数量。另外，上述存储单元阵列62中的每个存储单元可以是包括浮栅晶体管的浮栅类型的存储单元，或者是包括电荷捕获晶体管的电荷捕获类型的存储单元。
在本申请实施例中，上述存储单元可以是具有两种可能的存储状态并且因此可以存储一位数据的单层存储单元(Single Level Cell，SLC)。例如，第一存储状态“0”可以对应于第一电压范围，并且第二存储状态“1”可以对应于第二电压范围。在另一些实施例中，每个存储单元是能够在多于四个的存储器状态中存储多于单个位的数据的多层存储单元(Multi Level Cell，MLC)。例如，MLC可以每单元存储两位，每单元存储三位(又被称为三层存储单元(Triple Level Cell，TLC))，或者每单元存储四位(又被称为四层存储单元(Quad Level Cell，QLC))。每个MLC可以被编程为采取可能的标称存储值的范围。示例性地，如果每个MLC存储两位数据，则MLC可以被编程为通过将三个可能的标称存储值中的一个写入到该存储单元而从擦除状态采取三个可能的编程级中的一个。其中，第四标称存储值可以配置为擦除状态。
在本申请实施例中，上述外围电路可以通过位线(Bit Line，BL)、字线(Word Line，WL)、源极(Source Line)、源极选择栅(Source Select Gate，SSG)和漏极选择栅(Drain Select Gate，DSG)耦合到存储单元阵列。这里，外围电路可以包括任何合适的模拟、数字以及混合信号电路，以配置 为通过经由位线、字线、源极、SSG和DSG将电压信号和/或电流信号施加到每个目标存储单元以及从每个目标存储单元感测电压信号和/或电流信号来促进存储单元阵列的操作。此外。外围电路还可以包括使用金属-氧化物-半导体(MOS)技术形成的各种类型的外围电路。示例性地，如图1E所示。外围电路70包括页缓冲器(Page Buffer)/感测放大器71、VFC电路/列解码器/位线驱动器72、行解码器/字线驱动器73、电压发生器74、控制逻辑单元75、寄存器76、接口77和数据总线78。应当理解，上述外围电路70可以与图1D中的外围电路64相同，并且在另一些实施例中，外围电路70还可以包括图1E中未示出的附加电路。
如图1F所示，本申请实施例中示出了一种存储器中的VFC电路结构。其中，存储单元阵列80可以通过位线与页缓冲器90相连接，页缓冲器90和VFC电路100相连接。这里，存储单元阵列可以包括多个存储单元(Cell)，在经过编程操作之后，页缓冲器输出电流信号至VFC电路。示例性地，若存储单元通过了编程验证，则对应的数据通路上没有电流信号，或者电流为0；若存储单元未通过编程验证，则存储单元对应的位线支路的页缓冲器会输出对应的电流信号，多条位线上的输出的电流信号累加起来，则为对存储器进行验证得到的检测信号。
如图2A所示，本申请实施例提供了一种存储器，该存储器包括存储单元阵列80和外围电路，外围电路至少包括VFC电路100，其中，VFC电路具体包括：
触发电路120，包括基准信号输出电路121和错误位信号输出电路122；
其中，所述错误位信号输出电路122被配置为：根据对存储器进行验证得到的检测信号，产生错误位信号Vero；
所述基准信号输出电路121被配置为：输出至少一个基准信号Inp；
比较器130，与所述触发电路120耦接；所述比较器130被配置为：
依次比较所述错误位信号Vero和所述多个基准信号Inp，得到验证结果。
在本申请实施例中，上述VFC电路100还可以包括参考电路110。其中，参考电路可以配置为接收外部输入信号，例如时钟信号、使能信号或电压电流信号，使VFC电路启动验证错误位计数。
在一些实施例中，参考电路110与所述触发电路120连接，并被配置为基于外部输入信号向触发电路120输出控制信号；该控制信号配置为使能触发电路。示例性地，如图2B所示，参考电路110可以包括一个比较器111，该比较器配置为接收外部输入信号Vref，并依据其大小向触发电路120输出使能信号，该信号用以开启触发电路120中的部分控制开关，从而起到使能触发电路120的作用。
示例性地，如图2B所示，参考电路110的输出信号配置为为P1、P2以及P3晶体管提供栅极控制信号。参考电路输出低电平时，可以向打开P1、P2和P3。此时P1和P2所在的通路导通，产生第一控制信号e1和第二控制信号e2。其中，第一控制信号e1配置为使能基准信号输出电路121输出多个所述基准信号Inp；所述第二控制信号e2配置为使能所述错误位信号输出电路122接收所述检测信号Iero。
可以理解的是，第二控制信号e2使其连接的NMOS导通后，PB节点可以接收到PB侧对应的检测信号，从而将检测信号Iero对应的电压值Vero传递至触发电路120作为待比较的信号之一。第一控制信号e1则使能基准信号输出电路121开始输出第一个参考信号Inp(1)，之后可依次继续输出不同的基准信号Inp(i)，直至比较结束。
如图2B所示，触发电路120的基准信号输出电路121可以包括多条支路123，配置为产生对应的多个基准信号Inp。如图2B所示，每个支路开启时可提供信号i，多条支路并联得到的总信号则为上述基准信号Inp。各 支路上的开关的控制信号E1、E2……Ei等配置为触发电路120中多条支路123的开启或者关闭，可以改变总的电阻，使得产生多个不同大小的基准信号Inp。示例性地，若触发电路120中的多条支路123开启，则总的电阻变小，该多条支路123并联起来输出的总电流更大，对应的基准信号Inp对比较器的输入电压值更小。
另一方面，触发电路120还可以通过其他电路与存储单元阵列耦接。如图2B所示，触发电路120通过PB节点与页缓冲器连接(图2B中仅示出PB节点，未示出页缓冲器)，页缓冲器再连接至存储单元阵列。在对存储单元阵列中存储的数据进行验证后，可以通过页缓冲器得到相应的检测信号Iero。该检测信号Iero中可以携带有验证数据的错误信息。因此，触发电路120可以接收该检测信号并产生相应的错误位信号Vero(即PB节点的电压)。该错误位信号Vero会施加至触发电路120中与各支路123连接的电源端PMOS开关的控制极，配置为导通电源端的通路为这些支路123提供电流，同时作为比较器130的输入信号，即待比较的信号。通过比较该错误位信号Vero与不同的基准信号Inp，可以得出错误位信号Vero的大小范围，该范围则可以体现出错误位数量的范围，进而可以利用比较结果确定错误位计数的验证结果。
在本申请实施例中，比较器130可以耦接到上述触发电路120。如图2C所示，这里的比较器130是指对两个电压信号(错误位信号Vero和基准信号Inp)进行比较，以确定两个电压信号是否相等或大小关系的电路元件。其中，比较器130的两路输入为模拟信号，输出则为二进制信号“0”或“1”(通过低电平和高电平来表示)。在一些实施例中，需要根据二进制信号计算验证错误位的具体数量时，可以将比较器的比较结果用符号Ver_out<13:0>来表示。其中，Ver_out<13:0>表示将错误位信号与14个不同的基准信号进行比较后，得到的14个二进制输出信号的集合。示例性地， 若错误位信号大于基准信号，则输出Ver_out<0>＝1；若错误位信号小于基准信号，则输出Ver_out<0>＝0。需要说明的是，上述多个基准信号的数量需要根据实际情况确定。
图2B给出了本申请实施例的一种VFC电路的示意图，其中，触发电路120具有配置为产生多个基准信号Inp，这些基准信号Inp可以分时依次提供至同一比较器130，比较器130则依次比较错误位信号Vero与多个基准信号Inp，直至确定出错误位信号Vero的范围。
在一些实施例中，可以先比较错误位信号Vero与第一个基准信号Inp，若比较器输出结果为二进制信号“1”，则表示错误位信号大于第一个基准信号，再将错误位信号Vero与第二个基准信号(第二个基准信号大于第一个基准信号)进行比较，直至比较器130的输出结果为二进制信号“0”，就可以确定错误位信号Vero所在的电压大小范围，从而得到验证结果。因此，本申请实施例可以对不同的基准信号Inp复用比较器，从而减少多余电路元件的占用面积，节约存储器的空间，同时可以减少功耗，提升存储器的可靠性。
相对地，在一些实施例中，如图3示出的另一种VFC电路，该VFC电路的触发电路(虚线框中的部分)包括并列排布的多个与PB侧连接的支路以及多个输出基准信号Inp的支路(图3中示出的立体结构)，并且每个支路连接一个比较器。每组支路通过一组受控开关控制，导通时输出一个基准信号Inp与错误位信号Vero进行比较时，都需要采用不同的比较器。示例性地，将错误位信号与第一基准信号输入到第一比较器中，若输出的比较结果为高电平，则表示二进制信号“1”，需要将错误位信号与第二基准信号输入到与第一比较器不同的第二比较器中。相对于本申请实施例提供的如图2B所示的VFC电路中的触发电路120，图3中的触发电路，每次比较过程都采用单独的比较器，会占用较大的面积；另一方面，在第二个 比较器开启的情况下，第一个比较器仍保持开启状态，这样会导致多余的功耗，从而增加器件损坏的概率。
在一些实施例中，如图4所示，所述基准信号输出电路121，包括：
多条并联的支路123，每条支路包括至少一个受控开关410；所述多条并联的支路123分别配置为输出所述多个基准信号。
在本申请实施例中，上述触发电路120可以通过多个受控开关410来分别控制多条支路123的开启，基准信号Inp可以是多条支路并联后的干路电流，因此，并联的总电流在数值上等于多条支路电流的总和，不同的总电流值则对应不同的基准信号Inp的电压值。
在本申请实施例中，可以通过依次开启受控开关，使得导通的支路数量依次增加，从而得到多个不同的基准信号Inp。可以理解的是，若开启的受控开关越多，则接入触发电路的支路数量越多，使得干路上的电流越大，输出的基准信号的电压值越小；反之亦然，若开启的受控开关越少，则接入触发电路的支路数量越少，使得干路上的电流越小，输出的基准信号的电压值越大。示例性地，第一受控开关对应于第一支路的开启，第二受控开关对应于第二支路的开启，每个受控开关对应于每个支路，且受控开关和支路的数量需要根据实际生产需求确定。需要说明的是，上述受控开关包括但不限于三级管、场效应晶体管等三端器件或其他可实现开关功能的电路元件中的一种或多种。
在另一实施例中，上述各支路123上的受控开关可以具有不同的电阻值，从而导通时可以提供不同的基准信号。故这种情况可以分别依次导通不同的支路123，且每次仅导通一条支路123。
此外，各条支路上还可以具有另一受控开关，并且每条支路的这一受控开关均由如图4所示的e1信号控制，该e1信号可以由上述实施例中所涉及的参考电路110触发晶体管P1导通而得到，从而达到使能触发电路的作 用。
本申请实施例可以根据参考电路的控制信号来控制受控开关的开启或者关闭，且一个受控开关对应一个支路的开启，这样可以精准的调节基准信号的数值，从而提高比较结果的可靠性。
在一些实施例中，所述多个受控开关410被配置为：接收到第一使能信号Ei的所述受控开关410切换为导通状态，使对应的所述支路123导通并提供所述基准信号Inp。
在本申请实施例中，具体地，可以接收多个外部输入的第一使能信号E1、E2……Ei，从而控制受控开关410的开启或者关闭。并且，多个第一使能信号E1、E2……Ei可以依次输入到受控开关410，即可以以一定延迟依次触发上述受控开关410。这里，受控开关410可以是晶体管，第一使能信号E1、E2……Ei则为施加在晶体管控制极的电压信号。示例性地，第一使能信号可以是高电平，当对应支路接收到上述高电平的信号时，可以使得支路上的受控开关开启。
在另一些实施例中，上述第一使能信号E1、E2……Ei可以是上一支路123进行比较后的结果反馈至当前支路123后实现对下一支路123的使能，从而实现依次比较。
在一些实施例中，如图5所示，所述比较器130包括至少两个；所述基准信号输出电路121包括至少两个子输出电路；每个所述子输出电路包括至少一条所述支路123，且一个所述子输出电路连接一个所述比较器130，其中，所述子输出电路的个数与所述比较器130的个数相同。
可以理解的是，在上述实施例中，可以分时依次比较错误位信号Vero与多个不同的基准信号Inp，这样只需要一个比较器即可。在一些实施例中，为了平衡延迟时长，也可以使用多个比较器130。也就是说，可以将上述触发电路120中的多条支路进行分组，每组共用一个比较器130。示例性地， 可以将待比较的基准信号Inp通过支路分为两组(低比特组和高比特组)或者三组(低比特组、中比特组和高比特组)。这里的组数可以根据实际验证错误位计数的精确度来确定。
如图5所示，触发电路120的多条支路可以被分成两个子输出电路，包括：低比特组510与高比特组520。其中，低比特组510可以代表错误位为1至9比特数的范围，高比特组520可以代表错误位为10至25比特数的范围，两组支路提供的各基准信号不同。两组支路输出的基准信号Inp以及错误位信号Vero分别输入至不同的比较器130中，从而可以分别得到对应的比较参数。这里，比特数的上限可以根据存储单元阵列中未通过编程验证的存储单元数量来确定。
需要说明的是，上述比特是指存储器的最小存储单元，即存储单元阵列中的一个存储单元存储的数据。以单层存储单元(Single Level Cell)为例，存储单元的编程状态可以是二进制信息“0”或者“1”，其中，二进制信息“1”可以表示该存储单元未进行编程或编程失败(未通过编程验证)，二进制信息“0”可以表示该存储单元被编程且验证通过。示例性地，编程失败的存储单元数量将会以上述比特数的形式被锁存在页缓冲器中，再通过电信号的形式被VFC电路统计。具体地，页缓冲器输入VFC电路检测信号Iero可以经由VFC电路转换为错误位信号Vero并与VFC电路内部触发电路输出的多个基准信号Inp依次进行对比。由于导通的支路数量不同可以提供不同的多个基准信号Inp，因此，上述基于比特数将受控开关进行分组可以直观的确定错误位数的范围。
这里，每一子输出电路复用同一个比较器。例如，受控开关可以分为第一组(低比特组)和第二组(高比特组)，则第一组可以利用第一比较器来比较错误位是否处于低比特范围内，第二组可以利用第二比较器来比较错误位是否处于高比特范围内。需要说明的是，这里的低比特范围和高比 特范围可以根据子输出电路的数量改变。若子输出电路越多，则子输出电路对应的错误位比特范围越小，确定的错误位数越精确，需要设置的比较器也越多；若组数越少，则对应的错误位比特范围越大，确定的错误位数越宽泛，需要设置的比较器也越少。
因此，本申请实施例可以设置多个子输出电路，每个子输出电路中的各条支路都复用对应的比较器来依次比较错误位信号和多个基准信号；另一方面，每次比较器可以相互独立进行比较，这样既可以减少电路元件的占用面积，节约空间，又可以提高比较效率，提高VFC电路的可靠性。
在一些实施例中，所述比较器的输入端连接所述触发电路，并被配置为：
比较所述错误位信号和一个基准信号，输出比较参数；
如果所述比较参数指示所述错误位信号大于所述基准信号，则继续比较下一个基准信号；
如果所述比较参数指示所述错误位信号小于或等于所述基准信号，则停止比较并输出所述验证结果。
在本申请实施例中，上述比较器可以具有至少两个输入端和一个输出端，其中，两个输入端配置为分别接收触发电路产生的错误位信号和输出的一个基准信号，一个输出端配置为输出比较后的结果，即上述比较参数。这里的比较参数可以为二进制信号“0”或“1”。示例性地，若错误位信号大于所比较的基准信号，则输出二进制信号“1”，指示未通过编程验证的存储单元数量大于当前基准信号对应的比特数，需要继续下一轮的比较；若错误位信号小于或等于所比较的基准信号，则输出二进制信号“0”，指示未通过编程验证的存储单元数量已小于或等于当前基准信号对应的比特数或者位于当前基准信号对应的比特数范围内，从而可以停止比较，得到对应的验证结果。
因此，本申请实施例中的比较器可以依次比较错误位信号和多个基准信号，从而逐级判断未通过编程验证的存储单元数量是否位于当前基准信号对应的比特数范围内。这样可以提高比较的效率和精度，增加VFC电流的可靠性。
在一些实施例中，如图6A所示，所述存储器外围电路中的VFC电路100还包括：
延时电路140，与所述比较器130耦接；所述延时电路140被配置为：
依次接收多个第二使能信号en，输出延迟信号；
根据接收到的多个所述延迟信号，分别延迟所述比较器输出的多个所述比较参数，输出延迟比较参数。
在本申请实施例中，比较器可以配置为依次比较错误位信号和多个基准信号，从而实现复用，这样使得同一比较器130会输出多个比较参数。为了能有效的区分开上述多个比较参数，本申请实施例可以将比较器130与延时电路140耦接，这样可以通过施加对应的延时来进行区分。需要说明的是，如图6B所示，上述延时电路140可以在比较器130输出比较参数之前，接收第二使能信号en0……en6来输出对应的延迟信号a0……a6。这里的第二使能信号可以是高电平信号，配置为触发延时电路140输出对应的延迟信号；这里的延迟信号可以是时间Δt内的一段高电平信号。此外，第二使能信号en0……en6可以根据时钟信号或者其他外部信号按照预设的顺序依次提供至延迟电路140。
本申请实施例涉及的延时电路140可以具有多条延时支路，这里的多条支路与上述多个比较参数相对应，即配置为延迟每一基准信号与错误位信号比较后的比较参数。另外，延时电路140的多条延时支路可以复用一个延时模块，该延时模块可以分别对应每条支路的第二使能信号en0……en6输出对应的延迟信号，这样减少多余延时模块的功耗。需要说明的是， 每条延时支路设定一个延时模块，或者多条延时支路设定一个延时模块等其他的技术方案也是本申请实施例所要求保护的范围。
示例性地，如图6C所示，当比较器130输出第一比较参数out0时，上述延时电路140可以接收第二使能信号en0，从而触发对应的延时支路产生第一延迟信号a0，并可以通过一个与门610将第一比较参数out0延迟，最终输出第一延迟比较参数a0_1。这里，延迟单元140的多个输出端可以分别连接至多个与门610，由于延迟单元140的多个输出端是分时输出延迟信号的，因此，最终多个与门610输出的延迟比较参数a0_1至ax_1也是分时输出的，这样，就可以利用同一个比较器分别对不同的基准信号进行处理，分时得到各基准信号对应的比较结果，从而实现比较器的复用。
需要说明的是，上述延迟信号为高电平，若比较参数为高电平，则经过与门后的延迟比较参数也为高电平，反之，若比较参数为低电平，则经过与门后的延迟比较参数也为低电平。因此，上述延时电路不会改变比较器输出的比较参数对应的二进制信息，又可以区分多个比较参数。
本申请实施例中采用延时电路可以有效地区分比较器的比较参数，从而提高验证错误位计数的精度，提升产品可靠性。
在一些实施例中，如图7A所示，所述外围电路中，VFC电路100还包括：
锁存器电路150，包括多个锁存器，与所述延时电路140耦接；所述锁存器配置为存储所述延迟比较参数；其中，所述锁存器的个数与所述基准信号的个数相同。
在本申请实施例中，复用的比较器会产生多个比较参数，且每个比较参数是相对独立的，需要经过延时电路延迟并计算错误位数，从而得到验证结果。因此，可以将锁存器电路与上述延时电路耦接，将多个延迟比较参数锁存起来，再配置为后续的计算。这里的锁存器可以将二进制信息“0” 或“1”转换为电平信号锁存，并维持其电平状态。其中，每个延迟比较参数都可以对应于一个锁存器，从而组成了上述的锁存器电路，因此，锁存器的个数可以与基准信号的个数相同，从而使得每次比较后得到的延迟比较参数可以分别存储在单独的锁存器中。
在一些实施例中，所述锁存器电路还与所述触发电路耦接，其中所述锁存器被配置为：
将所述延迟比较参数转换为锁存信号，并锁存到对应的所述锁存器中；
根据所述锁存信号，输出反馈信号；其中，所述反馈信号配置为触发所述触发电路切换待比较的所述基准信号。
在本申请实施例中，如图7B所示，为上述锁存器电路150中的一个锁存器151的结构示意图。这里的锁存器151可以具有场效应晶体管710和锁存单元720，其中，场效应晶体管710的控制端接收上述延迟比较参数，如ax_1，即控制端连接在上述与门610的输出端，从而可以配置为开启锁存单元720实现数据的锁存。示例性地，若延迟比较参数为二进制信息“1”，则在场效应晶体管710导通的情况下，可以将该二进制信息转换为锁存器内部的电平信号(例如高电平)，并作为锁存单元720的输入锁存起来。示例性地，若延迟比较参数为二进制信息“1”，即高电平电压信号，使得场效应晶体管710导通，地电压通过场效应晶体管710到达锁存单元720，锁存单元720对地电压信号进行反相处理，得到的锁存信号b_0则为高电平电压信号，从而实现锁存。
进一步地，锁存单元720的结构可以如图7C所示。这里，在未锁存之前，锁存单元720的控制端Y＝“1”。当该延迟比较参数通过上述导通的场效应管710输入到锁存器后，需要锁存到对应的锁存单元720中。此时，该锁存单元的控制端Y由“1”变为“0”，由二进制信息“1”转换来的高电平信号从锁存单元的另一输入端A输入，从而将信号锁存起来。当后续 需要上述信息时，再将控制端Y由“0”变为“1”，则可以取消锁存，从输出端B输出对应的高电平信息。
另一方面，上述锁存器可以根据锁存的电平信息输出对应的反馈信号，这里的反馈信号可以是电平信号、时钟信号或其他反馈信号。示例性地，若锁存的信息为高电平，说明输入该锁存器的延迟比较参数为二进制信息“1”，进一步说明错误位电路大于当前基准信号，即错误位数未处于当前比较的比特数范围内。因此，需要根据该锁存的高电平信息输出高电平的反馈信息，并输入到与上述锁存器电路耦接的触发电路中，使得触发电路产生新的第一使能信号，配置为开启对应的受控开关，从而触发新的基准信号，配置为和错误位信号进行一轮新的比较。依次循环，直到错误位信号小于或等于当前的基准信号，则锁存器中的锁存信息为低电平，对应的反馈信号也为低电平，这样使得触发电路不再产生新的第一使能信号，对应的受控开关也不再开启，进而停止比较，最终通过后续计算得到对应的验证结果。
本申请实施例可以通过锁存器电路锁存上述延迟比较参数，并输出反馈信号到触发电路，配置为根据该锁存信息判断是否进行下一轮比较。这样可以有效地保存延迟比较参数，减少数据丢失，并且加入反馈信号，改变了触发电路中的受控开关的开启条件，从而增加了VFC电路的可靠性。
在一些实施例中，如图8所示，所述存储器中的VFC电路100还包括：
码制转换电路160，与所述锁存器电路150耦接；所述码制转换电路160被配置为：将所述锁存信号转换为二进制码；所述二进制码配置为计算得到所述验证结果。
在本申请实施例中，根据锁存器中锁存的锁存信息无法直观的表述未通过编程验证的存储单元数量，因此可以将锁存器电路与码制转换电路耦接，从而将锁存信息对应的电平信号转化为更易识别的二进制码。对应的， 高电平可以转换为二进制码“1”，低电平可以转换为二进制码“0”。这样，将电信号转换为数值信号可以更加方便、简洁、直观地表达验证结果，从而提升VFC电流的可靠性。
在一些实施例中，如图9所示，所述存储器中的VFC电路100还包括：
累加器170，与所述码制转换电路160耦接；所述累加器170被配置为：
累加从所述码制转换电路获得的多个所述二进制码，得到错误位计数的所述验证结果。
在本申请实施例中，将每个锁存信号转换为对应的二进制码后，还可以将上述二进制码进行累加，从而获得整个存储单元阵列的错误位数。因此，可以将上述码制转换电路与累加器耦接，这里的累加器可以采用寄存器。累加器可以在计算验证结果之前初始化，并以此将码制转换电路获得的多个二进制码累加，从而获得VFC电路多次比较后的错误位数量总和，最终得到错误位计数的验证结果。
在一些实施例中，所述锁存器电路150还被配置为：
接收重置信号，重置所述锁存信号。
在本申请实施例中，如图10所示，上述存储器电路中的每个锁存器151还可以包括配置为接收重置信号的场效应晶体管730，这些场效应晶体管730的输入端可以是同一电路节点，即当锁存器电路接收重置信号时，该电路中的所有锁存器也将对应的接收重置信号，并将锁存单元中的锁存信息重置。示例性地，一下锁存器锁存高电平，一下锁存器锁存低电平，在接收重置信号后，所有的锁存器将被重置为低电平，且锁存单元中的控制端将重置为“1”。
本申请实施例可以在参考电路输出控制信号到触发电路之后，将重置信号输入到锁存器电路，使得在锁存延迟比较参数之前保持锁存器的开启。这样，改变了VFC电路的触发方式，并可以增加锁存信息的准确性，提高 反馈信号的精度，从而提升了存储器的可靠性。
另一方面，如图11所示，本申请实施例还提供了一种半导体存储器的验证错误位计数电路的控制方法，包括：
步骤S10、输出至少一个基准信号；
步骤S20、根据对存储器进行验证得到的检测信号，产生错误位信号；
步骤S30、依次比较所述错误位信号和所述多个基准信号，得到验证结果。
在本申请实施例中，参考电路可以配置为接收外部控制信号，例如时钟信号或使能信号，使VFC电路启动验证错误位计数。对应的，参考电路可以将外部信号转换为内部的控制信号并输出，配置为控制VFC电路中的对应单元输出多个基准信号。这里的多个基准信号可以通过触发电路上多个受控开关来控制，受控开关又可以根据上述参考电路的控制信号来实现开启或者关闭。因此，若开启的受控开关越多，则接入触发电路的支路数量越多，使得干路上的基准信号越大；若开启的受控开关越少，则接入触发电路的支路数量越少，使得干路上的基准信号越小。
在VFC电路启动后，可以接收来自检测信号，并根据参考电路输出的控制信号，产生错误位信号。这里的错误位信号是页缓冲器中接收到的错误比特数所对应的电流，配置为指示存储单元阵列未通过编程验证的存储单元的数量。示例性地，存储单元阵列可以通过位线与页缓冲器耦接，若存储单元未通过编程验证，则存储单元对应的位线支路的页缓冲器会输出对应的电流信号，VFC电路通过对该电流信号进行统计，可以得到未通过编程验证的存储单元的个数并输出该个数，从而实现了验证过程中错误位的计数。需要说明的是，上述步骤S10和步骤S20是两个相互独立的步骤，在实际操作中可以依次实现，也可以同步实现。
最终，通过VFC电路中的比较器可以依次比较上述错误位信号和多个 基准信号，这样得到验证结果。需要说明的是，本申请实施例中依次进行比较可以实现比较器的复用，从而减少电路元件的占用面积，节约空间，同时可以减少功耗，提升存储器的可靠性。
在一些实施例中，所述控制方法还包括：
依次接收多个第一使能信号；其中，接收到所述第一使能信号的受控开关切换为所述导通状态；连接开启状态的所述受控开关的所述支路导通并配置为提供所述基准信号。
在本申请实施例中，VFC电路可以根据参考电路的控制信号来接收多个第一使能信号，从而控制受控开关的开启或者关闭。并且，多个使能信号可以依次输入到受控开关，即可以以一定延迟依次触发上述受控开关。需要说明的是，这里的使能信号可以作为电信号加在受控开关对应的支路上，从而控制受控开关的开启。示例性地，第一使能信号可以是高电平，当对应支路接收到上述高电平的信号时，可以使得支路上的受控开关开启。
在一些实施例中，所述依次比较所述错误位电路和所述多个基准信号，得到验证结果，包括：
比较所述错误位信号和一个基准信号，输出比较参数；
根据与所述比较参数对应的延迟信号，延迟所述比较参数，输出延迟比较参数；
将所述延迟比较参数转换为锁存信号，锁存到对应的锁存器中；
若所述锁存信号指示所述错误位信号大于所述基准信号，则比较所述错误位信号和下一个基准信号，直至所述延迟比较参数指示所述错误位信号小于或等于所述基准信号；
将多个锁存器中锁存的所述锁存信号分别转换为二进制码；
累加多个所述二进制码，得到错误位计数的所述验证结果。
在本申请实施例中，可以通过VFC电路中的比较器依次比较上述错误 位电路和多个基准信号。具体地，在比较错误位信号和一个基准信号后可以输出对应的比较参数，这里的比较参数可以为二进制信号“0”或“1”。
本申请实施例中的VFC电路可以包括延时电路配置为输出预设的延迟信号，配置为将上述比较器输出的多个比较参数延迟，从而区分开同一比较器输出的多个比较参数。这里的延迟信号可以是时间Δt内的一段高电平信号，当比较器输出一个比较参数时，将上述比较参数与对应的延迟信号经过一个与门，从而输出对应的延迟比较参数。示例性地，若比较参数为高电平，则经过与门后的延迟比较参数也为高电平；反之，若比较参数为低电平，则经过与门后的延迟比较参数也为低电平，这样使得上述延时电路不会改变比较器输出的比较参数对应的二进制信息。
接着，本申请实施例可以通过锁存器将上述的延迟比较参数锁存起来。这里的锁存器可以将二进制信息“0”或“1”转换为电平信号锁存，并维持其电平状态。其中，每个延迟比较参数都可以对应于一个锁存器，从而组成了VFC电路内部的锁存器电路。
示例性地，若错误位信号大于所比较的基准信号，则比较器输出二进制信号“1”，锁存器锁存对应的高电平，从而指示未通过编程验证的存储单元数量大于当前基准信号对应的比特数，需要继续下一轮的比较；若错误位信号小于或等于所比较的基准信号，则比较器输出二进制信号“0”，锁存器锁存对应的低电平，从而指示未通过编程验证的存储单元数量已小于或等于当前基准信号对应的比特数或者位于当前基准信号对应的比特数范围内，从而可以停止比较，并通过后续计算得到对应的验证结果。
最终，可以通过VFC电路中的码制转换电路将锁存器锁存的电平信号转换为为更易识别的二进制码。对应的，高电平可以转换为二进制码“1”，低电平可以转换为二进制码“0”。再通过累加器在计算验证结果之前初始化，并以此将码制转换电路获得的多个二进制码累加，从而获得VFC电路 多次比较后的错误位数量总和，最终得到错误位计数的验证结果。
在一些实施例中，所述若所述锁存信号指示所述错误位信号大于所述基准信号，则比较所述错误位信号和下一个基准信号，包括：
所述锁存器根据所述锁存信号，输出反馈信号；
若所述反馈信号指示所述错误位信号大于所述基准信号，则向下一个所述受控开关输出所述第一使能信号；其中，接收到所述第一使能信号的所述受控开关切换为开启状态，且所述触发电路产生下一个基准信号并与所述错误位信号进行比较。
在本申请实施例中，示例性地，若锁存的信息为高电平，说明输入该锁存器的延迟比较参数为高电平，进一步说明错误位电路大于当前基准信号，即错误位数未处于当前比较的比特数范围内。因此，需要根据该锁存的高电平信息输出高电平的反馈信息，并输入到与上述锁存器电路耦接的触发电路中，使得触发电路产生新的第一使能信号，配置为开启对应的受控开关，从而触发新的基准信号，配置为和错误位信号进行一轮新的比较。依次循环，直到错误位信号小于或等于当前的基准信号，则锁存器中的锁存信息为低电平，对应的反馈信号也为低电平，这样使得触发电路不再产生新的第一使能信号，对应的受控开关也不再开启，进而停止比较，最终通过上述码制转换电路和累加器计算得到对应的验证结果。
在一些实施例中，如图12所示，为本申请实施例提供的存储器的控制时序图。示例性地，在T0时刻，参考电路可以接收来自外部的控制信号En_ref(总的使能信号，图中未示出)启动VFC电路在T1时刻，需要向锁存器电路施加重置信号Rst_latch(图中未示出)，使得当前锁存器保持低电平，并恢复锁存状态。接着，参考电路输出的控制信号，打开如图4所示的触发电路120中的PMOS管P1、P2以及P3。从而产生使能信号e1和e2。使得触发电路120在T2时刻产生对应的错误位信号Vero和基准信号Inp。 然后，位于触发电路支路123上的受控开关在T3时刻接收对应的第一使能信号E1，同时如图6C所示的延时电路140接收对应的第二使能信号en0。比较器130输出对应的第一比较参数被延时电路输出的预设延迟信号a0延时，从T3时刻延迟至T4时刻，输出如图6C所示的延迟比较参数ax_1(此时为a0_1)，此时对应的延迟比较参数a0_1对应的二进制信息为“1”，传输到如图7B所示的锁存器151中，锁存到对应锁存器151中的电平信号b_0为高电平，该电平信号即反馈信号，并将作为下一支路123的第一使能信号E2。因此，将会继续比较错误位信号与下一个基准信号。
这时，锁存器151输出的反馈信号b_0使得触发电路再次接收第一使能信号E2，从而开启下一支路123的受控开关，输出下一个基准信号Inp，此时的基准信号Inp已经与上一次输出的基准信号Inp具有不同的电压值。同步地，延时电路140也会触发新的第二使能信号en1，输出预设延迟信号a1。自此循环，直至T6时刻，比较器130输出的第一比较参数为二进制信息“0”，这样，使得对应的延迟比较参数也为“0”，对应的锁存器锁存低电平，从而导致反馈信号不再触发对应的使能信号，验证结束。后续，码制转换单元会将锁存器电路中锁存的电平信息转换为二进制码，再输入到累加器中，从而得到最终的验证结果，即本次编程中未通过验证的存储单元数量为第三基准信号对应的比特数范围。
需要说明的是，如图12所示的时序图是以比较3次后得出比较结果为例，即比较到第三次，得到的锁存器延迟比较参数a2_1为低电平，表示当前的错误位信号大于参考信号，此时锁存器151中的电平信号b_2为低电平，将其反馈至下一支路123的第一使能信号E4无法导通下一支路123，故停止后续的比较，相应地，后续各锁存器存储的电平信号如b_3至b_12等也为低电平。
本申请所提供的几个方法或设备实施例中所揭露的特征，在不冲突的 情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种存储器，所述存储器包括存储单元阵列和外围电路；所述外围电路至少包括：
    触发电路，包括基准信号输出电路和错误位信号输出电路；
    其中，所述错误位信号输出电路被配置为：根据对存储器进行验证得到的检测信号，产生错误位信号；
    所述基准信号输出电路被配置为：输出至少一个基准信号；
    比较器，与所述触发电路耦接；所述比较器被配置为：
    比较所述错误位信号和至少一个所述基准信号，输出验证结果。
  2. 根据权利要求1所述的存储器，其中，所述基准信号输出电路，包括：
    多条并联的支路，每条支路包括至少一个受控开关；所述多条并联的支路分别配置为输出至少一个所述基准信号。
  3. 根据权利要求2所述的存储器，其中，所述受控开关被配置为：
    接收到第一使能信号的所述受控开关切换为导通状态，使对应的所述支路导通并提供所述基准信号。
  4. 根据权利要求2所述的存储器，其中，所述比较器包括至少两个；所述基准信号输出电路包括至少两个子输出电路；每个所述子输出电路包括至少一条所述支路，且一个所述子输出电路连接一个所述比较器，其中，所述子输出电路的个数与所述比较器的个数相同。
  5. 根据权利要求1至4任一所述的存储器，其中，所述比较器的输入端连接所述触发电路，并被配置为：
    比较所述错误位信号和一个基准信号，输出比较参数；
    如果所述比较参数指示所述错误位信号大于所述基准信号，则继续比较下一个基准信号；
    如果所述比较参数指示所述错误位信号小于或等于所述基准信号，则停止比较并输出所述验证结果。
  6. 根据权利要求5所述的存储器，其中，所述外围电路中，还包括：
    延时电路，与所述比较器耦接；所述延时电路被配置为：
    依次接收多个第二使能信号，输出延迟信号；
    根据接收到的多个所述延迟信号，分别延迟所述比较器输出的多个所述比较参数，输出延迟比较参数。
  7. 根据权利要求6所述的存储器，其中，所述外围电路，还包括：
    锁存器电路，包括多个锁存器，与所述延时电路耦接，所述锁存器配置为存储所述延迟比较参数；其中，所述锁存器的个数与所述基准信号的个数相同。
  8. 根据权利要求7所述的存储器，其中，所述锁存器电路还与所述触发电路耦接，其中所述锁存器被配置为：
    将所述延迟比较参数转换为锁存信号，并锁存到对应的所述锁存器中；
    根据所述锁存信号，输出反馈信号；其中，所述反馈信号配置为触发所述触发电路切换待比较的所述基准信号。
  9. 根据权利要求8所述的存储器，其中，所述存储器还包括：
    码制转换电路，与所述锁存器电路耦接；所述码制转换电路被配置为：
    将所述锁存信号转换为二进制码；所述二进制码配置为计算得到所述验证结果。
  10. 根据权利要求9所述的存储器，其中，所述外围电路还包括：
    累加器，与所述码制转换电路耦接；所述累加器被配置为：
    累加从所述码制转换电路获得的多个所述二进制码，得到错误位计数的所述验证结果。
  11. 根据权利要求8所述的存储器，其中，所述锁存器电路还被配置为：
    接收重置信号，重置所述锁存信号。
  12. 根据权利要求1所述的存储器，其中，所述外围电路还包括：
    参考电路，与所述触发电路连接，并被配置为基于外部输入信号向所述触发电路输出控制信号；所述控制信号配置为使能所述触发电路。
  13. 根据权利要求12所述的存储器，其中，所述控制信号，包括第一控制信号和第二控制信号；其中，所述第一控制信号配置为使能所述基准信号输出电路输出多个所述基准信号；所述第二控制信号配置为使能所述错误位信号输出电路接收所述检测信号。
  14. 一种存储器的控制方法，所述控制方法应配置为所述存储器的外围电路，包括：
    输出至少一个基准信号；
    根据对存储器进行验证得到的检测信号，产生错误位信号；
    比较所述错误位信号和至少一个所述基准信号，输出验证结果。
  15. 根据权利要求14所述的控制方法，其中，所述控制方法还包括：
    依次接收多个第一使能信号；其中，接收到所述第一使能信号的受控开关切换为导通状态；连接开启状态的所述受控开关的支路导通并配置为提供所述基准信号。
  16. 根据权利要求15所述的控制方法，其中，所述比较所述错误位信号和所述多个基准信号，输出验证结果，包括：
    比较所述错误位信号和一个基准信号，输出比较参数；根据与所述比较参数对应的延迟信号，延迟所述比较参数，输出延迟比较参数；
    将所述延迟比较参数转换为锁存信号，锁存到对应的锁存器中；
    若所述锁存信号指示所述错误位信号大于所述基准信号，则比较所述错误位信号和下一个基准信号，直至所述延迟比较参数指示所述错误位信号小于或等于所述基准信号；将多个锁存器中锁存的所述锁存信号分别转 换为二进制码；
    累加多个所述二进制码，得到配置为表示错误位计数的所述验证结果并输出所述验证结果。
  17. 根据权利要求16所述的控制方法，其中，所述若所述锁存信号指示所述错误位信号大于所述基准信号，则比较所述错误位信号和下一个基准信号，包括：
    所述锁存器根据所述锁存信号，输出反馈信号；
    若所述反馈信号指示所述错误位信号大于所述基准信号，则向下一个所述受控开关输出的所述第一使能信号，其中，接收到所述第一使能信号的所述受控开关切换为开启状态，且触发电路产生下一个基准信号并与所述错误位信号进行比较。
  18. 根据权利要求16所述的控制方法，其中，所述方法还包括：
    接收重置信号，重置所述锁存信号。
  19. 根据权利要求16所述的控制方法，其中，所述方法还包括：
    基于外部输入信号，输出控制信号；其中，所述控制信号包括：配置为使能输出多个所述基准信号的第一控制信号和配置为使能接收所述检测信号的第二控制信号。
  20. 一种存储器系统，所述存储器系统包括：
    存储器控制器；
    存储器；所述存储器包括存储单元阵列和外围电路；所述外围电路至少包括：触发电路和比较器；所述触发电路包括基准信号输出电路和错误位信号输出电路；其中，所述错误位信号输出电路被配置为：根据对存储器进行验证得到的检测信号，产生错误位信号；所述基准信号输出电路被配置为：输出至少一个基准信号；所述比较器，与所述触发电路耦接；所述比较器被配置为：比较所述错误位信号和至少一个所述基准信号，输出 验证结果。
PCT/CN2023/075741 2022-12-07 2023-02-13 存储器及其控制方法、存储器系统 Ceased WO2024119613A1 (zh)

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