WO2024117064A1 - 半導体集積回路、伝送システム、および、データ伝送方法 - Google Patents

半導体集積回路、伝送システム、および、データ伝送方法 Download PDF

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Publication number
WO2024117064A1
WO2024117064A1 PCT/JP2023/042305 JP2023042305W WO2024117064A1 WO 2024117064 A1 WO2024117064 A1 WO 2024117064A1 JP 2023042305 W JP2023042305 W JP 2023042305W WO 2024117064 A1 WO2024117064 A1 WO 2024117064A1
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Prior art keywords
data
logical value
transmitted
bits
transmission
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English (en)
French (fr)
Japanese (ja)
Inventor
翔平 福田
晃 高橋
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Nuvoton Technology Corp Japan
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Nuvoton Technology Corp Japan
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Priority to JP2024561467A priority Critical patent/JPWO2024117064A1/ja
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Definitions

  • Patent Document 1 Conventionally, semiconductor integrated circuits and transmission systems for transmitting data have been proposed (see, for example, Patent Document 1).
  • the signal quality of the transmitted data may deteriorate depending on the data pattern.
  • the present disclosure therefore aims to provide a semiconductor integrated circuit, a transmission system, and a data transmission method that can suppress degradation of the signal quality of transmitted data that can occur depending on the data pattern when transmitting data.
  • a semiconductor integrated circuit includes a transmission control unit that transmits M-bit (M is an integer of 2 or more) transmission data to a destination circuit every multiple cycles and transmits a strobe signal to the destination circuit to cause the destination circuit to receive the transmission data; a determination unit that determines whether or not the transmission control unit transmits dummy data to the destination circuit before transmitting the transmission-scheduled data to the destination circuit based on the transmission-scheduled data to be transmitted next by the transmission control unit and N pieces of transmitted data transmitted in N cycles (N is an integer of 1 or more) among the transmission data previously transmitted by the transmission control unit; and a dummy data generation unit that generates the dummy data by a predetermined method.
  • M-bit M is an integer of 2 or more
  • the transmission control unit transmits the dummy data to the destination circuit before transmitting the transmission-scheduled data to the destination circuit and performs an invalidation process to invalidate the dummy data in the destination circuit.
  • the transmission system includes a transmission control unit that transmits M bits (M is an integer of 2 or more) of transmission data every multiple cycles and transmits a strobe signal to the destination circuit to cause the destination circuit to receive the transmission data, a determination unit that determines whether or not the transmission control unit transmits dummy data to the destination circuit before transmitting the transmission-scheduled data to the destination circuit based on the transmission-scheduled data to be transmitted next by the transmission control unit and N pieces of transmitted data transmitted in N cycles (N is an integer of 1 or more) among the transmission data previously transmitted by the transmission control unit, and a dummy data generation unit that generates the dummy data by a predetermined method, and when the determination unit determines that the transmission control unit transmits the dummy data to the destination circuit before transmitting the transmission-scheduled data to the destination circuit, the transmission control unit transmits the dummy data to the destination circuit before transmitting the transmission-scheduled data to the destination circuit and performs an invalidation process to invalidate the d
  • the data transmission method includes a transmission control step of transmitting M-bit (M is an integer of 2 or more) transmission data to a destination circuit every multiple cycles and transmitting a strobe signal to the destination circuit to cause the destination circuit to receive the transmission data, a determination step of determining whether or not to transmit dummy data to the destination circuit before transmitting the transmission-scheduled data to the destination circuit based on the transmission-scheduled data to be transmitted next and N pieces of transmitted data transmitted in N cycles (N is an integer of 1 or more) among the transmission data transmitted in the past, and a dummy data generation step of generating the dummy data by a predetermined method, and in the transmission control step, if it is determined in the determination step that the dummy data is to be transmitted to the destination circuit before transmitting the transmission-scheduled data to the destination circuit, the dummy data is transmitted to the destination circuit before transmitting the transmission-scheduled data to the destination circuit, and an invalidation process is performed to invalidate the dummy data
  • the semiconductor integrated circuit, transmission system, and data transmission method according to one embodiment of the present disclosure can suppress degradation of the signal quality of the transmitted data that can occur depending on the data pattern when transmitting data.
  • FIG. 1 is a block diagram showing a configuration of a transmission system according to a first embodiment.
  • FIG. 2 is a schematic diagram showing an example of how the semiconductor integrated circuit according to the first embodiment transmits transmission data to a destination circuit according to the first embodiment.
  • FIG. 3 is a schematic diagram illustrating an example of how the determining unit according to the first embodiment stores N pieces of transmitted data.
  • FIG. 4 is a schematic diagram showing an example of how the determining unit according to the first embodiment performs a determination.
  • FIG. 5 is a schematic diagram showing an example of how the determining unit according to the first embodiment performs a determination.
  • FIG. 6 is a block diagram showing another configuration of the transmission system according to the first embodiment. In FIG. FIG. FIG.
  • FIG. 7 is a schematic diagram showing an example of how the determining unit according to the first embodiment performs a determination.
  • FIG. 8 is a schematic diagram illustrating an example of how the determining unit according to the first embodiment performs a determination.
  • FIG. 9 is a schematic diagram showing an example of how the determining unit according to the first embodiment performs a determination.
  • FIG. 10 is a schematic diagram showing an example of how the determining unit according to the first embodiment performs a determination.
  • FIG. 11 is a schematic diagram illustrating an example of how the determining unit according to the first embodiment performs a determination.
  • FIG. 12 is a schematic diagram showing an example of how the dummy data generating unit according to the first embodiment generates dummy data.
  • FIG. 13 is a schematic diagram showing an example of how the dummy data generating unit according to the first embodiment generates dummy data.
  • FIG. 14 is a schematic diagram showing an example of how the dummy data generating unit according to the first embodiment generates dummy data.
  • FIG. 15 is a flowchart of the first data transmission process according to the first embodiment.
  • FIG. 16 is an example of a timing chart showing how the semiconductor integrated circuit according to the comparative example transmits transmission data to a destination circuit.
  • FIG. 17 is an example of a timing chart showing how the semiconductor integrated circuit according to the first embodiment transmits transmission data to a destination circuit.
  • FIG. 18 is a block diagram showing a configuration of a transmission system according to the second embodiment.
  • FIG. 19 is a flowchart of a second data transmission process according to the second embodiment.
  • the data being transmitted is bus-format data consisting of multiple bits
  • multiple bits may toggle simultaneously, causing the transmitted data to contain noise such as simultaneous switching noise (SSN, sometimes called power supply noise) and crosstalk noise.
  • SSN simultaneous switching noise
  • crosstalk noise sometimes called power supply noise
  • simultaneous switching noise is a type of noise that occurs when the potential of the power supply lines of the drive circuits that drive multiple bits fluctuates when these bits toggle simultaneously, and this fluctuation in the potential of the power supply lines is carried over to the data being transmitted.
  • Crosstalk noise is a type of noise that occurs on the data transmission path due to the interaction between multiple bits that change at the same time.
  • ISI intersymbol interference
  • the inventors have developed technology that can transmit data without degrading signal quality.
  • dummy data refers to data that is not processed in the destination circuit (here, the receiving circuit).
  • the inventors conducted further experiments and studies to realize a technology that can suppress degradation of the signal quality of transmitted data that can occur depending on the data pattern when transmitting data.
  • the inventors came up with the semiconductor integrated circuit, transmission system, and data transmission method according to the present disclosure below.
  • a semiconductor integrated circuit includes a transmission control unit that transmits M-bit (M is an integer of 2 or more) transmission data to a destination circuit every multiple cycles and transmits a strobe signal to the destination circuit to cause the destination circuit to receive the transmission data; a determination unit that determines whether or not the transmission control unit transmits dummy data to the destination circuit before transmitting the transmission-scheduled data to the destination circuit based on the transmission-scheduled data to be transmitted next by the transmission control unit and N pieces of transmitted data transmitted in N cycles (N is an integer of 1 or more) among the transmission data previously transmitted by the transmission control unit; and a dummy data generation unit that generates the dummy data by a predetermined method.
  • M-bit M is an integer of 2 or more
  • the transmission control unit transmits the dummy data to the destination circuit before transmitting the transmission-scheduled data to the destination circuit and performs an invalidation process to invalidate the dummy data in the destination circuit.
  • the determination unit can determine, based on the data to be transmitted and the N pieces of transmitted data, whether or not there is a relatively high possibility that noise that may occur depending on the data pattern will be carried over to the data to be transmitted in the cycle in which the data to be transmitted is scheduled to be transmitted. Therefore, when the possibility is relatively high, the determination unit can determine that the transmission control unit will transmit dummy data to the destination circuit before the transmission control unit transmits the data to be transmitted to the destination circuit. Then, when the determination unit makes such a determination, the transmission control unit transmits dummy data to the destination circuit before transmitting the data to be transmitted.
  • the transmission control unit transmits dummy data without transmitting the data to be transmitted.
  • the transmission control unit may also suppress the transmission of the strobe signal to cause the destination circuit to receive the dummy data as the invalidation process.
  • the transmission control unit may also transmit an invalid flag signal to the destination circuit to invalidate the dummy data in the destination circuit as the invalidation process.
  • N may be 1, and the determination unit may determine that the transmission control unit will transmit the dummy data to the destination circuit before transmitting the data to be transmitted by the transmission control unit when the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the most recently transmitted data transmitted in the most recent cycle among the transmission data previously transmitted by the transmission control unit and the data to be transmitted is greater than a first threshold value.
  • N may be 1
  • M may be an integer equal to or greater than 3
  • the determination unit may determine that the transmission control unit will transmit the dummy data to the destination circuit before transmitting the data to be transmitted by the transmission control unit if the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the most recently transmitted data transmitted in the most recent cycle among the transmission data previously transmitted by the transmission control unit and the data to be transmitted is greater than a first threshold value.
  • N may be an integer equal to or greater than 2
  • the determination unit may determine that the transmission control unit will transmit the dummy data to the destination circuit before transmitting the data to be transmitted to the destination circuit when the bits of 1 in the N pieces of transmitted data are one logical value in all of the N pieces of transmitted data, and the bits of 1 in the data to be transmitted are the other logical value.
  • N may be an integer of 3 or more
  • the determination unit may determine that the transmission control unit transmits the dummy data before transmitting the data to be transmitted by the transmission control unit to the destination circuit when the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the Lth transmitted data transmitted in the latest cycle in the Lth (L is an integer of 3 or more and N or less) among the transmission data previously transmitted by the transmission control unit and the L-1th transmitted data transmitted in the L-1st most recent cycle is greater than a first threshold value, and when the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the latest transmitted data transmitted in the latest cycle among the transmission
  • a semiconductor integrated circuit configured as described above can suppress the deterioration of the signal quality of the transmitted data caused by the increased fluctuation in the potential of the power supply line.
  • N is an integer of 3 or more
  • M is an integer of 3 or more
  • the determination unit targeting a predetermined J bits (J is an integer of 2 or more and less than M) out of the M bits, determines the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the Lth transmitted data transmitted in the latest cycle in the Lth place (L is an integer of 3 or more and less than N) and the L-1th transmitted data transmitted in the L-1th most recent cycle among the transmission data previously transmitted by the transmission control unit.
  • J is an integer of 2 or more and less than M
  • the transmission control unit may determine to transmit the dummy data before transmitting the data to be transmitted to the destination circuit.
  • N may be an integer equal to or greater than 2
  • the determination unit may determine that the transmission control unit will transmit the dummy data before transmitting the data to be transmitted to the destination circuit when the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the latest transmitted data transmitted in the latest cycle among the transmission data previously transmitted by the transmission control unit and the data to be transmitted is greater than a first threshold value when the bits that are 1 in the N pieces of transmitted data are one logical value in all of the N pieces of transmitted data, and the bits that are 1 in the data to be transmitted are the other logical value.
  • N is an integer of 2 or more
  • M is an integer of 3 or more
  • the determination unit may determine that the transmission control unit will transmit the dummy data before transmitting the data to be transmitted to the destination circuit when, for a predetermined J bits (J is an integer of 2 or more and less than M) among the M bits, when a bit of 1 in the N pieces of transmitted data is one logical value in all of the N pieces of transmitted data and a bit of 1 in the data to be transmitted is the other logical value, and when the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the latest transmitted data transmitted in the latest cycle among the transmission data previously transmitted by the transmission control unit and the data to be transmitted is greater than a first threshold value.
  • N is an integer of 2 or more
  • M is an integer of 3 or more
  • the determination unit may determine that the transmission control unit transmits the dummy data to the destination circuit before transmitting the data to be transmitted by the transmission control unit when the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the latest transmitted data transmitted in the latest cycle among the transmission data previously transmitted by the transmission control unit and the data to be transmitted is greater than a first threshold value for a predetermined J bits (J is an integer of 2 or more and less than M) out of the M bits.
  • N is an integer equal to or greater than 3
  • M is an integer equal to or greater than 3
  • the determination unit determines, when the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the Lth transmitted data transmitted in the latest cycle in the Lth (L is an integer equal to or greater than 3 and equal to or less than N) cycle among the transmission data previously transmitted by the transmission control unit, and the L-1th transmitted data transmitted in the L-1st latest cycle, is greater than a first threshold value
  • J is an integer greater than or equal to 2 and less than M
  • N is an integer of 3 or more, and when the bits of 1 in the N pieces of transmitted data are one logical value in all of the N pieces of transmitted data, and the bits of 1 in the data to be transmitted are the other logical value, the determination unit further determines the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 between the Lth transmitted data transmitted in the Lth most recent cycle (L is an integer of 3 or more and N or less) and the L-1th transmitted data transmitted in the L-1th most recent cycle, among the transmission data previously transmitted by the transmission control unit.
  • the transmission control unit may determine to transmit the dummy data before transmitting the data to be transmitted to the destination circuit.
  • the transmission control unit may also transmit the transmission data to the destination circuit via M wires that transmit M-bit signals, and the predetermined J bits may be bits whose signals are transmitted via J wires among the M wires that are adjacent to each other and run parallel for a predetermined length or more.
  • the first threshold may be a variable, and the device may further include a threshold setting unit that sets the first threshold.
  • the first threshold and the second threshold may be variables, and the device may further include a threshold setting unit that sets the first threshold and the second threshold.
  • the first threshold, the second threshold, and the third threshold may be variables, and the device may further include a threshold setting unit that sets the first threshold, the second threshold, and the third threshold.
  • the dummy data generating unit may generate the dummy data consisting of a first bit, which is K bits (K is an integer between 1 and M) out of M bits in the data to be transmitted, and a second bit, which is M-K bits excluding the first bit out of M bits in the most recently transmitted data transmitted in the most recent cycle out of the transmission data previously transmitted by the transmission control unit.
  • the dummy data generation unit may also generate the dummy data that is predetermined.
  • (1) M may be an even number, and the dummy data may have M/2 bits that are one logical value, or (2) M may be an odd number, and the dummy data may have (M+1)/2 bits that are one logical value or the other logical value.
  • the number of bits that transition from one logical value to the other logical value and the number of bits that transition from the other logical value to one logical value can be set to M/2 or less.
  • the dummy data generator may also generate the dummy data by inverting the values of each bit of the transmitted data transmitted in the latest cycle among the N transmitted data.
  • the transmission system includes a transmission control unit that transmits M bits (M is an integer of 2 or more) of transmission data every multiple cycles and transmits a strobe signal to the destination circuit to cause the destination circuit to receive the transmission data, a determination unit that determines whether or not the transmission control unit transmits dummy data to the destination circuit before transmitting the transmission-scheduled data to the destination circuit based on the transmission-scheduled data to be transmitted next by the transmission control unit and N pieces of transmitted data transmitted in N cycles (N is an integer of 1 or more) among the transmission data previously transmitted by the transmission control unit, and a dummy data generation unit that generates the dummy data by a predetermined method, and when the determination unit determines that the transmission control unit transmits the dummy data to the destination circuit before transmitting the transmission-scheduled data to the destination circuit, the transmission control unit transmits the dummy data to the destination circuit before transmitting the transmission-scheduled data to the destination circuit and performs an invalidation process to invalidate the d
  • the determination unit can determine, based on the data to be transmitted and the N pieces of transmitted data, whether or not there is a relatively high possibility that noise that may occur depending on the data pattern will be carried over to the data to be transmitted in the cycle in which the data to be transmitted is scheduled to be transmitted. Therefore, when the possibility is relatively high, the determination unit can determine that the transmission control unit will transmit dummy data to the destination circuit before transmitting the data to be transmitted to the destination circuit. Then, when the determination unit makes such a determination, the transmission control unit transmits dummy data to the destination circuit before transmitting the data to be transmitted.
  • the transmission control unit transmits dummy data without transmitting the data to be transmitted.
  • the data transmission method includes a transmission control step of transmitting M-bit (M is an integer of 2 or more) transmission data to a destination circuit every multiple cycles and transmitting a strobe signal to the destination circuit to cause the destination circuit to receive the transmission data, a determination step of determining whether or not to transmit dummy data to the destination circuit before transmitting the transmission-scheduled data to the destination circuit based on the transmission-scheduled data to be transmitted next and N pieces of transmitted data transmitted in N cycles (N is an integer of 1 or more) among the transmission data transmitted in the past, and a dummy data generation step of generating the dummy data by a predetermined method, and in the transmission control step, if it is determined in the determination step that the dummy data is to be transmitted to the destination circuit before transmitting the transmission-scheduled data to the destination circuit, the dummy data is transmitted to the destination circuit before transmitting the transmission-scheduled data to the destination circuit, and an invalidation process is performed to invalidate the dummy data
  • the determination step it is possible to determine whether or not there is a relatively high possibility that noise that may occur depending on the data pattern will be carried over to the data to be transmitted in the cycle in which the data to be transmitted is scheduled to be transmitted, based on the data to be transmitted and the N pieces of transmitted data. Therefore, in the determination step, if the possibility is relatively high, it can be determined that dummy data will be transmitted to the destination circuit before transmitting the data to be transmitted to the destination circuit. Then, if such a determination is made in the determination step, dummy data is transmitted to the destination circuit before transmitting the data to be transmitted.
  • the above data transmission method makes it possible to suppress deterioration of the signal quality of the transmitted data that can occur depending on the data pattern when transmitting data.
  • FIG. 1 is a block diagram showing a configuration of a transmission system 1 according to a first embodiment.
  • the transmission system 1 includes a semiconductor integrated circuit 10 and a destination circuit 90.
  • the semiconductor integrated circuit 10 transmits M-bit (M is an integer equal to or greater than 2) transmission data to the destination circuit 90 every multiple cycles.
  • the semiconductor integrated circuit 10 also transmits a strobe signal to the destination circuit 90 to cause the destination circuit 90 to receive the transmission data.
  • FIG. 2 is a schematic perspective view showing an example of how the semiconductor integrated circuit 10 transmits transmission data to the destination circuit 90.
  • the semiconductor integrated circuit 10 transmits transmission data to the destination circuit 90 via M wirings 80 formed on a mounting board 70 that mounts the semiconductor integrated circuit 10 and the destination circuit 90, the M wirings 80 being used to transmit each signal of, for example, M bits of transmission data.
  • the semiconductor integrated circuit 10 includes a core block 11, a transmission control unit 20, a determination unit 30, a dummy data generation unit 40, a buffer 21, and a buffer 22.
  • the core block 11 generates M bits of transmission data to be sent to the destination circuit 90, and outputs the generated transmission data to the determination unit 30, the dummy data generation unit 40, and the transmission control unit 20. At this time, the core block 11 repeatedly generates and repeatedly outputs the transmission data. However, if a stop signal (described below) is output from the transmission control unit 20 (described below), the transmission of the transmission data is stopped for one cycle.
  • the core block 11 each time the core block 11 outputs transmission data, it outputs a strobe signal to the transmission control unit 20 to cause the destination circuit 90 to receive the transmission data.
  • the strobe signal is, for example, a signal that is input to a clock input terminal of a flip-flop circuit for acquiring the transmission data in the destination circuit 90.
  • the strobe signal may be, for example, a differential signal consisting of 2 bits, or a 1-bit signal.
  • the strobe signal and the strobe signal described below are described as being differential signals consisting of 2 bits.
  • the transmission control unit 20 receives the M-bit transmission data and strobe signal output from the core block 11, the M-bit dummy data output from the dummy data generation unit 40 described below, and the judgment flag output from the judgment unit 30 described below, and transmits the M-bit transmission data to the destination circuit 90 via the buffer 21 every several cycles, and transmits a strobe signal to the destination circuit 90 via the buffer 22 to cause the destination circuit 90 to receive the transmission data.
  • the transmission data is the transmission data output from the core block 11, or the dummy data output from the dummy data generation unit 40.
  • the judgment flag is a flag indicating the result of the judgment made by the transmission control unit 20 as to whether or not to transmit dummy data before the transmission control unit 20 transmits the transmission-scheduled data, which is the latest transmission data output from the core block 11, to the destination circuit 90.
  • the transmission control unit 20 transmits the data to be transmitted to the transmission destination circuit 90 as transmission data and transmits the strobe signal to the transmission destination circuit 90 as a strobe signal.
  • the transmission destination circuit 90 receives the transmission data transmitted from the transmission control unit 20.
  • the transmission control unit 20 transmits the dummy data to the destination circuit 90 as transmission data and suppresses the transmission of a strobe signal for causing the destination circuit 90 to receive the transmission data, i.e., the dummy data.
  • the destination circuit 90 does not receive the transmission data transmitted from the transmission control unit 20, i.e., the dummy data.
  • the transmission control unit 20 performs a process of suppressing the transmission of a strobe signal to cause the destination circuit 90 to receive the dummy data, as an invalidation process for invalidating the dummy data in the destination circuit 90.
  • the transmission control unit 20 outputs a stop signal to the core block 11 to stop the output of the next transmission data for one cycle.
  • the determination unit 30 receives the M-bit transmission data output from the core block 11 and the M-bit transmission data output from the transmission control unit 20, and determines whether or not the transmission control unit 20 will transmit dummy data before transmitting the transmission-scheduled data to the destination circuit 90, based on the transmission-scheduled data, which is the latest transmission data output from the core block 11, and the N pieces of transmitted data transmitted in N cycles (N is an integer equal to or greater than 1) of the transmission data previously transmitted by the transmission control unit 20 to the destination circuit 90.
  • the determination unit 30 then outputs a determination flag indicating the determination result to the dummy data generation unit 40 and the transmission control unit 20.
  • the determination unit 30 performs the above determination by, for example, storing N pieces of transmitted data and comparing the stored N pieces of transmitted data with the data to be transmitted that is output from the core block 11.
  • FIG. 3 is a schematic diagram showing an example of how the determination unit 30 stores N pieces of transmitted data.
  • FIG. 3 is a schematic diagram showing an example in which M is 8 and N is 5.
  • DQ0 to DQ7 indicate each bit of the transmitted data consisting of an 8-bit signal
  • T5 to T1 indicate the transmitted data transmitted by the transmission control unit 20 in the 5th to 1st cycles before, respectively.
  • the cycle before 1 cycle refers to the most recent cycle in which the transmission control unit 20 transmitted the transmission data to the destination circuit 90.
  • the determination unit 30 stores N (here, 5) pieces of transmitted data of M bits (here, 8 bits) in the chronological order in which they were transmitted by the transmission control unit 20.
  • N is 1.
  • FIGS. 4 and 5 are schematic diagrams showing an example of how the determination unit 30 makes the above determination in a configuration in which the determination unit 30 determines that the transmission control unit 20 will transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90 when the number of bits that transition from a logical value of 0 to a logical value of 1 between the most recently transmitted data and the data to be transmitted is greater than the first threshold value of 4, i.e., 5 or more.
  • DQ0 to DQ7 indicate each bit of the transmitted data and data to be transmitted, which are 8-bit signals
  • T1 indicates the transmitted data transmitted by the transmission control unit 20 in the previous cycle, i.e., the latest cycle
  • T0 indicates the data to be transmitted.
  • the determination unit 30 determines that the transmission control unit 20 will transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90.
  • the determination unit 30 determines that the transmission control unit 20 will not transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90.
  • the first threshold may be a predetermined value or a variable. If it is a variable, for example, as shown in FIG. 6, the semiconductor integrated circuit 10 may further include a threshold setting unit 60, which may set the first threshold.
  • the determination unit 30, for example, (2) targets a predetermined J bits (J is an integer equal to or greater than 2 and less than M) out of the M bits, and if the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the most recently transmitted data and the data to be transmitted is greater than a first threshold value, determines that the transmission control unit 20 will transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90.
  • N is 1
  • M is an integer equal to or greater than 3.
  • the predetermined J bits may be, for example, J wires 80 out of the M wires 80 shown in FIG. 2, and may be bits whose signals are transmitted by J wires 80 that run parallel to each other and are adjacent to each other for a predetermined length or more.
  • the state where J wires 80 run parallel to each other for a predetermined length or more means that when J-bit signals that use these J wires 80 as transmission paths change at the same timing, crosstalk noise is carried over to these J-bit signals due to the interaction between these J-bit signals.
  • FIG. 7 is a schematic diagram showing an example of how the determination unit 30 makes the above determination in a configuration in which the predetermined J bits are three bits, DQ1, DQ2, and DQ5, and the determination unit 30 determines that the transmission control unit 20 will transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90 if the number of bits that transition from logical value 0 to logical value 1 or from logical value 1 to logical value 0 between the most recently transmitted data and the data to be transmitted is greater than the first threshold value of 2, i.e., 3 or more.
  • DQ0 to DQ7 indicate each bit of the transmitted data and data to be transmitted, each of which is an 8-bit signal
  • T1 indicates the transmitted data transmitted by the transmission control unit 20 in the previous cycle, i.e., the most recent cycle
  • T0 indicates the data to be transmitted.
  • the determination unit 30 targets the three bits DQ1, DQ2, and DQ5, and if the number of bits that transition from logical value 0 to logical value 1 or from logical value 1 to logical value 0 between the most recently transmitted data and the data to be transmitted is three, it determines that the transmission control unit 20 will transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90.
  • the first threshold may be a predetermined value or a variable. If it is a variable, for example, as shown in FIG. 6, the semiconductor integrated circuit 10 may further include a threshold setting unit 60, which may set the first threshold.
  • the determination unit 30, for example, (3) determines that the transmission control unit 20 will transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90 when the bit of 1 in the N pieces of transmitted data is one logical value in all of the N pieces of transmitted data and the bit of 1 in the data to be transmitted is the other logical value.
  • N is an integer of 2 or more.
  • one logical value is a logical value of 0
  • the other logical value is a logical value of 1
  • the other logical value is a logical value of 0.
  • FIGS. 8 and 9 are schematic diagrams showing an example of how the determination unit 30 makes the above determination in a configuration in which, when any bit of 1 in the four pieces of transmitted data has one logical value in all four pieces of transmitted data, and the bit of 1 in the data to be transmitted has the other logical value, the transmission control unit 20 determines that the transmission control unit 20 will transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90.
  • DQ0 to DQ7 indicate each bit of the transmitted data and data to be transmitted, which are 8-bit signals
  • T4 to T1 indicate the transmitted data transmitted by the transmission control unit 20 in the 4th to 1st cycles ago, respectively
  • T0 indicates the data to be transmitted.
  • the determination unit 30 determines that the transmission control unit 20 will transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90.
  • the determination unit 30 determines that the transmission control unit 20 will not transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90.
  • the determination unit 30, for example, (4) determines that the transmission control unit 20 transmits dummy data before transmitting the data to be transmitted to the destination circuit 90 when the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the Lth transmitted data transmitted in the latest cycle in the Lth (L is an integer between 3 and N) among the transmission data previously transmitted by the transmission control unit 20 and the L-1th transmitted data transmitted in the L-1th latest cycle is greater than a first threshold value, and the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the latest transmitted data and the data to be transmitted is greater than a second threshold value.
  • N is an integer greater than
  • FIG. 10 is a schematic diagram showing an example of how the determination unit 30 makes the above determination in a configuration in which the determination unit 30 determines that the transmission control unit 20 will transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90 when the number of bits that transition from a logical value of 0 to a logical value of 1 between the transmitted data T4 transmitted by the transmission control unit 20 in the cycle four cycles ago and the transmitted data T3 transmitted by the transmission control unit 20 in the cycle three cycles ago is greater than a first threshold value of 4, i.e., 5 or more, and when the number of bits that transition from a logical value of 0 to a logical value of 1 between the latest transmitted data T1 and the data to be transmitted T0 is greater than a second threshold value of 4, i.e., 5 or more.
  • a first threshold value of 4 i.e., 5 or more
  • a second threshold value of 4 i.e., 5 or more.
  • DQ0 to DQ7 indicate each bit of the transmitted data and data to be transmitted, which are 8-bit signals
  • T4 to T1 indicate the transmitted data transmitted by the transmission control unit 20 in the 4th to 1st cycles ago, respectively
  • T0 indicates the data to be transmitted.
  • the determination unit 30 determines that the transmission control unit 20 will transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90.
  • the first threshold and/or the second threshold may be a predetermined value or may be a variable. If they are variables, for example, as shown in FIG. 6, the semiconductor integrated circuit 10 may further include a threshold setting unit 60, which may set the first threshold and/or the second threshold.
  • the determination unit 30 targets a predetermined J bits (J is an integer greater than or equal to 2 and less than M) out of the M bits, and determines that the transmission control unit 20 will transmit dummy data before transmitting the data to be transmitted to the destination circuit 90 when the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the Lth transmitted data transmitted in the most recent cycle in the Lth place (L is an integer greater than or equal to 3 and less than N) and the L-1th transmitted data transmitted in the L-1st most recent cycle among the transmission data previously transmitted by the transmission control unit 20 is greater than a first threshold value, and when the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and
  • the first threshold and/or the second threshold may be a predetermined value or may be a variable. If they are variables, for example, as shown in FIG. 6, the semiconductor integrated circuit 10 may further include a threshold setting unit 60, which may set the first threshold and/or the second threshold.
  • N is an integer of 2 or more.
  • FIG. 11 is a schematic diagram showing an example of how the determination unit 30 makes the above determination in a configuration in which the determination unit 30 determines that the transmission control unit 20 will transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90 when the number of bits that transition from a logical value of 0 to a logical value of 1 between the latest transmitted data and the data to be transmitted is greater than the first threshold value of 4, i.e., 5 or more, when any bit that is 1 in four transmitted data pieces has one logical value in all four transmitted data pieces and the bit that is 1 in the data to be transmitted has the other logical value.
  • the first threshold value of 4 i.e., 5 or more
  • DQ0 to DQ7 indicate each bit of the transmitted data and data to be transmitted, which are 8-bit signals
  • T4 to T1 indicate the transmitted data transmitted by the transmission control unit 20 in the 4th to 1st cycles ago, respectively
  • T0 indicates the data to be transmitted.
  • the determination unit 30 determines that the transmission control unit 20 will transmit dummy data to the destination circuit 90 before transmitting the to-be-transmitted data to the destination circuit 90.
  • the first threshold may be a predetermined value or a variable. If it is a variable, for example, as shown in FIG. 6, the semiconductor integrated circuit 10 may further include a threshold setting unit 60, which may set the first threshold.
  • the determination unit 30, for example, (7) targets a predetermined J bits (J is an integer equal to or greater than 2 and less than M) out of the M bits, and when a bit of 1 in N pieces of transmitted data is one logical value in all of the N pieces of transmitted data, and the bit of 1 in the data to be transmitted is the other logical value, and when the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the latest transmitted data and the data to be transmitted is greater than a first threshold value, determines that the transmission control unit 20 will transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90.
  • N is an integer equal to or greater than 2
  • M is an integer equal to or greater than 3.
  • the first threshold may be a predetermined value or a variable. If it is a variable, for example, as shown in FIG. 6, the semiconductor integrated circuit 10 may further include a threshold setting unit 60, which may set the first threshold.
  • the determination unit 30 for example, (8) when a bit of 1 in N pieces of transmitted data is one logical value in all of the N pieces of transmitted data, and the bit of 1 in the data to be transmitted is the other logical value, and, for a predetermined J bits (J is an integer greater than or equal to 2 and less than M) among the M bits, determines that the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the latest transmitted data and the data to be transmitted is greater than a first threshold value.
  • J is an integer greater than or equal to 2 and less than M
  • N is an integer greater than or equal to 2
  • M is an integer greater than or equal to 3.
  • one logical value is logical value 0
  • the other logical value is logical value 1
  • the other logical value is logical value 0.
  • the first threshold may be a predetermined value or a variable. If it is a variable, for example, as shown in FIG. 6, the semiconductor integrated circuit 10 may further include a threshold setting unit 60, which may set the first threshold.
  • the determination unit 30, for example, (9) determines the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the Lth transmitted data transmitted in the most recent cycle in the Lth place (L is an integer greater than or equal to 3 and less than or equal to N) and the L-1th transmitted data transmitted in the L-1st most recent cycle among the transmission data previously transmitted by the transmission control unit 20, when the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, between the most recently transmitted data and the data to be transmitted is greater than a first threshold value.
  • the first threshold, the second threshold, and/or the third threshold may be a predetermined value or may be a variable. If they are variables, for example, as shown in FIG. 6, the semiconductor integrated circuit 10 may further include a threshold setting unit 60, which may set the first threshold, the second threshold, and/or the third threshold.
  • the determination unit 30 determines the number of bits that transition from logical value 0 to logical value 1, and the number of bits that transition from logical value 1 to logical value 0 between the Lth transmitted data transmitted in the Lth most recent cycle (L is an integer between 3 and N) and the L-1th transmitted data transmitted in the L-1th most recent cycle, among the transmission data previously transmitted by the transmission control unit 20.
  • N is an integer of 3 or more.
  • the dummy data generator 40 receives the M-bit transmission data output from the core block 11, the M-bit transmission data output from the transmission control unit 20, and the determination flag output from the determination unit 30, generates dummy data using a predetermined method, and outputs the generated dummy data to the transmission control unit 20.
  • the dummy data generator 40 generates dummy data consisting of, for example, (1) a first bit, which is K bits (K is an integer between 1 and M) out of M bits in the data to be transmitted, and a second bit, which is M-K bits excluding the first bit out of M bits in the most recently transmitted data.
  • FIG. 12 is a schematic diagram showing an example of how the dummy data generator 40 generates dummy data consisting of first bits, which are the three bits DQ0, DQ4, and DQ6 in the data to be transmitted, and second bits, which are the five bits DQ1, DQ2, DQ3, DQ5, and DQ7 in the most recently transmitted data.
  • DQ0 to DQ7 indicate each bit of the transmitted data and data to be transmitted, each of which is an 8-bit signal
  • T1 indicates the transmitted data transmitted by the transmission control unit 20 in the previous cycle, i.e., the latest cycle
  • T0 indicates the data to be transmitted
  • TD indicates dummy data.
  • the dummy data generation unit 40 for example, (2) generates predetermined dummy data.
  • DQ0 to DQ7 indicate each bit of the transmitted data and data to be transmitted, each of which is an 8-bit signal
  • T1 indicates the transmitted data transmitted by the transmission control unit 20 in the previous cycle, i.e., the latest cycle
  • T0 indicates the data to be transmitted
  • TD indicates dummy data.
  • the dummy data generator 40 for example, (3) generates dummy data in which the values of each bit of the transmitted data sent in the latest cycle are inverted.
  • FIG. 14 is a schematic diagram showing an example of how the dummy data generator 40 generates dummy data in which the values of each bit of the transmitted data sent in the latest cycle are inverted.
  • DQ0 to DQ7 indicate each bit of the transmitted data and data to be transmitted, each of which is an 8-bit signal
  • T1 indicates the transmitted data transmitted by the transmission control unit 20 in the previous cycle, i.e., in the latest cycle
  • T0 indicates the data to be transmitted
  • TD indicates dummy data.
  • the destination circuit 90 receives the transmission data sent from the semiconductor integrated circuit 10 using the strobe signal sent from the semiconductor integrated circuit 10.
  • the destination circuit 90 includes a receiving circuit 92 and a core block 91.
  • the receiving circuit 92 is composed of M flip-flop circuits, each of which receives an M-bit transmission signal at its data input terminal, and each of which receives a strobe signal at its clock input terminal.
  • the receiving circuit 92 receives the transmission data sent from the semiconductor integrated circuit 10 at the timing when the strobe signal (here, a 2-bit differential signal) changes.
  • the strobe signal here, a 2-bit differential signal
  • the transmission control unit 20 when the transmission control unit 20 transmits dummy data to the destination circuit 90 as transmission data, it suppresses the transmission of a strobe signal to cause the destination circuit 90 to receive the dummy data. On the other hand, when the transmission control unit 20 transmits data to be transmitted to the destination circuit 90 as transmission data, it transmits a strobe signal to cause the destination circuit 90 to receive the data to be transmitted.
  • the receiving circuit 92 does not receive dummy data from the transmission data sent from the semiconductor integrated circuit 10, but only receives the data to be transmitted.
  • the core block 91 performs various signal processing using the transmission data received by the receiving circuit 92.
  • the transmission system 1 executes a first data transmission process to transmit the transmission data to the destination circuit 90.
  • the first data transmission process is started, for example, when the transmission system 1 is started.
  • FIG. 15 is a flowchart of the first data transmission process.
  • the determination unit 30 waits until new transmission data is output from the core block 11 (step S10: No is repeated), and when new transmission data is output from the core block 11 (step S10: Yes), it checks whether the transmission control unit 20 has transmitted N pieces of transmission data consecutively in the latest N cycles (N is an integer equal to or greater than 1) (step S20).
  • step S20 if the transmission control unit 20 has transmitted N pieces of transmission data consecutively in the latest N cycles (N is an integer equal to or greater than 1) (step S20: Yes), the determination unit 30 determines whether or not the transmission control unit 20 transmits dummy data to the destination circuit 90 before transmitting the transmission planned data to the destination circuit 90, based on the transmission planned data, which is data to be transmitted newly output from the core block 11, and the N pieces of transmitted data transmitted in the latest N cycles among the transmission data previously transmitted by the transmission control unit 20 (step S30).
  • step S30 if the determination unit 30 determines that the transmission control unit 20 will transmit dummy data to the destination circuit 90 before the transmission control unit 20 transmits the data to be transmitted to the destination circuit 90 (step S30: Yes), the dummy data generation unit 40 generates dummy data (step S40).
  • the transmission control unit 20 transmits the dummy data as transmission data to the destination circuit 90 and suppresses the transmission of the transmission data, i.e., the strobe signal for causing the destination circuit 90 to receive the dummy data (step S50).
  • the destination circuit 90 then does not receive the transmission data (step S60).
  • the transmission control unit 20 transmits the transmission data to the destination circuit 90 as transmission data, and transmits the transmission data, i.e., the strobe signal for causing the destination circuit 90 to receive the transmission data to the destination circuit 90 (step S70).
  • the destination circuit 90 then receives the transmission data (step S90).
  • step S20 If, in the process of step S20, the transmission control unit 20 has not transmitted N pieces of transmission data consecutively in the most recent N cycles (step S20: No), and if, in the process of step S30, the determination unit 30 determines that the transmission control unit 20 will not transmit dummy data to the destination circuit 90 before the transmission control unit 20 transmits the data to be transmitted to the destination circuit 90 (step S30: No), the transmission control unit 20 transmits the transmission data to the destination circuit 90 as transmission data, and transmits a strobe signal to the destination circuit 90 to cause the destination circuit 90 to receive the transmission data, i.e., the transmission data (step S80). The destination circuit 90 then receives the transmission data (step S90).
  • step S90 the core block 11 checks whether there is a request to send new transmission data (step S100).
  • step S100 If there is a request to send new transmission data in the process of step S100 (step S100: Yes), the process proceeds again to step S10.
  • step S100: No If there is no request to transmit new transmission data in the process of step S100 (step S100: No), the transmission system 1 ends the first data transmission process.
  • the determination unit 30 can determine whether or not there is a relatively high possibility that noise that may occur depending on a data pattern will be carried on the transmission-scheduled data in a cycle in which the transmission-scheduled data is to be transmitted, based on the transmission-scheduled data and the N pieces of transmitted data. Therefore, when the possibility is relatively high, the determination unit 30 can determine that the transmission control unit 20 transmits dummy data to the transmission destination circuit 90 before the transmission control unit 20 transmits the transmission-scheduled data to the transmission destination circuit 90. Then, when the determination unit 30 makes such a determination, the transmission control unit 20 transmits dummy data to the transmission destination circuit 90 before transmitting the transmission-scheduled data.
  • the transmission control unit 20 transmits dummy data without transmitting the transmission-scheduled data.
  • the semiconductor integrated circuit 10 configured as above can suppress degradation of the signal quality of the transmitted data that can occur depending on the data pattern when transmitting data.
  • FIG. 16 is an example of a timing chart showing how a semiconductor integrated circuit according to a comparative example, which is configured assuming that the semiconductor integrated circuit 10 according to the first embodiment does not have the function of transmitting dummy data to the destination circuit 90, transmits nine consecutive cycles of transmitted data to the destination circuit 90, and then transmits data to be transmitted to the destination circuit 90 without transmitting dummy data to the destination circuit 90.
  • FIG. 17 is an example of a timing chart showing how the semiconductor integrated circuit 10 according to the first embodiment transmits nine consecutive cycles of transmitted data to the destination circuit 90, then transmits dummy data to the destination circuit 90, and then transmits data to be transmitted to the destination circuit 90.
  • DQ0 to DQ7 indicate each bit of the transmitted data and data to be transmitted, which are 8-bit signals
  • DQS indicates a strobe signal
  • T9 to T1 indicate the transmitted data transmitted by the transmission control unit 20 in the 9th to 1st cycles ago, respectively
  • T0 indicates data to be transmitted
  • TD indicates dummy data.
  • the semiconductor integrated circuit according to the comparative example transmits the transmitted data T9-T1 to the destination circuit 90 in nine consecutive cycles, and then transmits the to-be-sent data T0 to the destination circuit 90
  • the semiconductor integrated circuit 10 suppresses the transmission of the strobe signal DQS to cause the destination circuit 90 to receive the dummy data TD.
  • the value of 8 bits simultaneously transitions between the transmitted data T1, i.e., the most recently transmitted data T1, and the data to be transmitted T0.
  • the data to be transmitted T0 is affected by noise such as simultaneous switching noise and crosstalk noise caused by the 8 bits toggling at once (hereinafter also referred to as "8-bit toggle noise").
  • the value of four bits simultaneously transitions between the dummy data TD and the data to be sent T0.
  • the data to be sent T0 is affected by noise such as simultaneous switching noise and crosstalk noise caused by the four bits toggling at the same time (hereinafter also referred to as "toggle noise for four bits").
  • toggle noise of 4 bits will be smaller than toggle noise of 8 bits.
  • the semiconductor integrated circuit 10 can suppress adverse effects of noise such as simultaneous switching noise and crosstalk noise that may occur depending on the data pattern when transmitting data, compared to the semiconductor integrated circuit of the comparative example.
  • the semiconductor integrated circuit 10 can suppress deterioration of the signal quality of the transmitted data that may occur depending on the data pattern when transmitting data, compared to the semiconductor integrated circuit of the comparative example.
  • bit DQ0 has a logical value of 0 for seven consecutive cycles from transmitted data T7 to T1, and then has a logical value of 1 in data to be transmitted T0.
  • the effect of jitter due to inter-symbol noise in bit DQ0 of data to be transmitted T0 reduces the timing margin for correctly receiving bit DQ0 of data to be transmitted T0 relative to strobe signal DQS in destination circuit 90, making it relatively likely that destination circuit 90 will not be able to correctly receive bit DQ0 of data to be transmitted T0.
  • the semiconductor integrated circuit 10 suppresses the transmission of a strobe signal DQS for causing the destination circuit 90 to receive the dummy data TD. Therefore, as shown in FIG. 17, in the destination circuit 90, a sufficiently large timing margin for the strobe signal DQS is provided for correctly receiving the bit DQ0 of the data to be transmitted T0. Therefore, the destination circuit 90 can correctly receive the bit DQ0 of the data to be transmitted T0.
  • the semiconductor integrated circuit 10 can suppress the adverse effects of inter-symbol noise that can occur depending on the data pattern when transmitting data, compared to the semiconductor integrated circuit of the comparative example. In other words, the semiconductor integrated circuit 10 can suppress the degradation of signal quality of transmitted data that can occur depending on the data pattern when transmitting data, compared to the semiconductor integrated circuit of the comparative example.
  • the transmission control unit 20 will transmit dummy data to the transmission destination circuit 90 before transmitting the data to be transmitted to the transmission destination circuit 90, and this can suppress deterioration of the signal quality of the transmission data due to simultaneous switching noise and/or crosstalk noise.
  • the semiconductor integrated circuit 10 may further include a threshold setting unit 60 that sets the first threshold. This makes it possible to adjust the degree of suppression of degradation of the signal quality of the transmission data according to the allowable rate of insertion of dummy data.
  • the transmission control unit 20 will transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90, degradation of the signal quality of the transmitted data due to crosstalk noise between the signals of the specific J bits can be suppressed.
  • the semiconductor integrated circuit 10 transmits the transmission data to the destination circuit 90 via M wirings 80 that transmit each signal of the M-bit transmission data, the M wirings 80 being formed on a mounting board 70 that mounts the semiconductor integrated circuit 10 and the destination circuit 90, and the predetermined J bits may be bits whose signals are transmitted by J wirings out of the M wirings that run in parallel adjacent to each other for a predetermined length or more.
  • a specific J-bit signal can be bits whose signals are transmitted by J wirings that run in parallel adjacent to each other for a predetermined length or more.
  • the transmission control unit 20 transmits dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90, it is possible to suppress deterioration of the signal quality of the transmitted data due to intersymbol interference noise.
  • the transmission control unit 20 determines that the transmission control unit 20 will transmit dummy data before transmitting the data to be transmitted to the destination circuit 90, deterioration of the signal quality of
  • the determination unit 30 determines whether (5) for a predetermined J bits (J is an integer equal to or greater than 2 and less than M) among the M bits, the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the Lth transmitted data transmitted in the Lth (L is an integer equal to or greater than 3 and less than N) most recent cycle and the L-1th transmitted data transmitted in the L-1th most recent cycle among the transmission data previously transmitted by the transmission control unit 20 is greater than a first threshold value.
  • J is an integer equal to or greater than 2 and less than M
  • the transmission control unit 20 determines to transmit dummy data before transmitting the data to be transmitted to the destination circuit 90, it is possible to suppress deterioration of the signal quality of the transmitted data due to increased fluctuations in the potential of the power supply line caused by a specific J-bit signal.
  • the transmission control unit 20 transmits dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90, and it is possible to suppress deterioration of the signal quality of the transmitted data due to the simultaneous occurrence of intersymbol interference noise, simultaneous switching noise, and/or crosstalk noise.
  • the determination unit 30 (7) targets a predetermined J bits (J is an integer equal to or greater than 2 and less than M) among the M bits, and when a bit of 1 in N pieces of transmitted data is one logical value in all of the N pieces of transmitted data, and the bit of 1 in the data to be transmitted is the other logical value, and when the number of bits that transition from logical value 0 to logical value 1, the number of bits that transition from logical value 1 to logical value 0, or the number of bits that transition from logical value 0 to logical value 1 and from logical value 1 to logical value 0 between the latest transmitted data and the data to be transmitted is greater than a first threshold value, if the determination unit 30 determines that the transmission control unit 20 will transmit dummy data to the destination circuit 90 before transmitting the data to be transmitted to the destination circuit 90, it is possible to suppress deterioration of the signal quality of the transmitted data caused by the simultaneous occurrence of intersymbol interference noise in a specific J-bit signal and simultaneous switching noise and/or crosstalk
  • the dummy data generator 40 when the dummy data generator 40 generates dummy data consisting of (1) a first bit that is K bits (K is an integer between 1 and M) out of M bits in the data to be transmitted, and a second bit that is M-K bits excluding the first bit out of M bits in the most recently transmitted data, the number of bits whose values change simultaneously can be set to max(K, M-K) or less. This also makes it possible to suppress degradation of the signal quality of the transmitted data due to inter-symbol interference noise for the first bit.
  • the dummy data generating unit 40 (2) when the dummy data generating unit 40 (2) generates predetermined dummy data, it is possible to realize the generation of dummy data using a circuit with a relatively simple configuration.
  • M may be an even number and the number of bits that become one logical value may be M/2, or M may be an odd number and the number of bits that become one logical value or the number of bits that become the other logical value may be (M+1)/2.
  • M may be an even number and the number of bits that become one logical value or the number of bits that become the other logical value may be M/2, or M may be an odd number and the number of bits that become one logical value or the number of bits that become the other logical value may be (M+1)/2.
  • FIG. 18 is a block diagram showing the configuration of a transmission system 1A according to embodiment 2.
  • the transmission system 1A is configured by changing the semiconductor integrated circuit 10 to a semiconductor integrated circuit 10A and changing the destination circuit 90 to a destination circuit 90A, in comparison with the transmission system 1 according to the first embodiment.
  • semiconductor integrated circuit 10A is configured by changing transmission control unit 20 to transmission control unit 20A and adding buffer 23 to semiconductor integrated circuit 10.
  • the destination circuit 90A is configured by adding an invalidation unit 94 and a receiving circuit 93 to the destination circuit 90.
  • the explanation of the other components in the transmission system 1A is the same as if the transmission control unit 20 had been read as the transmission control unit 20A, the semiconductor integrated circuit 10 had been read as the semiconductor integrated circuit 10A, and the destination circuit 90 had been read as the destination circuit 90A.
  • the transmission control unit 20 When the determination unit 30 outputs a determination flag indicating the determination result that the transmission control unit 20 has determined to transmit dummy data before the transmission control unit 20 transmits the data to be transmitted to the destination circuit 90, the transmission control unit 20 according to the first embodiment performs a process of suppressing the transmission of a strobe signal for causing the destination circuit 90 to receive the dummy data as an invalidation process for invalidating the dummy data in the destination circuit 90.
  • the transmission control unit 20A performs a process of transmitting an invalid flag signal for invalidating the dummy data in the destination circuit 90 via the buffer 23 to the destination circuit 90A as an invalidation process for invalidating the dummy data in the destination circuit 90.
  • the transmission control unit 20A transmits the strobe signal to the destination circuit 90A without performing a process of suppressing the transmission of a strobe signal for causing the destination circuit 90 to receive the dummy data.
  • the transmission control unit 20A transmits the data to be transmitted as transmission data to the transmission destination circuit 90A and transmits a strobe signal as a strobe signal to the transmission destination circuit 90A. In this case, the transmission control unit 20A does not transmit an invalid flag signal to the transmission destination circuit 90A.
  • the receiving circuit 93 is composed of a flip-flop circuit whose data input terminal receives an invalid flag signal and whose clock input terminal receives a strobe signal.
  • the receiving circuit 93 receives the invalid flag signal sent from the semiconductor integrated circuit 10 at the timing when the strobe signal (here, a 2-bit differential signal) changes.
  • the invalidation unit 94 receives the transmission data received by the receiving circuit 92 and the invalidation flag signal received by the receiving circuit 93.
  • the invalidation unit 94 When transmission data is input from the receiving circuit 92, and an invalid flag signal is not input from the receiving circuit 93, the invalidation unit 94 outputs the transmission data to the core block 91. On the other hand, when transmission data is input from the receiving circuit 92, and an invalid flag signal is input from the receiving circuit 93, the invalidation unit 94 invalidates the transmission data, i.e., does not output the reception data to the core block 91.
  • the core block 91 receives the transmission data sent from the semiconductor integrated circuit 10A as transmission data, but does not receive the dummy data sent as transmission data.
  • Transmission system 1A executes a second data transmission process in which some processing has been changed from the first data transmission process according to embodiment 1.
  • FIG. 19 is a flowchart of the second data transmission process.
  • steps S110 to S140 is the same as the processing of steps S10 to S40 in the first data transmission processing, except that the transmission control unit 20 is replaced with the transmission control unit 20A, the semiconductor integrated circuit 10 is replaced with the semiconductor integrated circuit 10A, and the destination circuit 90 is replaced with the destination circuit 90A.
  • step S150 the processing from step S150 to step S200.
  • the transmission control unit 20A transmits the dummy data as transmission data to the destination circuit 90, transmits a strobe signal to cause the destination circuit 90 to receive the transmission data, i.e., the dummy data, and further transmits an invalid flag signal to the destination circuit 90 (step S150).
  • the destination circuit 90A then receives the transmission data (step S160) and also receives the invalid flag signal.
  • the invalidation unit 94 invalidates the transmission data, i.e., the dummy data (step S165). That is, the invalidation unit 94 does not output the transmission data, i.e., the dummy data, to the core block 91. Therefore, the dummy data is not input to the core block 91. Then, in the cycle following the transmission of the dummy data, the transmission control unit 20A transmits the transmission data as transmission data to the destination circuit 90, and transmits a strobe signal to the destination circuit 90A to cause the destination circuit 90 to receive the transmission data, i.e., the transmission data, but does not transmit the invalid flag signal to the destination circuit 90A (step S170). Then, the destination circuit 90A receives the transmission data (step S190), but does not receive the invalid flag signal. Therefore, the transmission data is not invalidated (step S195), and the transmission data is input to the core block 91.
  • step S120 if the transmission control unit 20A has not transmitted N pieces of transmission data consecutively in the latest N cycles (step S120: No), and in the process of step S130, if the determination unit 30 determines that the transmission control unit 20A will not transmit dummy data to the transmission destination circuit 90A before the transmission control unit 20 transmits the data to be transmitted to the transmission destination circuit 90A (step S130: No), the transmission control unit 20A transmits the transmission data as transmission data to the transmission destination circuit 90A, and transmits a strobe signal to the transmission destination circuit 90A to cause the transmission data, i.e., the transmission data, to be received by the transmission destination circuit 90, but does not transmit an invalid flag signal to the transmission destination circuit 90A (step S180). Then, the transmission destination circuit 90A receives the transmission data (step S190), but does not receive the invalid flag signal. Therefore, the transmission data is not invalidated (step S195), and the transmission data is input to the core block 91.
  • step S195 the core block 11 checks whether there is a request to send new transmission data (step S200).
  • step S200 If there is a request to send new transmission data in the process of step S200 (step S200: Yes), the process proceeds again to step S110.
  • step S200 If there is no request to transmit new transmission data in the processing of step S200 (step S200: No), the transmission system 1A ends the second data transmission processing.
  • This disclosure can be widely used in semiconductor integrated circuits, transmission systems, and the like that transmit data.
  • REFERENCE SIGNS LIST 1 1A Transmission system 10, 10A Semiconductor integrated circuit 11, 91 Core block 20, 20A Transmission control unit 21, 22, 23 Buffer 30 Determination unit 40 Dummy data generation unit 60 Threshold setting unit 70 Mounting board 80 Wiring 90, 90A Destination circuit 92, 93 Reception circuit 94 Invalidation unit

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PCT/JP2023/042305 2022-11-29 2023-11-27 半導体集積回路、伝送システム、および、データ伝送方法 Ceased WO2024117064A1 (ja)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025047724A1 (ja) * 2023-08-31 2025-03-06 ヌヴォトンテクノロジージャパン株式会社 半導体集積回路およびデータ転送方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56126352A (en) * 1980-03-10 1981-10-03 Nec Corp Data transmission device
JPS57184354A (en) * 1981-05-08 1982-11-13 Nec Corp Digital transmitter
JP2007304797A (ja) * 2006-05-10 2007-11-22 Seiko Epson Corp データアクセス回路、デコード装置、情報再生装置及び電子機器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56126352A (en) * 1980-03-10 1981-10-03 Nec Corp Data transmission device
JPS57184354A (en) * 1981-05-08 1982-11-13 Nec Corp Digital transmitter
JP2007304797A (ja) * 2006-05-10 2007-11-22 Seiko Epson Corp データアクセス回路、デコード装置、情報再生装置及び電子機器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025047724A1 (ja) * 2023-08-31 2025-03-06 ヌヴォトンテクノロジージャパン株式会社 半導体集積回路およびデータ転送方法

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