WO2024113844A1 - 内存访问方法及相关装置 - Google Patents

内存访问方法及相关装置 Download PDF

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Publication number
WO2024113844A1
WO2024113844A1 PCT/CN2023/104219 CN2023104219W WO2024113844A1 WO 2024113844 A1 WO2024113844 A1 WO 2024113844A1 CN 2023104219 W CN2023104219 W CN 2023104219W WO 2024113844 A1 WO2024113844 A1 WO 2024113844A1
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Prior art keywords
memory
target
memory space
mirror
cache
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PCT/CN2023/104219
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English (en)
French (fr)
Inventor
潘伟
李炜建
吴平宇
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华为技术有限公司
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Publication of WO2024113844A1 publication Critical patent/WO2024113844A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

Definitions

  • the present application relates to the field of computers, and in particular to a memory access method and related devices.
  • Memory mirroring is a memory protection technology.
  • the memory space with memory mirroring function enabled includes main memory space and backup memory space.
  • the main memory space is used for the memory controller to read data
  • the backup memory space is used to save the backup of the data in the main memory space.
  • the computer device can recover the data from the other memory space, thereby improving memory stability and availability.
  • the related technology provides a memory access method based on dynamic memory mirroring.
  • this method after receiving a memory access instruction, it is determined whether the target memory space has enabled the dynamic memory mirroring function based on the page table entries in the target memory space to be accessed by the memory access instruction. If the target memory space has enabled the dynamic memory mirroring function, the operation corresponding to the memory access instruction is executed on both the main memory space and the backup memory space included in the target memory space.
  • the above method may result in low efficiency of memory access in the process of implementing dynamic memory mirroring.
  • the present application provides a memory access method and related devices, which can improve the security of mirror memory data.
  • the technical solution is as follows:
  • a memory access method comprising: a cache controller receiving a memory access instruction sent by a processor core, the memory access instruction being used to access a target memory space; the cache controller determining whether the target memory space is a mirror memory space based on mirror indication information of a target cache line corresponding to the memory access instruction in a cache.
  • the cache controller After the cache controller receives the memory access instruction sent by the processor core, it determines whether the target memory space is a mirror memory space through the mirror indication information of the target cache line corresponding to the memory access instruction. There is no need to determine whether the target memory space is a mirror memory space by accessing the memory, which can avoid the problem of increased delay caused by obtaining the mirror indication information in the memory, thereby improving the efficiency of memory access.
  • a cache typically includes multiple cache lines, each of which includes a data area and a non-data area, the data area is used to store a portion of data in the memory, and the non-data area includes a mirror indication field, the mirror indication field is used to record mirror indication information, and the mirror indication information is used to indicate whether the space in the memory where the data stored in the data area is located is a mirror memory space. Therefore, for a target cache line, the target cache line includes a data area and a non-data area, the data area stores the data to be accessed, and the non-data area includes a mirror indication field, and the mirror indication field is used to record the mirror indication information.
  • the target cache line may not exist in the cache.
  • the mirror indication information can be obtained from the memory to determine whether the target memory space is a mirror memory space. That is, if the target cache line does not exist in the cache, the cache controller determines whether the target memory space is a mirror memory space based on the mirror indication information of the target non-data area corresponding to the memory access instruction in the target memory space.
  • the target cache line does not exist in the cache, it is also possible to determine whether the target memory space is a mirror memory space through the mirror indication information in the target memory space, so that the reliability of memory access can be guaranteed.
  • the target memory space includes multiple data areas and multiple non-data areas, and the multiple data areas are paired with the multiple non-data areas one by one.
  • the non-data area includes mirror indication information, and the mirror indication information indicates whether the memory space where the data in the corresponding data area is located is a mirror memory space. Therefore, for the target non-data area, there is also a target data area corresponding to the target non-data area in the target memory space. That is, the target memory space includes a target data area and the target non-data area, the target data area stores the data to be accessed, and the target non-data area stores the mirror indication information.
  • the cache controller executes an operation corresponding to the memory access instruction on the target memory space.
  • the cache controller refuses to execute the memory access instruction if the target memory space is a mirrored memory space and the memory access instruction is in a non-mirrored access mode.
  • the cache controller can refuse to execute the memory access instruction. In this way, illegal access to the mirror memory data can be avoided, thereby improving the security of the mirror memory data.
  • the cache controller performs an operation corresponding to the memory access instruction on the target memory space.
  • the mirror configuration information of the target memory space can be set when the target memory space is allocated, that is, the mirror configuration information of the target memory space is set in advance.
  • the mirror configuration information of the target memory space can also be adjusted according to different requirements.
  • the memory access instruction is a memory write instruction, which carries target data to be written, and the target memory space includes a main memory space and a backup memory space; at this time, the cache controller executes the operation corresponding to the memory access instruction on the target memory space, including: the cache controller sends a memory write notification to the memory controller to instruct the memory controller to write the target data in both the main memory space and the backup memory space.
  • the target memory space is allocated for the target object in advance. That is, a memory allocation request of the target object is received, the memory allocation request is used to request the target memory space; in response to the mirror flag of the target object being set, the target memory space is allocated for the target object, and the mirror indication information of each non-data area in the target memory space is set.
  • the target object refers to a software module in a computer device that is allowed to occupy memory space.
  • the target object includes but is not limited to a process, a kernel, a portion of a VMA segment of a process, a portion of a module in the kernel, etc.
  • the memory allocation request indicates that a target memory space is allocated for the target object.
  • different types of target objects have different image flags. For example, the image flag of the kernel is different from the image flag of the process.
  • the embodiment of the present application can determine whether it is necessary to enable the memory mirroring function for the memory space allocated for the target object according to the needs of the target object.
  • mirror protection is used for the memory actually requested to be allocated when the target object is running, so as to avoid waste of memory resources caused by preset too large mirror memory and avoid business interruption caused by insufficient preset mirror memory.
  • the memory mirroring function of the target memory space can also be cancelled, so as to facilitate the recovery of the memory space. That is, a memory release request of the target object is received, and the memory release request is used to release the target memory space; the target memory space allocated for the target object is released, and the mirroring indication information of each non-data area in the target memory space is cancelled.
  • a processor comprising a cache controller, and the cache controller is used to implement the method provided in the first aspect.
  • a memory access device comprising a processor and a memory, the memory being used to store a computer program for executing the memory access method provided in the first aspect.
  • the processor is configured to execute the computer program stored in the memory to implement the memory access method described in the first aspect.
  • the memory access device may further include a communication bus, and the communication bus is used to establish a connection between the processor and the memory.
  • a computer-readable storage medium stores instructions, and when the instructions are executed on a computer, the computer executes the memory access method described in the first aspect.
  • a computer program product comprising instructions is provided, and when the instructions are executed on a computer, the computer executes the steps of the memory access method described in the first aspect.
  • a computer program is provided, and when the computer program is executed on a computer, the computer executes the memory access method described in the first aspect.
  • FIG1 is a schematic diagram of the structure of a computer device provided in an embodiment of the present application.
  • FIG2 is a flow chart of a memory access method provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of the structure of a cache line and a memory provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of a method for processing a memory read instruction provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of a method for processing a memory write instruction provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of the structure of a memory access device provided in an embodiment of the present application.
  • the memory space with the memory mirroring function enabled includes two independent physical memory spaces.
  • One physical memory space is used as the primary memory space, and the other physical memory space is used as the backup memory space.
  • the data is written to both the primary memory space and the backup memory space at the same time, so that two identical copies of the data exist in the memory.
  • the main memory space is used for reading and writing, while the backup memory space is used to save the backup of data. If the main memory space fails, the memory data can be restored from the backup memory space. Similarly, if the backup memory space fails, the memory data can also be restored from the main memory space.
  • the memory space with the memory mirroring function enabled is also referred to as a mirrored memory space, and the mirrored memory space is used hereinafter to represent the memory space with the memory mirroring function enabled.
  • the mirror indication information is indication information used to distinguish the mirror memory space, that is, whether a certain memory space is a mirror memory space can be distinguished through the mirror indication information.
  • the mirror flag carried by the memory access instruction is used to distinguish whether the memory access instruction needs to access the memory space through the mirror access mode.
  • the mirror flag of the target object is used to distinguish whether the memory mirroring function is enabled for the memory space allocated to the target object. For example, when the mirror flag is set (such as set to 1), it means that the memory mirroring function needs to be enabled for the memory space allocated to the target object. When the mirror flag is not set (such as set to 0), it means that only the memory space of the requested size is allocated, but the memory mirroring function does not need to be enabled.
  • process A sends a memory allocation request, which indicates that a page of memory space is allocated to process A. If the mirror flag of process A is 1, two physical pages are allocated to process A, one physical page is the main memory space, and the other physical page is the backup memory space. If the mirror flag of process A is 0, one physical page is allocated to process A.
  • the mirror flag is, for example, an input parameter of a memory allocation function.
  • the mirror flag indicates that memory space with memory mirroring enabled is allocated when the memory allocation function is executed.
  • the memory allocation function is a kmalloc function
  • the mirror flag is a get free pages (GFP) allocation flag (also called a memory allocation flag or flags parameter) of the kmalloc function.
  • GFP get free pages
  • the memory allocation function is a vmalloc function
  • the mirror flag is a virtual address space (VMA) flag in the vmalloc function.
  • VMA virtual address space
  • Cache is hardware that caches data in memory.
  • Cache line is the basic unit of cache.
  • Cache line size refers to the data size of a cache line.
  • Direct memory access refers to a technology that allows access to memory without going through the processor. That is, before direct memory access, the processor can hand over control of the bus to the DMA controller, so that input/output (IO) devices can directly access the memory through the DMA controller without going through the processor. After the direct memory access is completed, the DMA controller immediately hands the control of the bus back to the processor. During the entire direct memory access process, the processor can handle other tasks, which can improve the utilization of the processor.
  • IO input/output
  • DCA Direct cache access
  • Direct cache access refers to the technology of accessing the processor's cache without going through the processor. Direct cache access is an improvement on direct memory access, that is, IO devices can directly access the processor's cache. This helps to reduce I/O latency and reduce the utilization of the memory bus.
  • FIG1 is a schematic diagram of a computer device according to an embodiment of the present application.
  • the computer device may be a server or other device.
  • the computer device includes a processor 101 , a memory 102 and a communication interface 103 .
  • the processor 101 includes at least one processor core, that is, the processor 101 can be a single-core processor or a multi-core processor.
  • Each processor core has a cache and a cache controller, that is, the processor 101 includes a processor core, a cache and a cache controller.
  • the memory access instruction can be sent to the cache controller corresponding to itself, and the cache controller searches for the target cache line corresponding to the memory access instruction from the cache corresponding to the processor core and the cache corresponding to other processor cores. After finding the target cache line, it can be determined whether the target memory space is a mirror memory space based on the mirror indication information of the target cache line. If the target memory space is a mirror memory space and the memory access instruction is in a non-mirror access mode, the cache controller can refuse to execute the memory access instruction.
  • the memory 102 may include a memory, and the computer device may further include a memory controller (MC).
  • the memory 102 may communicate with a cache controller corresponding to each processor core through the MC. In the case where the cache controller fails to find the target cache line, the cache controller may also search for corresponding mirror indication information from the memory through the MC to determine whether the target memory space is a mirror memory space.
  • the cache controller may also be referred to as a caching and home agent (CHA).
  • the cache controller is used to control the read and write of the cache.
  • the MC is used to control the read and write of the memory, and the positional relationship between the MC and the processor also includes a variety of situations.
  • the MC may be set inside the processor, that is, the MC is integrated with the processor.
  • the MC may also be set outside the processor, that is, the MC is set separately from the processor, which is not shown in FIG1 .
  • the processor 101 may be a general-purpose central processing unit (CPU), a network processor (NP), a microprocessor, or one or more integrated circuits for implementing the solution of the present application, such as an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof.
  • the above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.
  • the memory 102 may be a read-only memory (ROM), a random access memory (RAM), an electrically erasable programmable read-only memory (EEPROM), an optical disk (including a compact disc read-only memory (CD-ROM), a compact disc, a laser disc, a digital versatile disc, a Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto.
  • the memory 102 may be an independent storage medium.
  • the memory 102 is connected to the processor 101.
  • the memory 102 can also be integrated with the processor 101.
  • the communication interface 103 uses any transceiver-like device for communicating with other devices or communication networks.
  • the communication interface 103 includes a wired communication interface and may also include a wireless communication interface.
  • the wired communication interface may be, for example, an Ethernet interface.
  • the Ethernet interface may be an optical interface, an electrical interface, or a combination thereof.
  • the wireless communication interface may be a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof, etc.
  • WLAN wireless local area network
  • the computer device may include multiple processors, such as processor 101 and processor 104 shown in Figure 1.
  • a processor herein may refer to one or more devices, circuits, and/or processors for processing data (such as computer program instructions).
  • the computer device may further include a communication bus 105.
  • the communication bus 105 is used to transmit information between the above components.
  • the communication bus 105 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.
  • the computer device may further include an output device 106 and an input device 107.
  • the output device 106 communicates with the processor 101 and may display information in a variety of ways, such as data read from a memory.
  • the input device 107 communicates with the processor 101 and may receive commands or data involved in the following method embodiments input by a user in a variety of ways.
  • the output device 106 may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device or a projector, etc.
  • the input device 107 may be a mouse, a keyboard, a touch screen device or a sensor device, etc.
  • the memory 102 is used to store program codes for executing the solution of the present application, and the cache controller implements the methods in the following embodiments by reading and executing the program codes stored in the memory 102.
  • the processor 101 memory stores program codes, and the cache controller implements the methods in the following embodiments by executing the program codes stored in the processor 101.
  • the program code may include one or more software modules, such as the modules involved in the subsequent device embodiments.
  • Fig. 2 is a flow chart of a memory access method provided in an embodiment of the present application. Referring to Fig. 2, the method includes the following steps.
  • Step 201 The cache controller receives a memory access instruction sent by a processor core, where the memory access instruction is used to access a target memory space.
  • the memory access instruction is used to instruct a read data operation or a write data operation to a target memory space.
  • the memory access instruction may carry the memory address of the target memory space.
  • the memory access instruction may carry the memory address of the target memory space and the target data to be written.
  • the target memory space refers to the space in the memory of the computer device that needs to be accessed currently.
  • the target memory space may be a mirrored memory space or a non-mirror memory space.
  • the target memory space may have the memory mirroring function enabled or may not have the memory mirroring function enabled.
  • the embodiment of the present application not only caches some data in the target memory space in the cache corresponding to the processor core, but also caches the mirror indication information of the target memory space in the cache corresponding to the processor core. Therefore, after the processor core receives the memory access instruction, the memory access instruction can be sent to the cache controller, so that the cache controller can perform subsequent processing based on the data in the cache.
  • Step 202 The cache controller determines whether the target memory space is a mirrored memory space based on the mirroring indication information of the target cache line corresponding to the memory access instruction in the cache.
  • the target memory space may be a mirror memory space or a non-mirror memory space
  • the mirror indication information can distinguish whether the target memory space is a mirror memory space.
  • the mirror indication information can also be cached in the cache corresponding to the processor core. In this way, the cache controller can determine whether the target memory space is a mirror memory space based on the mirror indication information in the cache, without having to obtain the mirror indication information from the memory, thereby improving the judgment efficiency of the mirror memory space.
  • a cache typically includes multiple cache lines, each of which includes a data area and a non-data area.
  • the data area is used to store a portion of data in the memory
  • the non-data area includes a mirror indication field, which is used to record mirror indication information.
  • the mirror indication information is used to indicate whether the space in the memory where the data stored in the data area is located is a mirror memory space. Therefore, for a target cache line, the target cache line includes a data area and a non-data area.
  • the data area stores the data to be accessed, and the non-data area includes a mirror indication field, which is used to record the mirror indication information.
  • the non-data area of each cache line may also store the memory address corresponding to the data in the data area.
  • the memory access instruction may carry the memory address of the target memory space, so the cache controller may compare the memory address of the target memory space with the memory address of the non-data area of each cache line, thereby determining the cache line that matches the memory address of the target memory space and using the cache line as the target cache line.
  • the mirror indication information of each cache line used to cache the data of the target memory space will also be the same, so the mirror indication information of any of these cache lines can be used to determine whether the target memory space is a mirror memory space.
  • the mirror indication information of the non-data area of the target cache line is used to indicate whether the memory space where the data in the data area is located is a mirror memory space, this memory space is located in the target memory space, so the mirror indication information of the target cache line can also be used to determine whether the target memory space is a mirror memory space.
  • the mirror indication information of the target cache line may be set or not set.
  • the target memory space is determined to be a mirror memory space.
  • the mirror indication information of the target cache line is not set, it is determined that the target memory space is not a mirror memory space, that is, a non-mirror memory space.
  • the mirror indication information being set can also be understood as the mirror indication information taking a value of 1, and the mirror indication information not being set can be understood as the mirror indication information taking a value of 0.
  • the two can also be reversed, that is, the mirror indication information being set can also be understood as the mirror indication information taking a value of 0, and the mirror indication information not being set can be understood as the mirror indication information taking a value of 1.
  • whether the mirror indication information is set can also be represented by other methods, and the embodiments of the present application are not limited to this.
  • the target cache line may not exist in the cache.
  • the mirror indication information can be obtained from the memory to determine whether the target memory space is a mirror memory space. That is, if the target cache line does not exist in the cache, it is determined whether the target memory space is a mirror memory space based on the mirror indication information of the target non-data area corresponding to the memory access instruction in the target memory space.
  • the target memory space includes multiple data areas and multiple non-data areas, the multiple data areas correspond to the multiple non-data areas one by one, and the non-data area includes mirror indication information, which indicates whether the memory space where the data in the corresponding data area is located is a mirror memory space. Therefore, for the target non-data area, there is also a target data area corresponding to the target non-data area in the target memory space. That is, the target memory space includes a target data area and a target non-data area, the target data area stores the data to be accessed, and the target non-data area stores the mirror indication information.
  • the mirror indication information of each non-data area included in the target memory space will also be the same, so the mirror indication information of any non-data area in these non-data areas can be used to determine whether the target memory space is a mirror memory space.
  • the mirror indication information of the target non-data area is used to indicate whether the memory space where the data of the target data area is located is a mirror memory space, this memory space is located in the target memory space, so the mirror indication information of the target non-data area can also be used to determine whether the target memory space is a mirror memory space.
  • the mirror indication information of the target non-data area may be set or not set. In the case where the mirror indication information of the target non-data area is set, the target memory space is determined to be the mirror memory space. In the case where the mirror indication information of the target non-data area is not set, it is determined that the target memory space is not the mirror memory space, that is, the non-mirror memory space.
  • the processor core corresponds to a cache controller and a cache.
  • the cache controller can also communicate with a memory controller, and the memory controller is used to control the memory.
  • the cache line includes a data area and a non-data area.
  • the non-data area can include two parts, namely an attribute area and a flag area.
  • the attribute area stores the memory address of the data in the data area.
  • the flag area includes a mirror indication field, which is used to record the mirror indication information.
  • the memory includes multiple data areas and multiple non-data areas.
  • FIG3 is schematically illustrated with a data area and a non-data area.
  • the non-data area stores the mirror indication information.
  • the above is an example of the attribute area storing the memory address. In actual applications, the attribute area may also store other data. Similarly, the above is an example of the flag area storing the mirror indication information. In actual applications, the flag area may also store other flag bits, etc., and the embodiments of the present application do not limit this.
  • the non-data area of the memory the above is an example of the non-data area storing the mirror indication information. In actual applications, the non-data area may also store other information, and the embodiments of the present application do not limit this either.
  • the memory may be dual inline memory modules (DIMM), registered DIMM (RDIMM), load reduced DIMM (LRDIMM), and of course, other memory modules.
  • DIMM dual inline memory modules
  • RDIMM registered DIMM
  • LPDIMM load reduced DIMM
  • the data in the cache is obtained by caching the data in the memory. Therefore, when caching the data in a data area in the memory, the mirror indication information of the non-data area corresponding to the data area can also be read, and then the mirror indication information is also cached. This facilitates the subsequent determination of whether the memory space where the data is located is a mirror memory space through the mirror indication information in the cache.
  • the granularity of the data area in the memory may be the same as the granularity of the cache line, that is, the size of the data area in the memory may be the same as the size of the cache line.
  • the above is to first determine whether the target cache line is included in the cache. If the target cache line is included, whether the target memory space is a mirror memory space is determined directly based on the mirror indication information of the target cache line. If the target cache line is not included, whether the target memory space is a mirror memory space is determined based on the mirror indication information of the target non-data area in the memory. Of course, in actual applications, it is also possible to directly determine whether the target memory space is a mirror memory space based on the mirror indication information of the target non-data area in the memory.
  • the target memory space is a mirror memory space, so as to facilitate subsequent operations on the target memory space.
  • the cache controller refuses to execute the memory access instruction if the target memory space is a mirrored memory space and the memory access instruction is in a non-mirrored access mode.
  • the cache controller can avoid illegal access to the mirrored memory data by refusing to execute the memory access instruction, thereby improving the security of the mirrored memory data.
  • the non-mirror access mode means that the memory access instruction is not a mirror access instruction.
  • the mirror access mode means that the memory access instruction is a mirror access instruction, or the memory access instruction is not a mirror access instruction but the parameter of the memory access instruction has a mirror flag.
  • the format of the mirror access instruction is different from the format of the ordinary memory access instruction.
  • whether the mirrored memory space rejects the non-mirror access mode can also be configured.
  • the cache controller can also obtain the mirror configuration information of the target memory space, and the mirror configuration information indicates whether the target memory space rejects the access in the non-mirror access mode. If the mirror configuration information indicates that the target memory space rejects the access in the non-mirror access mode, the cache controller refuses to execute the memory access instruction. If the mirror configuration information indicates that the target memory space allows the access in the non-mirror access mode, the cache controller performs the operation corresponding to the memory access instruction on the target memory space.
  • the mirror configuration information of the target memory space can be set when allocating the target memory space, that is, the mirror configuration information of the target memory space is set in advance.
  • the mirror configuration information of the target memory space can also be adjusted according to different requirements, and the embodiment of the present application does not limit this.
  • the cache controller performs an operation corresponding to the memory access instruction on the target memory space.
  • the memory access instruction is used to instruct a read data operation or a write data operation to the target memory space.
  • the cache controller can read the corresponding data from the target memory space based on the memory address carried by the memory access instruction.
  • the cache controller can write the target data carried by the memory access instruction to the target memory space based on the memory address carried by the memory access instruction.
  • the cache controller can determine whether there is corresponding data in the cache based on the memory address carried by the memory access instruction. If the corresponding data exists in the cache, the corresponding data can be directly read from the cache. If the corresponding data does not exist in the cache, the corresponding data can be read from the target memory space.
  • the cache controller can determine whether there is a corresponding cache line in the cache based on the memory address carried by the memory access instruction. If there is a corresponding cache line in the cache, the target data can be directly written into the cache and then written into the target memory space. If there is no corresponding cache line in the cache, the target data can be written into the target memory space.
  • the cache controller is used to control the read and write of the cache
  • the memory controller is used to control the read and write of the memory. Therefore, whether reading data from the target memory space or writing data to the target memory space, the cache controller needs to be implemented through the memory controller. That is, the cache controller reads data from the target memory space through the memory controller, and writes data to the target memory space through the memory controller.
  • the memory access instruction is a memory write instruction
  • the memory write instruction carries the target data to be written
  • the target memory space includes the main memory space and the backup memory space.
  • the cache controller sends a memory write notification to the memory controller to instruct the memory controller to write the target data in both the main memory space and the backup memory space. That is, after the memory controller receives the memory write notification sent by the cache controller, it writes the target data in both the main memory space and the backup memory space.
  • the target memory space is allocated in advance for the target object. That is, a memory allocation request for the target object is received, the memory allocation request is used to request the target memory space, and in response to the mirror flag of the target object being set, the target memory space is allocated for the target object, and the target memory space is allocated to the target object.
  • the mirror indication information of each non-data area in the space is set.
  • a target memory space is allocated to the target object. At this time, the memory mirror function is not enabled in the target memory space.
  • the target object refers to a software module in a computer device that is allowed to occupy memory space.
  • the target object includes but is not limited to a process, a kernel, a portion of a VMA segment of a process, a portion of a module in the kernel, etc.
  • the memory allocation request indicates that a target memory space is allocated for the target object.
  • different types of target objects have different image flags. For example, the image flag of the kernel is different from the image flag of the process.
  • the mirror flag of the target object being set can also be understood as the mirror flag value of the target object being 1, and the mirror flag of the target object not being set can be understood as the mirror flag value of the target object being 0.
  • the two can also be reversed, that is, the mirror flag of the target object being set can also be understood as the mirror flag value of the target object being 0, and the mirror flag of the target object not being set can be understood as the mirror flag value of the target object being 1.
  • whether the mirror flag of the target object is set can also be represented by other methods, and the embodiments of the present application do not limit this.
  • the embodiment of the present application can determine whether it is necessary to enable the memory mirroring function for the memory space allocated for the target object according to the needs of the target object.
  • mirror protection is used for the memory actually requested to be allocated when the target object is running, so as to avoid waste of memory resources caused by preset too large mirror memory and avoid business interruption caused by insufficient preset mirror memory.
  • the memory mirroring function of the target memory space can also be cancelled, so as to facilitate the recovery of the memory space. That is, a memory release request of the target object is received, the memory release request is used to release the target memory space, release the target memory space allocated for the target object, and cancel the mirroring indication information of each data area in the target memory space.
  • the memory access instruction involved in the embodiment of the present application may be a direct memory access instruction, i.e., a DMA instruction, or a direct cache access instruction, i.e., a DCA instruction, which is not limited in the embodiment of the present application.
  • the method provided in the embodiment of the present application can deny the access of the direct memory access instruction in the non-mirror mode to the data in the mirror memory space of the memory.
  • the method provided in the embodiment of the present application can deny the access of the direct cache access instruction in the non-mirror mode to the data in the mirror memory space cached in the cache.
  • the processor core After the processor core receives the memory access instruction, it is necessary to obtain the mirror indication information stored in the page table entry in the target memory space through the memory controller, and then determine whether the target memory space is a mirror memory space through the mirror indication information. That is to say, the page table entry in the memory stores the mirror indication information of the target memory space, which is used to determine whether the target memory space is a mirror memory space.
  • each cache line used to cache the data of the target memory space in the cache is cached with mirror indication information, which is used to determine whether the target memory space is a mirror memory space.
  • the cache controller after the cache controller receives the memory access instruction sent by the processor core, it can determine whether the target memory space is a mirror memory space through the mirror indication information of the target cache line corresponding to the memory access instruction, without accessing the memory to determine whether the target memory space is a mirror memory space, which can avoid the problem of increased delay caused by obtaining the mirror indication information in the memory, thereby improving the efficiency of memory access.
  • the cache controller can refuse to execute the memory access instruction, so that the mirror memory data can be avoided from being illegally accessed, and the security of the mirror memory data can be improved.
  • Figure 4 is introduced by taking a memory read instruction as an example
  • Figure 5 is introduced by taking a memory write instruction as an example.
  • Figures 4 and 5 are divided into four scenarios A, B, C, and D for introduction.
  • the cache controller receives a memory read instruction in the mirror access mode from the target object, and determines based on the memory read instruction that there is no data to be read in the cache. At this time, the cache controller can determine through the memory controller that there is data to be read in the memory, and the corresponding mirror indication information is 1, that is, the mirror indication information is set. In this way, the memory controller can read the corresponding data and the mirror indication information from the memory, and send the read data and the mirror indication information to the cache controller. The cache controller receives the read data and the mirror indication information, determines that the mirror indication information is set, and then sends the read data to the target object.
  • the cache controller receives a memory read instruction in a non-mirroring access mode from the target object, and determines based on the memory read instruction that there is no data to be read in the cache. At this time, the cache controller can determine through the memory controller that there is data to be read in the memory, and the corresponding mirror indication information is 1, that is, the mirror indication information is set. In this way, the memory controller can read the corresponding data from the memory to The cache controller receives the read data and the mirror indication information, determines that the mirror indication information is set, and then sends a prompt message that the instruction is not supported to the target object, that is, refuses to execute the memory read instruction.
  • the cache controller receives a memory read instruction in the mirror access mode from the target object, and determines that there is data to be read in the cache based on the memory read instruction. At this time, the cache controller reads the corresponding data and mirror indication information from the cache, and the mirror indication information is 1, that is, the mirror indication information is set. In this way, the cache controller sends the read data to the target object.
  • the cache controller receives a memory read instruction in the mirror access mode from the target object, and determines that there is data to be read in the cache based on the memory read instruction. At this time, the cache controller reads the corresponding data and mirror indication information from the cache, and the mirror indication information is 1, that is, the mirror indication information is set. In this way, the cache controller sends a prompt message that the instruction is not supported to the target object, that is, the execution of the memory read instruction is rejected.
  • the cache controller receives a memory write instruction in the mirror access mode from the target object, and determines based on the memory write instruction that there is no cache line in the cache where the data to be written is located. At this time, the cache controller can determine through the memory controller that there is a memory space corresponding to the data to be written in the memory, and the corresponding mirror indication information is 1, that is, the mirror indication information is set. In this way, the memory controller can send the mirror indication information to the cache controller, and then the cache controller writes the corresponding data to the memory.
  • the cache controller receives a memory write instruction in a non-mirror access mode from the target object, and determines based on the memory write instruction that there is no cache line in the cache where the data to be written is located. At this time, the cache controller can determine through the memory controller that there is a memory space corresponding to the data to be written in the memory, and the corresponding mirror indication information is 1, that is, the mirror indication information is set. In this way, the memory controller can send the mirror indication information to the cache controller. Then the cache controller sends a prompt message that the instruction is not supported to the target object, that is, the execution of the memory write instruction is rejected.
  • the cache controller receives a memory write instruction in the mirror access mode from the target object, and determines the cache line where the data to be written exists in the cache based on the memory write instruction. At this time, the cache controller reads the corresponding data and mirror indication information from the cache, and the mirror indication information is 1, that is, the mirror indication information is set. In this way, the cache controller writes the corresponding data to the memory through the memory controller based on the read data and the data to be written.
  • the cache controller receives a memory write instruction in the mirror access mode from the target object, and determines that there is data to be read in the cache based on the memory write instruction. At this time, the cache controller reads the corresponding data and mirror indication information from the cache, and the mirror indication information is 1, that is, the mirror indication information is set. In this way, the cache controller sends a prompt message that the instruction is not supported to the target object, that is, the execution of the memory write instruction is rejected.
  • Fig. 6 is a schematic diagram of the structure of a memory access device provided in an embodiment of the present application, which can be implemented by software, hardware or a combination of both to form part or all of a computer device, and the computer device can be the computer device shown in Fig. 1.
  • the device includes: an instruction receiving module 601 and a first determining module 602.
  • the instruction receiving module 601 is used to receive a memory access instruction sent by the processor core, where the memory access instruction is used to access a target memory space;
  • the first determination module 602 is used to determine whether the target memory space is a mirror memory space based on the mirror indication information of the target cache line corresponding to the memory access instruction in the cache.
  • the target cache line includes a data area and a non-data area, the data area stores data to be accessed, and the non-data area includes a mirror indication field, and the mirror indication field is used to record mirror indication information.
  • the device further comprises:
  • the second determination module is used to determine whether the target memory space is a mirror memory space based on the mirror indication information of the target non-data area corresponding to the memory access instruction in the target memory space if the target cache line does not exist in the cache.
  • the target memory space includes a target data area and a target non-data area, the target data area stores data to be accessed, and the target non-data area stores mirror indication information.
  • the device further comprises:
  • the instruction execution module is used to execute the operation corresponding to the memory access instruction on the target memory space if the target memory space is a mirror memory space and the memory access instruction is in a mirror access mode.
  • the device further comprises:
  • the instruction rejection module is used to reject the execution of the memory access instruction if the target memory space is a mirror memory space and the memory access instruction is in a non-mirror access mode.
  • the instruction rejection module is specifically used for:
  • the mirror configuration information indicating whether the target memory space denies access in a non-mirror access mode
  • the memory access instruction is denied execution.
  • the instruction execution module is further configured to execute an operation corresponding to the memory access instruction on the target memory space if the mirror configuration information indicates that the target memory space allows access in a non-mirror access mode.
  • the memory access instruction is a memory write instruction
  • the memory write instruction carries target data to be written
  • the target memory space includes a main memory space and a backup memory space
  • the instruction execution module is specifically used for:
  • a memory write notification is sent to the memory controller to instruct the memory controller to write target data in both the main memory space and the backup memory space.
  • the device further comprises:
  • An allocation request receiving module used for receiving a memory allocation request of a target object, wherein the memory allocation request is used for requesting a target memory space;
  • the memory allocation module is used to allocate a target memory space for the target object in response to the mirror flag of the target object being set, and to set the mirror indication information of each non-data area in the target memory space.
  • the device further comprises:
  • a release request receiving module used for receiving a memory release request of a target object, the memory release request being used for releasing a target memory space;
  • the memory release module is used to release the target memory space allocated for the target object and cancel the setting of the mirror indication information of each non-data area in the target memory space.
  • the cache controller after the cache controller receives the memory access instruction sent by the processor core, it can determine whether the target memory space is a mirror memory space based on the mirror indication information of the target cache line. When the target memory space is a mirror memory space and the memory access instruction is in a non-mirror access mode, the cache controller can refuse to execute the memory access instruction. In this way, illegal access to the mirror memory data can be avoided, and the security of the mirror memory data can be improved. Moreover, by determining whether the target memory space is a mirror memory space through the mirror indication information of the target cache line in the cache, the problem of increased delay caused by obtaining the mirror indication information in the memory can be avoided, thereby improving the efficiency of memory access.
  • the memory access device provided in the above embodiment only uses the division of the above functional modules as an example when performing memory access.
  • the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.
  • the memory access device provided in the above embodiment and the memory access method embodiment belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.
  • An embodiment of the present application also provides a processor, which includes a cache controller, and the cache controller is used to implement the memory access method of the above embodiment.
  • the embodiment of the present application also provides a memory access device, which includes a processor and a memory, wherein the memory is used to store a computer program for executing the memory access method provided in the first aspect.
  • the processor is configured to execute the computer program stored in the memory to implement the memory access method of the above embodiment.
  • the memory access device may further include a communication bus, and the communication bus is used to establish a connection between the processor and the memory.
  • An embodiment of the present application also provides a computer-readable storage medium, which stores instructions. When the instructions are executed on a computer, the computer executes the memory access method of the above embodiment.
  • the present application also provides a computer program product including instructions, which, when executed on a computer, enables the computer to execute the steps of the memory access method of the above embodiment.
  • a computer program is provided, which, when executed on a computer, enables the computer to execute the memory access method of the above embodiment.
  • the computer program product includes one or more computer instructions.
  • the computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device.
  • the computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium.
  • the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (for example: coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example: infrared, wireless, microwave, etc.)
  • the computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center that includes one or more available media integrated therein.
  • the available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital versatile disc (DVD)), or a semiconductor medium (e.g., a solid state disk (SSD)).
  • the computer-readable storage medium mentioned in the embodiment of the present application can be a non-volatile storage medium, in other words, a non-transient storage medium.
  • the information including but not limited to user device information, user personal information, etc.
  • data including but not limited to data used for analysis, stored data, displayed data, etc.
  • signals involved in the embodiments of the present application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions.

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Abstract

一种内存访问方法及相关装置，属于计算机领域。所述方法包括：缓存控制器接收处理器核发送的内存访问指令，该内存访问指令用于访问目标内存空间（201）；缓存控制器基于缓存中所述内存访问指令对应的目标缓存行的镜像指示信息，确定目标内存空间是否为镜像内存空间（202）。该方法可以避免通过获取内存中的镜像指示信息而导致延迟增加的问题，从而能够提高内存访问的效率。

Description

内存访问方法及相关装置
本申请要求于2022年11月29日提交的申请号为202211513508.2、发明名称为“一种动态内存镜像的处理方法”的中国专利申请的优先权，以及要求于2023年03月09日提交的申请号为202310255341.2、发明名称为“内存访问方法及相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机领域，特别涉及一种内存访问方法及相关装置。
背景技术
内存镜像(memory mirror)是一种内存保护技术。已启用内存镜像功能的内存空间包括主内存空间和备内存空间。主内存空间用于供内存控制器读取数据，备内存空间用于保存主内存空间中数据的备份。当主内存空间和备内存空间中的一个内存空间故障时，计算机设备能够从另一个内存空间恢复数据，从而提升内存稳定性和可用性。
相关技术提供了一种基于动态内存镜像的内存访问方法，在该方法中，当接收到内存访问指令之后，基于该内存访问指令所要访问的目标内存空间中的页表项，确定目标内存空间是否已启用动态内存镜像功能，如果目标内存空间已启用动态内存镜像功能，则对目标内存空间包括的主内存空间和备内存空间均执行该内存访问指令对应的操作。
然而，上述方法在实现动态内存镜像的过程中，可能会导致内存访问的效率较低。
发明内容
本申请提供了一种内存访问方法及相关装置，可以提高镜像内存数据的安全性。所述技术方案如下：
第一方面，提供了一种内存访问方法，该方法包括：缓存控制器接收处理器核发送的内存访问指令，所述内存访问指令用于访问目标内存空间；所述缓存控制器基于缓存中所述内存访问指令对应的目标缓存行的镜像指示信息，确定所述目标内存空间是否为镜像内存空间。
在相关技术中，处理器核接收到内存访问指令之后，需要通过内存控制器获取目标内存空间中的页表项存储的镜像指示信息，进而通过该镜像指示信息确定目标内存空间是否为镜像内存空间。也就是说，内存中的页表项存储有目标内存空间的镜像指示信息，用来确定目标内存空间是否为镜像内存空间。而本申请中，缓存中用于缓存目标内存空间的数据的各个缓存行均缓存有镜像指示信息，用于确定目标内存空间是否为镜像内存空间，这样，在缓存控制器接收到处理器核发送的内存访问指令之后，通过内存访问指令对应的目标缓存行的镜像指示信息来确定目标内存空间是否为镜像内存空间，无需通过访问内存来确定目标内存空间是否为镜像内存空间，可以避免通过获取内存中的镜像指示信息而导致延迟增加的问题，从而能够提高内存访问的效率。
通常情况下，缓存包括多个缓存行，每个缓存行包括数据区和非数据区，数据区用于存储内存中的一部分数据，非数据区包括镜像指示字段，该镜像指示字段用于记录镜像指示信息，该镜像指示信息用于指示数据区中存储的数据在内存中所处的空间是否为镜像内存空间。所以，对于目标缓存行来说，目标缓存行包括数据区和非数据区，所述数据区存储待访问的数据，所述非数据区包括镜像指示字段，所述镜像指示字段用于记录所述镜像指示信息。
由于缓存中可能只缓存部分内存数据，所以，缓存中也可能不存在目标缓存行。在这种情况下，可以从内存中获取镜像指示信息来确定目标内存空间是否为镜像内存空间。即，若所述缓存中不存在所述目标缓存行，则所述缓存控制器基于所述目标内存空间中所述内存访问指令对应的目标非数据区的镜像指示信息，确定所述目标内存空间是否为镜像内存空间。
在缓存不存在目标缓存行的情况下，还可以通过目标内存空间中的镜像指示信息，来确定目标内存空间是否为镜像内存空间，这样，可以保证内存访问的可靠性。
通常情况下，目标内存空间包括多个数据区和多个非数据区，该多个数据区与该多个非数据区一一对 应，非数据区包括镜像指示信息，该镜像指示信息指示对应的数据区中的数据所在的内存空间是否为镜像内存空间。所以，对于目标非数据区来说，目标内存空间中还存在与目标非数据区对应的目标数据区。即，目标内存空间包括目标数据区和所述目标非数据区，所述目标数据区中存储待访问的数据，所述目标非数据区存储所述镜像指示信息。
在一种可能的实现方式中，若所述目标内存空间为镜像内存空间，且所述内存访问指令为镜像访问模式，则所述缓存控制器对所述目标内存空间执行所述内存访问指令对应的操作。
在另一种可能的实现方式中，若所述目标内存空间为镜像内存空间，且所述内存访问指令为非镜像访问模式，则所述缓存控制器拒绝执行所述内存访问指令。
通过上述方法确定目标内存空间为镜像内存空间且该内存访问指令为非镜像访问模式的情况下，缓存控制器可以拒绝执行该内存访问指令，这样，可以避免镜像内存数据被非法访问，提高镜像内存数据的安全性。
镜像内存空间是否拒绝非镜像访问模式还可以进行配置。这样，在目标内存空间为镜像内存空间，且该内存访问指令为非镜像访问模式的情况下，缓存控制器还可以获取所述目标内存空间的镜像配置信息，所述镜像配置信息指示所述目标内存空间是否拒绝非镜像访问模式的访问；若所述镜像配置信息指示所述目标内存空间拒绝非镜像访问模式的访问，则所述缓存控制器拒绝执行所述内存访问指令。
在一种可能的实现方式中，若所述镜像配置信息指示所述目标内存空间允许非镜像访问模式的访问，则所述缓存控制器对所述目标内存空间执行所述内存访问指令对应的操作。
目标内存空间的镜像配置信息可以是在分配目标内存空间时设置的，即目标内存空间的镜像配置信息是事先设置的。当然，在实际应用中，目标内存空间的镜像配置信息还可以按照不同的需求进行调整。
在一种可能的实现方式中，所述内存访问指令为内存写指令，所述内存写指令携带待写入的目标数据，所述目标内存空间包括主内存空间和备内存空间；此时，所述缓存控制器对所述目标内存空间执行所述内存访问指令对应的操作，包括：所述缓存控制器向内存控制器发送内存写通知，以指示所述内存控制器在所述主内存空间和所述备内存空间中均写入所述目标数据。
上述目标内存空间是事先为目标对象分配的。即，接收目标对象的内存分配请求，所述内存分配请求用于请求所述目标内存空间；响应于所述目标对象的镜像标志被置位，为所述目标对象分配所述目标内存空间，并对所述目标内存空间中各个非数据区的镜像指示信息进行置位。
目标对象是指计算机设备中允许占用内存空间的软件模块。例如，目标对象包括而不限于进程、内核、进程的部分VMA段、内核中的部分模块等。内存分配请求指示为目标对象分配目标内存空间。在一种可能的实现方式中，不同类型的目标对象具有不同的镜像标志。例如，内核的镜像标志与进程的镜像标志不同。
在接收到目标对象的内存分配请求之后，如果目标对象的镜像标志被置位，表明当前需要为目标对象分配目标内存空间，而且目标内存空间需要开启内存镜像功能。所以，在为目标对象分配目标内存空间之后，可以为目标内存空间中各个非数据区的镜像指示信息进行置位，从而开启目标内存空间的内存镜像功能。也就是说，本申请实施例可以按照目标对象的需求来确定是否需要为目标对象分配的内存空间开启内存镜像功能。
通过上述方式，针对目标对象运行时实际请求分配的内存采用镜像保护，避免预设过大的镜像内存导致内存资源浪费，同时避免预设的镜像内存不足导致业务中断。
在目标对象需要释放目标内存空间时，还可以取消目标内存空间的内存镜像功能，这样便于内存空间的回收。即，接收所述目标对象的内存释放请求，所述内存释放请求用于释放所述目标内存空间；释放为所述目标对象分配的所述目标内存空间，并取消所述目标内存空间中各个非数据区的镜像指示信息的置位。
第二方面，提供了一种处理器，所述处理器包括缓存控制器，所述缓存控制器用于实现上述第一方面所提供的方法。
第三方面，提供了一种内存访问装置，所述内存访问装置包括处理器和存储器，所述存储器用于存储执行上述第一方面所提供的内存访问方法的计算机程序。所述处理器被配置为用于执行所述存储器中存储的计算机程序，以实现上述第一方面所述的内存访问方法。
可选地，所述内存访问装置还可以包括通信总线，该通信总线用于该处理器与存储器之间建立连接。
第四方面，提供了一种计算机可读存储介质，所述存储介质内存储有指令，当所述指令在计算机上运行时，使得计算机执行上述第一方面所述的内存访问方法。
第五方面，提供了一种包含指令的计算机程序产品，当所述指令在计算机上运行时，使得计算机执行上述第一方面所述的内存访问方法的步骤。或者说，提供了一种计算机程序，当所述计算机程序在计算机上运行时，使得计算机执行上述第一方面所述的内存访问方法。
上述第二方面至第五方面所获得的技术效果与第一方面中对应的技术手段获得的技术效果近似，在这里不再赘述。
附图说明
图1是本申请实施例提供的一种计算机设备的结构示意图；
图2是本申请实施例提供的一种内存访问方法的流程图；
图3是本申请实施例提供的一种缓存行和内存的结构示意图；
图4是本申请实施例提供的一种内存读指令的处理方法的示意图；
图5是本申请实施例提供的一种内存写指令的处理方法的示意图；
图6是本申请实施例提供的一种内存访问装置的结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
在对本申请实施例提供的内存访问方法进行详细地解释说明之前，先对本申请实施例涉及的术语和实施环境进行介绍。
首先对本申请实施例涉及的术语进行介绍。
1、启用内存镜像功能的内存空间
启用内存镜像功能的内存空间包括两个独立的物理内存空间。一个物理内存空间作为主内存空间，另外一个物理内存空间作为备内存空间。当进程、内核或者其他对象发起对启用内存镜像功能的内存空间的写数据指令时，数据会同时写入至主内存空间和备内存空间，使得数据在内存中存在相同的两份。
通常情况下，主内存空间用于进行读写，而备内存空间用于保存数据的备份。如果主内存空间出现故障，可以从备内存空间恢复内存数据。同理，如果备内存空间出现故障，也可以从主内存空间恢复内存数据。
在一些实施例中，启用内存镜像功能的内存空间也被称为镜像内存空间，后续均以镜像内存空间来表示已启用内存镜像功能的内存空间。
2、镜像指示信息(镜像indicator)
镜像指示信息是用于区分镜像内存空间的指示信息，即通过镜像指示信息能够区分某个内存空间是否为镜像内存空间。
3、内存访问指令携带的镜像标志
内存访问指令携带的镜像标志用于区分该内存访问指令是否需要通过镜像访问模式来访问内存空间。
4、目标对象的镜像标志
目标对象的镜像标志用于区分是否为目标对象分配的内存空间启用内存镜像功能。例如，当镜像标志被置位(如置为1)时，表示需要为目标对象分配的内存空间启用内存镜像功能。当镜像标志未被置位(如置为0)时，表示仅分配所请求大小的内存空间，但是不需要开启内存镜像功能。例如，进程A发送内存分配请求，该内存分配请求指示为进程A分配一个页的内存空间。如果进程A的镜像标志为1，则为进程A分配两个物理页，一个物理页是主内存空间，另一个物理页是备内存空间。如果进程A的镜像标志为0，则为进程A分配一个物理页。
镜像标志例如是内存分配函数的一个输入参数。镜像标志指示执行内存分配函数时分配启用内存镜像的内存空间。例如，内存分配函数是kmalloc函数，镜像标志是kmalloc函数的一种获取空闲页(get free pages，GFP)分配标志(也称内存分配标志或flags参数)。又如，内存分配函数是vmalloc函数，镜像标志是vmalloc函数中的一种虚拟地址空间(virtual memory area，VMA)标志。
5、缓存行(cache line)
缓存是对内存中的数据进行缓存的硬件。缓存行是缓存的基本单位。缓存行尺寸(cache line size)是指一个缓存行的数据大小。计算机设备在访问内存时，会以缓存行尺寸为单位，将内存中的数据迁移到缓存中。例如，缓存行尺寸是N个字节，计算机设备在访问内存时，一次最少迁移内存中N个字节的数据到缓存中。
6、直接内存访问(direct memory access，DMA)
直接内存访问是指无需经过处理器即可访问内存的技术。即，在直接内存访问之前，处理器可以将总线的控制权交给DMA控制器，这样，输入输出(input/output，IO)设备可以通过DMA控制器直接访问内存，而无需经过处理器。在结束直接内存访问之后，DMA控制器立即将总线的控制权再交回给处理器。在整个直接内存访问过程中，处理器可以处理其他的任务，这样可以提高处理器的利用率。
7、直接缓存访问(direct cache access，DCA)
直接缓存访问是指无需经过处理器即可访问处理器的缓存的技术。直接缓存访问是直接内存访问的改进技术，即IO设备可以直接访问处理器的缓存。这有助于降低I/O延迟，并减少内存总线的利用率。
其次对本申请实施例涉及的实施环境进行介绍。
请参考图1，图1是根据本申请实施例示出的一种计算机设备的结构示意图。该计算机设备可以为服务器，也可以为其他的设备。该计算机设备包括处理器101、存储器102以及通信接口103。
处理器101包括至少一个处理器核，也就是说，处理器101可以是一个单核处理器，也可以是一个多核处理器。每个处理器核对应有缓存(cache)和缓存控制器，也可以说，处理器101包括处理器核、缓存和缓存控制器。
处理器核接收到IO设备发送的待访问目标内存空间的内存访问指令之后，可以将该内存访问指令发送给自身对应的缓存控制器，该缓存控制器从该处理器核对应的缓存以及其他处理器核对应的缓存中，查找该内存访问指令对应的目标缓存行。在查找到目标缓存行之后，可以基于目标缓存行的镜像指示信息，确定目标内存空间是否为镜像内存空间。在目标内存空间为镜像内存空间，且该内存访问指令为非镜像访问模式的情况下，该缓存控制器可以拒绝执行该内存访问指令。
在一些实施例中，存储器102可以包括内存，该计算机设备还包括内存控制器(memory controller，MC)。存储器102可以通过MC与每个处理器核对应的缓存控制器通信。在上述缓存控制器未查找到目标缓存行的情况下，该缓存控制器还可以通过MC从内存中查找对应的镜像指示信息，从而确定目标内存空间是否为镜像内存空间。
在一些实施例中，缓存控制器也可以称为缓存归属代理(caching and home agent，CHA)。缓存控制器用于控制缓存的读写。MC用于控制内存的读写，MC与处理器之间的位置关系也包括多种情况。比如，MC可以设置在处理器内部，也即是，MC与处理器集成在一起。MC也可以设置在处理器外部，也即是，MC与处理器分离设置，图1中未示出。
其中，处理器101可以是一个通用中央处理器(central processing unit，CPU)、网络处理器(network processor，NP)、微处理器、或者可以是一个或多个用于实现本申请方案的集成电路，例如，专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)、现场可编程逻辑门阵列(field-programmable gate array，FPGA)、通用阵列逻辑(generic array logic，GAL)或其任意组合。
存储器102可以是只读存储器(read-only memory，ROM)，也可以是随机存取存储器(random access memory，RAM)，也可以是电可擦可编程只读存储器(electrically erasable programmable read-only Memory，EEPROM)、光盘(包括只读光盘(compact disc read-only memory，CD-ROM)、压缩光盘、激光盘、数字通用光盘、蓝光光盘等)、磁盘存储介质或者其它磁存储设备，或者是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其它介质，但不限于此。存储器102可以是独立存 在，并与处理器101相连接。存储器102也可以和处理器101集成在一起。
通信接口103使用任何收发器一类的装置，用于与其它设备或通信网络通信。通信接口103包括有线通信接口，还可以包括无线通信接口。其中，有线通信接口例如可以为以太网接口。以太网接口可以是光接口、电接口或其组合。无线通信接口可以为无线局域网(wireless local area networks，WLAN)接口、蜂窝网络通信接口或其组合等。
在一些实施例中，计算机设备可以包括多个处理器，如图1中所示的处理器101和处理器104。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(如计算机程序指令)的处理器。
在一些实施例中，计算机设备还可以包括通信总线105。该通信总线105用于在上述组件之间传送信息。通信总线105可以分为地址总线、数据总线、控制总线等。为便于表示，图中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
在一些实施例中，计算机设备还可以包括输出设备106和输入设备107。输出设备106和处理器101通信，可以以多种方式来显示信息，例如从内存中读取的数据。输入设备107和处理器101通信，可以以多种方式接收用户输入的下述方法实施例涉及的命令或数据。
输出设备106可以是液晶显示器(liquid crystal display，LCD)、发光二级管(light emitting diode，LED)显示设备、阴极射线管(cathode ray tube，CRT)显示设备或投影仪(projector)等。输入设备107可以是鼠标、键盘、触摸屏设备或传感设备等。
在一些实施例中，存储器102用于存储执行本申请方案的程序代码，缓存控制器通过读取并执行存储器102中存储的程序代码来实现下述实施例中的方法。或者，处理器101内存存储有程序代码，缓存控制器通过执行处理器101内部存储的程序代码来实现下述实施例中的方法。该程序代码中可以包括一个或多个软件模块，比如后续装置实施例涉及的模块。
对本申请实施例涉及的术语和实施环境进行介绍之后，接下来对本申请实施例提供的内存访问方法进行详细地解释说明。
图2是本申请实施例提供的一种内存访问方法的流程图。请参考图2，该方法包括如下步骤。
步骤201：缓存控制器接收处理器核发送的内存访问指令，该内存访问指令用于访问目标内存空间。
该内存访问指令用于指示对目标内存空间进行读数据操作或者写数据操作。在该内存访问指令指示对目标内存空间进行读数据操作的情况下，该内存访问指令可以携带目标内存空间的内存地址。在该内存访问指令指示对目标内存空间进行写数据操作的情况下，该内存访问指令可以携带目标内存空间的内存地址和待写入的目标数据。
目标内存空间是指计算机设备的内存中当前需要访问的空间。目标内存空间可能为镜像内存空间，也可能为非镜像内存空间。也就是说，目标内存空间可能已启用内存镜像功能，也可能未启用内存镜像功能。
由于缓存的访问速度高于内存的访问速度，为了提高内存的访问效率，本申请实施例不仅将目标内存空间中的一些数据缓存在处理器核对应的缓存中，还可以将目标内存空间的镜像指示信息缓存在处理器核对应的缓存中。所以，在处理器核接收到内存访问指令之后，可以将该内存访问指令发送给缓存控制器，便于缓存控制器基于缓存中的数据进行后续的处理。
步骤202：缓存控制器基于缓存中该内存访问指令对应的目标缓存行的镜像指示信息，确定目标内存空间是否为镜像内存空间。
基于上文描述，目标内存空间可能为镜像内存空间，也可能为非镜像内存空间，而镜像指示信息能够区分目标内存空间是否为镜像内存空间。而且，在目标内存空间中的一些数据被缓存在处理器核对应的缓存的过程中，还可以将镜像指示信息缓存在处理器核对应的缓存中。这样，缓存控制器可以基于缓存中的镜像指示信息来确定目标内存空间是否为镜像内存空间，而无需从内存中获取镜像指示信息，提高了镜像内存空间的判断效率。
通常情况下，缓存包括多个缓存行，每个缓存行包括数据区和非数据区，数据区用于存储内存中的一部分数据，非数据区包括镜像指示字段，该镜像指示字段用于记录镜像指示信息，该镜像指示信息用于指示数据区中存储的数据在内存中所处的空间是否为镜像内存空间。所以，对于目标缓存行来说，目标缓存行包括数据区和非数据区，该数据区存储待访问的数据，该非数据区包括镜像指示字段，该镜像指示字段用于记录镜像指示信息。
在一些实施例中，每个缓存行的非数据区还可以存储数据区中的数据对应的内存地址。而且基于上文描述，该内存访问指令可以携带目标内存空间的内存地址，所以，缓存控制器可以将目标内存空间的内存地址与每个缓存行的非数据区的内存地址进行比较，从而确定与目标内存空间的内存地址匹配的缓存行，将该缓存行作为目标缓存行。
通常情况下，在分配目标内存空间之后，目标内存空间是否为镜像内存空间是确定的，此时，用于缓存目标内存空间的数据的各个缓存行的镜像指示信息也会是相同，所以，通过这些缓存行中任意一个缓存行的镜像指示信息都可以确定目标内存空间是否为镜像内存空间。也就是说，虽然目标缓存行的非数据区的镜像指示信息用于指示数据区的数据所在的内存空间是否为镜像内存空间，但是，该内存空间位于目标内存空间中，所以，通过目标缓存行的镜像指示信息也可以确定目标内存空间是否为镜像内存空间。
在一些实施例中，目标缓存行的镜像指示信息可能会被置位或者未被置位。在目标缓存行的镜像指示信息被置位的情况下，确定目标内存空间为镜像内存空间。在目标缓存行的镜像指示信息未被置位的情况下，确定目标内存空间不为镜像内存空间，即非镜像内存空间。
在某些情况下，镜像指示信息被置位也可以理解为镜像指示信息的取值为1，镜像指示信息未被置位可以理解为镜像指示信息的取值为0。当然，两者也可以反过来，即镜像指示信息被置位也可以理解为镜像指示信息的取值为0，镜像指示信息未被置位可以理解为镜像指示信息的取值为1。实际应用中，还可以通过其他方式来表征镜像指示信息是否被置位，本申请实施例对此不做限定。
由于缓存中可能只缓存部分内存数据，所以，缓存中也可能不存在目标缓存行。在这种情况下，可以从内存中获取镜像指示信息来确定目标内存空间是否为镜像内存空间。即，若缓存中不存在目标缓存行，则基于目标内存空间中该内存访问指令对应的目标非数据区的镜像指示信息，确定目标内存空间是否为镜像内存空间。
通常情况下，目标内存空间包括多个数据区和多个非数据区，该多个数据区与该多个非数据区一一对应，非数据区包括镜像指示信息，该镜像指示信息指示对应的数据区中的数据所在的内存空间是否为镜像内存空间。所以，对于目标非数据区来说，目标内存空间中还存在与目标非数据区对应的目标数据区。即，目标内存空间包括目标数据区和目标非数据区，目标数据区中存储待访问的数据，目标非数据区存储镜像指示信息。
与上文同理，在分配目标内存空间之后，目标内存空间是否为镜像内存空间是确定的，此时，目标内存空间包括的各个非数据区的镜像指示信息也会是相同，所以，通过这些非数据区中任意一个非数据区的镜像指示信息都可以确定目标内存空间是否为镜像内存空间。也就是说，虽然目标非数据区的镜像指示信息用于指示目标数据区的数据所在的内存空间是否为镜像内存空间，但是，该内存空间位于目标内存空间中，所以，通过目标非数据区的镜像指示信息也可以确定目标内存空间是否为镜像内存空间。
在一些实施例中，目标非数据区的镜像指示信息可能会被置位或者未被置位。在目标非数据区的镜像指示信息被置位的情况下，确定目标内存空间为镜像内存空间。在目标非数据区的镜像指示信息未被置位的情况下，确定目标内存空间不为镜像内存空间，即非镜像内存空间。
示例地，请参考图3，处理器核对应有缓存控制器和缓存，缓存控制器还可以与内存控制器通信，内存控制器用于控制内存。缓存行包括数据区和非数据区，非数据区可以包括两部分，分别为属性区和标志区，属性区存储有数据区的数据的内存地址，标志区包括镜像指示字段，该镜像指示字段用于记录镜像指示信息。内存包括多个数据区和多个非数区，图3中以一个数据区和一个非数据区进行示意性说明，该非数据区存储有镜像指示信息。
需要说明的是，对于缓存行的非数据区来说，上述是以属性区存储内存地址为例，实际应用中，属性区也可能还存储其他的数据。同理，上述是以标志区存储镜像指示信息为例，实际应用中，标志区还可能存储其他的标志位等等，本申请实施例对此不做限定。对于内存的非数据区来说，上述是以该非数据区存储镜像指示信息为例，实际应用中，该非数据区还可能存储其他的信息，本申请实施例同样对此不做限定。
内存可以为双列直插式存储模块(dual inline memory modules，DIMM)，带有寄存器的双列直插式存储模块(registered DIMM，RDIMM)、低负荷双列直插式存储模块(load reduced DIMM，LRDIMM)，当然，还可以为其他的存储模块。
基于上文描述，缓存中的数据是将内存中的数据进行缓存得到的，所以，在将内存中某个数据区的数据进行缓存时，还可以读取该数据区对应的非数据区的镜像指示信息，进而将该镜像指示信息也进行缓存， 从而便于后续通过缓存中的镜像指示信息来确定该数据所在的内存空间是否为镜像内存空间。
需要说明的是，为了配合缓存行，内存中的数据区的粒度可以与缓存行的粒度相同，即，内存中的数据区的尺寸可以与缓存行的尺寸相同。
上述是先确定缓存中是否包括目标缓存行，在包括目标缓存行的情况下，直接基于目标缓存行的镜像指示信息来确定目标内存空间是否为镜像内存空间，在不包括目标缓存行的情况下，再基于内存中目标非数据区的镜像指示信息来确定目标内存空间是否为镜像内存空间。当然，在实际应用中，也可以直接基于内存中目标非数据区的镜像指示信息来确定目标内存空间是否为镜像内存空间。
经过上述内容能够确定出目标内存空间是否为镜像内存空间，从而便于后续对目标内存空间进行操作。
在一些实施例中，若目标内存空间为镜像内存空间，且该内存访问指令为非镜像访问模式，则缓存控制器拒绝执行该内存访问指令。
在目标内存空间为镜像内存空间，且该内存访问指令为非镜像访问模式的情况下，表明当前需要通过非镜像访问模式来访问镜像内存空间，这可能存在非法访问的情况，所以，缓存控制器通过拒绝执行该内存访问指令，能够避免镜像内存数据被非法访问的情况，从而提高镜像内存数据的安全性。
非镜像访问模式是指该内存访问指令不是镜像访问指令。镜像访问模式是指该内存访问指令为镜像访问指令，或者该内存访问指令不是镜像访问指令但该内存访问指令的参数带有镜像标志。其中，镜像访问指令的格式与普通的内存访问指令的格式不同。
在一些实施例中，镜像内存空间是否拒绝非镜像访问模式还可以进行配置。这样，在目标内存空间为镜像内存空间，且该内存访问指令为非镜像访问模式的情况下，缓存控制器还可以获取目标内存空间的镜像配置信息，该镜像配置信息指示目标内存空间是否拒绝非镜像访问模式的访问，若该镜像配置信息指示目标内存空间拒绝非镜像访问模式的访问，则缓存控制器拒绝执行内存访问指令。若该镜像配置信息指示目标内存空间允许非镜像访问模式的访问，则缓存控制器对目标内存空间执行该内存访问指令对应的操作。
目标内存空间的镜像配置信息可以是在分配目标内存空间时设置的，即目标内存空间的镜像配置信息是事先设置的。当然，在实际应用中，目标内存空间的镜像配置信息还可以按照不同的需求进行调整，本申请实施例对此不做限定。
在一些实施例中，若目标内存空间为镜像内存空间，且该内存访问指令为镜像访问模式，则缓存控制器对目标内存空间执行该内存访问指令对应的操作。
基于上文描述，该内存访问指令用于指示对目标内存空间进行读数据操作或者写数据操作。在该内存访问指令指示对目标内存空间进行读数据操作的情况下，缓存控制器可以基于该内存访问指令携带的内存地址，从目标内存空间中读取对应的数据。在该内存访问指令指示对目标内存空间进行写数据操作的情况下，缓存控制器可以基于该内存访问指令携带的内存地址，将该内存访问指令携带的目标数据写入目标内存空间。
在该内存访问指令指示对目标内存空间进行读数据操作的情况下，缓存控制器可以基于该内存访问指令携带的内存地址，确定缓存中是否存在对应的数据，如果缓存中存在对应的数据，可以直接从缓存中读取对应的数据，如果缓存中不存在对应的数据，可以从目标内存空间中读取对应的数据。
在该内存访问指令指示对目标内存空间进行写数据操作的情况下，缓存控制器可以基于该内存访问指令携带的内存地址，确定缓存中是否存在对应的缓存行，如果缓存中存在对应的缓存行，可以直接将目标数据写入缓存，之后再写入目标内存空间，如果缓存中不存在对应的缓存行，可以将目标数据写入目标内存空间。
基于上文描述，缓存控制器用于控制缓存的读写，内存控制器用于控制内存的读写，所以，不管是从目标内存空间中读取数据，还是向目标内存空间写入数据，缓存控制器都需要通过内存控制器来实现。即，缓存控制器通过内存控制器从目标内存空间中读取数据，以及通过内存控制器向目标内存空间写入数据。
在一些实施例中，内存访问指令为内存写指令，该内存写指令携带待写入的目标数据，目标内存空间包括主内存空间和备内存空间。此时，缓存控制器向内存控制器发送内存写通知，以指示内存控制器在该主内存空间和备内存空间中均写入目标数据。即，内存控制器接收到缓存控制器发送的内存写通知之后，在该主内存空间和备内存空间中均写入目标数据。
上述目标内存空间是事先为目标对象分配的。即，接收目标对象的内存分配请求，该内存分配请求用于请求目标内存空间，响应于目标对象的镜像标志被置位，为目标对象分配目标内存空间，并对目标内存 空间中各个非数据区的镜像指示信息进行置位。
进一步地，响应于目标对象的镜像标志未被置位，为目标对象分配目标内存空间，此时，目标内存空间并未开启内存镜像功能。
目标对象是指计算机设备中允许占用内存空间的软件模块。例如，目标对象包括而不限于进程、内核、进程的部分VMA段、内核中的部分模块等。内存分配请求指示为目标对象分配目标内存空间。在一些实施例中，不同类型的目标对象具有不同的镜像标志。例如，内核的镜像标志与进程的镜像标志不同。
在某些情况下，目标对象的镜像标志被置位也可以理解为目标对象的镜像标志的取值为1，目标对象的镜像标志未被置位可以理解为目标对象的镜像标志的取值为0。当然，两者也可以反过来，即目标对象的镜像标志被置位也可以理解为目标对象的镜像标志的取值为0，目标对象的镜像标志未被置位可以理解为目标对象的镜像标志的取值为1。实际应用中，还可以通过其他方式来表征目标对象的镜像标志是否被置位，本申请实施例对此不做限定。
在接收到目标对象的内存分配请求之后，如果目标对象的镜像标志被置位，表明当前需要为目标对象分配目标内存空间，而且目标内存空间需要开启内存镜像功能。所以，在为目标对象分配目标内存空间之后，可以为目标内存空间中各个非数据区的镜像指示信息进行置位，从而开启目标内存空间的内存镜像功能。也就是说，本申请实施例可以按照目标对象的需求来确定是否需要为目标对象分配的内存空间开启内存镜像功能。
通过上述方式，针对目标对象运行时实际请求分配的内存采用镜像保护，避免预设过大的镜像内存导致内存资源浪费，同时避免预设的镜像内存不足导致业务中断。
在目标对象需要释放目标内存空间时，还可以取消目标内存空间的内存镜像功能，这样便于内存空间的回收。即，接收目标对象的内存释放请求，该内存释放请求用于释放目标内存空间，释放为目标对象分配的目标内存空间，并取消目标内存空间中各个数据区的镜像指示信息的置位。
需要说明的是，本申请实施例涉及的内存访问指令可以为直接内存访问指令，即DMA指令，也可以为直接缓存访问指令，即DCA指令，本申请实施例对此不做限定。在内存访问指令为直接内存访问指令的情况下，按照本申请实施例提供的方法能够拒绝非镜像模式的直接内存访问指令对内存的镜像内存空间中的数据的访问。在内存访问指令为直接缓存访问指令的情况下，按照本申请实施例提供的方法能够拒绝非镜像模式的直接缓存访问指令对缓存中所缓存的镜像内存空间的数据的访问。
在相关技术中，处理器核接收到内存访问指令之后，需要通过内存控制器获取目标内存空间中的页表项存储的镜像指示信息，进而通过该镜像指示信息确定目标内存空间是否为镜像内存空间。也就是说，内存中的页表项存储有目标内存空间的镜像指示信息，用来确定目标内存空间是否为镜像内存空间。而本申请实施例中，缓存中用于缓存目标内存空间的数据的各个缓存行均缓存有镜像指示信息，用于确定目标内存空间是否为镜像内存空间，这样，在缓存控制器接收到处理器核发送的内存访问指令之后，可以通过内存访问指令对应的目标缓存行的镜像指示信息来确定目标内存空间是否为镜像内存空间，无需通过访问内存来确定目标内存空间是否为镜像内存空间，可以避免通过获取内存中的镜像指示信息而导致延迟增加的问题，从而能够提高内存访问的效率。而且，在目标内存空间为镜像内存空间且该内存访问指令为非镜像访问模式的情况下，缓存控制器可以拒绝执行该内存访问指令，这样，可以避免镜像内存数据被非法访问，提高镜像内存数据的安全性。
接下来通过图4和图5对本申请实施例提供的方法进行介绍。其中，图4是以内存读指令为例进行介绍，图5是以内存写指令为例进行介绍。而且，图4和图5将分为A、B、C、D四个场景进行介绍。
请参考图4，在场景A中，缓存控制器接收来自目标对象的镜像访问模式的内存读指令，基于该内存读指令确定缓存中不存在待读取的数据。此时，缓存控制器可以通过内存控制器，确定内存中存在待读取的数据，而且对应的镜像指示信息为1，即镜像指示信息被置位。这样，内存控制器可以从内存中读取对应的数据以及该镜像指示信息，并将读取的数据和该镜像指示信息发送给缓存控制器。缓存控制器接收读取到的数据以及镜像指示信息，确定该镜像指示信息被置位，然后将读取到的数据发送给目标对象。
在场景B中，缓存控制器接收来自目标对象的非镜像访问模式的内存读指令，基于该内存读指令确定缓存中不存在待读取的数据。此时，缓存控制器可以通过内存控制器，确定内存中存在待读取的数据，而且对应的镜像指示信息为1，即镜像指示信息被置位。这样，内存控制器可以从内存中读取对应的数据以 及该镜像指示信息，并将读取的数据和该镜像指示信息发送给缓存控制器。缓存控制器接收读取到的数据以及镜像指示信息，确定该镜像指示信息被置位，然后向目标对象发送指令不支持的提示信息，即，拒绝执行该内存读指令。
在场景C中，缓存控制器接收来自目标对象的镜像访问模式的内存读指令，基于该内存读指令确定缓存中存在待读取的数据。此时，缓存控制器从缓存中读取对应的数据和镜像指示信息，而且该镜像指示信息为1，即镜像指示信息被置位。这样，缓存控制器将读取到的数据发送给目标对象。
在场景D中，缓存控制器接收来自目标对象的镜像访问模式的内存读指令，基于该内存读指令确定缓存中存在待读取的数据。此时，缓存控制器从缓存中读取对应的数据和镜像指示信息，而且该镜像指示信息为1，即镜像指示信息被置位。这样，缓存控制器向目标对象发送指令不支持的提示信息，即，拒绝执行该内存读指令。
请参考图5，在场景A中，缓存控制器接收来自目标对象的镜像访问模式的内存写指令，基于该内存写指令确定缓存中不存在待写入的数据所在的缓存行。此时，缓存控制器可以通过内存控制器，确定内存中存在待写入的数据对应的内存空间，而且对应的镜像指示信息为1，即镜像指示信息被置位。这样，内存控制器可以将该镜像指示信息发送给缓存控制器，然后，缓存控制器向内存写入对应的数据。
在场景B中，缓存控制器接收来自目标对象的非镜像访问模式的内存写指令，基于该内存写指令确定缓存中不存在待写入的数据所在的缓存行。此时，缓存控制器可以通过内存控制器，确定内存中存在待写入的数据对应的内存空间，而且对应的镜像指示信息为1，即镜像指示信息被置位。这样，内存控制器可以将该镜像指示信息发送给缓存控制器。然后缓存控制器向目标对象发送指令不支持的提示信息，即，拒绝执行该内存写指令。
在场景C中，缓存控制器接收来自目标对象的镜像访问模式的内存写指令，基于该内存写指令确定缓存中存在待写入的数据所在的缓存行。此时，缓存控制器从缓存中读取对应的数据和镜像指示信息，而且该镜像指示信息为1，即镜像指示信息被置位。这样，缓存控制器基于读取到的数据和待写入的数据，通过内存控制器向内存中写入对应的数据。
在场景D中，缓存控制器接收来自目标对象的镜像访问模式的内存写指令，基于该内存写指令确定缓存中存在待读取的数据。此时，缓存控制器从缓存中读取对应的数据和镜像指示信息，而且该镜像指示信息为1，即镜像指示信息被置位。这样，缓存控制器向目标对象发送指令不支持的提示信息，即，拒绝执行该内存写指令。
图6是本申请实施例提供的一种内存访问装置的结构示意图，该装置可以由软件、硬件或者两者的结合实现成为计算机设备的部分或者全部，该计算机设备可以为图1所示的计算机设备。参见图6，该装置包括：指令接收模块601和第一确定模块602。
指令接收模块601，用于接收处理器核发送的内存访问指令，内存访问指令用于访问目标内存空间；
第一确定模块602，用于基于缓存中内存访问指令对应的目标缓存行的镜像指示信息，确定目标内存空间是否为镜像内存空间。
可选地，目标缓存行包括数据区和非数据区，该数据区存储待访问的数据，该非数据区包括镜像指示字段，该镜像指示字段用于记录镜像指示信息。
可选地，该装置还包括：
第二确定模块，用于若缓存中不存在目标缓存行，则基于目标内存空间中内存访问指令对应的目标非数据区的镜像指示信息，确定目标内存空间是否为镜像内存空间。
可选地，目标内存空间包括目标数据区和目标非数据区，目标数据区中存储待访问的数据，目标非数据区存储镜像指示信息。
可选地，该装置还包括：
指令执行模块，用于若目标内存空间为镜像内存空间，且内存访问指令为镜像访问模式，则对目标内存空间执行内存访问指令对应的操作。
可选地，该装置还包括：
指令拒绝模块，用于若目标内存空间为镜像内存空间，且该内存访问指令为非镜像访问模式，则拒绝执行该内存访问指令。
可选地，指令拒绝模块具体用于：
获取目标内存空间的镜像配置信息，镜像配置信息指示目标内存空间是否拒绝非镜像访问模式的访问；
若镜像配置信息指示目标内存空间拒绝非镜像访问模式的访问，则拒绝执行内存访问指令。
可选地，该指令执行模块，还用于若镜像配置信息指示目标内存空间允许非镜像访问模式的访问，则对目标内存空间执行内存访问指令对应的操作。
可选地，该内存访问指令为内存写指令，内存写指令携带待写入的目标数据，目标内存空间包括主内存空间和备内存空间；
指令执行模块具体用于：
向内存控制器发送内存写通知，以指示内存控制器在主内存空间和备内存空间中均写入目标数据。
可选地，该装置还包括：
分配请求接收模块，用于接收目标对象的内存分配请求，内存分配请求用于请求目标内存空间；
内存分配模块，用于响应于目标对象的镜像标志被置位，为目标对象分配目标内存空间，并对目标内存空间中各个非数据区的镜像指示信息进行置位。
可选地，该装置还包括：
释放请求接收模块，用于接收目标对象的内存释放请求，内存释放请求用于释放目标内存空间；
内存释放模块，用于释放为目标对象分配的目标内存空间，并取消目标内存空间中各个非数据区的镜像指示信息的置位。
在本申请实施例中，在缓存控制器接收到处理器核发送的内存访问指令之后，可以基于目标缓存行的镜像指示信息确定目标内存空间是否为镜像内存空间，在目标内存空间为镜像内存空间且该内存访问指令为非镜像访问模式的情况下，缓存控制器可以拒绝执行该内存访问指令，这样，可以避免镜像内存数据被非法访问，提高镜像内存数据的安全性。而且，通过缓存中的目标缓存行的镜像指示信息来确定目标内存空间是否为镜像内存空间，可以避免通过获取内存中的镜像指示信息而导致延迟增加的问题，从而能够提高内存访问的效率。
需要说明的是：上述实施例提供的内存访问装置在进行内存访问时，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的内存访问装置与内存访问方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
本申请实施例还提供了一种处理器，该处理器包括缓存控制器，该缓存控制器用于实现上述实施例的内存访问方法。
本申请实施例还提供了一种内存访问装置，该内存访问装置包括处理器和存储器，存储器用于存储执行上述第一方面所提供的内存访问方法的计算机程序。处理器被配置为用于执行存储器中存储的计算机程序，以实现上述实施例的内存访问方法。
可选地，内存访问装置还可以包括通信总线，该通信总线用于该处理器与存储器之间建立连接。
本申请实施例还提供了一种计算机可读存储介质，该存储介质内存储有指令，当指令在计算机上运行时，使得计算机执行上述实施例的内存访问方法。
本申请实施例还提供了一种包含指令的计算机程序产品，当指令在计算机上运行时，使得计算机执行上述实施例的内存访问方法的步骤。或者说，提供了一种计算机程序，当计算机程序在计算机上运行时，使得计算机执行上述实施例的内存访问方法。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意结合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络或其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如：同轴电缆、光纤、数据用户线(digital subscriber line，DSL))或无线(例如：红外、无线、微波等)方式向另一个网站站点、计算机、 服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质，或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如：软盘、硬盘、磁带)、光介质(例如：数字通用光盘(digital versatile disc，DVD))或半导体介质(例如：固态硬盘(solid state disk，SSD))等。值得注意的是，本申请实施例提到的计算机可读存储介质可以为非易失性存储介质，换句话说，可以是非瞬时性存储介质。
应当理解的是，本文提及的“多个”是指两个或两个以上。在本申请实施例的描述中，除非另有说明，“/”表示或的意思，例如，A/B可以表示A或B；本文中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，为了便于清楚描述本申请实施例的技术方案，在本申请实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
需要说明的是，本申请实施例所涉及的信息(包括但不限于用户设备信息、用户个人信息等)、数据(包括但不限于用于分析的数据、存储的数据、展示的数据等)以及信号，均为经用户授权或者经过各方充分授权的，且相关数据的收集、使用和处理需要遵守相关国家和地区的相关法律法规和标准。
以上所述为本申请提供的实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (24)

  1. 一种内存访问方法，其特征在于，所述方法包括：
    缓存控制器接收处理器核发送的内存访问指令，所述内存访问指令用于访问目标内存空间；
    所述缓存控制器基于缓存中所述内存访问指令对应的目标缓存行的镜像指示信息，确定所述目标内存空间是否为镜像内存空间。
  2. 如权利要求1所述的方法，其特征在于，所述目标缓存行包括数据区和非数据区，所述数据区存储待访问的数据，所述非数据区包括镜像指示字段，所述镜像指示字段用于记录所述镜像指示信息。
  3. 如权利要求1或2所述的方法，其特征在于，所述方法还包括：
    若所述缓存中不存在所述目标缓存行，则所述缓存控制器基于所述目标内存空间中所述内存访问指令对应的目标非数据区的镜像指示信息，确定所述目标内存空间是否为镜像内存空间。
  4. 如权利要求3所述的方法，其特征在于，所述目标内存空间包括目标数据区和所述目标非数据区，所述目标数据区中存储待访问的数据，所述目标非数据区存储所述镜像指示信息。
  5. 如权利要求1-4任一所述的方法，其特征在于，所述方法还包括：
    若所述目标内存空间为镜像内存空间，且所述内存访问指令为镜像访问模式，则所述缓存控制器对所述目标内存空间执行所述内存访问指令对应的操作。
  6. 如权利要求1-5任一所述的方法，其特征在于，所述方法还包括：
    若所述目标内存空间为镜像内存空间，且所述内存访问指令为非镜像访问模式，则所述缓存控制器拒绝执行所述内存访问指令。
  7. 如权利要求6所述的方法，其特征在于，所述缓存控制器拒绝执行所述内存访问指令，包括：
    所述缓存控制器获取所述目标内存空间的镜像配置信息，所述镜像配置信息指示所述目标内存空间是否拒绝非镜像访问模式的访问；
    若所述镜像配置信息指示所述目标内存空间拒绝非镜像访问模式的访问，则所述缓存控制器拒绝执行所述内存访问指令。
  8. 如权利要求7所述的方法，其特征在于，所述缓存控制器获取所述目标内存空间的镜像配置信息之后，所述方法还包括：
    若所述镜像配置信息指示所述目标内存空间允许非镜像访问模式的访问，则所述缓存控制器对所述目标内存空间执行所述内存访问指令对应的操作。
  9. 如权利要求5或8所述的方法，其特征在于，所述内存访问指令为内存写指令，所述内存写指令携带待写入的目标数据，所述目标内存空间包括主内存空间和备内存空间；
    所述缓存控制器对所述目标内存空间执行所述内存访问指令对应的操作，包括：
    所述缓存控制器向内存控制器发送内存写通知，以指示所述内存控制器在所述主内存空间和所述备内存空间中均写入所述目标数据。
  10. 如权利要求1-9任一所述的方法，其特征在于，所述方法还包括：
    接收目标对象的内存分配请求，所述内存分配请求用于请求所述目标内存空间；
    响应于所述目标对象的镜像标志被置位，为所述目标对象分配所述目标内存空间，并对所述目标内存空间中各个非数据区的镜像指示信息进行置位。
  11. 如权利要求10所述的方法，其特征在于，所述方法还包括：
    接收所述目标对象的内存释放请求，所述内存释放请求用于释放所述目标内存空间；
    释放为所述目标对象分配的所述目标内存空间，并取消所述目标内存空间中各个非数据区的镜像指示信息的置位。
  12. 一种处理器，其特征在于，所述处理器包括缓存控制器，所述缓存控制器用于：
    接收处理器核发送的内存访问指令，所述内存访问指令用于访问目标内存空间；
    基于缓存中所述内存访问指令对应的目标缓存行的镜像指示信息，确定所述目标内存空间是否为镜像内存空间。
  13. 如权利要求12所述的处理器，其特征在于，所述目标缓存行包括数据区和非数据区，所述数据区存储待访问的数据，所述非数据区包括镜像指示字段，所述镜像指示字段用于记录所述镜像指示信息。
  14. 如权利要求12或13所述的处理器，其特征在于，所述缓存控制器还用于：
    若所述缓存中不存在所述目标缓存行，则基于所述目标内存空间中所述内存访问指令对应的目标非数据区的镜像指示信息，确定所述目标内存空间是否为镜像内存空间。
  15. 如权利要求14所述的处理器，其特征在于，所述目标内存空间包括目标数据区和所述目标非数据区，所述目标数据区中存储待访问的数据，所述目标非数据区存储所述镜像指示信息。
  16. 如权利要求12-15任一所述的处理器，其特征在于，所述缓存控制器还用于：
    若所述目标内存空间为镜像内存空间，且所述内存访问指令为镜像访问模式，则对所述目标内存空间执行所述内存访问指令对应的操作。
  17. 如权利要求12-16任一所述的处理器，其特征在于，所述缓存控制还用于：
    若所述目标内存空间为镜像内存空间，且所述内存访问指令为非镜像访问模式，则拒绝执行所述内存访问指令。
  18. 如权利要求17所述的处理器，其特征在于，所述缓存控制器具体用于：
    获取所述目标内存空间的镜像配置信息，所述镜像配置信息指示所述目标内存空间是否拒绝非镜像访问模式的访问；
    若所述镜像配置信息指示所述目标内存空间拒绝非镜像访问模式的访问，则拒绝执行所述内存访问指令。
  19. 如权利要求18所述的处理器，其特征在于，所述缓存控制器还用于：
    若所述镜像配置信息指示所述目标内存空间允许非镜像访问模式的访问，则对所述目标内存空间执行所述内存访问指令对应的操作。
  20. 如权利要求16或19所述的处理器，其特征在于，所述内存访问指令为内存写指令，所述内存写指令携带待写入的目标数据，所述目标内存空间包括主内存空间和备内存空间；
    所述缓存控制器具体用于：
    向内存控制器发送内存写通知，以指示所述内存控制器在所述主内存空间和所述备内存空间中均写入所述目标数据。
  21. 如权利要求12-20任一所述的处理器，其特征在于，所述处理器还用于：
    接收目标对象的内存分配请求，所述内存分配请求用于请求所述目标内存空间；
    响应于所述目标对象的镜像标志被置位，为所述目标对象分配所述目标内存空间，并对所述目标内存空间中各个非数据区的镜像指示信息进行置位。
  22. 如权利要求21所述的处理器，其特征在于，所述处理器还用于：
    接收所述目标对象的内存释放请求，所述内存释放请求用于释放所述目标内存空间；
    释放为所述目标对象分配的所述目标内存空间，并取消所述目标内存空间中各个非数据区的镜像指示信息的置位。
  23. 一种内存访问装置，其特征在于，所述装置包括存储器和处理器，所述存储器用于存储计算机程序，所述处理器被配置为执行所述计算机程序，以实现权利要求1-11任一所述的方法。
  24. 一种计算机可读存储介质，其特征在于，所述存储介质内存储有指令，当所述指令在所述计算机上运行时，使得所述计算机执行权利要求1-11任一所述的方法。
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