WO2022228287A1 - 内存数据获取方法、装置及存储介质 - Google Patents

内存数据获取方法、装置及存储介质 Download PDF

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Publication number
WO2022228287A1
WO2022228287A1 PCT/CN2022/088354 CN2022088354W WO2022228287A1 WO 2022228287 A1 WO2022228287 A1 WO 2022228287A1 CN 2022088354 W CN2022088354 W CN 2022088354W WO 2022228287 A1 WO2022228287 A1 WO 2022228287A1
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Prior art keywords
page table
target
address register
base address
vmi
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PCT/CN2022/088354
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English (en)
French (fr)
Inventor
章张锴
赵思齐
陈谋
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华为技术有限公司
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Publication of WO2022228287A1 publication Critical patent/WO2022228287A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/45583—Memory management, e.g. access or allocation

Definitions

  • the embodiments of the present application relate to the field of virtualization technologies, and in particular, to a method, an apparatus, and a storage medium for acquiring memory data.
  • the hardware resources of a computer device can be divided into a rich execution environment (Rich Execution Environment, REE) side and a Trusted Execution Environment (Trusted Execution Environment, TEE) side.
  • REE Rich Execution Environment
  • TEE Trusted Execution Environment
  • the REE side includes multiple virtual machines (Virtual Machines, VMs).
  • VMs Virtual Machines
  • the VMs are used to process user-related data.
  • the security of the REE side is lower than that of the TEE side.
  • the VMs are easily attacked maliciously, resulting in lower security of user data. Therefore, it is necessary to obtain the memory data of the VM to monitor the VM, so as to prevent the VM from being maliciously attacked.
  • VMI Virtual machine introspection
  • the related art proposes a method for acquiring memory data with VMI technology.
  • the method introduces an Immersive Execution Environment (Immersive Execution EnvironmentImEE) system, and an extended page table (Extended Page Table, EPT) of the target VM includes one or more Multiple page table entries are modified, and the modified page table entries point to the VMI program.
  • the ImEE system can use the virtual address of the target VM to directly determine the corresponding physical address from the EPT by running the VMI program. In this way, the memory data of the target VM can be read quickly and efficiently, and since the virtual address can provide some semantic information, the ImEE system can effectively detect whether the target VM is maliciously attacked.
  • the data corresponding to the modified page table entries are the code and data of the VMI program, not the code and data of the target VM, that is, these page table entries
  • the code and data of the original corresponding target VM are not monitored, so there will be monitoring blind spots.
  • the embodiments of the present application provide a method, device, and storage medium for acquiring memory data, which can avoid the situation of monitoring blind spots to a certain extent.
  • the present application is described below through various aspects, and it should be understood that the implementation manners and beneficial effects of the following aspects can be referred to each other.
  • a first aspect provides a method for acquiring memory data, in which hardware resources of a computer device are divided into a REE side and a TEE side, the REE side includes one or more VMs, and the TEE side includes one or more SPs,
  • a VMI program is deployed on the TEE side, and the method includes: the processor shares a first page table for address mapping on the REE side to the TEE side, where the first page table refers to a page table that maps virtual addresses to intermediate addresses.
  • the processor runs the VMI program in the target SP, the target SP refers to the SP used to obtain the memory data of the target VM in one or more SPs, and the target VM refers to any one of the one or more VMs.
  • the processor obtains the memory data of the target VM through the VMI program running in the target SP according to the target virtual address, the first page table and the second page table.
  • the second page table is shared by the TEE side and the REE side and used to convert the intermediate address A page table mapped to a physical address, and the target virtual address refers to the virtual address corresponding to the memory data to be acquired.
  • the first page table refers to the page table that maps virtual addresses to intermediate addresses
  • the second page table refers to the page table shared by the TEE side and the REE side and used to map intermediate addresses to physical addresses. Therefore, on the REE side and the TEE side After the side shares the first page table and the second page table, the target SP on the TEE side can determine the physical address corresponding to the virtual address of the target VM according to the first page table and the second page table, and then can quickly and efficiently obtain the target VM's virtual address. memory data.
  • the VMI program running in the target SP will not occupy the page table of the target VM, that is, the page table entry in the first page table or the second page table will not be modified to point to the VMI program running in the target SP , so that there will be no monitoring blind spots.
  • the VMI program running in the target SP can be well hidden on the REE side, and the target VM cannot perceive the existence of the target SP.
  • both the REE side and the TEE side also include a first base address register and a second base address register, and the first base address register is the base address corresponding to the user space.
  • the second base register is the base register corresponding to the kernel space. That is to say, the first base register points to a page table in user space for mapping from virtual addresses to intermediate addresses, and the second base register points to a page table in kernel space for mapping from virtual addresses to intermediate addresses.
  • the processor shares the page table pointed to by the first base address register on the REE side as the first page table with the first base address register on the TEE side.
  • the processor shares the page table pointed to by the second base address register on the REE side to the second base address register on the TEE side as the first page table.
  • the processor can work on the REE side, it can also work on the TEE side, and the processor can switch back and forth between the REE side and the TEE side.
  • the processor works on the REE side
  • the hardware resources on the TEE side are prohibited from being accessed.
  • the processor can access both the hardware resources on the TEE side and the hardware resources on the REE side.
  • the memory data of the target VM on the REE side is obtained through the target SP on the TEE side. Therefore, in the embodiment of the present application, the processor works on the TEE side.
  • the processor can access the first base address register and the second base address register on the REE side, so as to determine the page table pointed to by the first base address register and the page table pointed to by the second base address register, and then to obtain
  • the page table pointed to by the first base address register is shared with the TEE side as the first page table.
  • the The page table pointed to by the two base address registers is shared with the TEE side as the first page table.
  • the processor may also directly share the page table of the first base address register and/or the second base address register to the TEE side without going through the judgment of the foregoing two "conditions".
  • the base address register is used to store the memory entry address, so as to point to the data corresponding to the memory entry address (the data refers to page table data in this embodiment). Therefore, the implementation process of the processor sharing the page table pointed to by the first base address register on the REE side to the first base address register on the TEE side as the first page table includes: The address is modified to the page table entry address stored in the first base address register on the REE side, so as to share the page table pointed to by the first base address register on the REE side as the first page table to the first base address register on the TEE side.
  • the implementation process of the processor sharing the page table pointed to by the second base address register on the REE side as the first page table to the second base address register on the TEE side includes: storing the second base address register on the TEE side.
  • the address of the REE side is modified to the page table entry address stored in the second base address register on the REE side, so as to share the page table pointed to by the second base address register on the REE side as the first page table to the second base address register on the TEE side .
  • VMI programs are deployed in both the user space and the kernel space on the TEE side.
  • the processor shares the page table pointed to by the first base address register on the REE side as the first page table to the first base address register on the TEE side, It is also necessary to point the second base address register on the TEE side to the VMI program deployed in the kernel space of the TEE side, and run the VMI program pointed to by the second base address register in the target SP with kernel mode authority.
  • the processor shares the page table pointed to by the second base address register on the REE side as the first page table with the second base address register on the TEE side, it is also necessary to Point the first base address register on the TEE side to the VMI program deployed in the user space on the TEE side, and run the VMI program pointed to by the first base address register in the target SP with the kernel mode authority.
  • the processor can work in user mode and also in kernel mode.
  • the second base address register on the TEE side The address register points to the VMI program deployed in the kernel space of the TEE side, so that the processor runs the VMI program deployed in the kernel space of the TEE side in the target SP, thereby realizing the isolation of the target SP and the target VM.
  • the The first base address register points to the VMI program deployed in the user space of the TEE side, so that the processor runs the VMI program deployed in the user space of the TEE side in the target SP, thereby realizing the isolation of the target SP and the target VM.
  • the memory data to be acquired may be the data of the target VM in the user space, or may be the data of the target VM in the kernel space.
  • the second base register on the TEE side points to the VMI program deployed in the kernel space on the TEE side. Since the code and data of the VMI program are located in the kernel space, the memory data to be acquired is located in the user space, and the permission level of the kernel mode is higher than that of the user mode, the processor in the kernel mode can access the hardware resources of the user space.
  • the processor runs the VMI program located in the kernel space in the target SP with the kernel mode authority, so that the memory data in the user space can be successfully read. That is, the VMI program pointed to by the second base address register is run in the target SP with the kernel mode authority, thereby successfully reading the memory data in the user space.
  • the memory data to be acquired is the data of the target VM in the kernel space
  • the first base address register on the TEE side will point to the VMI program deployed in the user space of the TEE side. Since the code and data of the VMI program are located in the user space, the memory data to be acquired is located in the kernel space, and the permission level of the kernel mode is higher than that of the user mode. , so that if the memory data of the kernel space is obtained, an error will occur during the permission check. Therefore, in the embodiment of the present application, when the processor runs the VMI program in the target SP, it needs to run the VMI program in the target SP with the kernel state permission. The VMI program of the space can successfully read the memory data of the kernel space. That is, running the VMI program pointed to by the first base address register in the target SP with the kernel state authority can successfully read the memory data in the kernel space, thus solving the problem that the VMI program in the user space cannot read the data in the kernel space. .
  • the VMI program needs to access the memory data required by itself during the running process, but the VMI program is located on the TEE side, the memory data required by the VMI program will also be stored in the secure memory, and the memory data of the target VM.
  • the TEE side further includes a fourth base address register (such as the above vsttbr_el2), the fourth base address register points to the third page table, and the third page table refers to the The page table where the VMI program runs normally and performs intermediate address-to-physical address mapping.
  • the processor can run the VMI program in the target SP according to the third page table pointed to by the fourth base address register, thereby ensuring that the VMI program can access the memory data required by itself in the secure memory during the running process. At the same time, it can better isolate the running of the VMI program from the target VM.
  • both the REE side and the REE side further include a third base address register, and both the third base address register on the REE side and the third base address register on the TEE side point to the second page table.
  • the realization process that the processor obtains the memory data of the target VM through the VMI program running in the target SP according to the target virtual address, the first page table and the second page table includes: in the process of the processor running the VMI program in the target SP , the MMU determines the intermediate address corresponding to the target virtual address according to the first page table, and determines the physical address corresponding to the intermediate address according to the second page table pointed to by the third base address register on the TEE side.
  • the processor obtains the memory data corresponding to the physical address through the VMI program running in the target SP.
  • the implementation process of determining the physical address corresponding to the intermediate address by the MMU according to the second page table pointed to by the third base address register on the TEE side includes: when the page table entry where the intermediate address is located is stored in the secure memory, using the MMU Get the NS bit in the page table entry where the intermediate address is located. If the NS bit is the first value, the MMU determines the physical address corresponding to the intermediate address according to the second page table pointed to by the third base address register on the TEE side. When the page table entry where the intermediate address is located is stored in the non-secure memory, the MMU determines the physical address corresponding to the intermediate address according to the second page table pointed to by the third base address register on the TEE side.
  • the physical address mapped by the second-layer memory address may fall into the secure memory or in the non-secure memory.
  • the intermediate address needs to be obtained.
  • the NS bit in the page table entry If the NS bit is the first value, it is considered that the processor currently needs to obtain the data of the non-secure memory, such as the data of the target VM. In this way, the physical address mapped through the second-layer memory address will fall into the non-secure memory. Therefore, the MMU The physical address corresponding to the intermediate address is determined according to the second page table pointed to by the third base address register on the TEE side.
  • the MMU will determine the physical address corresponding to the intermediate address according to the third page table pointed to by the fourth base address register on the TEE side.
  • the MMU will directly The second page table pointed to determines the physical address corresponding to the intermediate address without the need to determine by the NS bit in the page table entry where the intermediate address is located.
  • a device for acquiring memory data in a second aspect, has a function of implementing the behavior of the method for acquiring memory data in the first aspect.
  • the device for acquiring memory data includes at least one module, and the at least one module is configured to implement the method for acquiring memory data provided in the first aspect.
  • a computer device in a third aspect, includes a processor and a memory, and the memory is used for storing a program for executing the memory data acquisition method provided in the first aspect, and for implementing the first The data involved in the memory data acquisition method provided by the aspect.
  • the processor is configured to execute programs stored in the memory.
  • the computer device may also include a communication bus for establishing a connection between the processor and the memory.
  • a computer-readable storage medium is provided, and instructions are stored in the storage medium, and when the instructions are executed on a computer device, the computer device is made to execute the method for acquiring memory data according to the first aspect. step.
  • a computer program product containing instructions, which, when the instructions are executed on a computer device, cause the computer device to execute the steps of the method for acquiring memory data described in the first aspect above.
  • the second page table refers to a page table shared by the TEE side and the REE side and used to map intermediate addresses into physical addresses
  • the target SP on the TEE side can determine the physical address corresponding to the virtual address of the target VM according to the first page table and the second page table, and then can quickly, Efficiently obtain memory data of the target VM.
  • the VMI program running in the target SP will not occupy the page table of the target VM, that is, the page table entry in the first page table or the second page table will not be modified to point to the VMI program running in the target SP , so that there will be no monitoring blind spots.
  • the VMI program running in the target SP can be well hidden on the REE side, and the target VM cannot perceive the existence of the target SP.
  • FIG. 1 is a schematic diagram of a hardware architecture of an ARM processor provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of an architecture after virtualization is performed on a TEE side and a REE side according to an embodiment of the present application;
  • FIG. 3 is a schematic diagram of the architecture of a server scenario provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an intelligent terminal scenario provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a computer device provided by an embodiment of the present application.
  • FIG. 6 is a flowchart of a method for acquiring memory data provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a memory acquisition device provided by an embodiment of the present application.
  • TrustZone technology is currently the mainstream technology to solve the security of computer equipment.
  • the hardware resources of computer equipment can be divided into REE side and TEE side, and the physical memory of computer equipment can be divided into non-secure memory and secure memory.
  • Code and data on REE side are stored in non-secure memory
  • code on TEE side is stored in non-secure memory.
  • data is stored in secure memory, the security of the REE side is lower than that of the TEE side.
  • the user operating system works on the REE side
  • TrustZone as a hardware security feature, works on the TEE side.
  • the processor can work on the REE side or on the TEE side, and the processor can switch back and forth between the REE side and the TEE side.
  • the hardware resources such as registers, memory, cache, peripherals, etc.
  • the hardware resources such as registers, memory, cache, peripherals, etc.
  • the hardware resources on the TEE side are prohibited from being accessed. Once the processor tries to access these hardware resources, the system will crash directly.
  • the TrustZone address space contoller (TZASC) register and the TrustZone memory adapter (TZMA) register can be configured through the TrustZone technology to set the sensitive memory as safe memory and work on the REE side processing
  • the browser cannot access secure memory, but can access non-secure memory.
  • the processor can access both the hardware resources on the TEE side and the hardware resources on the REE side. For example, a processor working on the TEE side can access both secure memory and non-secure memory.
  • TrustZone can provide security protection for the operating system on the REE side as a trusted root.
  • non-secure memory does not mean that the data stored in it is malicious, but the security of the environment in which it is located is lower than that of secure memory. That is, non-secure memory is less secure than secure memory.
  • Figure 1 describes the hardware architecture of an ARM processor.
  • the left side is the architecture of the REE side, and through hardware virtualization, the REE side can create multiple VMs, and each VM runs a user operating system (not shown in FIG. 1 ).
  • the REE side includes not only user mode and kernel mode, but also HYP mode. These three modes correspond to different hardware resources on the REE side, and the permission levels of these three modes increase in turn, that is, Yes, the user mode has the lowest permission level, and the HYP mode has the highest permission level.
  • the VM runs in the user mode and the kernel mode on the REE side, that is, the user operating system runs in the user mode and the kernel mode on the REE side, and the hypervisor for virtualization management runs in the HYP mode.
  • the Hypervisor is also known as a virtual machine monitor (VMM). Since HYP mode is a mode with the highest privilege level on the REE side, when the processor works in HYP mode, it can access all hardware resources in user mode, kernel mode and HYP mode. But when the processor runs in user mode or kernel mode, it cannot access HYP mode hardware resources. Therefore, the hypervisor has higher privileges than the operating system.
  • the processor can also switch between the kernel mode and the HYP mode, that is, executing the hypervisor call (HVC) instruction in the kernel mode on the REE side can enter the HYP mode, and execute the ERET instruction in the HYP mode. will return to kernel mode.
  • HVC hypervisor call
  • the TEE side on the right also includes user mode and kernel mode, but initially the TEE side does not support hardware virtualization, so the TEE side does not include HYP mode, and the TEE side only runs one operating system.
  • the TEE side also includes a special mode, that is, the monitoring mode.
  • the TEE side also includes three modes, namely user mode, kernel mode and monitoring mode. These three modes correspond to different hardware resources on the TEE side, and The user mode has the lowest permission level, and the monitor mode has the highest permission level. At the same time, the monitor mode is also a mode with the highest authority level of the entire processor.
  • the Hypervisor-related control registers can be configured to initialize and activate the Hypervisor in monitor mode.
  • the monitoring mode is also a portal for the REE side to enter the TEE side.
  • executing the secure monitor call (SMC) instruction can switch from the REE side to the monitoring mode of the TEE side.
  • Execute the return (ERET) instruction in the monitor mode on the TEE side and the processor decides whether to return to the REE side or continue by checking the non-secure (non-secure, NS) bit of the secure control register (SCR) in monitor mode.
  • the NS bit is 1, the processor returns to the kernel mode on the REE side, and when the NS bit is 0, the processor returns to the kernel mode on the TEE side.
  • ARM introduced the memory virtualization technology of the second layer of memory address mapping.
  • the common one-layer memory address mapping from virtual addresses to physical addresses is transformed into two-layer memory address mappings from virtual addresses to intermediate addresses, and then from intermediate addresses to physical addresses.
  • the process of the second-layer memory address mapping is completely controlled by the hypervisor, which is transparent to the operating system. From the perspective of the operating system, the intermediate address is the physical address corresponding to the virtual address. Therefore, by setting the attributes of the control bits of the page table entries of the second-level address mapping, the hypervisor can perform access control on the memory access of the operating system.
  • the page table entry contains three control bits: read, write, and execute.
  • the read and write control bits are related to the data protection of the memory
  • the execution control bits are related to the execution of the memory code.
  • TEE side uses an operating system, which is the operating system of each major manufacturer, and the TEE operating system is fragmented. phenomenon is becoming more and more serious.
  • a single TEE operating system on the TEE side to support multiple VMs on the REE side also brings stability and robustness issues.
  • the embodiments of the present application introduce a new processor working mode, SEL2, to support the hardware virtualization technology on the TEE side.
  • SEL2 new processor working mode
  • the TEE side can construct a virtualized environment similar to the REE side, that is, the TEE side creates multiple SPs, and each SP can run a TEE operating system.
  • TEE operating system architectures can solve the two problems of TEE operating system fragmentation and supporting multiple VMs on the REE side. That is, as shown in FIG. 2 , the REE side includes multiple VMs, each VM runs a user operating system, and the virtual machine monitor is used to manage the multiple VMs. The REE side can also install an application (application, APP) for the user to use. Similarly, the TEE side includes multiple SPs, each SP runs a TEE operating system, and the SP manager is used to manage the multiple SPs.
  • application application
  • the design of the first-layer memory address mapping on the TEE side and the REE side is the same, but the design of the second-layer memory address mapping on the TEE side and the REE side is slightly different. That is, the TEE side includes two base address registers for performing the second-layer memory address mapping, namely vttbr_el2 and vsttbr_el2, while the REE side has only one base address register for performing the second-layer memory address mapping, namely vttbr_el2.
  • the physical address mapped by the page table pointed to by vttbr_el2 will fall on the non-secure memory
  • the physical address mapped by the page table pointed by vsttbr_el2 will fall on the secure memory. That is, through vttbr_el2 and vsttbr_el2, the processor can access both secure memory and non-secure memory when working on the TEE side.
  • the embodiments of the present application can run VMI programs on multiple SPs created on the TEE side. Through the design of the VMI program and the second-layer memory address mapping, the memory data of the VM can be obtained. , so as to monitor the VM and prevent the VM from being maliciously attacked.
  • the subsequent description please refer to the subsequent description, which will not be further elaborated here.
  • the method provided by the embodiment of the present application can be applied to a server scenario, and can also be applied to an intelligent terminal scenario.
  • both the REE side and the TEE side support hardware virtualization features.
  • Multiple VMs are created on the REE side, and each VM runs a user operating system and a client application (client applicationCA).
  • a hypervisor is used to manage the multiple VMs.
  • An APP can also be installed on the REE side for users to use.
  • multiple SPs are created on the TEE side, each SP runs a TEE operating system and a trusted application (TA), and an APP can also be installed in the SP, such as an APP for intrusion detection,
  • the SP manager is used to manage the plurality of SPs.
  • an SP will be started on the TEE side accordingly, and the TEE operating system will run in the SP to support security services in the VM.
  • the TEE operating system can also monitor the operating system in the VM to detect whether the operating system in the VM has been maliciously attacked and improve the security of the operating system in the VM.
  • the CA refers to the client that can call the application program on the TEE side, and the CA runs on the REE side.
  • TA refers to a trusted application running on the TEE side.
  • the CA in the VM can call the TA in the SP to implement certain functions. This aspect is rarely involved in the embodiments of the present application, so the embodiments of the present application do not introduce this aspect too much.
  • FIG. 5 is a schematic structural diagram of a computer device according to an embodiment of the present application, where the computer device is a server or an intelligent terminal.
  • the computer device includes at least one processor 501 , a communication bus 502 , memory 503 and at least one communication interface 504 .
  • the processor 501 is a general-purpose central processing unit (CPU), a network processor (NP), a microprocessor, or one or more integrated circuits for implementing the solution of the present application, for example, a dedicated Integrated circuit (application-specific integrated circuit, ASIC), programmable logic device (programmable logic device, PLD) or a combination thereof.
  • the above-mentioned PLD is a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a general array logic (generic array logic, GAL) or any combination thereof.
  • the communication bus 502 is used to transfer information between the aforementioned components.
  • the communication bus 502 is divided into an address bus, a data bus, a control bus, and the like. For ease of presentation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.
  • the memory 503 is a read-only memory (ROM), a random access memory (RAM), an electrically erasable programmable read-only memory (EEPROM), an optical disk (including Compact disc read-only memory (CD-ROM), compact disc, laser disc, digital versatile disc, Blu-ray disc, etc.), magnetic disk storage medium or other magnetic storage device, or capable of carrying or storing instructions or any other medium in the form of a desired program code in a data structure and which can be accessed by a computer, but is not limited thereto.
  • the memory 503 can exist independently and is connected to the processor 501 through the communication bus 502 .
  • the memory 503 can also be integrated with the processor 501 .
  • the Communication interface 504 uses any transceiver-like device for communicating with other devices or a communication network.
  • the communication interface 504 includes a wired communication interface and can also include a wireless communication interface.
  • the wired communication interface is, for example, an Ethernet interface.
  • the Ethernet interface is an optical interface, an electrical interface, or a combination thereof.
  • the wireless communication interface is a wireless local area network (wireless local area network, WLAN) interface, a cellular network communication interface, or a combination thereof.
  • the processor 501 includes one or more CPUs, such as CPU0 and CPU1 as shown in FIG. 5 .
  • the computer device can include multiple processors, such as processor 501 and processor 505 as shown in FIG. 5 .
  • processors such as processor 501 and processor 505 as shown in FIG. 5 .
  • Each of these processors is a single-core processor, or a multi-core processor.
  • a processor herein refers to one or more devices, circuits, and/or processing cores for processing data (eg, computer program instructions).
  • the computer device can further include an output device 506 and an input device 507 .
  • Output device 506 communicates with processor 501 to display information in a variety of ways.
  • the output device 506 is a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, a projector, or the like.
  • Input device 507 communicates with processor 501 to receive user input in a variety of ways.
  • the input device 507 is a mouse, a keyboard, a touch screen device, a sensor device, or the like.
  • the memory 503 is used to store the program code 510 for executing the solutions of the present application, and the processor 501 can execute the program code 510 stored in the memory 503 .
  • the program code 510 includes one or more software modules, and the computer device can implement the memory data acquisition method provided by the embodiment of FIG. 6 below through the processor 501 and the program code 510 in the memory 503 .
  • FIG. 6 is a flowchart of a method for acquiring memory data provided by an embodiment of the present application, and the method is applied to a computer device.
  • the hardware resources of the computer device are divided into a REE side and a TEE side.
  • the REE side includes one or more VMs
  • the TEE side includes one or more SPs
  • the TEE side is deployed with a VMI program.
  • the VMI program is run on the SP on the TEE side to obtain memory data of the VM on the REE side, so as to monitor the VM and prevent the VM from being maliciously attacked.
  • the method includes the following steps.
  • Step 601 The processor shares the first page table on the REE side for address mapping with the TEE side, where the first page table refers to a page table for mapping virtual addresses to intermediate addresses.
  • the memory virtualization technology of the second-layer memory address mapping is introduced. That is to say, when accessing memory data, two layers of memory address mapping are required.
  • the first layer of memory address mapping refers to mapping virtual addresses to intermediate addresses
  • the second layer of memory address mapping refers to mapping intermediate addresses to physical addresses.
  • the first page table in this embodiment of the present application refers to a page table on the REE side that maps virtual addresses to intermediate addresses, that is, the first page table is a page used to implement the first-layer memory address mapping on the REE side surface.
  • the target SP on the TEE side needs to obtain the memory data of the target VM
  • the first page table needs to be shared with the TEE side.
  • the target VM refers to any one of the one or more VMs on the REE side
  • the target SP refers to the SP used to obtain memory data of the target VM in the one or more SPs on the TEE side.
  • the VM on the REE side can run in user mode and kernel mode
  • the TEE side also includes user mode and kernel mode
  • the SP on the TEE side can also run in user mode and kernel mode. Therefore, REE
  • the running space on the side includes user space and kernel space
  • the running space on the TEE side also includes user space and kernel space.
  • the VM on the REE side runs in the user space or kernel space on the REE side
  • the SP on the TEE side runs in the user space on the TEE side. or kernel space.
  • the memory data of the VM includes the data of the VM in the user space and the data in the kernel space. That is to say, the memory data of the VM is divided into user space and kernel space.
  • both the REE side and the TEE side also include a first base address register and a second base address register, and the first base address register is the base address corresponding to the user space.
  • the second base register is the base register corresponding to the kernel space. That is to say, the first base register points to a page table in user space for mapping from virtual addresses to intermediate addresses, and the second base register points to a page table in kernel space for mapping from virtual addresses to intermediate addresses.
  • the processor shares the page table pointed to by the first base address register on the REE side as the first page table with the first base address register on the TEE side.
  • the processor shares the page table pointed to by the second base address register on the REE side to the second base address register on the TEE side as the first page table.
  • the processor can work on the REE side or the TEE side, and the processor can switch back and forth between the REE side and the TEE side.
  • the processor works on the REE side
  • the hardware resources on the TEE side are prohibited from being accessed.
  • the processor can access both the hardware resources on the TEE side and the hardware resources on the REE side.
  • the memory data of the target VM on the REE side is obtained through the target SP on the TEE side. Therefore, in the embodiment of the present application, the processor works on the TEE side.
  • the processor can access the first base address register and the second base address register on the REE side, so as to determine the page table pointed to by the first base address register and the page table pointed to by the second base address register, and then to obtain
  • the page table pointed to by the first base address register is shared with the TEE side as the first page table.
  • the The page table pointed to by the two base address registers is shared with the TEE side as the first page table.
  • the base address register is used to store the memory entry address, so as to point to the data corresponding to the memory entry address. Therefore, the implementation process of the processor sharing the page table pointed to by the first base address register on the REE side to the first base address register on the TEE side as the first page table includes: The address is modified to the page table entry address stored in the first base address register on the REE side, so as to share the page table pointed to by the first base address register on the REE side as the first page table to the first base address register on the TEE side.
  • the implementation process of the processor sharing the page table pointed to by the second base address register on the REE side as the first page table to the second base address register on the TEE side includes: storing the second base address register on the TEE side.
  • the address of the REE side is modified to the page table entry address stored in the second base address register on the REE side, so as to share the page table pointed to by the second base address register on the REE side as the first page table to the second base address register on the TEE side .
  • Step 602 The processor runs the VMI program in the target SP.
  • the VMI program is deployed in both the user space and the kernel space on the TEE side.
  • the processor shares the page table pointed to by the first base address register on the REE side as the first page table to the first base address register on the TEE side, It is also necessary to point the second base address register on the TEE side to the VMI program deployed in the kernel space of the TEE side, and run the VMI program pointed to by the second base address register in the target SP with kernel mode authority.
  • the processor shares the page table pointed to by the second base address register on the REE side as the first page table with the second base address register on the TEE side, it is also necessary to Point the first base address register on the TEE side to the VMI program deployed in the user space on the TEE side, and run the VMI program pointed to by the first base address register in the target SP with the kernel mode authority.
  • the TEE side includes a user mode and a kernel mode, and the processor can work in the user mode or in the kernel mode.
  • the second base address register on the TEE side The address register points to the VMI program deployed in the kernel space of the TEE side, so that the processor runs the VMI program deployed in the kernel space of the TEE side in the target SP, thereby realizing the isolation of the target SP and the target VM.
  • the The first base address register points to the VMI program deployed in the user space of the TEE side, so that the processor runs the VMI program deployed in the user space of the TEE side in the target SP, thereby realizing the isolation of the target SP and the target VM.
  • an implementation process for the processor to point the second base address register on the TEE side to the VMI program deployed in the kernel space on the TEE side includes: modifying the address stored in the second base address register on the TEE side to be in the kernel space on the TEE side The entry address of the deployed VMI program, so that the second base address register on the TEE side points to the VMI program deployed in the kernel space of the TEE side.
  • the implementation process of the processor pointing the first base address register of the TEE side to the VMI program deployed in the user space of the TEE side includes: modifying the address stored in the first base address register of the TEE side to the user space of the TEE side.
  • the memory data to be acquired may be the data of the target VM in the user space, or may be the data of the target VM in the kernel space.
  • the second base address register on the TEE side will point to the VMI program deployed in the kernel space of the TEE side. Since the code and data of the VMI program are located in the kernel space, the memory data to be acquired is located in the user space, and the permission level of the kernel mode is higher than that of the user mode, the processor in the kernel mode can access the hardware resources of the user space.
  • the processor runs the VMI program located in the kernel space in the target SP with the kernel mode authority, so that the memory data in the user space can be successfully read. That is, the VMI program pointed to by the second base address register is run in the target SP with the kernel mode authority, thereby successfully reading the memory data in the user space.
  • the memory data to be acquired is the data of the target VM in the kernel space
  • the first base address register on the TEE side will point to the VMI program deployed in the user space of the TEE side. Since the code and data of the VMI program are located in the user space, the memory data to be acquired is located in the kernel space, and the permission level of the kernel mode is higher than that of the user mode. , so that if the memory data of the kernel space is obtained, an error will occur during the permission check. Therefore, in the embodiment of the present application, when the processor runs the VMI program in the target SP, it needs to run the VMI program in the target SP with the kernel state permission. The VMI program of the space can successfully read the memory data of the kernel space. That is, running the VMI program pointed to by the first base address register in the target SP with the kernel state authority can successfully read the memory data in the kernel space, thus solving the problem that the VMI program in the user space cannot read the data in the kernel space. .
  • the VMI program needs to access the memory data required by itself during the running process, but the VMI program is located on the TEE side, the memory data required by the VMI program will also be stored in the secure memory, and the memory data of the target VM.
  • the TEE side further includes a fourth base address register (such as the above vsttbr_el2), the fourth base address register points to the third page table, and the third page table refers to the The page table where the VMI program runs normally and performs intermediate address-to-physical address mapping.
  • the processor can run the VMI program in the target SP according to the third page table pointed to by the fourth base address register, thereby ensuring that the VMI program can access the memory data required by itself in the secure memory during the running process. At the same time, it can better isolate the running of the VMI program from the target VM.
  • Step 603 The processor obtains the memory data of the target VM through the VMI program running in the target SP according to the target virtual address, the first page table and the second page table.
  • the second page table is shared by the TEE side and the REE side and used for The page table that maps the intermediate addresses to physical addresses, and the target virtual address refers to the virtual address corresponding to the memory data to be acquired.
  • the first page table is the page table used for the first layer of memory address mapping
  • the second page table is the page table that maps the intermediate addresses to physical addresses.
  • the second page table is the page table used for the second-layer memory address mapping. Therefore, after the first page table is shared with the TEE side, the second page table needs to be shared with the TEE side.
  • the target VM can run in user space or kernel space, and the data of the target VM is divided into user space and kernel space.
  • the second-layer memory address mapping is divided into the mapping of secure memory and non-secure memory.
  • the physical address mapped through the second page table falls in the non-secure memory
  • the physical address mapped through the third page table falls in the secure memory . That is to say, the second-layer memory address mapping is divided into the mapping of secure memory and non-secure memory, there is no distinction between user space and kernel space, and the data of the target VM is stored in the non-secure memory. Therefore, in the embodiments of the present application , the TEE side and the REE side can always share the second page table, and do not need to share in the process of acquiring the data of the target VM.
  • both the REE side and the REE side also include a third base address register (such as vttbr_el2 above), and the third base address register on the REE side and the third base address register on the TEE side both point to the second page table.
  • a third base address register such as vttbr_el2 above
  • the realization process that the processor obtains the memory data of the target VM through the VMI program running in the target SP according to the target virtual address, the first page table and the second page table includes: in the process of the processor running the VMI program in the target SP , the MMU determines the intermediate address corresponding to the target virtual address according to the first page table, and determines the physical address corresponding to the intermediate address according to the second page table pointed to by the third base address register on the TEE side.
  • the processor obtains the memory data corresponding to the physical address through the VMI program running in the target SP.
  • the processor is addressed by the virtual address, but the memory data is stored in the memory based on the physical address. Therefore, after the processor obtains the target virtual address, the target virtual address can be mapped through the MMU, thereby The corresponding physical address is determined, and then the processor obtains the corresponding memory data according to the physical address.
  • the implementation process of determining the physical address corresponding to the intermediate address by the MMU according to the second page table pointed to by the third base address register on the TEE side includes: when the page table entry where the intermediate address is located is stored in the secure memory, using the MMU Get the NS bit in the page table entry where the intermediate address is located. If the NS bit is the first value, the MMU determines the physical address corresponding to the intermediate address according to the second page table pointed to by the third base address register on the TEE side. When the page table entry where the intermediate address is located is stored in the non-secure memory, the MMU determines the physical address corresponding to the intermediate address according to the second page table pointed to by the third base address register on the TEE side.
  • the memory data of the target VM will be stored in the non-secure memory, but the VMI program may also need to access the memory data it needs during the running process, and these memory data are stored in the secure memory. Therefore, the processor obtains When storing data, secure memory may be accessed, or non-secure memory may be accessed, or the physical address mapped through the second-level memory address may fall to secure memory or non-secure memory.
  • the process of memory address mapping is done automatically by the MMU without any software participation. Therefore, for the MMU, the MMU does not know whether the processor currently needs to access the secure memory or the non-secure memory. Therefore, the MMU determines the intermediate address.
  • mapping table After that, based on whether the page table entry where the intermediate address is located is stored in secure memory or non-secure memory, it is necessary to determine whether to use the second page table to map the second-layer memory address or to use the third page table to map the second-layer memory address. mapping table.
  • the physical address mapped by the second-layer memory address may fall into the secure memory or in the non-secure memory.
  • the intermediate address needs to be obtained.
  • the NS bit in the page table entry If the NS bit is the first value, it is considered that the processor currently needs to obtain the data of the non-secure memory, such as the data of the target VM. In this way, the physical address mapped through the second-layer memory address will fall into the non-secure memory. Therefore, the MMU The physical address corresponding to the intermediate address is determined according to the second page table pointed to by the third base address register on the TEE side.
  • the MMU will determine the physical address corresponding to the intermediate address according to the third page table pointed to by the fourth base address register on the TEE side.
  • the MMU will directly The second page table pointed to determines the physical address corresponding to the intermediate address without the need to determine by the NS bit in the page table entry where the intermediate address is located.
  • the first numerical value and the second numerical value are set in advance and can be adjusted as required.
  • the first value is 1 and the second value is 0. That is to say, when the NS bit in the page table entry where the intermediate address is located is 1, the MMU will determine the physical address corresponding to the intermediate address according to the second page table pointed to by the third base address register on the TEE side. When the NS bit in the page table entry where the intermediate address is located is 0, the MMU determines the physical address corresponding to the intermediate address according to the third page table pointed to by the fourth base address register on the TEE side.
  • the MMU can also determine whether the relationship between the mapped physical address and the corresponding memory attribute matches, so as to determine the memory address. Whether an error occurred during the mapping process. That is, after the MMU determines the physical address corresponding to the intermediate address according to the second page table pointed to by the third base address register on the TEE side, the MMU determines whether the physical address is located in the non-secure memory, and if the physical address is located in the non-secure memory , then it is determined that there is no error in the process of memory address mapping, otherwise, it is determined that there is an error in the process of memory address mapping.
  • the MMU determines whether the physical address is located in the secure memory, and if the physical address is located in the secure memory , then it is determined that there is no error in the process of memory address mapping, otherwise, it is determined that there is an error in the process of memory address mapping.
  • the accuracy of memory address mapping can be further improved through subsequent detection.
  • the page table includes multi-level page table entries, the page table entries are used to indicate the mapping relationship of memory addresses, and the page table entries will include control bits, such as NS bits.
  • This embodiment of the present application does not introduce too much about the specific implementation process of memory address mapping through the page table.
  • relevant analysis tools can also be deployed in the VMI program, so that after the target SP obtains the memory data of the target VM, it can perform relevant analysis on the memory data of the target VM, especially for the target VM that is vulnerable to malicious attacks. Kernel integrity protection, etc., to achieve real-time analysis of the process granularity in the target VM, better protect the target VM, and avoid malicious attacks on the target VM.
  • the second page table refers to a page table shared by the TEE side and the REE side and used to map intermediate addresses into physical addresses
  • the target SP on the TEE side can determine the physical address corresponding to the virtual address of the target VM according to the first page table and the second page table, and then can quickly, Efficiently obtain memory data of the target VM.
  • the VMI program running in the target SP will not occupy the page table of the target VM, that is, the page table entry in the first page table or the second page table will not be modified to point to the VMI program running in the target SP , so that there will be no monitoring blind spots.
  • the VMI program running in the target SP can be well hidden on the REE side, and the target VM cannot perceive the existence of the target SP.
  • the virtual address can usually provide some semantic information
  • the VMI program in the target SP obtains the target virtual address, it can know the semantic information carried by the target virtual address, and can directly The address reads the memory data of the target VM, which solves the problem of semantic gap and can more effectively detect whether the target VM is maliciously attacked.
  • the normal operation of the VMI program in the target SP is to map the memory address through the non-shared third page table, which is completely isolated from the target VM, and the target SP is located on the TEE side, the target VM is located on the REE side, and the security of the target SP is high. For the target VM, in this way, the VMI program running in the target SP is not easily attacked by the REE side, which improves the concealment and security of the VMI program running in the target SP.
  • FIG. 7 is a schematic structural diagram of an apparatus for acquiring memory data provided by an embodiment of the present application.
  • the apparatus for acquiring memory data may be implemented as part or all of a computer device by software, hardware, or a combination of the two.
  • the hardware resources of the computer device are divided into a REE side and a TEE side.
  • the REE side includes one or more VMs
  • the TEE side includes one or more SPs
  • the TEE side is deployed with a VMI program.
  • the apparatus includes: a page table sharing module 701 , a program running module 702 and a data acquiring module 703 .
  • the page table sharing module 701 is configured to share the first page table for address mapping on the REE side to the TEE side, where the first page table refers to a page table for mapping virtual addresses to intermediate addresses.
  • the first page table refers to a page table for mapping virtual addresses to intermediate addresses.
  • the program running module 702 is used for running the VMI program in the target SP, the target SP refers to the SP used to obtain the memory data of the target VM in one or more SPs, and the target VM refers to any one of the one or more VMs .
  • the target SP refers to the SP used to obtain the memory data of the target VM in one or more SPs
  • the target VM refers to any one of the one or more VMs .
  • step 602 in the above-mentioned embodiment shown in FIG. 6 , which will not be repeated here.
  • the data acquisition module 703 is used to acquire the memory data of the target VM through the VMI program running in the target SP according to the target virtual address, the first page table and the second page table, and the second page table refers to the TEE side and the REE side shared and A page table used to map intermediate addresses into physical addresses, and the target virtual address refers to the virtual address corresponding to the memory data to be acquired.
  • the target virtual address refers to the virtual address corresponding to the memory data to be acquired.
  • both the REE side and the TEE side further include a first base address register and a second base address register, the first base address register is the base address register corresponding to the user space, and the second base address register is the base address corresponding to the kernel space. register;
  • the page table sharing module 701 is specifically used for:
  • the page table pointed to by the first base address register on the REE side is shared with the first base address register on the TEE side as the first page table.
  • a VMI program is deployed in both the user space and the kernel space on the TEE side;
  • the program running module 702 is specifically used for:
  • both the REE side and the TEE side further include a first base address register and a second base address register, the first base address register is the base address register corresponding to the user space, and the second base address register is the base address corresponding to the kernel space. register;
  • the page table sharing module 701 is specifically used for:
  • the page table pointed to by the second base address register on the REE side is shared with the second base address register on the TEE side as the first page table.
  • a VMI program is deployed in both the user space and the kernel space on the TEE side;
  • the program running module 702 is specifically used for:
  • both the REE side and the TEE side further include a third base address register, and the third base address register on the REE side and the third base address register on the TEE side both point to the second page table;
  • the data acquisition module 703 includes:
  • the address mapping unit is used to determine the intermediate address corresponding to the target virtual address according to the first page table through the memory management unit MMU during the process of running the VMI program in the target SP, and the third base address pointed to by the third base address register on the TEE side.
  • the two-page table determines the physical address corresponding to the intermediate address;
  • the data acquisition unit is used for acquiring the memory data corresponding to the physical address through the VMI program running in the target SP.
  • the address mapping unit is specifically used for:
  • the MMU determines the physical address corresponding to the intermediate address according to the second page table pointed to by the third base address register on the TEE side.
  • the address mapping unit is specifically used for:
  • the MMU determines the physical address corresponding to the intermediate address according to the second page table pointed to by the third base address register on the TEE side.
  • the TEE side also includes a fourth base address register, the fourth base address register points to the third page table, and the third page table refers to the page table for the VMI program to run normally and perform intermediate address to physical address mapping;
  • the program running module 702 is specifically used for:
  • the VMI program is run in the target SP.
  • the second page table refers to a page table shared by the TEE side and the REE side and used to map intermediate addresses into physical addresses
  • the target SP on the TEE side can determine the physical address corresponding to the virtual address of the target VM according to the first page table and the second page table, and then can quickly, Efficiently obtain the memory data of the target VM.
  • the VMI program running in the target SP will not occupy the page table of the target VM, that is, the page table entry in the first page table or the second page table will not be modified to point to the VMI program running in the target SP , so that there will be no monitoring blind spots.
  • the VMI program running in the target SP can be well hidden on the REE side, and the target VM cannot perceive the existence of the target SP.
  • the virtual address can usually provide some semantic information
  • the VMI program in the target SP obtains the target virtual address, it can know the semantic information carried by the target virtual address, and can directly The address reads the memory data of the target VM, which solves the problem of semantic gap and can more effectively detect whether the target VM is maliciously attacked.
  • the normal operation of the VMI program in the target SP is to map the memory address through the non-shared third page table, which is completely isolated from the target VM, and the target SP is located on the TEE side, the target VM is located on the REE side, and the security of the target SP is high. For the target VM, in this way, the VMI program running in the target SP is not easily attacked by the REE side, which improves the concealment and security of the VMI program running in the target SP.
  • the memory data acquisition device when the memory data acquisition device provided by the above embodiment acquires memory data, only the division of the above functional modules is used as an example for illustration. In practical applications, the above functions can be allocated to different functional modules as required. , that is, dividing the internal structure of the device into different functional modules to complete all or part of the functions described above.
  • the device for acquiring memory data provided in the above embodiment and the method for acquiring memory data belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general purpose computer, special purpose computer, computer network or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server or data center Transmission to another website site, computer, server, or data center by wire (eg, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server, a data center, etc. that includes one or more available media integrated.
  • the available media are magnetic media (eg: floppy disk, hard disk, magnetic tape), optical media (eg: digital versatile disc (DVD)) or semiconductor media (eg: solid state disk (SSD)), etc.
  • the computer-readable storage medium mentioned in the embodiments of the present application may be a non-volatile storage medium, in other words, may be a non-transitory storage medium.
  • references herein to "a plurality” means two or more.
  • “/” means or means, for example, A/B can mean A or B;
  • "and/or” in this document is only an association that describes an associated object Relation, it means that there can be three kinds of relations, for example, A and/or B can mean that A exists alone, A and B exist at the same time, and B exists alone.
  • words such as “first” and “second” are used to distinguish the same or similar items with basically the same function and effect. Those skilled in the art can understand that the words “first”, “second” and the like do not limit the quantity and execution order, and the words “first”, “second” and the like are not necessarily different.

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Abstract

本申请公开了一种内存数据获取方法、装置及存储介质，属于虚拟化技术领域。计算机设备的硬件资源被划分为REE侧和TEE侧，处理器将REE侧进行地址映射的第一页表共享给TEE侧，在TEE侧的目标SP中运行VMI程序，根据目标虚拟地址、第一页表和第二页表，通过目标SP中运行的VMI程序获取REE侧的目标VM的内存数据，第一页表是指将虚拟地址映射为中间地址的页表，第二页表是指将中间地址映射为物理地址的页表。由于目标SP中运行的VMI程序在获取目标VM的内存数据的时候使用的是REE侧共享的页面，并没有占用目标VM的页表，因此不会存在监控盲点，同时目标VM无法感知目标SP的存在。

Description

内存数据获取方法、装置及存储介质
本申请要求于2021年04月26日提交的申请号为202110454402.9、发明名称为“内存数据获取方法、装置及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及虚拟化技术领域，特别涉及一种内存数据获取方法、装置及存储介质。
背景技术
计算机设备的硬件资源能够被划分为富执行环境(Rich Execution Environment，REE)侧和可信执行环境(Trusted Execution Environment，TEE)侧。REE侧包括多个虚拟机(Virtual Machine，VM)，VM用于处理用户相关数据，但是REE侧的安全性低于TEE侧，VM很容易被恶意攻击，导致用户数据的安全性较低。因此，需要获取VM的内存数据，以对VM进行监控，从而避免VM被恶意攻击。
虚拟机自省(virtual machine introspection，VMI)技术是业界关注的安全监控方案，也即是，通过VMI技术获取VM的内存数据，以对VM进行监控，能够避免VM被恶意攻击。相关技术提出了一种关于VMI技术进行内存数据获取的方法，该方法引入了沉浸式执行环境(Immersive Execution EnvironmentImEE)系统，且目标VM的扩展页表(Extended Page Table，EPT)所包括的一个或多个页表项被修改，被修改的页表项指向VMI程序。ImEE系统能够使用目标VM的虚拟地址，通过运行VMI程序，从EPT中直接确定对应的物理地址。这样，能够快速、高效地读取目标VM的内存数据，而且由于虚拟地址能够提供一些语义信息，所以ImEE系统能够有效地检测到目标VM是否被恶意攻击。
然而，由于VMI程序占用了EPT的一部分页表项，这些页表项被修改后所对应的数据为VMI程序的代码和数据，而不是目标VM的代码和数据，也即是，这些页表项原本所对应的目标VM的代码和数据并没有监控到，这样就会存在监控盲点。
发明内容
本申请实施例提供了一种内存数据获取方法、装置及存储介质等，能够一定程度上避免监控盲点的情况。下面通过多个方面介绍本申请，应理解的是，以下各方面的实现方式和有益效果可以相互参考。
第一方面，提供了一种内存数据获取方法，在该方法中，计算机设备的硬件资源被划分为REE侧和TEE侧，REE侧包括一个或多个VM，TEE侧包括一个或多个SP，TEE侧部署有VMI程序，该方法包括：处理器将REE侧进行地址映射的第一页表共享给TEE侧，第一页表是指将虚拟地址映射为中间地址的页表。处理器在目标SP中运行VMI程序，目标SP是指一个或多个SP中用于获取目标VM的内存数据的SP，目标VM是指一个或多个VM中 的任一VM。处理器根据目标虚拟地址、第一页表和第二页表，通过目标SP中运行的VMI程序获取目标VM的内存数据，第二页表是指TEE侧和REE侧共享且用于将中间地址映射为物理地址的页表，目标虚拟地址是指待获取的内存数据对应的虚拟地址。
第一页表是指将虚拟地址映射为中间地址的页表，第二页表是指TEE侧和REE侧共享且用于将中间地址映射为物理地址的页表，因此，在REE侧和TEE侧共享第一页表和第二页表之后，TEE侧的目标SP能够根据第一页表和第二页表确定目标VM的虚拟地址对应的物理地址，进而能够快速、高效地获取目标VM的内存数据。而且，目标SP中运行的VMI程序不会占用目标VM的页表，也即是，第一页表或者第二页表中的页表项并不会被修改为指向目标SP中运行的VMI程序，这样就不会存在监控盲点，同时，目标SP中运行的VMI程序在REE侧还能够很好地进行隐藏，目标VM无法感知目标SP的存在。
为了对目标VM进行更好地监控，REE侧的目标SP不仅要获取目标VM在用户空间的数据，还需要获取目标VM在内核空间的数据。为了能够获取到目标VM在用户空间的数据以及在内核空间的数据，REE侧和TEE侧均还包括第一基址寄存器和第二基址寄存器，第一基址寄存器为用户空间对应的基址寄存器，第二基址寄存器为内核空间对应的基址寄存器。也就是说，第一基址寄存器指向用户空间中进行虚拟地址到中间地址映射的页表，第二基址寄存器指向内核空间中进行虚拟地址到中间地址映射的页表。这样，在待获取的内存数据为用户空间的数据的情况下，处理器将REE侧的第一基址寄存器所指向的页表作为第一页表共享给TEE侧的第一基址寄存器。在待获取的内存数据为内核空间的数据的情况下，处理器将REE侧的第二基址寄存器所指向的页表作为第一页表共享给TEE侧的第二基址寄存器。
由于处理器能够工作在REE侧，也能够工作在TEE侧，且处理器能够在REE侧和TEE侧来回切换。当处理器工作在REE侧时，TEE侧的硬件资源是被禁止访问的。但是当处理器工作在TEE侧时，处理器既能够访问TEE侧的硬件资源，又能够访问REE侧的硬件资源。而且本申请实施例是通过TEE侧的目标SP来获取REE侧的目标VM的内存数据，所以，在本申请实施例中处理器工作在TEE侧。这样，处理器就能够访问REE侧的第一基址寄存器和第二基址寄存器，从而确定第一基址寄存器所指向的页表以及第二基址寄存器所指向的页表，进而在待获取的内存数据为用户空间的数据的情况下，将第一基址寄存器所指向的页表作为第一页表共享给TEE侧，在待获取的内存数据为内核空间的数据的情况下，将第二基址寄存器所指向的页表作为第一页表共享给TEE侧。在其它一些实施例中，处理器也可以不经过前述两种“情况”的判断直接将第一基址寄存器和/或第二基址寄存器的页表共享给TEE侧。
其中，基址寄存器用于存储内存入口地址，从而指向该内存入口地址对应的数据(该数据在本实施例中指的是页表数据)。因此，处理器将REE侧的第一基址寄存器所指向的页表作为第一页表共享给TEE侧的第一基址寄存器的实现过程包括：将TEE侧的第一基址寄存器中存储的地址修改为REE侧的第一基址寄存器中存储的页表入口地址，以将REE侧的第一基址寄存器所指向的页表作为第一页表共享给TEE侧的第一基址寄存器。
同理，处理器将REE侧的第二基址寄存器所指向的页表作为第一页表共享给TEE侧的第二基址寄存器的实现过程包括：将TEE侧的第二基址寄存器中存储的地址修改为REE侧的第二基址寄存器中存储的页表入口地址，以将REE侧的第二基址寄存器所指向的页表作为第一页表共享给TEE侧的第二基址寄存器。
在本申请一些实施例中，TEE侧的用户空间和内核空间中均部署有VMI程序。这样，在待获取的内存数据为用户空间的数据的情况下，处理器将REE侧的第一基址寄存器所指向的页表作为第一页表共享给TEE侧的第一基址寄存器之后，还需要将TEE侧的第二基址寄存器指向TEE侧的内核空间中部署的VMI程序，并以内核态权限在目标SP中运行第二基址寄存器指向的VMI程序。在待获取的内存数据为内核空间的数据的情况下，处理器将REE侧的第二基址寄存器所指向的页表作为第一页表共享给TEE侧的第二基址寄存器之后，还需要将TEE侧的第一基址寄存器指向TEE侧的用户空间中部署的VMI程序，并以内核态权限在目标SP中运行第一基址寄存器指向的VMI程序。
由于TEE侧包括用户模式和内核模式，处理器能够工作在用户模式，也能够工作在内核模式。当获取目标VM在用户空间的数据时，在将REE侧的第一基址寄存器所指向的页表作为第一页表共享给TEE侧的第一基址寄存器之后，将TEE侧的第二基址寄存器指向TEE侧的内核空间中部署的VMI程序，从而使处理器在目标SP中运行TEE侧的内核空间中部署的VMI程序，实现了目标SP与目标VM的隔离。同理，当获取目标VM在内核空间的数据时，在将REE侧的第二基址寄存器所指向的页表作为第一页表共享给TEE侧的第二基址寄存器之后，将TEE侧的第一基址寄存器指向TEE侧的用户空间中部署的VMI程序，从而使处理器在目标SP中运行TEE侧的用户空间中部署的VMI程序，实现了目标SP与目标VM的隔离。
待获取的内存数据可能为目标VM在用户空间的数据，也可能为目标VM在内核空间的数据。为了实现目标SP与目标VM的隔离，当待获取的内存数据为目标VM在用户空间的数据时，TEE侧的第二基址寄存器会指向TEE侧的内核空间中部署的VMI程序。由于VMI程序的代码和数据位于内核空间，待获取的内存数据位于用户空间，而且内核模式的权限等级高于用户模式的权限等级，处于内核模式的处理器能够访问用户空间的硬件资源，因此，处理器以内核态权限在目标SP中运行位于内核空间的VMI程序，从而能够成功读取用户空间的内存数据。也即是，以内核态权限在目标SP中运行第二基址寄存器指向的VMI程序，从而成功读取用户空间的内存数据。
但是，当待获取的内存数据为目标VM在内核空间的数据时，TEE侧的第一基址寄存器会指向TEE侧的用户空间中部署的VMI程序。由于VMI程序的代码和数据位于用户空间，待获取的内存数据位于内核空间，而且内核模式的权限等级高于用户模式的权限等级，如果以用户态权限在目标SP中运行位于用户空间的VMI程序，从而获取内核空间的内存数据的话，就会在权限检查时出错，所以，在本申请实施例中，处理器在目标SP中运行VMI程序时，需要以内核态权限在目标SP中运行位于用户空间的VMI程序，从而能够成功读取内核空间的内存数据。也即是，以内核态权限在目标SP中运行第一基址寄存器指向的VMI程序，能够成功读取内核空间的内存数据，从而解决了用户空间的VMI程序无法读取内核空间的数据的问题。
需要说明的是，VMI程序在运行的过程中需要访问自身所需的内存数据，但是VMI程序位于TEE侧，VMI程序所需的内存数据也就会存储在安全内存中，而目标VM的内存数据存储在非安全内存中，所以，在本申请实施例中，TEE侧还包括第四基址寄存器(如上述的vsttbr_el2)，第四基址寄存器指向第三页表，第三页表是指供VMI程序正常运行而进行中间地址到物理地址映射的页表。这样，处理器能够根据第四基址寄存器所指向的第三页表，在 目标SP中运行VMI程序，从而保证VMI程序在运行的过程中能够在安全内存中访问自身所需的内存数据。同时也能够更好地将VMI程序的运行与目标VM进行隔离。
为了实现第二层内存地址映射，REE侧和REE侧均还包括第三基址寄存器，REE侧的第三基址寄存器和TEE侧的第三基址寄存器均指向第二页表。这样，处理器根据目标虚拟地址、第一页表和第二页表，通过目标SP中运行的VMI程序获取目标VM的内存数据的实现过程包括：处理器在目标SP中运行VMI程序的过程中，通过MMU根据第一页表确定目标虚拟地址对应的中间地址，以及根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址。处理器通过目标SP中运行的VMI程序获取物理地址对应的内存数据。
其中，通过MMU根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址的实现过程包括：在中间地址所在的页表项存储在安全内存的情况下，通过MMU获取中间地址所在页表项中的NS位。如果NS位为第一数值，则通过MMU根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址。在中间地址所在的页表项存储在非安全内存的情况下，通过MMU根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址。
在中间地址所在的页表项存储在安全内存的情况下，通过第二层内存地址映射出来的物理地址可能会落到安全内存，也可能会落到非安全内存，此时，需要获取中间地址所在页表项中的NS位。如果NS位为第一数值，那么认为处理器当前需要获取非安全内存的数据，比如目标VM的数据，这样，通过第二层内存地址映射出来的物理地址会落到非安全内存，因此，MMU会根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址。如果NS位为第二数值，那么认为处理器当前需要获取安全内存的数据，比如VMI程序正常运行时所需的自身的内存数据，这样，通过第二层内存地址映射出来的物理地址会落到安全内存，因此，MMU会根据TEE侧的第四基址寄存器所指向的第三页表确定中间地址对应的物理地址。
但是，在中间地址所在的页表项存储在非安全内存的情况下，认为处理器当前获取的内存数据必然为非安全内存的数据，因此，MMU会直接根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址，而无需通过中间地址所在页表项中的NS位来决定。
第二方面，提供了一种内存数据获取装置，所述内存数据获取装置具有实现上述第一方面中内存数据获取方法行为的功能。所述内存数据获取装置包括至少一个模块，该至少一个模块用于实现上述第一方面所提供的内存数据获取方法。
第三方面，提供了一种计算机设备，所述计算机设备包括处理器和存储器，所述存储器用于存储执行上述第一方面所提供的内存数据获取方法的程序，以及存储用于实现上述第一方面所提供的内存数据获取方法所涉及的数据。所述处理器被配置为用于执行所述存储器中存储的程序。所述计算机设备还可以包括通信总线，该通信总线用于该处理器与存储器之间建立连接。
第四方面，提供了一种计算机可读存储介质，所述存储介质内存储有指令，当所述指令在计算机设备上运行时，使得计算机设备执行上述第一方面所述的内存数据获取方法的步骤。
第五方面，提供了一种包含指令的计算机程序产品，当所述指令在计算机设备上运行时，使得计算机设备执行上述第一方面所述的内存数据获取方法的步骤。
上述第二方面、第三方面、第四方面和第五方面所获得的技术效果与第一方面中对应的技术手段获得的技术效果近似，在这里不再赘述。
在本申请实施例中，由于第一页表是指将虚拟地址映射为中间地址的页表，第二页表是指TEE侧和REE侧共享且用于将中间地址映射为物理地址的页表，在REE侧和TEE侧共享第一页表和第二页表之后，TEE侧的目标SP能够根据第一页表和第二页表确定目标VM的虚拟地址对应的物理地址，进而能够快速、高效地获取目标VM的内存数据。而且，目标SP中运行的VMI程序不会占用目标VM的页表，也即是，第一页表或者第二页表中的页表项并不会被修改为指向目标SP中运行的VMI程序，这样就不会存在监控盲点，同时，目标SP中运行的VMI程序在REE侧还能够很好地进行隐藏，目标VM无法感知目标SP的存在。
附图说明
图1是本申请实施例提供的一种ARM处理器的硬件架构示意图；
图2是本申请实施例提供的一种TEE侧和REE侧进行虚拟化后的架构示意图；
图3是本申请实施例提供的一种服务器场景的架构示意图；
图4是本申请实施例提供的一种智能终端场景的架构示意图；
图5是本申请实施例提供的一种计算机设备的结构示意图；
图6是本申请实施例提供的一种内存数据获取方法的流程图；
图7是本申请实施例提供的一种内存获取装置的结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
为了便于理解，在对本申请实施例提供的内存数据获取方法进行详细地解释说明之前，先对本申请实施例的实施背景进行介绍。
随着高级精简指令集设备(advanced RISC machines，ARM)处理器性能的不断提升，运行有ARM处理器的计算机设备给人们的生活带来了极大的便利。与此同时，计算机设备上也携带了越来越多的用户数据，用户也越来越重视计算机设备的安全性。
TrustZone技术是当前解决计算机设备安全性的主流技术。通过TrustZone技术能够将计算机设备的硬件资源划分为REE侧和TEE侧，且计算机设备的物理内存分为非安全内存和安全内存，REE侧的代码和数据存储在非安全内存中，TEE侧的代码和数据存储在安全内存中，REE侧的安全性低于TEE侧。用户操作系统工作在REE侧，TrustZone作为硬件安全特性，工作在TEE侧，处理器能够工作在REE侧，也能够工作在TEE侧，且处理器能够在REE侧和TEE侧来回切换。
当处理器工作在REE侧时，TEE侧的硬件资源(如寄存器、内存、缓存、外设等)是被禁止访问的，一旦处理器试图访问这些硬件资源，系统将会直接崩溃。例如，通过TrustZone技术能够配置TrustZone地址空间控制(TrustZone address space contoller，TZASC)寄存器和TrustZone存储适配(TrustZone memory adapter，TZMA)寄存器，以将敏感的内存设置为安全内存，工作在REE侧的处理器无法对安全内存进行访问，但是能够对非安全内存进行访问。当处理器工作在TEE侧时，处理器既能够访问TEE侧的硬件资源，又能够访问REE侧的硬 件资源。比如，工作在TEE侧的处理器既能够访问安全内存，又能够访问非安全内存。
正是由于拥有比REE侧的操作系统更高的权限，TrustZone能够作为可信根为REE侧的操作系统提供安全保护。其中，非安全内存并不是指其内存储的数据是恶意的，而是它所处环境的安全性低于安全内存。也即是，非安全内存的安全性低于安全内存。
图1描述了ARM处理器的硬件架构。其中，左侧是REE侧的架构，而且通过硬件虚拟化，REE侧能够创建多个VM，每个VM中运行有用户操作系统(图1中未示出)。而且，为了支持硬件虚拟化，REE侧不仅包括用户模式和内核模式，还包括HYP模式，这三个模式对应于REE侧不同的硬件资源，且这三个模式的权限等级依次升高，也即是，用户模式的权限等级最低，HYP模式的权限等级最高。VM运行在REE侧的用户模式和内核模式下，也即是，用户操作系统运行在REE侧的用户模式和内核模式下，用于进行虚拟化管理的管理程序(Hypervisor)运行在HYP模式下，其中Hypervisor又称为虚拟机监视器(virtual machine monitor，VMM)。由于HYP模式是REE侧权限等级最高的一个模式，当处理器工作在HYP模式下时，它能够访问用户模式、内核模式和HYP模式的所有硬件资源。但是当处理器运行在用户模式或者内核模式下时，它不能访问HYP模式的硬件资源。因此，Hypervisor拥有比操作系统更高的权限。另外，处理器还能够在内核模式和HYP模式之间切换，也即是，在REE侧的内核模式下执行管理程序调用(hypervisor call，HVC)指令能够进入HYP模式，在HYP模式下执行ERET指令将会返回内核模式。
与左侧的REE侧一样，右侧的TEE侧也包括用户模式和内核模式，但是最开始TEE侧不支持硬件虚拟化，所以TEE侧不包括HYP模式，而且TEE侧只运行有一个操作系统。但是，TEE侧还包括一个特殊的模式，即监控模式，这样，TEE侧也是包括三个模式，分别为用户模式、内核模式和监控模式，这三个模式对应于TEE侧不同的硬件资源，且用户模式的权限等级最低，监控模式的权限等级最高。同时，监控模式还是整个处理器权限等级最高的一个模式，当处理器工作在监控模式下时，它不仅能够访问TEE侧所有的硬件资源，还能够访问REE侧所有的硬件资源。通过TrustZone技术能够在监控模式下，配置Hypervisor相关的控制寄存器来初始化并激活Hypervisor。监控模式也是REE侧进入TEE侧的一个门户，在REE侧的内核模式或者HYP模式下，执行安全监控调用(secure monitor call，SMC)指令，能够从REE侧切换到TEE侧的监控模式。在TEE侧的监控模式下执行返回(ERET)指令，处理器通过检查监控模式下的安全控制寄存器(secure control register，SCR)的非安全(non-secure，NS)位来决定返回REE侧还是继续停留在TEE侧。当NS位为1时，处理器返回REE侧的内核模式，当NS位为0时，处理器返回TEE侧的内核模式。
为了支持内存虚拟化，ARM引入了第二层内存地址映射的内存虚拟化技术。利用该技术，常见的虚拟地址到物理地址的一层内存地址映射就转变为虚拟地址到中间地址,再从中间地址到物理地址的两层内存地址映射。其中第二层内存地址映射的过程是由Hypervisor完全控制的，对于操作系统来说是透明的，在操作系统看来，中间地址就是虚拟地址对应的物理地址。因此，通过设置第二层地址映射的页表项的控制位的属性，Hypervisor能够对操作系统的内存访问进行访问控制。页表项包含读、写、执行等三个控制位。其中读、写控制位和内存的数据保护相关，执行控制位和内存代码的执行相关。通过对读、写和执行控制位的配置，Hypervisor能够实现以页粒度监控物理内存的访问，保护相关敏感的信息。
然而，随着TrustZone技术的不断发展，各大厂商都纷纷采用自己的TEE操作系统，也 即是，TEE侧采用一个操作系统，该操作系统为各大厂商自己的操作系统，TEE操作系统碎片化的现象越来越严重。而且TEE侧单个TEE操作系统来支持REE侧的多个VM也会带来稳定性和鲁棒性的问题。为此，本申请实施例引入了SEL2这一新的处理器工作模式，支持TEE侧的硬件虚拟化技术。这样，TEE侧能够与REE侧类似地构建虚拟化环境，即TEE侧创建多个SP，每个SP中可运行一个TEE操作系统。多个TEE操作系统架构能够解决TEE操作系统碎片化和支持REE侧多个VM这两个问题。也即是，如图2所示，REE侧包括多个VM，每个VM中运行有一个用户操作系统，虚拟机监视器用于对该多个VM进行管理。REE侧还能够安装应用程序(application，APP)，供用户使用。类似地，TEE侧包括多个SP，每个SP中运行有一个TEE操作系统，SP管理器用于对该多个SP进行管理。
而且，在内存虚拟化的支持上，TEE侧和REE侧进行第一层内存地址映射的设计相同之外，TEE侧和REE侧进行第二层内存地址映射的设计略有不同。即，TEE侧用于进行第二层内存地址映射的基址寄存器包括两个，分别为vttbr_el2和vsttbr_el2，而REE侧仅仅只有一个进行第二层内存地址映射的基址寄存器，即vttbr_el2。其中，通过vttbr_el2指向的页表映射出来的物理地址会落在非安全内存上，通过vsttbr_el2指向的页表映射出来的物理地址会落在安全内存上。也即是，通过vttbr_el2和vsttbr_el2，处理器工作在TEE侧的时候既能访问安全内存，也能访问非安全内存。
由于VM中运行有用户操作系统，用于处理用户相关数据，且VM很容易被恶意攻击，从而导致用户数据的安全性较低。而且VMI技术是业界关注的安全监控方案，因此，本申请实施例能够在TEE侧创建的多个SP运行VMI程序，通过VMI程序以及第二层内存地址映射的设计，能够获取到VM的内存数据，从而对VM进行监控，避免VM被恶意攻击。详细实施内容参见后续描述，在此不再展开阐述。
本申请实施例提供的方法能够应用于服务器场景，也能够应用于智能终端场景。在服务器场景中，如图3所示，REE侧和TEE侧都支持硬件虚拟化特性，REE侧创建有多个VM，每个VM中运行有用户操作系统以及客户端应用程序(client applicationCA)，虚拟机监视器用于该多个VM进行管理。REE侧还能够安装APP，供用户使用。类似地，TEE侧创建有多个SP，每个SP中运行有一个TEE操作系统及可信应用程序(trusted application，TA)，而且SP中还能够安装APP，比如用于进行入侵检测的APP，SP管理器用于对该多个SP进行管理。为了提供TEE可信执行环境的支持，在某个VM启动时，会相应地在TEE侧启动一个SP，并在SP中运行TEE操作系统，来支持VM中的安全业务。
在智能终端场景中，如图4所示，虽然REE侧和TEE侧启动多个VM或者SP的需求并不强烈，但是当REE侧和TEE侧的内存虚拟化特性开启后，REE侧与用户关系紧密的操作系统(如Android操作系统)和TEE侧的TEE操作系统认为分别运行在VM和SP中。在这种场景下，TEE操作系统也能够监控VM中的操作系统，从而检测VM中的操作系统是否被恶意攻击，提升VM中操作系统的安全性。
其中，CA是指能够调用TEE侧的应用程序的客户端，且CA运行在REE侧。TA是指运行在TEE侧的可信应用程序。比如，在运行的过程中，VM中的CA能够调用SP中的TA来实现某些功能。本申请实施例关于这方面很少涉及，所以本申请实施例对此不做过多介绍。
请参考图5，图5是根据本申请实施例示出的一种计算机设备的结构示意图，该计算机设备为服务器或者智能终端。该计算机设备包括至少一个处理器501、通信总线502、存储器503以及至少一个通信接口504。
处理器501是一个通用中央处理器(central processing unit，CPU)、网络处理器(network processor，NP)、微处理器、或者是一个或多个用于实现本申请方案的集成电路，例如，专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD是复杂可编程逻辑器件(complex programmable logic device，CPLD)、现场可编程逻辑门阵列(field-programmable gate array，FPGA)、通用阵列逻辑(generic array logic，GAL)或其任意组合。
通信总线502用于在上述组件之间传送信息。通信总线502分为地址总线、数据总线、控制总线等。为便于表示，图中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
存储器503是只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、电可擦可编程只读存储器(electrically erasable programmable read-only Memory，EEPROM)、光盘(包括只读光盘(compact disc read-only memory，CD-ROM)、压缩光盘、激光盘、数字通用光盘、蓝光光盘等)、磁盘存储介质或者其它磁存储设备，或者是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其它介质，但不限于此。存储器503能够独立存在，并通过通信总线502与处理器501相连接。存储器503也能够和处理器501集成在一起。
通信接口504使用任何收发器一类的装置，用于与其它设备或通信网络通信。通信接口504包括有线通信接口，还能够包括无线通信接口。其中，有线通信接口例如为以太网接口。以太网接口是光接口、电接口或其组合。无线通信接口为无线局域网(wireless local area networks，WLAN)接口、蜂窝网络通信接口或其组合等。
在具体实现中，作为一种实施例，处理器501包括一个或多个CPU，如图5中所示的CPU0和CPU1。
在具体实现中，作为一种实施例，计算机设备能够包括多个处理器，如图5中所示的处理器501和处理器505。这些处理器中的每一个是一个单核处理器，或者是一个多核处理器。这里的处理器指一个或多个设备、电路、和/或用于处理数据(如计算机程序指令)的处理核。
在具体实现中，作为一种实施例，计算机设备还能够包括输出设备506和输入设备507。输出设备506和处理器501通信，以多种方式来显示信息。例如，输出设备506是液晶显示器(liquid crystal display，LCD)、发光二级管(light emitting diode，LED)显示设备、阴极射线管(cathode ray tube，CRT)显示设备或投影仪(projector)等。输入设备507和处理器501通信，以多种方式接收用户的输入。例如，输入设备507是鼠标、键盘、触摸屏设备或传感设备等。
在一些实施例中，存储器503用于存储执行本申请方案的程序代码510，处理器501能够执行存储器503中存储的程序代码510。该程序代码510中包括一个或多个软件模块，该计算机设备能够通过处理器501以及存储器503中的程序代码510，来实现下文图6实施例提供的内存数据获取方法。
接下来对本申请实施例提供的内存数据获取方法进行详细地解释说明。
图6是本申请实施例提供的一种内存数据获取方法的流程图，该方法应用于计算机设备中。该计算机设备的硬件资源被划分为REE侧和TEE侧，REE侧包括一个或多个VM，TEE侧包括一个或多个SP，TEE侧部署有VMI程序。本申请实施例是通过TEE侧的SP运行VMI程序，来获取REE侧的VM的内存数据，从而对VM进行监控，避免VM被恶意攻击。
请参考图6，该方法包括如下步骤。
步骤601：处理器将REE侧进行地址映射的第一页表共享给TEE侧，第一页表是指将虚拟地址映射为中间地址的页表。
基于前文描述，为了支持内存虚拟化，引入了第二层内存地址映射的内存虚拟化技术。也就是说，在访问内存数据时，需要进行两层内存地址的映射，第一层内存地址映射是指将虚拟地址映射为中间地址，第二层内存地址映射是指将中间地址映射为物理地址。由于本申请实施例中的第一页表是指REE侧将虚拟地址映射为中间地址的页表，也即是，第一页表是为了实现REE侧的第一层内存地址映射所使用的页表。因此，在TEE侧的目标SP需要获取目标VM的内存数据时，为了避免TEE侧占用目标VM的页表，需要将第一页表共享给TEE侧。其中，目标VM是指REE侧的一个或多个VM中的任一VM，目标SP是指TEE侧的一个或多个SP中用于获取目标VM的内存数据的SP。
由于REE侧包括用户模式和内核模式，REE侧的VM能够运行在用户模式和内核模式，TEE侧也包括用户模式和内核模式，TEE侧的SP也能够运行在用户模式和内核模式，因此，REE侧的运行空间包括用户空间和内核空间，TEE侧的运行空间也包括用户空间和内核空间，REE侧的VM运行在REE侧的用户空间或者内核空间，TEE侧的SP运行在TEE侧的用户空间或者内核空间。而且对于REE侧的VM来说，VM的内存数据包括VM在用户空间的数据以及在内核空间的数据。也就是说，VM的内存数据具有用户空间和内核空间之分。
在本申请实施例中，为了对目标VM进行更好地监控，REE侧的目标SP不仅要获取目标VM在用户空间的数据，还需要获取目标VM在内核空间的数据。为了能够获取到目标VM在用户空间的数据以及在内核空间的数据，REE侧和TEE侧均还包括第一基址寄存器和第二基址寄存器，第一基址寄存器为用户空间对应的基址寄存器，第二基址寄存器为内核空间对应的基址寄存器。也就是说，第一基址寄存器指向用户空间中进行虚拟地址到中间地址映射的页表，第二基址寄存器指向内核空间中进行虚拟地址到中间地址映射的页表。
这样，在待获取的内存数据为用户空间的数据的情况下，处理器将REE侧的第一基址寄存器所指向的页表作为第一页表共享给TEE侧的第一基址寄存器。在待获取的内存数据为内核空间的数据的情况下，处理器将REE侧的第二基址寄存器所指向的页表作为第一页表共享给TEE侧的第二基址寄存器。
基于前文描述，处理器能够工作在REE侧，也能够工作在TEE侧，且处理器能够在REE侧和TEE侧来回切换。当处理器工作在REE侧时，TEE侧的硬件资源是被禁止访问的。但是当处理器工作在TEE侧时，处理器既能够访问TEE侧的硬件资源，又能够访问REE侧的硬件资源。而且本申请实施例是通过TEE侧的目标SP来获取REE侧的目标VM的内存数据，所以，在本申请实施例中处理器工作在TEE侧。这样，处理器就能够访问REE侧的第一基址寄存器和第二基址寄存器，从而确定第一基址寄存器所指向的页表以及第二基址寄存器所指向的页表，进而在待获取的内存数据为用户空间的数据的情况下，将第一基址寄存器所指 向的页表作为第一页表共享给TEE侧，在待获取的内存数据为内核空间的数据的情况下，将第二基址寄存器所指向的页表作为第一页表共享给TEE侧。
其中，基址寄存器用于存储内存入口地址，从而指向该内存入口地址对应的数据。因此，处理器将REE侧的第一基址寄存器所指向的页表作为第一页表共享给TEE侧的第一基址寄存器的实现过程包括：将TEE侧的第一基址寄存器中存储的地址修改为REE侧的第一基址寄存器中存储的页表入口地址，以将REE侧的第一基址寄存器所指向的页表作为第一页表共享给TEE侧的第一基址寄存器。
同理，处理器将REE侧的第二基址寄存器所指向的页表作为第一页表共享给TEE侧的第二基址寄存器的实现过程包括：将TEE侧的第二基址寄存器中存储的地址修改为REE侧的第二基址寄存器中存储的页表入口地址，以将REE侧的第二基址寄存器所指向的页表作为第一页表共享给TEE侧的第二基址寄存器。
步骤602：处理器在目标SP中运行VMI程序。
在本申请实施例中，TEE侧的用户空间和内核空间中均部署有VMI程序。这样，在待获取的内存数据为用户空间的数据的情况下，处理器将REE侧的第一基址寄存器所指向的页表作为第一页表共享给TEE侧的第一基址寄存器之后，还需要将TEE侧的第二基址寄存器指向TEE侧的内核空间中部署的VMI程序，并以内核态权限在目标SP中运行第二基址寄存器指向的VMI程序。在待获取的内存数据为内核空间的数据的情况下，处理器将REE侧的第二基址寄存器所指向的页表作为第一页表共享给TEE侧的第二基址寄存器之后，还需要将TEE侧的第一基址寄存器指向TEE侧的用户空间中部署的VMI程序，并以内核态权限在目标SP中运行第一基址寄存器指向的VMI程序。
基于前文描述，TEE侧包括用户模式和内核模式，处理器能够工作在用户模式，也能够工作在内核模式。当获取目标VM在用户空间的数据时，在将REE侧的第一基址寄存器所指向的页表作为第一页表共享给TEE侧的第一基址寄存器之后，将TEE侧的第二基址寄存器指向TEE侧的内核空间中部署的VMI程序，从而使处理器在目标SP中运行TEE侧的内核空间中部署的VMI程序，实现了目标SP与目标VM的隔离。同理，当获取目标VM在内核空间的数据时，在将REE侧的第二基址寄存器所指向的页表作为第一页表共享给TEE侧的第二基址寄存器之后，将TEE侧的第一基址寄存器指向TEE侧的用户空间中部署的VMI程序，从而使处理器在目标SP中运行TEE侧的用户空间中部署的VMI程序，实现了目标SP与目标VM的隔离。
由于基址寄存器用于存储内存入口地址，从而指向该内存入口地址对应的数据。因此，处理器将TEE侧的第二基址寄存器指向TEE侧的内核空间中部署的VMI程序的实现过程包括：将TEE侧的第二基址寄存器中存储的地址修改为TEE侧的内核空间中部署的VMI程序的入口地址，以将TEE侧的第二基址寄存器指向TEE侧的内核空间中部署的VMI程序。同理，处理器将TEE侧的第一基址寄存器指向TEE侧的用户空间中部署的VMI程序的实现过程包括：将TEE侧的第一基址寄存器中存储的地址修改为TEE侧的用户空间中部署的VMI程序的入口地址，以将TEE侧的第一基址寄存器指向TEE侧的用户空间中部署的VMI程序。
基于步骤601中的描述，待获取的内存数据可能为目标VM在用户空间的数据，也可能为目标VM在内核空间的数据。为了实现目标SP与目标VM的隔离，当待获取的内存数据为目标VM在用户空间的数据时，TEE侧的第二基址寄存器会指向TEE侧的内核空间中部署 的VMI程序。由于VMI程序的代码和数据位于内核空间，待获取的内存数据位于用户空间，而且内核模式的权限等级高于用户模式的权限等级，处于内核模式的处理器能够访问用户空间的硬件资源，因此，处理器以内核态权限在目标SP中运行位于内核空间的VMI程序，从而能够成功读取用户空间的内存数据。也即是，以内核态权限在目标SP中运行第二基址寄存器指向的VMI程序，从而成功读取用户空间的内存数据。
但是，当待获取的内存数据为目标VM在内核空间的数据时，TEE侧的第一基址寄存器会指向TEE侧的用户空间中部署的VMI程序。由于VMI程序的代码和数据位于用户空间，待获取的内存数据位于内核空间，而且内核模式的权限等级高于用户模式的权限等级，如果以用户态权限在目标SP中运行位于用户空间的VMI程序，从而获取内核空间的内存数据的话，就会在权限检查时出错，所以，在本申请实施例中，处理器在目标SP中运行VMI程序时，需要以内核态权限在目标SP中运行位于用户空间的VMI程序，从而能够成功读取内核空间的内存数据。也即是，以内核态权限在目标SP中运行第一基址寄存器指向的VMI程序，能够成功读取内核空间的内存数据，从而解决了用户空间的VMI程序无法读取内核空间的数据的问题。
需要说明的是，VMI程序在运行的过程中需要访问自身所需的内存数据，但是VMI程序位于TEE侧，VMI程序所需的内存数据也就会存储在安全内存中，而目标VM的内存数据存储在非安全内存中，所以，在本申请实施例中，TEE侧还包括第四基址寄存器(如上述的vsttbr_el2)，第四基址寄存器指向第三页表，第三页表是指供VMI程序正常运行而进行中间地址到物理地址映射的页表。这样，处理器能够根据第四基址寄存器所指向的第三页表，在目标SP中运行VMI程序，从而保证VMI程序在运行的过程中能够在安全内存中访问自身所需的内存数据。同时也能够更好地将VMI程序的运行与目标VM进行隔离。
步骤603：处理器根据目标虚拟地址、第一页表和第二页表，通过目标SP中运行的VMI程序获取目标VM的内存数据，第二页表是指TEE侧和REE侧共享且用于将中间地址映射为物理地址的页表，目标虚拟地址是指待获取的内存数据对应的虚拟地址。
由于在访问内存数据时，需要进行两层内存地址的映射，而第一页表是进行第一层内存地址映射所采用的页表，第二页表是将中间地址映射为物理地址的页表，也即是，第二页表是进行第二层内存地址映射所采用的页表，因此，在将第一页表共享给TEE侧之后，还需要将第二页表共享给TEE侧。
基于上述描述，目标VM能够运行在用户空间或者内核空间，目标VM的数据具有用户空间和内核空间之分，这样在进行第一层内存地址映射时，就需要在用户空间和内核空间之间动态地切换第一页表。但是第二层内存地址映射分为安全内存和非安全内存的映射，比如，通过第二页表映射出来的物理地址落在非安全内存，通过第三页表映射出来的物理地址落在安全内存。也就是说，第二层内存地址映射分为安全内存和非安全内存的映射，不存在用户空间和内核空间之分，且目标VM的数据存储在非安全内存中，因此，在本申请实施例中，TEE侧和REE侧能够始终共享第二页表，而不需要在获取目标VM的数据的过程中再进行共享。
为了实现第二层内存地址映射，REE侧和REE侧均还包括第三基址寄存器(如上述的vttbr_el2)，REE侧的第三基址寄存器和TEE侧的第三基址寄存器均指向第二页表。这样，处理器根据目标虚拟地址、第一页表和第二页表，通过目标SP中运行的VMI程序获取目标VM 的内存数据的实现过程包括：处理器在目标SP中运行VMI程序的过程中，通过MMU根据第一页表确定目标虚拟地址对应的中间地址，以及根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址。处理器通过目标SP中运行的VMI程序获取物理地址对应的内存数据。
通常，处理器是通过虚拟地址来寻址的，但是内存数据又是基于物理地址存储在内存中的，因此，在处理器获取到目标虚拟地址之后，通过MMU可以对目标虚拟地址进行映射，从而确定对应的物理地址，进而由处理器按照该物理地址获取对应的内存数据。
其中，通过MMU根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址的实现过程包括：在中间地址所在的页表项存储在安全内存的情况下，通过MMU获取中间地址所在页表项中的NS位。如果NS位为第一数值，则通过MMU根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址。在中间地址所在的页表项存储在非安全内存的情况下，通过MMU根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址。
基于上述描述，目标VM的内存数据会存储在非安全内存，但是VMI程序在运行的过程中也可能需要访问自身所需要的内存数据，而这些内存数据存储在安全内存中，所以，处理器获取内存数据时，可能会访问安全内存，也可能会访问非安全内存，或者说通过第二层内存地址映射出来的物理地址可能会落到安全内存，也可能会落到非安全内存。但是内存地址映射的过程是MMU自动完成的，不需要任何的软件参与，因此，对于MMU来说，MMU并不知道处理器当前需要访问安全内存还是非安全内存，所以，在MMU确定出中间地址之后，需要基于中间地址所在的页表项存储在安全内存还是非安全内存，来判断是通过第二页表进行第二层内存地址的映射，还是通过第三页表进行第二层内存地址的映射表。
在中间地址所在的页表项存储在安全内存的情况下，通过第二层内存地址映射出来的物理地址可能会落到安全内存，也可能会落到非安全内存，此时，需要获取中间地址所在页表项中的NS位。如果NS位为第一数值，那么认为处理器当前需要获取非安全内存的数据，比如目标VM的数据，这样，通过第二层内存地址映射出来的物理地址会落到非安全内存，因此，MMU会根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址。如果NS位为第二数值，那么认为处理器当前需要获取安全内存的数据，比如VMI程序正常运行时所需的自身的内存数据，这样，通过第二层内存地址映射出来的物理地址会落到安全内存，因此，MMU会根据TEE侧的第四基址寄存器所指向的第三页表确定中间地址对应的物理地址。
但是，在中间地址所在的页表项存储在非安全内存的情况下，认为处理器当前获取的内存数据必然为非安全内存的数据，因此，MMU会直接根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址，而无需通过中间地址所在页表项中的NS位来决定。
需要说明的是，第一数值和第二数值事先设置，且能够按照需求调整。比如，第一数值为1，第二数值为0。也就是说，在中间地址所在页表项中的NS位为1的情况下，MMU会根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址。在中间地址所在页表项中的NS位为0的情况下，MMU会根据TEE侧的第四基址寄存器所指向的第三页表确定中间地址对应的物理地址。
为了保证MMU进行内存地址映射的准确性，在MMU通过第二层内存地址映射出来物理地址之后，MMU还能够判断映射出来的物理地址与对应的内存属性之间的关系是否匹配，从而确定内存地址映射过程中是否出错。即，当MMU根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址之后，MMU判断该物理地址是否位于非安全内存中，如果该物理地址位于非安全内存中，那么确定内存地址映射过程中没有出错，否则，确定内存地址映射过程中出错了。同理，当MMU会根据TEE侧的第四基址寄存器所指向的第三页表确定中间地址对应的物理地址之后，MMU判断该物理地址是否位于安全内存中，如果该物理地址位于安全内存中，那么确定内存地址映射过程中没有出错，否则，确定内存地址映射过程中出错了。通过后续的检测能够进一步提高内存地址映射的准确性。
需要说明的是，页表包括多级页表项，页表项用于指示内存地址的映射关系，且页表项中会包括控制位，比如NS位。本申请实施例对通过页表进行内存地址映射的具体实现过程不做过多介绍。
另外，VMI程序中还能够部署相关分析工具，这样，在目标SP获取到目标VM的内存数据之后，能够对目标VM的内存数据进行相关分析，尤其对于易受恶意攻击的目标VM进行入侵检测、内核完整性保护等，从而实现目标VM中进程粒度的实时分析，更好地保护目标VM，以避免目标VM被恶意攻击。
在本申请实施例中，由于第一页表是指将虚拟地址映射为中间地址的页表，第二页表是指TEE侧和REE侧共享且用于将中间地址映射为物理地址的页表，在REE侧和TEE侧共享第一页表和第二页表之后，TEE侧的目标SP能够根据第一页表和第二页表确定目标VM的虚拟地址对应的物理地址，进而能够快速、高效地获取目标VM的内存数据。而且，目标SP中运行的VMI程序不会占用目标VM的页表，也即是，第一页表或者第二页表中的页表项并不会被修改为指向目标SP中运行的VMI程序，这样就不会存在监控盲点，同时，目标SP中运行的VMI程序在REE侧还能够很好地进行隐藏，目标VM无法感知目标SP的存在。
再者，由于虚拟地址通常能够提供一些语义信息，因此，目标SP中的VMI程序获取到目标虚拟地址之后，能够获知目标虚拟地址所携带的语义信息，而且还能直接根据目标虚拟地址对应的物理地址读取目标VM的内存数据，从而解决了语义鸿沟的问题，能够更有效地检测目标VM是否被恶意攻击。另外，目标SP中VMI程序的正常运行是通过非共享的第三页表进行内存地址的映射，与目标VM完全隔离，而且目标SP位于TEE侧，目标VM位于REE侧，目标SP的安全性高于目标VM，这样，目标SP中运行的VMI程序不容易受到REE侧的攻击，提高了目标SP中运行的VMI程序的隐蔽性和安全性。
图7是本申请实施例提供的一种内存数据获取装置的结构示意图，该内存数据获取装置可以由软件、硬件或者两者的结合实现成为计算机设备的部分或者全部。该计算机设备的硬件资源被划分为REE侧和TEE侧，REE侧包括一个或多个VM，TEE侧包括一个或多个SP，TEE侧部署有VMI程序。参见图7，该装置包括：页表共享模块701、程序运行模块702和数据获取模块703。
页表共享模块701，用于将REE侧进行地址映射的第一页表共享给TEE侧，第一页表是指将虚拟地址映射为中间地址的页表。详细实现过程请参考上述图6所示的实施例中的步骤601，在此不再赘述。
程序运行模块702，用于在目标SP中运行VMI程序，目标SP是指一个或多个SP中用于获取目标VM的内存数据的SP，目标VM是指一个或多个VM中的任一VM。详细实现过程请参考上述图6所示的实施例中的步骤602，在此不再赘述。
数据获取模块703，用于根据目标虚拟地址、第一页表和第二页表，通过目标SP中运行的VMI程序获取目标VM的内存数据，第二页表是指TEE侧和REE侧共享且用于将中间地址映射为物理地址的页表，目标虚拟地址是指待获取的内存数据对应的虚拟地址。详细实现过程请参考上述图6所示的实施例中的步骤603，在此不再赘述。
可选地，REE侧和TEE侧均还包括第一基址寄存器和第二基址寄存器，第一基址寄存器为用户空间对应的基址寄存器，第二基址寄存器为内核空间对应的基址寄存器；
页表共享模块701具体用于：
在待获取的内存数据为用户空间的数据的情况下，将REE侧的第一基址寄存器所指向的页表作为第一页表共享给TEE侧的第一基址寄存器。
可选地，TEE侧的用户空间和内核空间中均部署有VMI程序；
程序运行模块702具体用于：
将TEE侧的第二基址寄存器指向TEE侧的内核空间中部署的VMI程序；
以内核态权限在目标SP中运行第二基址寄存器指向的VMI程序。
可选地，REE侧和TEE侧均还包括第一基址寄存器和第二基址寄存器，第一基址寄存器为用户空间对应的基址寄存器，第二基址寄存器为内核空间对应的基址寄存器；
页表共享模块701具体用于：
在待获取的内存数据为内核空间的数据的情况下，将REE侧的第二基址寄存器所指向的页表作为第一页表共享给TEE侧的第二基址寄存器。
可选地，TEE侧的用户空间和内核空间中均部署有VMI程序；
程序运行模块702具体用于：
将TEE侧的第一基址寄存器指向TEE侧的用户空间中部署的VMI程序；
以内核态权限在目标SP中运行第一基址寄存器指向的VMI程序。
可选地，REE侧和TEE侧均还包括第三基址寄存器，REE侧的第三基址寄存器和TEE侧的第三基址寄存器均指向第二页表；
数据获取模块703包括：
地址映射单元，用于在目标SP中运行VMI程序的过程中，通过内存管理单元MMU根据第一页表确定目标虚拟地址对应的中间地址，以及根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址；
数据获取单元，用于通过目标SP中运行的VMI程序获取物理地址对应的内存数据。
可选地，地址映射单元具体用于：
在中间地址所在的页表项存储在安全内存的情况下，通过MMU获取中间地址所在页表项中的非安全NS位；
如果NS位为第一数值，则通过MMU根据TEE侧的第三基址寄存器所指向的第二页表确定中间地址对应的物理地址。
可选地，地址映射单元具体用于：
在中间地址所在的页表项存储在非安全内存的情况下，通过MMU根据TEE侧的第三基 址寄存器所指向的第二页表确定中间地址对应的物理地址。
可选地，TEE侧还包括第四基址寄存器，第四基址寄存器指向第三页表，第三页表是指供VMI程序正常运行而进行中间地址到物理地址映射的页表；
程序运行模块702具体用于：
根据第四基址寄存器所指向的第三页表，在目标SP中运行VMI程序。
在本申请实施例中，由于第一页表是指将虚拟地址映射为中间地址的页表，第二页表是指TEE侧和REE侧共享且用于将中间地址映射为物理地址的页表，在REE侧和TEE侧共享第一页表和第二页表之后，TEE侧的目标SP能够根据第一页表和第二页表确定目标VM的虚拟地址对应的物理地址，进而能够快速、高效地获取目标VM的内存数据。而且，目标SP中运行的VMI程序不会占用目标VM的页表，也即是，第一页表或者第二页表中的页表项并不会被修改为指向目标SP中运行的VMI程序，这样就不会存在监控盲点，同时，目标SP中运行的VMI程序在REE侧还能够很好地进行隐藏，目标VM无法感知目标SP的存在。
再者，由于虚拟地址通常能够提供一些语义信息，因此，目标SP中的VMI程序获取到目标虚拟地址之后，能够获知目标虚拟地址所携带的语义信息，而且还能直接根据目标虚拟地址对应的物理地址读取目标VM的内存数据，从而解决了语义鸿沟的问题，能够更有效地检测目标VM是否被恶意攻击。另外，目标SP中VMI程序的正常运行是通过非共享的第三页表进行内存地址的映射，与目标VM完全隔离，而且目标SP位于TEE侧，目标VM位于REE侧，目标SP的安全性高于目标VM，这样，目标SP中运行的VMI程序不容易受到REE侧的攻击，提高了目标SP中运行的VMI程序的隐蔽性和安全性。
需要说明的是：上述实施例提供的内存数据获取装置在获取内存数据时，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的内存数据获取装置与内存数据获取方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
在上述实施例中，能够全部或部分地通过软件、硬件、固件或者其任意结合来实现。当使用软件实现时，能够全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络或其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如：同轴电缆、光纤、数据用户线(digital subscriber line，DSL))或无线(例如：红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质，或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质是磁性介质(例如：软盘、硬盘、磁带)、光介质(例如：数字通用光盘(digital versatile disc，DVD))或半导体介质(例如：固态硬盘(solid state disk，SSD))等。值得注意的是，本申请实施例提到的计算机可读存储介质可以为非易失性存储介质，换句话说，可以是非瞬时性存储介质。
应当理解的是，本文提及的“多个”是指两个或两个以上。在本申请实施例的描述中，除非另有说明，“/”表示或的意思，例如，A/B可以表示A或B；本文中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，为了便于清楚描述本申请实施例的技术方案，在本申请实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
以上所述为本申请提供的实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种内存数据获取方法，其特征在于，计算机设备的硬件资源被划分为富执行环境REE侧和可信执行环境TEE侧，所述REE侧包括一个或多个虚拟机VM，所述TEE侧包括一个或多个安全隔离区SP，所述TEE侧部署有虚拟机自省VMI程序，所述方法包括：
    处理器将所述REE侧进行地址映射的第一页表共享给所述TEE侧，所述第一页表是指将虚拟地址映射为中间地址的页表；
    所述处理器在目标SP中运行所述VMI程序，所述目标SP是指所述一个或多个SP中用于获取目标VM的内存数据的SP，所述目标VM是指所述一个或多个VM中的任一VM；
    所述处理器根据目标虚拟地址、所述第一页表和第二页表，通过所述目标SP中运行的所述VMI程序获取所述目标VM的内存数据，所述第二页表是指所述TEE侧和所述REE侧共享且用于将中间地址映射为物理地址的页表，所述目标虚拟地址是指待获取的内存数据对应的虚拟地址。
  2. 如权利要求1所述的方法，其特征在于，所述REE侧和所述TEE侧均还包括第一基址寄存器和第二基址寄存器，所述第一基址寄存器为用户空间对应的基址寄存器，所述第二基址寄存器为内核空间对应的基址寄存器；
    所述处理器将所述REE侧进行地址映射的第一页表共享给所述TEE侧，包括：
    当所述待获取的内存数据为所述用户空间的数据，所述处理器将所述REE侧的所述第一基址寄存器所指向的页表作为所述第一页表共享给所述TEE侧的所述第一基址寄存器。
  3. 如权利要求2所述的方法，其特征在于，所述TEE侧的所述用户空间和所述内核空间中均部署有所述VMI程序；
    所述处理器在目标SP中运行所述VMI程序，包括：
    所述处理器将所述TEE侧的所述第二基址寄存器指向所述TEE侧的所述内核空间中部署的所述VMI程序；
    所述处理器以内核态权限在所述目标SP中运行所述第二基址寄存器指向的VMI程序。
  4. 如权利要求1所述的方法，其特征在于，所述REE侧和所述TEE侧均还包括第一基址寄存器和第二基址寄存器，所述第一基址寄存器为用户空间对应的基址寄存器，所述第二基址寄存器为内核空间对应的基址寄存器；
    所述处理器将所述REE侧进行地址映射的第一页表共享给所述TEE侧，包括：
    当所述待获取的内存数据为所述内核空间的数据，所述处理器将所述REE侧的所述第二基址寄存器所指向的页表作为所述第一页表共享给所述TEE侧的所述第二基址寄存器。
  5. 如权利要求4所述的方法，其特征在于，所述TEE侧的所述用户空间和所述内核空间中均部署有所述VMI程序；
    所述处理器在目标SP中运行所述VMI程序，包括：
    所述处理器将所述TEE侧的所述第一基址寄存器指向所述TEE侧的所述用户空间中部署的所述VMI程序；
    所述处理器以内核态权限在所述目标SP中运行所述第一基址寄存器指向的VMI程序。
  6. 如权利要求1-5任一所述的方法，其特征在于，所述REE侧和所述TEE侧均还包括第三基址寄存器，所述REE侧的所述第三基址寄存器和所述TEE侧的所述第三基址寄存器均指向所述第二页表；
    所述处理器根据目标虚拟地址、所述第一页表和第二页表，通过所述目标SP中运行的所述VMI程序获取所述目标VM的内存数据，包括：
    所述处理器在所述目标SP中运行所述VMI程序的过程中，通过内存管理单元MMU根据所述第一页表确定所述目标虚拟地址对应的中间地址，以及根据所述TEE侧的所述第三基址寄存器所指向的所述第二页表确定所述中间地址对应的物理地址；
    所述处理器通过所述目标SP中运行的所述VMI程序获取所述物理地址对应的内存数据。
  7. 如权利要求6所述的方法，其特征在于，所述通过MMU根据所述TEE侧的所述第三基址寄存器所指向的所述第二页表确定所述中间地址对应的物理地址，包括：
    在所述中间地址所在的页表项存储在安全内存的情况下，通过所述MMU获取所述中间地址所在页表项中的非安全NS位；
    如果所述NS位为第一数值，则通过所述MMU根据所述TEE侧的所述第三基址寄存器所指向的所述第二页表确定所述中间地址对应的物理地址。
  8. 如权利要求6所述的方法，其特征在于，所述通过MMU根据所述TEE侧的所述第三基址寄存器所指向的所述第二页表确定所述中间地址对应的物理地址，包括：
    在所述中间地址所在的页表项存储在非安全内存的情况下，通过所述MMU根据所述TEE侧的所述第三基址寄存器所指向的所述第二页表确定所述中间地址对应的物理地址。
  9. 如权利要求1-8任一所述的方法，其特征在于，所述TEE侧还包括第四基址寄存器，所述第四基址寄存器指向第三页表，所述第三页表是指供所述VMI程序正常运行而进行中间地址到物理地址映射的页表；
    所述处理器在目标SP中运行所述VMI程序，包括：
    所述处理器根据所述第四基址寄存器所指向的所述第三页表，在所述目标SP中运行所述VMI程序。
  10. 一种内存数据获取装置，其特征在于，计算机设备的硬件资源被划分为富执行环境REE侧和可信执行环境TEE侧，所述REE侧包括一个或多个虚拟机VM，所述TEE侧包括一个或多个安全隔离区SP，所述TEE侧部署有虚拟机自省VMI程序，所述装置包括：
    页表共享模块，用于将所述REE侧进行地址映射的第一页表共享给所述TEE侧，所述第一页表是指将虚拟地址映射为中间地址的页表；
    程序运行模块，用于在目标SP中运行所述VMI程序，所述目标SP是指所述一个或多 个SP中用于获取目标VM的内存数据的SP，所述目标VM是指所述一个或多个VM中的任一VM；
    数据获取模块，用于根据目标虚拟地址、所述第一页表和第二页表，通过所述目标SP中运行的所述VMI程序获取所述目标VM的内存数据，所述第二页表是指所述TEE侧和所述REE侧共享且用于将中间地址映射为物理地址的页表，所述目标虚拟地址是指待获取的内存数据对应的虚拟地址。
  11. 如权利要求10所述的装置，其特征在于，所述REE侧和所述TEE侧均还包括第一基址寄存器和第二基址寄存器，所述第一基址寄存器为用户空间对应的基址寄存器，所述第二基址寄存器为内核空间对应的基址寄存器；
    所述页表共享模块具体用于：
    当所述待获取的内存数据为所述用户空间的数据，将所述REE侧的所述第一基址寄存器所指向的页表作为所述第一页表共享给所述TEE侧的所述第一基址寄存器。
  12. 如权利要求11所述的装置，其特征在于，所述TEE侧的所述用户空间和所述内核空间中均部署有所述VMI程序；
    所述程序运行模块具体用于：
    将所述TEE侧的所述第二基址寄存器指向所述TEE侧的所述内核空间中部署的所述VMI程序；
    以内核态权限在所述目标SP中运行所述第二基址寄存器指向的VMI程序。
  13. 如权利要求10所述的装置，其特征在于，所述REE侧和所述TEE侧均还包括第一基址寄存器和第二基址寄存器，所述第一基址寄存器为用户空间对应的基址寄存器，所述第二基址寄存器为内核空间对应的基址寄存器；
    所述页表共享模块具体用于：
    当所述待获取的内存数据为所述内核空间的数据，将所述REE侧的所述第二基址寄存器所指向的页表作为所述第一页表共享给所述TEE侧的所述第二基址寄存器。
  14. 如权利要求13所述的装置，其特征在于，所述TEE侧的所述用户空间和所述内核空间中均部署有所述VMI程序；
    所述程序运行模块具体用于：
    将所述TEE侧的所述第一基址寄存器指向所述TEE侧的所述用户空间中部署的所述VMI程序；
    以内核态权限在所述目标SP中运行所述第一基址寄存器指向的VMI程序。
  15. 如权利要求1-14任一所述的装置，其特征在于，所述REE侧和所述TEE侧均还包括第三基址寄存器，所述REE侧的所述第三基址寄存器和所述TEE侧的所述第三基址寄存器均指向所述第二页表；
    所述数据获取模块包括：
    地址映射单元，用于在所述目标SP中运行所述VMI程序的过程中，通过内存管理单元MMU根据所述第一页表确定所述目标虚拟地址对应的中间地址，以及根据所述TEE侧的所述第三基址寄存器所指向的所述第二页表确定所述中间地址对应的物理地址；
    数据获取单元，用于通过所述目标SP中运行的所述VMI程序获取所述物理地址对应的内存数据。
  16. 如权利要求15所述的装置，其特征在于，所述地址映射单元具体用于：
    在所述中间地址所在的页表项存储在安全内存的情况下，通过所述MMU获取所述中间地址所在页表项中的非安全NS位；
    如果所述NS位为第一数值，则通过所述MMU根据所述TEE侧的所述第三基址寄存器所指向的所述第二页表确定所述中间地址对应的物理地址。
  17. 如权利要求15所述的装置，其特征在于，所述地址映射单元具体用于：
    在所述中间地址所在的页表项存储在非安全内存的情况下，通过所述MMU根据所述TEE侧的所述第三基址寄存器所指向的所述第二页表确定所述中间地址对应的物理地址。
  18. 如权利要求10-17任一所述的装置，其特征在于，所述TEE侧还包括第四基址寄存器，所述第四基址寄存器指向第三页表，所述第三页表是指供所述VMI程序正常运行而进行中间地址到物理地址映射的页表；
    所述程序运行模块具体用于：
    根据所述第四基址寄存器所指向的所述第三页表，在所述目标SP中运行所述VMI程序。
  19. 一种计算机可读存储介质，其特征在于，所述存储介质内存储有指令，当所述指令在计算机设备上运行时，使得所述计算机设备执行权利要求1-9任一所述的方法的步骤。
  20. 一种计算机程序产品，其特征在于，包括指令，当所述指令在计算机设备上运行时，使得所述计算机设备执行权利要求1-9任一所述的方法的步骤。
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