WO2024113370A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024113370A1
WO2024113370A1 PCT/CN2022/136318 CN2022136318W WO2024113370A1 WO 2024113370 A1 WO2024113370 A1 WO 2024113370A1 CN 2022136318 W CN2022136318 W CN 2022136318W WO 2024113370 A1 WO2024113370 A1 WO 2024113370A1
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WIPO (PCT)
Prior art keywords
layer
transistor
orthographic projection
base substrate
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/136318
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English (en)
French (fr)
Inventor
张跳梅
于子阳
李宇婧
蒋志亮
胡明
邱海军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US18/842,819 priority Critical patent/US20250176375A1/en
Priority to GB2417030.0A priority patent/GB2634163A/en
Priority to PCT/CN2022/136318 priority patent/WO2024113370A1/zh
Priority to CN202280004872.8A priority patent/CN118435723A/zh
Publication of WO2024113370A1 publication Critical patent/WO2024113370A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/361—Temperature

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • the light transmittance of the display panel is relatively low, so that the display panel cannot meet the light transmittance requirements of technologies such as fingerprint recognition and under-screen cameras.
  • a display panel includes a light-emitting unit, and the display panel also includes: a substrate, a light-shielding layer, a pixel defining layer, and a multi-layer functional layer.
  • the substrate includes a light-transmitting area; the light-shielding layer is located on one side of the substrate, and the light-shielding layer has a light-shielding function; the pixel defining layer is located on the side of the light-shielding layer away from the substrate, and a pixel opening is formed on the pixel defining layer, and the pixel opening is used to form the light-emitting unit; the multi-layer functional layer is located between the substrate and the pixel defining layer, and the light-shielding structure of all functional layers located between the substrate and the pixel defining layer has an orthographic projection on the substrate that is located outside the light-transmitting area; the light-shielding layer has a first opening formed on the light-shielding layer, and the orthographic projection of the first opening on the substrate is located in the light-transmitting area.
  • the display panel also includes a pixel driving circuit for driving the light-emitting unit, and the pixel driving circuit includes a driving transistor;
  • the multi-layer functional layer includes: a first active layer, the first active layer includes a third active portion, and the third active portion is used to form a channel region of the driving transistor;
  • the light-shielding layer is located between the first active layer and the base substrate, the light-shielding layer includes a first light-shielding portion, and the orthographic projection of the first light-shielding portion on the base substrate covers the orthographic projection of the third active portion on the base substrate.
  • the pixel driving circuit further includes a first transistor and a fourth transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a gate electrode of the driving transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor;
  • the display panel further includes: a first reset signal line and a second gate line, wherein an orthographic projection of the first reset signal line on the substrate extends along a first direction, and a partial structure of the first reset signal line is used to form a top gate of the first transistor; an orthographic projection of the second gate line on the substrate extends along the first direction, and a partial structure of the second gate line is used to form a gate electrode of the fourth transistor; wherein an orthographic projection of the first opening on the substrate is located between the orthographic projections of the first reset signal line and the second gate line on the substrate in the same pixel driving circuit.
  • the display panel includes a plurality of repeating units, and the plurality of repeating units are arranged in an array in a first direction and a second direction, and the first direction and the second direction intersect;
  • the repeating unit includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same repeating unit are arranged in mirror symmetry.
  • the pixel driving circuit also includes a fourth transistor, a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; the orthographic projection of the data line on the substrate extends along the second direction, and the orthographic projection of the first opening on the substrate is located between the orthographic projections of two adjacent data lines on the substrate in the same repeating unit.
  • the pixel driving circuit also includes a sixth transistor and a seventh transistor, the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit;
  • the first active layer also includes: a sixth active portion, a seventh active portion, and an eighth active portion, the sixth active portion is used to form a channel region of the sixth transistor; the seventh active portion is used to form a channel region of the seventh transistor; the eighth active portion is connected between the sixth active portion and the seventh active portion;
  • the light-shielding layer also includes: a second light-shielding portion, the second light-shielding portion is connected to the first light-shielding portion; wherein the orthographic projection of the eighth active portion on the substrate and the orthographic projection of the second light-shielding portion
  • the orthographic projection of the eighth active portion on the substrate extends along a first direction, and the size of the orthographic projection of the eighth active portion on the substrate in the first direction is larger than the size of the orthographic projection of the eighth active portion on the substrate in the second direction; the orthographic projection of the second light-shielding portion on the substrate extends along the first direction, and the size of the orthographic projection of the second light-shielding portion on the substrate in the first direction is larger than the size of the orthographic projection of the second light-shielding portion on the substrate in the second direction; the first direction and the second direction intersect.
  • the light-shielding layer further includes: a third light-shielding portion, the orthographic projection of the third light-shielding portion on the substrate extends along the second direction, and the third light-shielding portion is connected between the first light-shielding portion and the second light-shielding portion;
  • the second light-shielding portion includes a first sub-light-shielding portion and a second sub-light-shielding portion, and in the first direction, the orthographic projections of the first sub-light-shielding portion and the second sub-light-shielding portion on the substrate are located on both sides of the orthographic projection of the third light-shielding portion on the substrate;
  • the orthographic projection of the first sub-light-shielding portion on the substrate and the orthographic projection of the eighth active portion on the substrate at least partially overlap, and the orthographic projection of the second sub-light-shielding portion on the substrate and the orthographic projection of the eighth active portion on
  • the first active layer also includes: a ninth active portion, the orthographic projection of the ninth active portion on the substrate extends along the second direction, and the ninth active portion is connected between the eighth active portion and the seventh active portion;
  • the eighth active portion includes a first sub-active portion and a second sub-active portion, and in the first direction, the orthographic projections of the first sub-active portion and the second sub-active portion on the substrate are located on both sides of the orthographic projection of the ninth active portion on the substrate;
  • the orthographic projection of the first sub-active portion on the substrate and the orthographic projection of the second shading portion on the substrate at least partially overlap, and the orthographic projection of the second sub-active portion on the substrate and the orthographic projection of the second shading portion on the substrate at least partially overlap.
  • the display panel includes a plurality of repeating units, and the plurality of repeating units are arranged in an array in a first direction and a second direction, and the first direction and the second direction intersect;
  • the repeating unit includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same repeating unit are arranged in a mirror-symmetrical manner;
  • the first light-shielding layer also includes: a fourth light-shielding portion, the fourth light-shielding portion and the repeating unit are arranged correspondingly, the fourth light-shielding portion is connected to the two second light-shielding portions in the repeating unit corresponding to it, and the fourth light-shielding portion is connected to an end of the second light-shielding portion away from the first light-shielding portion, and the first opening is formed on the fourth light-shielding portion.
  • the pixel driving circuit also includes a second transistor, a first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor;
  • the multi-layer functional layer also includes: a first conductive layer and a fourth conductive layer, the first conductive layer is located between the first active layer and the pixel defining layer, the first conductive layer includes a first conductive portion, the orthographic projection of the first conductive portion on the substrate covers the orthographic projection of the third active portion on the substrate, and the first conductive portion is used to form the gate of the driving transistor;
  • the fourth conductive layer is located between the first conductive layer and the pixel defining layer, the fourth conductive layer includes a first bridge portion and a second bridge portion; wherein the first bridge portion is connected to the first electrode of the second transistor, and the first bridge portion is connected to the first conductive portion through a via, the second bridge portion is connected to the eighth active portion through a via, and the size of the
  • an area of an orthographic projection of the first opening on the base substrate is smaller than an area of an orthographic projection of the first light shielding portion on the base substrate.
  • the pixel driving circuit further includes a first transistor and a second transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a gate of the driving transistor, a first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor;
  • the multi-layer functional layer further includes: a first conductive layer and a fourth conductive layer, wherein the first conductive layer is located between the first active layer and the pixel defining layer, the first conductive layer includes a first conductive portion, an orthographic projection of the first conductive portion on the base substrate covers an orthographic projection of the third active portion on the base substrate, and the first conductive portion is used to form the gate of the driving transistor;
  • the fourth conductive layer is located between the first conductive layer and the pixel defining layer, the fourth conductive layer includes a first bridging portion and the first initial signal line, and an orthographic projection
  • the pixel driving circuit also includes a capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to a first power line;
  • the multi-layer functional layer also includes: a first conductive layer, a second conductive layer, a fourth conductive layer, and a fifth conductive layer, the first conductive layer is located between the first active layer and the pixel defining layer, the first conductive layer includes a first conductive portion, the orthographic projection of the first conductive portion on the substrate covers the orthographic projection of the third active portion on the substrate, and the first conductive portion is used to form the gate of the driving transistor and the first electrode of the capacitor;
  • the second conductive layer is located between the first conductive layer and the pixel defining layer, the second conductive layer includes a second conductive portion and a first connecting portion, the orthographic projection of the second conductive portion on the substrate at least partially overlaps with the orthographic projection of the first conductive portion on the substrate, and the second conductive
  • the pixel defining layer is black, and a second opening is further formed on the pixel defining layer, the orthographic projection of the second opening on the substrate is located in the light-transmitting area; the orthographic projection of the second opening on the substrate coincides with the orthographic projection of the first opening on the substrate; or, the orthographic projection area of the second opening on the substrate is larger than the orthographic projection area of the first opening on the substrate, and the orthographic projection of the second opening on the substrate covers the orthographic projection of the first opening on the substrate; or, the orthographic projection area of the first opening on the substrate is larger than the orthographic projection area of the second opening on the substrate, and the orthographic projection of the first opening on the substrate covers the orthographic projection of the second opening on the substrate.
  • the display panel includes a display area, the display area includes a light signal collection area, and at least the light shielding layer in the light signal collection area is provided with the first opening.
  • the display area also includes a normal display area located outside the optical signal collection area; the orthographic projection of the light shading layer located in the optical signal collection area on the base substrate and the orthographic projection of the light shading layer located in the normal display area on the base substrate have different pattern shapes.
  • the display area also includes a normal display area outside the optical signal collection area, and the light-shielding layer in the normal display area is also provided with the first opening; the orthographic projection of the light-shielding layer located in the optical signal collection area on the base substrate and the orthographic projection of the light-shielding layer located in the normal display area on the base substrate have the same pattern shape.
  • the light shielding layer located in the optical signal collection area is provided on the entire surface except for the first opening.
  • the pixel driving circuit also includes a plurality of switching transistors;
  • the first active layer also includes: a plurality of active parts, the active parts are used to form a channel region of the switching transistor; wherein a plurality of first openings are also formed on the light shielding layer located in the optical signal acquisition area, the first openings and the active parts are arranged correspondingly, and the orthographic projection of the first opening on the substrate covers the orthographic projection of the corresponding active part on the substrate.
  • the light-shielding layer located in the normal display area further includes: a plurality of second connecting portions and a plurality of third connecting portions, wherein the orthographic projections of the second connecting portions on the base substrate extend along a first direction and are connected between the first light-shielding portions adjacent to each other in the first direction; the orthographic projections of the third connecting portions on the base substrate extend along a second direction and are connected between the first light-shielding portions adjacent to each other in the second direction, and the first direction and the second direction intersect.
  • the display panel further includes a display area, and the display area includes a fan-out area and an optical signal collection area; the display panel further includes: a plurality of data lines, a plurality of first data fan-out lines, and a plurality of second data fan-out lines, wherein the plurality of data lines are located in the display area, and the orthographic projections of the data lines on the substrate are spaced apart along a first direction and extend along a second direction, and the first direction and the second direction intersect; a plurality of first data fan-out lines are located in the fan-out area, and the orthographic projections of the first data fan-out lines on the substrate are spaced apart along the second direction and extend along the first direction, and the first data fan-out lines are arranged correspondingly to the data lines, and the first data fan-out lines are connected to the data lines corresponding thereto; a plurality of second data fan-out lines are located in the fan-out area, and the orthographic projections of the second data fan-out lines are located in the fan-out area
  • the multilayer functional layer also includes: a fifth conductive layer, the fifth conductive layer is located between the base substrate and the pixel defining layer, the fifth conductive layer includes the data line; the light shielding layer is located between the fifth conductive layer and the pixel defining layer.
  • the display area also includes other display areas located outside the fan-out area and the optical signal collection area;
  • the display panel also includes: a plurality of first signal lines, and the plurality of first signal lines are located in a conductive layer outside the light-shielding layer;
  • the light-shielding layer located in the other display areas includes a plurality of second signal lines, and the orthographic projection of the first signal line on the substrate intersects with the orthographic projection of the second signal line on the substrate, and the second signal line is connected to the first signal line intersecting with it through a via.
  • the display panel also includes a pixel driving circuit, which includes a driving transistor, a first transistor, a fifth transistor, and a seventh transistor; the first electrode of the first transistor is connected to a first initial signal line, the second electrode of the first transistor is connected to a gate of the driving transistor, the first electrode of the fifth transistor is connected to a first power line, the second electrode of the fifth transistor is connected to the first electrode of the driving transistor, the first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit; the multiple first signal lines include one or more of the first initial signal line, the second initial signal line, and the first power line.
  • a pixel driving circuit which includes a driving transistor, a first transistor, a fifth transistor, and a seventh transistor; the first electrode of the first transistor is connected to a first initial signal line, the second electrode of the first transistor is connected to a gate of the driving transistor, the first electrode of the fifth transistor is connected to a first power line,
  • the display area also includes other display areas located outside the fan-out area and the optical signal collection area;
  • the display panel also includes: a common electrode layer, the common electrode layer is located on the side of the pixel defining layer away from the base substrate, the common electrode layer is used to form the second electrode of the light-emitting unit;
  • the shading layer located in the other display areas includes a plurality of second power lines, and the second power lines are connected to the common electrode layer.
  • the orthographic projections of some of the second power lines on the base substrate extend along the first direction
  • the orthographic projections of some of the second power lines on the base substrate extend along the second direction
  • the second power lines with different extension directions intersect.
  • the display panel also includes a pixel driving circuit, which is used to drive the light-emitting unit to emit light.
  • the pixel driving circuit includes: a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor.
  • the first electrode of the first transistor is connected to the first initial signal line, and the second electrode is connected to the gate of the driving transistor; the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode is connected to the second electrode of the driving transistor; the first electrode of the fourth transistor is connected to the data line, and the second electrode is connected to the first electrode of the driving transistor; the first electrode of the fifth transistor is connected to the first power line, and the second electrode is connected to the first electrode of the driving transistor; the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit; the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit; the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to the first power line; the first transistor and the second transistor are N-type transistors, and the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the
  • the multilayer functional layer includes: a first active layer, a first conductive layer, a second active layer, and a third conductive layer.
  • the first active layer is located between the base substrate and the pixel defining layer, and the first active layer includes: a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, and a seventh active portion; wherein the third active portion is used to form the channel region of the driving transistor, the fourth active portion is used to form the channel region of the fourth transistor, the fifth active portion is used to form the channel region of the fifth transistor, the sixth active portion is used to form the channel region of the sixth transistor, and the seventh active portion is used to form the channel region of the seventh transistor;
  • the first conductive layer is located between the first active layer and the pixel defining layer, and the first conductive layer includes: a second reset signal line, a second gate line, an enable signal line, and a first conductive portion, wherein the orthographic projections of the second reset signal line, the second gate line
  • the first reset signal line, the second gate line, the first gate line, the first conductive portion, the enable signal line, and the second reset signal line are sequentially distributed in the second direction in their orthographic projections on the substrate, and the first direction and the second direction intersect; the second gate line in the pixel driving circuit of this row is multiplexed as the second reset signal line in the pixel driving circuit of the previous row.
  • the display panel also includes a pixel driving circuit, which is used to drive the light-emitting unit to emit light;
  • the multi-layer functional layer also includes: an electrode layer, the electrode layer includes a plurality of electrode portions, the electrode portion is used to form a first electrode of the light-emitting unit, and the plurality of electrode portions include a first electrode portion, a second electrode portion, and a third electrode portion; among the plurality of electrode portions connected to the pixel driving circuit in the same row, the second electrode portion, the first electrode portion, the third electrode portion, and the first electrode portion are alternately distributed in sequence in the row direction; in two adjacent columns of pixel driving circuits, a plurality of second electrode portions and a plurality of third electrode portions are connected to the pixel driving circuit in the same column, and the second electrode portions and the third electrode portions connected to the pixel driving circuit in the same column are alternately distributed in sequence in the column direction, a plurality of first electrode portions are connected to the pixel driving circuit in another column, and the
  • the first opening is used to image the optical signal hole on one side of the display panel onto the other side of the display panel.
  • a display panel comprising: a base substrate, a shading layer, a shading layer, the shading layer is located on one side of the base substrate, and the shading layer has a shading effect; a plurality of functional layers are located on one side of the base substrate; wherein a first opening is formed on the shading layer, the orthographic projection of the first opening on the base substrate and the orthographic projection of the shading structure in the functional layer on the base substrate do not overlap, and the orthographic projection of the shading layer on the base substrate and the orthographic projection of at least one layer of the shading structure in the functional layer on the base substrate overlap.
  • the display panel also includes a light-emitting unit and a pixel driving circuit for driving the light-emitting unit, the pixel driving circuit includes a driving transistor;
  • the multi-layer functional layer includes: a first active layer, the first active layer includes a third active portion, the third active portion is used to form a channel region of the driving transistor;
  • the light-shielding layer is located between the first active layer and the base substrate, the light-shielding layer includes a first light-shielding portion, the orthographic projection of the first light-shielding portion on the base substrate covers the orthographic projection of the third active portion on the base substrate.
  • the pixel driving circuit also includes a first transistor and a fourth transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a gate electrode of the driving transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor;
  • the display panel also includes: a first reset signal line and a second gate line, wherein an orthographic projection of the first reset signal line on the substrate extends along a first direction, and a partial structure of the first reset signal line is used to form a top gate of the first transistor; an orthographic projection of the second gate line on the substrate extends along the first direction, and a partial structure of the second gate line is used to form a gate electrode of the fourth transistor; wherein an orthographic projection of the first opening on the substrate is located between the orthographic projections of the first reset signal line and the second gate line on the substrate in the same pixel driving circuit.
  • the display panel further includes a display area, and the display area includes a fan-out area and an optical signal collection area; the display panel further includes: a plurality of data lines, a plurality of first data fan-out lines, and a plurality of second data fan-out lines, wherein the plurality of data lines are located in the display area, and the orthographic projections of the data lines on the substrate are spaced apart along a first direction and extend along a second direction, and the first direction and the second direction intersect; a plurality of first data fan-out lines are located in the fan-out area, and the orthographic projections of the first data fan-out lines on the substrate are spaced apart along the second direction and extend along the first direction, and the first data fan-out lines are arranged correspondingly to the data lines, and the first data fan-out lines are connected to the data lines corresponding thereto; a plurality of second data fan-out lines are located in the fan-out area, and the orthographic projections of the second data fan-out lines are located in the fan-out area
  • a display device comprising the above-mentioned display panel.
  • FIG1 is a schematic diagram of a circuit structure of a pixel driving circuit in the related art
  • FIG2 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG1 ;
  • FIG3 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;
  • FIG4 is a structural diagram of the light shielding layer in FIG3 ;
  • FIG5 is a structural diagram of the first active layer in FIG3;
  • FIG6 is a structural diagram of the first conductive layer in FIG3 ;
  • FIG7 is a structural diagram of the second conductive layer in FIG3 ;
  • FIG8 is a structural diagram of the second active layer in FIG3;
  • FIG9 is a structural diagram of the third conductive layer in FIG3 ;
  • FIG10 is a structural diagram of the fourth conductive layer in FIG3 ;
  • FIG11 is a structural diagram of the fifth conductive layer in FIG3 ;
  • FIG12 is a structural layout diagram of the electrode layer and the pixel definition layer in FIG3;
  • FIG13 is a structural diagram of the pixel definition layer in FIG3 ;
  • FIG14 is a structural layout diagram of the light shielding layer and the first active layer in FIG3;
  • FIG15 is a structural layout diagram of the light shielding layer, the first active layer, and the first conductive layer in FIG3;
  • FIG16 is a structural layout diagram of the light shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG3;
  • FIG17 is a structural layout diagram of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG3 ;
  • FIG18 is a structural layout diagram of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG3 ;
  • FIG19 is a structural layout diagram of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG3 ;
  • FIG20 is a structural layout diagram of the light shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG3 ;
  • FIG21 is a partial cross-sectional view of the display panel shown in FIG3 taken along dotted line AA;
  • FIG22 is a schematic structural diagram of another exemplary embodiment of a display panel disclosed herein;
  • FIG23 is a layout structure of a light shielding layer in an optical signal collection area
  • FIG24 is a layout structure of a light shielding layer in a normal display area
  • FIG25 is another layout structure of the light shielding layer in the optical signal collection area
  • FIG26 is a schematic structural diagram of another exemplary embodiment of a display panel disclosed herein;
  • FIG. 27 is a layout structure of a light shielding layer in other display areas of the display panel shown in FIG. 26 .
  • the pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the second gate driving signal terminal G2;
  • the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM;
  • the gate of the driving transistor T3 is connected to the node N;
  • the first electrode of the second transistor T2 is connected to the node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1;
  • the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the first electrode of the seventh transistor T7, the gate is connected to the enable signal terminal EM, the second electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2;
  • the pixel driving circuit can be connected to a light-emitting unit OLED, which is used to drive the light-emitting unit OLED to emit light, and the light-emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS.
  • the first transistor T1 and the second transistor T2 can be N-type transistors, for example, the first transistor T1 and the second transistor T2 can be N-type metal oxide transistors, and the N-type transistor has a smaller leakage current, so that the leakage current of the node N through the first transistor T1 and the second transistor T2 can be reduced during the light-emitting stage.
  • the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors, for example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon transistors, and the P-type low-temperature polycrystalline silicon transistor has a higher carrier mobility, which is conducive to realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio.
  • the first initial signal terminal and the second initial signal terminal can output the same or different voltage signals according to actual conditions.
  • FIG2 it is a timing diagram of each node in a driving method of the pixel driving circuit in FIG1.
  • G1 represents the timing of the first gate driving signal terminal G1
  • G2 represents the timing of the second gate driving signal terminal G2
  • Re1 represents the timing of the first reset signal terminal Re1
  • Re2 represents the timing of the second reset signal terminal Re2
  • EM represents the timing of the enable signal terminal EM.
  • the driving method of the pixel driving circuit may include a first reset stage t1, a compensation stage t2, a second reset stage t3, and a light-emitting stage t4.
  • the first reset stage t1 the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N.
  • the compensation stage t2 the first gate drive signal terminal G1 outputs a high level signal, the second gate drive signal terminal G2 outputs a low level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da outputs a data signal to write a voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3.
  • the second reset signal terminal Re2 outputs a low level signal
  • the seventh transistor T7 is turned on
  • the second initial signal terminal Vinit2 inputs an initial signal to the second electrode of the sixth transistor T6.
  • Light-emitting stage t4 the enable signal terminal EM outputs a low level signal
  • the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the output current formula of the driving transistor is as follows:
  • the pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.
  • This exemplary embodiment provides a display panel, which may include a base substrate, a light shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, an electrode layer, and a pixel defining layer stacked in sequence, wherein an insulating layer may be arranged between adjacent conductive layers.
  • Figure 3 is a structural layout of an exemplary embodiment of the display panel of the present disclosure
  • Figure 4 is a structural layout of the light shielding layer in Figure 3
  • Figure 5 is a structural layout of the first active layer in Figure 3
  • Figure 6 is a structural layout of the first conductive layer in Figure 3
  • Figure 7 is a structural layout of the second conductive layer in Figure 3
  • Figure 8 is a structural layout of the second active layer in Figure 3
  • Figure 9 is a structural layout of the third conductive layer in Figure 3
  • Figure 10 is a structural layout of the fourth conductive layer in Figure 3
  • Figure 11 is a structural layout of the fifth conductive layer in Figure 3
  • Figure 12 is a structural layout of the electrode layer and the pixel defining layer in Figure 3
  • Figure 13 is a structural layout of the pixel defining layer in Figure 3
  • Figure 14 is a structural layout of the light shielding layer and the first active layer in Figure 3
  • the display panel may include a plurality of pixel drive circuits shown in FIG1 .
  • the plurality of pixel driving circuits may include a first pixel driving circuit Pix1 and a second pixel driving circuit Pix2 adjacently distributed in a first direction X, and the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 may be arranged in a mirror-symmetrical manner.
  • the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 may form a repeating unit, and the display panel may include a plurality of repeating units arrayed in the first direction X and the second direction Y.
  • the first direction X and the second direction Y may intersect, for example, the first direction may be a row direction, and the second direction may be a column direction.
  • the shading layer may include a plurality of first shading portions 71, which are distributed in an array in the first direction X and the second direction Y, and the adjacent first shading portions 71 in the first direction X are connected, and the adjacent first shading portions 71 in the second direction Y are connected.
  • the first active layer may include a third active portion 63, a fourth active portion 64, a fifth active portion 65, a sixth active portion 66, a seventh active portion 67, an eighth active portion 68, a ninth active portion 69, a tenth active portion 610, an eleventh active portion 611, a twelfth active portion 612, and a thirteenth active portion 613.
  • the third active portion 63 can be used to form a channel region of the driving transistor T3; the fourth active portion 64 can be used to form a channel region of the fourth transistor T4; the fifth active portion 65 can be used to form a channel region of the fifth transistor T5; the sixth active portion 66 can be used to form a channel region of the sixth transistor T6; the seventh active portion 67 can be used to form a channel region of the seventh transistor T7; the eighth active portion 68 is connected between the sixth active portion 66 and the seventh active portion 67, and the orthographic projection of the eighth active portion 68 on the substrate substrate extends along the first direction X, and the size of the orthographic projection of the eighth active portion 68 on the substrate substrate in the first direction X is greater than the size of the orthographic projection of the eighth active portion 68 on the substrate substrate.
  • the first active layer can be formed of polysilicon material, and accordingly, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low temperature polysilicon thin film transistors
  • the orthographic projection of the first light shielding portion 71 on the substrate covers the orthographic projection of the third active portion 63 on the substrate, and the first light shielding portion 71 can shield the third active portion 63 to reduce the influence of light on the characteristics of the driving transistor T3.
  • the light shielding layer can also include a second light shielding portion 72 and a third light shielding portion 73, the orthographic projection of the third light shielding portion 73 on the substrate extends along the second direction Y, and the third light shielding portion 73 is connected between the first light shielding portion 71 and the second light shielding portion 72.
  • the second light-shielding portion 72 may include a first sub-light-shielding portion 721 and a second sub-light-shielding portion 722.
  • the orthographic projections of the first sub-light-shielding portion 721 and the second sub-light-shielding portion 722 on the substrate are located on both sides of the orthographic projection of the third light-shielding portion 73 on the substrate; the orthographic projection of the first sub-light-shielding portion 721 on the substrate and the orthographic projection of the eighth active portion 68 on the substrate at least partially overlap, and the orthographic projection of the second sub-light-shielding portion 722 on the substrate and the orthographic projection of the eighth active portion 68 on the substrate at least partially overlap.
  • the eighth active portion 68 may include a first sub-active portion 681 and a second sub-active portion 682.
  • the orthographic projections of the first sub-active portion 681 and the second sub-active portion 682 on the substrate are located on both sides of the orthographic projection of the ninth active portion 69 on the substrate; the orthographic projection of the first sub-active portion 681 on the substrate and the orthographic projection of the second light-shielding portion 72 on the substrate at least partially overlap, and the orthographic projection of the second sub-active portion 682 on the substrate and the orthographic projection of the second light-shielding portion 72 on the substrate at least partially overlap.
  • the first conductive layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, and a second reset signal line Re2.
  • the second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1;
  • the enable signal line EM can be used to provide the enable signal terminal in Figure 1;
  • the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1.
  • the orthographic projection of the second gate line G2 on the substrate, the orthographic projection of the enable signal line EM on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate can all extend along the first direction X.
  • the orthographic projection of the second gate line G2 on the substrate covers the orthographic projection of the fourth active portion 64 on the substrate, and a partial structure of the second gate line G2 is used to form the gate of the fourth transistor.
  • the orthographic projection of the enable signal line EM on the substrate covers the orthographic projection of the fifth active portion 65 on the substrate and the orthographic projection of the sixth active portion 66 on the substrate, and a partial structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively.
  • the orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projection of the seventh active portion 67 on the substrate, and a partial structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7.
  • the orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projection of the third active portion 63 on the substrate, and the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C.
  • the second gate line G2 in the pixel driving circuit of this row can be reused as the second reset signal line Re2 in the pixel driving circuit of the previous row. This setting can improve the integration of the pixel driving circuit and reduce the layout area of the pixel driving circuit.
  • the shading layer can be connected to a stable power supply terminal.
  • the shading layer can be connected to the first power supply terminal, the first initial signal terminal, the second initial signal terminal, etc. in FIG1.
  • the first shading portion 71 can stabilize the voltage of the first conductive portion 11, thereby reducing the voltage fluctuation of the gate of the driving transistor T3 during the light-emitting stage.
  • the display panel can use the first conductive layer as a mask to perform conductor processing on the first active layer, that is, the area covered by the first conductive layer in the first active layer can form a channel region of the transistor, and the area not covered by the first conductive layer forms a conductor structure.
  • the second conductive layer may include: a third reset signal line 2Re1, a third gate line 2G1, a plurality of second conductive portions 22, and a first connecting portion 21.
  • the third reset signal line 2Re1 can be used to provide the first reset signal terminal in Figure 1
  • the third gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 1.
  • the orthographic projection of the third reset signal line 2Re1 on the substrate substrate and the orthographic projection of the third gate line 2G1 on the substrate substrate can both extend along the first direction X.
  • the orthographic projection of the second conductive portion 22 on the substrate substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate substrate, and the second conductive portion 22 can be used to form a second electrode of the capacitor C, and the first connecting portion 21 is connected between two second conductive portions 22 in the same repeating unit. It should be understood that in other exemplary embodiments, in two adjacent repeating units in the first direction X, two adjacent second conductive portions can also be connected.
  • the second active layer may include a plurality of sub-active portions 8, the sub-active portions 8 include a first active portion 81, a second active portion 82, a fifteenth active portion 815, a sixteenth active portion 816 and a seventeenth active portion 817, the first active portion 81 may be used to form a channel region of the first transistor T1; the second active portion 82 may be used to form a channel region of the second transistor T2; the fifteenth active portion 815 is connected to an end of the first active portion 81 away from the second active portion 82, the sixteenth active portion 816 is connected to an end of the second active portion 82 away from the first active portion 81, and the seventeenth active portion 817 is connected between the first active portion 81 and the second active portion 82.
  • the second active layer may be formed of indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors.
  • the orthographic projection of the third gate line 2G1 on the substrate can cover the orthographic projection of the second active portion 82 on the substrate, and a partial structure of the third gate line 2G1 can be used to form the bottom gate of the second transistor.
  • the orthographic projection of the third reset signal line 2Re1 on the substrate can cover the orthographic projection of the first active portion 81 on the substrate, and a partial structure of the third reset signal line 2Re1 can be used to form the bottom gate of the first transistor T1.
  • the orthographic projection of the light shielding layer on the substrate can also cover the orthographic projection of the sub-active portion 8 on the substrate to reduce the influence of light on the characteristics of the first transistor and the second transistor.
  • the third conductive layer may include a first reset signal line 3Re1 and a first gate line 3G1.
  • the orthographic projection of the first reset signal line 3Re1 on the substrate and the orthographic projection of the first gate line 3G1 on the substrate may both extend along the first direction X.
  • the first reset signal line 3Re1 may be used to provide the first reset signal terminal in FIG.
  • the orthographic projection of the first reset signal line 3Re1 on the substrate may cover the orthographic projection of the first active portion 81 on the substrate, and a partial structure of the first reset signal line 3Re1 may be used to form the top gate of the first transistor T1, and at the same time, the first reset signal line 3Re1 may be connected to the third reset signal line 2Re1 through a via located in the edge wiring area of the display panel.
  • the first gate line 3G1 may be used to provide the first gate drive signal terminal in FIG.
  • the orthographic projection of the first gate line 3G1 on the substrate may cover the orthographic projection of the second active portion 82 on the substrate, and a partial structure of the first gate line 3G1 may be used to form the top gate of the second transistor T2, and at the same time, the first gate line 3G1 may be connected to the third gate line 2G1 through a via located in the edge wiring area of the display panel.
  • the first reset signal line 3Re1, the second gate line G2, the first gate line 3G1, the first conductive portion 11, the enable signal line EM and the second reset signal line Re2 are sequentially distributed in the second direction Y in the orthographic projection on the substrate.
  • the display panel can use the third conductive layer as a mask to perform conductor processing on the second active layer, that is, the area covered by the third conductive layer in the second active layer can form a channel region of the transistor, and the area not covered by the third conductive layer forms a conductor structure.
  • the fourth conductive layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a first initial signal line Vinit1, a second initial signal line Vinit2, and a first power connection line 4VDD.
  • the first bridge portion 41 can be connected to the seventeenth active portion 817 and the first conductive portion 11 through vias (black squares in the figure) to connect the first electrode of the second transistor T2 and the gate of the driving transistor T3.
  • An opening 221 may be formed on the second conductive portion 22, and the orthographic projection of the via connected between the first conductive portion 11 and the first bridge portion 41 on the substrate substrate is located on the orthographic projection of the opening 221 on the substrate substrate, so that the via connected between the first conductive portion 11 and the first bridge portion 41 is insulated from the second conductive portion 22.
  • the second bridge portion 42 can be connected to the eighth active portion through a via to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the size of the positive projection of the second bridge portion 42 on the substrate substrate in the first direction X is greater than the size of the positive projection of the second bridge portion 42 on the substrate substrate in the second direction Y, and the second bridge portion 42 and the first initial signal line Vinit1 and other signal lines can form a lateral parasitic capacitance to further increase the parasitic capacitance of the second pole of the sixth transistor.
  • the third bridge portion 43 can be connected to the sixteenth active portion 816 and the thirteenth active portion 613 through vias, respectively, to connect the second pole of the second transistor T2 and the second pole of the driving transistor T3.
  • the fourth bridge portion 44 can be connected to the tenth active portion 410 through a via to connect the first pole of the fourth transistor T4.
  • the positive projection of the first initial signal line Vinit1 on the substrate substrate extends along the first direction, and the first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 1.
  • the first initial signal line Vinit1 can be connected to the fifteenth active portion 815 through a via to connect the first pole of the first transistor T1.
  • the orthographic projection of the second initial signal line Vinit2 on the base substrate may extend along the first direction X, the second initial signal line Vinit2 may be the same as the second initial signal terminal provided in FIG. 1, and the second initial signal line Vinit2 may be connected to the twelfth active portion 612 through a via hole to connect the first electrode of the seventh transistor T7.
  • the orthographic projection of the first power connection line 4VDD on the base substrate may extend along the first direction X, and the first power connection line 4VDD may be connected to the first connection portion 21 and the eleventh active portion 611 through via holes to connect the first electrode of the fifth transistor T5 and the second electrode of the capacitor C.
  • the fifth conductive layer may include a first power line VDD, a data line Da, and a fifth bridge portion 55.
  • the fifth bridge portion 55 may be connected to the second bridge portion 42 through a via to connect the second electrode of the sixth transistor.
  • the positive projection of the first power line VDD on the substrate may extend along the second direction Y, and the first power line VDD is used to provide the first power signal terminal in FIG. 1.
  • the first power line VDD may include a first extension portion VDD1, a second extension portion VDD2, and a third extension portion VDD3, the second extension portion VDD2 is connected between the first extension portion VDD1 and the third extension portion VDD3, the size of the positive projection of the second extension portion VDD2 on the substrate in the first direction X may be greater than the size of the positive projection of the first extension portion VDD1 on the substrate in the first direction X, and the size of the positive projection of the second extension portion VDD2 on the substrate in the first direction X may be greater than the size of the positive projection of the third extension portion VDD3 on the substrate in the first direction X.
  • the second extensions VDD2 in the two adjacent first power lines VDD are connected, and the connected second extensions VDD2 are connected to the first power connection line 4VDD through one or more vias.
  • the first power line VDD and the first power connection line 4VDD can form a grid structure, and the power lines of the grid structure can reduce the voltage drop of the power signal thereon.
  • the orthographic projection of the second extension VDD2 on the substrate can cover the orthographic projection of the first active part 81 and the second active part 82 on the substrate, and the second extension VDD2 can reduce the influence of light on the characteristics of the first transistor and the second transistor.
  • the orthographic projection of the second extension VDD2 on the substrate can also cover the orthographic projection of the first bridge part 41 on the substrate, and the second extension VDD2 can stabilize and shield the first bridge part 41 to reduce the voltage fluctuation of the gate of the driving transistor T3 during the light-emitting stage.
  • the connected second extension portion VDD2 is connected to the first power connection line 4VDD through a via hole, and the first power connection line 4VDD can be connected to the first connection portion 21 through a via hole.
  • This arrangement can reduce the number of via holes, thereby saving the space occupied by the via holes.
  • the data line Da can be used to provide the data signal terminal in FIG1 , and the positive projection of the data line Da on the substrate can extend along the second direction Y.
  • the data line Da can be connected to the fourth bridge portion 44 through a via hole to connect the data signal terminal and the first electrode of the fourth transistor.
  • the electrode layer includes a plurality of electrode portions: a first electrode portion G, a second electrode portion B and a third electrode portion R, each of which can be connected to the fifth bridge portion 55 through a via hole to connect the second electrode of the sixth transistor.
  • a plurality of pixel openings PH are formed on the pixel defining layer, the pixel openings PH are arranged corresponding to the electrode portions, and the orthographic projection of the pixel openings PH on the base substrate coincides with the orthographic projection of the electrode portions on the base substrate.
  • the first electrode portion G can be used to form the electrode portion of the green light-emitting unit in the display panel
  • the second electrode portion B can be used to form the electrode portion of the blue light-emitting unit in the display panel
  • the third electrode portion R can be used to form the electrode portion of the red light-emitting unit.
  • the second electrode portion B, the first electrode portion G, the third electrode portion R, and the first electrode portion G are alternately distributed in the row direction X; in two adjacent columns of pixel driving circuits, the plurality of second electrode portions B and the plurality of third electrode portions R are connected to the same column of pixel driving circuits, and the second electrode portions B and the third electrode portions R connected to the same column of pixel driving circuits are alternately distributed in the column direction Y; the plurality of first electrode portions G are connected to another column of pixel driving circuits, and the first electrode portions G connected to the same column of pixel driving circuits are alternately distributed in the column direction.
  • the minimum distance S1 of the orthogonal projections of the two first electrode portions G connected to the adjacent rows of pixel driving circuits and the same column of pixel driving circuits on the substrate in the column direction is greater than the size S2 of the orthogonal projection of the third electrode portion R on the substrate in the column direction and/or the minimum distance S1 of the orthogonal projections of the two first electrode portions G connected to the adjacent rows of pixel driving circuits and the same column of pixel driving circuits on the substrate in the column direction is greater than the size S3 of the orthogonal projection of the second electrode portion B on the substrate in the column direction.
  • a first opening H1 may also be provided on the light shielding layer
  • the substrate may include a light-transmitting area
  • the light shielding structure of all functional layers including the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, the electrode layer, and the insulating layer between the above layers
  • the first opening H1 is located on the substrate substrate.
  • the positive projection is located in the light-transmitting area.
  • the optical signal located on one side of the display panel can be imaged on the other side of the display panel through the first opening H1, so that the display device using the display panel can realize fingerprint recognition, under-screen camera and other technologies.
  • the light shielding layer around the first opening H1 can reduce the influence of stray light formed by the light shielding structure between the substrate substrate and the pixel defining layer on the pinhole imaging effect.
  • the light shielding structure may refer to a structure with a transmittance of less than 50% in the stacking direction of the display panel.
  • the light shielding layer may further include a fourth light shielding portion 74, the fourth light shielding portion 74 and the repeating unit are arranged correspondingly, the fourth light shielding portion 74 is connected to the two second light shielding portions 72 in the repeating unit corresponding thereto, and the fourth light shielding portion 74 is connected to one end of the second light shielding portion 72 away from the first light shielding portion 71, and the first opening H1 is formed on the fourth light shielding portion 74.
  • the edge of the fourth light shielding portion 74 close to the second light shielding portion 72 may also form a lateral capacitor with the eighth active portion 68, thereby further increasing the parasitic capacitance of the second electrode of the sixth transistor T6.
  • the orthographic projection of the first opening H1 on the substrate can be located between the orthographic projections of the first reset signal line 3Re1 and the second gate line G2 on the substrate in the same pixel driving circuit.
  • the orthographic projection of the first opening H1 on the substrate is located between the orthographic projections of two adjacent data lines Da on the substrate in the same repeating unit.
  • the area of the orthographic projection of the first opening H1 on the substrate substrate may be smaller than the area of the orthographic projection of the first light shielding portion 71 on the substrate substrate.
  • the area of the orthographic projection of the first light shielding portion 71 on the substrate substrate may be 2-5 times the area of the orthographic projection of the first opening H1 on the substrate substrate.
  • the area of the orthographic projection of the first light shielding portion 71 on the substrate substrate may be 2 times, 3 times, 4 times, 5 times, etc., the area of the orthographic projection of the first opening H1 on the substrate substrate.
  • the pixel driving circuit can also be other structures, and accordingly, the layout structure of the display panel can also be other structures.
  • the layout structure of the display panel can also be other structures.
  • pinhole imaging can be achieved through the first opening located on the light-shielding layer, so that the display device using the display panel can realize fingerprint recognition, under-screen camera and other technologies.
  • the pixel defining layer PDL may be black, and a second opening H2 may be formed on the pixel defining layer, and the orthographic projection of the second opening H2 on the substrate may also be located in the light-transmitting area.
  • the second opening H2 and/or the first opening H1 may form a pinhole required for pinhole imaging.
  • the orthographic projection of the second opening H2 on the substrate and the orthographic projection of the first opening H1 on the substrate may overlap; or, the orthographic projection area of the second opening H2 on the substrate is larger than the orthographic projection area of the first opening H1 on the substrate, and the orthographic projection of the second opening H2 on the substrate covers the orthographic projection of the first opening H1 on the substrate; or, the orthographic projection area of the first opening H1 on the substrate is larger than the orthographic projection area of the second opening H2 on the substrate, and the orthographic projection of the first opening H1 on the substrate covers the orthographic projection of the second opening H2 on the substrate.
  • the display panel may further include a color filter layer located on the side of the pixel defining layer facing away from the base substrate, and the black matrix on the color filter layer may be formed with a third imaging hole, and one or more of the first opening, the second opening, and the third imaging hole may form a small hole required for pinhole imaging.
  • the black squares drawn on the side of the fourth conductive layer away from the base substrate indicate that the fourth conductive layer is connected to the via holes of other layers facing the base substrate; the black squares drawn on the side of the fifth conductive layer away from the base substrate indicate that the fifth conductive layer is connected to the via holes of other layers facing the base substrate; the black squares drawn on the side of the electrode layer away from the base substrate indicate that the electrode layer is connected to the via holes of other layers facing the base substrate.
  • the black squares indicate the positions of the via holes, and different via holes indicated by black squares at different positions may penetrate different insulating layers.
  • the display panel may further include a first buffer layer 92, a first insulating layer 93, a second insulating layer 94, a second buffer layer 95, a third insulating layer 96, a dielectric layer 97, a first flat layer 98, and a second flat layer 99.
  • the base substrate 91, the light shielding layer, the first buffer layer 92, the first active layer, the first insulating layer 93, the first conductive layer, the second insulating layer 94, the second conductive layer, the second buffer layer 95, the second active layer, the third insulating layer 96, the third conductive layer, the dielectric layer 97, the fourth conductive layer, the first flat layer 98, the fifth conductive layer, the second flat layer 99, the electrode layer, and the pixel defining layer PDL are stacked in sequence.
  • the first buffer layer 92 and the second buffer layer 95 may include one or more layers of silicon oxide and silicon nitride layers; the first insulating layer 93, the second insulating layer 94 and the third insulating layer 96 may include one or more layers of silicon oxide and silicon nitride layers; the dielectric layer 97 may include a silicon nitride layer; the materials of the first flat layer 98 and the second flat layer 99 may be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG) and the like.
  • PI polyimide
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • SOG silicon-glass bonding structure
  • the substrate 91 may include a glass substrate, a barrier layer and a polyimide layer stacked in sequence, and the barrier layer may be an inorganic material.
  • the materials of the first conductive layer, the second conductive layer and the third conductive layer may be one or an alloy of molybdenum, aluminum, copper, titanium and niobium, or a molybdenum/titanium alloy or a laminate, etc.
  • the materials of the fourth conductive layer and the fifth conductive layer may include metal materials, such as one or an alloy of molybdenum, aluminum, copper, titanium and niobium, or a molybdenum/titanium alloy or a laminate, etc., or a titanium/aluminum/titanium laminate.
  • the electrode layer may include an indium tin oxide layer and a silver layer.
  • the square resistance of any one of the first conductive layer, the second conductive layer and the third conductive layer may be greater than the square resistance of any one of the fourth conductive layer and the fifth conductive layer.
  • the proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the figure.
  • the drawings described in the present disclosure are only structural schematic diagrams.
  • the first, second and other qualifiers are only used to define different structural names, and they do not have a specific order and quantity.
  • the positive projection of a certain structure on the substrate substrate extends in a certain direction, which can be understood as the positive projection of the structure on the substrate substrate extending straight or bending along the direction.
  • a transistor refers to an element including at least three terminals: a gate, a drain and a source.
  • the transistor has a channel region between the drain (drain electrode terminal, a drain region or a drain electrode) and the source (source electrode terminal, a source region or a source electrode), and the current can flow through the drain, the channel region and the source.
  • the channel region refers to the area where the current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the gate electrode may also be referred to as a control electrode.
  • the display panel may include a display area AA, and the display area AA may include an optical signal acquisition area AA1 and a normal display area AA2 outside the optical signal acquisition area AA1.
  • the optical signal acquisition area AA1 may be in a circular, rectangular, triangular, polygonal or other shape.
  • the optical signal located on one side of the display panel can be imaged on the other side of the display panel through the first opening H1 located in the optical signal acquisition area AA1.
  • the optical signal acquisition area AA1 can be used as a fingerprint recognition area, an under-screen camera area, etc.
  • the layout structures in the optical signal collection area AA1 and the normal display area AA2 can be as shown in Figure 3.
  • the light shielding layers in the optical signal collection area AA1 and the normal display area AA2 have the same pattern shape, so that different areas of the display panel have the same parasitic capacitance distribution, and this setting can improve the display uniformity of the display panel.
  • the orthographic projections of the light shielding layer in the optical signal collection area AA1 and the normal display area AA2 on the substrate may have different pattern shapes.
  • Figure 23 is the layout structure of the light shielding layer in the optical signal collection area
  • Figure 24 is the layout structure of the light shielding layer in the normal display area.
  • the light shielding layer located in the optical signal collection area is arranged on the entire surface except for the first opening H1. This arrangement can make the first opening in the optical signal collection area have a better imaging effect.
  • the light shielding layer located in the normal display area may include: a first light shielding portion 71, a second connecting portion 752, and a third connecting portion 753, wherein the orthographic projection of the second connecting portion 752 on the substrate extends along the first direction X and is connected between the first light shielding portions 71 adjacent to each other in the first direction X; the orthographic projection of the third connecting portion 753 on the substrate extends along the second direction Y and is connected between the first light shielding portions 71 adjacent to each other in the second direction Y.
  • the ratio of the orthographic projection area of the hollow structure of the light shielding layer on the substrate substrate to the orthographic projection area of its physical structure on the substrate substrate in the normal display area is K1
  • the ratio of the orthographic projection area of the hollow structure of the light shielding layer on the substrate substrate to the orthographic projection area of its physical structure on the substrate substrate in the optical signal collection area is K2, wherein K1 may be greater than K2.
  • FIG. 25 another layout structure of the light shielding layer in the optical signal acquisition area is shown.
  • a plurality of first openings B1 are formed on the light shielding layer in the optical signal acquisition area.
  • the first openings B1 are arranged corresponding to the active portion for forming the transistor channel region in the display panel.
  • the orthographic projection of the first opening B1 on the substrate covers the orthographic projection of the corresponding active portion on the substrate.
  • the active portion for forming the transistor channel region may include a first active portion 81, a second active portion 82, a third active portion 63, a fourth active portion 64, a fifth active portion 65, a sixth active portion 66, and a seventh active portion 67.
  • the light shielding layer may also be located at any other position between the substrate and the pixel defining layer.
  • the light shielding layer may be located at the conductive layer where the fan-out line added in the FIP (Fanout In Panel) technology is located.
  • FIG26 it is a schematic diagram of the structure of another exemplary embodiment of the display panel disclosed in the present invention, and the display panel includes a display area AA, and the display area AA includes a fan-out area AA3, an optical signal collection area AA1, and other display areas AA4 located outside the fan-out area AA3 and the optical signal collection area AA1.
  • the display panel may include a plurality of data lines Da, a plurality of first data fan-out lines Fa1, and a plurality of second data fan-out lines Fa2, wherein the plurality of data lines Da are located in the display area AA, and the orthographic projections of the data lines Da on the substrate are spaced along the first direction X and extend along the second direction Y; the plurality of first data fan-out lines Fa1 are located in the fan-out area AA3, and the orthographic projections of the first data fan-out lines Fa1 on the substrate are spaced along the second direction Y and extend along the first direction X, and the first data fan-out lines Fa1 are arranged correspondingly to the data lines Da, and the first data fan-out lines Fa1 are connected to the corresponding data lines Da; the plurality of second data fan-out lines Fa2 are located in the fan-out area AA3, and the orthographic projections of the second data fan-out lines Fa2 on the substrate are spaced along the first direction X and extend along the second direction Y, and
  • the first data fan-out lines Fa1 may be located in the light shielding layer.
  • the data line Da and the second data fan-out line Fa2 may be located in the fifth conductive layer, and the first data fan-out line Fa1 may be located in the sixth conductive layer added between the fifth conductive layer and the pixel defining layer.
  • the layout structure of the light shielding layer in the optical signal acquisition area AA1 can be the same as the structure shown in FIG23 or FIG25.
  • the layout structure of the light shielding layer in the other display area AA4 in the display panel shown in FIG26 is shown.
  • the light shielding layer located in the other display area AA4 can include a plurality of second power lines VSS, and the orthographic projections of some second power lines VSS on the substrate can extend along the first direction X, and the orthographic projections of some second power lines VSS on the substrate can extend along the second direction Y.
  • the second power lines extending in different directions can intersect to form a grid structure, and the second power lines VSS forming the grid structure can be connected to the common electrode layer through vias, thereby reducing the voltage drop of the signal on the common electrode layer.
  • the common electrode layer is located on the side of the pixel defining layer away from the substrate, and the common electrode layer is used to form the second electrode of the light-emitting unit.
  • the second power lines of the light shielding layer located in the other display area AA4 can also extend in the same direction.
  • the shading layer located in other display areas AA4 may also include other signal lines.
  • the shading layer located in other display areas AA4 may also include a second signal line.
  • the second signal line may intersect with the orthographic projection of the first signal line located in a different conductive layer on the substrate, and the second signal line may be connected to the first signal line intersecting with it through a via, and the second signal line may form a grid structure with the first signal line to reduce the voltage drop of the signal on the first signal line.
  • the first signal line may include one or more of the first initial signal line, the second initial signal line, and the first power line. It should be noted that the shading layer located in other display areas AA4 may include a second signal line and a second power line at the same time.
  • This exemplary embodiment also provides a display device, which includes the above-mentioned display panel.
  • the display device can be a display device such as a mobile phone, a tablet computer, a television, etc.

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Abstract

一种显示面板及显示装置，显示面板包括发光单元(OLED)，显示面板还包括:衬底基板(91)、遮光层、像素界定层(PDL)、多层功能层。衬底基板(91)包括透光区；遮光层位于衬底基板(91)的一侧，遮光层具有遮光作用；像素界定层(PDL)位于遮光层背离衬底基板(91)的一侧，像素界定层(PDL)上形成有像素开口(PH)，像素开口(PH)内用于形成发光单元(OLED)；多层功能层位于衬底基板(91)和像素界定层(PDL)之间，位于衬底基板(91)和像素界定层(PDL)之间的所有功能层的遮光结构在衬底基板(91)上的正投影位于透光区以外；遮光层上形成有第一开孔(H1)，第一开孔(H1)在衬底基板(91)上的正投影位于透光区。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
在高像素密度的显示面板中，显示面板的透光率较小，从而显示面板无法满足指纹识别、屏下摄像头等技术的透光要求。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种显示面板，所述显示面板包括发光单元，所述显示面板还包括：衬底基板、遮光层、像素界定层、多层功能层。所述衬底基板包括透光区；遮光层位于所述衬底基板的一侧，所述遮光层具有遮光作用；像素界定层位于所述遮光层背离所述衬底基板的一侧，所述像素界定层上形成有像素开口，所述像素开口内用于形成所述发光单元；多层功能层位于所述衬底基板和所述像素界定层之间，位于所述衬底基板和所述像素界定层之间的所有功能层的遮光结构在所述衬底基板上的正投影位于所述透光区以外；所述遮光层上形成有第一开孔，所述第一开孔在所述衬底基板上的正投影位于所述透光区。
本公开一种示例性实施例中，所述显示面板还包括用于驱动所述发光单元的像素驱动电路，所述像素驱动电路包括驱动晶体管；多层功能层中包括：第一有源层，所述第一有源层包括第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区；所述遮光层位于所述第一有源层和所述衬底基板之间，所述遮光层包括第一遮光部，所述第一遮光部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影。
本公开一种示例性实施例中，所述像素驱动电路还包括第一晶体管、 第四晶体管，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；所述显示面板还包括：第一复位信号线、第二栅线，所述第一复位信号线在所述衬底基板上的正投影沿第一方向延伸，所述第一复位信号线的部分结构用于形成所述第一晶体管的顶栅；所述第二栅线在所述衬底基板上的正投影沿所述第一方向延伸，所述第二栅线的部分结构用于形成所述第四晶体管的栅极；其中，所述第一开孔在所述衬底基板上的正投影位于同一像素驱动电路中所述第一复位信号线和所述第二栅线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述显示面板包括多个重复单元，多个所述重复单元在第一方向和第二方向上阵列分布，所述第一方向和所述第二方向相交；所述重复单元包括在所述第一方向上分布的两个像素驱动电路，同一所述重复单元中两个所述像素驱动电路镜像对称设置。
本公开一种示例性实施例中，所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；所述数据线在所述衬底基板上的正投影沿所述第二方向延伸，所述第一开孔在所述衬底基板上的正投影位于同一所述重复单元中相邻两数据线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述像素驱动电路还包括第六晶体管、第七晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述发光单元的第一电极，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极；所述第一有源层还包括：第六有源部、第七有源部、第八有源部，第六有源部用于形成所述第六晶体管的沟道区；第七有源部用于形成所述第七晶体管的沟道区；第八有源部连接于所述第六有源部和所述第七有源部之间；所述遮光层还包括：第二遮光部，所述第二遮光部连接于第一遮光部；其中，所述第八有源部在所述衬底基板上的正投影和所述第二遮光部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述第八有源部在所述衬底基板上的正 投影沿第一方向延伸，所述第八有源部在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第八有源部在所述衬底基板上的正投影在第二方向上的尺寸；所述第二遮光部在所述衬底基板上的正投影沿所述第一方向延伸，所述第二遮光部在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第二遮光部在所述衬底基板上的正投影在所述第二方向上的尺寸；所述第一方向和所述第二方向相交。
本公开一种示例性实施例中，所述遮光层还包括：第三遮光部，第三遮光部在所述衬底基板上的正投影沿第二方向延伸，所述第三遮光部连接于所述第一遮光部和所述第二遮光部之间；所述第二遮光部包括第一子遮光部和第二子遮光部，在第一方向上，所述第一子遮光部和第二子遮光部在所述衬底基板上的正投影位于所述第三遮光部在所述衬底基板上的正投影的两侧；所述第一子遮光部在所述衬底基板上的正投影和所述第八有源部在所述衬底基板上的正投影至少部分交叠，所述第二子遮光部在所述衬底基板上的正投影和所述第八有源部在所述衬底基板上的正投影至少部分交叠；所述第一有源层还包括：第九有源部，所述第九有源部在所述衬底基板上的正投影沿所述第二方向延伸，所述第九有源部连接于所述第八有源部和所述第七有源部之间；所述第八有源部包括第一子有源部和第二子有源部，在所述第一方向上，所述第一子有源部和第二子有源部在所述衬底基板上的正投影位于所述第九有源部在所述衬底基板上的正投影的两侧；所述第一子有源部在所述衬底基板上的正投影和所述第二遮光部在所述衬底基板上的正投影至少部分交叠，所述第二子有源部在所述衬底基板上的正投影和所述第二遮光部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述显示面板包括多个重复单元，多个所述重复单元在第一方向和第二方向上阵列分布，所述第一方向和所述第二方向相交；所述重复单元包括在所述第一方向上分布的两个像素驱动电路，同一所述重复单元中两个所述像素驱动电路镜像对称设置；所述第一遮光层还包括：第四遮光部，所述第四遮光部和所述重复单元对应设置，所述第四遮光部连接与其对应的所述重复单元中的两所述第二遮光部，且第四遮光部连接于所述第二遮光部远离所述第一遮光部的一端，所述第一 开孔形成于所述第四遮光部上。
本公开一种示例性实施例中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极；多层功能层中还包括：第一导电层、第四导电层，第一导电层位于所述第一有源层和所述像素界定层之间，所述第一导电层包括第一导电部，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极；第四导电层位于所述第一导电层和所述像素界定层之间，所述第四导电层包括第一桥接部和第二桥接部；其中，所述第一桥接部连接所述第二晶体管的第一极，且所述第一桥接部通过过孔连接所述第一导电部，所述第二桥接部通过过孔连接所述第八有源部，且所述第二桥接部在所述衬底基板上的正投影在第一方向上的尺寸大于所述第二桥接部在所述衬底基板上的正投影在第二方向上的尺寸。
本公开一种示例性实施例中，所述第一开孔在所述衬底基板上的正投影的面积小于所述第一遮光部在所述衬底基板上的正投影的面积。
本公开一种示例性实施例中，所述像素驱动电路还包括第一晶体管、第二晶体管，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极；多层功能层中还包括：第一导电层、第四导电层，第一导电层位于所述第一有源层和所述像素界定层之间，所述第一导电层包括第一导电部，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极；第四导电层位于所述第一导电层和所述像素界定层之间，所述第四导电层包括第一桥接部和所述第一初始信号线，所述第一初始信号线在所述衬底基板上的正投影沿第一方向延伸；所述第一桥接部连接所述第二晶体管的第一极，且所述第一桥接部通过过孔连接所述第一导电部。
本公开一种示例性实施例中，所述像素驱动电路还包括电容，所述电容的第一电极连接所述驱动晶体管的栅极，所述电容的第二电极连接第一电源线；多层功能层中还包括：第一导电层、第二导电层、第四导电层、 第五导电层，第一导电层位于所述第一有源层和所述像素界定层之间，所述第一导电层包括第一导电部，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极和所述电容的第一电极；第二导电层位于所述第一导电层和所述像素界定层之间，所述第二导电层包括第二导电部和第一连接部，所述第二导电部在所述衬底基板上的正投影和所述第一导电部在所述衬底基板上的正投影至少部分交叠，所述第二导电部用于形成所述电容的第二电极，所述第一连接部连接于同一所述重复单元中两所述第二导电部之间；第四导电层位于所述第二导电层和所述像素界定层之间，所述第四导电层包括第一电源连接线，所述第一电源连接线在所述衬底基板上的正投影沿第一方向延伸且所述第一电源连接线通过过孔连接所述第一连接部；第五导电层位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包括所述第一电源线，在所述第一方向上相邻的两所述重复单元中，相邻两所述第一电源线相连接，且相连接两所述第一电源线通过过孔连接所述第一电源连接线。
本公开一种示例性实施例中，所述像素界定层为黑色，所述像素界定层上还形成有第二开孔，所述第二开孔在所述衬底基板上的正投影位于所述透光区；所述第二开孔在所述衬底基板上的正投影和所述第一开孔在所述衬底基板上的正投影重合；或，第二开孔在所述衬底基板上的正投影面积大于所述第一开孔在所述衬底基板上的正投影面积，所述第二开孔在所述衬底基板上的正投影覆盖所述第一开孔在所述衬底基板上的正投影；或，第一开孔在所述衬底基板上的正投影面积大于所述第二开孔在所述衬底基板上的正投影面积，所述第一开孔在所述衬底基板上的正投影覆盖所述第二开孔在所述衬底基板上的正投影。
本公开一种示例性实施例中，所述显示面板包括显示区，所述显示区包括光信号采集区，至少所述光信号采集区中的所述遮光层设置有所述第一开孔。
本公开一种示例性实施例中，所述显示区还包括位于所述光信号采集区以外的正常显示区；位于所述光信号采集区的所述遮光层在所述衬底基板上的正投影和位于所述正常显示区的所述遮光层在所述衬底基板上的 正投影具有不同的图案形状。
本公开一种示例性实施例中，所述显示区还包括所述光信号采集区以外的正常显示区，所述正常显示区中的所述遮光层也设置有所述第一开孔；位于所述光信号采集区的所述遮光层在所述衬底基板上的正投影和位于所述正常显示区的所述遮光层在所述衬底基板上的正投影具有相同的图案形状。
本公开一种示例性实施例中，位于所述光信号采集区的所述遮光层除了所述第一开孔以外整面设置。
本公开一种示例性实施例中，所述像素驱动电路还包括多个开关晶体管；所述第一有源层还包括：多个有源部，所述有源部用于形成所述开关晶体管的沟道区；其中，位于所述光信号采集区的所述遮光层上还形成有多个第一开口，所述第一开口和所述有源部对应设置，所述第一开口在所述衬底基板上的正投影覆盖与其对应的所述有源部在所述衬底基板上的正投影。
本公开一种示例性实施例中，位于所述正常显示区的所述遮光层还包括：多条第二连接部、多条第三连接部，第二连接部在所述衬底基板上的正投影沿第一方向延伸，且连接于在所述第一方向上相邻的所述第一遮光部之间；第三连接部在所述衬底基板上的正投影沿第二方向延伸，且连接于在所述第二方向上相邻的所述第一遮光部之间，所述第一方向和所述第二方向相交。
本公开一种示例性实施例中，所述显示面板还包括显示区，所述显示区包括扇出区和光信号采集区；所述显示面板还包括：多条数据线、多条第一数据扇出线、多条第二数据扇出线，多条数据线位于所述显示区，所述数据线在所述衬底基板上的正投影沿第一方向间隔分布且沿第二方向延伸，所述第一方向和所述第二方向相交；多条第一数据扇出线位于所述扇出区，所述第一数据扇出线在所述衬底基板上的正投影沿所述第二方向间隔分布且沿所述第一方向延伸，所述第一数据扇出线与所述数据线对应设置，所述第一数据扇出线连接与其对应的所述数据线；多条第二数据扇出线位于所述扇出区，所述第二数据扇出线在所述衬底基板上的正投影沿所述第一方向间隔分布且沿所述第二方向延伸，所述第二数据扇出线与所 述第一数据扇出线对应设置，所述第二数据扇出线连接与其对应的所述第一数据扇出线；所述第一数据扇出线位于所述遮光层。
本公开一种示例性实施例中，多层所述功能层中还包括：第五导电层，第五导电层位于所述衬底基板和所述像素界定层之间，所述第五导电层包括所述数据线；所述遮光层位于所述第五导电层和所述像素界定层之间。
本公开一种示例性实施例中，所述显示区还包括位于所述扇出区和光信号采集区以外的其他显示区；所述显示面板还包括：多条第一信号线，多条第一信号线位于所述遮光层以外的导电层；位于所述其他显示区的所述遮光层包括多条第二信号线，所述第一信号线在所述衬底基板上的正投影和所述第二信号线在所述衬底基板上的正投影相交，且所述第二信号线通过过孔连接与其相交的所述第一信号线。
本公开一种示例性实施例中，所述显示面板还包括像素驱动电路，所述像素驱动电路包括驱动晶体管、第一晶体管、第五晶体管、第七晶体管；所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第五晶体管的第一极连接第一电源线，所述第五晶体管的第二极连接所述驱动晶体管的第一极，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极；多条第一信号线中包括所述第一初始信号线、第二初始信号线、第一电源线中的一种或多种。
本公开一种示例性实施例中，所述显示区还包括位于所述扇出区和光信号采集区以外的其他显示区；所述显示面板还包括：公共电极层，公共电极层位于所述像素界定层背离所述衬底基板的一侧，所述公共电极层用于形成所述发光单元的第二电极；位于所述其他显示区的所述遮光层包括多条第二电源线，所述第二电源线连接所述公共电极层。
本公开一种示例性实施例中，部分所述第二电源线在所述衬底基板上的正投影沿所述第一方向延伸，部分所述第二电源线在所述衬底基板上的正投影沿所述第二方向延伸，且延伸方向不同的所述第二电源线相交。
本公开一种示例性实施例中，所述显示面板还包括像素驱动电路，所述像素驱动电路用于驱动所述发光单元发光，所述像素驱动电路包括：驱动晶体管、第一晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶 体管、第七晶体管、电容，第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极；第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极；第五晶体管的第一极连接第一电源线，第二极连接所述驱动晶体管的第一极；第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极；第七晶体管的第一极连接第二初始信号线，第二极连接所述发光单元的第一电极；电容的第一电极连接所述驱动晶体管的栅极，第二电极连接所述第一电源线；所述第一晶体管、第二晶体管为N型晶体管，所述驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管为P型晶体管。
本公开一种示例性实施例中，多层功能层中包括：第一有源层、第一导电层、第二有源层、第三导电层。第一有源层位于所述衬底基板和所述像素界定层之间，所述第一有源层包括：第三有源部、第四有源部、第五有源部、第六有源部、第七有源部；其中，所述第三有源部用于形成所述驱动晶体管的沟道区，所述第四有源部用于形成所述第四晶体管的沟道区，所述第五有源部用于形成所述第五晶体管的沟道区，所述第六有源部用于形成所述第六晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区；第一导电层位于所述第一有源层和所述像素界定层之间，所述第一导电层包括：第二复位信号线、第二栅线、使能信号线、第一导电部，所述第二复位信号线、第二栅线、使能信号线在所述衬底基板上的正投影沿第一方向延伸；其中，所述第一导电部用于形成所述驱动晶体管的栅极和所述电容的第一电极，所述第二栅线的部分结构用于形成所述第四晶体管的栅极，所述第二复位信号线的部分结构用于形成所述第七晶体管的栅极，所述使能信号线的部分结构用于分别形成所述第五晶体管和所述第六晶体管的栅极；第二有源层位于所述第一导电层和所述像素界定层之间，所述第二有源层包括第一有源部和第二有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第二有源部用于形成所述第二晶体管的沟道区；第三导电层位于所述第二有源层和所述像素界定层之间，所述第三导电层包括：所述第一栅线、第一复位信号线，所述第一栅线、第一复位信号线在所述衬底基板上的正投影沿所述第一方向延伸；所述第一栅线的 部分结构用于形成所述第二晶体管的顶栅，所述第一复位信号线的部分结构用于形成所述第一晶体管的顶栅。
本公开一种示例性实施例中，在同一像素驱动电路中，所述第一复位信号线、第二栅线、第一栅线、第一导电部、使能信号线、第二复位信号线在所述衬底基板上的正投影在第二方向上依次分布，所述第一方向和所述第二方向相交；本行像素驱动电路中所述第二栅线复用为上一行像素驱动电路中的所述第二复位信号线。
本公开一种示例性实施例中，所述显示面板还包括像素驱动电路，所述像素驱动电路用于驱动所述发光单元发光；多层功能层中还包括：电极层，所述电极层包括多个电极部，所述电极部用于形成所述发光单元的第一电极，多个所述电极部中包括第一电极部、第二电极部、第三电极部；在连接于同一行像素驱动电路的多个电极部中，第二电极部、第一电极部、第三电极部、第一电极部在行方向上依次交替分布；在相邻两列像素驱动电路中，多个第二电极部、多个第三电极部连接于同一列像素驱动电路，且连接于同一列像素驱动电路的第二电极部和第三电极部在列方向上依次交替分布，多个第一电极部连接于另一列像素驱动电路，连接于同一列像素驱动电路中的第一电极部在列方向上间隔分布。
本公开一种示例性实施例中，所述第一开孔用于将所述显示面板一侧的光信号小孔成像于所述显示面板的另一侧。
根据本公开的一个方面，提供一种显示面板，其中，所述显示面板包括：衬底基板、遮光层、遮光层，遮光层位于所述衬底基板的一侧，所述遮光层具有遮光作用；多层功能层位于所述衬底基板的一侧；其中，所述遮光层上形成有第一开孔，所述第一开孔在所述衬底基板上的正投影和所述功能层中遮光结构在所述衬底基板上的正投影不交叠，且所述遮光层在衬底基板上的正投影和至少一层所述功能层中遮光结构在所述衬底基板上的正投影交叠。
本公开一种示例性实施例中，所述显示面板还包括发光单元和用于驱动所述发光单元的像素驱动电路，所述像素驱动电路包括驱动晶体管；多层功能层中包括：第一有源层，所述第一有源层包括第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区；所述遮光层位于所述第一有 源层和所述衬底基板之间，所述遮光层包括第一遮光部，所述第一遮光部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影。所述像素驱动电路还包括第一晶体管、第四晶体管，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；所述显示面板还包括：第一复位信号线、第二栅线，所述第一复位信号线在所述衬底基板上的正投影沿第一方向延伸，所述第一复位信号线的部分结构用于形成所述第一晶体管的顶栅；所述第二栅线在所述衬底基板上的正投影沿所述第一方向延伸，所述第二栅线的部分结构用于形成所述第四晶体管的栅极；其中，所述第一开孔在所述衬底基板上的正投影位于同一像素驱动电路中所述第一复位信号线和所述第二栅线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述显示面板还包括显示区，所述显示区包括扇出区和光信号采集区；所述显示面板还包括：多条数据线、多条第一数据扇出线、多条第二数据扇出线，多条数据线位于所述显示区，所述数据线在所述衬底基板上的正投影沿第一方向间隔分布且沿第二方向延伸，所述第一方向和所述第二方向相交；多条第一数据扇出线位于所述扇出区，所述第一数据扇出线在所述衬底基板上的正投影沿所述第二方向间隔分布且沿所述第一方向延伸，所述第一数据扇出线与所述数据线对应设置，所述第一数据扇出线连接与其对应的所述数据线；多条第二数据扇出线位于所述扇出区，所述第二数据扇出线在所述衬底基板上的正投影沿所述第一方向间隔分布且沿所述第二方向延伸，所述第二数据扇出线与所述第一数据扇出线对应设置，所述第二数据扇出线连接与其对应的所述第一数据扇出线；所述第一数据扇出线位于所述遮光层。
根据本公开的一个方面，提供一种显示装置，其中，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中像素驱动电路的电路结构示意图；
图2为图1中像素驱动电路一种驱动方法中各节点的时序图；
图3为本公开显示面板一种示例性实施例中的结构版图；
图4为图3中遮光层的结构版图；
图5为图3中第一有源层的结构版图；
图6为图3中第一导电层的结构版图；
图7为图3中第二导电层的结构版图；
图8为图3中第二有源层的结构版图；
图9为图3中第三导电层的结构版图；
图10为图3中第四导电层的结构版图；
图11为图3中第五导电层的结构版图；
图12为图3中电极层和像素界定层的结构版图；
图13为图3中像素界定层的结构版图；
图14为图3中遮光层、第一有源层的结构版图；
图15为图3中遮光层、第一有源层、第一导电层的结构版图；
图16为图3中遮光层、第一有源层、第一导电层、第二导电层的结构版图；
图17为图3中遮光层、第一有源层、第一导电层、第二导电层、第二有源层的结构版图；
图18为图3中遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层的结构版图；
图19为图3中遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图；
图20为图3中遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层的结构版图；
图21为图3所示显示面板沿虚线AA剖开的部分剖视图；
图22为本公开显示面板另一种示例性实施例的结构示意图；
图23为光信号采集区中遮光层的版图结构；
图24为正常显示区中遮光层的版图结构；
图25为光信号采集区中遮光层的另一种版图结构；
图26为本公开显示面板另一种示例性实施例的结构示意图；
图27为图26所示显示面板中其他显示区中遮光层的版图结构。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为相关技术中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：驱动晶体管T3、第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第一极，栅极连接第二栅极驱动信号端G2；第五晶体管T5的第一极连接第一电源端VDD，第二极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；驱动晶体管T3的栅极连接节点N；第二晶体管T2的第一极连接节点N，第二极连接驱动晶体管T3的第二极，栅极连接第一栅极驱动信号端G1；第六晶体管T6的第一极连接驱动晶体管T3的第二极，第二极连接第七晶体管T7的第一极，栅极连接使能信号端EM，第七晶体管T7的第二极连接第二初始信号端Vinit2，栅极连接第二复位信号端Re2；第一晶体管T1的第一极连接节点N，第二极连接第一初始信号端Vinit1， 栅极连接第一复位信号端Re1；电容C的第一电极连接节点N，第二电极连接第一电源端VDD。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间。其中，第一晶体管T1和第二晶体管T2可以为N型晶体管，例如，第一晶体管T1和第二晶体管T2可以为N型金属氧化物晶体管，N型晶体管具有较小的漏电流，从而可以降低发光阶段，节点N通过第一晶体管T1和第二晶体管T2的漏电流。同时，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型晶体管，例如，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型低温多晶体硅晶体管，P型低温多晶体硅晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板。第一初始信号端和第二初始信号端可以根据实际情况输出相同或不同电压信号。
如图2所示，为图1中像素驱动电路一种驱动方法中各节点的时序图。其中，G1表示第一栅极驱动信号端G1的时序，G2表示第二栅极驱动信号端G2的时序，Re1表示第一复位信号端Re1的时序，Re2表示第二复位信号端Re2的时序，EM表示使能信号端EM的时序。该像素驱动电路的驱动方法可以包括第一复位阶段t1、补偿阶段t2，第二复位阶段t3、发光阶段t4。在第一复位阶段t1：第一复位信号端Re1输出高电平信号，第一晶体管T1导通，第一初始信号端Vinit1向节点N输入初始信号。在补偿阶段t2：第一栅极驱动信号端G1输出高电平信号，第二栅极驱动信号端G2输出低电平信号，第四晶体管T4、第二晶体管T2导通，同时数据信号端Da输出数据信号以向节点N写入电压Vdata+Vth，其中Vdata为数据信号的电压，Vth为驱动晶体管T3的阈值电压，在第二复位阶段t3，第二复位信号端Re2输出低电平信号，第七晶体管T7导通，第二初始信号端Vinit2向第六晶体管T6的第二极输入初始信号。发光阶段t4：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的电压Vdata+Vth作用下发光。
驱动晶体管输出电流公式如下：
I＝(μWCox/2L)(Vgs-Vth) 2
其中，I为驱动晶体管输出电流；μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。
根据上述驱动晶体管输出电流公式，将本公开像素驱动电路中驱动晶体管的栅极电压Vdata+Vth和源极电压Vdd带入上述公式可以得到：本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
本示例性实施例提供一种显示面板，该显示面板可以包括依次层叠设置的衬底基板、遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层、电极层、像素界定层，其中，上述相邻导电层之间可以设置有绝缘层。
如图3-20所示，图3为本公开显示面板一种示例性实施例中的结构版图，图4为图3中遮光层的结构版图，图5为图3中第一有源层的结构版图，图6为图3中第一导电层的结构版图，图7为图3中第二导电层的结构版图，图8为图3中第二有源层的结构版图，图9为图3中第三导电层的结构版图，图10为图3中第四导电层的结构版图，图11为图3中第五导电层的结构版图，图12为图3中电极层和像素界定层的结构版图，图13为图3中像素界定层的结构版图，图14为图3中遮光层、第一有源层的结构版图，图15为图3中遮光层、第一有源层、第一导电层的结构版图，图16为图3中遮光层、第一有源层、第一导电层、第二导电层的结构版图，图17为图3中遮光层、第一有源层、第一导电层、第二导电层、第二有源层的结构版图，图18为图3中遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层的结构版图，图19为图3中遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图，图20为图3中遮光层、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层的结构版图。该显示面板可以包括多个图1所示的像素驱动电路。如图20所示，多个像素驱动电路中可以包括在第一方向X上相邻分布第一像素驱动电路Pix1和第二像素驱动电路Pix2，第一像素驱动电路Pix1 和第二像素驱动电路Pix2可以镜像对称设置。其中，第一像素驱动电路Pix1和第二像素驱动电路Pix2可以形成一重复单元，该显示面板可以包括在第一方向X和第二方向Y上阵列分布的多个重复单元。其中，第一方向X和第二方向Y可以相交，例如，第一方向可以为行方向，第二方向可以为列方向。
如图3、图4、图14所示，遮光层可以包括多个第一遮光部71，第一遮光部71在第一方向X和第二方向Y上阵列分布，且在第一方向X上相邻的第一遮光部71相连接，在第二方向Y上相邻的第一遮光部71相连接。
如图3、5、15所示，第一有源层可以包括第三有源部63、第四有源部64、第五有源部65、第六有源部66、第七有源部67、第八有源部68、第九有源部69、第十有源部610、第十一有源部611、第十二有源部612、第十三有源部613。其中，第三有源部63可以用于形成驱动晶体管T3的沟道区；第四有源部64可以用于形成第四晶体管T4的沟道区；第五有源部65可以用于形成第五晶体管T5的沟道区；第六有源部66可以用于形成第六晶体管T6的沟道区；第七有源部67可以用于形成第七晶体管T7的沟道区；第八有源部68连接于第六有源部66和第七有源部67之间，第八有源部68在衬底基板上的正投影沿第一方向X延伸，且第八有源部68在衬底基板上的正投影在第一方向X上的尺寸大于第八有源部68在衬底基板上的正投影在第二方向Y上的尺寸；第九有源部69连接于第八有源部68和第七有源部67之间，第九有源部69在衬底基板上的正投影沿第二方向Y延伸；第十有源部610连接于第四有源部64远离第三有源部63的一端；第十一有源部611连接于第五有源部65远离第三有源部63的一端，同一重复单元中，两第十一有源部611可以相连接；第十二有源部612连接于第七有源部67远离第六有源部66的一端；第十三有源部613连接于第三有源部63和第六有源部66之间。第一有源层可以由多晶硅材料形成，相应的，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型的低温多晶硅薄膜晶体管。
如图14、15所示，第一遮光部71在衬底基板上的正投影覆盖第三有源部63在衬底基板上的正投影，第一遮光部71可以对第三有源部63起到遮光作用，以降低光线对驱动晶体管T3的特性影响。如图4所示，遮 光层还可以包括第二遮光部72、第三遮光部73，第三遮光部73在所述衬底基板上的正投影沿第二方向Y延伸，第三遮光部73连接于所述第一遮光部71和所述第二遮光部72之间。第二遮光部72在衬底基板上的正投影和第八有源部68在衬底基板上的正投影至少部分交叠，第二遮光部72和第八有源部68可以形成寄生电容，即该设置可以提高图1中第六晶体管T6第二极的寄生电容，从而改善低灰阶下显示面板发红的问题。其中，第二遮光部72可以包括第一子遮光部721和第二子遮光部722，在第一方向X上，所述第一子遮光部721和第二子遮光部722在所述衬底基板上的正投影位于所述第三遮光部73在所述衬底基板上的正投影的两侧；第一子遮光部721在所述衬底基板上的正投影和所述第八有源部68在所述衬底基板上的正投影至少部分交叠，第二子遮光部722在所述衬底基板上的正投影和所述第八有源部68在所述衬底基板上的正投影至少部分交叠。如图5所示，第八有源部68可以包括第一子有源部681和第二子有源部682，在第一方向X上，所述第一子有源部681和第二子有源部682在所述衬底基板上的正投影位于所述第九有源部69在所述衬底基板上的正投影的两侧；第一子有源部681在所述衬底基板上的正投影和所述第二遮光部72在所述衬底基板上的正投影至少部分交叠，第二子有源部682在所述衬底基板上的正投影和第二遮光部72在所述衬底基板上的正投影至少部分交叠。
如图3、6、15所示，第一导电层可以包括：第一导电部11、第二栅线G2、使能信号线EM、第二复位信号线Re2。第二栅线G2可以用于提供图1中第二栅极驱动信号端；使能信号线EM可以用于提供图1中的使能信号端；第二复位信号线Re2可以用于提供图1中的第二复位信号端。第二栅线G2在衬底基板上的正投影、使能信号线EM在衬底基板上的正投影、第二复位信号线Re2在衬底基板上的正投影均可以沿第一方向X延伸。其中，第二栅线G2在衬底基板上的正投影覆盖第四有源部64在衬底基板上的正投影，第二栅线G2的部分结构用于形成第四晶体管的栅极。使能信号线EM在衬底基板上的正投影覆盖第五有源部65在衬底基板上的正投影、第六有源部66在衬底基板上的正投影，使能信号线EM的部分结构可以分别用于形成第五晶体管T5、第六晶体管T6的栅极。第二复位信号线Re2 在衬底基板上的正投影可以覆盖第七有源部67在衬底基板上的正投影，第二复位信号线Re2的部分结构可以用于形成第七晶体管T7的栅极。第一导电部11在衬底基板上的正投影覆盖第三有源部63在衬底基板上的正投影，第一导电部11可以用于形成驱动晶体管T3的栅极和电容C的第一电极。如图15所示，本行像素驱动电路中的第二栅线G2可以复用为上一行像素驱动电路中的第二复位信号线Re2。该设置可以提高像素驱动电路的集成度，降低像素驱动电路的布图面积。遮光层可以连接一稳定电源端，例如，遮光层可以连接图1中的第一电源端、第一初始信号端、第二初始信号端等，第一遮光部71可以对第一导电部11起到稳压作用，从而降低驱动晶体管T3栅极在发光阶段的电压波动。此外，该显示面板可以利用第一导电层为掩膜对第一有源层进行导体化处理，即第一有源层中被第一导电层覆盖的区域可以形成晶体管的沟道区，未被第一导电层覆盖的区域形成导体结构。
如图3、7、16所示，第二导电层可以包括：第三复位信号线2Re1、第三栅线2G1、多个第二导电部22、第一连接部21。其中，第三复位信号线2Re1可以用于提供图1中的第一复位信号端，第三栅线2G1可以用于提供图1中的第一栅极驱动信号端。第三复位信号线2Re1在衬底基板上的正投影、第三栅线2G1在衬底基板上的正投影均可以沿第一方向X延伸。第二导电部22在衬底基板上的正投影可以和第一导电部11在衬底基板上的正投影至少部分交叠，第二导电部22可以用于形成电容C的第二电极，第一连接部21连接于同一重复单元中两第二导电部22之间。应该理解的是，在其他示例性实施例中，在第一方向X上相邻两重复单元中，相邻两第二导电部之间也可以相连接。
如图3、8、17所示，第二有源层可以包括多个子有源部8，子有源部8包括第一有源部81、第二有源部82、第十五有源部815、第十六有源部816、第十七有源部817，第一有源部81可以用于形成第一晶体管T1的沟道区；第二有源部82可以用于形成第二晶体管T2的沟道区；第十五有源部815连接于第一有源部81远离第二有源部82的一端，第十六有源部816连接于第二有源部82远离第一有源部81的一端，第十七有源部817连接于第一有源部81和第二有源部82之间。在第一方向X上相邻两重复单元 中，相邻子有源部8共用同一第十五有源部815。其中，第二有源层可以由氧化铟镓锌形成，相应的，第一晶体管T1、第二晶体管T2可以为N型的金属氧化物薄膜晶体管。第三栅线2G1在衬底基板上的正投影可以覆盖第二有源部82在衬底基板上的正投影，第三栅线2G1的部分结构可以用于形成第二晶体管的底栅。第三复位信号线2Re1在衬底基板上的正投影可以覆盖第一有源部81在衬底基板上的正投影，第三复位信号线2Re1的部分结构可以用于形成第一晶体管T1的底栅。在其他示例性实施例中，遮光层在衬底基板上的正投影也可以覆盖子有源部8在衬底基板上的正投影，以降低光照对第一晶体管、第二晶体管的特性影响。
如图3、9、18所示，第三导电层可以包括第一复位信号线3Re1、第一栅线3G1。第一复位信号线3Re1在衬底基板上的正投影、第一栅线3G1在衬底基板上的正投影均可以沿第一方向X延伸。第一复位信号线3Re1可以用于提供图1中的第一复位信号端，第一复位信号线3Re1在衬底基板上的正投影可以覆盖第一有源部81在衬底基板上的正投影，第一复位信号线3Re1的部分结构可以用于形成第一晶体管T1的顶栅，同时，第一复位信号线3Re1可以通过位于显示面板边沿走线区的过孔连接第三复位信号线2Re1。第一栅线3G1可以用于提供图1中的第一栅极驱动信号端，第一栅线3G1在衬底基板上的正投影可以覆盖第二有源部82在衬底基板上的正投影，第一栅线3G1的部分结构可以用于形成第二晶体管T2的顶栅，同时，第一栅线3G1可以通过位于显示面板边沿走线区的过孔连接第三栅线2G1。如图3、9、18所示，在同一像素驱动电路中，第一复位信号线3Re1、第二栅线G2、第一栅线3G1、第一导电部11、使能信号线EM、第二复位信号线Re2在所述衬底基板上的正投影在第二方向Y上依次分布。该显示面板可以利用第三导电层为掩膜对第二有源层进行导体化处理，即第二有源层中被第三导电层覆盖的区域可以形成晶体管的沟道区，未被第三导电层覆盖的区域形成导体结构。
如图3、10、19所示，第四导电层可以包括第一桥接部41、第二桥接部42、第三桥接部43、第四桥接部44、第一初始信号线Vinit1、第二初始信号线Vinit2、第一电源连接线4VDD。其中，第一桥接部41可以分别通过过孔(图中黑色方块)连接第十七有源部817和第一导电部11，以连 接第二晶体管T2的第一极和驱动晶体管T3的栅极。第二导电部22上可以形成有开口221，连接于第一导电部11和第一桥接部41之间的过孔在衬底基板上的正投影位于开口221在衬底基板上的正投影上，以使连接于第一导电部11和第一桥接部41之间的过孔和第二导电部22绝缘。第二桥接部42可以通过过孔连接第八有源部，以连接第六晶体管T6的第二极和第七晶体管T7的第二极。其中，第二桥接部42在衬底基板上的正投影在第一方向X上的尺寸大于第二桥接部42在衬底基板上的正投影在第二方向Y上的尺寸，第二桥接部42和第一初始信号线Vinit1等信号线可以形成侧向寄生电容，以进一步增加第六晶体管第二极的寄生电容。第三桥接部43可以分别通过过孔连接第十六有源部816和第十三有源部613，以连接第二晶体管T2的第二极和驱动晶体管T3的第二极。第四桥接部44可以通过过孔连接第十有源部410，以连接第四晶体管T4的第一极。第一初始信号线Vinit1在衬底基板上的正投影沿第一方向延伸，第一初始信号线Vinit1用于提供图1中的第一初始信号端，第一初始信号线Vinit1可以通过过孔连接第十五有源部815，以连接第一晶体管T1的第一极。第二初始信号线Vinit2在衬底基板上的正投影可以沿第一方向X延伸，第二初始信号线Vinit2可以同于提供图1中的第二初始信号端，第二初始信号线Vinit2可以通过过孔连接第十二有源部612，以连接第七晶体管T7的第一极。第一电源连接线4VDD在所述衬底基板上的正投影可以沿第一方向X延伸且第一电源连接线4VDD可以分别通过过孔连接所述第一连接部21和第十一有源部611，以连接第五晶体管T5的第一极和电容C的第二电极。
如图3、11、20所示，第五导电层可以包括第一电源线VDD、数据线Da、第五桥接部55。第五桥接部55可以通过过孔连接第二桥接部42，以连接第六晶体管的第二极。第一电源线VDD在衬底基板上的正投影可以沿第二方向Y延伸，第一电源线VDD用于提供图1中的第一电源信号端。第一电源线VDD可以包括第一延伸部VDD1、第二延伸部VDD2、第三延伸部VDD3，第二延伸部VDD2连接于第一延伸部VDD1和第三延伸部VDD3之间，第二延伸部VDD2在所述衬底基板上的正投影在第一方向X上的尺寸可以大于第一延伸部VDD1在所述衬底基板上的正投影在第一方向X上的尺寸， 且第二延伸部VDD2在所述衬底基板上的正投影在第一方向X上的尺寸可以大于第三延伸部VDD3在所述衬底基板上的正投影在第一方向X上的尺寸。在第一方向X上相邻的两所述重复单元中，相邻两第一电源线VDD中的第二延伸部VDD2相连接，且相连接的第二延伸部VDD2通过一个或多个过孔连接第一电源连接线4VDD。第一电源线VDD和第一电源连接线4VDD可以形成网格结构，该网格结构的电源线可以降低其上电源信号的压降。第二延伸部VDD2在衬底基板上的正投影可以覆盖第一有源部81、第二有源部82在衬底基板上的正投影，第二延伸部VDD2可以降低光照对第一晶体管、第二晶体管的特性影响。第二延伸部VDD2在衬底基板上的正投影还可以覆盖第一桥接部41在衬底基板上的正投影，第二延伸部VDD2可以对第一桥接部41进行稳压和屏蔽，以降低驱动晶体管T3栅极在发光阶段的电压波动。如图20所示，相连接的第二延伸部VDD2通过一个过孔连接第一电源连接线4VDD，第一电源连接线4VDD可以通过一个过孔连接所述第一连接部21，该设置可以减少过孔的数量，从而节约过孔的占用空间。数据线Da可以用于提供图1中的数据信号端，数据线Da在衬底基板上的正投影可以沿第二方向Y延伸，数据线Da可以通过过孔连接第四桥接部44，以连接数据信号端和第四晶体管的第一极。
如图3、12、13所示，所述电极层包括多个电极部：第一电极部G、第二电极部B、第三电极部R，各个电极部可以通过过孔连接第五桥接部55，以连接第六晶体管的第二极。像素界定层上形成有多个像素开口PH，所述像素开口PH与所述电极部对应设置，所述像素开口PH在所述衬底基板上的正投影和所述电极部在所述衬底基板上的正投影重合.第一电极部G可以用于形成显示面板中绿色发光单元的电极部，第二电极部B可以用于形成显示面板中蓝色发光单元的电极部，第三电极部R可以用于形成红色发光单元的电极部。在连接于同一行像素驱动电路的多个电极部中，第二电极部B、第一电极部G、第三电极部R、第一电极部G在行方向X上依次交替分布；在相邻两列像素驱动电路中，多个第二电极部B、多个第三电极部R连接于同一列像素驱动电路，且连接于同一列像素驱动电路的第二电极部B和第三电极部R在列方向Y上依次交替分布；多个第一电极部G连接于另一列像素驱动电路，连接于同一列像素驱动电路中的第一电极 部G在列方向上间隔分布。连接于相邻像素驱动电路行且连接于同一像素驱动电路列的两个第一电极部G在所述衬底基板上的正投影在列方向上的最小距离S1大于所述第三电极部R在所述衬底基板上的正投影在列方向的尺寸S2和/或连接于相邻像素驱动电路行且连接于同一像素驱动电路列的两个第一电极部G在所述衬底基板上的正投影在列方向上的最小距离S1大于所述第二电极部B所述衬底基板上的正投影在列方向的尺寸S3。
如图4所示，遮光层上还可以设置有第一开孔H1，衬底基板可以包括透光区，位于衬底基板和像素界定层之间的所有功能层(包括第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层、电极层，以及上述层级之间的绝缘层)的遮光结构在衬底基板上的正投影位于透光区以外，第一开孔H1在衬底基板上的正投影位于透光区。基于小孔成像原理，位于显示面板一侧的光信号可以通过第一开孔H1成像于显示面板的另一侧，从而应用该显示面板的显示装置可以实现指纹识别、屏下摄像头等技术。此外，第一开孔H1周围的遮光层可以降低衬底基板和像素界定层之间遮光结构所形成杂散光对小孔成像效果的影响。其中，遮光结构可以指在显示面板层叠方向上透光率小于50％的结构。
如图4所示，遮光层还可以包括第四遮光部74，第四遮光部74和重复单元对应设置，第四遮光部74连接与其对应的重复单元中的两第二遮光部72，且第四遮光部74连接于所述第二遮光部72远离所述第一遮光部71的一端，所述第一开孔H1形成于第四遮光部74上。第四遮光部74靠近第二遮光部72一侧的边沿还可以和第八有源部68形成侧向电容，从而可以进一步增加第六晶体管T6第二电极的寄生电容。
如图3、4、20所示，第一开孔H1在衬底基板上的正投影可以位于同一像素驱动电路中第一复位信号线3Re1和第二栅线G2在所述衬底基板上的正投影之间。第一开孔H1在衬底基板上的正投影位于同一重复单元中相邻两数据线Da在所述衬底基板上的正投影之间。
本示例性实施例中，第一开孔H1在所述衬底基板上的正投影的面积可以小于所述第一遮光部71在所述衬底基板上的正投影的面积。第一遮光部71在所述衬底基板上的正投影的面积可以为第一开孔H1在所述衬底基板上的正投影的面积的2-5倍，例如，第一遮光部71在所述衬底基板 上的正投影的面积可以为第一开孔H1在所述衬底基板上的正投影的面积的2倍、3倍、4倍、5倍等。
应该理解的是，在其他示例性实施例中，像素驱动电路还可以为其他结构，相应的，显示面板的版图结构也可以为其他结构，只要遮光层上形成有第一开孔，均可以通过位于遮光层上的第一开孔实现小孔成像，从而应用该显示面板的显示装置可以实现指纹识别、屏下摄像头等技术。
如图3、13所示，像素界定层PDL可以为黑色，像素界定层上还可以形成有第二开孔H2，第二开孔H2在衬底基板上的正投影也可以位于透光区。第二开孔H2和/或第一开孔H1可以形成小孔成像所需的小孔。其中，第二开孔H2在衬底基板上的正投影和第一开孔H1在衬底基板上的正投影可以重合；或，第二开孔H2在所述衬底基板上的正投影面积大于所述第一开孔H1在衬底基板上的正投影面积，第二开孔H2在所述衬底基板上的正投影覆盖所述第一开孔H1在所述衬底基板上的正投影；或，第一开孔H1在所述衬底基板上的正投影面积大于所述第二开孔H2在所述衬底基板上的正投影面积，所述第一开孔H1在所述衬底基板上的正投影覆盖所述第二开孔H2在所述衬底基板上的正投影。
在其他示例性实施例中，显示面板还可以包括位于像素界定层背离衬底基板一侧的彩膜层，彩膜层上黑矩阵可以形成有第三成像孔，第一开孔、第二开孔、第三成像孔中的一个或多个可以形成小孔成像所需的小孔。
需要说明的是，如图3、19、20所示，画于第四导电层背离衬底基板一侧的黑色方块表示第四导电层连接面向衬底基板一侧的其他层级的过孔；画于第五导电层背离衬底基板一侧的黑色方块表示第五导电层连接面向衬底基板一侧的其他层级的过孔；画于电极层背离衬底基板一侧的黑色方块表示电极层连接面向衬底基板一侧的其他层级的过孔。该黑色方块表示过孔的位置，不同位置黑色方块所表示的不同过孔可以贯穿于不同绝缘层。
如图21所示，为图3所示显示面板沿虚线AA剖开的部分剖视图。该显示面板还可以包括第一缓冲层92、第一绝缘层93、第二绝缘层94、第二缓冲层95、第三绝缘层96、介电层97、第一平坦层98、第二平坦层99。其中，衬底基板91、遮光层、第一缓冲层92、第一有源层、第一绝缘层 93、第一导电层、第二绝缘层94、第二导电层、第二缓冲层95、第二有源层、第三绝缘层96、第三导电层、介电层97、第四导电层、第一平坦层98、第五导电层、第二平坦层99、电极层、像素界定层PDL依次层叠设置。第一缓冲层92、第二缓冲层95可以包括氧化硅、氮化硅层中的一层或多层；第一绝缘层93、第二绝缘层94、第三绝缘层96可以包括氧化硅、氮化硅层中的一层或多层；介电层97可以包括氮化硅层；第一平坦层98、第二平坦层99的材料可以为有机材料，例如聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、硅-玻璃键合结构(SOG)等材料。衬底基板91可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一导电层、第二导电层、第三导电层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。第四导电层、第五导电层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。电极层可以包括氧化铟锡层、银层。第一导电层、第二导电层、第三导电层中任一导电层的方块电阻可以大于第四导电层、第五导电层中任一导电层的方块电阻。
需要说明的是，本公开中的附图比例可以作为实际工艺中的参考，但不限于此，例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图。此外，第一、第二等限定词仅用于限定不同的结构名称，其并没有特定顺序和数量的含义。在本示例性实施例中，某一结构在衬底基板上的正投影沿某一方向延伸，可以理解为该结构在衬底基板上的正投影沿该方向直线延伸或弯折延伸。晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区，并且电流能够流过漏极、沟道区以及源极。在本示例性实施例中，沟道区是指电流主要流过的区域。在本示例性实施例中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况下，“源极”及“漏极”的 功能有时互相调换。因此，在本示例性实施例中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
如图22所示，为本公开显示面板另一种示例性实施例的结构示意图。该显示面板可以包括显示区AA，显示区AA可以包括光信号采集区AA1和光信号采集区AA1以外的正常显示区AA2。其中，光信号采集区AA1可以为圆形、矩形、三角形、多边形等形状。位于显示面板一侧的光信号可以通过位于光信号采集区AA1的第一开孔H1成像于显示面板的另一侧。光信号采集区AA1可以作为指纹识别区、屏下摄像头区域等。
本示例性实施例中，光信号采集区AA1和正常显示区AA2中的版图结构均可以如图3所示。光信号采集区AA1和正常显示区AA2中的遮光层具有相同的图案形状，从而显示面板的不同区域具有相同的寄生电容分布，该设置可以提高显示面板的显示均一性。
在其他示例性实施例中，光信号采集区AA1和正常显示区AA2中遮光层在衬底基板上的正投影可以具有不同的图案形状。例如，如图23、24所示，图23为光信号采集区中遮光层的版图结构，图24为正常显示区中遮光层的版图结构。
如图23所示，位于光信号采集区的所述遮光层除了所述第一开孔H1以外整面设置。该设置可以使得光信号采集区中的第一开孔具有较好的成像效果。如图24所示，位于所述正常显示区的遮光层可以包括：第一遮光部71、第二连接部752、第三连接部753，第二连接部752在所述衬底基板上的正投影沿第一方向X延伸，且连接于在所述第一方向X上相邻的所述第一遮光部71之间；第三连接部753在所述衬底基板上的正投影沿第二方向Y延伸，且连接于在所述第二方向Y上相邻的所述第一遮光部71之间。正常显示区中遮光层镂空结构在衬底基板上正投影的面积和其实体结构在衬底基板上正投影的面积的比值为K1，光信号采集区中遮光层镂空结构在衬底基板上正投影的面积和其实体结构在衬底基板上正投影的面积的比值为K2，其中，K1可以大于K2。该设置可以有效改善由于正常显示区中遮光层大面积覆盖从而导致的对设备造成静电击伤的问题。
如图25所示，为光信号采集区中遮光层的另一种版图结构。其中，位于所述光信号采集区的遮光层上还形成有多个第一开口B1，所述第一开 口B1和显示面板中用于形成晶体管沟道区的有源部对应设置，第一开口B1在所述衬底基板上的正投影覆盖与其对应有源部在所述衬底基板上的正投影。其中，用于形成晶体管沟道区的有源部可以包括第一有源部81、第二有源部82、第三有源部63、第四有源部64、第五有源部65、第六有源部66、第七有源部67。在遮光层上形成第一开口B1可以降低遮光层和晶体管沟道区之间的寄生电容，从而降低该寄生电容对晶体管特性的影响。
在其他示例性实施例中，遮光层还可以位于衬底基板和像素界定层之间的其他任意位置。例如，遮光层可以位于FIP(Fanout In Panel，面板中扇出)技术中增设的扇出线所在的导电层。如图26所示，为本公开显示面板另一种示例性实施例的结构示意图，该显示面板包括显示区AA，显示区AA包括扇出区AA3、光信号采集区AA1、位于扇出区AA3和光信号采集区AA1以外的其他显示区AA4。该显示面板可以包括多条数据线Da、多条第一数据扇出线Fa1、多条第二数据扇出线Fa2，多条数据线Da位于所述显示区AA，数据线Da在所述衬底基板上的正投影沿第一方向X间隔分布且沿第二方向Y延伸；多条第一数据扇出线Fa1位于所述扇出区AA3，所述第一数据扇出线Fa1在所述衬底基板上的正投影沿所述第二方向Y间隔分布且沿所述第一方向X延伸，所述第一数据扇出线Fa1与所述数据线Da对应设置，所述第一数据扇出线Fa1连接与其对应的所述数据线Da；多条第二数据扇出线Fa2位于所述扇出区AA3，所述第二数据扇出线Fa2在所述衬底基板上的正投影沿所述第一方向X间隔分布且沿所述第二方向Y延伸，所述第二数据扇出线Fa2与所述第一数据扇出线Fa1对应设置，所述第二数据扇出线Fa2连接与其对应的所述第一数据扇出线Fa1。第一数据扇出线Fa1可以位于所述遮光层。其中，数据线Da、第二数据扇出线Fa2可以位于第五导电层，第一数据扇出线Fa1可以位于增设于第五导电层和像素界定层之间的第六导电层。
图26所示显示面板中，光信号采集区AA1中遮光层的版图结构可以和图23或图25所示结构相同。如图27所示，为图26所示显示面板中其他显示区AA4中遮光层的版图结构。位于其他显示区AA4中的遮光层可以包括多条第二电源线VSS，部分第二电源线VSS在衬底基板上的正投影可以沿第一方向X延伸，部分第二电源线VSS在衬底基板上的正投影可以沿 第二方向Y延伸，沿不同方向延伸的第二电源线可以相交以形成网格结构，形成网格结构的第二电源线VSS可以通过过孔和公共电极层连接，从而降低公共电极层上信号的压降。其中，公共电极层位于像素界定层背离衬底基板的一侧，公共电极层用于形成发光单元的第二电极。在其他示例性实施例中，位于其他显示区AA4中遮光层的第二电源线也可以沿同一方向延伸。此外，在其他示例性实施例中，位于其他显示区AA4中的遮光层还可以包括其他信号线，例如，位于其他显示区AA4中的遮光层还可以包括第二信号线，第二信号线可以和与其位于不同导电层的第一信号线在衬底基板上的正投影相交，且第二信号线可以通过过孔连接与其相交的第一信号线，第二信号线可以与第一信号线形成网格结构，以降低第一信号线上信号的压降。第一信号线可以包括第一初始信号线、第二初始信号线、第一电源线中的一种或多种。需要说明的是，位于其他显示区AA4中的遮光层可以同时包括第二信号线和第二电源线。
本示例性实施例还提供一种显示装置，其中，包括上述的显示面板。该显示装置可以为手机、平板电脑、电视等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (27)

  1. 一种显示面板，其中，所述显示面板包括发光单元，所述显示面板还包括：
    衬底基板，所述衬底基板包括透光区；
    遮光层，位于所述衬底基板的一侧，所述遮光层具有遮光作用；
    像素界定层，位于所述遮光层背离所述衬底基板的一侧，所述像素界定层上形成有像素开口，所述像素开口内用于形成所述发光单元；
    多层功能层，位于所述衬底基板和所述像素界定层之间，位于所述衬底基板和所述像素界定层之间的所有功能层的遮光结构在所述衬底基板上的正投影位于所述透光区以外；
    所述遮光层上形成有第一开孔，所述第一开孔在所述衬底基板上的正投影位于所述透光区。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括用于驱动所述发光单元的像素驱动电路，所述像素驱动电路包括驱动晶体管；
    多层功能层中包括：
    第一有源层，所述第一有源层包括第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区；
    所述遮光层位于所述第一有源层和所述衬底基板之间，所述遮光层包括第一遮光部，所述第一遮光部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影。
  3. 根据权利要求2所述的显示面板，其中，所述像素驱动电路还包括第一晶体管、第四晶体管，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；
    所述显示面板还包括：
    第一复位信号线，所述第一复位信号线在所述衬底基板上的正投影沿第一方向延伸，所述第一复位信号线的部分结构用于形成所述第一晶体管的顶栅；
    第二栅线，所述第二栅线在所述衬底基板上的正投影沿所述第一方向 延伸，所述第二栅线的部分结构用于形成所述第四晶体管的栅极；
    其中，所述第一开孔在所述衬底基板上的正投影位于同一像素驱动电路中所述第一复位信号线和所述第二栅线在所述衬底基板上的正投影之间。
  4. 根据权利要求2所述的显示面板，其中，所述显示面板包括多个重复单元，多个所述重复单元在第一方向和第二方向上阵列分布，所述第一方向和所述第二方向相交；
    所述重复单元包括在所述第一方向上分布的两个像素驱动电路，同一所述重复单元中两个所述像素驱动电路镜像对称设置。
  5. 根据权利要求4所述的显示面板，其中，所述像素驱动电路还包括第四晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；
    所述数据线在所述衬底基板上的正投影沿所述第二方向延伸，所述第一开孔在所述衬底基板上的正投影位于同一所述重复单元中相邻两数据线在所述衬底基板上的正投影之间。
  6. 根据权利要求2所述的显示面板，其中，所述像素驱动电路还包括第六晶体管、第七晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述发光单元的第一电极，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极；
    所述第一有源层还包括：
    第六有源部，用于形成所述第六晶体管的沟道区；
    第七有源部，用于形成所述第七晶体管的沟道区；
    第八有源部，连接于所述第六有源部和所述第七有源部之间；
    所述遮光层还包括：
    第二遮光部，所述第二遮光部连接于第一遮光部；
    其中，所述第八有源部在所述衬底基板上的正投影和所述第二遮光部在所述衬底基板上的正投影至少部分交叠。
  7. 根据权利要求6所述的显示面板，其中，所述第八有源部在所述衬底基板上的正投影沿第一方向延伸，所述第八有源部在所述衬底基板上 的正投影在所述第一方向上的尺寸大于所述第八有源部在所述衬底基板上的正投影在第二方向上的尺寸；
    所述第二遮光部在所述衬底基板上的正投影沿所述第一方向延伸，所述第二遮光部在所述衬底基板上的正投影在所述第一方向上的尺寸大于所述第二遮光部在所述衬底基板上的正投影在所述第二方向上的尺寸；
    所述第一方向和所述第二方向相交。
  8. 根据权利要求6所述的显示面板，其中，所述显示面板包括多个重复单元，多个所述重复单元在第一方向和第二方向上阵列分布，所述第一方向和所述第二方向相交；
    所述重复单元包括在所述第一方向上分布的两个像素驱动电路，同一所述重复单元中两个所述像素驱动电路镜像对称设置；
    所述第一遮光层还包括：
    第四遮光部，所述第四遮光部和所述重复单元对应设置，所述第四遮光部连接与其对应的所述重复单元中的两所述第二遮光部，且第四遮光部连接于所述第二遮光部远离所述第一遮光部的一端，所述第一开孔形成于所述第四遮光部上。
  9. 根据权利要求6所述的显示面板，其中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极；
    多层功能层中还包括：
    第一导电层，位于所述第一有源层和所述像素界定层之间，所述第一导电层包括第一导电部，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极；
    第四导电层，位于所述第一导电层和所述像素界定层之间，所述第四导电层包括第一桥接部和第二桥接部；
    其中，所述第一桥接部连接所述第二晶体管的第一极，且所述第一桥接部通过过孔连接所述第一导电部，所述第二桥接部通过过孔连接所述第八有源部，且所述第二桥接部在所述衬底基板上的正投影在第一方向上的尺寸大于所述第二桥接部在所述衬底基板上的正投影在第二方向上的尺 寸。
  10. 根据权利要求2所述的显示面板，其中，所述第一开孔在所述衬底基板上的正投影的面积小于所述第一遮光部在所述衬底基板上的正投影的面积。
  11. 根据权利要求2所述的显示面板，其中，所述像素驱动电路还包括第一晶体管、第二晶体管，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极；
    多层功能层中还包括：
    第一导电层，位于所述第一有源层和所述像素界定层之间，所述第一导电层包括第一导电部，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极；
    第四导电层，位于所述第一导电层和所述像素界定层之间，所述第四导电层包括第一桥接部和所述第一初始信号线，所述第一初始信号线在所述衬底基板上的正投影沿第一方向延伸；
    所述第一桥接部连接所述第二晶体管的第一极，且所述第一桥接部通过过孔连接所述第一导电部。
  12. 根据权利要求4所述的显示面板，其中，所述像素驱动电路还包括电容，所述电容的第一电极连接所述驱动晶体管的栅极，所述电容的第二电极连接第一电源线；
    多层功能层中还包括：
    第一导电层，位于所述第一有源层和所述像素界定层之间，所述第一导电层包括第一导电部，所述第一导电部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极和所述电容的第一电极；
    第二导电层，位于所述第一导电层和所述像素界定层之间，所述第二导电层包括第二导电部和第一连接部，所述第二导电部在所述衬底基板上的正投影和所述第一导电部在所述衬底基板上的正投影至少部分交叠，所 述第二导电部用于形成所述电容的第二电极，所述第一连接部连接于同一所述重复单元中两所述第二导电部之间；
    第四导电层，位于所述第二导电层和所述像素界定层之间，所述第四导电层包括第一电源连接线，所述第一电源连接线在所述衬底基板上的正投影沿第一方向延伸且所述第一电源连接线通过过孔连接所述第一连接部；
    第五导电层，位于所述第四导电层背离所述衬底基板的一侧，所述第五导电层包括所述第一电源线，在所述第一方向上相邻的两所述重复单元中，相邻两所述第一电源线相连接，且相连接两所述第一电源线通过过孔连接所述第一电源连接线。
  13. 根据权利要求1所述的显示面板，其中，所述像素界定层为黑色，所述像素界定层上还形成有第二开孔，所述第二开孔在所述衬底基板上的正投影位于所述透光区；
    所述第二开孔在所述衬底基板上的正投影和所述第一开孔在所述衬底基板上的正投影重合；
    或，第二开孔在所述衬底基板上的正投影面积大于所述第一开孔在所述衬底基板上的正投影面积，所述第二开孔在所述衬底基板上的正投影覆盖所述第一开孔在所述衬底基板上的正投影；
    或，第一开孔在所述衬底基板上的正投影面积大于所述第二开孔在所述衬底基板上的正投影面积，所述第一开孔在所述衬底基板上的正投影覆盖所述第二开孔在所述衬底基板上的正投影。
  14. 根据权利要求2所述的显示面板，其中，所述显示面板包括显示区，所述显示区包括光信号采集区，至少所述光信号采集区中的所述遮光层设置有所述第一开孔。
  15. 根据权利要求14所述的显示面板，其中，所述显示区还包括位于所述光信号采集区以外的正常显示区；
    位于所述光信号采集区的所述遮光层在所述衬底基板上的正投影和位于所述正常显示区的所述遮光层在所述衬底基板上的正投影具有不同的图案形状。
  16. 根据权利要求14所述的显示面板，其中，所述显示区还包括所 述光信号采集区以外的正常显示区，所述正常显示区中的所述遮光层也设置有所述第一开孔；
    位于所述光信号采集区的所述遮光层在所述衬底基板上的正投影和位于所述正常显示区的所述遮光层在所述衬底基板上的正投影具有相同的图案形状。
  17. 根据权利要求15所述的显示面板，其中，位于所述光信号采集区的所述遮光层除了所述第一开孔以外整面设置。
  18. 根据权利要求17所述的显示面板，其中，所述像素驱动电路还包括多个开关晶体管；
    所述第一有源层还包括：
    多个有源部，所述有源部用于形成所述开关晶体管的沟道区；
    其中，位于所述光信号采集区的所述遮光层上还形成有多个第一开口，所述第一开口和所述有源部对应设置，所述第一开口在所述衬底基板上的正投影覆盖与其对应的所述有源部在所述衬底基板上的正投影。
  19. 根据权利要求15所述的显示面板，其中，位于所述正常显示区的所述遮光层还包括：
    多条第二连接部，在所述衬底基板上的正投影沿第一方向延伸，且连接于在所述第一方向上相邻的所述第一遮光部之间；
    多条第三连接部，在所述衬底基板上的正投影沿第二方向延伸，且连接于在所述第二方向上相邻的所述第一遮光部之间，所述第一方向和所述第二方向相交。
  20. 根据权利要求1所述的显示面板，其中，所述显示面板还包括显示区，所述显示区包括扇出区和光信号采集区；
    所述显示面板还包括：
    多条数据线，位于所述显示区，所述数据线在所述衬底基板上的正投影沿第一方向间隔分布且沿第二方向延伸，所述第一方向和所述第二方向相交；
    多条第一数据扇出线，位于所述扇出区，所述第一数据扇出线在所述衬底基板上的正投影沿所述第二方向间隔分布且沿所述第一方向延伸，所述第一数据扇出线与所述数据线对应设置，所述第一数据扇出线连接与其 对应的所述数据线；
    多条第二数据扇出线，位于所述扇出区，所述第二数据扇出线在所述衬底基板上的正投影沿所述第一方向间隔分布且沿所述第二方向延伸，所述第二数据扇出线与所述第一数据扇出线对应设置，所述第二数据扇出线连接与其对应的所述第一数据扇出线；
    所述第一数据扇出线位于所述遮光层。
  21. 根据权利要求20所述的显示面板，其中，多层所述功能层中还包括：
    第五导电层，位于所述衬底基板和所述像素界定层之间，所述第五导电层包括所述数据线；
    所述遮光层位于所述第五导电层和所述像素界定层之间。
  22. 根据权利要求20所述的显示面板，其中，所述显示区还包括位于所述扇出区和光信号采集区以外的其他显示区；
    所述显示面板还包括：
    多条第一信号线，位于所述遮光层以外的导电层；
    位于所述其他显示区的所述遮光层包括多条第二信号线，所述第一信号线在所述衬底基板上的正投影和所述第二信号线在所述衬底基板上的正投影相交，且所述第二信号线通过过孔连接与其相交的所述第一信号线。
  23. 根据权利要求1所述的显示面板，其中，所述第一开孔用于将所述显示面板一侧的光信号小孔成像于所述显示面板的另一侧。
  24. 一种显示面板，其中，所述显示面板包括：
    衬底基板；
    遮光层，位于所述衬底基板的一侧，所述遮光层具有遮光作用；
    多层功能层，位于所述衬底基板的一侧；
    其中，所述遮光层上形成有第一开孔，所述第一开孔在所述衬底基板上的正投影和所述功能层中遮光结构在所述衬底基板上的正投影不交叠，且所述遮光层在衬底基板上的正投影和至少一层所述功能层中遮光结构在所述衬底基板上的正投影交叠。
  25. 根据权利要求24所述的显示面板，其中，所述显示面板还包括发光单元和用于驱动所述发光单元的像素驱动电路，所述像素驱动电路包 括驱动晶体管；
    多层功能层中包括：
    第一有源层，所述第一有源层包括第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区；
    所述遮光层位于所述第一有源层和所述衬底基板之间，所述遮光层包括第一遮光部，所述第一遮光部在所述衬底基板上的正投影覆盖所述第三有源部在所述衬底基板上的正投影；
    所述像素驱动电路还包括第一晶体管、第四晶体管，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；
    所述显示面板还包括：
    第一复位信号线，所述第一复位信号线在所述衬底基板上的正投影沿第一方向延伸，所述第一复位信号线的部分结构用于形成所述第一晶体管的顶栅；
    第二栅线，所述第二栅线在所述衬底基板上的正投影沿所述第一方向延伸，所述第二栅线的部分结构用于形成所述第四晶体管的栅极；
    其中，所述第一开孔在所述衬底基板上的正投影位于同一像素驱动电路中所述第一复位信号线和所述第二栅线在所述衬底基板上的正投影之间。
  26. 根据权利要求24所述的显示面板，其中，所述显示面板还包括显示区，所述显示区包括扇出区和光信号采集区；
    所述显示面板还包括：
    多条数据线，位于所述显示区，所述数据线在所述衬底基板上的正投影沿第一方向间隔分布且沿第二方向延伸，所述第一方向和所述第二方向相交；
    多条第一数据扇出线，位于所述扇出区，所述第一数据扇出线在所述衬底基板上的正投影沿所述第二方向间隔分布且沿所述第一方向延伸，所述第一数据扇出线与所述数据线对应设置，所述第一数据扇出线连接与其对应的所述数据线；
    多条第二数据扇出线，位于所述扇出区，所述第二数据扇出线在所述衬底基板上的正投影沿所述第一方向间隔分布且沿所述第二方向延伸，所述第二数据扇出线与所述第一数据扇出线对应设置，所述第二数据扇出线连接与其对应的所述第一数据扇出线；
    所述第一数据扇出线位于所述遮光层。
  27. 一种显示装置，其中，所述显示装置包括权利要求1-26任一项所述的显示面板。
PCT/CN2022/136318 2022-12-02 2022-12-02 显示面板及显示装置 Ceased WO2024113370A1 (zh)

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