WO2024108744A1

WO2024108744A1 - Semiconductor structure and forming method therefor

Info

Publication number: WO2024108744A1
Application number: PCT/CN2023/070665
Authority: WO
Inventors: 李松雨; 刘梅花; 王学生
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-11-24
Filing date: 2023-01-05
Publication date: 2024-05-30
Also published as: CN118119175A

Abstract

The present disclosure relates to a semiconductor structure and a forming method therefor. The forming method for a semiconductor structure comprises the following steps: forming a base, the base comprising a substrate and a stack layer, which is located on the substrate, wherein the substrate is provided with a plurality of active areas; forming a first etched pattern on the stack layer, the first etched pattern comprising a first mask layer and first trenches, which penetrate through the first mask layer; backfilling the first trenches to form a first filling layer; forming a second etched pattern on the first filling layer and the first etched pattern, the second etched pattern comprising a second mask layer, second trenches, which penetrate through the second mask layer, and second side wall layers, which cover side walls of the second trenches; removing the second mask layer to form third trenches; and etching the stack layer by taking overlap areas of the third trenches and the first mask layer as mask patterns, so as to form contact holes, which expose the active areas. The present disclosure simplifies the manufacturing process of the semiconductor structure, and facilitates the miniaturization of the size of the semiconductor structure.

Description

Semiconductor structure and method of forming the same

Related Application Citations

This application claims priority to Chinese Patent Application No. 202211481289.4, filed on November 24, 2022, and entitled “Semiconductor Structure and Method for Forming the Same,” the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same.

Background technique

Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It is composed of multiple storage units, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.

In the manufacturing process of semiconductor structures such as DRAM, when forming a conductive structure such as a bit line electrically connected to the source region in the transistor, it is necessary to first form a contact hole such as a bit line contact hole, and then form the conductive structure such as the bit line contact hole in the contact hole such as the bit line contact hole. However, when forming contact holes such as the bit line contact hole, multiple masks and multiple etching processes are required, which not only makes the process complicated but also has high process costs. Moreover, as the size of semiconductor structures such as DRAM is further reduced, the characteristic dimensions (CD) of contact holes such as the bit line contact hole are further miniaturized, so that the distance between adjacent contact holes is reduced, which in turn leads to a strong capacitive coupling effect between adjacent conductive structures, reducing the electrical performance of the semiconductor structure.

Therefore, how to simplify the manufacturing process of the semiconductor structure, reduce the manufacturing cost of the semiconductor structure, reduce the capacitive coupling effect inside the semiconductor structure, and improve the electrical performance of the semiconductor structure are technical problems that need to be solved urgently.

Summary of the invention

Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which are used to simplify the manufacturing process of the semiconductor structure, reduce the manufacturing cost of the semiconductor structure, and reduce the capacitive coupling effect inside the semiconductor structure to improve the electrical performance of the semiconductor structure.

According to some embodiments, the present disclosure provides a method for forming a semiconductor structure, comprising the following steps:

forming a substrate, the substrate comprising a substrate and a stacked layer located on the substrate, the substrate having a plurality of active regions;

Forming a first etching pattern above the stacked layer, the first etching pattern comprising a first mask layer and a first groove penetrating the first mask layer along a first direction, a plurality of the first grooves being arranged at intervals along a second direction, the first direction being perpendicular to the top surface of the substrate, and the second direction being parallel to the top surface of the substrate;

backfilling the first trench to form a first filling layer;

Forming a second etching pattern above the first filling layer and the first etching pattern, wherein the second etching pattern includes a second mask layer, a second trench penetrating the second mask layer along the first direction, and a second sidewall layer covering the sidewall of the second trench, wherein a plurality of the second trenches are arranged at intervals along the second direction;

removing the second mask layer to form a plurality of third trenches spaced apart along the second direction;

The stacked layer is etched using the overlapping area of the third trench and the first mask layer as a mask pattern to form a contact hole exposing the active area.

In some embodiments, the specific steps of forming the substrate include:

providing a substrate;

A stacking layer is formed on the top surface of the substrate, wherein the stacking layer includes a contact material stacking layer and a sacrificial stacking layer located above the contact material stacking layer.

In some embodiments, the specific steps of forming a first etched pattern on the stacked layer include:

forming a first mask layer above the stacked layer, and forming a third mask layer above the first mask layer;

Etching the third mask layer to form a fourth trench penetrating the third mask layer along the first direction, wherein a plurality of the fourth trenches are arranged at intervals along the second direction;

forming a first spacer layer covering only the sidewall of the fourth trench;

removing the third mask layer to form a fifth trench;

The first mask layer is etched downward along the fifth trench and the retained fourth trench to form a plurality of first trenches.

In some embodiments, the specific steps of forming a first spacer layer covering only the sidewall of the fourth trench include:

forming an initial first spacer layer continuously covering inner walls of a plurality of the fourth trenches and a top surface of the third mask layer;

The initial first spacer layer covering the bottom wall of the fourth trench and the top surface of the third mask layer is removed, and the initial first spacer layer on the side wall of the fourth trench is retained as the first spacer layer.

In some embodiments, the specific steps of forming the first filling layer include:

forming the first filling layer that fills the first trench and covers the top surface of the first mask layer;

A portion of the first filling layer is removed, and a top surface of the remaining first filling layer is flush with a top surface of the first mask layer.

In some embodiments, the specific steps of forming the second etched pattern on the first filling layer and the first etched pattern include:

forming the second mask layer above the first filling layer and the first mask layer;

Etching the second mask layer to form the second groove penetrating the second mask layer along the first direction, wherein a plurality of the second grooves are arranged at intervals along the second direction;

forming the second sidewall layer continuously covering the inner walls of a plurality of the second trenches and the top surface of the second mask layer;

The second spacer layer covering the bottom wall of the second trench and the top surface of the second mask layer is removed, and only the second spacer layer covering the side wall of the second trench is retained.

In some embodiments, before etching the stacked layer using the overlapping area of the third trench and the first mask layer as a mask pattern, the following steps are also included:

A second filling layer is formed to completely fill the second trench.

In some embodiments, the substrate includes a plurality of active regions arranged in an array along the second direction and a third direction, the active regions extend along the third direction, the third direction is parallel to the top surface of the substrate, and the third direction intersects with the second direction;

A projection of the third trench on the top surface of the substrate covers the plurality of active regions spaced apart along the second direction.

In some embodiments, the width of the third trench along the second direction is equal to the width of the first mask layer along the fourth direction, the fourth direction is parallel to the top surface of the substrate, and the fourth direction intersects both the second direction and the third direction.

In some embodiments, the specific steps of etching the stacked layer using the overlapping area of the third trench and the first mask layer as a mask pattern to form a contact hole exposing the active area include:

Etching the first mask layer downward along the third trench to form an etching window located between adjacent first filling layers and exposing the top surface of the sacrificial stack layer;

The sacrificial layer stack and the contact material stack are etched downward along the etching window to form the contact hole exposing the active area.

In some embodiments, the active region includes a conductive contact region located in a middle portion of the active region;

A projection of the contact hole on the top surface of the substrate is aligned with the conductive contact region in one of the active regions.

In some embodiments, the projection of the contact hole on the top surface of the substrate is entirely located within the active area; or,

A width of a projection of the contact hole on the top surface of the substrate along the second direction is greater than a width of the active region along the second direction.

In some embodiments, a projection of the contact hole on the top surface of the substrate is in the shape of an ellipse or a parallelogram.

In some embodiments, the conductive contact region is a bit line contact region, and the contact hole is a bit line contact hole.

In some embodiments, the active region further includes a capacitor contact region located at an end of the active region, and the contact material stack layer is connected to the capacitor contact region.

According to some other embodiments, the present disclosure further provides a semiconductor structure, including:

A substrate having a plurality of active regions therein, wherein the active regions include a conductive contact region located in the middle of the active regions;

A stacking layer, located on the top surface of the substrate;

A contact plug penetrates the stacked layers along a first direction and is electrically connected to the conductive contact region, wherein a projection of the contact plug on the top surface of the substrate is aligned with one of the conductive contact regions, and the first direction is perpendicular to the top surface of the substrate.

In some embodiments, the substrate includes a plurality of active regions arranged in an array along the second direction and a third direction, the active regions extend along the third direction, the second direction and the third direction are both parallel to the top surface of the substrate, and the third direction intersects with the second direction;

The plurality of contact plugs are electrically connected to the plurality of active regions in a one-to-one correspondence.

In some embodiments, the projection of the contact plug on the top surface of the substrate is entirely located within the active region; or,

A width of a projection of the contact plug on the top surface of the substrate along the second direction is greater than a width of the active region along the second direction.

In some embodiments, a projection of the contact plug on the top surface of the substrate is in the shape of an ellipse or a parallelogram.

In some embodiments, the conductive contact region is a bit line contact region, and the contact plug is a bit line contact plug.

Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same. A first etching pattern and a second etching pattern located above the first etching pattern are formed. After removing the second mask layer in the second etching pattern and forming a third groove, a stacked layer is etched using an overlapping area between the third groove and the first mask layer along a first direction as a mask pattern to form a contact hole exposing an active area in a substrate. On the one hand, only one photomask is required to etch the stacked layer to form the contact hole, thereby simplifying the manufacturing process of the semiconductor structure and reducing the manufacturing cost of the semiconductor structure. On the other hand, the contact hole with a smaller feature size can be formed, which helps to further shrink the size of the semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure;

Figures 2 to 20 are schematic cross-sectional views of the main processes in forming a semiconductor structure according to a specific embodiment of the present disclosure;

21 is a schematic cross-sectional view of a semiconductor structure in a specific embodiment of the present disclosure.

Detailed ways

The specific implementation of the semiconductor structure and the method for forming the same provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

This specific embodiment provides a method for forming a semiconductor structure. FIG1 is a flow chart of the method for forming a semiconductor structure in the specific embodiment of the present disclosure. FIG2-20 are schematic cross-sectional views of the main processes in the process of forming a semiconductor structure in the specific embodiment of the present disclosure. As shown in FIG1-20, the method for forming a semiconductor structure includes the following steps:

Step S11, forming a substrate, the substrate comprising a substrate 20 and a stacked layer located on the substrate 20, the substrate 20 having a plurality of active regions 140 (see FIGS. 14, 15 and 16), as shown in FIG. 1;

Step S12, forming a first etching pattern on the stacked layer, wherein the first etching pattern includes a first mask layer 28, and a first groove 60 penetrating the first mask layer 28 along a first direction D1, and a plurality of first grooves 60 are arranged at intervals along a second direction D2, wherein the first direction D1 is perpendicular to the top surface of the substrate 20, and the second direction D2 is parallel to the top surface of the substrate 20, as shown in FIG. 6;

Step S13, backfilling the first trench 60 to form a first filling layer 70, as shown in FIG. 8;

Step S14, forming a second etching pattern on the first filling layer 70 and the first etching pattern, wherein the second etching pattern includes a second mask layer, a second trench 110 penetrating the second mask layer along the first direction D1, and a second spacer layer 120 covering the sidewall of the second trench 110, and a plurality of second trenches 110 are arranged at intervals along the second direction D2, as shown in FIG. 13;

Step S15, removing the second mask layer, forming a plurality of third trenches 150 spaced apart along the second direction D2, as shown in FIG. 15 , which is a top view schematic diagram during the process of forming the semiconductor structure. In the top view schematic diagram shown in FIG. 15 , the active area 140 is not visible, so the active area 140 is represented by a dotted line to clearly identify the relative positional relationship between the active area 140 and the third trenches 150;

In step S16, the stacked layer is etched using the overlapping area of the third trench 150 and the first mask layer 28 as the mask pattern 170 to form a contact hole 200 exposing the active area 140, see Figures 17 and 20, wherein Figure 17 is an enlarged schematic diagram of the square dotted box area in Figure 16.

In some embodiments, the specific steps of forming the substrate include:

Providing a substrate 20;

A stacked layer is formed on the top surface of the substrate 20 , and the stacked layer includes a contact material stacked layer S1 and a sacrificial stacked layer S2 located above the contact material stacked layer S1 , as shown in FIG. 2 .

The semiconductor structure described in this specific embodiment can be but is not limited to DRAM. The substrate 20 can be but is not limited to a silicon substrate. This specific embodiment is described by taking the substrate 20 as a silicon substrate as an example. In other embodiments, the substrate 20 can also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. The top surface of the substrate 20 refers to the surface of the substrate 20 facing the stacked layer. Taking the semiconductor structure as DRAM as an example, the substrate 20 has a plurality of active areas 140 arranged in an array, each of the active areas 140 includes a capacitor contact area 201 and a bit line contact area 21, the capacitor contact area 201 is used to be electrically connected to the capacitor, and the bit line contact area 21 is used to be electrically connected to the bit line. The substrate 20 also includes an isolation structure 22 located between the adjacent capacitor contact area 201 and the bit line contact area 21, which is used to electrically isolate the capacitor contact area 201 and the bit line contact area 21. The contact material stack layer S1 is subsequently used to form a capacitor contact structure electrically connected to the capacitor contact area 201, and the sacrificial stack layer S2 is used as a mask layer for forming the contact hole 200.

In one example, the contact material stack layer S1 includes a substrate isolation layer 34 covering the top surface of the substrate 20, a first dielectric layer 23 located on the surface of the substrate isolation layer 34, a conductive material layer 24 located on the surface of the first dielectric layer 23, and a second dielectric layer 25 located on the conductive material layer 24. The material of the substrate isolation layer 34 may be an oxide material (e.g., silicon dioxide), the material of the first dielectric layer 23 may be a nitride material (e.g., silicon nitride), the material of the conductive material layer 24 may be polysilicon, and the material of the second dielectric layer 25 may be an oxide material (e.g., silicon dioxide). The sacrificial stack layer S2 includes a first sacrificial layer 26 covering the surface of the contact material stack layer S1, and a second sacrificial layer 27 located on the surface of the first sacrificial layer 26. The material of the first sacrificial layer 26 may be a SOH (Spin On Hardmask) material, and the material of the second sacrificial layer 27 may be a nitride oxide material (e.g., silicon oxynitride).

Forming a first mask layer 28 on the stacked layer, and forming a third mask layer on the first mask layer 28, as shown in FIG. 2;

The third mask layer is etched to form a fourth trench 40 penetrating the third mask layer along the first direction D1, and a plurality of the fourth trenches 40 are arranged at intervals along the second direction D2, as shown in FIG. 4 ;

forming a first spacer layer 41 covering only the sidewall of the fourth trench 40, as shown in FIG5;

removing the third mask layer to form a fifth trench;

The first mask layer 28 is etched downward along the fifth trench and the retained fourth trench 40 to form a plurality of first trenches 60 , as shown in FIG. 6 .

In some embodiments, the specific steps of forming the first spacer layer 41 covering only the sidewall of the fourth trench 40 include:

forming an initial first spacer layer 42 that continuously covers the inner walls of the plurality of fourth trenches 40 and the top surface of the third mask layer;

The initial first spacer layer 42 covering the bottom wall of the fourth trench 40 and the top surface of the third mask layer is removed, and the initial first spacer layer 42 on the side wall of the fourth trench 40 is retained as the first spacer layer 41 .

For example, after the stacked layers are formed, the first mask layer 28, the fourth mask layer 29 and the third mask layer are sequentially formed on the top surface of the stacked layers along the first direction D1. In order to further improve the morphology of the first groove 60, the third mask layer includes a first sub-mask layer 30 covering the surface of the fourth mask layer 29 and a second sub-mask layer 31 covering the surface of the first sub-mask layer 30, as shown in FIG2. The material of the first mask layer 28 may be an oxide material (e.g., silicon dioxide), the material of the fourth mask layer 29 may be an oxynitride material (e.g., silicon oxynitride), the material of the first sub-mask layer 30 may be SOH, and the material of the second sub-mask layer 31 may be an oxynitride material (e.g., silicon oxynitride). Afterwards, a first photoresist layer 32 is formed on the top surface of the second sub-mask layer 31, and the first photoresist layer 32 has a first opening 32 exposing the second sub-mask layer 31, as shown in FIG3. The third mask layer is etched downward along the first opening 32 to form a plurality of fourth trenches 40 arranged at intervals along the second direction D2 and continuously penetrating the second sub-mask layer 31 and the first sub-mask layer 30 along the first direction D1. An oxide material (e.g., silicon dioxide) is deposited on the third mask layer to form the initial first spacer layer 42 that continuously covers the inner walls of the plurality of fourth trenches 40 and the top surface of the third mask layer, as shown in FIG4 . At this time, the initial first spacer layer 42 does not completely fill the fourth trench 40. The initial first spacer layer 42 is etched back to remove the initial first spacer layer 42 covering the bottom wall of the fourth trench 40 and the top surface of the third mask layer, and the initial first spacer layer 42 that is retained on the sidewall of the fourth trench 40 is used as the first spacer layer 41, as shown in FIG5 .

Afterwards, the third mask layer is removed to form the fifth trench between two adjacent first spacer layers 41. The fourth mask layer 29 and the first mask layer 28 are etched downward along the fifth trench and the remaining fourth trench 40 between two adjacent first spacer layers 41 to form a plurality of first trenches 60 arranged at intervals along the second direction D2 and penetrating the first mask layer 28 along the first direction D1. After removing the third mask layer, the first spacer layer 41 and the fourth mask layer 29, a structure as shown in FIG. 6 is obtained.

This specific embodiment forms the first etching pattern through a double pattern etching process, and does not use the fourth groove 40, the fifth groove, and the first sidewall layer 41 directly as a mask pattern for etching to form the contact hole 200. This can avoid the influence of defects such as the chamfer of the upper part of the first sidewall layer 41 on the morphology and characteristic size of the contact hole 200 finally formed, and can improve the uniformity of the morphology and characteristic size of multiple contact holes 200, so as to improve the performance of the semiconductor structure.

In order to maintain the morphology of the first trench 60 and the first mask layer 28, in some embodiments, the specific steps of forming the first filling layer 70 include:

forming the first filling layer 70 that fills the first trench 60 and covers the top surface of the first mask layer 28, as shown in FIG. 7;

Part of the first filling layer 70 is removed, and the top surface of the remaining first filling layer 70 is flush with the top surface of the first mask layer 28, as shown in Fig. 8. In one example, the material of the first filling layer 70 is SOH.

In some embodiments, the specific steps of forming the second etched pattern on the first filling layer 70 and the first etched pattern include:

forming the second mask layer above the first filling layer 70 and the first mask layer 28, as shown in FIG. 9 ;

The second mask layer is etched to form the second trench 110 penetrating the second mask layer along the first direction D1, and a plurality of the second trenches 110 are arranged at intervals along the second direction D2, as shown in FIG11 ;

Forming an initial second spacer layer 120 that continuously covers the inner walls of a plurality of the second trenches 110 and the top surface of the second mask layer, as shown in FIG. 12 ;

The initial second spacer layer 120 covering the bottom wall of the second trench 110 and the top surface of the second mask layer is removed, and the initial second spacer layer 120 retained on the side wall of the second trench 110 is used as the second spacer layer 130, as shown in FIG. 13 .

For example, after forming the first filling layer 70, a fifth mask layer 90 is formed on the top surface of the first filling layer 70 and the first mask layer 28, a sixth mask layer 91 is formed on the surface of the fifth mask layer 90, and the second mask layer is formed on the surface of the sixth mask layer 91. In order to further improve the morphology of the contact hole 200, the second mask layer includes a third sub-mask layer 92 covering the surface of the sixth mask layer 91 and a fourth sub-mask layer 93 covering the surface of the third sub-mask layer 92, as shown in FIG9. In one example, the material of the fifth mask layer 90 is an oxide material (e.g., silicon dioxide), the material of the sixth mask layer 91 is an oxynitride material (e.g., silicon oxynitride), the material of the third sub-mask layer 92 is SOH, and the material of the fourth sub-mask layer 93 is an oxynitride material (e.g., silicon oxynitride). A second photoresist layer 100 is formed on the surface of the fourth mask layer 93, and the second photoresist layer 100 has a second opening 101 exposing the fourth mask layer 93, as shown in FIG10. The second mask layer is etched downward along the second opening 101 to form the second trench 110 that continuously penetrates the third sub-mask layer 92 and the fourth sub-mask layer 93 along the first direction D1, as shown in FIG11. Thereafter, the second spacer layer 130 is formed on the sidewall of the second trench 110, as shown in FIG13.

In some embodiments, before etching the stacked layer using the overlapping region of the third trench 150 and the first mask layer 28 as a mask pattern, the following steps are further included:

A second filling layer is formed to completely fill the second trench 110 .

In some embodiments, the substrate 20 includes a plurality of active regions 140 arranged in an array along the second direction D2 and the third direction D3, the active regions 140 extend along the third direction D3, the third direction D3 is parallel to the top surface of the substrate 20, and the third direction D3 intersects with the second direction D2;

The projection of the third trench 150 on the top surface of the substrate 20 covers the plurality of active regions 140 arranged at intervals along the second direction D2, as shown in FIG. 15 .

FIG. 14 to FIG. 16 are top views of the semiconductor structure during its formation, FIG. 17 is an enlarged view of the square dotted box area in FIG. 16, FIG. 18 is a cross-sectional view along the fifth direction D5 in FIG. 16, and FIG. 19 is a cross-sectional view along the second direction D2 in FIG. 16. Specifically, the plurality of active regions 140 in the substrate 20 are arranged in an array along the second direction D2 and the third direction D3 to form an active region array. In one example, the fifth direction D5 is the extension direction of the bit line, the fourth direction D4 is the extension direction of the word line, the fifth direction D5 and the fourth direction D4 are both parallel to the top surface of the substrate 20, and the fifth direction D5 intersects with the fourth direction D4. The projection of the third trench 150 on the top surface of the substrate 20 covers the multiple active areas 140 arranged at intervals along the second direction D2, so as to increase the overlapping area between the third trench 150 and the active area 140 (that is, the overlapping area between the projection of the third trench 150 on the top surface of the substrate 20 and the projection of one of the active areas 140 on the top surface of the substrate 20), further ensuring that the contact hole 200 finally formed can be aligned with the active area 140.

In some embodiments, the width of the third trench 150 along the third direction D3 is equal to the width of the first mask layer 28 along a fourth direction D4, the fourth direction is parallel to the top surface of the substrate, and the fourth direction D4 intersects both the second direction D2 and the third direction D3.

Specifically, the width of the first mask layer 28 along the fourth direction D4 is a first width L1, and the width of the third trench 150 along the second direction D2 is a second width L2, as shown in FIG17. In this specific embodiment, by setting the first width L1 to be equal to the second width L2, the area of the overlapping region between the contact hole 200 and the active area 140 (i.e., the overlapping region between the projection of the contact hole 200 on the top surface of the substrate 20 and the projection of one of the active areas 140 on the top surface of the substrate 20) formed in the contact hole 200 can be maximized, so as to increase the contact area between the contact plug 210 (see FIG21) subsequently formed in the contact hole 200 and the active area 140, reduce the contact resistance between the contact plug 210 and the active area 140, and further improve the electrical performance of the semiconductor structure. Those skilled in the art can flexibly adjust the first width L1 by adjusting the width of the fourth trench 40 along the second direction D2 and the width of the first spacer layer 41 along the second direction D2, thereby adjusting the characteristic size of the finally formed contact hole 200. Those skilled in the art can flexibly adjust the second width L2 by adjusting the width of the second opening 101 along the second direction D2, thereby adjusting the characteristic size of the finally formed contact hole 200.

In some embodiments, the specific steps of etching the stacked layer using the overlapping area of the third trench 150 and the first mask layer 28 as a mask pattern to form the contact hole 200 exposing the active area 140 include:

Etching the first mask layer 28 downward along the third trench 150 to form an etching window 170 located between adjacent first filling layers 70 and exposing the top surface of the sacrificial stack layer S2, as shown in FIGS. 16 to 19 ;

The sacrificial layer stack S2 and the contact material stack S1 are etched downward along the etching window 170 to form the contact hole 200 exposing the active area 140 , as shown in FIG. 20 .

In this specific embodiment, the stacked layer is etched using the overlapping area of the third groove 150 and the first mask layer 28 formed after removing the second mask layer as a mask pattern, which can avoid the influence of the chamfer at the top of the second sidewall layer 130 on the characteristic size of the contact hole 200 finally formed, thereby further improving the consistency of the morphology and characteristic size of the multiple contact holes 200 formed.

In some embodiments, the active region 140 includes a conductive contact region located in the middle of the active region 140;

The projection of the contact hole 200 on the top surface of the substrate 20 is aligned with the conductive contact region in one of the active regions 140 .

The alignment of the projection of the contact hole 200 on the top surface of the substrate 20 with the conductive contact area in one of the active areas 140 means that the projection of the contact hole 200 on the top surface of the substrate 20 and the projection of the conductive contact area in the middle of the active area 140 on the top surface of the substrate 20 at least partially overlap. In this specific embodiment, by aligning the contact hole 200 with the conductive contact area located in the middle of the active area 140, a plurality of the contact holes 200 correspond to a plurality of the conductive contact areas in the active area 140 one by one, which can not only improve the flexibility of controlling the conductive contact area in the semiconductor structure, but also adapt to the requirement of continuously shrinking the size of the semiconductor structure.

In some embodiments, the projection of the contact hole 200 on the top surface of the substrate 20 is entirely located within the active area 140; or,

The width of the projection of the contact hole 200 on the top surface of the substrate 20 along the second direction D2 is greater than the width of the active region 140 along the second direction D2.

In one example, the projection of the contact hole 200 on the top surface of the substrate 20 is entirely located within the active area 140, so that the active area 140 can be exposed through the contact hole 200, while the characteristic size of the contact hole 200 is further reduced. In another example, the width of the projection of the contact hole 200 on the top surface of the substrate 20 along the second direction D2 is greater than the width of the active area 140 along the second direction D2, so that the active area 140 is fully exposed through the contact hole 200, and the contact area between the contact plug 210 subsequently formed in the contact hole 200 and the active area 140 is increased.

In some embodiments, the projection of the contact hole 200 on the top surface of the substrate 20 is in the shape of an ellipse or a parallelogram.

In some embodiments, the conductive contact region is a bit line contact region 21 , and the contact hole 200 is a bit line contact hole.

In some embodiments, the active region 140 further includes a capacitor contact region 201 located at an end of the active region 140 , and the contact material stack layer S1 is connected to the capacitor contact region 201 .

This specific embodiment also provides a semiconductor structure, and FIG21 is a cross-sectional schematic diagram of the semiconductor structure in the specific embodiment of the present disclosure. The semiconductor structure provided in this specific embodiment can be formed by using the semiconductor structure forming method shown in FIG1-FIG20. As shown in FIG1-FIG21, the semiconductor structure includes:

A substrate 20, wherein the substrate 20 has a plurality of active regions 140, wherein the active regions 140 include a conductive contact region located in the middle of the active regions 140;

A stacking layer, located on the top surface of the substrate 20;

The contact plug 210 penetrates the stacked layer along a first direction D1 and is electrically connected to the conductive contact region. The projection of the contact plug 210 on the top surface of the substrate 20 is aligned with one of the conductive contact regions. The first direction D1 is perpendicular to the top surface of the substrate 20 .

In one example, the contact plug 210 may be formed by filling a conductive material in the contact hole 200 formed by the method for forming a semiconductor structure as shown in FIGS. 1 to 20 .

In some embodiments, the substrate 20 includes a plurality of active regions 140 arranged in an array along the second direction D2 and the third direction D3, the active regions 140 are in the third direction D3, the third direction D3 is parallel to the surface of the substrate 20, and the third direction D3 intersects the second direction D2;

The plurality of contact plugs 210 are electrically connected to the plurality of active regions 140 in a one-to-one correspondence.

In some embodiments, the projection of the contact plug 210 on the top surface of the substrate 20 is entirely located within the active region 140; or,

A width of a projection of the contact plug 210 on the top surface of the substrate 20 along the second direction D2 is greater than a width of the active region 140 along the second direction D2.

In some embodiments, the projection of the contact plug 210 on the top surface of the substrate 20 is in the shape of an ellipse or a parallelogram.

In some embodiments, the conductive contact region is a bit line contact region 21 , and the contact plug 210 is a bit line contact plug.

Some embodiments of the present specific implementation manner provide a semiconductor structure and a method for forming the same. By forming a first etching pattern and a second etching pattern located above the first etching pattern, after removing the second mask layer in the second etching pattern and forming a third groove, a stacked layer is etched using an overlapping area between the third groove and the first mask layer along a first direction as a mask pattern to form a contact hole exposing an active area in a substrate. On the one hand, only one photomask is required to etch the stacked layer to form the contact hole, thereby simplifying the manufacturing process of the semiconductor structure and reducing the manufacturing cost of the semiconductor structure. On the other hand, the contact hole with a smaller feature size can be formed, which helps to further shrink the size of the semiconductor structure.

The above is only a preferred embodiment of the present disclosure. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

A method for forming a semiconductor structure comprises the following steps:

forming a substrate, the substrate comprising a substrate and a stacked layer located on the substrate, the substrate having a plurality of active regions;

Forming a first etching pattern above the stacked layer, the first etching pattern comprising a first mask layer and a first groove penetrating the first mask layer along a first direction, a plurality of the first grooves being arranged at intervals along a second direction, the first direction being perpendicular to the top surface of the substrate, and the second direction being parallel to the top surface of the substrate;

backfilling the first trench to form a first filling layer;

Forming a second etching pattern above the first filling layer and the first etching pattern, wherein the second etching pattern includes a second mask layer, a second trench penetrating the second mask layer along the first direction, and a second sidewall layer covering the sidewall of the second trench, wherein a plurality of the second trenches are arranged at intervals along the second direction;

removing the second mask layer to form a plurality of third trenches spaced apart along the second direction;

The stacked layer is etched using the overlapping area of the third trench and the first mask layer as a mask pattern to form a contact hole exposing the active area.
The method for forming a semiconductor structure according to claim 1, wherein the specific step of forming the substrate comprises:

providing a substrate;

A stacking layer is formed on the top surface of the substrate, wherein the stacking layer includes a contact material stacking layer and a sacrificial stacking layer located above the contact material stacking layer.
The method for forming a semiconductor structure according to claim 2, wherein the specific step of forming a first etching pattern above the stacked layer comprises:

forming a first mask layer above the stacked layer, and forming a third mask layer above the first mask layer;

Etching the third mask layer to form a fourth trench penetrating the third mask layer along the first direction, wherein a plurality of the fourth trenches are arranged at intervals along the second direction;

forming a first spacer layer covering only the sidewall of the fourth trench;

removing the third mask layer to form a fifth trench;

The first mask layer is etched downward along the fifth trench and the retained fourth trench to form a plurality of first trenches.
The method for forming a semiconductor structure according to claim 3, wherein the specific step of forming a first spacer layer covering only the sidewall of the fourth trench comprises:

forming an initial first spacer layer continuously covering inner walls of a plurality of the fourth trenches and a top surface of the third mask layer;

The initial first spacer layer covering the bottom wall of the fourth trench and the top surface of the third mask layer is removed, and the initial first spacer layer on the side wall of the fourth trench is retained as the first spacer layer.
The method for forming a semiconductor structure according to claim 1, wherein the specific step of forming the first filling layer comprises:

forming the first filling layer that fills the first trench and covers the top surface of the first mask layer;

A portion of the first filling layer is removed, and a top surface of the remaining first filling layer is flush with a top surface of the first mask layer.
The method for forming a semiconductor structure according to claim 1, wherein the specific step of forming a second etched pattern above the first filling layer and the first etched pattern comprises:

forming the second mask layer above the first filling layer and the first mask layer;

Etching the second mask layer to form the second groove penetrating the second mask layer along the first direction, wherein a plurality of the second grooves are arranged at intervals along the second direction;

forming the second sidewall layer continuously covering the inner walls of a plurality of the second trenches and the top surface of the second mask layer;

The second spacer layer covering the bottom wall of the second trench and the top surface of the second mask layer is removed, and only the second spacer layer covering the side wall of the second trench is retained.
The method for forming a semiconductor structure according to claim 1, wherein before etching the stacked layer using the overlapping area of the third trench and the first mask layer as a mask pattern, the method further comprises the following steps:

A second filling layer is formed to completely fill the second trench.
The method for forming a semiconductor structure according to claim 2, wherein the substrate comprises a plurality of active regions arranged in an array along the second direction and a third direction, the active regions extend along the third direction, the third direction is parallel to the top surface of the substrate, and the third direction intersects with the second direction;

A projection of the third trench on the top surface of the substrate covers the plurality of active regions spaced apart along the second direction.
The method for forming a semiconductor structure according to claim 8, wherein the width of the third trench along the second direction is equal to the width of the first mask layer along a fourth direction, the fourth direction is parallel to the top surface of the substrate, and the fourth direction intersects with both the second direction and the third direction.
The method for forming a semiconductor structure according to claim 8, wherein the specific step of etching the stacked layer using the overlapping area of the third trench and the first mask layer as a mask pattern to form a contact hole exposing the active area comprises:

Etching the first mask layer downward along the third trench to form an etching window located between adjacent first filling layers and exposing the top surface of the sacrificial stack layer;

The sacrificial layer stack and the contact material stack are etched downward along the etching window to form the contact hole exposing the active area.
The method for forming a semiconductor structure according to claim 8, wherein the active region comprises a conductive contact region located in a middle portion of the active region;

A projection of the contact hole on the top surface of the substrate is aligned with the conductive contact region in one of the active regions.
The method for forming a semiconductor structure according to claim 11, wherein the projection of the contact hole on the top surface of the substrate is entirely located within the active area; or

A width of a projection of the contact hole on the top surface of the substrate along the second direction is greater than a width of the active region along the second direction.
The method for forming a semiconductor structure according to claim 8, wherein the shape of the projection of the contact hole on the top surface of the substrate is an ellipse or a parallelogram.
The method for forming a semiconductor structure according to claim 11, wherein the conductive contact region is a bit line contact region, and the contact hole is a bit line contact hole.
The method for forming a semiconductor structure according to claim 14, wherein the active area further comprises a capacitor contact area located at an end of the active area, and the contact material stack layer is connected to the capacitor contact area.
A semiconductor structure comprising:

A substrate having a plurality of active regions therein, wherein the active regions include a conductive contact region located in the middle of the active regions;

A stacking layer, located on the top surface of the substrate;

A contact plug penetrates the stacked layers along a first direction and is electrically connected to the conductive contact region, wherein a projection of the contact plug on the top surface of the substrate is aligned with one of the conductive contact regions, and the first direction is perpendicular to the top surface of the substrate.
The semiconductor structure according to claim 16, wherein the substrate comprises a plurality of active regions arranged in an array along a second direction and a third direction, the active regions extend along the third direction, the second direction and the third direction are both parallel to the top surface of the substrate, and the third direction intersects with the second direction;

The plurality of contact plugs are electrically connected to the plurality of active regions in a one-to-one correspondence.
The semiconductor structure according to claim 17, wherein the projection of the contact plug on the top surface of the substrate is entirely located within the active region; or

A width of a projection of the contact plug on the top surface of the substrate along the second direction is greater than a width of the active region along the second direction.
The semiconductor structure according to claim 16, wherein the shape of the projection of the contact plug on the top surface of the substrate is an ellipse or a parallelogram.
The semiconductor structure according to claim 16, wherein the conductive contact region is a bit line contact region, and the contact plug is a bit line contact plug.