WO2024105724A1 - Bipolar transistor and method for manufacturing same - Google Patents

Bipolar transistor and method for manufacturing same Download PDF

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WO2024105724A1
WO2024105724A1 PCT/JP2022/042212 JP2022042212W WO2024105724A1 WO 2024105724 A1 WO2024105724 A1 WO 2024105724A1 JP 2022042212 W JP2022042212 W JP 2022042212W WO 2024105724 A1 WO2024105724 A1 WO 2024105724A1
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layer
emitter
forming
base
electrode
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PCT/JP2022/042212
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French (fr)
Japanese (ja)
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悠太 白鳥
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日本電信電話株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors

Definitions

  • the present invention relates to a bipolar transistor and a method for manufacturing the same.
  • Heterojunction bipolar transistors (HBTs) using indium phosphide (InP)-based materials excel in terms of speed and output, and are particularly suited to front-end ICs for large-capacity optical communications, which require ultra-high frequency operation, and ICs for "Beyond 5G" wireless communications. In terms of application, it is necessary to maintain practical reliability and achieve intermittent high-speed operation of HBTs.
  • the base resistance is the sum of the intrinsic base resistance occurring in the base layer directly below the emitter layer, the base access resistance occurring in the base layer from the emitter end to the base electrode end, and the base electrode resistance occurring in the base electrode. In order to reduce these, it is important to miniaturize the element (reducing the emitter width and reducing the distance between the emitter and base electrodes).
  • Non-Patent Document 1 a typical InP-based HBT will be described with reference to Figure 3 (Non-Patent Document 1).
  • This HBT is provided with a substrate 301 made of InP that is highly resistive by doping with Fe, a sub-collector layer 302 made of InGaAs/InP doped with a high concentration of n-type impurities, a collector layer 303 made of InP doped with n-type impurities, a base layer 304 made of InGaAs doped with a high concentration of p-type impurities, and an emitter layer 305 made of InP doped with n-type impurities.
  • an emitter cap layer 306 made of InGaAs doped with a high concentration of n-type impurities is formed on the emitter layer 305.
  • a collector electrode 321 is formed on the sub-collector layer 302 around the collector layer 303, and a base electrode 322 is formed on the base layer 304 around the emitter layer 305.
  • the base electrode 322 is formed surrounding the outer periphery of the emitter layer 305 to reduce the base resistance.
  • An emitter electrode 323 is formed on the emitter cap layer 306.
  • the emitter layer 305 is extended from the emitter mesa portion to form a ledge layer 305a, forming a ledge structure.
  • a protective film 307 made of an insulating material is formed to cover the side surface of the emitter cap layer 306 and the top surface of the ledge layer 305a.
  • the depleted ledge layer 305a prevents electrons injected from the emitter electrode 323 from leaking out from the side of the emitter layer 305 and unintentionally recombining with holes in the base layer 304, improving current gain and long-term reliability.
  • Another method of improving long-term reliability without increasing the ledge width is to thin the ledge layer. Thinning the ledge layer promotes depletion of the ledge, further suppressing leakage current.
  • the ledge layer has already been thinned to about 20 nm, and there is a limit to how thin it can be made further because it could increase the emitter capacitance or, conversely, increase leakage current due to the tunneling phenomenon.
  • the present invention was made to solve the above problems, and aims to improve the high-frequency characteristics of bipolar transistors while ensuring long-term reliability.
  • the bipolar transistor according to the present invention comprises a collector layer made of a compound semiconductor formed on a substrate, a base layer made of a compound semiconductor formed on the collector layer, an emitter layer made of a compound semiconductor formed on the base layer and having an area smaller than that of the base layer in a planar view, an emitter cap layer made of a compound semiconductor formed on the emitter layer and having an area smaller than that of the emitter layer in a planar view, a collector electrode connected to the collector layer, a base electrode formed on the base layer around the emitter layer and spaced apart from the emitter layer, an emitter electrode formed on the emitter cap layer, and a control electrode that applies a voltage to a ledge layer made of the emitter layer around the emitter cap layer.
  • the method for manufacturing a bipolar transistor according to the present invention is a method for manufacturing the bipolar transistor, comprising the steps of: a first step of forming a collector-forming layer made of a compound semiconductor on a substrate; a second step of forming a base-forming layer made of a compound semiconductor on the collector-forming layer; a third step of forming an emitter-forming layer made of a compound semiconductor on the base-forming layer; a fourth step of forming an emitter cap-forming layer made of a compound semiconductor on the emitter-forming layer; a fifth step of forming an emitter electrode on the emitter cap-forming layer by patterning the emitter cap-forming layer using the emitter electrode as a mask to form an emitter electrode on the emitter-forming layer;
  • the method includes a sixth step of forming an emitter cap layer, a seventh step of forming a control electrode after forming the emitter cap layer, an eighth step of forming an emitter layer on the base formation layer by patterning the emitter formation layer after forming the control electrode
  • the present invention provides a control electrode that applies a voltage to the ledge layer, thereby improving the high-frequency characteristics of the bipolar transistor while ensuring long-term reliability.
  • FIG. 1A is a cross-sectional view showing a configuration of a bipolar transistor according to an embodiment of the present invention.
  • FIG. 1B is a cross-sectional view showing a configuration of a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2A is a cross-sectional view showing a state of a bipolar transistor in the middle of a process, for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2B is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 1A is a cross-sectional view showing a configuration of a bipolar transistor according to an embodiment of the present invention.
  • FIG. 1B is a cross-sectional view showing a configuration of a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2A is a cross-sectional view showing a state of
  • FIG. 2C is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2D is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2E is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2F is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2G is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2H is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2I is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2J is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2K is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2I is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2J is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of
  • FIG. 2L is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2M is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2N is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2O is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 2P is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view showing the structure of a heterojunction bipolar transistor.
  • This bipolar transistor first includes a collector layer 103 made of a compound semiconductor formed on a substrate 101, a base layer 104 made of a compound semiconductor formed on the collector layer 103, and an emitter layer 105 made of a compound semiconductor formed on the base layer 104, the emitter layer having an area smaller than that of the base layer 104 in a plan view.
  • the collector layer 103 is formed on the sub-collector layer 102 formed on the substrate 101.
  • the emitter layer 105 is made of a compound semiconductor different from that of the base layer 104, and this bipolar transistor is a heterojunction bipolar transistor.
  • This heterojunction bipolar transistor also includes an emitter cap layer 106 made of a compound semiconductor formed on an emitter layer 105 and formed to have a smaller area than the emitter layer 105 in a planar view.
  • a first mesa that is rectangular in a planar view is formed by a laminated structure of the collector layer 103 and the base layer 104
  • a second mesa that is rectangular in a planar view is formed by a laminated structure of the emitter layer 105 and the emitter cap layer 106.
  • the second mesa has a smaller area than the first mesa in a planar view.
  • the element portion including the collector layer 103, base layer 104, and emitter layer 105 has a rectangular shape (planar shape) whose length in a first direction is longer than its length in a second direction perpendicular to the first direction when viewed from above.
  • Figure 1A shows a cross section of a plane perpendicular to the first direction
  • Figure 1B shows a cross section of a plane perpendicular to the second direction.
  • the heterojunction bipolar transistor also includes a collector electrode 121 connected to the collector layer 103, a base electrode 122 formed on the base layer 104 around the emitter layer 105 and spaced apart from the emitter layer 105, and an emitter electrode 123 formed on the emitter cap layer 106.
  • the emitter electrode 123 is disposed directly above the emitter cap layer 106.
  • the base electrode 122 is formed so as to surround the emitter layer 105 in a plan view.
  • the base electrode 122 includes a connection portion with an upper wiring (not shown).
  • This heterojunction bipolar transistor also has a ledge structure, with a ledge layer 105a formed by the emitter layer 105 around the emitter cap layer 106. Furthermore, this heterojunction bipolar transistor has a control electrode 107 that applies a voltage (electric field) to the ledge layer 105a. The control electrode 107 is formed insulated and separated from the other electrodes.
  • the heterojunction bipolar transistor includes a first insulating layer 108 formed in contact with the side surface of the emitter cap layer 106 and the surface of the ledge layer 105a.
  • the control electrode 107 is formed on the ledge layer 105a via the first insulating layer 108.
  • the first insulating layer 108 prevents the control electrode 107 from contacting the emitter cap layer 106.
  • the total thickness of the first insulating layer 108 on the base layer 104 and the control electrode 107 is made thicker than the base electrode 122.
  • the heterojunction bipolar transistor may further include a second insulating layer 109 formed in contact with the side of the first insulating layer 108 on the side of the emitter cap layer 106 and the upper surface of the control electrode 107.
  • the control electrode 107 and the second insulating layer 109 include a portion that extends in the second direction of the element portion. In this extending portion, a contact hole 109a formed in the second insulating layer 109 allows connection between an upper wiring (not shown) and the control electrode 107.
  • the substrate 101 can be made of, for example, InP that has been doped with Fe to give it high resistance.
  • the subcollector layer 102 can be made of, for example, InGaAs doped with a high concentration of n-type impurities.
  • the subcollector layer 102 can also have a two-layer structure consisting of a layer made of InP on the substrate 101 side and a layer made of InGaAs formed on top of this layer.
  • the collector layer 103 may be made of, for example, InP doped with n-type impurities.
  • the base layer 104 may be made of InGaSb doped with a high concentration of p-type impurities.
  • the emitter layer 105 may be made of InP doped with a low concentration of n-type impurities.
  • the emitter cap layer 106 may be made of InGaAs doped with a high concentration of n-type impurities.
  • the potential of the ledge layer 105a can be controlled by the voltage applied to the control electrode 107.
  • applying a negative bias to the control electrode 107 can promote depletion of the ledge layer 105a, and the ledge leakage current can be suppressed even if the ledge width is reduced. In other words, it is possible to reduce the ledge width while maintaining the current gain and reliability, thereby improving the high frequency characteristics of the element.
  • ledge layer 105a that includes a control electrode 107
  • the current gain variation between different elements can be reduced by adjusting the voltage applied to the control electrode 107 of each element, which is expected to have the effect of reducing characteristic variation in the integrated circuit.
  • Figures 2A to 2G, 2I, 2K, 2M, and 2O show cross sections perpendicular to a first direction
  • Figures 2H, 2J, 2L, 2N, and 2P show cross sections perpendicular to a second direction.
  • This method for manufacturing a bipolar transistor is a method for manufacturing a bipolar transistor (heterojunction bipolar transistor) according to the embodiment described above.
  • a sub-collector forming layer 202, a collector forming layer 203, a base forming layer 204, an emitter forming layer 205, and an emitter cap forming layer 206 are formed by stacking them in this order on a substrate 101 (first step, second step, third step, fourth step).
  • the sub-collector forming layer 202 is formed by crystal growth (epitaxial growth) of InGaAs doped with a high concentration of n-type impurities.
  • the collector forming layer 203 is formed by crystal growth of InP doped with n-type impurities.
  • the base forming layer 204 is formed by crystal growth of InGaSb doped with a high concentration of p-type impurities.
  • the emitter forming layer 205 is formed by crystal growth of InP doped with a low concentration of n-type impurities.
  • the emitter cap forming layer 206 is formed by crystal growth of InGaAs doped with a high concentration of n-type impurities.
  • the thickness, doping concentration, and composition of each of the layers described above are set to optimal values to obtain the desired electrical performance. From the perspective of maximizing the effect of the fine ledge structure, it is desirable to make the thickness of the emitter-forming layer 205, which serves as the emitter layer 105, as thin as possible while still allowing for acceptable electrical characteristics. Specifically, it is desirable for the thickness of the emitter-forming layer 205 to be approximately 10 nm to 20 nm.
  • Each of the layers described above can be formed by well-known methods such as metalorganic vapor phase epitaxy and molecular beam epitaxy.
  • the emitter electrode 123 is formed on the emitter cap formation layer 206 (step 5).
  • a mask having an opening is formed where the emitter electrode 123 is to be formed, and the metal that constitutes the emitter electrode 123 is deposited on top of the mask.
  • the metal can be deposited by sputtering or vacuum deposition. The mask is then removed (lifted off) to form the emitter electrode 123.
  • the emitter cap layer 206 is patterned using the emitter electrode 123 as a mask to form the emitter cap layer 106 on the emitter formation layer 205 as shown in FIG. 2C (sixth step).
  • the emitter cap layer 106 can be formed by etching (wet etching or dry etching) the emitter cap layer 206 using the emitter electrode 123 as a mask.
  • a first insulating film 208 is formed on the emitter formation layer 205 including the emitter electrode 123 and the emitter cap layer 106 (12th step).
  • the first insulating layer 108 is formed from the first insulating film 208.
  • the first insulating film 208 can be formed by depositing an insulating material such as SiN or Al2O3 by chemical vapor deposition (CVD) or atomic layer deposition (ALD ) . Insulating materials such as SiN and Al2O3 can form a relatively good interface with an InP-based compound semiconductor.
  • the thickness of the first insulating film 208 which becomes the first insulating layer 108, affects the efficiency of modulating the ledge potential by the control electrode 107.
  • the thickness of the first insulating film 208 is proportional to the ledge width, it is desirable to form the first insulating film 208 thin as long as the desired insulation properties can be obtained, and a thickness of about 10 nm to 100 nm is desirable.
  • a control electrode forming layer 207 is formed on the first insulating film 208 around the emitter electrode 123 and on the first insulating film 208 above the emitter cap layer 106 (step 13).
  • the control electrode forming layer 207 can be formed by depositing the metal that constitutes the control electrode 107 by a sputtering method or a vacuum deposition method. With this type of deposition method with high vertical anisotropy, metal is not deposited on the sides (side faces) of the mesa structure formed by the emitter cap layer 106 and emitter electrode 123 that have already been formed, but metal is selectively deposited on the surface of the first insulating film 208 that is parallel to the plane of the substrate 101.
  • the material constituting the control electrode forming layer 207 may be any metal that functions as the control electrode 107, such as Pt or Pd, which have a high work function.
  • the control electrode By forming the control electrode from this type of metal, the potential of the surface of the ledge layer 105a, which is made of a compound semiconductor such as InP, can be raised, and the ledge layer 105a can be depleted at a low voltage.
  • the thickness of the control electrode forming layer 207 affects the ledge width, just like the first insulating film 208, so it is desirable for it to be thin.
  • a second insulating film 209 is formed to cover the emitter cap layer 106, the exposed portion of the first insulating film 208 on the side of the mesa structure formed by the emitter electrode 123, and the control electrode forming layer 207 (step 14).
  • the second insulating film 209 can be made of, for example, SiO 2.
  • the second insulating film 209 can be formed on the side of the mesa structure by depositing SiO 2 by chemical vapor deposition.
  • the second insulating film 209 is made of an insulating material different from that of the first insulating film 208 in order to etch the first insulating film 208 using the second insulating layer 109 formed from the second insulating film 209 as a mask.
  • the second insulating film 209 is patterned (etched) to form the second insulating layer 109 as shown in Figures 2G and 2H (step 15).
  • the etching process using dry etching with high vertical anisotropy, it is possible to form the sidewall-shaped second insulating layer 109 on the sides of the mesa structure formed by the emitter cap layer 106 and the emitter electrode 123 as shown in Figure 2G.
  • the above-mentioned etching process can be performed using high-frequency inductively coupled plasma reactive ion etching (ICP-RIE) using fluorine gas.
  • ICP-RIE inductively coupled plasma reactive ion etching
  • a mask pattern 231 is used to form a portion in the sidewall-shaped second insulating layer 109 that extends in a direction parallel to the plane of the substrate 101, as shown in FIG. 2H.
  • control electrode forming layer 207 is etched to form the control electrode 107 as shown in Figures 2I and 2J (seventh step).
  • the control electrode forming layer 207 is etched (patterned) by, for example, reactive ion etching to form the control electrode 107.
  • the dry etching conditions and gas type are adjusted to form a slight undercut in the control electrode 107 that is being formed.
  • the first insulating film 208 is patterned to form the first insulating layer 108 on the side of the emitter cap layer 106 as shown in Figures 2K and 2L (step 16).
  • the first insulating layer 108 can be formed by etching the first insulating film 208 by, for example, reactive ion etching using the second insulating layer 109 (mask pattern 231) as a mask. By this etching, the first insulating layer 108 is also formed on the surface of the portion that will become the ledge layer 105a of the emitter formation layer 205.
  • the first insulating layer 108 is formed in contact with the side of the emitter cap layer 106 and in contact with the surface of the portion that will become the ledge layer 105a of the emitter formation layer 205.
  • a slight undercut is made in the first insulating layer 108 formed under the second insulating layer 109.
  • the emitter-forming layer 205 is patterned to form the emitter layer 105 on the base-forming layer 204 as shown in Figures 2M and 2N (step 8).
  • the emitter-forming layer 205 is wet-etched (patterned) using the mesa formed by the emitter electrode 123, the control electrode 107, the first insulating layer 108, and the second insulating layer 109 as a mask to form the emitter layer 105.
  • the emitter-forming layer 205 made of InP can be selectively etched using a hydrochloric acid-based etching solution without etching the base-forming layer 204 made of InGaSb.
  • the base electrode 122 is formed on the base formation layer 204 around the emitter layer 105 (ninth step). For example, a mask with an opening is formed where the base electrode 122 is to be formed, and the metal that constitutes the base electrode 122 is deposited on top of the mask. For example, the metal can be deposited by sputtering or vacuum deposition. The mask is then removed (lifted off) to form the base electrode 122.
  • the thickness of the base electrode 122 is formed to be thinner than the sum of the thickness of the control electrode 107 and the thickness of the first insulating layer 108. In other words, the total thickness of the first insulating layer 108 and the control electrode 107 on the base layer 104 is formed to be thicker than the base electrode 122.
  • the second insulating layer 109 acts as a canopy, preventing the emitter electrode 123 and the control electrode 107 from contacting the base electrode 122.
  • the base forming layer 204 is patterned to form the base layer 104 on the collector forming layer 203 (step 9).
  • the collector forming layer 203 is patterned to form the collector layer 103 on the sub-collector forming layer 202 (substrate 101) (step 10), and the collector electrode 121 is formed on the sub-collector forming layer 202 (step 11).
  • the sub-collector forming layer 202 is also patterned to form the sub-collector layer 102.
  • a contact hole 109a is formed in the second insulating layer 109 in the portion of the control electrode 107 and the second insulating layer 109 that extends in the second direction of the element portion.
  • the present invention provides a control electrode that applies a voltage to the ledge layer, thereby improving the high-frequency characteristics of the bipolar transistor while ensuring long-term reliability.

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Abstract

This bipolar transistor comprises a collector layer (103) formed on a substrate (101), a base layer (104) formed on the collector layer (103), an emitter layer (105) formed on the base layer (104), and an emitter cap layer (106) formed on the emitter layer (105), includes a ledge layer (105a) in the emitter layer (105) around the emitter cap layer (106) so as to have a ledge structure, and is provided with a control electrode (107) which applies a voltage (electric field) to the ledge layer (105a).

Description

バイポーラトランジスタおよびその製造方法Bipolar transistor and method for manufacturing same
　本発明は、バイポーラトランジスタおよびその製造方法に関する。 The present invention relates to a bipolar transistor and a method for manufacturing the same.
　インジウムリン（ＩｎＰ）系材料を用いたヘテロ接合バイポーラトランジスタ（ＨＢＴ）は、高速・高出力性に優れ、特に超高周波動作が要求される大容量光通信のフロントエンドＩＣや「Beyond 5G」無線通信用ＩＣに適している。アプリケーションの応用上、実用的な信頼性の維持と、断続的なＨＢＴの高速動作化の実現が求められる。 Heterojunction bipolar transistors (HBTs) using indium phosphide (InP)-based materials excel in terms of speed and output, and are particularly suited to front-end ICs for large-capacity optical communications, which require ultra-high frequency operation, and ICs for "Beyond 5G" wireless communications. In terms of application, it is necessary to maintain practical reliability and achieve intermittent high-speed operation of HBTs.
　特に上記用途で要求される最大発振周波数を向上させるためには、エミッタの微細化により真性コレクタ容量を削減するとともに、ベース抵抗を低減することが有効である。ベース抵抗は、エミッタ層の直下のベース層で生じる真性ベース抵抗と、エミッタ端からベース電極端までのベース層で生じるベースアクセス抵抗と、ベース電極で生じるベース電極抵抗との和となる。これらを削減するめには、素子の微細化（エミッタ幅の縮小、エミッタ・ベース電極間隔の縮小）が重要となる。 In particular, to improve the maximum oscillation frequency required for the above applications, it is effective to reduce the intrinsic collector capacitance by miniaturizing the emitter, as well as reducing the base resistance. The base resistance is the sum of the intrinsic base resistance occurring in the base layer directly below the emitter layer, the base access resistance occurring in the base layer from the emitter end to the base electrode end, and the base electrode resistance occurring in the base electrode. In order to reduce these, it is important to miniaturize the element (reducing the emitter width and reducing the distance between the emitter and base electrodes).
　しかしながら、既存技術でＨＢＴの信頼性を維持したまま上記で示したような構造改良により高周波特性の改善を図ることは非常に困難である。 However, it is extremely difficult to improve the high-frequency characteristics of HBTs using the structural improvements described above while maintaining their reliability using existing technology.
　以下、図３を用いて一般的なＩｎＰ系ＨＢＴについて説明する（非特許文献１）。このＨＢＴは、Ｆｅをドープすることで高抵抗とされたＩｎＰからなる基板３０１の上に、ｎ型不純物が高濃度にドープされたＩｎＧａＡｓ／ＩｎＰからなるサブコレクタ層３０２、ｎ型不純物がドープされたＩｎＰからなるコレクタ層３０３、ｐ型不純物が高濃度にドープされたＩｎＧａＡｓからなるベース層３０４、ｎ型不純物がドープされたＩｎＰからなるエミッタ層３０５を備える。また、エミッタ層３０５の上には、ｎ型不純物が高濃度にドープされたＩｎＧａＡｓからなるエミッタキャップ層３０６が形成されている。 Below, a typical InP-based HBT will be described with reference to Figure 3 (Non-Patent Document 1). This HBT is provided with a substrate 301 made of InP that is highly resistive by doping with Fe, a sub-collector layer 302 made of InGaAs/InP doped with a high concentration of n-type impurities, a collector layer 303 made of InP doped with n-type impurities, a base layer 304 made of InGaAs doped with a high concentration of p-type impurities, and an emitter layer 305 made of InP doped with n-type impurities. In addition, an emitter cap layer 306 made of InGaAs doped with a high concentration of n-type impurities is formed on the emitter layer 305.
　また、コレクタ層３０３の周囲のサブコレクタ層３０２の上には、コレクタ電極３２１が形成され、エミッタ層３０５の周囲のベース層３０４の上には、ベース電極３２２が形成されている。ベース電極３２２は、ベース抵抗を低減するためにエミッタ層３０５の外周部を囲って形成されている。また、エミッタキャップ層３０６の上には、エミッタ電極３２３が形成されている。 A collector electrode 321 is formed on the sub-collector layer 302 around the collector layer 303, and a base electrode 322 is formed on the base layer 304 around the emitter layer 305. The base electrode 322 is formed surrounding the outer periphery of the emitter layer 305 to reduce the base resistance. An emitter electrode 323 is formed on the emitter cap layer 306.
　また、ベース層３０４の上のエミッタメサ部分とベース電極３２２との間の領域である外部ベース層の表面に流れる表面再結合電流を抑制するために、エミッタメサの部分よりエミッタ層３０５を延長してレッジ層３０５ａを形成してレッジ構造としている。また、エミッタキャップ層３０６の側面を覆い、レッジ層３０５ａの上面を覆って、絶縁材料から構成された保護膜３０７が形成されている。 In order to suppress the surface recombination current that flows on the surface of the external base layer, which is the region between the emitter mesa portion on the base layer 304 and the base electrode 322, the emitter layer 305 is extended from the emitter mesa portion to form a ledge layer 305a, forming a ledge structure. In addition, a protective film 307 made of an insulating material is formed to cover the side surface of the emitter cap layer 306 and the top surface of the ledge layer 305a.
　このＨＢＴ構造においては、空乏化したレッジ層３０５ａにより、エミッタ電極３２３から注入された電子がエミッタ層３０５の側面側からリークしベース層３０４内の正孔と意図せず再結合する事象を抑制することができ、電流利得の向上並びに長期信頼性を向上させることができる。 In this HBT structure, the depleted ledge layer 305a prevents electrons injected from the emitter electrode 323 from leaking out from the side of the emitter layer 305 and unintentionally recombining with holes in the base layer 304, improving current gain and long-term reliability.
　上述したＨＢＴ構造において、通常、電流利得並びに長期信頼性を向上させるためには、レッジ層の平面視の幅（レッジ幅）を拡大することが有効である。一方で、レッジ幅の拡大は、ベースアクセス抵抗の増大や、コレクタ容量の増大による高周波特性の劣化を招くため、本質的に長期信頼性と高周波特性がトレードオフの関係にある。 In the above-mentioned HBT structure, it is usually effective to increase the width of the ledge layer in a plan view (ledge width) in order to improve the current gain and long-term reliability. However, increasing the ledge width leads to increased base access resistance and increased collector capacitance, degrading high-frequency characteristics, so there is essentially a trade-off between long-term reliability and high-frequency characteristics.
　レッジ幅を増大させることなく、長期信頼性を向上させるその他の方法として、レッジ層の薄層化がある。レッジ層を薄層化することで、レッジの空乏化が進みリーク電流をさらに抑制することができる。しかしながら、近年のＨＢＴにおいては、レッジ層は既に２０ｎｍ程度まで薄層化が進んでおり、これ以上の薄層化はエミッタ容量増大や、逆にトンネル現象によるリーク電流増大を招く恐れがあるため限界がある。このように、従来技術では、バイポーラトランジスタの長期信頼性と高周波特性の向上とを両立することが容易ではないという問題があった。 Another method of improving long-term reliability without increasing the ledge width is to thin the ledge layer. Thinning the ledge layer promotes depletion of the ledge, further suppressing leakage current. However, in recent HBTs, the ledge layer has already been thinned to about 20 nm, and there is a limit to how thin it can be made further because it could increase the emitter capacitance or, conversely, increase leakage current due to the tunneling phenomenon. Thus, with conventional technology, there was a problem in that it was not easy to achieve both long-term reliability and improved high-frequency characteristics in bipolar transistors.
　本発明は、以上のような問題点を解消するためになされたものであり、長期信頼性を確保した上でバイポーラトランジスタの高周波特性を向上させることを目的とする。 The present invention was made to solve the above problems, and aims to improve the high-frequency characteristics of bipolar transistors while ensuring long-term reliability.
　本発明に係るバイポーラトランジスタは、基板の上に形成された化合物半導体からなるコレクタ層と、コレクタ層の上に形成された化合物半導体からなるベース層と、ベース層の上に形成された化合物半導体からなり、平面視でベース層より小さい面積に形成されたエミッタ層と、エミッタ層の上に形成された化合物半導体からなり、平面視でエミッタ層より小さい面積に形成されたエミッタキャップ層と、コレクタ層に接続するコレクタ電極と、エミッタ層の周囲のベース層の上に形成されてエミッタ層とは離間して形成されたベース電極と、エミッタキャップ層の上に形成されたエミッタ電極と、エミッタキャップ層の周囲のエミッタ層によるレッジ層に電圧を印加する制御電極とを備える。 The bipolar transistor according to the present invention comprises a collector layer made of a compound semiconductor formed on a substrate, a base layer made of a compound semiconductor formed on the collector layer, an emitter layer made of a compound semiconductor formed on the base layer and having an area smaller than that of the base layer in a planar view, an emitter cap layer made of a compound semiconductor formed on the emitter layer and having an area smaller than that of the emitter layer in a planar view, a collector electrode connected to the collector layer, a base electrode formed on the base layer around the emitter layer and spaced apart from the emitter layer, an emitter electrode formed on the emitter cap layer, and a control electrode that applies a voltage to a ledge layer made of the emitter layer around the emitter cap layer.
　また、本発明に係るバイポーラトランジスタの製造方法は、上記バイポーラトランジスタの製造方法であって、基板の上に化合物半導体からなるコレクタ形成層を形成する第１工程と、コレクタ形成層の上に化合物半導体からなるベース形成層を形成する第２工程と、ベース形成層の上に化合物半導体からなるエミッタ形成層を形成する第３工程と、エミッタ形成層の上に化合物半導体からなるエミッタキャップ形成層を形成する第４工程と、エミッタキャップ形成層の上にエミッタ電極を形成する第５工程と、エミッタ電極をマスクとしてエミッタキャップ形成層をパターニングして、エミッタ形成層の上にエミッタキャップ層を形成する第６工程と、エミッタキャップ層を形成した後で、制御電極を形成する第７工程と、制御電極を形成した後で、エミッタ形成層をパターニングしてベース形成層の上にエミッタ層を形成する第８工程と、エミッタ層を形成した後で、エミッタ層の周囲のベース形成層の上にベース電極を形成する第９工程と、ベース電極を形成した後で、ベース形成層をパターニングして、コレクタ形成層の上にベース層を形成する第９工程と、ベース層を形成した後で、コレクタ形成層をパターニングして、基板の上にコレクタ層を形成する第１０工程と、コレクタ電極を形成する第１１工程とを備える。 The method for manufacturing a bipolar transistor according to the present invention is a method for manufacturing the bipolar transistor, comprising the steps of: a first step of forming a collector-forming layer made of a compound semiconductor on a substrate; a second step of forming a base-forming layer made of a compound semiconductor on the collector-forming layer; a third step of forming an emitter-forming layer made of a compound semiconductor on the base-forming layer; a fourth step of forming an emitter cap-forming layer made of a compound semiconductor on the emitter-forming layer; a fifth step of forming an emitter electrode on the emitter cap-forming layer by patterning the emitter cap-forming layer using the emitter electrode as a mask to form an emitter electrode on the emitter-forming layer; The method includes a sixth step of forming an emitter cap layer, a seventh step of forming a control electrode after forming the emitter cap layer, an eighth step of forming an emitter layer on the base formation layer by patterning the emitter formation layer after forming the control electrode, a ninth step of forming a base electrode on the base formation layer around the emitter layer after forming the emitter layer, a ninth step of forming a base layer on the collector formation layer after forming the base electrode by patterning the base formation layer, a tenth step of forming a collector layer on the substrate by patterning the collector formation layer after forming the base layer, and an eleventh step of forming a collector electrode.
　以上説明したように、本発明によれば、レッジ層に電圧を印加する制御電極を備えるので、長期信頼性を確保した上でバイポーラトランジスタの高周波特性を向上させることができる。 As described above, the present invention provides a control electrode that applies a voltage to the ledge layer, thereby improving the high-frequency characteristics of the bipolar transistor while ensuring long-term reliability.
図１Ａは、本発明の実施の形態に係るバイポーラトランジスタの構成を示す断面図である。FIG. 1A is a cross-sectional view showing a configuration of a bipolar transistor according to an embodiment of the present invention. 図１Ｂは、本発明の実施の形態に係るバイポーラトランジスタの構成を示す断面図である。FIG. 1B is a cross-sectional view showing a configuration of a bipolar transistor according to an embodiment of the present invention. 図２Ａは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2A is a cross-sectional view showing a state of a bipolar transistor in the middle of a process, for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図２Ｂは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2B is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図２Ｃは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2C is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図２Ｄは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2D is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図２Ｅは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2E is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図２Ｆは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2F is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図２Ｇは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2G is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図２Ｈは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2H is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図２Ｉは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2I is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図２Ｊは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2J is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図２Ｋは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2K is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図２Ｌは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2L is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図２Ｍは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2M is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図２Ｎは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2N is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図２Ｏは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2O is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図２Ｐは、本発明の実施の形態に係るバイポーラトランジスタの製造方法を説明するための途中工程のバイポーラトランジスタの状態を示す断面図である。FIG. 2P is a cross-sectional view showing a state of a bipolar transistor in the middle of a process for explaining a method for manufacturing a bipolar transistor according to an embodiment of the present invention. 図３は、ヘテロ接合バイポーラトランジスタの構成を示す断面図である。FIG. 3 is a cross-sectional view showing the structure of a heterojunction bipolar transistor.
　以下、本発明の実施の形態に係るバイポーラトランジスタについて図１Ａ、図１Ｂを参照して説明する。このバイポーラトランジスタは、まず、基板１０１の上に形成された化合物半導体からなるコレクタ層１０３と、コレクタ層１０３の上に形成された化合物半導体からなるベース層１０４と、ベース層１０４の上に形成された化合物半導体からなり、平面視でベース層１０４より小さい面積に形成されたエミッタ層１０５とを備える。 Below, a bipolar transistor according to an embodiment of the present invention will be described with reference to Figures 1A and 1B. This bipolar transistor first includes a collector layer 103 made of a compound semiconductor formed on a substrate 101, a base layer 104 made of a compound semiconductor formed on the collector layer 103, and an emitter layer 105 made of a compound semiconductor formed on the base layer 104, the emitter layer having an area smaller than that of the base layer 104 in a plan view.
　実施の形態において、コレクタ層１０３は、基板１０１の上に形成されたサブコレクタ層１０２の上に形成されている。また、エミッタ層１０５は、ベース層１０４とは異なる化合物半導体から構成されており、このバイポーラトランジスタは、ヘテロ接合バイポーラトランジスタである。 In the embodiment, the collector layer 103 is formed on the sub-collector layer 102 formed on the substrate 101. The emitter layer 105 is made of a compound semiconductor different from that of the base layer 104, and this bipolar transistor is a heterojunction bipolar transistor.
　また、このヘテロ接合バイポーラトランジスタは、エミッタ層１０５の上に形成された化合物半導体からなり、平面視でエミッタ層１０５より小さい面積に形成されたエミッタキャップ層１０６を備える。コレクタ層１０３とベース層１０４の積層構造により、平面視矩形の第１メサが形成され、エミッタ層１０５とエミッタキャップ層１０６との積層構造により、平面視矩形の第２メサが形成されている。第２メサは、平面視で第１メサより小さい面積とされている。 This heterojunction bipolar transistor also includes an emitter cap layer 106 made of a compound semiconductor formed on an emitter layer 105 and formed to have a smaller area than the emitter layer 105 in a planar view. A first mesa that is rectangular in a planar view is formed by a laminated structure of the collector layer 103 and the base layer 104, and a second mesa that is rectangular in a planar view is formed by a laminated structure of the emitter layer 105 and the emitter cap layer 106. The second mesa has a smaller area than the first mesa in a planar view.
　コレクタ層１０３，ベース層１０４，エミッタ層１０５を含む素子部は、平面視で第１方向の長さが、第１方向と垂直な第２方向の長さより長い矩形（平面形状）とされている。図１Ａは、第１方向に垂直な面の断面を示し、図１Ｂは、第２方向に垂直な面の断面を示している。 The element portion including the collector layer 103, base layer 104, and emitter layer 105 has a rectangular shape (planar shape) whose length in a first direction is longer than its length in a second direction perpendicular to the first direction when viewed from above. Figure 1A shows a cross section of a plane perpendicular to the first direction, and Figure 1B shows a cross section of a plane perpendicular to the second direction.
　また、このヘテロ接合バイポーラトランジスタは、コレクタ層１０３に接続するコレクタ電極１２１と、エミッタ層１０５の周囲のベース層１０４の上に形成されてエミッタ層１０５とは離間して形成されたベース電極１２２と、エミッタキャップ層１０６の上に形成されたエミッタ電極１２３とを備える。エミッタ電極１２３は、エミッタキャップ層１０６の直上に配置されている。ベース電極１２２は、平面視でエミッタ層１０５を囲うように形成されている。また、素子部の第２方向において、ベース電極１２２は、図示しない上部配線との接続部を備える。 The heterojunction bipolar transistor also includes a collector electrode 121 connected to the collector layer 103, a base electrode 122 formed on the base layer 104 around the emitter layer 105 and spaced apart from the emitter layer 105, and an emitter electrode 123 formed on the emitter cap layer 106. The emitter electrode 123 is disposed directly above the emitter cap layer 106. The base electrode 122 is formed so as to surround the emitter layer 105 in a plan view. In addition, in the second direction of the element portion, the base electrode 122 includes a connection portion with an upper wiring (not shown).
　また、このヘテロ接合バイポーラトランジスタは、エミッタキャップ層１０６の周囲のエミッタ層１０５によるレッジ層１０５ａを備えてレッジ構造とされている。さらに、このヘテロ接合バイポーラトランジスタは、レッジ層１０５ａに電圧（電界）を印加する制御電極１０７を備える。制御電極１０７は、他の電極とは絶縁分離して形成されている。 This heterojunction bipolar transistor also has a ledge structure, with a ledge layer 105a formed by the emitter layer 105 around the emitter cap layer 106. Furthermore, this heterojunction bipolar transistor has a control electrode 107 that applies a voltage (electric field) to the ledge layer 105a. The control electrode 107 is formed insulated and separated from the other electrodes.
　また、実施の形態において、このヘテロ接合バイポーラトランジスタは、エミッタキャップ層１０６の側面およびレッジ層１０５ａの表面に接して形成された第１絶縁層１０８を備える。制御電極１０７は、第１絶縁層１０８を介してレッジ層１０５ａの上に形成されている。第１絶縁層１０８により制御電極１０７がエミッタキャップ層１０６に接触することが防止されている。ここで、ベース層１０４の上の第１絶縁層１０８と制御電極１０７との合計の厚さは、ベース電極１２２より厚くされている。 In addition, in the embodiment, the heterojunction bipolar transistor includes a first insulating layer 108 formed in contact with the side surface of the emitter cap layer 106 and the surface of the ledge layer 105a. The control electrode 107 is formed on the ledge layer 105a via the first insulating layer 108. The first insulating layer 108 prevents the control electrode 107 from contacting the emitter cap layer 106. Here, the total thickness of the first insulating layer 108 on the base layer 104 and the control electrode 107 is made thicker than the base electrode 122.
　また、このヘテロ接合バイポーラトランジスタは、エミッタキャップ層１０６の側部における第１絶縁層１０８の側部および制御電極１０７の上面に接して形成された第２絶縁層１０９をさらに備えることができる。制御電極１０７および第２絶縁層１０９は、素子部の第２方向に延在する部分を備える。この延在する部分において、第２絶縁層１０９に形成されたコンタクトホール１０９ａにより、図示しない上部配線と制御電極１０７との接続を可能としている。 The heterojunction bipolar transistor may further include a second insulating layer 109 formed in contact with the side of the first insulating layer 108 on the side of the emitter cap layer 106 and the upper surface of the control electrode 107. The control electrode 107 and the second insulating layer 109 include a portion that extends in the second direction of the element portion. In this extending portion, a contact hole 109a formed in the second insulating layer 109 allows connection between an upper wiring (not shown) and the control electrode 107.
　基板１０１は、例えば、Ｆｅをドープすることで高抵抗とされたＩｎＰから構成することができる。サブコレクタ層１０２は、例えば、ｎ型不純物が高濃度にドープされたＩｎＧａＡｓから構成することができる。また、サブコレクタ層１０２は、基板１０１の側のＩｎＰからなる層と、この層に上に形成されたＩｎＧａＡｓからなる層との２層構造とすることもできる。 The substrate 101 can be made of, for example, InP that has been doped with Fe to give it high resistance. The subcollector layer 102 can be made of, for example, InGaAs doped with a high concentration of n-type impurities. The subcollector layer 102 can also have a two-layer structure consisting of a layer made of InP on the substrate 101 side and a layer made of InGaAs formed on top of this layer.
　コレクタ層１０３は、例えば、ｎ型不純物がドープされたＩｎＰから構成することができる。ベース層１０４は、ｐ型不純物が高濃度にドープされたＩｎＧａＳｂから構成することができる。エミッタ層１０５は、ｎ型不純物が低濃度にドープされたＩｎＰから構成することができる。エミッタキャップ層１０６は、ｎ型不純物が高濃度にドープされたＩｎＧａＡｓから構成することができる。 The collector layer 103 may be made of, for example, InP doped with n-type impurities. The base layer 104 may be made of InGaSb doped with a high concentration of p-type impurities. The emitter layer 105 may be made of InP doped with a low concentration of n-type impurities. The emitter cap layer 106 may be made of InGaAs doped with a high concentration of n-type impurities.
　実施の形態に係るバイポーラトランジスタによれば、制御電極１０７へ印加する電圧により、レッジ層１０５ａのポテンシャルを制御可能となる。典型的には制御電極１０７に負バイアスを印加することで、レッジ層１０５ａの空乏化を促進することができ、レッジ幅を短縮してもレッジリーク電流を抑制することができる。すなわち、電流利得や信頼性を維持したまま、レッジ幅の微細化が可能となり、素子高周波特性を向上させることができる。 In the bipolar transistor according to the embodiment, the potential of the ledge layer 105a can be controlled by the voltage applied to the control electrode 107. Typically, applying a negative bias to the control electrode 107 can promote depletion of the ledge layer 105a, and the ledge leakage current can be suppressed even if the ledge width is reduced. In other words, it is possible to reduce the ledge width while maintaining the current gain and reliability, thereby improving the high frequency characteristics of the element.
　また、微細なレッジ構造においては、素子間のレッジ幅ばらつきに起因した電流利得ばらつきも無視できない課題となる。これに対し、制御電極１０７を備えるレッジ構造（レッジ層１０５ａ）においては、個々の素子の制御電極１０７に対する印加電圧を調整することで、異なる素子間の電流利得ばらつきを低減することができ、集積回路の特性ばらつきを低減する効果も期待できる。 Furthermore, in a fine ledge structure, current gain variation due to ledge width variation between elements is also an issue that cannot be ignored. In contrast, in a ledge structure (ledge layer 105a) that includes a control electrode 107, the current gain variation between different elements can be reduced by adjusting the voltage applied to the control electrode 107 of each element, which is expected to have the effect of reducing characteristic variation in the integrated circuit.
　次に、本発明に係るバイポーラトランジスタの製造方法について、図２Ａ～図２Ｐを参照して説明する。なお、図２Ａ～図２Ｇ，図２Ｉ，図２Ｋ，図２Ｍ，図２Ｏは、第１方向に垂直な面の断面を示し、図２Ｈ，図２Ｊ，図２Ｌ，図２Ｎ，図２Ｐは、第２方向に垂直な面の断面を示している。 Next, a method for manufacturing a bipolar transistor according to the present invention will be described with reference to Figures 2A to 2P. Note that Figures 2A to 2G, 2I, 2K, 2M, and 2O show cross sections perpendicular to a first direction, and Figures 2H, 2J, 2L, 2N, and 2P show cross sections perpendicular to a second direction.
　このバイポーラトランジスタの製造方法は、前述した実施の形態に係るバイポーラトランジスタ（ヘテロ接合バイポーラトランジスタ）の製造方法である。まず、図２Ａに示すように、基板１０１の上に、サブコレクタ形成層２０２、コレクタ形成層２０３、ベース形成層２０４、エミッタ形成層２０５、エミッタキャップ形成層２０６を、これらの順に積層して形成する（第１工程、第２工程、第３工程、第４工程）。 This method for manufacturing a bipolar transistor is a method for manufacturing a bipolar transistor (heterojunction bipolar transistor) according to the embodiment described above. First, as shown in FIG. 2A, a sub-collector forming layer 202, a collector forming layer 203, a base forming layer 204, an emitter forming layer 205, and an emitter cap forming layer 206 are formed by stacking them in this order on a substrate 101 (first step, second step, third step, fourth step).
　例えば、まず、サブコレクタ形成層２０２は、ｎ型不純物が高濃度にドープされたＩｎＧａＡｓを結晶成長（エピタキシャル成長）することで形成する。次に、コレクタ形成層２０３は、ｎ型不純物がドープされたＩｎＰを結晶成長することで形成する。次に、ベース形成層２０４は、ｐ型不純物が高濃度にドープされたＩｎＧａＳｂを結晶成長することで形成する。次に、エミッタ形成層２０５は、ｎ型不純物が低濃度にドープされたＩｎＰを結晶成長することで形成する。次に、エミッタキャップ形成層２０６は、ｎ型不純物が高濃度にドープされたＩｎＧａＡｓを結晶成長することで形成する。 For example, first, the sub-collector forming layer 202 is formed by crystal growth (epitaxial growth) of InGaAs doped with a high concentration of n-type impurities. Next, the collector forming layer 203 is formed by crystal growth of InP doped with n-type impurities. Next, the base forming layer 204 is formed by crystal growth of InGaSb doped with a high concentration of p-type impurities. Next, the emitter forming layer 205 is formed by crystal growth of InP doped with a low concentration of n-type impurities. Next, the emitter cap forming layer 206 is formed by crystal growth of InGaAs doped with a high concentration of n-type impurities.
　上述した各層の厚さ、ドーピング濃度、組成は、所望の電気的性能を得るために最適な値に設定する。なお、微細なレッジ構造の効果を最大化する観点では、エミッタ層１０５とするエミッタ形成層２０５の厚さは、電気的特性が許容できる限りにおいて薄層にすることが望ましい。具体的には、エミッタ形成層２０５の厚さは１０ｎｍ～２０ｎｍ程度が望ましい。なお、上述した各層は、よく知られた有機金属気相成長法や、分子線エピタキシー法などにより形成することができる。 The thickness, doping concentration, and composition of each of the layers described above are set to optimal values to obtain the desired electrical performance. From the perspective of maximizing the effect of the fine ledge structure, it is desirable to make the thickness of the emitter-forming layer 205, which serves as the emitter layer 105, as thin as possible while still allowing for acceptable electrical characteristics. Specifically, it is desirable for the thickness of the emitter-forming layer 205 to be approximately 10 nm to 20 nm. Each of the layers described above can be formed by well-known methods such as metalorganic vapor phase epitaxy and molecular beam epitaxy.
　次に、図２Ｂに示すように、エミッタキャップ形成層２０６の上にエミッタ電極１２３を形成する（第５工程）。例えば、エミッタ電極１２３を形成する箇所に開口を有するマスクを形成し、この上からエミッタ電極１２３を構成する金属を堆積する。例えば、スパッタ法や真空蒸着法などにより金属を堆積することができる。この後、上記マスクを除去（リフトオフ）することで、エミッタ電極１２３を形成することができる。 Next, as shown in FIG. 2B, the emitter electrode 123 is formed on the emitter cap formation layer 206 (step 5). For example, a mask having an opening is formed where the emitter electrode 123 is to be formed, and the metal that constitutes the emitter electrode 123 is deposited on top of the mask. For example, the metal can be deposited by sputtering or vacuum deposition. The mask is then removed (lifted off) to form the emitter electrode 123.
　次に、エミッタ電極１２３をマスクとしてエミッタキャップ形成層２０６をパターニングすることで、図２Ｃに示すように、エミッタ形成層２０５の上にエミッタキャップ層１０６を形成する（第６工程）。例えば、エミッタ電極１２３をマスクとしてエミッタキャップ形成層２０６をエッチング（ウエットエッチングまたはドライエッチング）することで、エミッタキャップ層１０６が形成できる。 Next, the emitter cap layer 206 is patterned using the emitter electrode 123 as a mask to form the emitter cap layer 106 on the emitter formation layer 205 as shown in FIG. 2C (sixth step). For example, the emitter cap layer 106 can be formed by etching (wet etching or dry etching) the emitter cap layer 206 using the emitter electrode 123 as a mask.
　上述したようにエミッタキャップ層１０６を形成した後で、図２Ｄに示すように、エミッタ電極１２３、エミッタキャップ層１０６を含むエミッタ形成層２０５の上に第１絶縁膜２０８を形成する（第１２工程）。第１絶縁膜２０８から、第１絶縁層１０８を形成する。例えば、ＳｉＮやＡｌ2Ｏ3などの絶縁材料を化学的気相成長法（ＣＶＤ）や原子層成長（ＡＬＤ）法により堆積することで、第１絶縁膜２０８が形成できる。ＳｉＮやＡｌ2Ｏ3などの絶縁材料は、ＩｎＰ系の化合物半導体と比較的良好な界面形成が可能である。 After forming the emitter cap layer 106 as described above, as shown in Fig. 2D, a first insulating film 208 is formed on the emitter formation layer 205 including the emitter electrode 123 and the emitter cap layer 106 (12th step). The first insulating layer 108 is formed from the first insulating film 208. For example, the first insulating film 208 can be formed by depositing an insulating material such as SiN or Al2O3 by chemical vapor deposition (CVD) or atomic layer deposition (ALD ) . Insulating materials such as SiN and Al2O3 can form a relatively good interface with an InP-based compound semiconductor.
　第１絶縁層１０８となる第１絶縁膜２０８の厚さは、制御電極１０７によるレッジポテンシャルの変調効率に影響を与える。また、第１絶縁膜２０８の厚さとレッジ幅とは比例することから、所望の絶縁性が得られる限りにおいて、第１絶縁膜２０８は薄く形成することが望まく、厚さ１０ｎｍ～１００ｎｍ程度が望ましい。 The thickness of the first insulating film 208, which becomes the first insulating layer 108, affects the efficiency of modulating the ledge potential by the control electrode 107. In addition, since the thickness of the first insulating film 208 is proportional to the ledge width, it is desirable to form the first insulating film 208 thin as long as the desired insulation properties can be obtained, and a thickness of about 10 nm to 100 nm is desirable.
　次に、図２Ｅに示すように、エミッタ電極１２３の周囲の第１絶縁膜２０８の上、およびエミッタキャップ層１０６の上方の第１絶縁膜２０８の上に制御電極形成層２０７を形成する（第１３工程）。例えば、制御電極１０７を構成する金属を、スパッタ法や真空蒸着法により堆積することで、制御電極形成層２０７が形成できる。この種の垂直異方性の高い堆積法によれば、既に形成されているエミッタキャップ層１０６、エミッタ電極１２３によるメサ構造の側方（側面）には、金属が堆積せず、基板１０１の平面に平行な第１絶縁膜２０８の面に選択的に金属が堆積する。 Next, as shown in FIG. 2E, a control electrode forming layer 207 is formed on the first insulating film 208 around the emitter electrode 123 and on the first insulating film 208 above the emitter cap layer 106 (step 13). For example, the control electrode forming layer 207 can be formed by depositing the metal that constitutes the control electrode 107 by a sputtering method or a vacuum deposition method. With this type of deposition method with high vertical anisotropy, metal is not deposited on the sides (side faces) of the mesa structure formed by the emitter cap layer 106 and emitter electrode 123 that have already been formed, but metal is selectively deposited on the surface of the first insulating film 208 that is parallel to the plane of the substrate 101.
　制御電極形成層２０７を構成する材料は、制御電極１０７として機能する金属であればよく、例えば、仕事関数が高いＰｔ，Ｐｄなどとすることができる。この種の金属から制御電極を構成することで、ＩｎＰなどの化合物半導体から構成されるレッジ層１０５ａの表面のポテンシャルを引き上げることができ、低電圧でレッジ層１０５ａを空乏化させることができる。制御電極形成層２０７の厚さは、第１絶縁膜２０８と同様にレッジ幅に影響するため、薄い方が望ましい。 The material constituting the control electrode forming layer 207 may be any metal that functions as the control electrode 107, such as Pt or Pd, which have a high work function. By forming the control electrode from this type of metal, the potential of the surface of the ledge layer 105a, which is made of a compound semiconductor such as InP, can be raised, and the ledge layer 105a can be depleted at a low voltage. The thickness of the control electrode forming layer 207 affects the ledge width, just like the first insulating film 208, so it is desirable for it to be thin.
　次に、図２Ｆに示すように、エミッタキャップ層１０６、エミッタ電極１２３によるメサ構造の側方の第１絶縁膜２０８の露出部および制御電極形成層２０７を覆って第２絶縁膜２０９を形成する（第１４工程）。第２絶縁膜２０９は、例えば、ＳｉＯ2から構成することができる。例えば、化学的気相成長法によりＳｉＯ2を堆積することで、メサ構造の側方の部分にも、第２絶縁膜２０９が形成できる。後述するように、第２絶縁膜２０９から形成する第２絶縁層１０９をマスクとして第１絶縁膜２０８をエッチング加工するため、第２絶縁膜２０９は、第１絶縁膜２０８とは異なる絶縁材料から構成する。 Next, as shown in FIG. 2F, a second insulating film 209 is formed to cover the emitter cap layer 106, the exposed portion of the first insulating film 208 on the side of the mesa structure formed by the emitter electrode 123, and the control electrode forming layer 207 (step 14). The second insulating film 209 can be made of, for example, SiO 2. For example, the second insulating film 209 can be formed on the side of the mesa structure by depositing SiO 2 by chemical vapor deposition. As will be described later, the second insulating film 209 is made of an insulating material different from that of the first insulating film 208 in order to etch the first insulating film 208 using the second insulating layer 109 formed from the second insulating film 209 as a mask.
　次に、第２絶縁膜２０９をパターニング（エッチング加工）することで、図２Ｇ、図２Ｈに示すように、第２絶縁層１０９を形成する（第１５工程）。例えば、垂直異方性の高いドライエッチングによりエッチング処理をすることで、図２Ｇに示すように、エミッタキャップ層１０６、エミッタ電極１２３によるメサ構造の側方に、側壁状の第２絶縁層１０９を形成することができる。例えば、フッ素ガスを用いた高周波誘導結合プラズマによる反応性イオンエッチング（ＩＣＰ－ＲＩＥ）により、上述したエッチング処理ができる。 Next, the second insulating film 209 is patterned (etched) to form the second insulating layer 109 as shown in Figures 2G and 2H (step 15). For example, by performing the etching process using dry etching with high vertical anisotropy, it is possible to form the sidewall-shaped second insulating layer 109 on the sides of the mesa structure formed by the emitter cap layer 106 and the emitter electrode 123 as shown in Figure 2G. For example, the above-mentioned etching process can be performed using high-frequency inductively coupled plasma reactive ion etching (ICP-RIE) using fluorine gas.
　なお、第１方向における素子部の一端側には上部配線と制御電極１０７との接続部を設けるため、図２Ｈに示すように、マスクパターン２３１を用い、側壁状の第２絶縁層１０９に、基板１０１の平面に平行な方向に延在する部分を形成する。 In order to provide a connection between the upper wiring and the control electrode 107 on one end side of the element portion in the first direction, a mask pattern 231 is used to form a portion in the sidewall-shaped second insulating layer 109 that extends in a direction parallel to the plane of the substrate 101, as shown in FIG. 2H.
　次に、制御電極形成層２０７をエッチング加工することで、図２Ｉ、図２Ｊに示すように、制御電極１０７を形成する（第７工程）。制御電極１０７を形成する工程では、既にエミッタキャップ層１０６が形成されている。第２絶縁層１０９（マスクパターン２３１）をマスクとし、例えば、反応性イオンエッチングにより制御電極形成層２０７をエッチング加工（パターニング）することで、制御電極１０７が形成できる。ここで、ドライエッチング条件やガス種を調整することで、形成される制御電極１０７にわずかにアンダーカットを入れる。 Next, the control electrode forming layer 207 is etched to form the control electrode 107 as shown in Figures 2I and 2J (seventh step). In the step of forming the control electrode 107, the emitter cap layer 106 has already been formed. Using the second insulating layer 109 (mask pattern 231) as a mask, the control electrode forming layer 207 is etched (patterned) by, for example, reactive ion etching to form the control electrode 107. Here, the dry etching conditions and gas type are adjusted to form a slight undercut in the control electrode 107 that is being formed.
　上述したように第２絶縁層１０９を形成し、制御電極１０７を形成した後で、第１絶縁膜２０８をパターニングすることで、図２Ｋ，図２Ｌに示すように、エミッタキャップ層１０６の側面に第１絶縁層１０８を形成する（第１６工程）。第２絶縁層１０９（マスクパターン２３１）をマスクとし、例えば、反応性イオンエッチングにより第１絶縁膜２０８をエッチング加工することで、第１絶縁層１０８が形成できる。このエッチング加工により、エミッタ形成層２０５のレッジ層１０５ａとなる箇所の表面にも、第１絶縁層１０８が形成される。第１絶縁層１０８は、エミッタキャップ層１０６の側面に接し、また、エミッタ形成層２０５のレッジ層１０５ａとなる箇所の表面に接して形成される。ここで、ドライエッチング条件やガス種を調整することで、第２絶縁層１０９の下に形成される第１絶縁層１０８にわずかにアンダーカットを入れる。 After forming the second insulating layer 109 and forming the control electrode 107 as described above, the first insulating film 208 is patterned to form the first insulating layer 108 on the side of the emitter cap layer 106 as shown in Figures 2K and 2L (step 16). The first insulating layer 108 can be formed by etching the first insulating film 208 by, for example, reactive ion etching using the second insulating layer 109 (mask pattern 231) as a mask. By this etching, the first insulating layer 108 is also formed on the surface of the portion that will become the ledge layer 105a of the emitter formation layer 205. The first insulating layer 108 is formed in contact with the side of the emitter cap layer 106 and in contact with the surface of the portion that will become the ledge layer 105a of the emitter formation layer 205. Here, by adjusting the dry etching conditions and gas type, a slight undercut is made in the first insulating layer 108 formed under the second insulating layer 109.
　上述したように制御電極１０７を形成し、第１絶縁層１０８を形成した後で、エミッタ形成層２０５をパターニングすることで、図２Ｍ，図２Ｎに示すように、ベース形成層２０４の上にエミッタ層１０５を形成する（第８工程）。エミッタ電極１２３によるメサ、制御電極１０７、第１絶縁層１０８、第２絶縁層１０９をマスクとしてエミッタ形成層２０５をウエットエッチング（パターニング）することで、エミッタ層１０５が形成できる。ＩｎＰから構成したエミッタ形成層２０５は、塩酸系のエッチング液を用いることで、ＩｎＧａＳｂから構成したベース形成層２０４をエッチングすることなく選択的にエッチングすることができる。 After forming the control electrode 107 and the first insulating layer 108 as described above, the emitter-forming layer 205 is patterned to form the emitter layer 105 on the base-forming layer 204 as shown in Figures 2M and 2N (step 8). The emitter-forming layer 205 is wet-etched (patterned) using the mesa formed by the emitter electrode 123, the control electrode 107, the first insulating layer 108, and the second insulating layer 109 as a mask to form the emitter layer 105. The emitter-forming layer 205 made of InP can be selectively etched using a hydrochloric acid-based etching solution without etching the base-forming layer 204 made of InGaSb.
　上述したようにエミッタ層１０５を形成した後で、図２Ｏ、図２Ｐに示すように、エミッタ層１０５の周囲のベース形成層２０４の上にベース電極１２２を形成する（第９工程）。例えば、ベース電極１２２を形成する箇所に開口を有するマスクを形成し、この上からベース電極１２２を構成する金属を堆積する。例えば、スパッタ法や真空蒸着法などにより金属を堆積することができる。この後、上記マスクを除去（リフトオフ）することで、ベース電極１２２を形成することができる。 After forming the emitter layer 105 as described above, as shown in Figures 2O and 2P, the base electrode 122 is formed on the base formation layer 204 around the emitter layer 105 (ninth step). For example, a mask with an opening is formed where the base electrode 122 is to be formed, and the metal that constitutes the base electrode 122 is deposited on top of the mask. For example, the metal can be deposited by sputtering or vacuum deposition. The mask is then removed (lifted off) to form the base electrode 122.
　ベース電極１２２の厚さは、制御電極１０７の厚さと第１絶縁層１０８の厚さの総和より薄く形成する。言い換えると、ベース層１０４の上の第１絶縁層１０８と制御電極１０７との合計の厚さは、ベース電極１２２より厚く形成する。前述したように、第２絶縁層１０９をマスクとしたエッチング加工において、制御電極１０７および第１絶縁層１０８にアンダーカットを形成しておくことで、第２絶縁層１０９が庇の役目を果たし、エミッタ電極１２３と制御電極１０７が、ベース電極１２２と接触することを防止することができる。 The thickness of the base electrode 122 is formed to be thinner than the sum of the thickness of the control electrode 107 and the thickness of the first insulating layer 108. In other words, the total thickness of the first insulating layer 108 and the control electrode 107 on the base layer 104 is formed to be thicker than the base electrode 122. As described above, by forming undercuts in the control electrode 107 and the first insulating layer 108 during etching using the second insulating layer 109 as a mask, the second insulating layer 109 acts as a canopy, preventing the emitter electrode 123 and the control electrode 107 from contacting the base electrode 122.
　上述したようにベース電極１２２を形成した後で、ベース形成層２０４をパターニングして、コレクタ形成層２０３の上にベース層１０４を形成する（第９工程）。次いで、ベース層１０４を形成した後で、コレクタ形成層２０３をパターニングして、サブコレクタ形成層２０２（基板１０１）の上にコレクタ層１０３を形成し（第１０工程）、サブコレクタ形成層２０２の上にコレクタ電極１２１を形成する（第１１工程）。また、サブコレクタ形成層２０２をパターニングして、サブコレクタ層１０２を形成する。また、制御電極１０７および第２絶縁層１０９の素子部の第２方向に延在する部分において、第２絶縁層１０９にコンタクトホール１０９ａを形成する。 After forming the base electrode 122 as described above, the base forming layer 204 is patterned to form the base layer 104 on the collector forming layer 203 (step 9). Next, after forming the base layer 104, the collector forming layer 203 is patterned to form the collector layer 103 on the sub-collector forming layer 202 (substrate 101) (step 10), and the collector electrode 121 is formed on the sub-collector forming layer 202 (step 11). The sub-collector forming layer 202 is also patterned to form the sub-collector layer 102. Also, a contact hole 109a is formed in the second insulating layer 109 in the portion of the control electrode 107 and the second insulating layer 109 that extends in the second direction of the element portion.
　なお、上述では、超高速集積回路を実現する上で有望なＩｎＰ基板上のｎｐｎ型ＩｎＰ／ＧａＡｓＳｂ系ＨＢＴについて詳細に述べたが、同様な効果は、他のＨＢＴ、具体的にはＩｎＰ／ＩｎＧａＡｓ系ＨＢＴや、ＳｉＣ放熱基板上に形成されたＩｎＰ系ＨＢＴに対しても有効である。 The above describes in detail the npn-type InP/GaAsSb HBT on an InP substrate, which is a promising candidate for realizing ultra-high-speed integrated circuits, but the same effects are also effective for other HBTs, specifically InP/InGaAs HBTs and InP HBTs formed on SiC heat dissipation substrates.
　以上に説明したように、本発明によれば、レッジ層に電圧を印加する制御電極を備えるので、長期信頼性を確保した上でバイポーラトランジスタの高周波特性を向上させることができるようになる。 As described above, the present invention provides a control electrode that applies a voltage to the ledge layer, thereby improving the high-frequency characteristics of the bipolar transistor while ensuring long-term reliability.
　なお、本発明は以上に説明した実施の形態に限定されるものではなく、本発明の技術的思想内で、当分野において通常の知識を有する者により、多くの変形および組み合わせが実施可能であることは明白である。 The present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be implemented by those with ordinary skill in the art within the technical concept of the present invention.
　１０１…基板、１０２…サブコレクタ層、１０３…コレクタ層、１０４…ベース層、１０５…エミッタ層、１０５ａ…レッジ層、１０６…エミッタキャップ層、１０７…制御電極、１０８…第１絶縁層、１０９…第２絶縁層、１０９ａ…コンタクトホール、１２１…コレクタ電極、１２２…ベース電極、１２３…エミッタ電極。 101...substrate, 102...sub-collector layer, 103...collector layer, 104...base layer, 105...emitter layer, 105a...ledge layer, 106...emitter cap layer, 107...control electrode, 108...first insulating layer, 109...second insulating layer, 109a...contact hole, 121...collector electrode, 122...base electrode, 123...emitter electrode.

Claims (7)

  1. 　基板の上に形成された化合物半導体からなるコレクタ層と、
    　前記コレクタ層の上に形成された化合物半導体からなるベース層と、
    　前記ベース層の上に形成された化合物半導体からなり、平面視で前記ベース層より小さい面積に形成されたエミッタ層と、
    　前記エミッタ層の上に形成された化合物半導体からなり、平面視で前記エミッタ層より小さい面積に形成されたエミッタキャップ層と、
    　前記コレクタ層に接続するコレクタ電極と、
    　前記エミッタ層の周囲の前記ベース層の上に形成されて前記エミッタ層とは離間して形成されたベース電極と、
    　前記エミッタキャップ層の上に形成されたエミッタ電極と、
    　前記エミッタキャップ層の周囲の前記エミッタ層によるレッジ層に電圧を印加する制御電極と
    　を備えるバイポーラトランジスタ。     a collector layer made of a compound semiconductor formed on a substrate;
    a base layer made of a compound semiconductor formed on the collector layer;
    an emitter layer made of a compound semiconductor formed on the base layer, the emitter layer having an area smaller than that of the base layer in a plan view;
    an emitter cap layer made of a compound semiconductor and formed on the emitter layer, the emitter cap layer having an area smaller than that of the emitter layer in a plan view;
    a collector electrode connected to the collector layer;
    a base electrode formed on the base layer around the emitter layer and spaced apart from the emitter layer;
    an emitter electrode formed on the emitter cap layer;
    a control electrode for applying a voltage to a ledge layer formed by the emitter layer around the emitter cap layer.
  2. 　請求項１記載のバイポーラトランジスタにおいて、
    　前記エミッタキャップ層の側面および前記レッジ層の表面に接して形成された第１絶縁層を備え、
    　前記制御電極は、前記第１絶縁層を介して前記レッジ層の上に形成されている
    　ことを特徴とするバイポーラトランジスタ。     2. The bipolar transistor according to claim 1,
    a first insulating layer formed in contact with a side surface of the emitter cap layer and a surface of the ledge layer;
    the control electrode is formed on the ledge layer via the first insulating layer,
  3. 　請求項２記載のバイポーラトランジスタにおいて、
    　前記ベース層の上の前記第１絶縁層と前記制御電極との合計の厚さは、前記ベース電極より厚いことを特徴とするバイポーラトランジスタ。     3. The bipolar transistor according to claim 2,
    A bipolar transistor, comprising: a first insulating layer on said base layer and said control electrode; a total thickness of said first insulating layer and said control electrode on said base layer being greater than a total thickness of said base electrode;
  4. 　請求項２または３記載のバイポーラトランジスタにおいて、
    　前記エミッタキャップ層の側部における前記第１絶縁層の側部および前記制御電極の上面に接して形成された第２絶縁層をさらに備えることを特徴とするバイポーラトランジスタ。     4. The bipolar transistor according to claim 2,
    a second insulating layer formed in contact with a side portion of the first insulating layer at a side portion of the emitter cap layer and in contact with an upper surface of the control electrode;
  5. 　基板の上に形成された化合物半導体からなるコレクタ層と、
    　前記コレクタ層の上に形成された化合物半導体からなるベース層と、
    　前記ベース層の上に形成された化合物半導体からなり、平面視で前記ベース層より小さい面積に形成されたエミッタ層と、
    　前記エミッタ層の上に形成された化合物半導体からなり、平面視で前記エミッタ層より小さい面積に形成されたエミッタキャップ層と、
    　前記コレクタ層に接続するコレクタ電極と、
    　前記エミッタ層の周囲の前記ベース層の上に形成されて前記エミッタ層とは離間して形成されたベース電極と、
    　前記エミッタキャップ層の上に形成されたエミッタ電極と、
    　前記エミッタキャップ層の周囲の前記エミッタ層によるレッジ層に電圧を印加する制御電極と
    　を備えるバイポーラトランジスタの製造方法であって、
    　前記基板の上に化合物半導体からなるコレクタ形成層を形成する第１工程と、
    　前記コレクタ形成層の上に化合物半導体からなるベース形成層を形成する第２工程と、
    　前記ベース形成層の上に化合物半導体からなるエミッタ形成層を形成する第３工程と、
    　前記エミッタ形成層の上に化合物半導体からなるエミッタキャップ形成層を形成する第４工程と、
    　前記エミッタキャップ形成層の上に前記エミッタ電極を形成する第５工程と、
    　前記エミッタ電極をマスクとして前記エミッタキャップ形成層をパターニングして、前記エミッタ形成層の上に前記エミッタキャップ層を形成する第６工程と、
    　前記エミッタキャップ層を形成した後で、前記制御電極を形成する第７工程と、
    　前記制御電極を形成した後で、前記エミッタ形成層をパターニングして前記ベース形成層の上に前記エミッタ層を形成する第８工程と、
    　前記エミッタ層を形成した後で、前記エミッタ層の周囲の前記ベース形成層の上に前記ベース電極を形成する第９工程と、
    　前記ベース電極を形成した後で、前記ベース形成層をパターニングして、前記コレクタ形成層の上に前記ベース層を形成する第９工程と、
    　前記ベース層を形成した後で、前記コレクタ形成層をパターニングして、前記基板の上に前記コレクタ層を形成する第１０工程と、
    　前記コレクタ電極を形成する第１１工程と
    　を備えるバイポーラトランジスタの製造方法。     a collector layer made of a compound semiconductor formed on a substrate;
    a base layer made of a compound semiconductor formed on the collector layer;
    an emitter layer made of a compound semiconductor formed on the base layer, the emitter layer having an area smaller than that of the base layer in a plan view;
    an emitter cap layer made of a compound semiconductor and formed on the emitter layer, the emitter cap layer having an area smaller than that of the emitter layer in a plan view;
    a collector electrode connected to the collector layer;
    a base electrode formed on the base layer around the emitter layer and spaced apart from the emitter layer;
    an emitter electrode formed on the emitter cap layer;
    a control electrode for applying a voltage to a ledge layer formed by the emitter layer around the emitter cap layer, the method comprising the steps of:
    a first step of forming a collector-forming layer made of a compound semiconductor on the substrate;
    a second step of forming a base forming layer made of a compound semiconductor on the collector forming layer;
    a third step of forming an emitter-forming layer made of a compound semiconductor on the base-forming layer;
    a fourth step of forming an emitter cap forming layer made of a compound semiconductor on the emitter forming layer;
    a fifth step of forming the emitter electrode on the emitter cap forming layer;
    a sixth step of patterning the emitter cap formation layer using the emitter electrode as a mask to form the emitter cap layer on the emitter formation layer;
    a seventh step of forming the control electrode after forming the emitter cap layer;
    an eighth step of patterning the emitter-forming layer to form the emitter layer on the base-forming layer after forming the control electrode;
    a ninth step of forming the base electrode on the base forming layer around the emitter layer after forming the emitter layer;
    a ninth step of patterning the base forming layer after forming the base electrode to form the base layer on the collector forming layer;
    a tenth step of patterning the collector-forming layer after forming the base layer to form the collector layer on the substrate;
    and an eleventh step of forming the collector electrode.
  6. 　請求項５記載のバイポーラトランジスタの製造方法において、
    　前記エミッタキャップ層を形成した後で、前記エミッタ電極、前記エミッタキャップ層を含む前記エミッタ形成層の上に第１絶縁膜を形成する第１２工程と、
    　前記エミッタ電極の周囲の前記第１絶縁膜の上、および前記エミッタキャップ層の上方の前記第１絶縁膜の上に制御電極形成層を形成する第１３工程と、
    　前記第１絶縁膜の露出部および前記制御電極形成層を覆って第２絶縁膜を形成する第１４工程と、
    　前記第２絶縁膜をパターニングして前記エミッタ電極および 前記エミッタキャップ層の側方に第２絶縁層を形成する第１５工程と、
    　前記第２絶縁層を形成した後で前記第１絶縁膜をパターニングして、前記エミッタキャップ層の側面および前記レッジ層の表面に接して形成された第１絶縁層を形成する第１６工程とを備え、
    　前記第７工程は、前記第２絶縁層をマスクとして前記制御電極形成層をパターニングすることで前記制御電極を形成し、
    　前記第８工程は、前記第１絶縁層をマスクとして前記エミッタ形成層をパターニングすることで前記エミッタ層を形成する
    　ことを特徴とするバイポーラトランジスタの製造方法。     6. The method for manufacturing a bipolar transistor according to claim 5,
    a twelfth step of forming a first insulating film on the emitter formation layer including the emitter electrode and the emitter cap layer after forming the emitter cap layer;
    a thirteenth step of forming a control electrode forming layer on the first insulating film around the emitter electrode and on the first insulating film above the emitter cap layer;
    a fourteenth step of forming a second insulating film to cover the exposed portion of the first insulating film and the control electrode formation layer;
    a fifteenth step of patterning the second insulating film to form a second insulating layer on the sides of the emitter electrode and the emitter cap layer;
    and a sixteenth step of patterning the first insulating film after forming the second insulating layer to form a first insulating layer in contact with a side surface of the emitter cap layer and a surface of the ledge layer,
    the seventh step includes forming the control electrode by patterning the control electrode formation layer using the second insulating layer as a mask;
    the eighth step comprises forming the emitter layer by patterning the emitter formation layer using the first insulating layer as a mask.
  7. 　請求項６記載のバイポーラトランジスタの製造方法において、
    　前記ベース層の上の前記第１絶縁層と前記制御電極との合計の厚さは、前記ベース電極より厚く形成することを特徴とするバイポーラトランジスタの製造方法。     7. The method of manufacturing a bipolar transistor according to claim 6,
    a first insulating layer formed on said base layer and said control electrode formed on said base layer, the first insulating layer being thicker than said base electrode;
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JP2011176171A (en) * 2010-02-25 2011-09-08 Nippon Telegr & Teleph Corp <Ntt> Bipolar transistor, and method of manufacturing the same
JP2011233617A (en) * 2010-04-26 2011-11-17 Nippon Telegr & Teleph Corp <Ntt> Manufacturing method of semiconductor device
JP2014120503A (en) * 2012-12-13 2014-06-30 Nippon Telegr & Teleph Corp <Ntt> Heterojunction bipolar transistor
JP2018018876A (en) * 2016-07-26 2018-02-01 日本電信電話株式会社 Heterojunction bipolar transistor

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001135642A (en) * 1999-11-04 2001-05-18 Nippon Telegr & Teleph Corp <Ntt> Heterojunction bipolar transistor and its manufacturing method
JP2011176171A (en) * 2010-02-25 2011-09-08 Nippon Telegr & Teleph Corp <Ntt> Bipolar transistor, and method of manufacturing the same
JP2011233617A (en) * 2010-04-26 2011-11-17 Nippon Telegr & Teleph Corp <Ntt> Manufacturing method of semiconductor device
JP2014120503A (en) * 2012-12-13 2014-06-30 Nippon Telegr & Teleph Corp <Ntt> Heterojunction bipolar transistor
JP2018018876A (en) * 2016-07-26 2018-02-01 日本電信電話株式会社 Heterojunction bipolar transistor

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