WO2024103311A1 - 探测基板及其控制方法、探测装置、打印装置 - Google Patents

探测基板及其控制方法、探测装置、打印装置 Download PDF

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Publication number
WO2024103311A1
WO2024103311A1 PCT/CN2022/132357 CN2022132357W WO2024103311A1 WO 2024103311 A1 WO2024103311 A1 WO 2024103311A1 CN 2022132357 W CN2022132357 W CN 2022132357W WO 2024103311 A1 WO2024103311 A1 WO 2024103311A1
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Prior art keywords
substrate
transistor
charge
layer
detection substrate
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PCT/CN2022/132357
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English (en)
French (fr)
Inventor
孟凡理
李泽源
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京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/132357 priority Critical patent/WO2024103311A1/zh
Priority to CN202280004348.0A priority patent/CN118355502A/zh
Publication of WO2024103311A1 publication Critical patent/WO2024103311A1/zh

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03G—ELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G5/00—Recording members for original recording by exposure, e.g. to light, to heat, to electrons; Manufacture thereof; Selection of materials therefor
    • G03G5/02—Charge-receiving layers
    • G03G5/04—Photoconductive layers; Charge-generation layers or charge-transporting layers; Additives therefor; Binders therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures

Definitions

  • the present application relates to the field of detection technology, and in particular to a detection substrate and a preparation method thereof, a detection device, and a printing device.
  • detection substrates or detection devices have broad application prospects in the fields of industrial non-destructive testing, container scanning, circuit board inspection, medical treatment, security, etc.
  • current detection technology is usually based on the conversion process of optical signals to electrical signals.
  • the optical signal has a great influence on the accuracy of detection, and the optical signal is easily interfered by external light.
  • an embodiment of the present application provides a detection substrate, comprising:
  • a plurality of data lines extending along a first direction and a plurality of gate lines extending along a second direction are located on the substrate; the first direction intersects with the second direction;
  • the sub-pixel includes a control unit and a charge distribution unit, the control unit is electrically connected to the data line and the gate line respectively, the charge distribution unit includes a first electrode and a charge transfer layer, the first electrode is electrically connected to the control unit, and the orthographic projection of the charge transfer layer on the substrate covers the orthographic projection of the first electrode on the substrate; the charge distribution unit is configured to be able to discharge under the control of the control unit.
  • the detection substrate further includes a first signal line, the first signal line is electrically connected to the control unit, and when the charge distribution unit is in a fully charged state, the voltage of the signal transmitted in the first signal line is less than the voltage of the first electrode;
  • the first signal line is configured to transmit a signal with a constant voltage
  • the charge distribution unit is configured to discharge to the first signal line along the control unit under the control of the control unit.
  • the first signal line includes a ground line or a negative power signal line.
  • control unit includes at least two transistors, one of the transistors is electrically connected to the data line, and the other of the transistors is electrically connected to the first signal line.
  • the charge distribution unit also includes a buffer layer and a charge injection layer, the buffer layer is located between the first electrode and the charge transport layer, and the charge injection layer is located between the buffer layer and the charge transport layer; wherein the polarity of the charge injected by the charge injection layer is the same as the polarity of the charge transported by the charge transport layer.
  • the control unit includes a first transistor and a second transistor, the gate of the first transistor is electrically connected to the data line, the first end of the first transistor is electrically connected to the first electrode, and the second end of the first transistor is electrically connected to the first end of the second transistor; the gate of the second transistor is electrically connected to the gate line, and the second end of the second transistor is electrically connected to the first signal line.
  • the control unit includes a first transistor and a second transistor, the gate of the first transistor is electrically connected to the data line, the first end of the first transistor is electrically connected to the first electrode, and the second end of the first transistor is shared with the first end of the second transistor; the gate of the second transistor is electrically connected to the gate line, and the second end of the second transistor is electrically connected to the first signal line.
  • the control unit includes a first transistor and a second transistor, the gate of the first transistor is electrically connected to the gate line, the first end of the first transistor is electrically connected to the data line, and the second end of the first transistor is electrically connected to the gate of the second transistor; the first end of the second transistor is electrically connected to the first electrode, and the second end of the second transistor is electrically connected to the first signal line.
  • the charge transport layer includes a hole transport layer, and each of the transistors in the control unit is a P-type transistor.
  • the charge transport layer includes an electron transport layer
  • each of the transistors in the control unit is an N-type transistor.
  • the detection substrate includes:
  • a first conductive layer located on one side of the substrate, the first conductive layer comprising a gate line and a gate of each of the transistors;
  • a semiconductor layer located on a side of the first conductive layer away from the substrate and insulated from the first conductive layer, wherein the semiconductor layer includes an active region of each of the transistors;
  • a second conductive layer located on a side of the semiconductor layer away from the substrate, including the data line and the source and drain of each transistor;
  • the orthographic projection of the gate of at least one of the transistors in the control unit on the substrate partially overlaps with the orthographic projection of the active region on the substrate.
  • an orthographic projection of the gate of the first transistor on the substrate partially overlaps with an orthographic projection of the active region on the substrate;
  • the active region of the first transistor includes a plurality of active portions and a first bending portion connecting two adjacent active portions, and an orthographic projection of a portion of the first bending portion on the substrate is located within an orthographic projection of the gate on the substrate.
  • an orthographic projection of the gate of the first transistor on the substrate partially overlaps with an orthographic projection of the active region on the substrate;
  • the active area of the first transistor includes a plurality of active portions
  • the second conductive layer includes a plurality of second bending portions, and two adjacent active portions are electrically connected via the second bending portions; the orthographic projection of the second bending portion on the substrate does not overlap with the orthographic projection of the gate on the substrate.
  • a detection substrate provided in an embodiment of the present application, there is a gap between two adjacent active portions, and the orthographic projection of the gate on the substrate at least partially overlaps with an area defined by the orthographic projection of a portion of the outer contour of the gap on the substrate.
  • the detection substrate further comprises a pixel definition layer and a plurality of pixel partition structures, wherein the pixel definition layer is located on a side of the first electrode away from the substrate; the charge transfer layer is located on a side of the pixel definition layer away from the substrate;
  • the pixel definition layer includes a plurality of first openings and a plurality of second openings, the orthographic projection of the first electrode on the substrate overlaps with the area enclosed by the orthographic projection of the outer contour of the first opening on the substrate, and the orthographic projection of the pixel partition structure on the substrate overlaps with the area enclosed by the orthographic projection of the outer contour of the second opening on the substrate;
  • the pixel partition structure is located between two adjacent sub-pixels, and the charge transfer layer is disconnected at the position of the pixel partition structure.
  • the substrate is a flexible substrate.
  • the charge transport layers in each of the sub-pixels are located in the same plane;
  • the charge transfer layers in each of the sub-pixels are located on the same curved surface, and the three-dimensional shape of the detection substrate in the second state includes a cylinder.
  • the detection substrate further comprises a first insulating layer, an organic layer, and a second insulating layer stacked in sequence, the first insulating layer covers each of the control units, and the second insulating layer is located on a side of each of the first electrodes close to the substrate;
  • the first insulating layer is provided with a plurality of grooves in a region between two adjacent control units, and the organic layer extends into the grooves.
  • the material of the semiconductor layer includes metal oxide
  • the detection substrate also includes an etch stop layer
  • the etch stop layer covers the semiconductor layer
  • the second conductive layer is located on a side of the etch stop layer away from the substrate.
  • an embodiment of the present application provides a detection device, comprising a detection substrate as described in any one of the first aspects.
  • an embodiment of the present application provides a printing device, comprising a detection substrate as described in any one of the first aspects, and also comprising a charging device and a driving chip, wherein the charging device is configured to charge the charge distribution unit of the detection substrate, and the driving chip is configured to transmit a control signal to the detection substrate.
  • an embodiment of the present application provides a control method for detecting a substrate, which is applied to the detection substrate as described in any one of the first aspects, and the method comprises:
  • a second control signal is inputted into the control unit of some of the sub-pixels, wherein the second control signal is configured to control the charge distribution unit of the sub-pixel to retain the charge; and the detection substrate having a charge pattern is obtained.
  • FIG1 is a schematic diagram of the printing principle of a laser printer in a related art provided by an embodiment of the present application
  • FIG2 is a schematic diagram of an exposure discharge process in a related technology provided by an embodiment of the present application.
  • 3 to 6 are schematic structural diagrams of four detection substrates provided in embodiments of the present application.
  • FIG. 7 and 8 are diagrams illustrating charging of two detection substrates provided in embodiments of the present application.
  • 9-11 are schematic circuit diagrams of three detection substrates provided in embodiments of the present application.
  • 16 and 17 are schematic structural diagrams of two detection substrates provided in embodiments of the present application.
  • FIG20 is a flow chart of a control method for detecting a substrate provided in an embodiment of the present application.
  • 21-24 are intermediate structure diagrams of the detection substrate preparation method provided in the embodiments of the present application.
  • the term “including” is to be interpreted as an open, inclusive meaning, that is, “including, but not limited to”.
  • the terms “one embodiment”, “some embodiments”, “exemplary embodiment”, “example”, “specific example” or “some examples” and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application.
  • the schematic representation of the above terms does not necessarily refer to the same embodiment or example.
  • the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • the polygon in this specification is not a strict polygon, and can be an approximate triangle, rectangle, trapezoid, pentagon or hexagon, etc. There can be some small deformations caused by tolerances, and there can be chamfers, rounded corners, arc edges and deformations.
  • electrostatic printing mainly includes the following steps: imaging (charging, exposure), inking (development), toner transfer (transfer), fixing, and cleaning.
  • Imaging is to form a charge pattern by charging a suitable photosensitive surface (such as the photosensitive surface OPC of the photosensitive drum) and controlling the light source exposure;
  • the development process is as follows: when the photosensitive drum charged at a specific position passes through the ink cartridge, due to the electrostatic adsorption effect, the charged position of the photosensitive drum will adsorb a certain amount of toner, and at this time the pattern on the photosensitive drum is the pattern we need, thereby forming a printed image; wherein the printed image corresponds to the position of the light signal on the photoconductive drum (photosensitive drum).
  • the photosensitive body is the photosensitive material on the photosensitive drum.
  • the resistivity is very high, which is similar to an insulator. After being exposed to light, it will quickly become a conductor.
  • the process of forming a charge pattern refers to: through exposure, a part of the surface of the uniformly charged photosensitive body is discharged (the resistance of the illuminated area becomes smaller and the charge disappears, as shown in Figure 2, the charge of the area marked -70V gradually disappears), so that the exposed area is consistent with the area of the required printed image. This process requires high precision in controlling light, and the exposure process is easily disturbed by external light.
  • the structure shown in FIG2 is the surface structure of the photosensitive drum in FIG1.
  • an embodiment of the present application provides a detection substrate and a preparation method thereof, a detection device, and a printing device
  • the detection substrate includes: a substrate; a plurality of data lines extending along a first direction and a plurality of gate lines extending along a second direction on the substrate; the first direction intersects with the second direction; a plurality of sub-pixels arranged in an array, the sub-pixels being located at positions defined by the data lines and the gate lines, the sub-pixels being electrically connected to the data lines and the gate lines, respectively; wherein the sub-pixels include a control unit and a charge distribution unit, the control unit being electrically connected to the data lines and the gate lines, respectively, the charge distribution unit including a first electrode and a charge transfer layer, the first electrode being electrically connected to the control unit, the orthographic projection of the charge transfer layer on the substrate covering the orthographic projection of the first electrode on the substrate; the charge distribution unit is configured to be able to discharge under the control of the control unit.
  • each sub-pixel includes a control unit and a charge distribution unit, so that the control unit is electrically connected to the charge distribution unit, and in each sub-pixel, the control unit can control the charge distribution unit to discharge.
  • control units of some sub-pixels can be set to control the charge distribution unit to discharge, and the control units of some sub-pixels can be set to control the charge distribution unit not to discharge, thereby forming a charge pattern, realizing the control of the charge pattern by electrical signals, providing a new electrostatic imaging method, and avoiding the problem of low exposure accuracy caused by interference from external light when forming a charge pattern by controlling the exposure of a light source in the related art.
  • An embodiment of the present application provides a detection substrate, comprising: a substrate 1;
  • a plurality of data lines DL extending along a first direction and a plurality of gate lines GL extending along a second direction are located on the substrate 1 ; the first direction intersects the second direction;
  • a plurality of sub-pixels P arranged in an array the sub-pixels P are located at positions defined by the data lines DL and the gate lines GL, and the sub-pixels P are electrically connected to the data lines DL and the gate lines GL respectively;
  • the sub-pixel P includes a control unit KZ and a charge distribution unit DH
  • the control unit KZ is electrically connected to the data line DL and the gate line GL respectively
  • the charge distribution unit DH includes a first electrode 9 and a charge transfer layer 10, the first electrode 9 is electrically connected to the control unit KZ, and the orthographic projection of the charge transfer layer 10 on the substrate 1 covers the orthographic projection of the first electrode 9 on the substrate 1; the charge distribution unit DH is configured to be able to discharge under the control of the control unit KZ.
  • the material of the substrate 1 can be a rigid material, such as ordinary optical glass or silicon material; wherein the silicon material substrate can be a P-type single crystal silicon substrate, or an N-type single crystal silicon substrate, which can be determined according to the actual product.
  • the material of the substrate 1 may be a flexible material, such as ultra-thin glass, polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film.
  • the substrate 1 may include a single-layer flexible material layer; or, the substrate 1 may include a first flexible material layer, a first inorganic non-metallic material layer, and a second flexible material layer stacked in sequence.
  • the materials of the first flexible material layer and the second flexible material layer are polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film.
  • the material of the first inorganic non-metallic material layer is a single-layer structure of silicon nitride (SiNx), a single-layer structure of silicon oxide (SiOx), or a stacked structure of silicon nitride and silicon oxide, etc., which are used to improve the water and oxygen resistance of the detection substrate, thereby improving the service life of the detection substrate.
  • the specific number of the data lines DL and the gate lines GL is not limited here.
  • the number of the data lines DL and the gate lines GL is related to the size of the detection substrate and the pixel distribution density (PPI) of the sub-pixels, and can be determined according to the design of the actual product.
  • PPI pixel distribution density
  • the specific angle at which the first direction and the second direction intersect is not limited here.
  • the first direction may be a vertical direction
  • the second direction may be a horizontal direction
  • the first direction and the second direction are perpendicular.
  • the angle at which the first direction and the second direction intersect may also be an acute angle.
  • the specific materials of the gate lines GL and the data lines DL are not limited here.
  • the material of the gate line GL may include molybdenum, copper, aluminum, etc.
  • a Mo/Al/Mo stacked structure may be formed by sputtering, wherein the material on the side close to the substrate is Mo with a thickness of about 1000 nm. It is mainly used to improve the adhesion between film layers.
  • the middle layer material of the laminated structure is Al, which is the material of the electrical signal transmission channel.
  • the material on the side away from the substrate 1 is Mo, with a thickness of about It can be used to protect the middle layer and prevent the low resistivity middle layer from being exposed and oxidized.
  • a MoNb/Cu/MoNb stacked structure can be formed by sputtering, where the material on the side close to the substrate is MoNb with a thickness of about It is mainly used to improve the adhesion between film layers.
  • the middle layer material of the laminated structure is Cu, which is the material of the electrical signal transmission channel.
  • the material on the side away from the substrate 1 is MoNb, with a thickness of about It can be used to protect the middle layer and prevent the surface of the middle layer with low resistivity from being exposed and oxidized. Since the thickness of a single sputtering generally does not exceed 1 ⁇ m, multiple sputterings are required to form the gate line GL with a thickness exceeding 1 ⁇ m.
  • a seed layer such as Cu or Ag
  • a seed layer can be formed first as a seed layer (wherein Ti or a similar alloy material can be pre-deposited as an adhesion layer of the seed layer), and then copper with low resistivity is produced by electroplating, and then an anti-oxidation layer is produced.
  • the material of the data lines DL may be the same as that of the gate lines GL.
  • the figure of the orthographic projection of the sub-pixel P on the substrate 1 includes at least one of a polygon, an arc, and a combination of a polygon and an arc, wherein the combination of a polygon and an arc includes: a figure formed by splicing a polygon and an arc, or a figure obtained by cutting out a local area on a polygon or an arc.
  • the orthographic projection patterns of each sub-pixel P on the substrate 1 may be set to be the same;
  • a plurality of sub-pixels P may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein the orthographic projection patterns of the first sub-pixel, the second sub-pixel, and the third sub-pixel on the substrate 1 are different.
  • the control unit KZ includes a pixel circuit to control the discharge of the charge distribution unit DH through the pixel circuit, and the pixel circuit includes a plurality of electrical components, such as transistors.
  • the specific electrical components included in the control unit KZ and the electrical connection method between the electrical components are not limited here.
  • the first electrode 9 in the charge distribution unit DH is not limited here.
  • the first electrode 9 can be made of metal materials, such as any one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo); or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), which can be a single-layer structure or a multi-layer structure, such as Ti/Al/Ti, etc.; or transparent conductive materials, such as ITO, IZO; or, a stacked structure formed by metal and transparent conductive materials, such as ITO/Ag/ITO, Mo/AlNd/ITO and other materials.
  • metal materials such as any one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo); or alloy materials of the above metals, such as
  • the charge transport layer 10 may include a hole transport layer; in other embodiments, the charge transport layer 10 may include an electron transport layer.
  • the orthographic projection of the charge transport layer 10 on the substrate 1 covers the orthographic projection of the first electrode 9 on the substrate 1, which means that: in the same sub-pixel, the orthographic projection of the first electrode 9 on the substrate 1 is located within the orthographic projection of the charge transport layer 10 on the substrate 1, including but not limited to the following situations: the outer contour of the orthographic projection of the first electrode 9 on the substrate 1 is located within the outer contour of the orthographic projection of the charge transport layer 10 on the substrate 1, at this time, the area of the orthographic projection of the charge transport layer 10 on the substrate 1 is greater than the area of the orthographic projection of the first electrode 9 on the substrate 1; or, the outer contour of the orthographic projection of the first electrode 9 on the substrate 1 overlaps with the outer contour of the orthographic projection of the charge transport layer 10 on the substrate 1, at this time, the area of the orthographic projection of the charge transport layer 10 on the substrate 1 is equal to the area of the orthographic projection of the first electrode 9 on the substrate 1.
  • each sub-pixel P includes a control unit KZ and a charge distribution unit DH, so that the control unit KZ is electrically connected to the charge distribution unit DH, and in each sub-pixel P, the control unit KZ can control the charge distribution unit DH to discharge.
  • control unit KZ of some sub-pixels can be set to control the charge distribution unit DH to discharge, and the control unit KZ of some sub-pixels can be set to control the charge distribution unit DH not to discharge, thereby forming a charge pattern, realizing the control of the charge pattern by an electrical signal, providing a new electrostatic imaging method, avoiding the problem of low exposure accuracy caused by interference from external light when forming a charge pattern by controlling light source exposure in the related art, and improving the accuracy of forming the charge pattern.
  • the detection substrate When the detection substrate is used in a printing device, the printing accuracy and print clarity can be improved, and the printing blur caused by interference from external light during the exposure process can be avoided; in addition, in the printing device, the shading component in the related art can be omitted, simplifying the design of the printing device and reducing the cost.
  • the detection substrate also includes a first signal line (for example, a VSS line), which is electrically connected to the control unit KZ, and when the charge distribution unit DH is in a fully charged state, the voltage of the signal transmitted in the first signal line is less than the voltage of the first electrode 9; wherein the first signal line is configured to be able to transmit a signal with a constant voltage, and the charge distribution unit DH is configured to be able to discharge to the first signal line along the control unit KZ under the control of the control unit.
  • a first signal line for example, a VSS line
  • the state where the charge distribution unit DH is in full charge includes two situations: the charge distribution unit DH is in a state where the charge distribution unit DH is in full charge with a positive charge; or the charge distribution unit DH is in a state where the charge distribution unit DH is in full charge with a negative charge.
  • the state in which the charge distribution unit DH is fully charged refers to the state after the detection substrate has been fully charged.
  • a high voltage can be used to energize the charging roller, and the charging roller is brought into contact with the surface of the charge transport layer 10 of the detection substrate.
  • the surface of the charge transport layer 10 of the detection substrate will carry a uniform charge (positive charge or negative charge), and the polarity of the charge on the surface of the charge transport layer 10 is the same as the polarity of the voltage energized by the charging roller.
  • the specific charging process of the detection substrate can refer to the charging process of the printer in the related art, which will not be described in detail here.
  • the first signal line includes a ground line GND or a negative power signal line VSS.
  • control unit KZ controls the conduction between the charge distribution unit DH and the first signal line.
  • the charge distribution unit DH can discharge to the first signal line along the control unit KZ, so that the charge on the surface of the charge transfer layer 10 of the charge distribution unit DH disappears (for example, in the sub-pixel P2 in FIG.
  • the negative charge is transmitted along the dotted arrow direction and neutralized with the positive charge, so that the positive charge on the surface of the charge transfer layer 10 gradually disappears), so that the surface of the charge transfer layer 10 of some sub-pixels is not charged, forming a charge pattern; in this way, the control of the charge pattern by the electric signal is realized, and a new electrostatic imaging method is provided, which avoids the problem of low exposure accuracy caused by interference of external light when forming the charge pattern by controlling the light source exposure in the related art.
  • the accuracy of forming the charge pattern is improved, and when the detection substrate is applied to the printing device, the printing accuracy and printing clarity can be improved, and the printing blur caused by interference of external light during the exposure process can be avoided; in addition, in the printing device, the light shielding component in the related art can be omitted, simplifying the design of the printing device and reducing the cost.
  • control unit KZ includes at least two transistors, one of which is electrically connected to the data line DL, and the other is electrically connected to the first signal line (eg, VSS).
  • the above-mentioned transistor can be a thin film transistor (Thin Film Transistor, TFT); or, the above-mentioned transistor can be a metal-oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET).
  • TFT Thin Film Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the above transistors may all be N-type transistors, or the above transistors may all be P-type transistors, which may be determined according to actual conditions.
  • control units KZ with different structures are provided, and the electrical connection mode and working principle of the components in each control unit KZ are explained:
  • the control unit KZ includes a first transistor M1 and a second transistor M2, the gate of the first transistor M1 is electrically connected to the data line DL (for example, DL1 or DL2), the first end of the first transistor M1 is electrically connected to the first electrode 9, and the second end of the first transistor M1 is electrically connected to the first end of the second transistor M2; the gate of the second transistor M2 is electrically connected to the gate line GL (for example, GL1 or GL2), and the second end of the second transistor M2 is electrically connected to the first signal line (for example, VSS).
  • DL for example, DL1 or DL2
  • the first end of the first transistor M1 is electrically connected to the first electrode 9
  • the second end of the first transistor M1 is electrically connected to the first end of the second transistor M2
  • the gate of the second transistor M2 is electrically connected to the gate line GL (for example, GL1 or GL2)
  • the second end of the second transistor M2 is electrically connected to
  • the detection substrate may further include a gate driving circuit and a driving chip, wherein the gate driving circuit is electrically connected to each gate line GL for controlling each gate line GL to scan each row of sub-pixels P row by row; the driving chip is electrically connected to each data line DL for providing a control signal to the data line DL.
  • the gate driving circuit is electrically connected to each gate line GL for controlling each gate line GL to scan each row of sub-pixels P row by row
  • the driving chip is electrically connected to each data line DL for providing a control signal to the data line DL.
  • the electric signal provided by the gate line GL controls whether the first transistor M1 is turned on, and the electric signal provided by the data line DL controls whether the second transistor M2 is turned on.
  • the control unit KZ connects the charge distribution unit DH to the first signal line (for example, VSS), so that the charge distribution unit DH can be discharged to the first signal line (for example, VSS), so that the charge on the surface of the charge distribution unit DH disappears.
  • the charge distribution unit DH cannot be turned on from the first signal line (for example, VSS), and the charge distribution unit DH cannot be discharged, and the charge distribution unit DH maintains its charge. In this way, the formation of a charge pattern through electric signal control is achieved.
  • the control unit KZ includes a first transistor M1 and a second transistor M2, the gate of the first transistor M1 is electrically connected to the data line DL, the first end of the first transistor M1 is electrically connected to the first electrode 9, and the second end of the first transistor M1 is shared with the first end of the second transistor M2; the gate of the second transistor M2 is electrically connected to the gate line GL, and the second end of the second transistor M2 is electrically connected to the first signal line (for example, VSS).
  • VSS first signal line
  • the second end of the first transistor M1 is shared with the first end of the second transistor M2.
  • the discharge path from the charge distribution unit DH to the first signal line is greatly shortened, thereby increasing the discharge rate of the charge distribution unit DH and shortening the time to form a charge pattern.
  • the control unit includes a first transistor M1 and a second transistor M2, the gate of the first transistor M1 is electrically connected to the gate line GL, the first end of the first transistor M1 is electrically connected to the data line DL, and the second end of the first transistor M1 is electrically connected to the gate of the second transistor M2; the first end of the second transistor M2 is electrically connected to the first electrode 9, and the second end of the second transistor M2 is electrically connected to the first signal line (for example, VSS).
  • VSS first signal line
  • the detection substrate may further include a gate driving circuit and a driving chip, wherein the gate driving circuit is electrically connected to each gate line GL for controlling each gate line GL to scan each row of sub-pixels P row by row; the driving chip is electrically connected to each data line DL for providing a control signal to the data line DL.
  • the gate driving circuit is electrically connected to each gate line GL for controlling each gate line GL to scan each row of sub-pixels P row by row
  • the driving chip is electrically connected to each data line DL for providing a control signal to the data line DL.
  • the electric signal provided by the gate line GL is used to control whether the first transistor M1 is turned on.
  • the electric signal provided by the data line DL is used to control whether the second transistor M2 is turned on.
  • the control unit KZ connects the charge distribution unit DH to the first signal line (for example, VSS), so that the charge distribution unit DH can be discharged to the first signal line (for example, VSS), so that the charge on the surface of the charge distribution unit DH disappears.
  • the charge distribution unit DH cannot be turned on from the first signal line (for example, VSS), and the charge distribution unit DH cannot be discharged, and the charge distribution unit DH maintains its charge. In this way, the formation of a charge pattern through electric signal control is achieved.
  • the detection substrate provided in the embodiment of the present application, by setting the structure of the control unit KZ, it can be one of the three situations described above, realizing the formation of the charge pattern simply through the control of the electric signal, providing a new electrostatic imaging method, avoiding the problems of low exposure accuracy and low laser service life caused by interference from external light when forming the charge pattern by controlling the light source (laser) exposure in the related art.
  • the accuracy of forming the charge pattern is improved.
  • the detection substrate is used in a printing device, the printing accuracy and print clarity can be improved, and the printing blur caused by interference from external light during the exposure process can be avoided; in addition, in the printing device, the shading component in the related art can also be omitted, simplifying the design of the printing device and reducing costs.
  • the design of the above-mentioned control unit KZ is simple and easy to implement.
  • the charge distribution unit DH also includes a buffer layer and a charge injection layer, the buffer layer is located between the first electrode and the charge transport layer, and the charge injection layer is located between the buffer layer and the charge transport layer, wherein the polarity of the charge injected by the charge injection layer is the same as the polarity of the charge transported by the charge transport layer.
  • the charge injection layer may include a hole injection layer (HIL) and an electron injection layer (EIL).
  • HIL hole injection layer
  • EIL electron injection layer
  • the material of the hole injection layer may include oxides, such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide, and manganese oxide.
  • oxides such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide, and manganese oxide.
  • the material of the hole injection layer may also include organic materials, such as hexacyanohexaazatriphenylene, 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ), and 1,2,3-tris[(cyano)(4-cyano-2,3,5,6-tetrafluorophenyl)methylene]cyclopropane.
  • organic materials such as hexacyanohexaazatriphenylene, 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ), and 1,2,3-tris[(cyano)(4-cyano-2,3,5,6-tetrafluorophenyl)methylene]cyclopropane.
  • the charge transport layer 10 includes a hole transport layer (HTL), and each transistor in the control unit KZ is a P-type transistor.
  • HTL hole transport layer
  • the N-type transistor transmits a high level
  • the P-type transistor transmits a low level
  • the charging roller is negatively charged and is brought into contact with the surface of the charge transport layer 10, so that the surface of the charge transport layer 10 is negatively charged, and its surface electrostatic potential is -600 V; then a charge pattern is formed, and in the process of the charge distribution unit DH discharging the first signal line, positive charges (holes) are transferred to the surface of the charge distribution unit DH so that the negative charges (electrons) and the positive charges (holes) are neutralized, thereby causing the charges on the surface of the charge distribution unit DH to disappear.
  • HTL hole transport layer
  • the charge transport layer of the charge distribution unit DH may include a hole transport layer (a film layer having hole transport properties) so that the holes can be smoothly transferred to the surface of the charge distribution unit DH.
  • Exemplary materials of the hole transport layer may include aromatic amines, hydrazones, imidazoles, thiazoles, oxadiazoles, butadiene compounds, and dimethylfluorene or carbazole materials having hole transport properties, such as polyvinylcarbazole (PVK) 4,4'-bis[N-(1-naphthyl)-N-phenylamino]biphenyl (NPB), N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl] -4,4'-diamine (TPD), 4-phenyl-4'-(9-phenylfluoren-9-yl)triphenylamine (BAFLP), 4,4'-bis[N-(9,9-dimethylfluoren-2-yl)-N-phenylamino]biphenyl (DFLDPBi), 4,4'-bis(9-carbazolyl
  • the charge transport layer 10 includes an electron transport layer (ETL), and each transistor in the control unit KZ is an N-type transistor.
  • ETL electron transport layer
  • the charging roller is positively charged and is in contact with the surface of the charge transport layer 10, so that the surface of the charge transport layer 10 is positively charged, and its surface electrostatic potential is +600V, and then a charge pattern is formed.
  • negative charges are transferred to the surface of the charge distribution unit DH so that the negative charges (electrons) are neutralized with positive charges (holes), thereby causing the charge on the surface of the charge distribution unit DH to disappear.
  • the charge transport layer of the charge distribution unit DH may include an electron transport layer (a film layer with electron transport properties) so that the electrons can be smoothly transferred to the surface of the charge distribution unit DH.
  • the material of the electron transport layer may include aromatic heterocyclic compounds, such as benzimidazole derivatives, imidazole derivatives, pyrimidine derivatives, oxazine derivatives, quinoline derivatives, isoquinoline derivatives, phenanthroline derivatives, etc.; the material of the electron transport layer (ETL) may also include polynitro compounds (such as 2,4,7-trinitrofluorenone, TNF), cyano compounds, naphthalene anhydride derivatives, quinone compounds, or inorganic ZnO, IGZO, TiO2 , SnO2 , etc.
  • aromatic heterocyclic compounds such as benzimidazole derivatives, imidazole derivatives, pyrimidine derivatives, oxazine derivatives, quinoline derivatives, isoquinoline derivatives, phenanthroline derivatives, etc.
  • the material of the electron transport layer (ETL) may also include polynitro compounds (such as 2,4,7-trinitrofluorenone, TNF
  • the detection substrate includes:
  • the semiconductor layer 4 is located at a side of the first conductive layer 2 away from the substrate 1 and is insulated from the first conductive layer 2.
  • the semiconductor layer 4 includes an active region 41 of each transistor.
  • the second conductive layer 5 is located on the side of the semiconductor layer 4 away from the substrate 1, and includes a data line DL and a source s and a drain d of each transistor; wherein the orthographic projection of the gate gt of at least one transistor in the control unit KZ on the substrate 1 partially overlaps with the orthographic projection of the active area 41 on the substrate 1.
  • the material of the semiconductor layer 4 may include amorphous silicon (a-Si); in other embodiments, the material of the semiconductor layer 4 may include low-temperature polycrystalline silicon (LTPS); in other embodiments, the material of the semiconductor layer 4 may include metal oxide, such as indium gallium zinc oxide (IGZO).
  • a-Si amorphous silicon
  • LTPS low-temperature polycrystalline silicon
  • IGZO metal oxide, such as indium gallium zinc oxide
  • the first conductive layer 2 can also be referred to as a gate layer
  • the second conductive layer 5 can also be referred to as a source-drain metal layer.
  • the materials of the first conductive layer 2 and the second conductive layer 5 both include conductive materials, for example, copper.
  • the film layer marked Gate is the gate layer
  • the film layer marked Active is the semiconductor layer 4
  • the film layer marked SD is the source-drain metal layer.
  • the semiconductor layer 4 includes an active area 41 of each transistor, and a contact area 42 and a contact area 43 located on both sides of the active area 41, wherein the semiconductor layer 4 is in direct contact with the second conductive layer 5, the contact area 42 is in contact and conductive with the source 5/s, and the contact area 43 is in contact and conductive with the drain 5/d.
  • the semiconductor layer 4 includes an active area 41 of each transistor, a contact area 42 and a contact area 43 located on both sides of the active area 41, wherein an etching stop layer ESL is also arranged between the semiconductor layer 4 and the second conductive layer 5, the contact area 42 is connected to the source 5/s through a through hole, and the contact area 43 is connected to the drain 5/d through a through hole.
  • an etching stop layer ESL is also arranged between the semiconductor layer 4 and the second conductive layer 5
  • the contact area 42 is connected to the source 5/s through a through hole
  • the contact area 43 is connected to the drain 5/d through a through hole.
  • the orthographic projection of the gate gt of at least one transistor in the control unit KZ on the substrate 1 partially overlaps with the orthographic projection of the active area 41 on the substrate 1, and the orthographic projection of the gate gt of at least one transistor on the substrate 1 does not overlap with the orthographic projection of the active area 41 on the substrate 1.
  • the part where the orthographic projection of the active area 41 on the substrate 1 does not overlap with the gate gt can greatly improve the high-voltage resistance characteristics of the transistor. This design is called an Offset design.
  • the power-on voltage of the charging roller is usually high, when the charging roller charges the detection substrate, the voltage on the charge distribution unit DH of the detection substrate is also high.
  • the transistor in the control unit KZ needs to withstand a higher voltage.
  • the above design can significantly improve this problem, thereby improving the electrical stability of the control unit KZ and extending the service life of the detection substrate.
  • the orthographic projection of the gate gt of the first transistor M1 on the substrate 1 partially overlaps with the orthographic projection of the active region 41 on the substrate 1 ;
  • the active region 41 of the first transistor M1 includes a plurality of active portions Y and a first bending portion W1 connecting two adjacent active portions Y.
  • the orthographic projection of a portion of the first bending portion W1 on the substrate 1 is located within the orthographic projection of the gate gt on the substrate 1 .
  • the number of first bends W1 in an active region 41 is less than the number of active portions Y; specifically, in the same transistor, the number of first bends W1 is equal to the number of active portions Y minus 1.
  • the width-to-length ratio of the transistor can be greatly improved, thereby increasing the current value Id passing through the transistor.
  • the orthographic projection of the gate gt of the second transistor M2 on the substrate 1 may also be arranged to partially overlap with the orthographic projection of the active area 41 on the substrate 1;
  • the active area 41 of the second transistor M2 includes a plurality of active portions Y and a first bending portion W1 connecting two adjacent active portions Y, and the orthographic projection of part of the first bending portion W1 on the substrate 1 is located within the orthographic projection of the gate gt on the substrate 1.
  • the width-to-length ratio of the transistor can be greatly improved, thereby increasing the current value Id passing through the transistor;
  • by providing a part of the first bend portion W1 so that the orthographic projection on the substrate 1 is located within the orthographic projection of the gate gt on the substrate 1, the part where the orthographic projection of the active area 41 on the substrate 1 does not overlap with the gate gt can greatly improve the high-voltage resistance characteristics of the transistor, thereby increasing the service life of the transistor and improving the product quality of the detection substrate.
  • each active portion Y and each first bending portion W1 of the active area 41 is an integrated structure.
  • each active portion Y and each first bending portion W1 can be formed using the same material in the same preparation process, and the preparation process is low in difficulty and low in cost.
  • the gate gt controls the source s and drain d of the transistor to be turned on
  • a carrier channel is formed in the active region 41, and the active region 41 changes from a semiconductor to a conductor, thereby turning on the transistor
  • the active region 41 is designed using the structure shown in FIG12, since the active region 41 includes the active portion Y and the first bent portion W1, the first bent portion W1 has a bent structure so that the carrier migration characteristics inside it are slightly inferior to the active portion Y.
  • the channel region includes the active portion Y and the first bent portion W1.
  • the orthographic projection of the gate gt of the first transistor M1 on the substrate 1 partially overlaps with the orthographic projection of the active area 41 on the substrate 1;
  • the active area 41 of the first transistor M1 includes a plurality of active portions Y, and the second conductive layer (for example, SD) includes a plurality of second bending portions W2, and two adjacent active portions Y are electrically connected through the second bending portions W2;
  • the orthographic projection of the second bending portions W2 on the substrate 1 does not overlap with the orthographic projection of the gate gt on the substrate 1.
  • the film layer marked with Gate is the gate layer
  • the film layer marked with Active is the semiconductor layer 4
  • the film layer marked with SD is the source-drain metal layer.
  • the active parts Y are electrically connected together by arranging a plurality of second bends W2 located in the second conductive layer; on the one hand, the second bends W2 are originally conductors, which can further reduce the size of the gate gt, so that the orthographic projection of the second bends W2 on the substrate 1 and the orthographic projection of the gate gt on the substrate 1 do not overlap each other, thereby increasing the area that does not overlap with the gate in the active area 41 and the second bends W2, thereby improving the high voltage impact resistance of the transistor; on the other hand, when the gate gt controls the source s and drain d of the transistor to be turned on, a carrier channel is formed in each active part Y and the second bend W2 of the active area 41, and each active part Y is changed from a semiconductor to a conductor, thereby turning on the transistor; on the other hand, the width-to-length ratio of the transistor can be greatly improved, thereby increasing the current value Id passing through the transistor.
  • the second bends W2 are
  • the orthographic projection of the gate gt of the second transistor M2 on the substrate 1 may also be arranged to partially overlap with the orthographic projection of the active area 41 on the substrate 1;
  • the active area 41 of the second transistor M2 includes a plurality of active portions Y
  • the second conductive layer 5 (for example, SD) includes a plurality of second bending portions W2, and two adjacent active portions Y are electrically connected via the second bending portions W2;
  • the orthographic projection of the second bending portions W2 on the substrate 1 and the orthographic projection of the gate gt on the substrate 1 do not overlap with each other.
  • a shape of an orthographic projection of each active portion Y on the substrate may include a polygon, for example, a rectangle.
  • a detection substrate provided in an embodiment of the present application, as shown in Figures 12 and 13, there is a gap between two adjacent active parts Y, and the orthographic projection of the gate gt on the substrate 1 at least partially overlaps with the area enclosed by the orthographic projection of the outer contour of part of the gap on the substrate 1.
  • the orthographic projection of the gate gt on the substrate 1 and the area enclosed by the orthographic projection of the outer contour of the partial gap on the substrate 1 at least partially overlap, including but not limited to the following situations:
  • the orthographic projection of the gate gt on the substrate 1 partially overlaps with the area defined by the orthographic projection of the outer contour of a portion of the gap on the substrate 1;
  • the orthographic projection of the gate gt on the substrate 1 completely overlaps with the area enclosed by the orthographic projection of the outer contour of the partial gap on the substrate 1 .
  • the gate gt of the first transistor M1 may include multiple overlapping portions and at least one connecting portion, and the connecting portion electrically connects the overlapping portions together, wherein the orthographic projection of the overlapping portion on the substrate 1 overlaps with the orthographic projection of the active portion Y on the substrate 1.
  • the detection substrate also includes a pixel definition layer 11 (PDL) and a plurality of pixel partition structures 12, the pixel definition layer 11 is located on the side of the first electrode 9 away from the substrate 1; the charge transfer layer 10 is located on the side of the pixel definition layer 11 away from the substrate 1; the pixel definition layer 11 includes a plurality of first openings K1 and a plurality of second openings K2, the orthographic projection of the first electrode 9 on the substrate 1 overlaps with the area enclosed by the orthographic projection of the outer contour of the first opening K1 on the substrate 1, and the orthographic projection of the pixel partition structure 12 on the substrate 1 overlaps with the area enclosed by the orthographic projection of the outer contour of the second opening K2 on the substrate 1; the pixel partition structure 12 is located between two adjacent sub-pixels, and the charge transfer layer 10 is disconnected at the position of the pixel partition structure 12.
  • PDL pixel definition layer 11
  • the charge transfer layer 10 is located on the side of the pixel definition layer 11 away from the substrate 1
  • the material of the pixel definition layer 11 may include organic materials, such as polyimide, acrylic or polyethylene terephthalate.
  • a depth of the first opening K1 along a direction perpendicular to the thickness of the substrate 1 is smaller than a depth of the second opening K2 along the direction perpendicular to the thickness of the substrate 1 .
  • the first opening K1 penetrates the pixel definition layer 11
  • the second opening K2 does not penetrate the pixel definition layer 11 .
  • the pixel partition structure 12 is arranged in the second opening K2.
  • the fixing stability between the pixel partition structure 12 and the pixel definition layer 11 is better.
  • the size of the interface between the pixel partition structure 12 and the pixel definition layer 11 is increased. Even if there is carrier migration at the junction between the pixel partition structure 12 and the pixel definition layer 11, crosstalk between adjacent sub-pixels is unlikely to occur due to the long propagation path.
  • the detection substrate provided in the embodiment of the present application is arranged such that the orthographic projection of the first electrode 9 on the substrate 1 overlaps with the area defined by the orthographic projection of the outer contour of the first opening K1 on the substrate 1, thereby separating the first electrodes 9 of two adjacent sub-pixels and avoiding crosstalk of electrical signals between the two adjacent first electrodes 9.
  • a pixel partition structure 12 is arranged in the second opening K2 of the pixel definition layer 11, so that the pixel partition structure 12 separates the charge transfer layers 10 of adjacent sub-pixels, thereby avoiding the migration of carriers between the charge transfer layers 10 of different sub-pixels, and avoiding that when the charge distribution unit DH in a sub-pixel discharges, the sub-pixel that does not need to discharge is disturbed and also discharges to a certain extent, thereby reducing the accuracy of forming the charge pattern.
  • the substrate 1 is a flexible substrate.
  • the charge transfer layers in each sub-pixel are located in the same plane; in a second state, the charge transfer layers in each sub-pixel are located on the same curved surface, and the three-dimensional shape of the detection substrate in the second state includes a cylinder.
  • the detection substrate can be set to a planar structure; or the detection substrate can be rolled into an axis shape (cylindrical shape), similar to the shape of a photosensitive drum in the related art;
  • the space occupied by the detection substrate can be reduced, so that it can be applied to more different products or scenarios.
  • the detection substrate also includes a first insulating layer 6, an organic layer 7 and a second insulating layer 8 stacked in sequence, the first insulating layer 6 covers each control unit KZ, and the second insulating layer 8 is located on the side of each first electrode 9 close to the substrate 1; the first insulating layer 8 is provided with a plurality of grooves C in the area between two adjacent control units KZ, and the organic layer 7 extends into the grooves C.
  • the detection substrate further includes a gate insulating layer 3, and the gate insulating layer 3 covers each gate electrode gt and each gate line.
  • the materials of the first insulating layer 6 and the second insulating layer 8 may include an inorganic material, for example, at least one of silicon nitride, silicon oxide, or silicon oxynitride.
  • the material of the organic layer 7 may include resin.
  • the groove C may penetrate the first insulating layer 8 .
  • a first insulating layer 8 is provided with a plurality of grooves C in the area between two adjacent control units KZ, and the organic layer 7 extends into the grooves C; when the detection substrate is bent, the internal stress in the inorganic film layer can be effectively released at the position of the grooves C, thereby avoiding cracks in the film layer in the detection substrate and improving the reliability and service life of the detection substrate.
  • the material of the semiconductor layer 4 includes metal oxide
  • the detection substrate also includes an etching stop layer ESL
  • the etching stop layer ESL covers the semiconductor layer 4
  • the second conductive layer 5 is located on the side of the etching stop layer ESL away from the substrate 1.
  • a plurality of through holes are provided in the etching stop layer ESL, the contact region 42 is connected to the source electrode 5/s through the through holes, and the contact region 43 is connected to the drain electrode 5/d through the through holes.
  • the metal oxide may include indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • this is a current-voltage transfer characteristic curve (I-V curve) of a transistor provided in an embodiment of the present application when the voltage is 300V.
  • Vds is 300V
  • the transistor device still has switching characteristics, and the threshold voltage Vth of the transistor is close to 0V.
  • this is a current-voltage transfer characteristic curve (I-V curve) of a transistor provided in an embodiment of the present application when the voltage is 600V.
  • Vgs ⁇ Vth when Vds is 600V, it can be seen that the leakage current value is at the noise level, indicating that when the transistor is in the off state, it is not broken down under the high voltage of 600V, and effective shutdown can be guaranteed.
  • the transistor in the control unit KZ provided in the embodiment of the present application can maintain the switching characteristics under high voltage, and effectively control the discharge state or the holding state of the charge distribution unit DH, so as to realize the formation of the charge pattern through the control of the electrical signal.
  • the voltage value of the high voltage resistance of the transistor is related to the voltage value when the detection substrate is charged. For example, the detection substrate is charged at 600V, and the transistor provided in the embodiment of the present application can maintain the switching characteristics under this high voltage.
  • An embodiment of the present application provides a detection device, comprising the detection substrate as described above.
  • control unit KZ controls the conduction between the charge distribution unit DH and the first signal line.
  • the charge distribution unit DH and the first signal line are conductive, the charge distribution unit DH can discharge toward the first signal line along the control unit KZ, so that the charge on the surface of the charge transfer layer 10 of the charge distribution unit DH disappears (for example, in the sub-pixel P2 in FIG.
  • the negative charge is transmitted in the direction of the dotted arrow and neutralized with the positive charge, so that the positive charge on the surface of the charge transfer layer 10 gradually disappears), thereby making the surface of the charge transfer layer 10 of some sub-pixels uncharged, forming an electrostatic pattern charge pattern; in this way, the control of the electrostatic pattern charge pattern by electrical signals is realized, providing a new electrostatic imaging method, and avoiding the problem of low exposure accuracy caused by interference from external light when the electrostatic pattern charge pattern is formed by controlling the light source exposure in the related art.
  • An embodiment of the present application provides a printing device, including the detection substrate as described above, and also including a charging device and a driving chip, the charging device is configured to charge the charge distribution unit of the detection substrate, and the driving chip is configured to transmit a control signal to the detection substrate.
  • the charging device may include a charging roller.
  • control unit KZ controls the conduction between the charge distribution unit DH and the first signal line.
  • the charge distribution unit DH can discharge to the first signal line along the control unit KZ, so that the charge on the surface of the charge transfer layer 10 of the charge distribution unit DH disappears (for example, in the sub-pixel P2 in FIG.
  • the negative charge is transmitted along the dotted arrow direction and neutralized with the positive charge, so that the positive charge on the surface of the charge transfer layer 10 gradually disappears), so that the surface of the charge transfer layer 10 of some sub-pixels is not charged, forming an electrostatic pattern charge pattern; in this way, the control of the electrostatic pattern charge pattern by the electric signal is realized, and a new electrostatic imaging method is provided, which avoids the problem of low exposure accuracy caused by the interference of external light when the electrostatic pattern charge pattern is formed by controlling the light source exposure in the related art.
  • the accuracy of forming the electrostatic pattern charge pattern is improved, and when the detection substrate is applied to the printing device, the printing accuracy and printing clarity can be improved, and the printing blur caused by the interference of external light in the exposure process can be avoided; in addition, in the printing device, the light shielding component in the related art can be omitted, simplifying the design of the printing device and reducing the cost.
  • An embodiment of the present application provides a control method for detecting a substrate, which is applied to the detection substrate as described above. As shown in FIG20 , the method includes:
  • the state in which the charge distribution unit DH is fully charged refers to the state after the detection substrate is completely charged.
  • a high voltage can be used to energize the charging roller so that the charging roller contacts the surface of the charge transport layer 10 of the detection substrate.
  • the surface of the charge transport layer 10 of the detection substrate will carry a uniform charge (positive charge or negative charge), and the polarity of the charge on the surface of the charge transport layer 10 is the same as the polarity of the voltage on the charging roller.
  • the specific charging process of the detection substrate can refer to the charging process of the printer in the related art, which will not be described in detail here.
  • the control unit KZ controls the conduction between the charge distribution unit DH and the first signal line.
  • the charge distribution unit DH can discharge to the first signal line along the control unit KZ, so that the charge on the surface of the charge transport layer 10 of the charge distribution unit DH disappears (for example, in the sub-pixel P2 in FIG. 5 , the negative charge is transmitted along the direction of the dotted arrow and neutralized with the positive charge, so that the positive charge on the surface of the charge transport layer 10 gradually disappears), so that the surface of the charge transport layer 10 of some sub-pixels is not charged;
  • the control method of the detection substrate realizes the control of the charge pattern through the electrical signal, provides a new electrostatic imaging method, and avoids the problem of low exposure accuracy caused by interference from external light when forming the charge pattern by controlling the light source exposure in the related art.
  • the accuracy of forming the charge pattern is improved.
  • the detection substrate is used in a printing device, the printing accuracy and print clarity can be improved, and the printing blur caused by interference from external light during the exposure process can be avoided; in addition, in the printing device, the shading component in the related art can be omitted, simplifying the design of the printing device and reducing costs.
  • An embodiment of the present application provides a method for preparing a detection substrate, the method comprising:
  • a second conductive layer 5 (eg, a source-drain metal layer) on the etching stop layer ESL;
  • the detection substrate prepared by the detection substrate preparation method provided by the embodiment of the present application realizes the control of the charge pattern by the electric signal, provides a new electrostatic imaging method, and avoids the problem of low exposure accuracy caused by interference of external light when forming the charge pattern by controlling the light source exposure in the related art.
  • the accuracy of forming the charge pattern is improved, and when the detection substrate is used in a printing device, the printing accuracy and printing clarity can be improved, and the printing blur caused by interference of external light during the exposure process can be avoided; in addition, in the printing device, the light shielding component in the related art can be omitted, simplifying the design of the printing device and reducing costs.
  • the above-mentioned detection substrate may also include other structures and layouts, and the preparation method of the above-mentioned detection substrate may also include other processes and steps.
  • This specification only introduces the preparation process related to the invention point. The other preparation processes included therein can refer to the relevant technology and will not be repeated here.

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Abstract

本申请提供了一种探测基板及其制备方法、探测装置、打印装置，涉及探测技术领域，该探测基板包括：衬底；多条数据线和多条栅线；阵列排布的多个子像素，子像素位于数据线和栅线限定的位置处，子像素分别与数据线和栅线电连接；其中，子像素包括控制单元和电荷分布单元，控制单元分别与数据线和栅线电连接，电荷分布单元包括第一电极和电荷传输层，第一电极与控制单元电连接，电荷传输层在衬底上的正投影覆盖第一电极在衬底上的正投影；电荷分布单元被配置为能够在控制单元的控制下进行放电。该探测基板实现了通过电信号控制形成电荷图案，提供了一种静电成像的新方式。

Description

探测基板及其控制方法、探测装置、打印装置 技术领域
本申请涉及探测技术领域，尤其涉及一种探测基板及其制备方法、探测装置、打印装置。
背景技术
随着探测技术的不断发展，探测基板或探测装置在工业无损检测、集装箱扫描、电路板检查、医疗、安防等领域，具有广阔的应用前景。然而，当前的探测技术通常基于光信号到电信号的转换过程，光信号对探测的准确性影响较大，且光信号极易受到外界光线的干扰。
发明内容
本申请的实施例采用如下技术方案：
第一方面，本申请的实施例提供了一种探测基板，包括：
衬底；
位于所述衬底上沿第一方向延伸的多条数据线和沿第二方向延伸的多条栅线；所述第一方向与所述第二方向相交；
阵列排布的多个子像素，所述子像素位于所述数据线和所述栅线限定的位置处，所述子像素分别与所述数据线和所述栅线电连接；
其中，所述子像素包括控制单元和电荷分布单元，所述控制单元分别与所述数据线和所述栅线电连接，所述电荷分布单元包括第一电极和电荷传输层，所述第一电极与所述控制单元电连接，所述电荷传输层在所述衬底上的正投影覆盖所述第一电极在所述衬底上的正投影；所述电荷分布单元被配置为能够在所述控制单元的控制下进行放电。
在本申请的实施例提供的一探测基板中，所述探测基板还包括第一信号线，所述第一信号线与所述控制单元电连接，在所述电荷分布单元处于满电荷的状态下，所述第一信号线中传输的信号的电压小于所述第一电极的电压；
其中，所述第一信号线被配置为能够传输电压恒定的信号，所述电 荷分布单元被配置为能够在所述控制单元的控制下，沿所述控制单元向所述第一信号线放电。
在本申请的实施例提供的一探测基板中，所述第一信号线包括接地线或负极电源信号线。
在本申请的实施例提供的一探测基板中，所述控制单元包括至少两个晶体管，其中一个所述晶体管与所述数据线电连接，另一个所述晶体管与所述第一信号线电连接。
在本申请的实施例提供的一探测基板中，所述电荷分布单元还包括缓冲层和电荷注入层，所述缓冲层位于所述第一电极与所述电荷传输层之间，所述电荷注入层位于所述缓冲层与所述电荷传输层之间；其中，所述电荷注入层注入的电荷的极性与所述电荷传输层传输的电荷的极性相同。
在本申请的实施例提供的一探测基板中，所述控制单元包括第一晶体管和第二晶体管，所述第一晶体管的栅极与所述数据线电连接，所述第一晶体管的第一端与所述第一电极电连接，所述第一晶体管的第二端与所述第二晶体管的第一端电连接；所述第二晶体管的栅极与所述栅线电连接，所述第二晶体管的第二端与所述第一信号线电连接。
在本申请的实施例提供的一探测基板中，所述控制单元包括第一晶体管和第二晶体管，所述第一晶体管的栅极与所述数据线电连接，所述第一晶体管的第一端与所述第一电极电连接，所述第一晶体管的第二端与所述第二晶体管的第一端共用；所述第二晶体管的栅极与所述栅线电连接，所述第二晶体管的第二端与所述第一信号线电连接。
在本申请的实施例提供的一探测基板中，所述控制单元包括第一晶体管和第二晶体管，所述第一晶体管的栅极与所述栅线电连接，所述第一晶体管的第一端与所述数据线电连接，所述第一晶体管的第二端与所述第二晶体管的栅极电连接；所述第二晶体管的第一端与所述第一电极电连接，所述第二晶体管的第二端与所述第一信号线电连接。
在本申请的实施例提供的一探测基板中，所述电荷传输层包括空穴传输层，所述控制单元中的各所述晶体管均为P型晶体管。
在本申请的实施例提供的一探测基板中，所述电荷传输层包括电子传输层，所述控制单元中的各所述晶体管均为N型晶体管。
在本申请的实施例提供的一探测基板中，所述探测基板包括：
第一导电层，位于所述衬底的一侧，所述第一导电层包括栅线和各所述晶体管的栅极；
半导体层，位于所述第一导电层远离所述衬底的一侧，与所述第一导电层之间绝缘设置，所述半导体层包括各所述晶体管的有源区；
第二导电层，位于所述半导体层远离所述衬底的一侧，包括所述数据线以及各所述晶体管的源极和漏极；
其中，所述控制单元中的至少一个所述晶体管的所述栅极在所述衬底上的正投影与所述有源区在所述衬底上的正投影部分交叠。
在本申请的实施例提供的一探测基板中，所述第一晶体管的所述栅极在所述衬底上的正投影与所述有源区在所述衬底上的正投影部分交叠；
所述第一晶体管的有源区包括多个有源部以及连接相邻两个所述有源部之间的第一弯折部，部分所述第一弯折部在所述衬底上的正投影位于所述栅极在所述衬底上的正投影以内。
在本申请的实施例提供的一探测基板中，所述第一晶体管的所述栅极在所述衬底上的正投影与所述有源区在所述衬底上的正投影部分交叠；
所述第一晶体管的有源区包括多个有源部，所述第二导电层包括多个第二弯折部，相邻两个所述有源部之间通过所述第二弯折部电连接；所述第二弯折部在所述衬底上的正投影与所述栅极在所述衬底上的正投影互不交叠。
在本申请的实施例提供的一探测基板中，相邻两个所述有源部之间具有间隙，所述栅极在所述衬底上的正投影与部分所述间隙的外轮廓在所述衬底上的正投影圈定的区域至少部分交叠。
在本申请的实施例提供的一探测基板中，
所述探测基板还包括像素定义层和多个像素隔断结构，所述像素定 义层位于所述第一电极远离所述衬底的一侧；所述电荷传输层位于所述像素定义层远离所述衬底的一侧；
所述像素定义层包括多个第一开口和多个第二开口，所述第一电极在所述衬底上的正投影与所述第一开口的外轮廓在所述衬底上的正投影圈定的区域重叠，所述像素隔断结构在所述衬底上的正投影与所述第二开口的外轮廓在所述衬底上的正投影圈定的区域重叠；
所述像素隔断结构位于相邻的两个所述子像素之间，所述电荷传输层在所述像素隔断结构位置处断开设置。
在本申请的实施例提供的一探测基板中，所述衬底为柔性衬底。
在本申请的实施例提供的一探测基板中，在第一状态下，各所述子像素中的所述电荷传输层均位于同一平面内；
在第二状态下，各所述子像素中的所述电荷传输层均位于同一曲面，且所述探测基板在所述第二状态下的立体图形包括圆柱形。
在本申请的实施例提供的一探测基板中，所述探测基板还包括依次叠层设置的第一绝缘层、有机层和第二绝缘层，所述第一绝缘层覆盖各所述控制单元，所述第二绝缘层位于各所述第一电极靠近所述衬底的一侧；
所述第一绝缘层在相邻两个所述控制单元之间的区域设置有多个凹槽，所述有机层延伸至所述凹槽内。
在本申请的实施例提供的一探测基板中，所述半导体层的材料包括金属氧化物，所述探测基板还包括刻蚀阻挡层，所述刻蚀阻挡层覆盖所述半导体层，所述第二导电层位于所述刻蚀阻挡层远离所述衬底的一侧。
第二方面，本申请的实施例提供了一种探测装置，包括如第一方面中任一项所述的探测基板。
第三方面，本申请的实施例提供了一种打印装置，包括如第一方面中任一项所述的探测基板，还包括充电设备和驱动芯片，所述充电设备被配置为能够向所述探测基板的电荷分布单元充电，所述驱动芯片被配置为能够向所述探测基板传输控制信号。
第四方面，本申请的实施例提供了一种探测基板的控制方法，应用 于如第一方面中任一项所述的探测基板，所述方法包括：
向所述探测基板充电，使得所述电荷分布单元处于满电荷状态；
向部分所述子像素的所述控制单元输入第一控制信号，所述第一控制信号被配置为能够控制所述子像素的所述电荷分布单元放电，使得所述电荷分布单元表面不带电荷；
向部分所述子像素的所述控制单元输入第二控制信号，所述第二控制信号被配置为能够控制所述子像素的所述电荷分布单元上保持电荷；得到具有电荷图案的所述探测基板。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本申请的实施例提供的一种相关技术中的激光打印机的打印原理示意图；
图2为本申请的实施例提供的一种相关技术中的曝光放电过程示意图；
图3-图6为本申请的实施例提供的四种探测基板的结构示意图；
图7和图8为本申请的实施例提供的两种探测基板的充电说明图；
图9-图11为本申请的实施例提供的三种探测基板的电路示意图；
图12-图15为本申请的实施例提供的四种晶体管的结构示意图；
图16和图17为本申请的实施例又提供的两种探测基板的结构示意图；
图18和图19为本申请的实施例提供的晶体管的两种电流电压转移特性曲线图；
图20为本申请的实施例提供的一种探测基板的控制方法流程图；
图21-图24为本申请的实施例提供的探测基板制备方法的中间结构图。
具体实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”、“特定示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
另外，还需要说明的是，当介绍本申请的元素及其实施例时，冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素；除非另有说明，“多个”的含义是两个或两个以上；用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素；术语“第一”、“第二”、“第三”等仅用于描述的目的，而不能理解为指示或暗示相对重要性及形成顺序。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的 元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
本说明书中多边形并非严格意义上的，可以是近似的三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在倒角、圆角、弧边以及变形等。
如图1所示，静电印刷术主要包括如下步骤：成像(充电、曝光)、着墨(显影)、色粉转移(转印)、定影、清洁。成像就是通过对一个合适的感光体表面(例如感光鼓的光敏表面OPC)充电及控制光源曝光来形成电荷图案；显影过程如下：当在特定位置带电的感光鼓经过墨盒时，由于静电吸附效应，感光鼓带电的位置就会吸附一定的墨粉，此时感光鼓上面的图形便是我们需要的图形，从而形成印刷图像；其中，印刷图像与光导鼓(感光鼓)上光信号的位置相对应。感光体是感光鼓上的光敏材料，在暗环境中，电阻率很高，近似于绝缘体，受光照射后，会迅速成为导体。需要说明的是，形成电荷图案的过程指的是：通过曝光，使得均匀带电的感光体表面的部分区域放电(光照区域的电阻变小，电荷消失，如图2所示，标记-70V的区域的电荷逐渐消失)，使曝光的区域与所需要的印刷图像的区域一致。这个过程对光线的控制精准度要求较高，且曝光过程极易受到外界光线的干扰。其中，图2中所示的结构为图1中的感光鼓的表面结构。
基于此，本申请的实施例提供了一种探测基板及其制备方法、探测装置、打印装置，该探测基板包括：衬底；位于衬底上沿第一方向延伸的多条数据线和沿第二方向延伸的多条栅线；第一方向与第二方向相交；阵列排布的多个子像素，子像素位于数据线和栅线限定的位置处，子像素分别与数据线和栅线电连接；其中，子像素包括控制单元和电荷分布单元，控制单元分别与数据线和栅线电连接，电荷分布单元包括第一电极和电荷传输层，第一电极与控制单元电连接，电荷传输层在衬底上的正投影覆盖第一电极在衬底上的正投影；电荷分布单元被配置为能够在控制单元的控制下进行放电。在本申请的实施例中，通过在探测基板中设置阵列排布的多个子像素，各子像素包括控制单元和电荷分布单元， 使得控制单元与电荷分别单元电连接，在各子像素中，其控制单元均能够控制电荷分布单元进行放电，这样，可以设置部分子像素的控制单元控制电荷分布单元进行放电，设置部分子像素的控制单元控制电荷分布单元不进行放电，从而形成电荷图案，实现了通过电信号对电荷图案的控制，提供了一种新的静电成像的方式，避免了相关技术中通过控制光源曝光来形成电荷图案时，外界光线的干扰造成的曝光精准度低的问题。
现将参照附图更全面地描述示例性的实施例。
本申请的实施例提供了一种探测基板，包括：衬底1；
如图9、图10和图11，位于衬1上沿第一方向延伸的多条数据线DL和沿第二方向延伸的多条栅线GL；第一方向与第二方向相交；
阵列排布的多个子像素P，子像素P位于数据线DL和栅线GL限定的位置处，子像素P分别与数据线DL和栅线GL电连接；
其中，如图3-图6所示，子像素P包括控制单元KZ和电荷分布单元DH，控制单元KZ分别与数据线DL和栅线GL电连接，电荷分布单元DH包括第一电极9和电荷传输层10，第一电极9与控制单元KZ电连接，电荷传输层10在衬底1上的正投影覆盖第一电极9在衬底1上的正投影；电荷分布单元DH被配置为能够在控制单元KZ的控制下进行放电。
这里对于上述衬底1的具体材料不进行限定。在一些实施例中，衬底1的材料可以为刚性材料，例如，普通光学玻璃、硅材料；其中，硅材料衬底可以为P型单晶硅衬底，或者，也可以为N型单晶硅衬底，具体可以根据实际产品进行确定。
在一些实施例中，衬底1的材料可以为柔性材料，例如超薄玻璃、聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料。当衬底1为柔性衬底时，衬底1可以包括单层的柔性材料层；或者，衬底1可以包括依次层叠设置的第一柔性材料层、第一无机非金属材料层、第二柔性材料层。第一柔性材料层、第二柔性材料层的材料采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料。第一无机非金属材料层的材料采用单层结构的氮 化硅(SiNx)、单层结构的氧化硅(SiOx)，或者叠层设置的氮化硅和氧化硅等，用于提高探测基板的抗水氧能力，从而提高探测基板的使用寿命。
这里对于上述数据线DL和栅线GL的具体数量不进行限定，数据线DL和栅线GL的数量与探测基板的尺寸以及子像素的像素分布密度(PPI)相关，可以根据实际产品的设计确定。
这里对于上述第一方向和第二方向相交的具体角度不进行限定。
示例性的，上述第一方向可以为竖直方向，第二方向可以为水平方向，第一方向和第二方向垂直。
示例性的，上述第一方向和第二方向相交的角度还可以为锐角。
这里对于上述栅线GL和数据线DL的具体材料不进行限定。
示例性的，栅线GL的材料可以包括钼、铜、铝等，例如可以通过溅射的方式形成Mo/Al/Mo叠层结构，其中，靠近衬底的一侧材料为Mo，厚度大约在
Figure PCTCN2022132357-appb-000001
左右，主要用于提高膜层间的粘附力，叠层结构的中间层材料为Al，为电信号传递通道的材料，远离衬底1一侧的材料为Mo，厚度大约在
Figure PCTCN2022132357-appb-000002
左右，可以用于保护中间层，防止电阻率低的中间层表面暴露发生氧化。例如也可以通过溅射的方式形成MoNb/Cu/MoNb的叠层结构，其中，靠近衬底的一侧材料为MoNb，厚度大约在
Figure PCTCN2022132357-appb-000003
左右，主要用于提高膜层间的粘附力，叠层结构的中间层材料为Cu，为电信号传递通道的材料，远离衬底1一侧的材料为MoNb，厚度大约在
Figure PCTCN2022132357-appb-000004
左右，可以用于保护中间层，防止电阻率低的中间层表面暴露发生氧化。由于单次溅射的厚度一般不超过1μm，因此在制作超过厚度1μm的栅线GL时，需要多次溅射来形成。此外，还可以通过电镀的方式形成，具体地，可以先形成种子层，例如Cu或Ag作为种子层(其中可预先沉积Ti或者类似合金材料作为种子层的粘附层)，之后再通过电镀制作电阻率低的铜，之后再制作防氧化层。
示例性的，数据线DL的材料可以和栅线GL的材料相同。
这里对于上述子像素P在衬底1上的正投影的图形不进行限定，示例性的，上述子像素P在衬底1上的正投影的图形包括多边形、弧形、 以及多边形与弧形的组合中的至少一种，其中，多边形与弧形的组合包括：多边形与弧形拼接形成的图形，或者，在多边形或弧形上挖除局部区域得到的图形。
在一些实施例中，可以设置各子像素P在衬底1上的正投影的图形均相同；
在一些实施例中，可以设置多个子像素P包括第一子像素、第二子像素和第三子像素，其中，第一子像素、第二子像素和第三子像素在衬底1上的正投影的图形不相同。
上述控制单元KZ中包括像素电路，以通过像素电路对电荷分布单元DH进行放电控制，像素电路中包括多个电器件，例如晶体管。在控制单元KZ能够实现控制电荷分布单元DH进行放电的情况下，这里对于上述控制单元KZ中包括的具体的电器件及各电器件之间的电连接方式不进行限定。
这里对于上述电荷分布单元DH中第一电极9的材料不进行限定。示例性的，第一电极9可以采用金属材料，如镁(Mg)、银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种；或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层结构，如Ti/Al/Ti等；或者透明导电材料，如ITO、IZO；或者，是金属和透明导电材料形成的堆叠结构，如ITO/Ag/ITO、Mo/AlNd/ITO等材料。
在一些实施例中，上述电荷传输层10可以包括空穴传输层；在另一些实施例中，上述电荷传输层10可以包括电子传输层。
其中，电荷传输层10在衬底1上的正投影覆盖第一电极9在衬底1上的正投影指的是：在同一子像素中，第一电极9在衬底1上的正投影位于电荷传输层10在衬底1上的正投影以内，包括但不限于如下情况：第一电极9在衬底1上的正投影的外轮廓位于电荷传输层10在衬底1上的正投影的外轮廓以内，此时，电荷传输层10在衬底1上的正投影的面积大于第一电极9在衬底1上的正投影的面积；或者，第一电极9在衬底1上的正投影的外轮廓与电荷传输层10在衬底1上的正投 影的外轮廓重叠，此时，电荷传输层10在衬底1上的正投影的面积等于第一电极9在衬底1上的正投影的面积。
在本申请的实施例中，通过在探测基板中设置阵列排布的多个子像素P，各子像素P包括控制单元KZ和电荷分布单元DH，使得控制单元KZ与电荷分别单元DH电连接，在各子像素P中，其控制单元KZ均能够控制电荷分布单元DH进行放电，这样，可以设置部分子像素的控制单元KZ控制电荷分布单元DH进行放电，设置部分子像素的控制单元KZ控制电荷分布单元DH不进行放电，从而形成电荷图案，实现了通过电信号对电荷图案的控制，提供了一种新的静电成像的方式，避免了相关技术中通过控制光源曝光来形成电荷图案时，外界光线的干扰造成的曝光精准度低的问题，提高了形成电荷图案的精准度，在该探测基板应用于打印装置中时，能够提高打印精度和打印清晰度，避免曝光过程受外界光线干扰造成的打印模糊；另外，在打印装置中，还可以省去相关技术中的遮光组件，简化打印装置的设计，降低成本。
在本申请的实施例提供的一探测基板中，如图9-图11所示，探测基板还包括第一信号线(例如VSS线)，第一信号线与控制单元KZ电连接，在电荷分布单元DH处于满电荷的状态下，第一信号线中传输的信号的电压小于第一电极9的电压；其中，第一信号线被配置为能够传输电压恒定的信号，电荷分布单元DH被配置为能够在控制单元的控制下，沿控制单元KZ向第一信号线放电。
示例性的，电荷分布单元DH处于满电荷的状态包括两种情况：电荷分布单元DH处于正电荷满电荷的状态；或者，电荷分布单元DH处于负电荷满电荷的状态。
需要说明的是，上述电荷分布单元DH处于满电荷的状态下指的是探测基板完成充电之后的状态。
示例性的，可以使用高压电给充电辊通电，并使得充电辊与探测基板的电荷传输层10表面接触，探测基板的电荷传输层10表面会带有均匀的电荷(正电荷或负电荷)，电荷传输层10表面上的电荷的极性与充电辊通电的电压的极性相同。探测基板的具体充电过程可以参考相关 技术中的打印机的充电过程，这里不进行详细介绍。
在本申请的实施例提供的一探测基板中，第一信号线包括接地线GND或负极电源信号线VSS。
在本申请的实施例中，通过控制单元KZ控制电荷分布单元DH与第一信号线之间的导通情况，在电荷分布单元DH与第一信号线之间导通的情况下，电荷分布单元DH能够沿着控制单元KZ向第一信号线放电，使得电荷分布单元DH的电荷传输层10表面的电荷消失(例如在图5中的子像素P2中，负电荷沿虚线箭头方向传输，与正电荷进行中和，使得电荷传输层10表面的正电荷逐渐消失)，从而使得部分子像素的电荷传输层10表面不带电，形成了电荷图案；这样，实现了通过电信号对电荷图案的控制，提供了一种新的静电成像的方式，避免了相关技术中通过控制光源曝光来形成电荷图案时，外界光线的干扰造成的曝光精准度低的问题。提高了形成电荷图案的精准度，在该探测基板应用于打印装置中时，能够提高打印精度和打印清晰度，避免曝光过程受外界光线干扰造成的打印模糊；另外，在打印装置中，还可以省去相关技术中的遮光组件，简化打印装置的设计，降低成本。
在本申请的实施例提供的一探测基板中，控制单元KZ包括至少两个晶体管，其中一个晶体管与数据线DL电连接，另一个晶体管与第一信号线(例如VSS)电连接。
这里对于上述晶体管的具体类型不进行限定。
示例性的，上述晶体管可以为薄膜晶体管(Thin Film Transistor，TFT)；或者，上述晶体管可以为金属-氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor,MOSFET)。
示例性的，上述晶体管可以均为N型晶体管；或者，上述晶体管可以均为P型晶体管。具体可以根据实际情况确定。
需要说明的是，如图7所示，在控制单元KZ中的各晶体管均为P型晶体管的情况下，对充电辊通负电，并使得充电辊与电荷传输层10表面接触，使得电荷传输层10表面带负电荷；如图8所示，在控制单元KZ中的各晶体管均为N型晶体管的情况下，对充电辊通正电，并使 得充电辊与电荷传输层10表面接触，使得电荷传输层10表面带正电荷。
下面，提供三种不同结构的控制单元KZ，并对各控制单元KZ中元器件的电连接方式和工作原理进行说明：
第一种，如图9所示，控制单元KZ包括第一晶体管M1和第二晶体管M2，第一晶体管M1的栅极与数据线DL(例如DL1或DL2)电连接，第一晶体管M1的第一端与第一电极9电连接，第一晶体管M1的第二端与第二晶体管M2的第一端电连接；第二晶体管M2的栅极与栅线GL(例如GL1或GL2)电连接，第二晶体管M2的第二端与第一信号线(例如VSS)电连接。
探测基板还可以包括栅极驱动电路和驱动芯片，其中，栅极驱动电路与各栅线GL电连接，用于控制各栅线GL对各行子像素P进行逐行扫描；驱动芯片与各数据线DL电连接，用于向数据线DL提供控制信号。
在图9所示的探测基板中，栅线GL提供的电信号控制第一晶体管M1是否导通，数据线DL提供的电信号控制第二晶体管M2是否导通，在栅线GL提供的电信号控制第一晶体管M1导通、且数据线DL提供的电信号控制第二晶体管M2导通的情况下，控制单元KZ将电荷分布单元DH与第一信号线(例如VSS)导通，从而能够使得电荷分布单元DH向第一信号线(例如VSS)放电，使得电荷分布单元DH表面的电荷消失。在第一晶体管M1导通与第二晶体管M2中有至少一个不导通的情况下，电荷分布单元DH与第一信号线(例如VSS)之间无法导通，电荷分布单元DH也就无法放电，电荷分布单元DH保持其电荷。这样，实现了通过电信号控制形成电荷图案。
第二种，如图10所示，控制单元KZ包括第一晶体管M1和第二晶体管M2，第一晶体管M1的栅极与数据线DL电连接，第一晶体管M1的第一端与第一电极9电连接，第一晶体管M1的第二端与第二晶体管M2的第一端共用；第二晶体管M2的栅极与栅线GL电连接，第二晶体管M2的第二端与第一信号线(例如VSS)电连接。
第二种控制单元KZ中的元器件的设置和电连接方式与第一种类似， 其工作原理也与第一种的情况相同，这里不再赘述。
需要说明的是，在第二种控制单元KZ中，设置了第一晶体管M1的第二端与第二晶体管M2的第一端共用，这样，在形成探测基板形成电荷图案的过程中，由于第一晶体管M1的第二端与第二晶体管M2的第一端共用，很大程度上缩短了电荷分布单元DH向第一信号线之间的放电路径，从而提高了电荷分布单元DH的放电速率，缩短了形成电荷图案的时间，在该探测基板应用于打印装置时，可以很大程度上缩短打印时间，提高用户体验。
第三种，如图11所示，控制单元包括第一晶体管M1和第二晶体管M2，第一晶体管M1的栅极与栅线GL电连接，第一晶体管M1的第一端与数据线DL电连接，第一晶体管M1的第二端与第二晶体管M2的栅极电连接；第二晶体管M2的第一端与第一电极9电连接，第二晶体管M2的第二端与第一信号线(例如VSS)电连接。
探测基板还可以包括栅极驱动电路和驱动芯片，其中，栅极驱动电路与各栅线GL电连接，用于控制各栅线GL对各行子像素P进行逐行扫描；驱动芯片与各数据线DL电连接，用于向数据线DL提供控制信号。
在图11所示的探测基板中，栅线GL提供的电信号用于控制第一晶体管M1是否导通，在第一晶体管M1导通的情况下，数据线DL提供的电信号用于控制第二晶体管M2是否导通；在栅线GL提供的电信号控制第一晶体管M1导通，数据线DL提供的电信号经过第一晶体管M1传输给第二晶体管M2的栅极，且控制第二晶体管M2导通的情况下，控制单元KZ将电荷分布单元DH与第一信号线(例如VSS)导通，从而能够使得电荷分布单元DH向第一信号线(例如VSS)放电，使得电荷分布单元DH表面的电荷消失。在第一晶体管M1导通与第二晶体管M2中有至少一个不导通的情况下，电荷分布单元DH与第一信号线(例如VSS)之间无法导通，电荷分布单元DH也就无法放电，电荷分布单元DH保持其电荷。这样，实现了通过电信号控制形成电荷图案。
在本申请的实施例提供的探测基板中，通过设置控制单元KZ的结 构可以为如上述描述的三种情况的其中一种，实现了单纯通过电信号控制形成电荷图案，提供了一种新的静电成像的方式，避免了相关技术中通过控制光源(激光器)曝光来形成电荷图案时，外界光线的干扰造成的曝光精准度低和激光器使用寿命较低的问题。提高了形成电荷图案的精准度，在该探测基板应用于打印装置中时，能够提高打印精度和打印清晰度，避免曝光过程受外界光线干扰造成的打印模糊；另外，在打印装置中，还可以省去相关技术中的遮光组件，简化打印装置的设计，降低成本。上述控制单元KZ的设计简单，易于实现。
在本申请的实施例提供的一探测基板中，电荷分布单元DH还包括缓冲层和电荷注入层，缓冲层位于第一电极与电荷传输层之间，电荷注入层位于缓冲层与电荷传输层之间，其中，电荷注入层注入的电荷的极性与电荷传输层传输的电荷的极性相同。
电荷注入层可以包括空穴注入层(HIL)和电子注入层(EIL)。
其中，在电荷传输层包括空穴传输层的情况下，电荷注入层可以包括空穴注入层；在电荷传输层包括电子传输层的情况下，电荷注入层可以包括电子注入层。
示例性的，空穴注入层的材料可包括氧化物，例如：钼氧化物、钛氧化物、钒氧化物、铼氧化物、钌氧化物、铬氧化物、锆氧化物、铪氧化物、钽氧化物、银氧化物、钨氧化物、锰氧化物。
示例性的，空穴注入层的材料也可包括有机材料，例如：六氰基六氮杂三亚苯基、2,3,5,6-四氟-7,7,8,8-四氰基对醌二甲烷(F4TCNQ)、1,2,3-三[(氰基)(4-氰基-2,3,5,6-四氟苯基)亚甲基]环丙烷。
示例性的，电子注入层的材料可为碱金属或者金属及其它们的化合物，例如：氟化锂(LiF)、镱(Yb)、镁(Mg)、钙(Ca)。
本申请的实施例中，通过在电荷分布单元DH中设置电荷注入层，能够进一步提高电荷传输速率，提高放电的速率，从而缩短形成电荷图案的时间。
在本申请的实施例提供的一探测基板中，如图7所示，电荷传输层10包括空穴传输层(HTL)，控制单元KZ中的各晶体管均为P型晶体 管。
其中，N型晶体管传递高电平，P型晶体管传递低电平。
在电荷传输层10包括空穴传输层(HTL)，控制单元KZ中的各晶体管均为P型晶体管的情况下如图7所示，对充电辊通负电，并使得充电辊与电荷传输层10表面接触，使得电荷传输层10表面带负电荷，其表面静电电位为-600V；再形成电荷图案，电荷分布单元DH对第一信号线进行放电的过程中，通过向电荷分布单元DH的表面传输正电荷(空穴)，以使得负电荷(电子)与正电荷(空穴)进行中和，从而使得电荷分布单元DH的表面的电荷消失，在向电荷分布单元DH的表面传输正电荷(空穴)的情况下，电荷分布单元DH的电荷传输层可以包括空穴传输层(具有空穴传输性能的膜层)，以使得空穴能够顺利传输至电荷分布单元DH的表面。
示例性的，空穴传输层(HTL)的材料可包括具有空穴传输特性的芳胺类、腙类、咪唑类、噻唑类、噁二唑类、丁二烯类化合物以及二甲基芴或者咔唑材料，例如：聚乙烯咔唑(PVK)4,4’-双[N-(1-萘基)-N-苯基氨基]联苯(NPB)、N,N’-双(3-甲基苯基)-N,N’-二苯基-[1,1’-联苯]-4,4’-二胺(TPD)、4-苯基-4’-(9-苯基芴-9-基)三苯基胺(BAFLP)、4,4’-双[N-(9,9-二甲基芴-2-基)-N-苯基氨基]联苯(DFLDPBi)、4,4’-二(9-咔唑基)联苯(CBP)、9-苯基-3-[4-(10-苯基-9-蒽基)苯基]-9H-咔唑(PCzPA)。
在本申请的实施例提供的一探测基板中，如图8所示，电荷传输层10包括电子传输层(ETL)，控制单元KZ中的各晶体管均为N型晶体管。
在电荷传输层10包括电子传输层(ETL)，控制单元KZ中的各晶体管均为N型晶体管的情况下，如图8所示，对充电辊通正电，并使得充电辊与电荷传输层10表面接触，使得电荷传输层10表面带正电荷，其表面静电电位为+600V，再形成电荷图案，电荷分布单元DH对第一信号线进行放电的过程中，通过向电荷分布单元DH的表面传输负电荷(电子)，以使得负电荷(电子)与正电荷(空穴)进行中和，从而使得电荷分布单元DH的表面的电荷消失，在向电荷分布单元DH的 表面传输负电荷(电子)的情况下，电荷分布单元DH的电荷传输层可以包括电子传输层(具有电子传输性能的膜层)，以使得电子能够顺利传输至电荷分布单元DH的表面。
示例性的，电子传输层(ETL)的材料可包括芳族杂环化合物，例如：苯并咪唑衍生物、咪唑衍生物、嘧啶衍生物、嗪衍生物、喹啉衍生物、异喹啉衍生物、菲咯啉衍生物等；电子传输层(ETL)的材料还可包括多硝基化合物(如2,4,7-三硝基芴酮，TNF)、氰基化合物、萘的酸酐衍生物、醌类化合物，或者无机的ZnO、IGZO、TiO 2、SnO 2等。
在本申请的实施例提供的一探测基板中，如图3-图6、图16-图17所示，探测基板包括：
第一导电层2，位于衬底1的一侧，第一导电层2包括栅线GL和各晶体管的栅极gt；
半导体层4，位于第一导电层2远离衬底1的一侧，与第一导电层2之间绝缘设置，半导体层4包括各晶体管的有源区41；
第二导电层5，位于半导体层4远离衬底1的一侧，包括数据线DL以及各晶体管的源极s和漏极d；其中，控制单元KZ中的至少一个晶体管的栅极gt在衬底1上的正投影与有源区41在衬底1上的正投影部分交叠。
这里对于上述半导体层4的材料不进行限制，在一些实施例中，半导体层4的材料可以包括非晶硅(a-Si)；在另一些实施例中，半导体层4的材料可以包括低温多晶硅(LTPS)；在另一些实施例中，半导体层4的材料可以包括金属氧化物，例如铟镓锌氧化物(IGZO)。
上述第一导电层2又可以称作栅极层，第二导电层5又可以称作源漏金属层，第一导电层2和第二导电层5的材料均包括导电材料，例如，金属铜。在图12和图13中，标记Gate的膜层为栅极层，标记Active的膜层为半导体层4，标记SD的膜层为源漏金属层。
在一些实施例中，如图3-图6所示，半导体层4包括各晶体管的有源区41，位于有源区41两侧的接触区42和接触区43，其中，半导体层4与第二导电层5直接接触，接触区42与源极5/s接触导通，接触 区43与漏极5/d接触导通。
在一些实施例中，如图16所示，半导体层4包括各晶体管的有源区41，位于有源区41两侧的接触区42和接触区43，其中，半导体层4与第二导电层5之间还设置有刻蚀阻挡层ESL，接触区42与源极5/s通过通孔导通，接触区43与漏极5/d通过通孔导通。
控制单元KZ中的至少一个晶体管的栅极gt在衬底1上的正投影与有源区41在衬底1上的正投影部分交叠，且使得至少一个晶体管的栅极gt在衬底1上的正投影与有源区41在衬底1上的正投影部分不交叠，有源区41在衬底1上的正投影与栅极gt不交叠的部分能够很大程度上提高晶体管的耐高压特性，这种设计称作Offset设计。
由于充电辊的通电电压通常较高，这样，在充电辊对探测基板进行充电时，使得探测基板的电荷分布单元DH上的电压也较高，在电荷分布单元DH对第一信号线进行放电的过程中，控制单元KZ中的晶体管需要承受较高的电压，为了避免控制单元KZ中的晶体管失效，延长控制单元KZ中的晶体管的使用寿命，通过上述设计，可以显著改善该问题，从而提高了控制单元KZ的电性的稳定，延长了探测基板的使用寿命。
在本申请的实施例提供的一探测基板中，如图12所示，第一晶体管M1的栅极gt在衬底1上的正投影与有源区41在衬底1上的正投影部分交叠；
第一晶体管M1的有源区41包括多个有源部Y以及连接相邻两个有源部Y之间的第一弯折部W1，部分第一弯折部W1在衬底1上的正投影位于栅极gt在衬底1上的正投影以内。
示例性的，一个有源区41中第一弯折部W1的数量小于有源部Y的数量；具体的，同一个晶体管中，第一弯折部W1的数量等于有源部Y的数量减去1。通过设置有源区包括多个有源部Y以及连接相邻两个有源部Y之间的第一弯折部W1，可以很大程度上提高晶体管的宽长比，从而提高通过晶体管的电流值Id。
在示例性的实施例中，还可以设置第二晶体管M2的栅极gt在衬 底1上的正投影与有源区41在衬底1上的正投影部分交叠；第二晶体管M2的有源区41包括多个有源部Y以及连接相邻两个有源部Y之间的第一弯折部W1，部分第一弯折部W1在衬底1上的正投影位于栅极gt在衬底1上的正投影以内。
在本申请的实施例中，一方面，通过设置有源区包括多个有源部Y以及连接相邻两个有源部Y之间的第一弯折部W1，可以很大程度上提高晶体管的宽长比从而提高通过晶体管的电流值Id；另一方面，通过设置部分第一弯折部W1在衬底1上的正投影位于栅极gt在衬底1上的正投影以内，这样有源区41在衬底1上的正投影与栅极gt不交叠的部分能够很大程度上提高晶体管的耐高压特性，从而提高晶体管的使用寿命，提高探测基板的产品品质。
在示例性的实施例中，有源区41的各有源部Y和各第一弯折部W1为一体化结构，这样，在实际制备工艺中，各有源部Y和各第一弯折部W1可以采用相同的材料在同一制备工艺中形成，制备工艺难度低且成本较低。
在实际应用中，当栅极gt控制晶体管的源极s和漏极d导通时，在有源区41中形成载流子沟道，有源区41由半导体变为导体，从而使得晶体管导通；在采用如图12所示的结构设计有源区41时，由于有源区41包括有源部Y和第一弯折部W1，第一弯折部W1由于其弯折结构以至于其内部的载流子迁移特性稍逊色于有源部Y。在图12中，沟道区域包括有源部Y和第一弯折部W1。
进一步的，在本申请的实施例提供的一探测基板中，如图13所示，第一晶体管M1的栅极gt在衬底1上的正投影与有源区41在衬底1上的正投影部分交叠；第一晶体管M1的有源区41包括多个有源部Y，第二导电层(例如SD)包括多个第二弯折部W2，相邻两个有源部Y之间通过第二弯折部W2电连接；第二弯折部W2在衬底1上的正投影与栅极gt在衬底1上的正投影互不交叠。
在图12和图13中，标记Gate的膜层为栅极层，标记Active的膜层为半导体层4，标记SD的膜层为源漏金属层。
本申请的实施例中，通过设置位于第二导电层中的多个第二弯折部W2将各有源部Y电连接在一起；一方面，第二弯折部W2原本就是导体，可以进一步缩小栅极gt的尺寸，使得第二弯折部W2在衬底1上的正投影与栅极gt在衬底1上的正投影互不交叠，从而使得有源区41和第二弯折部W2中与栅极不交叠的区域增大，提高晶体管的耐高压冲击性能；另一方面，当栅极gt控制晶体管的源极s和漏极d导通时，在有源区41的各有源部Y和第二弯折部W2中形成载流子沟道，各有源部Y由半导体变为导体，从而使得晶体管导通；再一方面，可以很大程度上提高晶体管的宽长比从而提高通过晶体管的电流值Id。其中，在图13中，沟道区域包括有源部Y和第二弯折部W2。
在示例性的实施例中，还可以设置第二晶体管M2的栅极gt在衬底1上的正投影与有源区41在衬底1上的正投影部分交叠；第二晶体管M2的有源区41包括多个有源部Y，第二导电层5(例如SD)包括多个第二弯折部W2，相邻两个有源部Y之间通过第二弯折部W2电连接；第二弯折部W2在衬底1上的正投影与栅极gt在衬底1上的正投影互不交叠。
在示例性的实施例中，如图12和图13所示，各有源部Y在衬底上的正投影的图形可以包括多边形，例如，矩形。
在本申请的实施例提供的一探测基板中，如图12和图13所示，相邻两个有源部Y之间具有间隙，栅极gt在衬底1上的正投影与部分间隙的外轮廓在衬底1上的正投影圈定的区域至少部分交叠。
其中，栅极gt在衬底1上的正投影与部分间隙的外轮廓在衬底1上的正投影圈定的区域至少部分交叠包括但不限于如下情况：
1、栅极gt在衬底1上的正投影与部分间隙的外轮廓在衬底1上的正投影圈定的区域部分交叠；
2、栅极gt在衬底1上的正投影与部分间隙的外轮廓在衬底1上的正投影圈定的区域完全交叠。
在本申请的实施例提供的一探测基板中，如图14和图15所示，第一晶体管M1的栅极gt可以包括多个重叠部以及至少一个连接部，连 接部将各重叠部电连接在一起，其中，重叠部在衬底1上的正投影与有源部Y在衬底1上的正投影重叠。
在本申请的实施例提供的一探测基板中，如图6所示，探测基板还包括像素定义层11(PDL)和多个像素隔断结构12，像素定义层11位于第一电极9远离衬底1的一侧；电荷传输层10位于像素定义层11远离衬底1的一侧；像素定义层11包括多个第一开口K1和多个第二开口K2，第一电极9在衬底1上的正投影与第一开口K1的外轮廓在衬底1上的正投影圈定的区域重叠，像素隔断结构12在衬底1上的正投影与第二开口K2的外轮廓在衬底1上的正投影圈定的区域重叠；像素隔断结构12位于相邻的两个子像素之间，电荷传输层10在像素隔断结构12位置处断开设置。
其中，像素定义层11的材料可包括有机材料，例如聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等。
在示例性的实施例中，第一开口K1沿垂直于衬底1厚度方向的深度小于第二开口K2沿垂直于衬底1厚度方向的深度。
示例性的，第一开口K1贯穿像素定义层11，第二开口K2不贯穿像素定义层11。
需要说明的是，将像素隔断结构12设置在第二开口K2内，一方面，使得像素隔断结构12与像素定义层11之间固定的稳定性更好，另一方面，增加了像素隔断结构12与像素定义层11之间的界面的尺寸，即使在像素隔断结构12与像素定义层11之间的交界位置处有载流子迁移，由于传播路径较长，也很难发生相邻子像素之间的串扰。
本申请的实施例提供的探测基板，通过设置第一电极9在衬底1上的正投影与第一开口K1的外轮廓在衬底1上的正投影圈定的区域重叠，将相邻两个子像素的第一电极9间隔开，避免相邻两个第一电极9之间电信号的串扰。另外，由于电荷传输层的载流子迁移率较高，为了避免不同子像素的电荷传输层10之间的载流子发生迁移，在像素定义层11的第二开口K2内设置像素隔断结构12，使得像素隔断结构12将相邻子像素的电荷传输层10隔开，从而避免不同子像素的电荷传输层 10之间的载流子发生迁移，避免在一个子像素中的电荷分布单元DH发生放电时，原本不需要放电的子像素受到干扰也发生一定程度的放电，降低了形成电荷图案的准确度。
在本申请的实施例提供的一探测基板中，衬底1为柔性衬底。
在本申请的实施例提供的一探测基板中，在第一状态下，各子像素中的电荷传输层均位于同一平面内；在第二状态下，各子像素中的电荷传输层均位于同一曲面，且探测基板在第二状态下的立体图形包括圆柱形。
在探测基板的衬底1为柔性衬底的情况下，可以设置探测基板为平面的结构；或者，也可以将探测基板卷曲成轴状(圆柱形)，类似于相关技术中的感光鼓的形态；
在本申请的实施例中，通过将探测基板卷曲成轴状，可以缩小探测基板占据的空间，以其适用于更多不同的产品或场景中。
在本申请的实施例提供的一探测基板中，如图4、图6和图17所示，探测基板还包括依次叠层设置的第一绝缘层6、有机层7和第二绝缘层8，第一绝缘层6覆盖各控制单元KZ，第二绝缘层8位于各第一电极9靠近衬底1的一侧；第一绝缘层8在相邻两个控制单元KZ之间的区域设置有多个凹槽C，有机层7延伸至凹槽C内。
示例性的，探测基板还包括栅绝缘层3，栅绝缘层3覆盖各栅极gt和各栅线。
示例性的，第一绝缘层6和第二绝缘层8的材料可以包括无机材料，例如，氮化硅、氧化硅或氮氧化硅中的至少一种。
示例性的，有机层7的材料可以包括树脂。
这里对于上述凹槽C的深度不进行限定。在一些实施例中，如图4所示，凹槽C可以贯穿第一绝缘层8。
本申请的实施例中，通过设置第一绝缘层8在相邻两个控制单元KZ之间的区域设置有多个凹槽C，有机层7延伸至凹槽C内；在探测基板进行弯曲时，凹槽C位置处能够有效释放无机膜层中的内应力，从而避免探测基板中的膜层发生裂纹，提高探测基板的可靠性和使用寿 命。
在本申请的实施例提供的一探测基板中，如图16所示，半导体层4的材料包括金属氧化物，探测基板还包括刻蚀阻挡层ESL，刻蚀阻挡层ESL覆盖半导体层4，第二导电层5位于刻蚀阻挡层ESL远离衬底1的一侧。
其中，刻蚀阻挡层ESL中设置有多个通孔，接触区42与源极5/s通过通孔导通，接触区43与漏极5/d通过通孔导通。
上述金属氧化物可以包括铟镓锌氧化物(IGZO)，通过设置刻蚀阻挡层ESL覆盖半导体层4，可以对半导体层4起到保护作用，避免在后续形成第二导电层5等工艺过程中对半导体层4造成损伤，从而确保晶体管的电性稳定。
如图18所示为本申请的实施例提供的一种晶体管在电压为300V的情况下的电流电压转移特性曲线(I-V曲线)，在Vds为300V的情况下，晶体管器件依然具有开关特性，且晶体管的阈值电压Vth接近0V。
如图19所示为本申请的实施例提供的一种晶体管在电压为600V的情况下的电流电压转移特性曲线(I-V曲线)，在关态(Vgs<Vth)时，Vds为600V的情况下，可见漏电流值为噪声级别，说明晶体管处于关态时，600V的高压下也没有被击穿，可以保证有效关断。
根据图18和图19所示的数据可以说明，本申请的实施例提供的控制单元KZ中的晶体管能够在高压下保持开关特性，并有效控制电荷分布单元DH的放电状态或保持状态，从而实现通过电信号控制形成电荷图案。需要说明的是，晶体管的耐高压的电压值与探测基板充电时的电压值相关，例如，探测基板在600V的情况下充电，而本申请的实施例提供的晶体管可以在此高压下保持开关特性。
本申请的实施例提供了一种探测装置，包括如前文中所述的探测基板。
在本申请的实施例中，通过控制单元KZ控制电荷分布单元DH与 第一信号线之间的导通情况，在电荷分布单元DH与第一信号线之间导通的情况下，电荷分布单元DH能够沿着控制单元KZ向第一信号线放电，使得电荷分布单元DH的电荷传输层10表面的电荷消失(例如在图5中的子像素P2中，负电荷沿虚线箭头方向传输，与正电荷进行中和，使得电荷传输层10表面的正电荷逐渐消失)，从而使得部分子像素的电荷传输层10表面不带电，形成了静电图案电荷图案；这样，实现了通过电信号对静电图案电荷图案的控制，提供了一种新的静电成像的方式，避免了相关技术中通过控制光源曝光来形成静电图案电荷图案时，外界光线的干扰造成的曝光精准度低的问题。
本申请的实施例提供了一种打印装置，包括如前文中所述的探测基板，还包括充电设备和驱动芯片，充电设备被配置为能够向探测基板的电荷分布单元充电，驱动芯片被配置为能够向探测基板传输控制信号。
其中，充电设备可以包括充电辊。
在本申请的实施例中，通过控制单元KZ控制电荷分布单元DH与第一信号线之间的导通情况，在电荷分布单元DH与第一信号线之间导通的情况下，电荷分布单元DH能够沿着控制单元KZ向第一信号线放电，使得电荷分布单元DH的电荷传输层10表面的电荷消失(例如在图5中的子像素P2中，负电荷沿虚线箭头方向传输，与正电荷进行中和，使得电荷传输层10表面的正电荷逐渐消失)，从而使得部分子像素的电荷传输层10表面不带电，形成了静电图案电荷图案；这样，实现了通过电信号对静电图案电荷图案的控制，提供了一种新的静电成像的方式，避免了相关技术中通过控制光源曝光来形成静电图案电荷图案时，外界光线的干扰造成的曝光精准度低的问题。提高了形成静电图案电荷图案的精准度，在该探测基板应用于打印装置中时，能够提高打印精度和打印清晰度，避免曝光过程受外界光线干扰造成的打印模糊；另外，在打印装置中，还可以省去相关技术中的遮光组件，简化打印装置的设计，降低成本。
本申请的实施例提供了一种探测基板的控制方法，应用于如前文中所述的探测基板，如图20所示，该方法包括：
S901、向探测基板充电，使得电荷分布单元DH处于满电荷状态；
上述电荷分布单元DH处于满电荷的状态下指的是探测基板完成充电之后的状态。
示例性的，可以使用高压电给充电辊通电，使得充电辊与探测基板的电荷传输层10表面接触，探测基板的电荷传输层10表面会带有均匀的电荷(正电荷或负电荷)，电荷传输层10表面上的电荷的极性与充电辊上的电压的极性相同。探测基板的具体充电过程可以参考相关技术中的打印机的充电过程，这里不进行详细介绍。
S902、向部分子像素的控制单元KZ输入第一控制信号，第一控制信号被配置为能够控制子像素的电荷分布单元DH放电，使得电荷分布单元表面不带电荷；
通过控制单元KZ控制电荷分布单元DH与第一信号线之间的导通情况，在电荷分布单元DH与第一信号线之间导通的情况下，电荷分布单元DH能够沿着控制单元KZ向第一信号线放电，使得电荷分布单元DH的电荷传输层10表面的电荷消失(例如在图5中的子像素P2中，负电荷沿虚线箭头方向传输，与正电荷进行中和，使得电荷传输层10表面的正电荷逐渐消失)，从而使得部分子像素的电荷传输层10表面不带电；
S903、向部分子像素的控制单元KZ输入第二控制信号，第二控制信号被配置为能够控制子像素的电荷分布单元DH上保持电荷；得到具有电荷图案的探测基板。
通过本申请的实施例提供的探测基板的控制方法，实现了通过电信号对电荷图案的控制，提供了一种新的静电成像的方式，避免了相关技术中通过控制光源曝光来形成电荷图案时，外界光线的干扰造成的曝光精准度低的问题。提高了形成电荷图案的精准度，在该探测基板应用于打印装置中时，能够提高打印精度和打印清晰度，避免曝光过程受外界光线干扰造成的打印模糊；另外，在打印装置中，还可以省去相关技术 中的遮光组件，简化打印装置的设计，降低成本。
本申请的实施例提供了一种探测基板的制备方法，该方法包括：
S01、提供衬底1，如图21所示，在衬底1上形成第一导电层2(例如栅极层)；
S02、在第一导电层2上形成栅绝缘层3；
S03、在栅绝缘层3上形成半导体层4；
S04、如图22所示，在半导体层4上形成刻蚀阻挡层ESL；
S05、如图23所示，在刻蚀阻挡层ESL上形成第二导电层5(例如源漏金属层)；
S06、在第二导电层5上形成第一绝缘层6；
S07、在第一绝缘层6上形成有机层7；
S08、如图24所示，在有机层7上形成第二绝缘层8；
S09、在第二绝缘层8上形成第一电极9；
S010、形成像素定义层和像素隔断结构，再形成电荷传输层10。
通过本申请的实施例提供的探测基板的制备方法制备的探测基板，实现了通过电信号对电荷图案的控制，提供了一种新的静电成像的方式，避免了相关技术中通过控制光源曝光来形成电荷图案时，外界光线的干扰造成的曝光精准度低的问题。提高了形成电荷图案的精准度，在该探测基板应用于打印装置中时，能够提高打印精度和打印清晰度，避免曝光过程受外界光线干扰造成的打印模糊；另外，在打印装置中，还可以省去相关技术中的遮光组件，简化打印装置的设计，降低成本。
需要说明的是，上述探测基板还可以包括其它结构和布局，上述探测基板的制备方法还可以包括其它工艺和步骤，本说明书仅介绍与发明点相关的制备过程，其包括的其它制备过程可以参考相关技术，这里不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种探测基板，其中，包括：
    衬底；
    位于所述衬底上沿第一方向延伸的多条数据线和沿第二方向延伸的多条栅线；所述第一方向与所述第二方向相交；
    阵列排布的多个子像素，所述子像素位于所述数据线和所述栅线限定的位置处，所述子像素分别与所述数据线和所述栅线电连接；
    其中，所述子像素包括控制单元和电荷分布单元，所述控制单元分别与所述数据线和所述栅线电连接，所述电荷分布单元包括第一电极和电荷传输层，所述第一电极与所述控制单元电连接，所述电荷传输层在所述衬底上的正投影覆盖所述第一电极在所述衬底上的正投影；所述电荷分布单元被配置为能够在所述控制单元的控制下进行放电。
  2. 根据权利要求1所述的探测基板，其中，所述探测基板还包括第一信号线，所述第一信号线与所述控制单元电连接，在所述电荷分布单元处于满电荷的状态下，所述第一信号线中传输的信号的电压小于所述第一电极的电压；
    其中，所述第一信号线被配置为能够传输电压恒定的信号，所述电荷分布单元被配置为能够在所述控制单元的控制下，沿所述控制单元向所述第一信号线放电。
  3. 根据权利要求2所述的探测基板，其中，所述第一信号线包括接地线或负极电源信号线。
  4. 根据权利要求2或3所述的探测基板，其中，所述控制单元包括至少两个晶体管，其中一个所述晶体管与所述数据线电连接，另一个所述晶体管与所述第一信号线电连接。
  5. 根据权利要求4所述的探测基板，其中，所述控制单元包括第一晶体管和第二晶体管，所述第一晶体管的栅极与所述数据线电连接，所述第一晶体管的第一端与所述第一电极电连接，所述第一晶体管的第二端与所述第二晶体管的第一端电连接；所述第二晶体管的栅极与所述栅线电连接，所述第二晶体管的第二端与所述第一信号线电连接。
  6. 根据权利要求4所述的探测基板，其中，所述控制单元包括第一晶体管和第二晶体管，所述第一晶体管的栅极与所述数据线电连接，所述第一晶体管的第一端与所述第一电极电连接，所述第一晶体管的第二端与所述第二晶体管的第一端共用；所述第二晶体管的栅极与所述栅线电连接，所述第二晶体管的第二端与所述第一信号线电连接。
  7. 根据权利要求4所述的探测基板，其中，所述控制单元包括第一晶体管和第二晶体管，所述第一晶体管的栅极与所述栅线电连接，所述第一晶体管的第一端与所述数据线电连接，所述第一晶体管的第二端与所述第二晶体管的栅极电连接；所述第二晶体管的第一端与所述第一电极电连接，所述第二晶体管的第二端与所述第一信号线电连接。
  8. 根据权利要求1所述的探测基板，其中，所述电荷分布单元还包括缓冲层和电荷注入层，所述缓冲层位于所述第一电极与所述电荷传输层之间，所述电荷注入层位于所述缓冲层与所述电荷传输层之间；其中，所述电荷注入层注入的电荷的极性与所述电荷传输层传输的电荷的极性相同。
  9. 根据权利要求1-3、5-8中任一项所述的探测基板，其中，所述电荷传输层包括空穴传输层，所述控制单元中的各所述晶体管均为P型晶体管。
  10. 根据权利要求1-3、5-8中任一项所述的探测基板，其中，所述电荷传输层包括电子传输层，所述控制单元中的各所述晶体管均为N型晶体管。
  11. 根据权利要求5-7中任一项所述的探测基板，其中，所述探测基板包括：
    第一导电层，位于所述衬底的一侧，所述第一导电层包括栅线和各所述晶体管的栅极；
    半导体层，位于所述第一导电层远离所述衬底的一侧，与所述第一导电层之间绝缘设置，所述半导体层包括各所述晶体管的有源区；
    第二导电层，位于所述半导体层远离所述衬底的一侧，包括所述数据线以及各所述晶体管的源极和漏极；
    其中，所述控制单元中的至少一个所述晶体管的所述栅极在所述衬底上的正投影与所述有源区在所述衬底上的正投影部分交叠。
  12. 根据权利要求11所述的探测基板，其中，所述第一晶体管的所述栅极在所述衬底上的正投影与所述有源区在所述衬底上的正投影部分交叠；
    所述第一晶体管的有源区包括多个有源部以及连接相邻两个所述有源部之间的第一弯折部，部分所述第一弯折部在所述衬底上的正投影位于所述栅极在所述衬底上的正投影以内。
  13. 根据权利要求11所述的探测基板，其中，所述第一晶体管的所述栅极在所述衬底上的正投影与所述有源区在所述衬底上的正投影部分交叠；
    所述第一晶体管的有源区包括多个有源部，所述第二导电层包括多个第二弯折部，相邻两个所述有源部之间通过所述第二弯折部电连接；所述第二弯折部在所述衬底上的正投影与所述栅极在所述衬底上的正投影互不交叠。
  14. 根据权利要求12或13所述的探测基板，其中，相邻两个所述有源部之间具有间隙，所述栅极在所述衬底上的正投影与部分所述间隙的外轮廓在所述衬底上的正投影圈定的区域至少部分交叠。
  15. 根据权利要求1所述的探测基板，其中，所述探测基板还包括像素定义层和多个像素隔断结构，所述像素定义层位于所述第一电极远离所述衬底的一侧；所述电荷传输层位于所述像素定义层远离所述衬底的一侧；
    所述像素定义层包括多个第一开口和多个第二开口，所述第一电极在所述衬底上的正投影与所述第一开口的外轮廓在所述衬底上的正投影圈定的区域重叠，所述像素隔断结构在所述衬底上的正投影与所述第二开口的外轮廓在所述衬底上的正投影圈定的区域重叠；
    所述像素隔断结构位于相邻的两个所述子像素之间，所述电荷传输层在所述像素隔断结构位置处断开设置。
  16. 根据权利要求1所述的探测基板，其中，所述衬底为柔性衬底。
  17. 根据权利要求16所述的探测基板，其中，在第一状态下，各所述子像素中的所述电荷传输层均位于同一平面内；
    在第二状态下，各所述子像素中的所述电荷传输层均位于同一曲面，且所述探测基板在所述第二状态下的立体图形包括圆柱形。
  18. 根据权利要求17所述的探测基板，其中，所述探测基板还包括依次叠层设置的第一绝缘层、有机层和第二绝缘层，所述第一绝缘层覆盖各所述控制单元，所述第二绝缘层位于各所述第一电极靠近所述衬底的一侧；
    所述第一绝缘层在相邻两个所述控制单元之间的区域设置有多个凹槽，所述有机层延伸至所述凹槽内。
  19. 根据权利要求11所述的探测基板，其中，所述半导体层的材料包括金属氧化物，所述探测基板还包括刻蚀阻挡层，所述刻蚀阻挡层覆盖所述半导体层，所述第二导电层位于所述刻蚀阻挡层远离所述衬底的一侧。
  20. 一种探测装置，其中，包括如权利要求1-19中任一项所述的探测基板。
  21. 一种打印装置，其中，包括如权利要求1-19中任一项所述的探测基板，还包括充电设备和驱动芯片，所述充电设备被配置为能够向所述探测基板的电荷分布单元充电，所述驱动芯片被配置为能够向所述探测基板传输控制信号。
  22. 一种探测基板的控制方法，其中，应用于如权利要求1-19中任一项所述的探测基板，所述方法包括：
    向所述探测基板充电，使得所述电荷分布单元处于满电荷状态；
    向部分所述子像素的所述控制单元输入第一控制信号，所述第一控制信号被配置为能够控制所述子像素的所述电荷分布单元放电，使得所述电荷分布单元表面不带电荷；
    向部分所述子像素的所述控制单元输入第二控制信号，所述第二控制信号被配置为能够控制所述子像素的所述电荷分布单元上保持电荷；得到具有电荷图案的所述探测基板。
PCT/CN2022/132357 2022-11-16 2022-11-16 探测基板及其控制方法、探测装置、打印装置 WO2024103311A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112133717A (zh) * 2020-09-24 2020-12-25 京东方科技集团股份有限公司 一种探测基板及射线探测器
CN113410258A (zh) * 2021-06-18 2021-09-17 福州京东方光电科技有限公司 一种探测基板、探测装置
CN113721432A (zh) * 2021-09-16 2021-11-30 北京京东方技术开发有限公司 电控鼓及其制作方法、打印机
CN114388538A (zh) * 2020-10-22 2022-04-22 北京京东方传感技术有限公司 一种探测基板、平板探测器

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Publication number Priority date Publication date Assignee Title
CN112133717A (zh) * 2020-09-24 2020-12-25 京东方科技集团股份有限公司 一种探测基板及射线探测器
CN114388538A (zh) * 2020-10-22 2022-04-22 北京京东方传感技术有限公司 一种探测基板、平板探测器
CN113410258A (zh) * 2021-06-18 2021-09-17 福州京东方光电科技有限公司 一种探测基板、探测装置
CN113721432A (zh) * 2021-09-16 2021-11-30 北京京东方技术开发有限公司 电控鼓及其制作方法、打印机

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