WO2024101307A1 - セラミック電子部品およびその製造方法 - Google Patents

セラミック電子部品およびその製造方法 Download PDF

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Publication number
WO2024101307A1
WO2024101307A1 PCT/JP2023/039886 JP2023039886W WO2024101307A1 WO 2024101307 A1 WO2024101307 A1 WO 2024101307A1 JP 2023039886 W JP2023039886 W JP 2023039886W WO 2024101307 A1 WO2024101307 A1 WO 2024101307A1
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Prior art keywords
layer
dielectric
electronic component
ceramic electronic
internal electrode
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English (en)
French (fr)
Japanese (ja)
Inventor
須賀康友
猪又康之
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Taiyo Yuden Co Ltd
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Taiyo Yuden Co Ltd
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Priority to CN202380077852.8A priority Critical patent/CN120188242A/zh
Priority to JP2024557394A priority patent/JPWO2024101307A1/ja
Publication of WO2024101307A1 publication Critical patent/WO2024101307A1/ja
Priority to US19/178,004 priority patent/US20250273395A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
    • H01G4/1227—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates based on alkaline earth titanates

Definitions

  • the present invention relates to ceramic electronic components and methods for manufacturing the same.
  • thinning the internal electrode layer may cause discontinuities in the internal electrode layer, reducing the continuity rate.
  • the present invention has been made in consideration of the above problems, and aims to provide a ceramic electronic component and a manufacturing method thereof that can improve the continuity rate of the internal electrode layers.
  • the ceramic electronic component according to the present invention comprises a laminated chip in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately laminated, and at least one of the plurality of dielectric layers comprises a first layer located toward the center in the stacking direction, and a second layer adjacent to the internal electrode layer and having an average particle size of dielectric particles smaller than that of the first layer.
  • the average particle size of the dielectric particles in the second layer may be 0.02 ⁇ m or less.
  • the particle size of the dielectric particles in the second layer may be 0.025 ⁇ m or less.
  • the average particle size of the dielectric particles in the first layer may be 0.035 ⁇ m or more.
  • the particle size of the dielectric particles in the first layer may be 0.03 ⁇ m or more.
  • the average particle size of the dielectric particles in the first layer may be 0.08 ⁇ m or less.
  • the particle size of the dielectric particles in the first layer may be 0.085 ⁇ m or less.
  • the first layer may contain flat particles whose maximum length is three or more times the minimum length in a cross section including the stacking direction.
  • 60% or more of the dielectric particles contained in the first layer may be the flat particles.
  • the angle between the average direction of the long diameter of the flat particles and the direction in which the dielectric layer extends may be ⁇ 20° or less.
  • the main component of the multiple dielectric layers may be a ferroelectric.
  • 80% or more of the dielectric layers may include the first layer and the second layer.
  • the method for manufacturing a ceramic electronic component according to the present invention is characterized by comprising the steps of alternately laminating a dielectric green sheet, in which a first green sheet containing a ceramic material is laminated on the upper and lower surfaces thereof with a second green sheet containing a ceramic material having an average grain size smaller than the average grain size of the ceramic material of the first green sheet, and an internal electrode pattern for an internal electrode layer to form a laminate, and firing the laminate.
  • the present invention provides a ceramic electronic component and a manufacturing method thereof that can improve the continuity rate of the internal electrode layers.
  • FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor.
  • 2 is a cross-sectional view taken along line AA in FIG. 1.
  • 2 is a cross-sectional view taken along line BB in FIG. 1.
  • FIG. 13 is a diagram showing a continuity ratio.
  • FIG. 13 is a diagram illustrating an example of an XZ cross section.
  • FIG. 13 is a diagram illustrating an example of an XZ cross section.
  • 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor.
  • 4(a) to 4(c) are diagrams illustrating a lamination process.
  • FIG. 1 is a partially sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment.
  • FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1.
  • FIG. 3 is a cross-sectional view taken along line B-B in FIG. 1.
  • the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape, and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the upper and lower faces in the lamination direction are referred to as side faces.
  • the external electrodes 20a, 20b extend on the upper, lower and two side faces in the lamination direction of the laminated chip 10. However, the external electrodes 20a and 20b are spaced apart from each other.
  • the Z-axis direction is the direction in which the multiple internal electrode layers 12 face each other, the stacking direction of the dielectric layers 11, and the direction in which the top and bottom surfaces of the laminated chip 10 face each other.
  • the X-axis direction is the length direction of the laminated chip 10, the direction in which the two end faces of the element body 10 face each other, the direction in which the external electrodes 20a and 20b face each other, and the longitudinal direction in which the dielectric layers 11 extend.
  • the Y-axis direction is the width direction of the internal electrode layers 12, and the direction in which the two side faces other than the two end faces of the four side faces of the laminated chip 10 face each other.
  • the laminated chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 mainly composed of metal are alternately laminated.
  • the laminated chip 10 has a plurality of internal electrode layers 12 facing each other and a dielectric layer 11 sandwiched between the plurality of internal electrode layers 12.
  • the edges in the direction in which each internal electrode layer 12 extends are alternately exposed to the first end face on which the external electrode 20a of the laminated chip 10 is provided and the second end face on which the external electrode 20b is provided.
  • the internal electrode layer 12 connected to the external electrode 20a is not connected to the external electrode 20b.
  • the internal electrode layer 12 connected to the external electrode 20b is not connected to the external electrode 20a.
  • each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b.
  • the internal electrode layer 12 is disposed on the top layer in the lamination direction, and the internal electrode layer 12 is also disposed on the bottom layer in the lamination direction, and the top and bottom surfaces of the laminate are covered with a cover layer 13.
  • the cover layer 13 is mainly composed of a ceramic material.
  • the cover layer 13 may have the same composition as the dielectric layer 11 or may have a different composition.
  • a ceramic material having a perovskite structure represented by the general formula ABO 3 can be used as the main component of the dielectric layer 11.
  • the perovskite structure may contain ABO 3- ⁇ that is not stoichiometric.
  • the ceramic material may be selected from at least one of BaTiO 3 (barium titanate), CaZrO 3 (calcium zirconate), CaTiO 3 (calcium titanate), SrTiO 3 (strontium titanate), MgTiO 3 (magnesium titanate), Ba 1-x-y Ca x Sr y Ti 1-z Zr z O 3 (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ z ⁇ 1) that forms a perovskite structure, and the like.
  • Ba1 -xyCaxSryTi1 - zZrzO3 is barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate and barium calcium titanate zirconate , etc.
  • ferroelectric materials with a relative dielectric constant of 1000 or more.
  • the dielectric layer 11 may contain additives.
  • additives to the dielectric layer 11 include oxides of magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing Co, Ni, Li, B, Na, K, or Si.
  • the main component of the internal electrode layer 12 is a base metal such as Ni, copper (Cu), or tin (Sn), or an alloy containing these.
  • the main component of the internal electrode layer 12 may be a precious metal such as platinum (Pt), palladium (Pd), silver (Ag), or gold (Au), or an alloy containing these.
  • the size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm long, 0.125 mm wide, and 0.125 mm high, or 0.4 mm long, 0.2 mm wide, and 0.2 mm high, or 0.6 mm long, 0.3 mm wide, and 0.3 mm high, or 0.6 mm long, 0.3 mm wide, and 0.110 mm high, or 1.0 mm long, 0.5 mm wide, and 0.5 mm high, or 1.0 mm long, 0.5 mm wide, and 0.1 mm high, or 3.2 mm long, 1.6 mm wide, and 1.6 mm high, or 4.5 mm long, 3.2 mm wide, and 2.5 mm high, but is not limited to these sizes.
  • the length and width may be interchanged for these sizes.
  • the multilayer ceramic capacitor 100 may also be a three-terminal multilayer ceramic capacitor having three external electrodes.
  • each dielectric layer 11 is, for example, 0.3 ⁇ m to 20 ⁇ m, or 0.3 ⁇ m to 10 ⁇ m, or 0.4 ⁇ m to 8 ⁇ m, or 0.5 ⁇ m to 5 ⁇ m.
  • the thickness of each dielectric layer 11 can be measured by exposing the cross section of the multilayer ceramic capacitor 100, for example, as shown in FIG. 2, by mechanical polishing, and then obtaining the average thickness value at 10 points from an image taken by a microscope such as a scanning transmission electron microscope.
  • each internal electrode layer 12 is, for example, 0.1 ⁇ m to 2 ⁇ m, or 0.2 ⁇ m to 1 ⁇ m, or 0.3 ⁇ m to 0.8 ⁇ m.
  • the thickness of each internal electrode layer 12 can be measured by exposing the cross section of the multilayer ceramic capacitor 100, for example, as shown in FIG. 2, by mechanical polishing, and then obtaining the average thickness value at 10 locations from an image taken by a microscope such as a scanning transmission electron microscope.
  • the number of layers of the internal electrode layers 12 is, for example, about 50 or more and about 500 or less.
  • the layer density of the internal electrode layers 12 is about 20 layers/mm or more and about 1500 layers/mm or less.
  • the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region that generates capacitance in the multilayer ceramic capacitor 100. Therefore, this region that generates capacitance is referred to as the capacitance section 14.
  • the capacitance section 14 is a region where adjacent internal electrode layers connected to different external electrodes face each other.
  • the region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b being interposed therebetween is called the end margin 15.
  • the region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a being interposed therebetween is also the end margin 15.
  • the end margin is the region where the internal electrode layers connected to the same external electrode face each other without an internal electrode layer connected to a different external electrode being interposed therebetween.
  • the end margin 15 is a region that does not generate capacitance.
  • the end margin 15 may have the same composition as the dielectric layer 11 of the capacitance section 14, or may have a different composition.
  • the side margin 16 is a region that is provided to cover the ends of the multiple internal electrode layers 12 that are laminated in the laminated structure and extend to the two side faces.
  • the side margin 16 is also a region that does not generate capacitance.
  • the side margin 16 may have the same composition as the dielectric layer 11 of the capacitance section 14, or it may have a different composition.
  • the internal electrode layers 12 will be made thinner. However, making the internal electrode layers 12 thinner reduces the continuity of the internal electrode layers 12.
  • the continuity rate which is an index that represents the continuity of the internal electrode layers 12.
  • FIG. 4 is a diagram showing the continuity rate. As shown in FIG. 4, in an observation area of length L0 in a certain internal electrode layer 12, the lengths L1, L2, ..., Ln of the metal parts are measured and added together, and the ratio of the metal parts, ⁇ Ln/L0, can be defined as the continuity rate of that layer. The closer this continuity rate is to 100%, the better the continuity of the internal electrode layer 12.
  • the multilayer ceramic capacitor 100 has a configuration that can improve the continuity of the internal electrode layers 12.
  • FIG. 5 is an enlarged view of the XZ cross section.
  • FIG. 5 illustrates an enlarged view of the XZ cross section of the capacitance section 14 as an example.
  • the dielectric layer 11 has a structure in which a plurality of dielectric particles 30 are sintered.
  • the dielectric layer 11 has a first layer 111 in the center in the Z-axis direction, and a second layer 112 at both ends in the Z-axis direction. That is, the dielectric layer 11 has a configuration in which one first layer 111 is sandwiched between two second layers 112. The second layer 112 is adjacent to the internal electrode layer 12.
  • the average particle size of the dielectric particles 30 contained in the dielectric layer 11 is larger in the first layer 111 than in the second layer 112.
  • the area of the dielectric layer 11 that contacts the adjacent internal electrode layer 12 becomes the second layer 112. Since the average particle size of the dielectric particles 30 is small in the second layer 112, the surface roughness of the second layer 112 is small, and as a result, the internal electrode layer 12 that contacts the second layer 112 is also flat, and the continuity rate of the internal electrode layer 12 is high.
  • the dielectric constant of the dielectric layer 11 will be low.
  • the first layer 111 is provided in the center of the dielectric layer 11. This allows the dielectric constant of the dielectric layer 11 to be maintained high.
  • the average particle size of the dielectric particles 30 in the second layer 112 is not small enough, the surface roughness of the second layer 112 may not be sufficiently small. Therefore, it is preferable to set an upper limit on the average particle size in the second layer 112.
  • the average particle size in the second layer 112 is preferably 0.02 ⁇ m or less, more preferably 0.018 ⁇ m or less, and even more preferably 0.016 ⁇ m or less.
  • the upper limit of the particle size of each dielectric particle 30 contained in the second layer 112 is preferably 0.025 ⁇ m or less, more preferably 0.023 ⁇ m or less, and even more preferably 0.021 ⁇ m or less.
  • the average particle size of the dielectric particles 30 in the second layer 112 is preferably 0.010 ⁇ m or more, more preferably 0.012 ⁇ m or more, and even more preferably 0.014 ⁇ m or more.
  • the lower limit of the particle size of each dielectric particle 30 contained in the second layer 112 is preferably 0.005 ⁇ m or more, more preferably 0.007 ⁇ m or more, and even more preferably 0.009 ⁇ m or more.
  • the average particle size of the dielectric particles 30 in the first layer 111 is not sufficiently large, there is a risk that a sufficient relative dielectric constant will not be obtained in the dielectric layer 11. Therefore, it is preferable to set a lower limit for the average particle size in the first layer 111.
  • the average particle size in the first layer 111 is preferably 0.035 ⁇ m or more, more preferably 0.037 ⁇ m or more, and even more preferably 0.039 ⁇ m or more.
  • the lower limit of the particle size of each dielectric particle 30 contained in the first layer 111 is preferably 0.03 ⁇ m or more, more preferably 0.032 ⁇ m or more, and even more preferably 0.034 ⁇ m or more.
  • the average particle size of the dielectric particles 30 in the first layer 111 is preferably 0.08 ⁇ m or less, more preferably 0.078 ⁇ m or less, and even more preferably 0.076 ⁇ m or less.
  • the upper limit of the particle size of the dielectric particles 30 contained in the first layer 111 is preferably 0.085 ⁇ m or less, more preferably 0.083 ⁇ m or less, and even more preferably 0.081 ⁇ m or less.
  • the thickness of the first layer 111 is 1/30 to 1/4 of the thickness of the dielectric layer 11, and the thickness of each second layer 112 is 1/20 to 1/50 of the thickness of the dielectric layer 11.
  • the particle size of the dielectric particles 30 can be measured by measuring the maximum diameter of the dielectric particles observed in the SEM or TEM photograph of the XZ cross section.
  • the average particle size of the dielectric particles 30 can be measured by measuring the average value of the maximum diameters of the dielectric particles observed in the SEM or TEM photograph of the XZ cross section.
  • the dielectric particles 30 of the first layer 111 have a flat shape in the XZ cross section, as illustrated in FIG. 6.
  • particles whose maximum length is three times or more their minimum length are defined as flat-shaped particles.
  • the dielectric particles 30 contained in the first layer 111 have a flat shape, it is more preferable that 55% or more have a flat shape, and it is even more preferable that 50% or more have a flat shape.
  • the flattened dielectric particles 30 are oriented. Specifically, it is preferable that the angle between the X-axis direction (the direction in which the dielectric layer 11 extends) and the average direction of the major axis of each dielectric particle 30 is ⁇ 20° or less. In this configuration, it is possible to increase the relative dielectric constant of the dielectric layer 11 while preventing the dielectric layer 11 from becoming thick.
  • the average direction of each dielectric particle 30 can be measured by measuring the average value of the major axis direction of the dielectric particles observed in a SEM or TEM photograph of the XZ cross section.
  • At least one dielectric layer 11 may include the first layer 111 and the second layer 112.
  • Figure 7 is a diagram illustrating the flow of the manufacturing method of the multilayer ceramic capacitor 100.
  • a dielectric material for forming the dielectric layer 11 is prepared.
  • the A-site elements and B-site elements contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO3 particles.
  • BaTiO3 is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate.
  • a predetermined additive compound is added to the obtained ceramic powder according to the purpose.
  • the additive compound include oxides of magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm) and ytterbium (Yb)), or oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K) or silicon (Si), or glasses containing Co, Ni, Li, B, Na, K or Si.
  • SiO 2 mainly functions as a sintering aid.
  • a compound containing an additive compound is wet mixed with a ceramic raw material powder, and then dried and pulverized to prepare a ceramic material.
  • the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. Through the above steps, a dielectric material is obtained.
  • the particle size of the dielectric material used to form the first layer 111 is made large, and the particle size of the dielectric material used to form the second layer 112 is made small.
  • a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained raw material powder and wet mixed.
  • a dielectric green sheet 52 is applied onto a substrate 51 by, for example, a die coater method, a doctor blade method, or a spin coat method, as illustrated in Fig. 8(a), and then dried.
  • the substrate 51 is, for example, a polyethylene terephthalate (PET) film.
  • FIG. 8(b) is a diagram illustrating the details of the dielectric green sheet 52.
  • the dielectric material for forming the second layer 112 is applied to form a small grain size green sheet 522
  • the dielectric material for forming the first layer 111 is applied thereon to form a large grain size green sheet 521
  • the dielectric material for forming the second layer 112 is applied thereon to form a small grain size green sheet 522.
  • the first layer 111 is applied using spin coating, the long diameter direction of the flat ceramic powder tends to be oriented close to the in-plane direction.
  • the dielectric material for forming the second layer 112 may be deposited by a vacuum deposition method such as sputtering to form a small grain size green sheet 522
  • the dielectric material for forming the first layer 111 may be deposited on top of the small grain size green sheet 522 by a vacuum deposition method to form a large grain size green sheet 521
  • the dielectric material for forming the second layer 112 may be deposited on top of the large grain size green sheet 521 by a vacuum deposition method to form a small grain size green sheet 522.
  • the internal electrode pattern 53 is formed on the dielectric green sheet 52.
  • the dielectric green sheet 52 on which the internal electrode pattern 53 is formed is regarded as a stacking unit.
  • each internal electrode pattern 53 a metal paste of the main component metal of the internal electrode layer 12 is used.
  • the film formation method may be printing, sputtering, vapor deposition, etc.
  • the shape of each internal electrode pattern 53 corresponds to the internal electrode layer 12.
  • the dielectric green sheet 52 is peeled off from the substrate 51 while stacking the laminate units as shown in FIG. 8(c).
  • cover sheets 54 e.g., 2 to 10 layers are laminated on the top and bottom of the laminate obtained by stacking the stacking units, thermocompressed, and cut to the specified chip dimensions (e.g., 1.0 mm x 0.5 mm). In the example of FIG. 8(c), cutting is performed along the dotted lines.
  • the cover sheet 54 may be of the same composition as the dielectric green sheet 52, or may contain different additives.
  • the ceramic laminate thus obtained is subjected to a binder removal process in a N2 atmosphere, and then a metal paste that will become the base layer of the external electrodes 20a, 20b is applied by a dipping method or the like.
  • the metal paste contains a co-material.
  • the metal paste is applied to the two end faces of the laminate where the internal electrode pattern 53 is exposed.
  • a re-oxidation treatment may be performed at 600° C. to 1000° C. in a N 2 gas atmosphere.
  • a plating layer may be formed on the underlayer by plating, thereby completing the multilayer ceramic capacitor 100.
  • a small grain size green sheet 522 is formed, a large grain size green sheet 521 is formed on the small grain size green sheet 522, and then a small grain size green sheet 522 is formed on the large grain size green sheet 521 to form the dielectric green sheet 52.
  • a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this.
  • the configuration of each of the above embodiments can also be applied to other multilayer ceramic electronic components, such as varistors and thermistors.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Inorganic Chemistry (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)
  • Materials Engineering (AREA)
PCT/JP2023/039886 2022-11-08 2023-11-06 セラミック電子部品およびその製造方法 Ceased WO2024101307A1 (ja)

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JP2024557394A JPWO2024101307A1 (https=) 2022-11-08 2023-11-06
US19/178,004 US20250273395A1 (en) 2022-11-08 2025-04-14 Ceramic electronic device and manufacturing method of the same

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299145A (ja) * 2001-03-29 2002-10-11 Kyocera Corp セラミック積層体およびその製法
JP2014053584A (ja) * 2012-09-10 2014-03-20 Samsung Electro-Mechanics Co Ltd 積層セラミック電子部品及びその製造方法
JP2019096779A (ja) * 2017-11-24 2019-06-20 京セラ株式会社 コンデンサ

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299145A (ja) * 2001-03-29 2002-10-11 Kyocera Corp セラミック積層体およびその製法
JP2014053584A (ja) * 2012-09-10 2014-03-20 Samsung Electro-Mechanics Co Ltd 積層セラミック電子部品及びその製造方法
JP2019096779A (ja) * 2017-11-24 2019-06-20 京セラ株式会社 コンデンサ

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