WO2024100499A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024100499A1
WO2024100499A1 PCT/IB2023/061021 IB2023061021W WO2024100499A1 WO 2024100499 A1 WO2024100499 A1 WO 2024100499A1 IB 2023061021 W IB2023061021 W IB 2023061021W WO 2024100499 A1 WO2024100499 A1 WO 2024100499A1
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Prior art keywords
insulating layer
layer
conductive layer
transistor
semiconductor
Prior art date
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Ceased
Application number
PCT/IB2023/061021
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English (en)
French (fr)
Japanese (ja)
Inventor
島行徳
肥塚純一
神長正美
熊倉佳代
中田昌孝
楠紘慈
熱海知昭
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to KR1020257015464A priority Critical patent/KR20250108622A/ko
Priority to CN202380077483.2A priority patent/CN120202740A/zh
Priority to JP2024556823A priority patent/JPWO2024100499A1/ja
Publication of WO2024100499A1 publication Critical patent/WO2024100499A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional [2D] radiating surfaces
    • H05B33/14—Light sources with substantially two-dimensional [2D] radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Definitions

  • One aspect of the present invention relates to a semiconductor device and a manufacturing method thereof.
  • One aspect of the present invention relates to a transistor and a manufacturing method thereof.
  • One aspect of the present invention relates to a display device having a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, or manufacturing methods thereof.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.
  • Display devices are used in, for example, mobile information terminals, television devices (also called television receivers), digital signage, and public information displays (PIDs).
  • display devices include display devices having organic electroluminescence (EL) elements or light-emitting diodes (LEDs), display devices having liquid crystal elements, and electronic paper that displays using an electrophoretic method.
  • EL organic electroluminescence
  • LEDs light-emitting diodes
  • the pixel size can be reduced and the resolution can be increased.
  • the aperture ratio can be increased. For these reasons, there is a demand for miniaturized transistors.
  • Devices requiring high-definition display devices such as those for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR), are being actively developed.
  • VR virtual reality
  • AR augmented reality
  • SR substitute reality
  • MR mixed reality
  • Patent document 1 discloses a high-definition display device that uses organic EL elements.
  • One aspect of the present invention has an object to provide a transistor with a minute size. Another object is to provide a transistor with a short channel length. Another object is to provide a transistor with a large on-state current. Another object is to provide a transistor with good electrical characteristics. Another object is to provide a semiconductor device with a small occupation area. Another object is to provide a semiconductor device with low wiring resistance. Another object is to provide a semiconductor device or display device with low power consumption. Another object is to provide a highly reliable transistor, semiconductor device, or display device. Another object is to provide a display device with high definition. Another object is to provide a method for manufacturing a semiconductor device or display device with high productivity. Another object is to provide a new transistor, semiconductor device, or display device, or a manufacturing method thereof.
  • One embodiment of the present invention is a semiconductor device including a transistor and a first insulating layer.
  • the transistor includes a first conductive layer, a second conductive layer having a region overlapping with the first conductive layer via the first insulating layer, and a semiconductor layer.
  • the second conductive layer has a first opening in a region overlapping with the first conductive layer.
  • the first insulating layer has a second opening reaching the first conductive layer in a region overlapping with the first opening.
  • the semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer through the first opening and the second opening.
  • the first insulating layer has an oxygen diffusion coefficient of 5 ⁇ 10 ⁇ 12 cm 2 /sec or more at 350° C.
  • the oxygen diffusion coefficient is preferably calculated by thermal desorption spectrometry or secondary ion mass spectrometry.
  • the semiconductor layer preferably contains a metal oxide.
  • the semiconductor device it is preferable to have a second insulating layer and a third insulating layer.
  • the second insulating layer is preferably located between the first insulating layer and the first conductive layer.
  • the third insulating layer is preferably located between the first insulating layer and the second conductive layer.
  • the first insulating layer preferably has an oxide or an oxynitride.
  • the second insulating layer and the third insulating layer preferably have a nitride or a oxynitride, respectively.
  • the fourth insulating layer is preferably located between the second insulating layer and the first conductive layer.
  • the fourth insulating layer preferably has a region having more hydrogen than the second insulating layer.
  • the fifth insulating layer is preferably located between the third insulating layer and the second conductive layer.
  • the fifth insulating layer preferably has a region having more hydrogen than the third insulating layer.
  • One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, and a first insulating layer.
  • the first transistor has a first conductive layer, a second conductive layer having a region overlapping with the first conductive layer via the first insulating layer, and a first semiconductor layer.
  • the second conductive layer has a first opening in a region overlapping with the first conductive layer.
  • the first insulating layer has a second opening reaching the first conductive layer in a region overlapping with the first opening.
  • the first semiconductor layer contacts the top surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer in the first opening and the second opening.
  • the second transistor has a third conductive layer on the first insulating layer, a second semiconductor layer, and a second insulating layer located between the third conductive layer and the second semiconductor layer.
  • the second insulating layer contacts the top surface and the side surface of the third conductive layer.
  • the diffusion coefficient of oxygen in the first insulating layer is greater than the diffusion coefficient of oxygen in the second insulating layer.
  • the oxygen diffusion coefficient is preferably calculated by thermal desorption spectrometry or secondary ion mass spectrometry.
  • One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, and a first insulating layer.
  • the first transistor has a first conductive layer, a second conductive layer having a region overlapping with the first conductive layer via the first insulating layer, and a first semiconductor layer.
  • the second conductive layer has a first opening in a region overlapping with the first conductive layer.
  • the first insulating layer has a second opening reaching the first conductive layer in a region overlapping with the first opening.
  • the first semiconductor layer contacts the top surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer in the first opening and the second opening.
  • the second transistor has a third conductive layer on the first insulating layer, a second semiconductor layer, and a second insulating layer located between the third conductive layer and the second semiconductor layer.
  • the second insulating layer contacts the top surface and the side surface of the third conductive layer.
  • the etching rate of the first insulating layer in one etchant is faster than the etching rate of the second insulating layer.
  • the etchant preferably contains hydrofluoric acid.
  • the first semiconductor layer and the second semiconductor layer each contain a metal oxide.
  • the second conductive layer and the third conductive layer have different materials.
  • the second conductive layer and the third conductive layer have the same material.
  • the semiconductor device it is preferable to have a third insulating layer and a fourth insulating layer.
  • the third insulating layer is preferably located between the first insulating layer and the first conductive layer.
  • the fourth insulating layer is preferably located between the first insulating layer and the second conductive layer.
  • the fourth insulating layer is preferably located between the first insulating layer and the third conductive layer.
  • the first insulating layer preferably has an oxide or an oxynitride.
  • the third insulating layer and the fourth insulating layer preferably have a nitride or a oxynitride, respectively.
  • the fifth insulating layer is preferably located between the third insulating layer and the first conductive layer.
  • the fifth insulating layer preferably has a region having more hydrogen than the third insulating layer.
  • the sixth insulating layer is preferably located between the fourth insulating layer and the second conductive layer.
  • the sixth insulating layer is preferably located between the fourth insulating layer and the third conductive layer.
  • the sixth insulating layer preferably has a region having more hydrogen than the fourth insulating layer.
  • One embodiment of the present invention can provide a transistor with a small size. Or a transistor with a short channel length. Or a transistor with a large on-state current. Or a transistor with good electrical characteristics. Or a semiconductor device with a small occupation area can be provided. Or a semiconductor device with low wiring resistance can be provided. Or a semiconductor device or display device with low power consumption can be provided. Or a highly reliable transistor, semiconductor device, or display device can be provided. Or a display device with high definition can be provided. Or a method for manufacturing a semiconductor device or display device with high productivity can be provided. Or a novel transistor, semiconductor device, display device, or a manufacturing method thereof can be provided.
  • Fig. 1A is a top view illustrating an example of a semiconductor device
  • Fig. 1B and Fig. 1C are cross-sectional views illustrating the example of the semiconductor device
  • 2A and 2B are perspective views showing an example of a semiconductor device.
  • FIG. 3 is a cross-sectional view showing an example of a semiconductor device.
  • 4A and 4B are a top view and a cross-sectional view illustrating an example of a semiconductor device.
  • Fig. 5A is a top view showing an example of a semiconductor device
  • Figs. 5B and 5C are cross-sectional views showing the example of the semiconductor device.
  • 6A and 6B are cross-sectional views showing an example of a semiconductor device.
  • FIG. 7A and 7B are a top view and a cross-sectional view illustrating an example of a semiconductor device.
  • Fig. 8A is a top view illustrating an example of a semiconductor device
  • Fig. 8B and Fig. 8C are cross-sectional views illustrating the example of the semiconductor device.
  • Fig. 9A is a top view illustrating an example of a semiconductor device
  • Fig. 9B and Fig. 9C are cross-sectional views illustrating the example of the semiconductor device.
  • 10A and 10B are cross-sectional views showing an example of a semiconductor device.
  • 11A to 11C are cross-sectional views showing an example of a semiconductor device.
  • 12A and 12B are cross-sectional views showing an example of a semiconductor device.
  • FIG. 13A is a top view illustrating an example of a semiconductor device
  • Fig. 13B and Fig. 13C are cross-sectional views illustrating the example of the semiconductor device.
  • 14A and 14B are equivalent circuit diagrams of the semiconductor device
  • Fig. 14C is a top view showing an example of the semiconductor device.
  • FIG. 15 is a cross-sectional view showing an example of a semiconductor device.
  • FIG. 16 is a perspective view showing an example of a semiconductor device.
  • 17A to 17D are perspective views showing an example of a semiconductor device.
  • 18A and 18B are equivalent circuit diagrams of a semiconductor device
  • Fig. 18C is a top view showing an example of the semiconductor device.
  • FIG. 19 is a cross-sectional view showing an example of a semiconductor device.
  • FIG. 19 is a cross-sectional view showing an example of a semiconductor device.
  • 20 is a perspective view showing an example of a semiconductor device.
  • 21A to 21D are perspective views showing an example of a semiconductor device.
  • 22A to 22D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 23A to 23C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 24A to 24C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 25A to 25C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 26A and 26B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 27A and 27B are perspective and block diagrams illustrating an example of a display device. Fig.
  • FIG. 28A is a circuit diagram of a latch circuit
  • Fig. 28B is a circuit diagram of an inverter circuit
  • 29A and 29B are circuit diagrams of a pixel circuit
  • Fig. 29C is a cross-sectional view showing an example of a pixel circuit
  • FIG. 30 is a circuit diagram of a pixel circuit.
  • FIG. 31 is a top view showing an example of a pixel layout.
  • FIG. 32 is a top view showing an example of a pixel layout.
  • FIG. 33 is a top view showing an example of a pixel layout.
  • FIG. 34 is a cross-sectional view showing an example of a pixel layout.
  • 35A and 35B are cross-sectional views showing an example of a pixel layout.
  • 36A to 36C are top views showing an example of a pixel layout.
  • 37A to 37C are top views showing an example of a pixel layout.
  • FIG. 38 is a top view showing an example of a pixel layout.
  • FIG. 39 is a top view showing an example of a pixel layout.
  • 40A and 40B are top views showing an example of a pixel layout.
  • 41A and 41B are top views showing an example of a pixel layout.
  • 42A and 42B are top views showing an example of a pixel layout.
  • 43A and 43B are cross-sectional views showing an example of a display device.
  • FIG. 44 is a cross-sectional view showing an example of a display device.
  • 45A to 45C are cross-sectional views showing an example of a display device.
  • FIG. 46A and 46B are cross-sectional views showing an example of a display device.
  • FIG. 47 is a cross-sectional view showing an example of a display device.
  • FIG. 48 is a cross-sectional view showing an example of a display device.
  • FIG. 49 is a cross-sectional view showing an example of a display device.
  • 50A and 50B are cross-sectional views showing an example of a display device.
  • 51A to 51F are cross-sectional views showing an example of a method for manufacturing a display device.
  • 52A to 52D are diagrams showing an example of an electronic device.
  • 53A to 53F are diagrams showing an example of an electronic device.
  • 54A to 54G are diagrams showing an example of an electronic device.
  • FIG. 55 is an SEM image of a transistor according to an example.
  • FIG. 56A and 56B are STEM images of a transistor according to an example.
  • FIG. 57 is a diagram showing the Id-Vg characteristics of a transistor according to an example.
  • 58A and 58B are diagrams showing electrical characteristics of a transistor according to an example.
  • FIG. 59 is a diagram showing electrical characteristics of a transistor according to an example.
  • FIG. 60 is a diagram showing electrical characteristics of a transistor according to an example.
  • FIG. 61 is a diagram showing the reliability of the transistor according to the example.
  • 62A and 62B are photographs showing the display state of an OLED panel according to an embodiment of the present invention.
  • FIG. 63 is a diagram showing the I-V characteristics of a sample according to an example.
  • FIG. 63 is a diagram showing the I-V characteristics of a sample according to an example.
  • FIG. 64 is a diagram showing the sheet resistance and carrier concentration of the sample according to the example.
  • FIG. 65 is a diagram showing the Id-Vg characteristics of a transistor according to an example.
  • FIG. 66 is a diagram showing electrical characteristics of a transistor according to an example.
  • 67A and 67B are diagrams showing electrical characteristics and Id-Vg characteristics of a transistor according to an example;
  • FIG. 68 is a diagram showing the Id-Vg characteristics of a transistor according to an example.
  • 69A and 69B are diagrams showing electrical characteristics of a transistor according to an example.
  • FIG. 70 is a diagram showing electrical characteristics of a transistor according to an example.
  • 71A and 71B are diagrams showing the Id-Vg characteristics and the electrical characteristics of a transistor according to an example;
  • FIG. 72 is a diagram showing the reliability of the transistor according to the example.
  • FIG. 73 is a photograph of the display state of an OLED panel according to an embodiment.
  • 74A to 74C are cross-sectional views showing the structure of a sample according to an embodiment.
  • 75A and 75B are diagrams showing a cross-sectional TEM image and crystal orientation according to an example.
  • 76A and 76B are diagrams showing a cross-sectional TEM image and crystal orientation according to an example.
  • 77A and 77B are diagrams showing the Id-Vg characteristics of a transistor according to an example.
  • FIG. 78 is a diagram illustrating a method for evaluating the off-state current of a transistor according to an example.
  • FIG. 80 is a diagram showing the Id-Vg characteristics of a transistor according to an example.
  • 81A and 81B are TDS spectra according to an embodiment.
  • FIG. 82 is a diagram showing the diffusion coefficient of oxygen according to an example.
  • 83A and 83B are diagrams showing the measurement results of TDS according to the embodiment.
  • 84A and 84B are diagrams showing the Id-Vg characteristics of a transistor according to an example.
  • 85A and 85B are diagrams showing the Id-Vg characteristics of a transistor according to an example.
  • 86A and 86B are diagrams showing electrical characteristics of a transistor according to an example.
  • FIG. 87A to 87F are TDS spectra according to an embodiment.
  • FIG. 88 shows a TDS spectrum according to the embodiment.
  • FIG. 89 is a diagram showing the measurement results of the TDS according to the embodiment.
  • FIG. 90 is a diagram showing electrical characteristics of a transistor according to an example.
  • 91A and 91B are diagrams showing the reliability of a transistor according to an embodiment.
  • FIG. 92 is a diagram showing the drain breakdown voltage of a transistor according to an example.
  • an identification reference number such as “_1”, “[n]”, “[m,n]” may be added to the reference number.
  • an identification reference number such as “_1”, “[n]”, “[m,n]” is added to a reference number in a drawing, etc., when it is not necessary to distinguish between them in this specification, the identification reference number may not be added.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., process order or stacking order). Furthermore, an ordinal number attached to a component in one place in this specification may not match an ordinal number attached to the same component in another place in this specification or in the claims.
  • film and “layer” can be interchanged depending on the circumstances.
  • conductive layer can be changed to the term “conductive film.”
  • insulating film can be changed to the term “insulating layer.”
  • a transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conduction.
  • transistor includes IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).
  • source and drain may be interchanged when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification and the like, the terms “source” and “drain” may be used interchangeably. Note that the source and drain of a transistor may be appropriately referred to as the source terminal and drain terminal, or the source electrode and drain electrode, depending on the situation.
  • Gate and backgate can be used interchangeably. For this reason, in this specification and the like, the terms “gate” and “backgate” can be used interchangeably. Note that the names of the gate and backgate of a transistor can be appropriately changed depending on the situation, such as gate electrode and backgate electrode.
  • electrically connected includes cases where the connection is made via "something that has some kind of electrical action.”
  • something that has some kind of electrical action is not particularly limited as long as it allows the transmission and reception of electrical signals between the connected objects.
  • something that has some kind of electrical action includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.
  • off-state current refers to the leakage current between the source and drain when a transistor is in the off state (also called non-conducting state or cut-off state).
  • the off state refers to a state in which the voltage between the gate and source (also written as Vgs or Vg) is lower than the threshold voltage (also written as Vth) in an n-channel transistor, and a state in which the voltage is higher than the threshold voltage in a p-channel transistor.
  • top surface shapes roughly match means that at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where parts of the mask pattern are the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer, in which case it may also be said that “top surface shapes roughly match.” Furthermore, when the top surface shapes match or roughly match, it can also be said that the edges are aligned or roughly aligned.
  • a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.
  • a device manufactured using a metal mask or an FMM may be referred to as a device with an MM (metal mask) structure.
  • a device manufactured without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.
  • devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of fineness resulting from the alignment accuracy of the metal mask.
  • devices with an MML structure can eliminate the need for equipment related to the manufacturing of metal masks and the process of cleaning the metal masks.
  • devices with an MML structure are suitable for mass production because they make it possible to keep manufacturing costs low.
  • SBS Side By Side
  • the SBS structure allows the materials and configuration to be optimized for each light-emitting element, which increases the freedom to select materials and configurations and makes it easier to improve brightness and reliability.
  • holes or electrons may be referred to as "carriers".
  • the hole injection layer or electron injection layer may be referred to as the "carrier injection layer”
  • the hole transport layer or electron transport layer may be referred to as the “carrier transport layer”
  • the hole block layer or electron block layer may be referred to as the "carrier block layer”.
  • the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other due to their cross-sectional shapes or characteristics.
  • one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.
  • the light-emitting element has an EL layer between a pair of electrodes.
  • the EL layer has at least a light-emitting layer.
  • layers also called functional layers
  • the EL layer has include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer).
  • the light-receiving element also called a light-receiving device
  • one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.
  • the sacrificial layer (which may also be referred to as a mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that make up the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.
  • step discontinuity refers to the phenomenon in which a layer, film, or electrode is separated due to the shape of the surface on which it is formed (e.g., a step, etc.).
  • One aspect of the present invention is a semiconductor device having a transistor and a first insulating layer.
  • the transistor has a first conductive layer, a second conductive layer having a region overlapping with the first conductive layer via the first insulating layer, a semiconductor layer, a gate insulating layer, and a gate electrode.
  • the second conductive layer has a first opening in a region overlapping with the first conductive layer.
  • the first insulating layer has a second opening that reaches the first conductive layer in a region overlapping with the first opening.
  • the semiconductor layer is in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer in the first opening and the second opening.
  • a gate insulating layer is provided on the semiconductor layer, and a gate electrode is provided on the gate insulating layer.
  • the first conductive layer functions as one of a source electrode and a drain electrode
  • the second conductive layer functions as the other. Since the source electrode, the layer having a channel formation region, and the drain electrode can be provided in an overlapping manner, the occupied area can be reduced.
  • the region of the semiconductor layer in contact with the first insulating layer functions as a channel formation region. This allows the channel length of the transistor to be made smaller than the limit resolution of the exposure device, resulting in a transistor with a large on-state current.
  • the semiconductor layer preferably contains a metal oxide.
  • the first insulating layer preferably uses a material that releases oxygen. This allows oxygen to be supplied from the first insulating layer to the semiconductor layer (particularly, the channel formation region), and reduces oxygen vacancies ( VO ) in the semiconductor layer.
  • the amount of oxygen supplied from the first insulating layer to the semiconductor layer is larger.
  • the first insulating layer has a large oxygen diffusion coefficient.
  • the first insulating layer has an oxygen diffusion coefficient of 5 ⁇ 10 ⁇ 12 cm 2 /sec or more at 350° C. This increases the diffusion rate of oxygen in the first insulating layer, and oxygen can be effectively supplied to the semiconductor layer. Therefore, even in a transistor having a short channel length, it is possible to achieve both good electrical characteristics and high reliability.
  • FIG 1A A top view (also referred to as a plan view) of a semiconductor device 10 is shown in FIG 1A.
  • FIG 1B A cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG 1A is shown in FIG 1B, and a cross-sectional view of a cut surface taken along dashed line B1-B2 in FIG 1C is shown in FIG 1A.
  • FIG 1A Note that some of the components of the semiconductor device 10 (such as an insulating layer) are omitted in FIG 1A. As with FIG 1A, some of the components are omitted in the top views of the semiconductor device in the following drawings.
  • FIGS. 2A and 2B show perspective views of the semiconductor device 10.
  • FIG. 2B shows some of the components shown in FIG. 2A shifted in the normal direction of the surface of the substrate 102.
  • the semiconductor device 10 includes a transistor 100, a transistor 200, a capacitor 150, and an insulating layer 110.
  • the transistor 100, the transistor 200, and the capacitor 150 are provided on a substrate 102.
  • the transistor 100 and the transistor 200 have different structures.
  • the transistor 100, the transistor 200, and the capacitor 150 can be formed by sharing some of the processes.
  • the transistor 100 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b.
  • the conductive layer 104 functions as a gate electrode (also referred to as a first gate electrode), and a part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer).
  • the conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other.
  • Each layer constituting the transistor 100 may have a single-layer structure or a stacked structure. Note that in FIG. 2A, the insulating layer 110 and the insulating layer 106 are shown through the transparent layer, and their contours are indicated by dashed lines.
  • a conductive layer 112a is provided on the substrate 102, and an insulating layer 110 is provided on the conductive layer 112a.
  • the insulating layer 110 is provided so as to cover the upper and side surfaces of the conductive layer 112a.
  • the insulating layer 110 has an opening 141 that reaches the conductive layer 112a. It can also be said that the conductive layer 112a is exposed in the opening 141.
  • a conductive layer 112b is provided on the insulating layer 110.
  • the conductive layer 112b has an area that overlaps with the conductive layer 112a via the insulating layer 110.
  • the conductive layer 112b has an opening 143 in the area that overlaps with the conductive layer 112a.
  • the opening 143 is provided in the area that overlaps with the opening 141.
  • the semiconductor layer 108 is provided so as to cover the openings 141 and 143.
  • the semiconductor layer 108 has a region in contact with the upper and side surfaces of the conductive layer 112b, the side surfaces of the insulating layer 110, and the upper surface of the conductive layer 112a.
  • the semiconductor layer 108 is electrically connected to the conductive layer 112a through the openings 141 and 143.
  • the semiconductor layer 108 has a shape that conforms to the shapes of the upper and side surfaces of the conductive layer 112b, the side surfaces of the insulating layer 110, and the upper surface of the conductive layer 112a.
  • the semiconductor layer 108 has a region that overlaps with the conductive layer 112a through the insulating layer 110. It can also be said that the insulating layer 110 has a region sandwiched between the conductive layer 112a and the semiconductor layer 108.
  • the region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source region and the drain region, and the region in contact with the conductive layer 112b functions as the other.
  • a channel formation region is provided between the source region and the drain region.
  • the insulating layer 106 is provided so as to cover the openings 141 and 143.
  • the insulating layer 106 is provided on the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110.
  • the insulating layer 106 has an area that contacts the upper surface and side surfaces of the semiconductor layer 108, the upper surface and side surfaces of the conductive layer 112b, and the upper surface of the insulating layer 110.
  • the insulating layer 106 has a shape that follows the shapes of the upper surface and side surfaces of the semiconductor layer 108, the upper surface and side surfaces of the conductive layer 112b, and the upper surface of the insulating layer 110.
  • the conductive layer 104 is provided on the insulating layer 106 and has a region in contact with the upper surface of the insulating layer 106.
  • the conductive layer 104 has a region that overlaps with the semiconductor layer 108 via the insulating layer 106.
  • the conductive layer 104 has a shape that follows the shape of the upper surface of the insulating layer 106.
  • the source electrode and the drain electrode are located at different heights relative to the surface of the substrate 102 on which they are formed, and the drain current flows perpendicularly or approximately perpendicularly to the surface of the substrate 102. It can also be said that the drain current flows vertically or approximately vertically in the transistor 100. Therefore, the transistor that is one embodiment of the present invention can be called a vertical channel transistor, a vertical transistor, or a VFET (Vertical Field Effect Transistor).
  • VFET Very Field Effect Transistor
  • the channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 (specifically, the insulating layer 110b) provided between the conductive layer 112a and the conductive layer 112b. Therefore, a transistor having a channel length shorter than the limit resolution of an exposure device used to manufacture the transistor can be manufactured with high precision.
  • the characteristic variation between multiple transistors 100 is also reduced. This makes it possible to stabilize the operation of a semiconductor device including the transistor 100 and to increase its reliability.
  • the reduced characteristic variation increases the degree of freedom in circuit design and allows the operating voltage of the semiconductor device to be reduced. This allows the power consumption of the semiconductor device to be reduced.
  • the transistor 100 can have a source electrode, a layer having a channel formation region, and a drain electrode stacked on top of each other, so the area it occupies can be significantly reduced compared to a so-called planar type transistor in which the layer having the channel formation region is arranged in a planar shape.
  • the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each function as wiring, and the transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit having the transistor 100 and the wiring, the area occupied by the transistor 100 and the wiring can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be obtained.
  • the transistor 200 includes a conductive layer 204, a conductive layer 212a, a conductive layer 212b, an insulating layer 106, a semiconductor layer 208, an insulating layer 120, and a conductive layer 202.
  • the conductive layer 204 functions as a gate electrode (also referred to as a first gate electrode), and a part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer).
  • the conductive layer 202 functions as a back gate electrode (also referred to as a second gate electrode), and a part of the insulating layer 120 functions as a back gate insulating layer (also referred to as a second gate insulating layer).
  • the conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other.
  • Each layer constituting the transistor 200 may have a single layer structure or a stacked structure. Note that the transistor 200 does not necessarily have the conductive layer 202. Note that the insulating layer 120 is omitted in FIG. 2A.
  • the entire region of the semiconductor layer 208 that overlaps with the gate electrode via the gate insulating layer between the source electrode and drain electrode functions as a channel formation region.
  • the semiconductor layer 208 has a pair of regions 208L that sandwich the channel formation region, and a pair of regions 208D on the outside of the pair.
  • Region 208L and region 208D are regions containing impurity elements.
  • the impurity elements may be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases.
  • noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of boron, phosphorus, aluminum, magnesium, and silicon as the impurity elements.
  • an impurity element is supplied (also referred to as added or injected) to the semiconductor layer 208.
  • a region 208D is formed in a region of the semiconductor layer 208 that does not overlap with any of the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the insulating layer 106
  • a region 208L is formed in a region that does not overlap with any of the conductive layer 204, the conductive layer 212a, and the conductive layer 212b and overlaps with the insulating layer 106.
  • the region of the semiconductor layer 208 that contacts the conductive layer 212a and the region 208D adjacent to this region function as one of the source region and the drain region.
  • the region of the semiconductor layer 208 that contacts the conductive layer 212b and the region 208D adjacent to this region function as the other of the source region and the drain region.
  • a conductive layer 202 is provided on the insulating layer 110, and an insulating layer 120 is provided on the conductive layer 202.
  • the insulating layer 120 is provided so as to cover the upper and side surfaces of the conductive layer 202.
  • the insulating layer 120 has a portion that protrudes beyond the end of the conductive layer 202. The end of the insulating layer 120 contacts the upper surface of the insulating layer 110.
  • the semiconductor layer 208 is provided on the insulating layer 120.
  • the semiconductor layer 208 has a region that overlaps with the conductive layer 202 via the insulating layer 120.
  • the same material as the semiconductor layer 108 can be used for the semiconductor layer 208.
  • the semiconductor layer 208 can be formed in the same process as the semiconductor layer 108.
  • the semiconductor layer 108 and the semiconductor layer 208 can be formed by forming a film that will become the semiconductor layer 108 and the semiconductor layer 208 and processing the film.
  • An insulating layer 106 is provided on the semiconductor layer 208.
  • a part of the insulating layer 106 functions as a gate insulating layer for the transistor 100, and another part functions as a gate insulating layer for the transistor 200.
  • the insulating layer 106 has an opening 147a and an opening 147b in the area overlapping with the semiconductor layer 208.
  • the conductive layer 204, the conductive layer 212a, and the conductive layer 212b are provided on the insulating layer 106.
  • the conductive layer 204 has a region that overlaps with the semiconductor layer 208 through the insulating layer 106.
  • the conductive layer 204 also has a region that overlaps with the conductive layer 202 through the semiconductor layer 208.
  • the conductive layer 212a and the conductive layer 212b are provided so as to cover a part of the opening 147a and the opening 147b.
  • the conductive layer 212a is electrically connected to the semiconductor layer 208 through the opening 147a
  • the conductive layer 212b is electrically connected to the semiconductor layer 208 through the opening 147b.
  • the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be made of the same material as the conductive layer 104.
  • the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed in the same process as the conductive layer 104.
  • a film that will become the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed by forming the film and processing the film to form the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b.
  • Transistor 200 is a planar type transistor in which semiconductor layer 208 is arranged in a plane. It is also a so-called top-gate type transistor that has a gate electrode above semiconductor layer 208. For example, by supplying impurity elements to semiconductor layer 208 using conductive layer 204, which functions as a gate electrode, as a mask, it is possible to form regions 208D that function as source and drain regions in a self-aligned manner. Transistor 200 can be said to be a TGSA (Top Gate Self-Aligned) type transistor.
  • TGSA Top Gate Self-Aligned
  • the channel length of the transistor 200 can be controlled by the length of the conductive layer 204. Therefore, the channel length of the transistor 200 is equal to or greater than the resolution limit of an exposure device used to fabricate the transistor. In other words, the channel length of the transistor 200 can be made longer than the channel length of the transistor 100. By making the channel length longer, a transistor with high saturation properties can be obtained.
  • high saturation may be used to refer to a small change in current in the saturation region in the Id-Vd characteristics of a transistor.
  • the transistor 100 with a short channel length and the transistor 200 with a long channel length can be formed on the same substrate by sharing some of the processes.
  • a high-performance semiconductor device can be obtained by applying the transistor 100 to a transistor that requires a large on-state current and the transistor 200 to a transistor that requires high saturation.
  • a semiconductor device of one embodiment of the present invention when a semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained.
  • a semiconductor device of one embodiment of the present invention when a semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.
  • the capacitor 150 has a conductive layer 112b and a conductive layer 202 that function as a pair of electrodes, and an insulating layer 120.
  • the conductive layer 112b functions as the other of the source electrode and drain electrode of the transistor 100 and functions as one of the pair of electrodes of the capacitor 150.
  • the conductive layer 202 functions as the back gate electrode of the transistor 200 and functions as the other of the pair of electrodes of the capacitor 150.
  • the region of the insulating layer 120 sandwiched between the conductive layer 112b and the conductive layer 202 functions as a dielectric of the capacitor 150.
  • the capacitor 150 is composed of the conductive layer 112b, the conductive layer 202, and the insulating layer 120, but the configuration of the capacitor 150 is not particularly limited. Furthermore, the semiconductor device 10 does not necessarily have to have the capacitor 150. Note that when the capacitor 150 composed of the conductive layer 112b, the conductive layer 202, and the insulating layer 120 is not provided, the conductive layer 112b and the conductive layer 202 may be formed in the same process.
  • the other of the source electrode and drain electrode of the transistor 100 is electrically connected to one of the pair of electrodes of the capacitor 150, and one of the source electrode and drain electrode of the transistor 200 is electrically connected to the other of the pair of electrodes of the capacitor 150, but the electrical connection relationship between the transistor 100, the transistor 200, and the capacitor 150 is not particularly limited.
  • An insulating layer 195 is provided to cover the transistor 100, the transistor 200, and the capacitor 150.
  • the insulating layer 195 functions as a protective layer for the transistor 100, the transistor 200, and the capacitor 150. Note that the insulating layer 195 is omitted in the perspective views shown in Figures 2A and 2B.
  • transistor 100 and transistor 200 The detailed configuration of transistor 100 and transistor 200 will be described.
  • the semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited.
  • a semiconductor made of a single element or a compound semiconductor can be used.
  • semiconductors made of a single element include silicon and germanium.
  • compound semiconductors include gallium arsenide and silicon germanium.
  • Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: oxide semiconductor). Note that these semiconductor materials may contain impurities as dopants.
  • the crystallinity of the semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited, and any of an amorphous semiconductor, a single crystalline semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • the use of a single crystalline semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.
  • the semiconductor layer 108 and the semiconductor layer 208 can each be made of silicon.
  • silicon examples include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • polycrystalline silicon examples include low temperature polysilicon (LTPS).
  • Transistors using amorphous silicon in the channel formation region can be formed on a large glass substrate and can be manufactured at low cost. Transistors using polycrystalline silicon in the channel formation region have high field effect mobility and can operate at high speed. Furthermore, transistors using microcrystalline silicon in the channel formation region have higher field effect mobility and can operate at high speed than transistors using amorphous silicon.
  • the semiconductor layer 108 and the semiconductor layer 208 each have a metal oxide (also called an oxide semiconductor) that exhibits semiconductor properties.
  • a metal oxide also called an oxide semiconductor
  • the band gap of the metal oxide used in the semiconductor layer 108 and the semiconductor layer 208 is preferably 2.0 eV or more, and more preferably 2.5 eV or more.
  • OS transistors have extremely high field-effect mobility compared to transistors using amorphous silicon.
  • OS transistors have an extremely small off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time.
  • the use of OS transistors can reduce the power consumption of a semiconductor device.
  • the insulating layer 110 preferably has one or more inorganic insulating films.
  • materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides.
  • oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate.
  • nitrides include silicon nitride and aluminum nitride.
  • Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride.
  • Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen.
  • An oxynitride refers to a material whose composition contains more nitrogen than oxygen.
  • the insulating layer 110 has a region in contact with the semiconductor layer 108.
  • a metal oxide is used for the semiconductor layer 108
  • the part of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 contains oxygen.
  • One or more of an oxide and an oxynitride can be suitably used for the part of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108.
  • the insulating layer 110 preferably has a laminated structure.
  • FIG. 1B and other figures show an example in which the insulating layer 110 has an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b.
  • FIG. 3 shows an enlarged view of the transistor 100 shown in FIG. 1B.
  • the region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region.
  • the insulating layer 110b preferably contains oxygen, and preferably uses one or more of the above-mentioned oxides and oxynitrides. Specifically, one or both of silicon oxide and silicon oxynitride can be preferably used for the insulating layer 110b.
  • a film that releases oxygen when heated for the insulating layer 110b It is more preferable to use a film that releases oxygen when heated for the insulating layer 110b.
  • the insulating layer 110b releases oxygen, so that oxygen can be supplied to the semiconductor layer 108.
  • oxygen vacancies (V O ) can be repaired and reduced. Therefore, a transistor having good electrical characteristics and high reliability can be obtained.
  • oxygen can be supplied to the insulating layer 110b by performing heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere.
  • oxygen may be supplied to the insulating layer 110b by forming an oxide film in an oxygen-containing atmosphere on the upper surface of the insulating layer 110b by a sputtering method. The oxide film may then be removed. Note that a method for supplying oxygen to the insulating layer 110b will be described in embodiment 2.
  • the insulating layer 110b is preferably formed by a deposition method such as sputtering or plasma enhanced chemical vapor deposition (PECVD) (also referred to as plasma CVD).
  • PECVD plasma enhanced chemical vapor deposition
  • a film with an extremely low hydrogen content can be obtained. This can prevent hydrogen from being supplied to the channel formation region, and stabilize the electrical characteristics of the transistor 100.
  • the insulating layer 110b it is preferable that substances (e.g., atoms, molecules, and ions) diffuse easily. It can also be said that it is preferable that the diffusion coefficient of the substance in the insulating layer 110b is large. In particular, it is preferable that oxygen diffuses easily in the insulating layer 110b. In other words, it is preferable that the diffusion coefficient of oxygen in the insulating layer 110b is large. The oxygen contained in the insulating layer 110b diffuses in the insulating layer 110b and is supplied to the semiconductor layer 108 through the interface between the insulating layer 110b and the semiconductor layer 108. In FIG.
  • substances e.g., atoms, molecules, and ions
  • the arrows show a schematic view of the state in which the oxygen contained in the insulating layer 110b diffuses to the interface between the insulating layer 110b and the semiconductor layer 108.
  • the oxygen diffusion coefficient of the insulating layer 110b at 350° C. is preferably 5 ⁇ 10 ⁇ 12 cm 2 /sec or more, more preferably 1 ⁇ 10 ⁇ 11 cm 2 /sec or more, further preferably 5 ⁇ 10 ⁇ 11 cm 2 /sec or more, and further preferably 1 ⁇ 10 ⁇ 10 cm 2 /sec or more.
  • the diffusion coefficient can be calculated by, for example, thermal desorption spectrometry (TDS). Alternatively, secondary ion mass spectrometry (SIMS) may be used.
  • the formation of the insulating layer 110b will now be described in detail.
  • an example of forming silicon oxynitride using the PECVD method will be given.
  • a deposition gas containing silicon and a gas containing an oxidizing gas can be used as the source gas of the insulating layer 110b.
  • the deposition gas containing silicon for example, one or more of silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), silane fluoride (SiF 4 ), and TEOS (tetraethoxysilane, Si(OC 2 H 5 ) 4 ) can be used.
  • a gas containing oxygen can be preferably used as the oxidizing gas.
  • the oxidizing gas for example, one or more of oxygen (O 2 ), ozone (O 3 ), dinitrogen monoxide (N 2 O), nitric oxide (NO), and nitrogen dioxide (NO 2 ) can be used.
  • oxygen (O 2 ) oxygen (O 2 )
  • ozone (O 3 ) dinitrogen monoxide (N 2 O)
  • nitric oxide (NO) nitrogen dioxide
  • NO 2 nitrogen dioxide
  • silane (SiH 4 ) it is preferable to use dinitrogen monoxide (N 2 O) as the oxidizing gas, since particles can be reduced compared to the case of using oxygen (O 2 ).
  • oxygen (O 2 ) can be suitably used as the oxidizing gas.
  • the plasma density is lowered relative to the flow rate of the deposition gas, that is, the ratio of the plasma density to the flow rate of the deposition gas is lowered, thereby making it possible to obtain an insulating layer with a large diffusion coefficient.
  • the power of the RF power source (hereinafter also referred to as RF power) can be lowered to lower the plasma density.
  • the diffusion coefficient of oxygen in the insulating layer 110b becomes large, and the oxygen contained in the insulating layer 110b can be efficiently supplied to the semiconductor layer 108 (particularly the channel formation region).
  • a gas containing hydrogen e.g., SiH 4
  • the F ratio is too small, the amount of hydrogen contained in the insulating layer 110b may become large. If the insulating layer 110b contains a large amount of hydrogen, there is a risk that the amount of hydrogen-containing impurities (eg, water, hydrogen, and ammonia) released from the insulating layer 110b will be large.
  • the F ratio is 12 or less, 10 or less, 9 or less, 8 or less, 7 or less, 6 or less, or 5 or less, and preferably 2 or more, or 3 or more.
  • the F ratio is 4.
  • sccm indicates the flow rate at 1 atmosphere and 0°C (273.15K).
  • the F ratio is shown when the gas flow rate is expressed in units of sccm and the RF power in W, but if a different unit is used, the F ratio can be calculated by converting the unit. For example, if the flow rate is 0.3 SLM (Standard Liter Per Minute), the F ratio can be calculated by converting it to 300 sccm.
  • oxygen vacancies ( VO ) and VOH in the channel formation region have a greater effect on the electrical characteristics than in a transistor having a long channel length. Therefore, it is very important to efficiently supply oxygen from the insulating layer 110b to the semiconductor layer 108 (particularly the channel formation region) and to reduce the amount of impurities released from the insulating layer 110b.
  • the F ratio in the formation of the insulating layer 110b within the above range, a transistor can be obtained that exhibits good electrical characteristics and is highly reliable.
  • the rate-limiting process in the gas release includes the diffusion rate-limiting process in the film and the reaction rate-limiting process on the film surface.
  • a film in which a substance is easily diffused is not likely to be diffusion rate-limiting, so the temperature at which gas starts to be released when heat is applied (hereinafter also referred to as the release temperature) is low.
  • the release temperature the temperature at which gas starts to be released when heat is applied
  • the gas release temperature is high.
  • the gas release temperature is low in the TDS of the insulating layer 110b.
  • oxygen is supplied from the insulating layer 110b to the semiconductor layer 108 during the manufacturing process of the semiconductor device 10, and the amount of oxygen that can be released from the insulating layer 110b in the semiconductor device 10 after the manufacturing process may be small. Therefore, when performing TDS of the semiconductor device 10, the amount of released oxygen may be small.
  • a film in which oxygen is easily diffused also easily diffuses substances other than oxygen, if the release temperature of gas released other than oxygen is low, it is considered to be a film in which oxygen is easily diffused.
  • the rate of temperature rise of the sample surface in TDS is about 14° C./min.
  • the rate of temperature rise of the stage on which the sample is placed can be, for example, about 32° C./min.
  • a method for calculating the emission temperature in TDS is described below.
  • background processing is a method in which the minimum value of the detection intensity in the entire temperature range of the measurement is subtracted from the actual measurement value as the background value.
  • the etching rate for the etchant when the F ratio is high during the formation of the film, the etching rate for the etchant is slow, and when the F ratio is low, the etching rate for the etchant is fast, so the etching rate can be used as an index of the ease of diffusion.
  • an etchant containing hydrofluoric acid can be used.
  • hydrofluoric acid and BHF Buffered Hydrofluoric Acid
  • BHF is an etchant containing hydrofluoric acid and a buffer (e.g., ammonium fluoride (NH 4 F)).
  • a buffer e.g., ammonium fluoride (NH 4 F)
  • an etchant containing these and a surfactant may be used.
  • the etching rate of the insulating layer 110b for 0.5 wt % hydrofluoric acid at 25° C. is 8 nm/min or more, 9 nm/min or more, 10 nm/min or more, 11 nm/min or more, or 12 nm/min or more, and is preferably 15 nm/min or less.
  • the etching rate can be calculated by dividing the difference between the thickness of the target film before etching and the thickness of the target film after etching by the time for which etching is performed.
  • the transistor with a large on-current can be obtained.
  • a material with high conductivity oxygen vacancies (V O ) are easily formed, and when the oxygen vacancies (V O ) in the channel formation region increase, the threshold voltage of the transistor shifts, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may become large.
  • cutoff current may become large due to the shift of the threshold voltage to the negative side.
  • oxygen is supplied to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, that is, the channel formation region, and the oxygen vacancies (V O ) in the channel formation region can be reduced.
  • the shift of the threshold voltage is suppressed, and a transistor with both a small cutoff current and a large on-current can be obtained. Therefore, a semiconductor device with both low power consumption and high performance can be obtained.
  • the region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source and drain regions of the transistor 100, and the region in contact with the conductive layer 112b functions as the other.
  • the source and drain regions are regions with lower electrical resistance than the channel formation region.
  • the source and drain regions can also be said to be regions with a higher carrier concentration and a higher oxygen defect density than the channel formation region.
  • the insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a.
  • the insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b. It is preferable that the insulating layer 110a and the insulating layer 110c each release a small amount of impurities (e.g., hydrogen and water) and are difficult for impurities to permeate. This can prevent the impurities contained in the insulating layer 110a and the insulating layer 110c from diffusing into the channel formation region. Therefore, a transistor that exhibits good electrical characteristics and is highly reliable can be obtained.
  • impurities e.g., hydrogen and water
  • the insulating layer 110a and the insulating layer 110c are preferably made of a film that is difficult for oxygen to permeate. This can suppress the oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112a through the insulating layer 110a. Similarly, the oxygen contained in the insulating layer 110b can be suppressed from diffusing to the conductive layer 112b through the insulating layer 110c. This can suppress the conductive layer 112a and the conductive layer 112b from being oxidized and increasing their electrical resistance.
  • the oxygen contained in the insulating layer 110b is suppressed from diffusing to the insulating layer 110a side and the insulating layer 110c side, so that the amount of oxygen supplied from the insulating layer 110b to the channel formation region is increased, and oxygen vacancies (V O ) and V O H in the channel formation region can be reduced.
  • oxygen can be effectively supplied from the insulating layer 110b to the channel formation region.
  • a configuration in which one or both of the insulating layers 110a and 110c are not provided may also be used.
  • the insulating layer 110a and the insulating layer 110c each preferably contain nitrogen, and preferably use one or more of the above-mentioned nitrides and nitride oxides.
  • silicon nitride or silicon nitride oxide may be preferably used for the insulating layer 110a and the insulating layer 110c.
  • one or both of the insulating layer 110a and the insulating layer 110c may use one or more of an oxide and an oxynitride.
  • aluminum oxide may be preferably used for the insulating layer 110a and the insulating layer 110c.
  • the insulating layer 110a may use the same material as the insulating layer 110c, or a different material.
  • different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.
  • the thickness T110a of the insulating layer 110a can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 20 nm or more, 50 nm or more, or 70 nm or more, and can be less than 1 ⁇ m, 500 nm or less, 400 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, or 120 nm or less. As shown in FIG. 3, the thickness T110a can be the shortest distance between the surface on which the insulating layer 110a is formed (here, the upper surface of the conductive layer 112a) and the lower surface of the insulating layer 110b in a cross-sectional view.
  • the thickness T110a of the insulating layer 110a When the thickness T110a of the insulating layer 110a is large, the amount of impurities released from the insulating layer 110a increases, and the amount of impurities diffusing into the channel formation region may increase. On the other hand, when the thickness T110a is small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112a side through the insulating layer 110a, and the amount of oxygen supplied to the channel formation region may decrease. By setting the thickness T110a within the above range, oxygen vacancies (V O ) and V O H in the channel formation region can be reduced. In addition, the conductive layer 112a is oxidized by the oxygen contained in the insulating layer 110b, and the electrical resistance of the conductive layer 112a can be prevented from increasing.
  • the thickness T110c of the insulating layer 110c can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 15 nm or more, or 20 nm or more, and 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, 120 nm or less, or 100 nm or less.
  • the thickness T110c can be the shortest distance between the surface on which the insulating layer 110c is formed (here, the upper surface of the insulating layer 110b) and the lower surface of the conductive layer 112b in a cross-sectional view.
  • the thickness T110c of the insulating layer 110c When the thickness T110c of the insulating layer 110c is large, the amount of impurities released from the insulating layer 110c increases, and the amount of impurities diffusing into the channel formation region may increase. On the other hand, when the thickness T110c is small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112b side through the insulating layer 110c, and the amount of oxygen supplied to the channel formation region may decrease. By setting the thickness T110c within the above range, oxygen vacancies (V O ) and V O H in the channel formation region can be reduced. In addition, the conductive layer 112b is oxidized by the oxygen contained in the insulating layer 110b, and the electrical resistance of the conductive layer 112b can be prevented from increasing.
  • At least one of the region of the semiconductor layer 108 in contact with the insulating layer 110a and the region of the semiconductor layer 108 in contact with the insulating layer 110c may be a region having a lower electrical resistance than the channel formation region (hereinafter, also referred to as a low-resistance region).
  • the region may be a region having a higher carrier concentration or a higher oxygen defect density than the channel formation region.
  • the semiconductor layer 108 can be configured to have a low-resistance region between the region in contact with the conductive layer 112a (one of the source region and the drain region) and the channel formation region. Similarly, by using a material that releases impurities in the insulating layer 110c, the region of the semiconductor layer 108 in contact with the insulating layer 110c can be a low-resistance region.
  • the semiconductor layer 108 can be configured to have a low-resistance region between the region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel formation region.
  • the low resistance regions can function as buffer regions to reduce the drain electric field. These low resistance regions may also function as source or drain regions.
  • the conductive layer 112a functions as a drain electrode and the conductive layer 112b functions as a source electrode, by making the region of the semiconductor layer 108 in contact with the insulating layer 110a into a low resistance region, a high electric field is unlikely to occur near the drain region, the generation of hot carriers is suppressed, and deterioration of the transistor can be suppressed.
  • the conductive layer 112a functions as a source electrode and the conductive layer 112b functions as a drain electrode, by making the region of the semiconductor layer 108 in contact with the insulating layer 110c into a low resistance region, a high electric field is unlikely to occur near the drain region, the generation of hot carriers is suppressed, and deterioration of the transistor can be suppressed.
  • the amount of impurities released from the insulating layers 110a and 110c is too large, the impurities may diffuse into the channel formation region. Even if a material that releases impurities is used for the insulating layers 110a and 110c, it is preferable that the amount of released impurities is small.
  • the insulating layer 110 has at least the insulating layer 110b.
  • the insulating layer 110 may not have one or both of the insulating layer 110a and the insulating layer 110c.
  • the insulating layer 110 may have a stacked structure of two layers, four or more layers, or a single layer structure.
  • the top surface shape of the openings 141 and 143 is not limited, and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or other polygon, or a shape with rounded corners of these polygons.
  • the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).
  • it is preferable that the top surface shape of the openings 141 and 143 is a circle.
  • the top shape of the opening 141 refers to the shape of the top end of the insulating layer 110 on the opening 141 side.
  • the top shape of the opening 143 refers to the shape of the bottom end of the conductive layer 112b on the opening 143 side.
  • the top surface shapes of openings 141 and 143 can be made to match or roughly match each other.
  • the bottom surface of conductive layer 112b refers to the surface on the insulating layer 110 side.
  • the top surface of insulating layer 110 refers to the surface on the conductive layer 112b side.
  • openings 141 and 143 do not have to be the same. Furthermore, when the top surface shapes of openings 141 and 143 are circular, openings 141 and 143 may or may not be concentric.
  • Figures 4A and 4B are enlarged views of the transistor 100 shown in Figures 1A and 1B.
  • the channel length L100 of the transistor 100 is indicated by a double-headed dashed arrow.
  • the channel length L100 of the transistor 100 corresponds to the length of the side of the insulating layer 110b on the opening 141 side in a cross-sectional view.
  • the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle ⁇ 110 between the side of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Therefore, the channel length L100 can be set to a value smaller than the limit resolution of the exposure device, and a transistor of a fine size can be realized.
  • a transistor with an extremely short channel length that could not be realized with a conventional exposure device for mass production of flat panel displays (for example, a minimum line width of about 2 ⁇ m or 1.5 ⁇ m).
  • a transistor with a channel length of less than 10 nm without using an extremely expensive exposure device used in cutting-edge LSI technology.
  • the channel length L100 can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.
  • the channel length L100 can be 100 nm or more and 1 ⁇ m or less.
  • the on-state current of the transistor 100 can be increased.
  • the transistor 100 By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-definition display device, even if the number of wirings is increased, signal delay in each wiring can be reduced and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.
  • the channel length L100 can be controlled by adjusting the thickness T110b and angle ⁇ 110 of the insulating layer 110b. Note that in FIG. 4B, the thickness T110b of the insulating layer 110b is indicated by a double-headed arrow of a dashed line.
  • the thickness T110b of the insulating layer 110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and can be less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.
  • the side of the insulating layer 110 on the opening 141 side is preferably tapered.
  • the angle ⁇ 110 is preferably less than 90 degrees. By reducing the angle ⁇ 110, the coverage of the layer (e.g., the semiconductor layer 108) formed on the insulating layer 110 can be improved. Furthermore, the smaller the angle ⁇ 110, the longer the channel length L100 can be, and the larger the angle ⁇ 110, the shorter the channel length L100 can be.
  • the angle ⁇ 110 can be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more, and less than 90 degrees, 85 degrees or less, or 80 degrees or less.
  • the angle ⁇ 110 may also be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less.
  • the shape of the side of the insulating layer 110 on the opening 141 side is shown as straight lines in cross section, but this is not a limitation of one embodiment of the present invention. In cross section, the shape of the side of the insulating layer 110 on the opening 141 side may be curved, or the side may have both straight and curved regions.
  • the conductive layer 112b is not provided inside the opening 141. Specifically, it is preferable that the conductive layer 112b does not have a region that is in contact with the side surface of the insulating layer 110 on the opening 141 side. If the conductive layer 112b is also provided inside the opening 141, the channel length L100 of the transistor 100 becomes shorter than the length of the side surface of the insulating layer 110b, which may make it difficult to control the channel length L100. Therefore, it is preferable that the top shape of the opening 143 matches the top shape of the opening 141, or that the opening 143 encompasses the opening 141 in a top view (also referred to as a plan view).
  • the width D141 of opening 141 is indicated by a double-headed arrow with a dashed two-dot line.
  • Figure 4A shows an example in which the top surface shape of opening 141 is circular.
  • width D141 corresponds to the diameter of the circle
  • channel width W100 of transistor 100 is the length of the circumference of the circle.
  • channel width W100 is ⁇ x D141. In this way, when the top surface shape of opening 141 is circular, a transistor with a smaller channel width W100 can be realized compared to other shapes.
  • the width D141 of the opening 141 may vary in the depth direction.
  • the average value of the diameter at the highest point of the insulating layer 110b (or insulating layer 110) in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these three diameters may be used as the width D141 of the opening 141.
  • the diameter of the opening 141 may be any one of the diameters at the highest point of the insulating layer 110b (or insulating layer 110) in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these two diameters.
  • the width D141 of the opening 141 is equal to or greater than the limit resolution of the exposure device.
  • the width D141 can be, for example, 200 nm or more, 300 nm or more, 400 nm or more, or 500 nm or more, and less than 5 ⁇ m, 4.5 ⁇ m or less, 4 ⁇ m or less, 3.5 ⁇ m or less, 3 ⁇ m or less, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, or 1 ⁇ m or less.
  • the insulating layer 110a and the insulating layer 110c are made of a material that releases less hydrogen from themselves.
  • the insulating layer 110a and the insulating layer 110c are made of a material that releases even a small amount of hydrogen, it is preferable that the thicknesses of these layers are thin.
  • the thickness T110a of the insulating layer 110a and the thickness T110c of the insulating layer 110c are 1 nm or more, 3 nm or more, or 5 nm or more, and preferably 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. This makes it possible to reduce the amount of impurities that diffuse into the channel formation region, and to provide a transistor that exhibits good electrical characteristics and is highly reliable even when the channel length L100 is short.
  • the region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region
  • one embodiment of the present invention is not limited to this.
  • the region of the semiconductor layer 108 in contact with the insulating layer 110a may also function as a channel formation region.
  • the region in contact with the insulating layer 110c may also function as a channel formation region.
  • a step may be formed between the insulating layer 110 and the conductive layer 112a, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 may be provided along the step.
  • Figures 5A to 5C are enlarged views of the transistor 200 shown in Figures 1A to 1C.
  • the channel length of the transistor 200 is the length of the region where the semiconductor layer 208 and the conductive layer 204 overlap between a pair of regions 208D.
  • the channel length L200 of the transistor 200 is indicated by a dashed double-headed arrow.
  • the channel length L200 of the transistor 200 is determined by the length of the conductive layer 204, and is equal to or greater than the limit resolution of the exposure device used to fabricate the transistor.
  • the channel length L200 can be 1.5 ⁇ m or greater.
  • the conductive layer 202 which functions as the back gate electrode of the transistor 200, preferably extends beyond the end of the region where the conductive layer 204 and the semiconductor layer 208 overlap in the channel length direction.
  • the size of the conductive layer 202 is preferably larger than the size of the region where the conductive layer 204 and the semiconductor layer 208 overlap in the channel length direction.
  • the conductive layer 202 preferably has a portion that protrudes beyond the end of the conductive layer 204 in the channel length direction.
  • the portion of the semiconductor layer 208 that overlaps with the conductive layer 204 is described as a channel formation region, but in reality, a channel can also be formed in the portion that overlaps with the conductive layer 202 without overlapping with the conductive layer 204.
  • the channel width of the transistor 200 is the width of the region where the semiconductor layer 208 and the conductive layer 204 overlap in a direction perpendicular to the channel length direction.
  • the channel width W200 of the transistor 200 is indicated by a dashed double-headed arrow.
  • the channel length L100 of the transistor 100 can be set to a value smaller than the limit resolution of the exposure device, and the channel length L200 of the transistor 200 can be set to a value equal to or greater than the limit resolution of the exposure device.
  • the transistors 100 and 200 can be formed by sharing some of the steps. Specifically, the semiconductor layer 108 and the semiconductor layer 208 can be formed in the same step.
  • a part of the insulating layer 106 functions as a gate insulating layer of the transistor 100, and another part of the insulating layer 106 functions as a gate insulating layer of the transistor 200.
  • the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed in the same step. Therefore, the productivity of the semiconductor device 10 can be increased and the manufacturing cost can be reduced.
  • the conductive layer 204 and the conductive layer 202 preferably protrude outward beyond the end of the semiconductor layer 208.
  • the entire channel width direction of the semiconductor layer 208 is covered by the conductive layer 204 and the conductive layer 202 via the insulating layer 106 and the insulating layer 120.
  • the semiconductor layer 208 can be electrically surrounded by an electric field generated by a pair of gate electrodes.
  • 5A and 5C show a configuration in which the conductive layer 204 and the conductive layer 202 are not electrically connected.
  • a constant potential may be applied to one of the pair of gate electrodes, and a signal for driving the transistor 200 may be applied to the other.
  • the threshold voltage when the transistor 200 is driven by the other gate electrode can be controlled by the potential applied to one gate electrode.
  • the conductive layer 204 and the conductive layer 202 may be electrically connected.
  • an electric field for inducing a channel in the semiconductor layer 208 can be effectively applied, and the on-current of the transistor 200 can be increased.
  • This also makes it possible to miniaturize the transistor 200.
  • an opening reaching the conductive layer 202 can be provided in the insulating layer 106 and the insulating layer 120, and the conductive layer 204 can be formed to cover the opening.
  • the conductive layer 202 may be electrically connected to the conductive layer 212a or the conductive layer 212b.
  • an opening reaching the conductive layer 202 may be provided in the insulating layer 120, and the conductive layer 212a or the conductive layer 212b may be formed to cover the opening.
  • the insulating layer 120 which is provided in contact with the upper and side surfaces of the conductive layer 202, can be made of the same material as that used for the insulating layer 110.
  • the insulating layer 120 preferably has a laminated structure.
  • FIG. 5B and other figures show that the insulating layer 120 has a laminated structure of an insulating layer 120a and an insulating layer 120b on the insulating layer 120a.
  • the insulating layers 120a and 120b can each be made of a material that can be used for the insulating layer 110.
  • oxygen can be supplied to the semiconductor layer 208, particularly to the channel formation region of the semiconductor layer 208.
  • the oxygen contained in the insulating layer 120b diffuses in the insulating layer 120b and is supplied to the semiconductor layer 208 through the interface between the insulating layer 120b and the semiconductor layer 208.
  • oxygen vacancies (V O ) are repaired and oxygen vacancies (V O ) can be reduced. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.
  • the oxygen diffusion coefficient of the insulating layer 120b at 350° C. is preferably 1 ⁇ 10 ⁇ 12 cm 2 /sec or more, and more preferably 5 ⁇ 10 ⁇ 12 cm 2 /sec or more.
  • the insulating layer 120b can be made of a material that can be used for the insulating layer 110b.
  • the insulating layer 120b preferably contains oxygen, and one or more of an oxide and an oxynitride can be suitably used.
  • the insulating layer 120b can be made of, for example, silicon oxide or silicon oxynitride.
  • the formation of the insulating layer 120b will now be described in detail.
  • silicon oxynitride is formed using the PECVD method.
  • a deposition gas containing silicon and a gas containing an oxidizing gas can be used as the raw material gas for the insulating layer 120b. Please refer to the above description for the deposition gas containing silicon and the oxidizing gas.
  • the F ratio is 20 or less, 18 or less, 16 or less, 14 or less, 13 or less, 12 or less, or 11 or less, and preferably 4 or more, 6 or more, 7 or more, 8 or more, or 9 or more.
  • the F ratio may be smaller than the diffusion coefficient of oxygen in the insulating layer 120b compared to the diffusion coefficient of oxygen in the insulating layer 110b. Therefore, the F ratio in the formation of the insulating layer 120b can be made higher than the F ratio in the formation of the insulating layer 110b. By increasing the F ratio, the film formation speed of the insulating layer 120b can be increased, and the productivity can be improved.
  • the etching rate of the insulating layer 120b with 0.5 wt % hydrofluoric acid at 25° C. is 5 nm/min or more, 6 nm/min or more, or 7 nm/min or more, and preferably 15 nm/min or less.
  • the amount of oxygen supplied from the insulating layer 120b to the semiconductor layer 208 may be smaller than the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108.
  • the amount of oxygen released from the insulating layer 120b may be smaller than the amount of oxygen released from the insulating layer 110b.
  • the diffusion coefficient of the substance in the insulating layer 110b is preferably larger than that in the insulating layer 120b.
  • the diffusion coefficient of oxygen in the insulating layer 110b is preferably larger than that in the insulating layer 120b. This allows the transistor 100, even with a short channel length, to exhibit good electrical characteristics and to be a highly reliable transistor.
  • the F ratio in the formation of the insulating layer 110b is preferably lower than that in the formation of the insulating layer 120b.
  • the etching rate of the insulating layer 110b is preferably faster than the etching rate of the insulating layer 120b with respect to one etchant.
  • the insulating layer 120a in contact with the conductive layer 202 is preferably made of a material that does not easily diffuse the metal elements contained in the conductive layer 202. This makes it possible to prevent the metal elements contained in the conductive layer 202 from diffusing into the channel formation region of the semiconductor layer 208 via the insulating layer 120.
  • the insulating layer 120a is preferably made of a material that can be used for the insulating layer 110a and the insulating layer 110c.
  • the insulating layer 120a preferably contains nitrogen, and one or more of a nitride and a nitride oxide can be preferably used.
  • the insulating layer 120a can be made of, for example, silicon nitride.
  • the insulating layer 120a can be made of one or more of an oxide and an oxynitride.
  • the insulating layer 120a can be made of, for example, aluminum oxide. Note that the insulating layer 120a, the insulating layer 110a, and the insulating layer 110c may be made of the same material or different materials.
  • the amount of impurities (e.g., water and hydrogen) released from the insulating layer 120a is small. This makes it possible to prevent impurities contained in the insulating layer 120a from diffusing into the channel formation region of the semiconductor layer 208 via the insulating layer 120b, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.
  • impurities e.g., water and hydrogen
  • the insulating layer 120 is shown here as having a two-layer stacked structure, one embodiment of the present invention is not limited to this.
  • the insulating layer 120 may have a three or more layer stacked structure, or a single layer structure.
  • the insulating layer 120 is preferably provided at least in a portion that contacts the channel formation region of the semiconductor layer 208 and is provided so as to cover the upper surface and side surface of the conductive layer 202.
  • FIG. 5B and other figures show a configuration in which the semiconductor layer 208 has a portion that protrudes from the end of the insulating layer 120.
  • the semiconductor layer 208 has a region that contacts the side surface of the insulating layer 120. A portion of the end of the semiconductor layer 208 contacts the upper surface of the insulating layer 120, and another portion contacts the upper surface of the insulating layer 110. It can also be said that a portion of the lower surface of the semiconductor layer 208 contacts the upper surface of the insulating layer 120, and another portion contacts the upper surface of the insulating layer 110.
  • the insulating layer 120 may be provided in the region where the semiconductor layer 208 is provided, and the entire lower surface of the semiconductor layer 208 may contact the upper surface of the insulating layer 120.
  • the thickness of the semiconductor layer 208 is uniform regardless of location, but one embodiment of the present invention is not limited to this.
  • the thickness may be different between the region of the semiconductor layer 208 that overlaps with the insulating layer 106 and the region that does not overlap with the insulating layer 106.
  • the thickness of the region of the semiconductor layer 208 that does not overlap with the insulating layer 106 may be thinner than the thickness of the overlapping region.
  • the thickness may be different between the region of the semiconductor layer 208 that overlaps with any of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b, and the region that does not overlap with any of these.
  • the conductive layers 212a and 212b are formed, a part of the semiconductor layer 208 is removed, and the thickness of the region of the semiconductor layer 208 that does not overlap with any of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b may be thinner than the thickness of the region that overlaps with any of these.
  • the thickness may be different between the region of the semiconductor layer 208 that overlaps with the insulating layer 106, the region that overlaps with any of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b, and the region that does not overlap with any of these.
  • the region 208D has a lower electrical resistance than the channel formation region.
  • the region 208D can also be said to have a higher carrier concentration, a higher oxygen defect density, or a higher impurity concentration than the channel formation region.
  • Region 208L has the same or lower electrical resistance as the channel formation region. Region 208L can also be described as a region with the same or higher carrier concentration, the same or higher oxygen defect density, or the same or higher impurity concentration as the channel formation region. Furthermore, region 208L has the same or higher electrical resistance as region 208D. Region 208L can also be described as a region with the same or lower carrier concentration, the same or lower oxygen defect density, or the same or lower impurity concentration as region 208D.
  • Region 208L functions as a buffer region for alleviating the drain electric field.
  • Region 208L does not overlap with conductive layer 204, and therefore is a region in which a channel is hardly formed even when a gate voltage is applied to conductive layer 204.
  • Region 208L preferably has a higher carrier concentration than the channel formation region. This allows region 208L to function as an LDD (Lightly Doped Drain) region.
  • LDD Lightly Doped Drain
  • the carrier concentration in the semiconductor layer 208 is preferably lowest in the channel formation region, and increases in the order of region 208L and region 208D.
  • region 208L between the channel formation region and region 208D, the carrier concentration in the channel formation region can be kept extremely low, even if impurities such as hydrogen diffuse from region 208D during the manufacturing process.
  • the carrier concentration in region 208L does not have to be uniform, and may have a gradient in which the carrier concentration decreases from region 208D toward the channel formation region.
  • either the hydrogen concentration or the oxygen vacancy concentration in region 208L, or both, may have a gradient in which the concentration decreases from region 208D toward the channel formation region.
  • some ends of the conductive layers 212a and 212b are located inside the openings 147a and 147b. In other words, it is preferable that some ends of the conductive layers 212a and 212b are in contact with the semiconductor layer 208 in the openings 147a and 147b. This makes it possible to make the region in contact with the conductive layer 212a adjacent to one of the pair of regions 208D, and similarly, to make the region in contact with the conductive layer 212b adjacent to the other of the pair of regions 208D.
  • top surface shapes of openings 147a and 147b are not particularly limited.
  • the top surface shapes of openings 147a and 147b can be shapes that can be applied to openings 141 and 143.
  • FIG. 5A and other figures show a configuration in which openings 147a and 147b have a top surface shape that is a rectangle with rounded corners, which is different from the top surface shapes of openings 141 and 143, but one aspect of the present invention is not limited to this.
  • the top surface shapes of openings 147a and 147b may be the same as the top surface shapes of openings 141 and 143.
  • the impurity element When the impurity element is added to the semiconductor layer 208 to form the regions 208L and 208D, the impurity element may be supplied to the semiconductor layer 108 through the insulating layer 106 using the conductive layer 104 as a mask. As a result, the region 108L is formed in a region of the semiconductor layer 108 that does not overlap with the conductive layer 104. Note that in the transistor 100, the region of the semiconductor layer 108 that is in contact with the conductive layer 112b functions as a source region or a drain region. The region 108L is formed in a part of the source region or the drain region. Note that the concentration of the impurity element in the region 108L may be different from the concentration of the impurity element in the region 208L.
  • the region 108L may not be formed.
  • the conductive layer 104 extends to cover the end of the semiconductor layer 108, the entire semiconductor layer 108 is masked by the conductive layer 104, so that the impurity element is not supplied to the semiconductor layer 108 and the region 108L is not formed.
  • the structure in which the conductive layer 212a and the conductive layer 212b are formed in the same process as the conductive layer 204 is shown here, one embodiment of the present invention is not limited to this.
  • the conductive layer 212a and the conductive layer 212b may be formed in a process different from that of the conductive layer 204.
  • the conductive layer 104 and the conductive layer 204 are formed over the insulating layer 106, and an impurity element is supplied to the semiconductor layer 208 using the conductive layer 204 as a mask to form a source region and a drain region.
  • An insulating layer 195 is formed over the conductive layer 104 and the conductive layer 204, and an opening reaching the source region and an opening reaching the drain region are formed in the insulating layer 106 and the insulating layer 195, and the conductive layer 212a and the conductive layer 212b can be formed so as to cover these openings.
  • Metal oxides that can be used for the semiconductor layer 108 and the semiconductor layer 208 will be specifically described.
  • metal oxides include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide preferably contains at least indium or zinc.
  • the metal oxide preferably contains two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium.
  • the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more of gallium and tin.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification may include metalloid elements.
  • the semiconductor layer 108 and the semiconductor layer 208 may each be made of, for example, indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also referred to as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide ( Indium aluminum zinc oxide (In-Al-Zn oxide, also written as AZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-
  • the field effect mobility of the transistor can be increased.
  • a transistor with a large on-current can be realized.
  • the metal oxide may contain one or more metal elements having a high period number in the periodic table.
  • metal elements having a high period number include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may contain one or more nonmetallic elements.
  • the carrier concentration increases or the band gap decreases, which may increase the field effect mobility of the transistor.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline and the diffusion of impurities in the metal oxide can be suppressed. This suppresses fluctuations in the electrical characteristics of the transistor and increases its reliability.
  • the electrical characteristics and reliability of the transistors vary depending on the composition of the metal oxide applied to the semiconductor layer 108 and the semiconductor layer 208. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that combines excellent electrical characteristics and high reliability can be obtained.
  • the metal oxide is an In-M-Zn oxide
  • the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of element M.
  • the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of element M.
  • element M contains multiple metal elements
  • the total proportion of the atomic numbers of the metal elements can be regarded as the proportion of the atomic number of element M.
  • the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained may be referred to as the indium content. The same applies to other metal elements.
  • the on-state current or field effect mobility of the transistor can be increased. Furthermore, by having the element M, the generation of oxygen vacancies (V 2 O 3 ) can be suppressed.
  • the element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium.
  • In:Al:Zn 40:1:10 and metal oxides in the vicinity thereof can be preferably used.
  • a metal oxide having a polycrystalline structure is used for the semiconductor layer 108 and the semiconductor layer 208, the grain boundaries become the recombination centers, and carriers are captured, which may reduce the on-current of the transistor.
  • a metal oxide having a composition that is likely to form a polycrystalline structure it is preferable to include an element that inhibits crystallization.
  • ITO indium tin oxide
  • ITSO indium tin oxide containing silicon
  • the silicon content (the ratio of the number of silicon atoms to the sum of the number of atoms of all metal elements contained) is preferably 1% or more and 20% or less, more preferably 3% or more and 20% or less, even more preferably 3% or more and 15% or less, and even more preferably 5% or more and 15% or less.
  • the composition of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES).
  • EDX energy dispersive X-ray spectrometry
  • XPS X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • a combination of these techniques may be used for the analysis.
  • the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, may be difficult to quantify, or may be below the detection limit.
  • the metal oxide can be formed preferably by sputtering or atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the composition of the formed metal oxide may differ from the composition of the sputtering target.
  • the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.
  • the semiconductor layer 108 and the semiconductor layer 208 may each have a stacked structure having two or more metal oxide layers.
  • the compositions of the two or more metal oxide layers in the semiconductor layer 108 and the semiconductor layer 208 may be the same or approximately the same.
  • a stacked structure of metal oxide layers with the same composition for example, they can be formed using the same sputtering target, thereby reducing manufacturing costs.
  • compositions of the two or more metal oxide layers in each of the semiconductor layer 108 and the semiconductor layer 208 may be different from each other.
  • gallium, aluminum, or tin as the element M.
  • the element M in the first metal oxide layer and the second metal oxide layer may be the same or different from each other.
  • the first metal oxide layer and the second metal oxide layer may be IGZO layers having different compositions from each other.
  • a laminated structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) may be used.
  • the boundary (interface) between the first metal oxide layer and the second metal oxide layer may not be clearly identified.
  • the semiconductor layer 108 and the semiconductor layer 208 are preferably made of a crystalline metal oxide.
  • a crystalline metal oxide examples include a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a nanocrystalline (nc: nano-crystal) structure.
  • the semiconductor layer 108 and the semiconductor layer 208 each use CAAC-OS or nc-OS.
  • CAAC-OS has multiple layered crystals.
  • the c-axis of the crystals is oriented in the normal direction of the surface on which the semiconductor layer 108 and the semiconductor layer 208 are preferably layered crystals parallel or approximately parallel to the surface on which the semiconductor layer 108 is formed.
  • the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the top surface in a region in contact with the top surface of the conductive layer 112b, and has layered crystals parallel or approximately parallel to the side surface in a region in contact with the side surface of the conductive layer 112b.
  • the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the side surface of the insulating layer 110, which is the surface on which the semiconductor layer 108 is formed, in the opening 141.
  • the layered crystals of the semiconductor layer 108 are formed approximately parallel to the channel length direction of the transistor 100, so that the transistor can have a large on-current.
  • the semiconductor layer 208 preferably has layered crystals parallel or approximately parallel to the surface on which the semiconductor layer 108 is formed (here, the top surface and side surface of the insulating layer 120 and the top surface of the insulating layer 110).
  • the semiconductor layer 208 has layered crystals that are parallel or approximately parallel to the upper surface of the insulating layer 120, which is the surface on which it is formed, in the region where it overlaps with the conductive layer 204.
  • the density of defect states in the channel formation region can be reduced.
  • a metal oxide with low crystallinity a transistor capable of passing a large current can be realized.
  • the substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation.
  • the crystallinity of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed, for example, by X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • VOH When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable to reduce VOH in the channel formation region as much as possible to make it highly pure or substantially highly pure.
  • it is important to remove impurities such as water and hydrogen in the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to repair oxygen vacancies ( VOH ).
  • impurities such as water and hydrogen in the metal oxide
  • VOH repair oxygen vacancies
  • supplying oxygen to a metal oxide to repair oxygen vacancies ( VOH ) may be referred to as oxygen addition treatment.
  • the carrier concentration of the channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , further preferably less than 1 ⁇ 10 16 cm ⁇ 3 , further preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and further preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the carrier concentration of the channel formation region can be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • OS transistors have small variations in electrical characteristics due to radiation exposure, i.e., they have high resistance to radiation, and therefore can be suitably used in environments where radiation may be present. It can also be said that OS transistors have high reliability against radiation.
  • OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors.
  • OS transistors can also be suitably used in semiconductor devices used in outer space.
  • radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).
  • the semiconductor layer 108 and the semiconductor layer 208 may each have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, conductive layer 212b, conductive layer 202 may each have a single layer structure or a stacked structure of two or more layers.
  • Examples of materials that can be used for the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, and alloys containing one or more of the above-mentioned metals.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 can each be preferably made of a conductive material having a low electrical resistivity, including one or more of copper, silver, gold, and aluminum. In particular, copper or aluminum is preferable because of its excellent mass productivity.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 can each be made of a metal oxide (oxide conductor) having electrical conductivity.
  • oxide conductors include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called ITO containing silicon, ITSO), zinc oxide to which gallium is added, and In-Ga-Zn oxide.
  • Metal oxides containing indium are particularly preferred because of their high electrical conductivity.
  • a metal oxide that has become a conductor can be called an oxide conductor.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 may each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) described above and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, the wiring resistance can be reduced.
  • the conductive layers 112a, 112b, 104, 204, 212a, 212b, and 202 may each be a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, the film can be processed by wet etching, reducing manufacturing costs.
  • X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 may be made of the same material or different materials.
  • the conductive layer 112a and the conductive layer 112b have a region in contact with the semiconductor layer 108.
  • a metal oxide is used as the semiconductor layer 108
  • an insulating oxide e.g., aluminum oxide
  • the conductive layer 112a and the conductive layer 112b are preferably made of, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain low electrical resistance even when oxidized. Note that, when the conductive layer 112a has a stacked structure, it is preferable to use a conductive material that is difficult to oxidize at least for the layer in contact with the semiconductor layer 108. The same applies to the conductive layer 112b.
  • the conductive layer 112a and the conductive layer 112b can each be made of the oxide conductors described above. Specifically, metal oxides such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, and zinc oxide doped with gallium can be used.
  • metal oxides such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, and zinc oxide doped with gallium can be used.
  • the conductive layers 112a and 112b may each be made of a nitride conductor.
  • nitride conductors include tantalum nitride and titanium nitride.
  • the conductive layer 112b is provided on the insulating layer 120b.
  • a conductive material that is not easily oxidized a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor for the conductive layer 112b.
  • the amount of oxygen released from the insulating layer 120b is smaller than the amount of oxygen released from the insulating layer 110b. Therefore, there is little risk that the conductive layer 112b having a region in contact with the insulating layer 120b will be oxidized, and the electrical resistance of the conductive layer 112b will increase.
  • the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 may each have a laminated structure.
  • Figures 6A and 6B show a configuration in which the conductive layer 112a has a laminated structure of a conductive layer 112a_1 and a conductive layer 112a_2 on the conductive layer 112a_1.
  • a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor is preferably used.
  • materials that can be used for the conductive layer 112a_2 see the description of the conductive layer 112a.
  • the material used is not particularly limited. For example, it is preferable to use a material having a lower electrical resistivity than the conductive layer 112a_2 for the conductive layer 112a_1. This can reduce the electrical resistance of the conductive layer 112a. For example, it is preferable to use In-Sn-Si oxide (ITSO) for the conductive layer 112a_2, and copper or tungsten for the conductive layer 112a_1.
  • ITSO In-Sn-Si oxide
  • 6A and 6B show a configuration in which the thickness of the conductive layer 112a_1 and the thickness of the conductive layer 112a_2 are the same or approximately the same, but one embodiment of the present invention is not limited to this.
  • the thickness of the conductive layer 112a_1 and the thickness of the conductive layer 112a_2 may be different.
  • a material having a lower electrical resistivity than the conductive layer 112a_2 may be used for the conductive layer 112a_1, and the thickness of the conductive layer 112a_1 may be made thicker than the thickness of the conductive layer 112a_2. This can reduce the electrical resistance of the conductive layer 112a.
  • conductive layer 112a_2 may be aligned or approximately aligned with the end of conductive layer 112a_1.
  • conductive layer 112a can be formed by forming a first film that will become conductive layer 112a_1 and a second film that will become conductive layer 112a_2, and processing the first film and the second film.
  • the end of the conductive layer 112a_2 does not have to be aligned with the end of the conductive layer 112a_1.
  • the conductive layer 112a_2 can be provided so as to cover the conductive layer 112a_1.
  • the conductive layer 112a_2 is in contact with the top and side surfaces of the conductive layer 112a_1. It can also be said that the conductive layer 112a_2 has a portion that protrudes beyond the end of the conductive layer 112a_1.
  • the conductive layer 112a_1 can be formed, a film that becomes the conductive layer 112a_2 can be formed on the conductive layer 112a_1, and the film can be processed to form the conductive layer 112a_2.
  • the insulating layer 106 may have a single-layer structure or a stacked structure of two or more layers.
  • the insulating layer 106 preferably has one or more inorganic insulating films. Examples of materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides.
  • the insulating layer 106 can be made of any of the materials that can be used for the insulating layer 110.
  • the insulating layer 106 has a region in contact with the semiconductor layer 108 and the semiconductor layer 208.
  • a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable to use either the oxide or the oxynitride described above for at least the film that is in contact with the semiconductor layer 108 and the semiconductor layer 208 among the films that constitute the insulating layer 106. It is more preferable to use a film that releases oxygen when heated for the insulating layer 106.
  • the insulating layer 106 has a single-layer structure, it is preferable to use an oxide or an oxynitride for the insulating layer 106. Specifically, silicon oxide or silicon oxynitride can be suitably used for the insulating layer 106.
  • the insulating film on the side in contact with the semiconductor layer 108 and the semiconductor layer 208 has an oxide or an oxynitride
  • the insulating film on the side in contact with the conductive layer 104 and the conductive layer 204 has a nitride or a nitride oxide.
  • the oxide or oxynitride for example, silicon oxide or silicon oxynitride can be preferably used.
  • silicon nitride or silicon nitride oxide can be preferably used.
  • Silicon nitride and silicon nitride oxide are suitable for use as the insulating layer 106 because they release a small amount of impurities (e.g., water and hydrogen) and are less permeable to oxygen and hydrogen. By preventing impurities from diffusing from the insulating layer 106 to the semiconductor layer 108 and the semiconductor layer 208, the electrical characteristics of the transistor can be improved and the reliability can be increased.
  • impurities e.g., water and hydrogen
  • the thickness of the gate insulating layer becomes thin, the leakage current may become large.
  • a material with a high relative dielectric constant also called a high-k material
  • high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.
  • the insulating layer 195 which functions as a protective layer for the transistor 100, the transistor 200, and the capacitor 150, is preferably made of a material from which impurities are unlikely to diffuse. By providing the insulating layer 195, diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the semiconductor device. Examples of impurities include water and hydrogen.
  • the insulating layer 195 can be an insulating layer having an inorganic material or an insulating layer having an organic material.
  • an inorganic material such as oxide, oxynitride, nitride oxide, or nitride can be suitably used for the insulating layer 195.
  • silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used.
  • one or more of acrylic resin and polyimide resin can be used as the organic material.
  • a photosensitive material may be used as the organic material. Two or more of the above insulating films may be stacked.
  • the insulating layer 195 may have a stacked structure of an insulating layer having an inorganic material and an insulating layer having an organic material.
  • Substrate 102 Although there is no significant limitation on the material of the substrate 102, it is necessary that the material has at least a heat resistance sufficient to withstand subsequent heat treatment.
  • a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 102.
  • a semiconductor element may be provided on the substrate 102.
  • the shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.
  • a flexible substrate may be used as the substrate 102, and the transistors 100 and the like may be formed directly on the flexible substrate.
  • a peeling layer may be provided between the substrate 102 and the transistors 100 and the like. By providing a peeling layer, after a semiconductor device is partially or entirely completed on the substrate, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistors 100 and the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.
  • FIG 7A is a top view of a semiconductor device 10A according to one embodiment of the present invention.
  • FIG 7B is a cross-sectional view taken along dashed line A1-A2 in FIG 7A.
  • FIG 1C can be used to refer to a cross-sectional view taken along dashed line B1-B2.
  • the semiconductor device 10A includes a transistor 100, a transistor 200A, a capacitance element 150, and an insulating layer 110.
  • the transistor 200A differs from the transistor 100 shown in FIG. 1C etc. mainly in that the side surface of the insulating layer 120 is not in contact with the semiconductor layer 208.
  • the insulating layer 120 is provided over the entire area in which the semiconductor layer 208 is provided, and the entire lower surface of the semiconductor layer 208 contacts the upper surface of the insulating layer 120. This reduces the step on the surface on which the semiconductor layer 208 is formed, and improves the coverage of the semiconductor layer 208.
  • configuration of the insulating layer 120 shown in configuration example 2 can also be applied to other configuration examples.
  • FIG 8A is a top view of a semiconductor device 10B according to one embodiment of the present invention
  • FIG 8B is a cross-sectional view taken along dashed line A1-A2 in FIG 8A
  • FIG 8C is a cross-sectional view taken along dashed line B1-B2 in FIG 8A.
  • the semiconductor device 10B has a transistor 100, a transistor 200B, a capacitance element 150A, and an insulating layer 110.
  • the transistor 200B differs mainly from the transistor 200 shown in FIG. 1C etc. in that a conductive layer 202 is provided between the insulating layer 110 and the substrate 102.
  • the capacitance element 150A differs mainly from the capacitance element 150 in that the capacitance element 150A has an insulating layer 110 instead of the insulating layer 120.
  • the conductive layer 202 is provided on the substrate 102.
  • the conductive layer 202 can be formed in the same process as the conductive layer 112a.
  • the conductive layer 202 and the conductive layer 112a can be formed by forming a film that will become the conductive layer 202 and the conductive layer 112a, and processing the film.
  • the productivity of the semiconductor device 10B can be increased and the manufacturing cost can be reduced.
  • insulating layer 110 and a portion of insulating layer 120 function as a backgate insulating layer (second gate insulating layer).
  • the capacitor 150A has a conductive layer 112b and a conductive layer 202 that function as a pair of electrodes, and an insulating layer 110 sandwiched between them.
  • FIG. 8C and other figures show a configuration in which the insulating layer 120 is not provided between the conductive layer 112a and the insulating layer 110, one embodiment of the present invention is not limited to this.
  • the insulating layer 120 may be provided between the conductive layer 112a and the insulating layer 110, and the insulating layer 110 and the insulating layer 120 may function as a dielectric for the capacitor 150A.
  • configuration of the conductive layer 202 shown in configuration example 3 can also be applied to other configuration examples.
  • FIG. 9A is a top view of a semiconductor device 10C according to one embodiment of the present invention
  • FIG 9B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG 9A
  • FIG 9C is a cross-sectional view taken along dashed dotted line B1-B2 in FIG 9A.
  • the semiconductor device 10C includes a transistor 100, a transistor 200, a capacitance element 150B, and an insulating layer 110.
  • the capacitance element 150B differs from the capacitance element 150 shown in FIG. 1C etc. mainly in that it includes a conductive layer 112a instead of the conductive layer 112b, and an insulating layer 110 instead of the insulating layer 120.
  • the capacitor 150B has a conductive layer 112a and a conductive layer 202 that function as a pair of electrodes, and an insulating layer 110 sandwiched between them.
  • the conductive layer 112a functions as one of the source and drain electrodes of the transistor 100 and also functions as one of the pair of electrodes of the capacitor 150.
  • the conductive layer 202 may be formed in the same process using the same material as the conductive layer 112b.
  • the conductive layer 202 and the conductive layer 112b are given the same hatching pattern.
  • a film that will become the conductive layer 202 and the conductive layer 112b can be formed on the insulating layer 110, and the conductive layer 202 and the conductive layer 112b can be formed by processing the film.
  • the configuration of the capacitive element 150B shown in configuration example 4 can also be applied to other configuration examples.
  • FIG. 11A and 11B are cross-sectional views of a semiconductor device 10D according to one embodiment of the present invention.
  • FIG. 11A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A
  • FIG. 11B is a cross-sectional view of a cut surface taken along dashed line B1-B2 in FIG. 1A.
  • the semiconductor device 10D differs from the semiconductor device 10 shown in FIG. 1B etc. mainly in that it has insulating layers 110d and 110e.
  • FIG. 11C shows an enlarged view of the transistor 100 in FIG. 11A and its vicinity.
  • the insulating layer 110 has an insulating layer 110d between the conductive layer 112a and the insulating layer 110a, and an insulating layer 110e between the conductive layer 112b and the insulating layer 110c.
  • the insulating layer 110d and the insulating layer 110e can be made of the same material as can be used for the insulating layer 110a and the insulating layer 110c, respectively.
  • silicon nitride or silicon oxynitride can be suitably used for the insulating layer 110d and the insulating layer 110e, respectively.
  • the region of the semiconductor layer 108 in contact with the insulating layer 110d can be a low-resistance region.
  • the semiconductor layer 108 can be configured to have a low-resistance region between the region in contact with the conductive layer 112a (one of the source region and the drain region) and the channel formation region.
  • the region of the semiconductor layer 108 in contact with the insulating layer 110e can be configured to have a low-resistance region.
  • the semiconductor layer 108 can be configured to have a low-resistance region between the region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel formation region.
  • the low-resistance region can function as a buffer region for relaxing the drain electric field. Note that these low-resistance regions may function as source or drain regions.
  • the conductive layer 112a functions as a drain electrode and the conductive layer 112b functions as a source electrode
  • the region of the semiconductor layer 108 in contact with the insulating layer 110d into a low resistance region
  • a high electric field is unlikely to occur near the drain region, the generation of hot carriers is suppressed, and deterioration of the transistor can be suppressed.
  • the conductive layer 112a functions as a source electrode and the conductive layer 112b functions as a drain electrode, by making the region of the semiconductor layer 108 in contact with the insulating layer 110e into a low resistance region, a high electric field is unlikely to occur near the drain region, the generation of hot carriers is suppressed, and deterioration of the transistor can be suppressed.
  • the region of the semiconductor layer 108 in contact with the insulating layer 110d functions as a source region or a drain region
  • the distance from the source region of the semiconductor layer 108 to the gate electrode and the distance from the drain region to the gate electrode can be made more uniform. This makes it possible to make the electric field of the gate electrode applied to the channel formation region more uniform.
  • the insulating layer 110a located between the insulating layers 110d and 110b preferably emits a small amount of impurities and is difficult for impurities to penetrate. This makes it possible to prevent impurities from diffusing into the channel formation region of the semiconductor layer 108 and its vicinity through the insulating layers 110a and 110b, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.
  • insulating layer 110d has an area with a higher hydrogen content than insulating layer 110a.
  • the hydrogen content of insulating layer 110 can be analyzed using, for example, secondary ion mass spectrometry (SIMS).
  • the amount of hydrogen released can be adjusted by making the film formation conditions different between insulating layer 110d and insulating layer 110a. Specifically, one or more of the film formation power (film formation power density), film formation pressure, film formation gas type, film formation gas flow rate ratio, film formation temperature, and distance between the substrate and the electrode can be made different between insulating layer 110d and insulating layer 110a. For example, by making the film formation power density of insulating layer 110d smaller than the film formation power density of insulating layer 110a, the hydrogen content in insulating layer 110d can be made larger than the hydrogen content in insulating layer 110a. This makes it possible to increase the amount of hydrogen released from insulating layer 110d itself due to heat applied to it.
  • the deposition gas used to form the insulating layer 110d preferably contains more hydrogen than the deposition gas used to form the insulating layer 110a.
  • the ratio of the flow rate of ammonia gas to the total deposition gas used to form the insulating layer 110d (hereinafter also referred to as the ammonia flow rate ratio) is preferably higher than the ammonia flow rate ratio of the deposition gas used to form the insulating layer 110a.
  • the hydrogen content in the insulating layer 110d can be increased.
  • the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d can be increased. It is not necessary to use ammonia gas to form the insulating layer 110d and ammonia gas to form the insulating layer 110a. In particular, when the channel length L100 is short (for example, 100 nm or less) or when a material with high conductivity is used for the semiconductor layer 108, it is not necessary to use ammonia gas to form the insulating layer 110a.
  • the amount of hydrogen released from the insulating layer 110a increases, the effect on the electrical characteristics may become greater.
  • the amount of hydrogen in the insulating layer 110a can be reduced, resulting in a transistor with good electrical characteristics.
  • the film density of the insulating layer 110a is preferably higher than that of the insulating layer 110d. This can prevent hydrogen contained in the insulating layer 110d from diffusing into the channel formation region of the semiconductor layer 108 and its vicinity through the insulating layers 110a and 110b.
  • the film density can be evaluated, for example, by Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity Measurement (XRR).
  • RRS Rutherford Backscattering Spectrometry
  • XRR X-ray Reflectivity Measurement
  • the difference in film density can sometimes be evaluated by a cross-sectional transmission electron microscope (TEM) image. In TEM observation, if the film density is high, the transmission electron (TE) image will be dense (dark), and if the film density is low, the transmission electron (TE) image will be faint (bright).
  • the insulating layer 110a may appear dense (dark) compared to the insulating layer 110d. Even if the same material is used for the insulating layers 110d and 110a, the film densities are different, so the boundary between them may be observed as a difference in contrast in the cross-sectional TEM image.
  • the insulating layer 110c located between the insulating layers 110e and 110b preferably emits a small amount of impurities and is difficult for impurities to penetrate. This can prevent impurities from diffusing into the channel formation region of the semiconductor layer 108 and its vicinity through the insulating layers 110c and 110b, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.
  • the film density of the insulating layer 110c is preferably higher than that of the insulating layer 110e.
  • the insulating layer 110c refer to the description of the insulating layer 110a, and for the insulating layer 110e, refer to the description of the insulating layer 110d.
  • configuration of the insulating layer 110 shown in configuration example 5 can also be applied to other configuration examples.
  • FIG. 12A is a cross-sectional view of a transistor 100A that can be used in a semiconductor device according to one embodiment of the present invention.
  • a top view of the transistor 100A refer to the transistor 100 in FIG. 1A.
  • FIG. 12A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.
  • Transistor 100A differs from transistor 100 shown in FIG. 1B etc. mainly in that the thickness of the conductive layer 112a in the region that contacts the bottom surface of semiconductor layer 108 is different from the thickness of the region that does not contact semiconductor layer 108.
  • the thickness of the region of the conductive layer 112a that contacts the lower surface of the semiconductor layer 108 is preferably thinner than the thickness of the region that does not contact the semiconductor layer 108.
  • FIG. 12A shows the height H104 from the surface on which the conductive layer 112a is formed (here, the upper surface of the substrate 102) to the lowest position of the lower surface of the conductive layer 104. Also shown is the height H112 from the surface on which the conductive layer 112a is formed (here, the upper surface of the substrate 102) to the highest position of the region where the conductive layer 112a and the semiconductor layer 108 contact.
  • the height H104 is preferably the same as or approximately the same as the height H112. Alternatively, as shown in FIG. 12B, the height H104 is preferably lower than the height H112.
  • the electric field of the gate electrode applied to the channel formation region near the conductive layer 112a can be strengthened, and the on-current of the transistor 100A can be increased.
  • the electric field of the gate electrode applied to the channel formation region can be made more uniform.
  • the electrical characteristics when the conductive layer 112a is the source electrode and the conductive layer 112b is the drain electrode may differ from the electrical characteristics when the conductive layer 112a is the drain electrode and the conductive layer 112b is the source electrode.
  • the transistor 100A can be suitably used in a circuit configuration in which the source and drain are interchanged.
  • the thickness of the conductive layer 112a can be adjusted appropriately so that the height H104 is equal to or lower than the height H112.
  • configuration of the conductive layer 112a shown in configuration example 6 can also be applied to other configuration examples.
  • FIGA is a top view of a semiconductor device 10E according to one embodiment of the present invention
  • FIG 13B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG 13A
  • FIG 13C is a cross-sectional view taken along dashed dotted line B1-B2 in FIG 13A.
  • the semiconductor device 10E includes a transistor 100B, a transistor 200, a capacitor 150, and an insulating layer 110.
  • the transistor 100B differs from the transistor 100 shown in FIG. 1B etc. mainly in that the transistor 100B includes a conductive layer 103 and an insulating layer 107 between the conductive layer 112a and the insulating layer 110.
  • the insulating layer 107 is located on the conductive layer 112a.
  • the insulating layer 107 is provided so as to cover the upper and side surfaces of the conductive layer 112a.
  • the conductive layer 103 is located on the insulating layer 107.
  • the conductive layer 112a and the conductive layer 103 are electrically insulated from each other by the insulating layer 107.
  • the conductive layer 103 has an opening 148 that reaches the insulating layer 107 in the area that overlaps with the conductive layer 112a.
  • the insulating layer 110 is provided on the insulating layer 107 and the conductive layer 103.
  • the insulating layer 110 is provided so as to cover the upper and side surfaces of the conductive layer 103 and the upper surface of the insulating layer 107.
  • the insulating layer 110 and the insulating layer 107 are provided with an opening 141 that reaches the conductive layer 112a.
  • the insulating layer 110a is located on the insulating layer 107 and the conductive layer 103.
  • the insulating layer 110a is provided so as to cover the upper and side surfaces of the conductive layer 103.
  • the insulating layer 110a is also provided so as to cover a portion of the opening 148.
  • the insulating layer 110a contacts the insulating layer 107 through the opening 148.
  • the top surface shape of opening 148 is not particularly limited.
  • the top surface shape of opening 148 can be a shape that can be applied to opening 141. As shown in FIG. 13A, it is preferable that the top surface shapes of openings 141 and 148 are each circular. By making the top surface shapes of the openings circular, the processing accuracy when forming the openings can be improved, and openings of fine size can be formed.
  • the top surface shape of the opening 148 refers to the shape of the top surface end or bottom surface end of the conductive layer 103 on the opening 148 side.
  • opening 141 and opening 148 are preferably concentric. This allows the shortest distance between semiconductor layer 108 and conductive layer 103 in a cross-sectional view to be equal on the left and right sides of opening 141. Also, opening 141 and opening 148 may not be concentric.
  • transistor 100B there is a region in semiconductor layer 108 that overlaps with conductive layer 104 via insulating layer 106, and also overlaps with conductive layer 103 via a portion of insulating layer 110 (particularly insulating layer 110a and insulating layer 110b). In other words, there is a region in semiconductor layer 108 that is sandwiched between conductive layer 104 via insulating layer 106, and conductive layer 103 via a portion of insulating layer 110 (particularly insulating layer 110a and insulating layer 110b).
  • the conductive layer 103 functions as a back gate electrode (also referred to as a second gate electrode) of the transistor 100B.
  • a part of the insulating layer 110 functions as a back gate insulating layer (also referred to as a second gate insulating layer) of the transistor 100B.
  • the conductive layer 103 can be made of the same material as can be used for the conductive layer 112a and the conductive layer 104. Note that the conductive layer 103 does not necessarily have to be provided.
  • the potential on the backgate electrode side (also called the backchannel side) of the semiconductor layer 108 is fixed, and the saturation of the Id-Vd characteristics can be improved.
  • the transistor 100B has a back gate electrode, the potential on the back gate electrode side of the semiconductor layer 108 can be fixed, and a shift in the threshold voltage can be suppressed.
  • the threshold voltage of the transistor shifts, the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may become large.
  • cutoff current the drain current that flows when the gate voltage is 0 V may become large.
  • the insulating layer 107 can be formed using a material that can be used for the insulating layer 110.
  • the insulating layer 107 in contact with the conductive layer 112a and the conductive layer 103 is preferably formed using an insulating layer containing nitrogen.
  • the insulating layer 107 can be preferably formed using a material that can be used for the insulating layer 110a and the insulating layer 110c.
  • the insulating layer 107 can be preferably formed using, for example, silicon nitride. Note that in this embodiment, the insulating layer 107 has a single-layer structure; however, one embodiment of the present invention is not limited to this.
  • the insulating layer 107 may be formed using a stacked structure of two or more layers.
  • the conductive layer 103 may be electrically connected to the conductive layer 112a.
  • an opening may be provided in a region of the insulating layer 107 that overlaps with the conductive layer 112a, and the conductive layer 103 may be provided to cover the opening, so that the conductive layer 103 and the conductive layer 112a are in contact with each other.
  • the conductive layer 112a that functions as a source electrode or drain electrode and the conductive layer 103 that functions as a backgate electrode are electrically connected to each other, so that the source electrode or drain electrode and the backgate electrode can have the same potential.
  • the conductive layer 112a functions as a source electrode
  • a shift in the threshold voltage of the transistor 100B can be suppressed.
  • the reliability of the transistor 100B can be improved.
  • the conductive layer 103 may be formed in contact with the upper surface of the conductive layer 112a without providing the insulating layer 107.
  • the conductive layer 103 may be electrically connected to the conductive layer 104.
  • an opening may be provided in an area of the insulating layer 106 and the insulating layer 110 that overlaps with the conductive layer 103, and the conductive layer 104 may be provided to cover the opening, thereby making it possible to configure the conductive layer 103 and the conductive layer 104 in contact with each other.
  • the backgate electrode and the gate electrode can be at the same potential, and the on-current of the transistor 100B can be increased.
  • the thickness of the conductive layer 103 may be greater than the thickness T110b of the insulating layer 110. This allows the potential on the back gate electrode side of the semiconductor layer 108 to be fixed over a wide range between the source region and the drain region in the semiconductor layer 108.
  • Transistor 100B has a region in which conductive layer 103, insulating layer 110, semiconductor layer 108, insulating layer 106, and conductive layer 104 overlap in this order in one direction without any other layers in between.
  • This direction is a direction perpendicular to the channel length direction.
  • the thickness of the conductive layer 103 can be greater than the sum of the thickness of the portion of the semiconductor layer 108 that contacts the conductive layer 112a inside the opening 141 and the thickness of the insulating layer 106 that contacts that portion.
  • configuration of the conductive layer 103 and insulating layer 107 shown in configuration example 7 can also be applied to other configuration examples.
  • ⁇ Configuration Example 8> 14A illustrates an equivalent circuit diagram of a transistor 100C that can be used in a semiconductor device of one embodiment of the present invention.
  • the transistor 100C is a group of transistors including transistors 100_1 to 100_p (p is an integer of 2 or more).
  • the transistors 100_1 to 100_p are connected in parallel, and the transistor 100C can be regarded as one transistor.
  • the gate electrodes of transistors 100_1 to 100_p are electrically connected to each other.
  • the source electrodes of transistors 100_1 to 100_p are electrically connected to each other.
  • the drain electrodes of transistors 100_1 to 100_p are electrically connected to each other.
  • FIG. 14A illustrates the transistors 100_1 to 100_p as n-channel transistors, one embodiment of the present invention is not limited to this.
  • the transistors 100_1 to 100_p may be p-channel transistors.
  • FIG. 14B shows an equivalent circuit diagram of a transistor 100C according to one embodiment of the present invention.
  • FIG. 14C shows a top view of the transistor 100C.
  • FIG. 15 shows a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 14C.
  • FIG. 16 shows a perspective view of the transistor 100C.
  • Transistor 100C includes transistors 100_1 to 100_4.
  • the structure of the transistor 100 described above can be applied to each of transistors 100_1 to 100_4. Note that although the transistor 100 is described here as an example, one embodiment of the present invention is not limited thereto. Any of transistors 100A to 100D may be applied to transistors 100_1 to 100_4.
  • the transistors 100_1 to 100_4 are arranged in two rows and two columns, but the arrangement of the transistors is not particularly limited.
  • the transistors 100_1 to 100_4 may be arranged in one row and four columns.
  • the transistors may or may not be arranged in a matrix.
  • Transistors 100_1 to 100_4 each have a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b.
  • the conductive layer 104 functions as a gate electrode of transistors 100_1 to 100_4.
  • a part of the insulating layer 106 functions as a gate insulating layer of transistors 100_1 to 100_4.
  • the conductive layer 112a functions as the other of the source and drain electrodes of transistors 100_1 to 100_4, and the conductive layer 112b functions as one of the source and drain electrodes.
  • FIG. 17A is a perspective view showing conductive layer 112a.
  • FIG. 17B is a perspective view showing the conductive layer 112a, the conductive layer 112b, the openings 141_1 to 141_4, and the openings 143_1 to 143_4. Note that the openings 141_1 to 141_4 provided in the insulating layer 110 are shown by dashed lines. The description of the openings 141 and 143 can be referred to for the openings 141_1 to 141_4 and the openings 143_1 to 143_4, and therefore detailed description thereof will be omitted.
  • the channel width of the transistor is the sum of the channel widths of the transistors 100_1 to 100_4.
  • the transistor 100C can be regarded as a transistor having a channel width of "D141 x ⁇ x 4" (see Figures 4A and 4B).
  • the transistor 100C which is composed of p transistors, can be regarded as a transistor having a channel width of "D141 x ⁇ x p". Note that the transistor 100C can be regarded as a transistor having a channel length L100 (see Figure 4B).
  • the channel width can be increased, and the on-current can be increased.
  • the channel width can be varied by adjusting the number (p) of transistors connected in parallel. The number (p) of transistors connected in parallel can be determined so as to obtain a desired on-current.
  • FIG. 17C is a perspective view showing the conductive layer 112a and the semiconductor layer 108.
  • the semiconductor layer 108 is provided to cover the openings 141_1 to 141_4 and the openings 143_1 to 143_4. Note that although FIG. 17C and other drawings show a structure in which the transistors 100_1 to 100_4 share the semiconductor layer 108, one embodiment of the present invention is not limited to this.
  • the semiconductor layer 108 may be separate for each of the transistors 100_1 to 100_4.
  • 17D is a perspective view showing the conductive layer 112a and the conductive layer 104.
  • the conductive layer 104 is provided so as to cover the openings 141_1 to 141_4 and the openings 143_1 to 143_4.
  • the configuration of the transistor 100C shown in configuration example 8 can also be applied to other configuration examples.
  • the transistor 100C may be applied to one or more of the transistors included in the semiconductor device shown in Figures 1 to 13.
  • ⁇ Configuration Example 9> 18A illustrates an equivalent circuit diagram of a transistor 100D that can be used in a semiconductor device of one embodiment of the present invention.
  • the transistor 100D is a group of transistors including transistors 100_1 to 100_q (q is an integer of 2 or more).
  • the transistors 100_1 to 100_q are connected in series, and the transistor 100D can be regarded as one transistor.
  • FIG. 18A illustrates the transistors 100_1 to 100_q as n-channel transistors, one embodiment of the present invention is not limited to this.
  • the transistors 100_1 to 100_q may be p-channel transistors.
  • FIG. 18B shows an equivalent circuit diagram of a transistor 100D according to one embodiment of the present invention.
  • FIG. 18C shows a top view of the transistor 100D.
  • FIG. 19 shows a cross-sectional view taken along dashed dotted line A5-A6 in FIG. 18C.
  • FIG. 20 shows a perspective view of the transistor 100D.
  • Transistor 100D includes transistors 100_1 to 100_4.
  • the structure of transistor 100 described above can be applied to each of transistors 100_1 to 100_4. Note that although transistor 100 is described here as an example, one embodiment of the present invention is not limited thereto. Any of transistors 100A to 100D may be applied to transistors 100_1 to 100_4.
  • the transistors 100_1 to 100_4 are arranged in two rows and two columns, but the arrangement of the transistors is not particularly limited.
  • the transistors 100_1 to 100_4 may be arranged in one row and four columns.
  • the transistors may or may not be arranged in a matrix.
  • Transistor 100_1 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a, and a conductive layer 112b.
  • the conductive layer 112a functions as one of the source electrode and drain electrode of transistor 100_1, and the conductive layer 112b functions as the other.
  • Transistor 100_2 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108_2, a conductive layer 112a, and a conductive layer 112c.
  • the conductive layer 112a functions as one of a source electrode and a drain electrode of transistor 100_2, and the conductive layer 112c functions as the other.
  • the conductive layer 112a is shared by transistors 100_1 and 100_2.
  • Transistor 100_3 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108_3, a conductive layer 112c, and a conductive layer 112d.
  • the conductive layer 112c functions as one of a source electrode and a drain electrode of transistor 100_3, and the conductive layer 112d functions as the other.
  • the conductive layer 112c is shared by transistors 100_2 and 100_3.
  • Transistor 100_4 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108_4, a conductive layer 112d, and a conductive layer 112e.
  • the conductive layer 112d functions as one of a source electrode and a drain electrode of transistor 100_4, and the conductive layer 112e functions as the other.
  • the conductive layer 112d is shared by transistors 100_3 and 100_4.
  • FIG. 21A is a perspective view showing conductive layer 112a and conductive layer 112d. Conductive layer 112a and conductive layer 112d can be formed in the same process.
  • 21B is a perspective view showing conductive layer 112a, conductive layer 112b, conductive layer 112c, conductive layer 112d, conductive layer 112e, openings 141_1 to 141_4, and openings 143_1 to 143_4.
  • Conductive layers 112a to 112e can be formed in the same process.
  • An opening 143_1 is provided in conductive layer 112b
  • openings 143_2 and 143_3 are provided in conductive layer 112c
  • opening 143_4 is provided in conductive layer 112e.
  • FIG. 21C is a perspective view showing the conductive layer 112a, the conductive layer 112d, and the semiconductor layers 108_1 to 108_4.
  • the semiconductor layers 108_1 to 108_4 can be formed in the same process.
  • 21D is a perspective view showing the conductive layer 112a, the conductive layer 112d, and the conductive layer 104.
  • the conductive layer 104 functions as the gate electrode of the transistors 100_1 to 100_4.
  • One of the source electrode and drain electrode of transistor 100_1 is electrically connected to one of the source electrode and drain electrode of transistor 100_2.
  • the other of the source electrode and drain electrode of transistor 100_2 is electrically connected to one of the source electrode and drain electrode of transistor 100_3.
  • the other of the source electrode and drain electrode of transistor 100_3 is electrically connected to one of the source electrode and drain electrode of transistor 100_4.
  • the channel length of the transistor is the sum of the channel lengths of the transistors 100_1 to 100_4.
  • the transistor 100D can be regarded as a transistor with a channel length of "L100 x 4" (see FIG. 4B).
  • the transistor 100D which is composed of q transistors, can be regarded as a transistor with a channel length of "L100 x q".
  • the transistor 100D can be regarded as a transistor with a channel width of W100 (see FIGS. 4A and 4B).
  • the channel length can be made different by adjusting the number (q) of transistors connected in series.
  • the number (q) of transistors connected in series can be determined so as to achieve the desired saturation.
  • the configuration of the transistor 100D shown in configuration example 9 can also be applied to other configuration examples.
  • the transistor 100D may be applied to one or more of the transistors included in the semiconductor device shown in Figures 1 to 13.
  • Transistor 100D may be applied to each transistor in transistor 100C.
  • a configuration can be created in which a group of transistors connected in parallel are further connected in series (hereinafter also referred to as series-parallel connection).
  • Embodiment 2 a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described with reference to Fig. 22A to Fig. 26B. Note that with regard to materials and formation methods of elements, description of the same parts as those described in Embodiment 1 may be omitted.
  • 22A to 26B show a cross-sectional view between dashed dotted lines A1-A2 and B1-B2 shown in FIG. 1A.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), and ALD.
  • CVD methods include PECVD and thermal CVD.
  • One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • the thin film When processing the thin film that constitutes the semiconductor device, a photolithography method or the like can be used.
  • the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method, or the like.
  • island-shaped thin films may be directly formed using a film formation method that uses a shielding mask such as a metal mask.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these.
  • ultraviolet light, KrF laser light, ArF laser light, etc. can also be used.
  • Exposure can also be performed by immersion exposure technology.
  • Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure.
  • Electron beams can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.
  • etching the thin film one or more of the following methods can be used: dry etching, wet etching, and sandblasting.
  • a film that will become the conductive layer 112a is formed on the substrate 102, and then the film is processed to form the conductive layer 112a.
  • the film can be preferably formed by a sputtering method.
  • an insulating film 110af that will become the insulating layer 110a, and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 112a ( Figure 22A).
  • the insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to continuously form the insulating film 110bf in a vacuum without exposing the surface of the insulating film 110af to the atmosphere. By continuously forming the insulating films 110af and 110bf, it is possible to prevent impurities derived from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic matter.
  • the amount of oxygen released from the insulating layer 110b is large. Furthermore, it is preferable that the diffusion coefficient of the substance (particularly oxygen) in the insulating layer 110b is large.
  • the F ratio is set to the above-mentioned range. This makes it easier for oxygen to diffuse in the insulating layer 110b, and the oxygen contained in the insulating layer 110b can be efficiently supplied to the semiconductor layer 108 (particularly the channel formation region), while reducing the amount of impurities released from the insulating layer 110b.
  • the substrate temperature during the formation of the insulating film 110af and the insulating film 110bf is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 450°C or lower, even more preferably 300°C or higher and 450°C or lower, even more preferably 300°C or higher and 400°C or lower, even more preferably 350°C or higher and 400°C or lower.
  • the substrate temperature during the formation of the insulating film 110af and the insulating film 110bf within the above-mentioned range, it is possible to reduce the release of impurities (e.g., water and hydrogen) from the insulating film 110af and the insulating film 110bf, and to suppress the diffusion of impurities into the semiconductor layer 108. Therefore, it is possible to obtain a transistor that exhibits good electrical characteristics and is highly reliable.
  • impurities e.g., water and hydrogen
  • the insulating films 110af and 110bf are formed before the semiconductor layers 108 and 208, there is no need to worry about oxygen being desorbed from the semiconductor layers 108 and 208 due to the heat applied during the formation of the insulating films 110af and 110bf.
  • oxygen may be supplied to the insulating film 110bf.
  • an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used as a method for supplying oxygen.
  • an apparatus that converts oxygen gas into plasma by high-frequency power can be suitably used.
  • a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus can be given as an apparatus that converts gas into plasma by high-frequency power.
  • the plasma treatment is preferably performed in an atmosphere containing oxygen.
  • the plasma treatment is preferably performed in an atmosphere containing one or more of oxygen, nitrous oxide (N 2 O), nitrogen dioxide (NO 2 ), carbon monoxide, and carbon dioxide.
  • the plasma treatment may be performed continuously in a vacuum without exposing the surface of the insulating film 110bf to the atmosphere.
  • a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can increase productivity.
  • an N 2 O plasma treatment can be performed continuously in a vacuum.
  • a metal oxide layer 137 on the insulating film 110bf ( Figure 22B). By forming the metal oxide layer 137, oxygen can be supplied to the insulating film 110bf.
  • the conductivity of the metal oxide layer 137 does not matter.
  • At least one of an insulating film, a semiconductor film, and a conductive film can be used as the metal oxide layer 137.
  • aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO) can be used as the metal oxide layer 137.
  • the metal oxide layer 137 it is preferable to use an oxide material that contains one or more of the same elements as the semiconductor layer 108 and the semiconductor layer 208. In particular, it is preferable to use a metal oxide material that can be applied to the semiconductor layer 108 and the semiconductor layer 208.
  • the oxygen flow ratio or oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% or more and 100% or less, more preferably 80% or more and 100% or less, and even more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow ratio to 100% and the oxygen partial pressure as close to 100% as possible.
  • oxygen can be supplied to the insulating film 110bf during the formation of the metal oxide layer 137, and oxygen can be prevented from being released from the insulating film 110bf.
  • a large amount of oxygen can be trapped in the insulating film 110bf.
  • a large amount of oxygen can be supplied to the semiconductor layer 108 by subsequent heat treatment.
  • oxygen vacancies and VOH in the semiconductor layer 108 can be reduced, and a transistor with good electrical characteristics and high reliability can be obtained.
  • a heat treatment may be performed. By performing a heat treatment after forming the metal oxide layer 137, oxygen can be effectively supplied from the metal oxide layer 137 to the insulating film 110bf.
  • the temperature of the heat treatment is preferably 150°C or more, 200°C or more, 230°C or more, or 250°C or more, and is less than the distortion point of the substrate, 450°C or less, 400°C or less, 350°C or less, or 300°C or less.
  • the heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen.
  • a noble gas nitrogen, or oxygen.
  • dry air CODA: Clean Dry Air
  • It is preferable that the content of hydrogen, water, and the like in the atmosphere is as small as possible.
  • As the atmosphere it is preferable to use a high-purity gas with a dew point of -60°C or less, preferably -100°C or less.
  • an atmosphere containing as little hydrogen, water, and the like it is possible to prevent hydrogen, water, and the like from being taken into the insulating film 110af and the insulating film 110bf as much as possible.
  • an oven a rapid heating (RTA: Rapid Thermal Annealing) device, and the like can be used. Using an RTA device can shorten the heating process time.
  • RTA Rapid Thermal Annealing
  • oxygen may be further supplied to the insulating film 110bf through the metal oxide layer 137.
  • a method for supplying oxygen for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used.
  • the plasma treatment the above description can be referred to, and therefore a detailed description will be omitted.
  • the metal oxide layer 137 is removed.
  • a wet etching method can be preferably used. By using the wet etching method, etching of the insulating film 110bf can be suppressed when removing the metal oxide layer 137. This can suppress the thickness of the insulating film 110bf from becoming thin, and the thickness of the insulating layer 110b can be made uniform.
  • oxygen may be further supplied to the insulating film 110bf.
  • the above description can be referred to for the method of supplying oxygen.
  • a film 139 may be formed on the insulating film 110bf, and oxygen may be supplied to the insulating film 110bf through the film 139.
  • a plasma treatment in an atmosphere containing oxygen can be used.
  • FIG. 22C shows a schematic diagram with arrows showing the state in which oxygen is supplied to the insulating film 110bf.
  • the film 139 is preferably a conductive film or a semiconductor film.
  • the film 139 can be a metal oxide film, a metal film, or an alloy film. It is preferable to use a metal oxide as the film 139 and form it by a sputtering method or the like in an atmosphere containing oxygen, because oxygen can be supplied to the insulating film 110bf even during the formation of the film 139.
  • the thickness of film 139 is preferably thin. Specifically, the thickness of film 139 is preferably 1 nm or more, 2 nm or more, or 3 nm or more, and 20 nm or less, 15 nm or less, or 10 nm or less. Typically, the thickness can be about 5 nm.
  • the substrate temperature during the formation of film 139 is preferably 350°C or less, more preferably 340°C or less, even more preferably 330°C or less, and even more preferably 300°C or less. This allows a large amount of oxygen to be supplied to insulating film 110bf.
  • a dry etching apparatus As the processing apparatus for supplying oxygen, a dry etching apparatus, an ashing apparatus, or a PECVD apparatus can be suitably used. In particular, it is preferable to use an ashing apparatus.
  • the bias voltage When a bias voltage is applied between a pair of electrodes of the processing apparatus, the bias voltage may be set to, for example, 10 V or more and 1 kV or less. Alternatively, the power density of the bias may be set to, for example, 1 W/cm 2 or more and 5 W/cm 2 or less.
  • a wet etching method can be suitably used to remove the film 139.
  • the process of supplying oxygen to the insulating film 110bf is not limited to the above-mentioned method.
  • oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions may be supplied to the insulating film 110bf by ion doping, ion implantation, or plasma treatment.
  • a film that suppresses oxygen desorption may be formed on the insulating film 110bf, and then oxygen may be supplied to the insulating film 110bf through the film. The film is preferably removed after oxygen is supplied.
  • a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.
  • the amount of oxygen released from the insulating layer 110b in contact with the channel formation region of the transistor 100 having a short channel length is large compared to the insulating layer 120b in contact with the channel formation region of the transistor 200 having a long channel length.
  • insulating film 110cf which will become insulating layer 110c, is formed on insulating film 110bf (FIG. 22D).
  • the description of the formation of insulating film 110af and insulating film 110bf can be referenced for the formation of insulating film 110cf, so a detailed description will be omitted.
  • a film that will become the conductive layer 202 is formed on the insulating film 110cf, and the film is processed to form the conductive layer 202 ( Figure 23A).
  • the film can be preferably formed by a sputtering method.
  • insulating film 120af which will become insulating layer 120a
  • insulating film 120bf which will become insulating layer 120b
  • the insulating films 120af and 120bf can be preferably formed by sputtering or PECVD. After forming the insulating film 120af, it is preferable to continuously form the insulating film 120bf in a vacuum without exposing the surface of the insulating film 120af to the atmosphere. By continuously forming the insulating films 120af and 120bf, it is possible to prevent impurities from the atmosphere from adhering to the surface of the insulating film 120af. Examples of such impurities include water and organic matter.
  • the amount of oxygen released from insulating layer 120b may be smaller than the amount of oxygen released from insulating layer 110b.
  • the diffusion coefficient of oxygen in insulating layer 120b may be smaller than the diffusion coefficient of oxygen in insulating layer 110b.
  • the substrate temperature during the formation of the insulating film 120af and the insulating film 120bf is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 450°C or lower, even more preferably 300°C or higher and 450°C or lower, even more preferably 300°C or higher and 400°C or lower, even more preferably 350°C or higher and 400°C or lower.
  • the substrate temperature during the formation of the insulating film 120af and the insulating film 120bf within the above-mentioned range, it is possible to reduce the release of impurities (e.g., water and hydrogen) from the insulating film 120af and the insulating film 120bf, and to suppress the diffusion of impurities into the semiconductor layer 108. Therefore, it is possible to obtain a transistor that exhibits good electrical characteristics and is highly reliable.
  • impurities e.g., water and hydrogen
  • the insulating films 120af and 120bf are formed before the semiconductor layers 108 and 208, there is no need to worry about oxygen being desorbed from the semiconductor layers 108 and 208 due to the heat applied during the formation of the insulating films 120af and 120bf.
  • oxygen may be supplied to the insulating film 120bf.
  • oxygen For the method of supplying oxygen, see the above description.
  • the insulating film 120af and the insulating film 120bf are processed to form the insulating layer 120 having the insulating layer 120a and the insulating layer 120b.
  • the dry etching method can be suitably used to process the insulating film 120af and the insulating film 120bf.
  • a conductive film 112bf that will become the conductive layer 112b is formed on the insulating film 110cf and the insulating layer 120 (FIG. 23C).
  • the conductive film 112bf can be formed, for example, by a sputtering method.
  • the conductive film 112bf is processed to form the conductive layer 112B (FIG. 24A).
  • the conductive layer 112B will later become the conductive layer 112b.
  • the conductive layer 112B can be preferably formed by, for example, wet etching.
  • a portion of the conductive layer 112B is removed to form a conductive layer 112b having an opening 143.
  • the conductive layer 112b can be formed, for example, by a wet etching method.
  • the insulating films 110af, 110bf, and 110cf are partially removed to form the insulating layer 110 having an opening 141 (FIG. 24B).
  • the opening 141 is provided in a region overlapping with the opening 143.
  • the conductive layer 112a is exposed by forming the opening 141.
  • the insulating layer 110 can be preferably formed by, for example, a dry etching method.
  • the opening 141 can be formed, for example, by using the resist mask used to form the opening 143. Specifically, a resist mask is formed on the conductive layer 112B, a part of the conductive layer 112B is removed using the resist mask to form the opening 143, and the insulating film 110af, the insulating film 110bf, and the insulating film 110cf are removed using the resist mask to form the opening 141.
  • the opening 141 may be formed by using a resist mask different from the resist mask used to form the opening 143.
  • the opening 141 when forming the opening 141 or after forming the opening 141, a part of the conductive layer 112a in the area overlapping the opening 141 may be removed.
  • the thickness of the area of the conductive layer 112a in contact with the bottom surface of the semiconductor layer 108 thinner than the thickness of the area not in contact with the semiconductor layer 108, the electric field of the gate electrode applied to the channel formation area near the conductive layer 112a can be strengthened, and the on-current of the transistor can be increased.
  • metal oxide film 108f which will become semiconductor layer 108 and semiconductor layer 208, is formed so as to cover openings 141 and 143 (FIG. 24C).
  • Metal oxide film 108f is provided in contact with the upper surface and side surfaces of insulating layer 110, the upper surface of conductive layer 112a, the upper surface and side surfaces of conductive layer 112b, and the upper surface and side surfaces of insulating layer 120.
  • the metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target.
  • the metal oxide film 108f is preferably formed by an ALD method.
  • the ALD method has high coverage and can be suitably used to form the metal oxide film 108f that covers the openings 141 and 143.
  • a metal oxide film can be formed with high coverage on the side surfaces of the insulating layer 110.
  • the ALD method makes it easy to control the film formation speed, so a thin film can be formed with good yield.
  • the metal oxide film 108f is preferably a dense film with as few defects as possible.
  • the metal oxide film 108f is preferably a high-purity film with as few impurities, including hydrogen, as possible reduced.
  • oxygen gas oxygen can be suitably supplied to the insulating layer 110 and the insulating layer 120.
  • oxygen gas oxygen can be suitably supplied to the insulating layer 110b.
  • oxygen can be suitably supplied to the insulating layer 120b.
  • oxygen By supplying oxygen to the insulating layer 110b, oxygen can be supplied to the channel formation region of the semiconductor layer 108 in a later step, and oxygen vacancies and VOH in the channel formation region can be reduced.
  • oxygen vacancies and VOH in the channel formation region can be reduced.
  • oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.).
  • an inert gas e.g., helium gas, argon gas, xenon gas, etc.
  • the lower the oxygen flow rate ratio or the oxygen partial pressure the lower the crystallinity and the higher the electrical conductivity of the metal oxide film, and the higher the on-current of the transistor can be.
  • the metal oxide film may become polycrystalline.
  • the grain boundaries become the recombination center, and carriers may be captured, resulting in a small on-current of the transistor. Therefore, it is preferable to adjust the oxygen flow ratio or oxygen partial pressure so that the metal oxide film 108f does not become polycrystalline. Since the ease with which the metal oxide film becomes polycrystalline differs depending on the composition of the metal oxide film, the oxygen flow ratio or oxygen partial pressure can be adjusted according to the composition of the metal oxide film 108f.
  • the higher the substrate temperature when forming the metal oxide film the higher the crystallinity and the denser the metal oxide film will be.
  • the lower the substrate temperature the lower the crystallinity and the higher the electrical conductivity of the metal oxide film will be.
  • the substrate temperature during the formation of the metal oxide film 108f is preferably from room temperature to 250°C, more preferably from room temperature to 200°C, and even more preferably from room temperature to 140°C.
  • a substrate temperature of from room temperature to 140°C is preferable because it increases productivity.
  • the crystallinity can be reduced.
  • the metal oxide film may become polycrystalline. It is preferable to adjust the substrate temperature so that the metal oxide film 108f does not become polycrystalline.
  • the substrate temperature can be adjusted according to the composition to be applied to the metal oxide film 108f.
  • the ALD method it is preferable to use a film formation method such as thermal ALD or PEALD (Plasma Enhanced ALD).
  • a film formation method such as thermal ALD or PEALD (Plasma Enhanced ALD).
  • the thermal ALD method is preferable because it shows extremely high coating properties.
  • the PEALD method is preferable because it shows high coating properties and allows low-temperature film formation.
  • the metal oxide film can be formed, for example, by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.
  • three precursors can be used: a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.
  • two precursors can be used: a precursor containing indium, and a precursor containing gallium and zinc.
  • precursors containing indium include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.
  • Gallium-containing precursors include, for example, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.
  • Examples of zinc-containing precursors include dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.
  • Oxidizing agents include, for example, ozone, oxygen, and water.
  • Methods for controlling the composition of the resulting film include adjusting one or more of the type of raw material gas, the flow rate ratio of the raw material gas, the time for which the raw material gas is flowed, and the order in which the raw material gas is flowed. By adjusting these, the composition of the metal oxide film 108f can be controlled. In addition, by adjusting these, a film whose composition changes continuously can be formed. The composition of the metal oxide film 108f may be configured to change continuously.
  • a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surfaces of the insulating layer 110 and the insulating layer 120 and a treatment for supplying oxygen into the insulating layer 110 For example, a heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, a plasma treatment in an atmosphere containing oxygen may be performed. Alternatively, oxygen may be supplied to the insulating layer 110 by a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N 2 O).
  • N 2 O nitrous oxide
  • oxygen can be supplied while the organic substances on the surface of the insulating layer 110 are suitably removed. After such a treatment, it is preferable to continuously form the metal oxide film 108f without exposing the surface of the insulating layer 110 to the air.
  • the semiconductor layer 108 and the semiconductor layer 208 have a laminated structure, it is preferable to deposit the next metal oxide film in succession after depositing the first metal oxide film without exposing the surface to the air.
  • all layers constituting the semiconductor layer 108 and the semiconductor layer 208 may be formed by the same film formation method (e.g., sputtering or ALD), or different film formation methods may be used for each layer.
  • the first metal oxide layer may be formed by sputtering
  • the second metal oxide layer may be formed by ALD.
  • the metal oxide film 108f is processed into an island shape to form the semiconductor layer 108 and the semiconductor layer 208 ( Figure 25A).
  • the semiconductor layer 108 and the semiconductor layer 208 can be preferably formed by wet etching. At this time, a part of the insulating layer 110 in an area that does not overlap with either the semiconductor layer 108 or the semiconductor layer 208 may be etched and become thinner. Note that, in etching the metal oxide film 108f, it is preferable to use a material with a high selectivity for the insulating layer 110c, which can prevent the insulating layer 110c from becoming thinner. The same applies to the insulating layer 120.
  • the heat treatment can remove hydrogen and water contained in the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 or adsorbed on the surface.
  • the heat treatment can also improve the film quality of the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 (e.g., defects are reduced or crystallinity is improved).
  • oxygen can also be supplied from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108. This can reduce oxygen vacancies (V O ) in the channel formation region.
  • the above description can be referred to for the heat treatment, and detailed description thereof will be omitted.
  • the heat treatment is not limited to this, and oxygen may also be supplied to the channel formation region in a step in which heat is applied after the formation of the metal oxide film 108f (for example, a step of forming the insulating layer 106).
  • this heat treatment does not have to be performed if it is not necessary. Also, instead of performing the heat treatment here, it may be performed in a later step. Also, a process in a later step in which heat is applied (e.g., a film formation step) may also serve as the heat treatment.
  • insulating film 106f which will become insulating layer 106, is formed to cover semiconductor layer 108, semiconductor layer 208, and insulating layer 110 (FIG. 25B).
  • PECVD or ALD can be suitably used to form insulating film 106f.
  • the insulating layer 106 When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion.
  • the insulating layer 106 has a function of suppressing oxygen diffusion, which suppresses oxygen contained in the semiconductor layer 108 and the semiconductor layer 208 from diffusing above the insulating layer 106, and can suppress an increase in oxygen vacancies ( VO ) in the semiconductor layer 108 and the semiconductor layer 208. As a result, a transistor having favorable electrical characteristics and high reliability can be obtained.
  • a barrier film refers to a film that has barrier properties.
  • an insulating layer that has barrier properties can be called a barrier insulating layer.
  • barrier properties refer to one or both of the function of suppressing the diffusion of a target substance (also called low permeability) and the function of capturing or fixing the substance (also called gettering).
  • the substrate temperature during the formation of the insulating film 106f is preferably 180° C. to 450° C., more preferably 200° C. to 450° C., more preferably 250° C. to 450° C., even more preferably 300° C. to 450° C., and even more preferably 300° C. to 400° C.
  • the substrate temperature during the formation of the insulating film 106f within the above range, defects in the insulating layer 106 can be reduced and oxygen can be suppressed from being released from the semiconductor layer 108 and the semiconductor layer 208. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.
  • a plasma treatment may be performed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208.
  • the plasma treatment can reduce impurities such as water adsorbed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 and the interface between the semiconductor layer 208 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable for the case where the surfaces of the semiconductor layer 108 and the semiconductor layer 208 are exposed to the air between the formation of the semiconductor layer 108 and the semiconductor layer 208 and the formation of the insulating film 106f.
  • the plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. In addition, it is preferable that the plasma treatment and the formation of the insulating layer 106 are performed successively without exposure to the air.
  • the insulating film 106f is processed to form the insulating layer 106 (FIG. 25C).
  • the insulating layer 106 is provided with openings 147a and 147b that reach the semiconductor layer 208.
  • the insulating layer 106 can be preferably formed by dry etching.
  • a film that will become the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b is formed on the insulating layer 106, and the film is processed to form the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b (Fig. 26A).
  • the film can be formed by, for example, a sputtering method, a thermal CVD method (including a MOCVD method), or an ALD method.
  • impurities are supplied (also referred to as added or injected) to the semiconductor layer 208 using the conductive layer 204, the conductive layer 212a, and the conductive layer 212b as masks.
  • a region 208D is formed in a region of the semiconductor layer 208 that does not overlap with any of the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the insulating layer 106
  • a region 208L is formed in a region that does not overlap with any of the conductive layer 204, the conductive layer 212a, and the conductive layer 212b and overlaps with the insulating layer 106 (FIG. 26B).
  • the conditions for supplying the impurities in consideration of the material and thickness of the conductive layer 204 that serves as a mask so that the impurities are not supplied as much as possible to the region of the semiconductor layer 208 that overlaps with the conductive layer 204.
  • a channel formation region in which the impurity concentration is sufficiently reduced can be formed in the region of the semiconductor layer 208 that overlaps with the conductive layer 204.
  • the semiconductor layer 108 may be supplied with impurities using the conductive layer 104 as a mask. Region 108L is formed in the region of semiconductor layer 108 that does not overlap with conductive layer 104 and overlaps with insulating layer 106.
  • the impurities can be preferably supplied by plasma ion doping or ion implantation. These methods allow the concentration profile in the depth direction to be controlled with high precision by the ion acceleration voltage and dose amount, etc. By using the plasma ion doping method, productivity can be increased. In addition, by using the ion implantation method using mass separation, the purity of the supplied impurities can be increased.
  • the impurity concentration is highest on the surface of the semiconductor layer 208 or in the area close to the surface.
  • the source material used for supplying the impurity may be, for example, a gas containing the above-mentioned impurity element.
  • a gas containing the above-mentioned impurity element typically, one or more of B2H6 gas and BF3 gas may be used.
  • B2H6 gas and BF3 gas may be used.
  • PH3 gas may be used. Gases obtained by diluting these source gases with a noble gas may also be used.
  • Examples of the raw material used for supplying the impurity include CH4 , N2 , NH3, AlH3 , AlCl3 , SiH4 , Si2H6 , F2 , HF, H2 , ( C5H5 ) 2Mg , and noble gases. Note that the raw material is not limited to gas, and a solid or liquid may be heated and vaporized for use.
  • the addition of impurities can be controlled by setting conditions such as acceleration voltage and dose amount, taking into account the composition, density, and thickness of the insulating layer 106 and the semiconductor layer 208.
  • the acceleration voltage can be, for example, in the range of 5 kV to 100 kV, preferably 7 kV to 70 kV, and more preferably 10 kV to 50 kV.
  • the dose can be, for example, in the range of 1 ⁇ 10 13 ions/cm 2 to 1 ⁇ 10 17 ions/cm 2 , preferably 1 ⁇ 10 14 ions/cm 2 to 5 ⁇ 10 16 ions/cm 2 , and more preferably 1 ⁇ 10 15 ions/cm 2 to 3 ⁇ 10 16 ions/cm 2 .
  • the acceleration voltage can be, for example, in the range of 10 kV to 100 kV, preferably 30 kV to 90 kV, and more preferably 40 kV to 80 kV.
  • the dose can be, for example, in the range of 1 ⁇ 10 13 ions/cm 2 to 1 ⁇ 10 17 ions/cm 2 , preferably 1 ⁇ 10 14 ions/cm 2 to 5 ⁇ 10 16 ions/cm 2 , and more preferably 1 ⁇ 10 15 ions/cm 2 to 3 ⁇ 10 16 ions/cm 2 .
  • the method of supplying the impurities is not limited to this, and for example, plasma processing or processing utilizing thermal diffusion by heating may be used.
  • the impurities can be added by generating plasma in a gas atmosphere containing the impurities to be added and performing plasma processing.
  • a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high density plasma CVD apparatus, etc. may be used as an apparatus for generating the above plasma.
  • hydrogen can be supplied as an impurity to the semiconductor layer 208 in the region that does not overlap with the conductive layer 204.
  • a plasma CVD apparatus to supply the impurity and form the insulating layer 195, the supply of the impurity and the formation of the insulating layer 195 can be performed continuously within the apparatus, thereby improving productivity.
  • a capacitance element 150 is formed in the area where the conductive layer 202, the insulating layer 120, and the conductive layer 112b overlap each other.
  • an insulating layer 195 is formed covering the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, the insulating layer 106, and the semiconductor layer 208 (FIGS. 1B and 1C).
  • the insulating layer 195 can be preferably formed by the PECVD method.
  • the deposition temperature of the insulating layer 195 may be determined taking into account the diffusion of impurities.
  • the deposition temperature of the insulating layer 195 is, for example, 150° C. or higher and 400° C. or lower, preferably 180° C. or higher and 360° C. or lower, and more preferably 200° C. or higher and 250° C. or lower.
  • a heat treatment may be performed.
  • the heat treatment may reduce the electrical resistance of the regions 108L, 208L, and 208D.
  • the heat treatment may cause the impurities to diffuse appropriately, forming the regions 208L and 208D with an ideal impurity concentration gradient.
  • the above description can be referred to for the heat treatment, and a detailed description is omitted. Note that if the temperature of the heat treatment is too high (for example, 500° C. or higher), the impurities may diffuse to the channel formation region, which may cause deterioration in the electrical characteristics and reliability of the transistor.
  • this heat treatment does not have to be performed. Also, the heat treatment may not be performed here, and may be combined with a heat treatment performed in a later process. Also, if there is a process in a later process in which heat is applied (such as a film formation process), this may be combined with the heat treatment in question.
  • a semiconductor device according to one embodiment of the present invention can be manufactured.
  • the display device of this embodiment can be a high-resolution display device or a large display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • electronic devices with relatively large screens such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, in the display section of a wristwatch-type or bracelet-type information terminal (wearable device), as well as in the display section of a wearable device that can be worn on the head, such as a head-mounted display (HMD) or other VR device, or a glasses-type AR device.
  • a wearable device such as a head-mounted display (HMD) or other VR device, or a glasses-type AR device.
  • HMD head-mounted display
  • AR device glasses-type AR device
  • the semiconductor device of one embodiment of the present invention can be used in a display device or a module having the display device.
  • the module having the display device include a module in which a connector such as a flexible printed circuit (hereinafter, referred to as FPC) or a TCP (Tape Carrier Package) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a COG (chip on glass) method, a COF (chip on film) method, or the like.
  • the display device of this embodiment may have a function as a touch panel.
  • various detection elements also called sensor elements
  • various detection elements that can detect the proximity or contact of a detectable object such as a finger can be applied to the display device.
  • Sensor types include, for example, capacitive type, resistive film type, surface acoustic wave type, infrared type, optical type, and pressure sensitive type.
  • Examples of the capacitance type include the surface capacitance type and the projected capacitance type.
  • Examples of the projected capacitance type include the self-capacitance type and the mutual capacitance type.
  • the mutual capacitance type is preferable because it allows simultaneous multi-point detection.
  • touch panels examples include out-cell, on-cell, and in-cell types.
  • an in-cell touch panel is one in which electrodes constituting a sensing element are provided on one or both of a substrate supporting a display element (also called a display device) and an opposing substrate.
  • Figure 27A shows an oblique view of display device 50A.
  • Display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together.
  • substrate 152 is indicated by a dashed line.
  • the display device 50A has a display section 162, a connection section 140, a circuit section 164, a conductive layer 165, etc.
  • FIG. 27A shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in FIG. 27A can also be said to be a display module having the display device 50A, an IC, and an FPC.
  • connection portion 140 is provided on the outside of the display portion 162.
  • the connection portion 140 can be provided along one or more sides of the display portion 162. There may be one or more connection portions 140.
  • FIG. 27A shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion.
  • the connection portion 140 electrically connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.
  • the circuit portion 164 has, for example, a scanning line driver circuit (also called a gate driver).
  • the circuit portion 164 may also have both a scanning line driver circuit and a signal line driver circuit (also called a source driver).
  • the conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164.
  • the signals and power are input to the conductive layer 165 from the outside via the FPC 172, or are input to the conductive layer 165 from the IC 173.
  • FIG. 27A shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like.
  • an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173.
  • the display device 50A and the display module may be configured without an IC.
  • the IC may be mounted on an FPC by a COF method, or the like.
  • the semiconductor device of one embodiment of the present invention can be used, for example, as one or both of the display portion 162 and the circuit portion 164 of the display device 50A.
  • the semiconductor device of one embodiment of the present invention when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, the reliability of the display device can be improved by using it in a display device.
  • a driver circuit of a display device e.g., one or both of a gate line driver circuit and a source line driver circuit
  • the display unit 162 is an area in the display device 50A that displays an image, and has a number of periodically arranged pixels 210.
  • Figure 27A shows an enlarged view of one pixel 210.
  • pixel arrangements there are no particular limitations on the pixel arrangement in the display device of this embodiment, and various methods can be applied. Examples of pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a Pentile arrangement.
  • the pixel 210 shown in FIG. 27A has a pixel 230R that emits red light, a pixel 230G that emits green light, and a pixel 230B that emits blue light.
  • a full-color display can be realized by configuring one pixel 210 with pixels 230R, 230G, and 230B.
  • Each of pixels 230R, 230G, and 230B functions as a sub-pixel.
  • the display device 50A shown in FIG. 27A shows an example in which pixels 230 that function as sub-pixels are arranged in a stripe array.
  • the number of sub-pixels that configure one pixel 210 is not limited to three, and may be four or more.
  • the pixel 210 may have four sub-pixels that emit R, G, B, and white (W) light.
  • the pixel 210 may have four sub-pixels that emit R, G, B, and Y light.
  • Pixel 230R, pixel 230G, and pixel 230B each have a display element and a circuit that controls the driving of the display element.
  • Various elements can be used as display elements, including liquid crystal elements and light-emitting elements.
  • Other elements that can be used include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements that use microcapsules, electrophoresis, electrowetting, or electronic liquid powder (registered trademark) methods, etc.
  • QLEDs Quantum-dot LEDs that use a light source and color conversion technology using quantum dot materials.
  • Display devices using liquid crystal elements include, for example, transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.
  • Modes that can be used in displays using liquid crystal elements include, for example, vertical alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane Switching) mode, TN (Twisted Nematic) mode, and ASM (Axially Symmetrically aligned Micro-cell) mode.
  • VA mode include the MVA (Multi-Domain Vertical Alignment) mode, the PVA (Patterned Vertical Alignment) mode, and the ASV (Advanced Super View) mode.
  • Liquid crystal materials that can be used in liquid crystal elements include, for example, thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), polymer network liquid crystal (PNLC: Polymer Network Liquid Crystal), ferroelectric liquid crystal, and antiferroelectric liquid crystal.
  • thermotropic liquid crystal low molecular weight liquid crystal
  • polymer liquid crystal polymer dispersed liquid crystal
  • PNLC Polymer Network liquid crystal
  • ferroelectric liquid crystal and antiferroelectric liquid crystal.
  • these liquid crystal materials can exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, blue phase, etc.
  • either positive type liquid crystal or negative type liquid crystal can be used as the liquid crystal material, and can be selected according to the mode or design to be applied.
  • Light-emitting elements include, for example, self-emitting light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. LEDs can also include, for example, mini LEDs and micro LEDs.
  • Light-emitting materials that light-emitting elements have include, for example, materials that emit fluorescence (fluorescent materials), materials that emit phosphorescence (phosphorescent materials), materials that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).
  • fluorescent materials materials that emit fluorescence
  • phosphorescent materials materials that emit phosphorescence
  • TADF thermally activated delayed fluorescence
  • inorganic compounds quantum dot materials, etc.
  • the light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, or white.
  • the color purity can be increased by providing the light-emitting element with a microcavity structure.
  • one electrode functions as an anode and the other electrode functions as a cathode.
  • the display device of one embodiment of the present invention may be a top-emission type that emits light in a direction opposite to the substrate on which the light-emitting elements are formed, a bottom-emission type that emits light toward the substrate on which the light-emitting elements are formed, or a dual-emission type that emits light on both sides.
  • FIG. 27B is a block diagram illustrating the display device 50A.
  • the display device 50A has a display unit 162 and a circuit unit 164.
  • the display unit 162 has a plurality of periodically arranged pixels 230 (pixels 230[1,1] to 230[m,n], where m and n are each independently an integer of 2 or more).
  • the circuit unit 164 has a first drive circuit unit 231 and a second drive circuit unit 232.
  • the circuit included in the first drive circuit unit 231 functions, for example, as a scanning line drive circuit.
  • the circuit included in the second drive circuit unit 232 functions, for example, as a signal line drive circuit. Note that some kind of circuit may be provided at a position facing the first drive circuit unit 231 across the display unit 162. Some kind of circuit may be provided at a position facing the second drive circuit unit 232 across the display unit 162.
  • the circuit portion 164 may include various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexer circuit, and a logic circuit.
  • the circuit portion 164 may include transistors and capacitor elements. The transistors in the circuit portion 164 may be formed in the same process as the transistors included in the pixel 230.
  • Display device 50A has wiring 236 that are arranged approximately in parallel and whose potential is controlled by a circuit included in first drive circuit section 231, and wiring 238 that are arranged approximately in parallel and whose potential is controlled by a circuit included in second drive circuit section 232.
  • FIG. 27B shows an example in which wiring 236 and wiring 238 are connected to pixel 230.
  • wiring 236 and wiring 238 are just an example, and wirings connected to pixel 230 are not limited to wiring 236 and wiring 238.
  • a vertical transistor (VFET) having a submicron-sized channel length and a large on-state current and a TGSA transistor having a long channel length and high saturation can be formed by sharing some of the steps.
  • An oxide semiconductor (OS) can be preferably used for the channel formation region of these transistors, and the transistors can have a small off-state current.
  • the semiconductor device according to one embodiment of the present invention can be preferably used for one or both of the display portion 162 and the circuit portion 164.
  • the semiconductor device according to one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all the transistors included in the display device can be OS transistors. By using OS transistors for all the transistors included in the display device in this way, it is possible to achieve an effect of reducing manufacturing costs.
  • ⁇ Configuration example of the driving circuit> As a circuit that can be used for the driver circuit, a configuration example will be described taking a latch circuit as an example.
  • FIG. 28A is a circuit diagram showing an example of the configuration of a latch circuit LAT.
  • the latch circuit LAT shown in FIG. 28A has transistors Tr31, Tr33, Tr35, Tr36, a capacitance element C31, and an inverter circuit INV.
  • a node to which one of the source and drain of transistor Tr33, the gate of transistor Tr35, and one electrode of the capacitance element C31 are electrically connected is referred to as node N.
  • the transistor Tr33 when a high potential signal is input to the terminal SMP, the transistor Tr33 is turned on. As a result, the potential of the node N becomes a potential corresponding to the potential of the terminal ROUT, and data corresponding to the signal input from the terminal ROUT to the latch circuit LAT is written to the latch circuit LAT. After the data is written to the latch circuit LAT, if the potential of the terminal SMP is made low, the transistor Tr33 is turned off. As a result, the potential of the node N is held, and the data written to the latch circuit LAT is held.
  • transistor Tr33 It is preferable to use a transistor with a small off-state current as the transistor Tr33.
  • An OS transistor can be suitably used as the transistor Tr33. This allows the latch circuit LAT to hold data for a long period of time. This reduces the frequency with which data is rewritten to the latch circuit LAT.
  • writing data to the latch circuit LAT such that the signal input from terminal SP2 is output to terminal LIN may be simply referred to as "writing data to the latch circuit LAT.”
  • writing data with a value of "1" to the latch circuit LAT may be simply referred to as "writing data to the latch circuit LAT.”
  • a semiconductor device can be suitably used in the latch circuit LAT.
  • the transistor 100 or the transistor 200 shown in FIG. 1B or the like can be used as one or more of the transistors Tr31, Tr33, Tr35, and Tr36.
  • the inverter circuit INV has transistors Tr41, Tr43, Tr45, Tr47, and a capacitance element C41.
  • all the transistors in the latch circuit LAT can be transistors of the same polarity, for example, n-channel transistors. This allows, for example, transistor Tr33 as well as transistors Tr31, Tr35, Tr36, Tr41, Tr43, Tr45, and Tr47 to be OS transistors. Therefore, all the transistors in the latch circuit LAT can be manufactured in the same process.
  • a semiconductor device can be preferably used for the inverter circuit INV.
  • the transistor 100 or the transistor 200 shown in FIG. 1B can be used for one or more of the transistors Tr41, Tr43, Tr45, and Tr47.
  • transistors 100 to 100D By using one or more types of transistors 100 to 100D, the occupied area can be reduced, and a display device with a narrow frame can be obtained.
  • one or more types of transistors 100 to 100D can be preferably used as transistors that require a large on-state current.
  • transistors 200 to 200B can be preferably used as transistors that require high saturation. This allows a display device with high performance.
  • ⁇ Pixel Circuit Configuration Example 1> 29A shows an example of the configuration of the pixel 230.
  • the pixel 230 includes a pixel circuit 51 and a light-emitting device 61.
  • the pixel circuit 51 shown in FIG. 29A has a transistor 52A, a transistor 52B, and a capacitor 53.
  • the pixel circuit 51 is a 2Tr1C type pixel circuit having two transistors and one capacitor. Note that there is no particular limitation on the pixel circuit that can be applied to the display device of one embodiment of the present invention.
  • the anode of the light-emitting device 61 is electrically connected to one of the source and drain of the transistor 52B and one electrode of the capacitance element 53.
  • the other of the source and drain of the transistor 52B is electrically connected to the wiring ANO.
  • the gate of the transistor 52B is electrically connected to one of the source and drain of the transistor 52A and the other electrode of the capacitance element 53.
  • the other of the source and drain of the transistor 52A is electrically connected to the wiring GL.
  • the gate of the transistor 52A is electrically connected to the wiring GL.
  • the cathode of the light-emitting device 61 is electrically connected to the wiring VCOM.
  • the wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 238.
  • the wiring VCOM is a wiring that provides a potential for supplying a current to the light-emitting device 61.
  • the transistor 52A has a function of controlling the conductive state or non-conductive state between the wiring SL and the gate of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.
  • Transistor 52B has the function of controlling the amount of current flowing through light-emitting device 61.
  • Capacitive element 53 has the function of maintaining the gate potential of transistor 52B. The intensity of the light emitted by light-emitting device 61 is controlled according to an image signal supplied to the gate of transistor 52B.
  • a backgate may be provided for some or all of the transistors included in the pixel circuit 51.
  • the pixel circuit 51 shown in FIG. 29A shows a configuration in which the transistor 52B has a backgate, and the backgate is electrically connected to one of the source and drain of the transistor 52B. Note that the backgate of the transistor 52B may be electrically connected to the gate of the transistor 52B.
  • the above-mentioned semiconductor device can be suitably used in the pixel circuit 51.
  • the transistor 52B functioning as a drive transistor for controlling the current flowing through the light-emitting device 61 preferably has high saturation.
  • the transistors 200 to 200B having a long channel length as the transistor 52B a highly reliable display device can be obtained.
  • the transistors 100 to 100D as the transistor 52A the area occupied by the pixel circuit 51A can be reduced, and a high-definition display device can be obtained.
  • one of the transistors 100 to 100D may be used as the transistor 52B.
  • a transistor with a short channel length as the transistor 52B, a display device with high luminance can be obtained.
  • the area occupied by the pixel circuit 51 can be reduced, and a high-definition display device can be obtained.
  • FIG. 29B shows an example of a configuration different from that of pixel 230 shown in FIG. 29A.
  • Pixel 230 has a pixel circuit 51A and a light-emitting device 61.
  • Pixel circuit 51A shown in FIG. 29B differs from pixel circuit 51 shown in FIG. 29A mainly in that it has transistor 52C.
  • Pixel circuit 51A has transistor 52A, transistor 52B, transistor 52C, and capacitance element 53.
  • Pixel circuit 51A is a 3Tr1C type pixel circuit having three transistors and one capacitance element.
  • One of the source and drain of transistor 52C is electrically connected to one of the source and drain of transistor 52B.
  • the other of the source and drain of transistor 52C is electrically connected to wiring V0.
  • a reference potential is supplied to wiring V0.
  • the gate of transistor 52C is electrically connected to wiring GL.
  • Transistor 52C has a function of controlling the conductive or non-conductive state between one of the source and drain electrodes of transistor 52B and wiring V0 based on the potential of wiring GL.
  • the reference potential of wiring V0 provided via transistor 52C can suppress variations in the gate-source potential of transistor 52B.
  • the wiring V0 can be used to obtain a current value that can be used to set pixel parameters.
  • the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting device 61 to the outside.
  • the current output to the wiring V0 can be converted to a voltage by a source follower circuit and output to the outside. Alternatively, it can be converted to a digital signal by an AD converter and output to the outside.
  • the above-mentioned semiconductor device can be suitably used in the pixel circuit 51A.
  • the transistors 200 to 200B having a long channel length as the transistor 52B a highly reliable display device can be obtained.
  • the transistors 100 to 100D as the transistors 52A and 52C, the area occupied by the pixel circuit 51A can be reduced, and a high-definition display device can be obtained. Note that one of the transistors 100 to 100D may also be used for the transistor 52B.
  • FIG. 29C is a cross-sectional view of pixel circuit 51.
  • FIG. 29C shows an excerpt of transistor 52A, transistor 52B, capacitance element 53, and pixel electrode of light-emitting device 61. Note that the electrical connection between transistor 52A and transistor 52B is omitted.
  • Transistor 52A has a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b.
  • Transistor 52B has a conductive layer 202, an insulating layer 106, a semiconductor layer 208, an insulating layer 120, a conductive layer 204, a conductive layer 212a, and a conductive layer 212b.
  • the above description can be referred to for transistors 52A and 52B, so detailed description is omitted.
  • the capacitor 53 has a conductive layer 212a, a conductive layer 112p, and an insulating layer 106 sandwiched between them.
  • the conductive layer 112p is provided on the insulating layer 120.
  • the conductive layer 112p can be formed, for example, in the same process as the conductive layer 112b.
  • the insulating layer 106 is provided on the conductive layer 112p, and the conductive layer 212a is provided on the insulating layer 106.
  • the conductive layer 212a functions as one of the source and drain electrodes of the transistor 52B and also functions as one electrode of the capacitor 53. Note that the configuration of the capacitor 53 is not particularly limited.
  • An insulating layer 195 is provided to cover the transistor 52A, the transistor 52B, and the capacitor 53, an insulating layer 233 is provided to cover the insulating layer 195, and an insulating layer 235 is provided to cover the insulating layer 233.
  • a light-emitting device 61 can be provided on the insulating layer 235.
  • FIG. 29C shows a pixel electrode 111 that functions as one electrode of the light-emitting device 61.
  • the insulating layer 195 and the insulating layer 233 have a first opening that reaches the conductive layer 212a, and a conductive layer 234 is provided to cover the first opening.
  • the conductive layer 234 is electrically connected to the conductive layer 212a through the first opening.
  • the insulating layer 235 has a second opening that reaches the conductive layer 234, and a pixel electrode 111 is provided to cover the second opening.
  • the pixel electrode 111 is electrically connected to the conductive layer 234 through the second opening.
  • the insulating layer 195 can be described above, so a detailed description will be omitted.
  • the insulating layer 233 and the insulating layer 235 have the function of reducing unevenness caused by the transistor 52A, the transistor 52B, and the transistor 52C, and making the surface on which the light-emitting device 61 is formed more flat. Note that in this specification and the like, the insulating layer 233 and the insulating layer 235 may each be referred to as a flattening layer.
  • the insulating layer 233 and the insulating layer 235 are preferably organic insulating films.
  • Examples of materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins.
  • the insulating layer 235 may have a laminated structure of an organic insulating film and an inorganic insulating film. It is preferable that the insulating layer 235 has a laminated structure of an organic insulating film and an inorganic insulating film on the organic insulating film. This allows the inorganic insulating film to function as an etching protection layer when forming the light-emitting device 61.
  • the insulating layer 233 may have a laminated structure of an organic insulating film and an inorganic insulating film.
  • ⁇ Pixel Circuit Configuration Example 2> 30 shows an example of a configuration different from the above-described pixel 230.
  • the pixel 230 has a pixel circuit 51B and a light-emitting device 61.
  • Pixel circuit 51B has transistor M11, transistor M12, transistor M13, transistor M14, transistor M15, transistor M16, capacitance element C11, and capacitance element C12.
  • Pixel circuit 51B is a 6Tr2C type pixel circuit having six transistors and two capacitance elements.
  • the anode of the light-emitting device 61 is electrically connected to one of the source and drain of the transistor M15.
  • the cathode of the light-emitting device 61 is electrically connected to the wiring VCOM.
  • the other of the source and drain of the transistor M15 is electrically connected to one of the source and drain of the transistor M12, one of the source and drain of the transistor M13, one of the source and drain of the transistor M16, one electrode of the capacitance element C11, and one electrode of the capacitance element C12.
  • the gate of the transistor M12 is electrically connected to one of the source and drain of the transistor M11, the other of the source and drain of the transistor M13, and the other electrode of the capacitance element C11.
  • the backgate of the transistor M12 is electrically connected to one of the source and drain of the transistor M14, and the other electrode of the capacitance element C12.
  • the other of the source and drain of transistor M11 is electrically connected to wiring SL.
  • the other of the source and drain of transistor M12 is electrically connected to wiring ANO.
  • the other of the source and drain of transistor M14 is electrically connected to wiring V0.
  • the other of the source and drain of transistor M16 is electrically connected to wiring V1.
  • a constant potential is supplied to wiring V1.
  • the gate of transistor M11 and the gate of transistor M16 are electrically connected to wiring GL1.
  • the gate of transistor M13 and the gate of transistor M14 are electrically connected to wiring GL2.
  • the gate of transistor M15 is electrically connected to wiring GL3.
  • Transistor M11 functions as a selection transistor that controls the conductive state or non-conductive state between the gate of transistor M12 and the wiring SL.
  • Transistor M12 functions as a drive transistor that controls the current flowing through the light-emitting device 61.
  • Transistor M14 has a function of supplying the potential of the wiring V0 to the back gate of transistor M12.
  • the threshold voltage can be controlled by supplying a constant potential to the back gate of transistor M12.
  • Capacitive element C11 has a function of holding the gate potential of transistor M12.
  • Capacitive element C12 has a function of holding the back gate potential of transistor M12.
  • the pixel circuit 51B has a so-called internal threshold voltage correction function that corrects the threshold voltage of transistor M12 by the back gate.
  • the capacitive element C12 is made to hold a back gate potential such that the threshold voltage of transistor M12 becomes 0V. This makes it possible to correct the threshold voltage of transistor M12 to a constant value of 0V or close to 0V, regardless of the variation in threshold voltage of the transistor and deterioration over time.
  • the above-mentioned semiconductor device can be suitably used in the pixel circuit 51B.
  • one or more types of transistors 100 to 100D shown in FIG. 1B can be used for the transistors M11, M13, M14, M15, and M16, and one of the transistors 200 to 200B can be used for the transistor M12.
  • the transistor M12 which functions as a driving transistor, preferably has high saturation.
  • the transistors 200 to 200B which have a long channel length, as the transistor M12, a highly reliable display device can be obtained.
  • the transistors 100 to 100D as the transistors M11, M13, M14, M15, and M16, the area occupied by the pixel circuit 51B can be reduced, and a high-definition display device can be obtained.
  • one of the transistors 100 to 100D may be used as the transistor M12.
  • a transistor with a short channel length as the transistor M12, a display device with high luminance can be obtained.
  • the area occupied by the pixel circuit 51B can be reduced, and a high-definition display device can be obtained.
  • a high-performance display device By using a plurality of transistors and capacitors in a pixel circuit, a high-performance display device can be obtained.
  • the area occupied can be reduced even if the number of transistors and capacitors is increased, and a high-performance and high-resolution display device can be obtained.
  • a display device with a resolution of 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, or 3000 ppi or more can be realized.
  • the semiconductor device can reduce the area occupied by the semiconductor device, and therefore can increase the aperture ratio of a pixel in a display device having a bottom emission structure.
  • a display device having an aperture ratio of 50% or more, 55% or more, or 60% or more can be realized.
  • the aperture ratio refers to the ratio of the area of the region through which light is emitted to the area of the pixel.
  • FIG. 31 to 33 show examples of the layout of the pixel 230.
  • FIG. 31 is a top view corresponding to the circuit diagram shown in FIG. 30.
  • FIG. 31 shows the transistor M11, the transistor M12, the transistor M13, the transistor M14, the transistor M15, the transistor M16, the capacitor C11, the capacitor C12, the wiring GL1, the wiring GL2, the wiring GL3, the wiring SL, the wiring V1, the wiring ANO, and the pixel electrode 111 of the light-emitting device 61.
  • the pixel electrode 111 is shown with transparent hatching to make it easier to understand the configuration below the pixel electrode 111.
  • the wiring ANO also has wiring ANO_1 and wiring ANO_2.
  • the wiring ANO_1 and wiring ANO_2 are electrically connected and function as the wiring ANO.
  • the wiring V0 is omitted in FIG. 31.
  • FIG. 32 is a top view in which the pixel electrode 111 is omitted from FIG. 31.
  • FIG. 33 is a top view in which the wiring V1, wiring SL, and wiring ANO_2 are further omitted from FIG. 32. Note that in FIGS. 31 to 33, the range of one pixel 230 is indicated by a two-dot chain line.
  • FIG. 34 A cross-sectional view of the cut surface taken along dashed line G1-G2 in FIG. 31 is shown in FIG. 34, a cross-sectional view of the cut surface taken along dashed line B3-G4 in FIG. 35A, and a cross-sectional view of the cut surface taken along dashed line G5-G6 in FIG. 35B.
  • Figures 31 to 35 show an example in which the configuration of transistor 100 shown in Figure 1B etc. is applied to transistors M11, M13, M14, M15, and M16, and the configuration of transistor 200 is applied to transistor M12.
  • Transistor M11 has conductive layers 112a, 112b, a semiconductor layer 108, an insulating layer 106, and a conductive layer 104.
  • conductive layer 112b functions as one of a source electrode and a drain electrode
  • conductive layer 112a functions as the other.
  • a part of insulating layer 106 functions as a gate insulating layer
  • conductive layer 104 functions as a gate electrode.
  • conductive layer 104 functions as wiring GL1.
  • the conductive layer 112b and the insulating layer 110 have openings 143 and 141 in the areas where they overlap with the conductive layer 112a.
  • the semiconductor layer 108 is provided so as to cover the openings 143 and 141.
  • the insulating layer 106 is provided on the semiconductor layer 108, and the conductive layer 104 is provided on the insulating layer 106.
  • Transistor M12 has a conductive layer 202, an insulating layer 120, a semiconductor layer 208, an insulating layer 106, a conductive layer 204, a conductive layer 212a, and a conductive layer 212b.
  • the conductive layer 204 functions as a gate electrode (also referred to as a first gate electrode), and a part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer).
  • the conductive layer 202 functions as a back gate electrode (also referred to as a second gate electrode), and a part of the insulating layer 120 functions as a back gate insulating layer (also referred to as a second gate insulating layer).
  • the conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other.
  • a conductive layer 202 is provided on the insulating layer 110, and an insulating layer 120 is provided to cover the conductive layer 202.
  • a semiconductor layer 208 is provided on the insulating layer 120, and an insulating layer 106 is provided to cover the semiconductor layer 208.
  • a conductive layer 204, a conductive layer 212a, and a conductive layer 212b are provided on the insulating layer 106.
  • the insulating layer 106 has openings 147a and 147b that reach the semiconductor layer 208, and the conductive layers 212a and 212b are in contact with the semiconductor layer 208 via the openings 147a and 147b.
  • the insulating layer 106 has an opening 188 that reaches the conductive layer 112b, and a conductive layer 204 is provided to cover the opening 188.
  • the conductive layer 204 is electrically connected to the conductive layer 112b through the opening 188.
  • FIG. 36A A top view of the conductive layer 112a is shown in FIG. 36A.
  • FIG. 36A shows conductive layer 112aA and conductive layer 112aB, which can be formed in the same process.
  • the conductive layer 112aB functions as wiring V0.
  • the conductive layer 112aB (wiring V0) extends in the column direction.
  • FIG. 36B A top view of the conductive layer 202 and the insulating layer 120 is shown in FIG. 36B.
  • the insulating layer 120 is shown by a dashed line.
  • FIG. 36C A top view of conductive layer 112b is shown in Figure 36C.
  • Figure 36C shows conductive layer 112bA, conductive layer 112bB, conductive layer 112bC, conductive layer 112p, and conductive layer 112q, which can be formed in the same process.
  • conductive layer 112b has opening 143A of transistor M13.
  • Conductive layer 112bA has opening 143B of transistor M14.
  • Conductive layer 112bB has opening 143C of transistor M15.
  • Conductive layer 112bC has opening 143D of transistor M16.
  • Conductive layer 112p has opening 143p
  • conductive layer 112q has opening 143q.
  • the openings 143 to 143D, the opening 143p, and the opening 143q can be formed in the same process.
  • the top shapes of the openings 143p and 143q are shown different from the top shapes of the openings 143 to 143D, but the top shapes of the openings 143p and 143q are not particularly limited.
  • the top shapes of the openings 143 to 143D, the opening 143p, and the opening 143q can be circular.
  • the openings 141 to 141D, the opening 141p, and the opening 141q are provided in the regions of the insulating layer 110 that overlap with the openings 143 to 143D, the opening 143p, and the opening 143q.
  • FIG. 37A A top view of semiconductor layer 108 and semiconductor layer 208 is shown in FIG. 37A.
  • FIG. 37A also shows semiconductor layer 108A, semiconductor layer 108B, semiconductor layer 108C, and semiconductor layer 108D, which can be formed in the same process.
  • FIG. 37B The top view of the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b is shown in FIG. 37B.
  • FIG. 37B shows the conductive layer 104A, the conductive layer 104B, the conductive layer 104p, the conductive layer 104q, the conductive layer 104r, the conductive layer 104s, and the wiring ANO_1, which can be formed in the same process.
  • the conductive layer 104 functions as the wiring GL1, the conductive layer 104A functions as the wiring GL2, and the conductive layer 104B functions as the wiring GL3.
  • the conductive layer 104 (wiring GL1), the conductive layer 104A (wiring GL2), the conductive layer 104B (wiring GL3), and the wiring ANO_1 extend in the row direction.
  • FIG. 37C A top view of wiring V1, wiring SL, and wiring ANO_2 is shown in FIG. 37C.
  • FIG. 37C shows conductive layer 234, which can be formed in the same process.
  • Wiring V1, wiring SL, and wiring ANO_2 extend in the column direction.
  • insulating layer 195 and insulating layer 233 are provided on wiring ANO_1.
  • Insulating layer 195 and insulating layer 233 have opening 183 that reaches wiring ANO_1, and wiring ANO_2 is provided to cover opening 183.
  • Wiring ANO_1 and wiring ANO_2 are electrically connected via opening 183 and function as wiring ANO.
  • the conductive layer 112a of the transistor M11 is electrically connected to the wiring SL through the conductive layer 104s.
  • the conductive layer 104s is electrically connected to the conductive layer 112a through the opening 190, the opening 143p, and the opening 141p.
  • An opening 141p reaching the conductive layer 112a is provided in the insulating layer 110, and a conductive layer 112p having an opening 143p is provided on the insulating layer 110.
  • An insulating layer 106 is provided on the conductive layer 112p, and an opening 190 is provided in a region overlapping with the opening 143p of the insulating layer 106.
  • the conductive layer 104s is provided so as to cover the opening 190, the opening 143p, and the opening 141p.
  • An insulating layer 195 and an insulating layer 233 are provided on the conductive layer 104s, an opening 191 is provided in a region overlapping with the conductive layer 104s of the insulating layer 195 and the insulating layer 233, and a wiring SL is provided so as to cover the opening 191.
  • the conductive layer 212a of the transistor M12 is electrically connected to the conductive layer 112aA via the opening 189, the opening 143q, and the opening 141q.
  • An opening 141q reaching the conductive layer 212a is provided in the insulating layer 110, and a conductive layer 112q having an opening 143q is provided on the insulating layer 110.
  • An insulating layer 106 is provided on the conductive layer 112q, and an opening 189 is provided in a region of the insulating layer 106 that overlaps with the opening 143q.
  • a conductive layer 212a is provided to cover the opening 189, the opening 143q, and the opening 141q.
  • Transistor M13 has conductive layer 112aA, conductive layer 112b, semiconductor layer 108A, insulating layer 106, and conductive layer 104A.
  • conductive layer 112aA functions as one of a source electrode and a drain electrode
  • conductive layer 112b functions as the other.
  • a part of insulating layer 106 functions as a gate insulating layer
  • conductive layer 104A functions as a gate electrode.
  • Conductive layer 112b functions as one of a source electrode and a drain electrode of transistor M11 and also functions as the other of a source electrode and a drain electrode of transistor M13.
  • the conductive layer 112b and the insulating layer 110 have openings 143A and 141A in the areas where they overlap with the conductive layer 112aA.
  • the semiconductor layer 108A is provided so as to cover the openings 143A and 141A.
  • the insulating layer 106 is provided on the semiconductor layer 108A, and the conductive layer 104A is provided on the insulating layer 106.
  • Transistor M14 has conductive layer 112aB, conductive layer 112bA, semiconductor layer 108B, insulating layer 106, and conductive layer 104A.
  • conductive layer 112bA functions as one of a source electrode and a drain electrode
  • conductive layer 112aB functions as the other.
  • a part of insulating layer 106 functions as a gate insulating layer
  • conductive layer 104A functions as a gate electrode.
  • Conductive layer 104A functions as the gate electrode of transistor M13 and also functions as the gate electrode of transistor M14.
  • the conductive layer 112bA and the insulating layer 110 have openings 143B and 141B in the areas where they overlap with the conductive layer 112aB.
  • the semiconductor layer 108B is provided so as to cover the openings 143B and 141B.
  • the insulating layer 106 is provided on the semiconductor layer 108B, and the conductive layer 104A is provided on the insulating layer 106.
  • Transistor M15 has conductive layer 112aA, conductive layer 112bB, semiconductor layer 108C, insulating layer 106, and conductive layer 104B.
  • conductive layer 112bB functions as one of a source electrode and a drain electrode
  • conductive layer 112aA functions as the other.
  • a part of insulating layer 106 functions as a gate insulating layer
  • conductive layer 104B functions as a gate electrode.
  • Conductive layer 112aA functions as one of a source electrode and a drain electrode of transistor M13, and also functions as the other of a source electrode and a drain electrode of transistor M15.
  • the conductive layer 112bB and the insulating layer 110 have openings 143C and 141C in the areas where they overlap with the conductive layer 112aA.
  • the semiconductor layer 108C is provided so as to cover the openings 143C and 141C.
  • the insulating layer 106 is provided on the semiconductor layer 108C, and the conductive layer 104B is provided on the insulating layer 106.
  • the conductive layer 112bB of the transistor M15 is electrically connected to the pixel electrode 111 via the conductive layer 104p and the conductive layer 234.
  • the insulating layer 106 has an opening 181 that reaches the conductive layer 112bB, and the conductive layer 104p is provided so as to cover the opening 181.
  • the insulating layer 195 and the insulating layer 233 are provided on the conductive layer 104p.
  • the insulating layer 195 and the insulating layer 233 have an opening 182 that reaches the conductive layer 104p, and the conductive layer 234 is provided so as to cover the opening 182.
  • the insulating layer 235 is provided on the conductive layer 234.
  • the insulating layer 235 has an opening 184 that reaches the conductive layer 234, and the pixel electrode 111 is provided so as to cover the opening 184.
  • Transistor M16 has conductive layer 112aA, conductive layer 112bC, semiconductor layer 108D, insulating layer 106, and conductive layer 104.
  • conductive layer 112aA functions as one of a source electrode and a drain electrode
  • conductive layer 112bC functions as the other.
  • a part of insulating layer 106 functions as a gate insulating layer
  • conductive layer 104 functions as a gate electrode.
  • Conductive layer 112aA functions as one of a source electrode and a drain electrode of transistor M13 and the other of a source electrode and a drain electrode of transistor M15, and also functions as one of a source electrode and a drain electrode of transistor M16.
  • Conductive layer 104 functions as a gate electrode of transistor M11 and a gate electrode of transistor M16.
  • the conductive layer 112bC and the insulating layer 110 have openings 143D and 141D in the areas where they overlap with the conductive layer 112aA.
  • the semiconductor layer 108D is provided so as to cover the openings 143D and 141D.
  • the insulating layer 106 is provided on the semiconductor layer 108D, and the conductive layer 104 is provided on the insulating layer 106.
  • the capacitance element C12 includes a conductive layer 112aA, a conductive layer 202, an insulating layer 110 sandwiched between the conductive layer 112aA and the conductive layer 202, and an insulating layer 120 provided on the conductive layer 202.
  • the insulating layer 120 is provided on the conductive layer 202.
  • the insulating layer 120 has an opening 185 that reaches the conductive layer 202, and a conductive layer 112bA is provided so as to cover the opening 185. Note that the top surface shape of the opening 185 is not particularly limited.
  • An insulating layer 106 is provided on the conductive layer 112bA, and a conductive layer 104q is provided on the insulating layer 106.
  • the conductive layer 104q is electrically connected to the conductive layer 112bA through the openings 186 and 187 provided in the insulating layer 106.
  • the conductive layer 104q can be formed in the same process as the conductive layer 104 and the conductive layer 204. For example, it is preferable to use a material having a lower electrical resistivity than the conductive layer 112bA for the conductive layer 104q. This can reduce the wiring resistance between the capacitor C12 and the transistor M14. Note that the conductive layer 104q does not necessarily have to be provided.
  • the conductive layer 112bA has a region in contact with the conductive layer 202, and thus they are electrically connected, one embodiment of the present invention is not limited to this.
  • a structure in which the conductive layer 112bA does not have a region in contact with the conductive layer 202 and the conductive layer 112bA and the conductive layer 202 are electrically connected through the conductive layer 104q may also be used.
  • the conductive layer 112bA may not be provided in the opening 185, and the conductive layer 104q may be provided so as to cover the opening 185 and the opening 187.
  • the capacitive element C11 has a conductive layer 112b, a conductive layer 212a, and an insulating layer 106 sandwiched between the conductive layer 112b and the conductive layer 212a.
  • the conductive layer 112a which functions as the other of the source electrode and drain electrode of the transistor M11, is electrically connected to the wiring SL through the conductive layer 104s.
  • An opening 190 reaching the conductive layer 112a is provided in the insulating layer 110 and the insulating layer 106, and the conductive layer 104s is provided so as to cover the opening 190.
  • An insulating layer 195 and an insulating layer 233 are provided on the conductive layer 104s, an opening 191 reaching the conductive layer 104s is provided in the insulating layer 195 and the insulating layer 233, and a wiring SL is provided so as to cover the opening 191.
  • the conductive layer 212b which functions as the other of the source electrode and drain electrode of the transistor M12, is electrically connected to the wiring ANO_2 through the opening 193.
  • An opening 193 reaching the conductive layer 212b is provided in the insulating layer 195 and the insulating layer 233, and the wiring ANO_2 is provided to cover the opening 193.
  • the conductive layer 112bC which functions as the other of the source electrode and drain electrode of the transistor M16, is electrically connected to the wiring V1 via the conductive layer 104r.
  • An opening 194 reaching the conductive layer 112bC is provided in the insulating layer 106, and the conductive layer 104r is provided so as to cover the opening 194.
  • An insulating layer 195 and an insulating layer 233 are provided on the conductive layer 104r, an opening 196 reaching the conductive layer 104r is provided in the insulating layer 195 and the insulating layer 233, and a wiring V1 is provided so as to cover the opening 196.
  • FIG. 38 A layout in which subpixels are arranged in 3 rows and 6 columns is shown in FIG. 38.
  • six pixels 230R (pixels 230R[p,q] to 230R[p+2,q+1], where p and q are each independently an integer of 2 or more) functioning as subpixels
  • six pixels 230G (pixels 230G[p,q] to 230G[p+2,q+1])
  • six pixels 230B pixels 230B[p,q] to 230B[p+2,q+1]
  • One pixel 230R, one pixel 230G, and one pixel 230B function as one pixel 210, and FIG.
  • FIG. 38 shows three rows and two columns of pixels 210 (pixels 210[p,q] to 210[p+2,q+1]).
  • FIG. 39 shows the layout of pixels 230R, 230G, and 230B corresponding to FIG. 38.
  • the layout of pixel 230 described above can be applied to pixels 230R, 230G, and 230B, respectively.
  • the layouts of adjacent pixels 230 are line-symmetrical with respect to the boundary. Specifically, the layouts of pixels 230R[p,q], 230R[p+1,q], and 230R[p+2,q] arranged in the same column and the layouts of pixels 230G[p,q], 230G[p+1,q], and 230G[p+2,q] arranged in an adjacent column are line-symmetrical with respect to the boundary between these columns (see arrow A in FIG. 38).
  • the layouts of pixels 230G[p,q], 230G[p+1,q], and 230G[p+2,q] and the layouts of pixels 230B[p,q], 230B[p+1,q], and 230B[p+2,q] arranged in an adjacent column are line-symmetrical with respect to the boundary between these columns (see arrow B in FIG. 38). From here on, the process is the same, so we won't go into detail here.
  • pixels 230R[p,q], pixel 230G[p,q], pixel 230B[p,q], pixel 230R[p,q+1], pixel 230G[p,q+1], and pixel 230B[p,q+1] arranged in the same row, and the layout of pixels 230R[p+1,q], pixel 230G[p+1,q], pixel 230B[p+1,q], pixel 230R[p+1,q+1], pixel 230G[p+1,q+1], and pixel 230B[p+1,q+1] arranged in adjacent rows, are linearly symmetrical about the boundary between these rows (see arrow C in Figure 38).
  • the layout of pixel 230R[p+1,q], pixel 230G[p+1,q], pixel 230B[p+1,q], pixel 230R[p+1,q+1], pixel 230G[p+1,q+1], and pixel 230B[p+1,q+1] is symmetrical with respect to the boundary between these rows, as compared to the layout of pixel 230R[p+2,q], pixel 230G[p+2,q], pixel 230B[p+2,q], pixel 230R[p+2,q+1], pixel 230G[p+2,q+1], and pixel 230B[p+2,q+1], which are arranged in adjacent rows (see arrow D in FIG. 38). Since the following is a repetition of the same procedure, detailed description will be omitted.
  • Pixel 230 shares wiring and the like with adjacent pixels 230. Enlarged views of pixel 230R[p+1,q], pixel 230G[p+1,q], pixel 230B[p+1,q] and their vicinity are shown in Figures 40A to 42B.
  • Pixels 230 in the same column share wiring ANO_2 and wiring V0 with pixels 230 in adjacent columns.
  • pixels 230 share openings 183 and 193 with pixels 230 in adjacent columns.
  • pixels 230R[p+1,q] and pixels 230R[p+2,q] in the same column share wiring ANO_2 and wiring V0 with pixels 230G[p+1,q] and pixels 230G[p+2,q] in adjacent columns (see arrow A in Figures 40A and 42B).
  • pixel 230R[p+1,q] shares openings 183 and 193 with pixels 230G[p+1,q] in adjacent columns (see arrow A in Figures 40A and 42B).
  • Pixels 230 in the same column share the wiring V1 with pixels 230 in adjacent columns. Specifically, pixels 230G[p+1,q] and pixels 230G[p+2,q] in the same column share the wiring V1 with pixels 230B[p+1,q] and pixels 230B[p+2,q] in adjacent columns (see arrow B in FIG. 42B). In addition, the wiring ANO_2 and wiring V0 shared between pixels 230 and the wiring V1 shared between pixels 230 are arranged alternately (see arrows A and B in FIG. 38 and FIG. 42B).
  • the wiring V0 corresponds to the conductive layer 112aB shown in FIG. 36A and the like. It can be said that the pixels 230 provided in the same column share the conductive layer 112aB (wiring V0) of the transistor M14 with the pixels 230 provided in the adjacent columns (see arrow A in FIG. 40A). In addition, the pixel 230 shares the semiconductor layer 208, conductive layer 212b, and opening 147b of the transistor M12 with the pixels 230 provided in the adjacent columns (see arrow A in FIG. 41B and FIG. 42A). Furthermore, the pixel 230 may share the insulating layer 120 with the pixels 230 provided in the adjacent columns. FIG.
  • FIG. 40B shows an example in which the pixel 230R[p+1,q] shares the insulating layer 120 with the pixel 230G[p+1,q] provided in the adjacent column (see arrow A in FIG. 40B).
  • the insulating layer 120 is provided so as to encompass the conductive layer 204 provided in the pixel 230R[p+1,q] and the conductive layer 204 provided in the pixel 230G[p+1,q].
  • the insulating layer 120 is provided in contact with the upper surface and side surface of the conductive layer 204 provided in the pixel 230R[p+1,q] and the upper surface and side surface of the conductive layer 204 provided in the pixel 230G[p+1,q]. Note that the insulating layer 120 does not have to be shared by adjacent pixels 230.
  • Pixels 230 in the same row share the wiring ANO_1 with pixels 230 in adjacent rows. Specifically, pixels 230R[p,q], 230G[p,q], 230B[p,q], 230R[p,q+1], 230G[p,q+1], and 230B[p,q+1] in the same row share the wiring ANO_1 with pixels 230R[p+1,q], 230G[p+1,q], 230B[p+1,q], 230R[p+1,q+1], 230G[p+1,q+1], and 230B[p+1,q+1] in adjacent rows (see arrow C in FIG. 42A).
  • Pixel 230 shares the conductive layer 112a, conductive layer 104s, opening 190, opening 194, and opening 191 of transistor M11 with pixels 230 in adjacent rows (see arrow D in Figures 40A, 42A, and 42B).
  • the pixels 230 in two adjacent rows and two adjacent columns share the conductive layer 104r, the opening 196, and the conductive layer 112bC of the transistor M16. Specifically, the pixels 230G[p+1,q], 230G[p+2,q], 230B[p+1,q], and 230B[p+2,q] share the conductive layer 104r and the conductive layer 112bC (see arrows B and D in Figures 41A, 42A, and 42B).
  • Figure 43A shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion are each cut away.
  • Display device 50A shown in FIG. 43A has transistor 205D, transistor 205R, transistor 205G, transistor 207G, transistor 207B, light-emitting element 130R, light-emitting element 130G, light-emitting element 130B, etc. between substrate 151 and substrate 152.
  • Light-emitting element 130R is a display element included in pixel 230R that emits red light
  • light-emitting element 130G is a display element included in pixel 230G that emits green light
  • light-emitting element 130B is a display element included in pixel 230B that emits blue light.
  • the display device 50A uses an SBS structure.
  • the SBS structure allows the material and configuration to be optimized for each light-emitting element, which increases the freedom of material and configuration selection and makes it easier to improve brightness and reliability.
  • the display device 50A is a top emission type.
  • transistors and the like can be arranged so as to overlap the light emitting region of the light emitting element, so the aperture ratio of the pixel can be increased compared to a bottom emission type.
  • Transistors 205D, 205R, 205G, 207G, and 207B are all formed on substrate 151. These transistors can be manufactured using some of the same processes.
  • One or more of the transistors 100 to 100D and the transistors 200 to 200B described above can be applied to any one or more of the transistors 205D, 205R, 205G, 207G, and 207B.
  • FIG. 43A shows a configuration example in which the transistor 100 described above is applied to the transistors 205D, 205R, and 205G, and the transistor 200 described above is applied to the transistors 207G and 207B.
  • a high-definition display device can be obtained by using one or more of the transistors 100 to 100D described above as the transistors provided in the display portion 162.
  • one or more of the highly saturable transistors 200 to 200B can be suitably used as the driving transistors of the light-emitting elements 130R, 130G, and 130B. This makes it possible to obtain a highly reliable display device.
  • the transistors 100 to 100D described above in the circuit portion 164 By using one or more of the transistors 100 to 100D described above in the circuit portion 164, a display device that operates at high speed can be obtained. Compared to the transistors provided in the display portion 162, the transistors provided in the circuit portion 164 may require a large on-state current. It is preferable to use a transistor with a short channel length in the circuit portion 164.
  • one or more of the transistors 100 to 100D described above can be suitably used in the circuit portion 164.
  • the occupied area can be reduced, and a display device with a narrow frame can be obtained.
  • one or more of the transistors 200 to 200B may be used in the circuit portion 164.
  • the transistors included in the display device of this embodiment are not limited to only the transistors included in the semiconductor device of one embodiment of the present invention.
  • the display device of this embodiment may have a combination of a transistor included in the semiconductor device of one embodiment of the present invention and a transistor having another structure.
  • the display device of this embodiment may have, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor.
  • the transistors included in the display device of this embodiment may be either a top-gate type or a bottom-gate type.
  • gates may be provided above and below a semiconductor layer in which a channel is formed.
  • Transistor 205D, transistor 205R, transistor 205G, transistor 207G, and transistor 207B can preferably be OS transistors.
  • the display device of this embodiment may have a Si transistor.
  • an OS transistor When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current in response to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, and the amount of current flowing to the light-emitting element can be controlled. This makes it possible to increase the number of gray levels in the pixel circuit.
  • an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to the light-emitting element, for example, even when there is variation in the current-voltage characteristics of the light-emitting element. In other words, when an OS transistor operates in the saturation region, the source-drain current hardly changes even when the source-drain voltage is changed, so the light emission luminance of the light-emitting element can be stabilized.
  • the transistors in the circuit unit 164 and the transistors in the display unit 162 may have the same structure or different structures.
  • the transistors in the circuit unit 164 may all have the same structure or may be of two or more types.
  • the transistors in the display unit 162 may all have the same structure or may be of two or more types.
  • All of the transistors in the display portion 162 may be OS transistors, all of the transistors in the display portion 162 may be Si transistors, or some of the transistors in the display portion 162 may be OS transistors and the rest may be Si transistors.
  • LTPS transistors and OS transistors are used in the display unit 162 to realize a display device with low power consumption and high driving capability.
  • a configuration in which LTPS transistors and OS transistors are combined is sometimes called LTPO.
  • a more suitable example is a configuration in which OS transistors are used as transistors that function as switches for controlling conduction/non-conduction between wirings, and LTPS transistors are used as transistors for controlling current.
  • one of the transistors in the display unit 162 functions as a transistor for controlling the current flowing to the light-emitting element, and can also be called a driving transistor.
  • One of the source and drain of the driving transistor is electrically connected to the pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor as the driving transistor. This makes it possible to increase the current flowing to the light-emitting element in the pixel circuit.
  • the other transistor in the display unit 162 functions as a switch for controlling pixel selection/non-selection and can also be called a selection transistor.
  • the gate of the selection transistor is electrically connected to a gate line, and one of the source and drain is electrically connected to a source line (signal line). It is preferable to use an OS transistor as the selection transistor. This makes it possible to maintain the gradation of the pixel even if the frame frequency is significantly reduced (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.
  • An insulating layer 195 is provided to cover transistors 205D, 205R, 205G, 207G, and 207B, and an insulating layer 235 is provided on insulating layer 195.
  • Light emitting elements 130R, 130G, and 130B are provided on insulating layer 235.
  • the light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R.
  • the light-emitting element 130R shown in FIG. 43A emits red light (R).
  • the EL layer 113R has a light-emitting layer that emits red light.
  • the light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G.
  • the light-emitting element 130G shown in FIG. 43A emits green light (G).
  • the EL layer 113G has a light-emitting layer that emits green light.
  • the light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B.
  • the light-emitting element 130B shown in FIG. 43A emits blue light (B).
  • the EL layer 113B has a light-emitting layer that emits blue light.
  • EL layers 113R, 113G, and 113B are all shown to have the same thickness, but this is not limited to the above.
  • EL layers 113R, 113G, and 113B may each have a different thickness.
  • the pixel electrode 111R is electrically connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layer 106, the insulating layer 195, and the insulating layer 235.
  • the pixel electrode 111G is electrically connected to the conductive layer 112b of the transistor 205G
  • the pixel electrode 111B is electrically connected to the conductive layer 112b of the transistor 205B (not shown).
  • the ends of each of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237.
  • the insulating layer 237 functions as a partition wall.
  • the insulating layer 237 can be formed in a single layer structure or a multilayer structure using one or both of an inorganic insulating material and an organic insulating material.
  • the material that can be used for the insulating layer 195 and the material that can be used for the insulating layer 235 can be used for the insulating layer 237.
  • the insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.
  • the insulating layer 237 is provided at least in the display section 162.
  • the insulating layer 237 may be provided not only in the display section 162, but also in the connection section 140 and the circuit section 164.
  • the insulating layer 237 may also be provided up to the edge of the display device 50A.
  • the common electrode 115 is a continuous film that is provided in common to the light-emitting elements 130R, 130G, and 130B.
  • the common electrode 115 that is shared by the multiple light-emitting elements is electrically connected to a conductive layer 123 provided in the connection portion 140.
  • a conductive layer 123 it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.
  • a conductive film that transmits visible light is used for the electrode from which light is extracted, between the pixel electrode and the common electrode. It is preferable to use a conductive film that reflects visible light for the electrode from which light is not extracted.
  • a conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted.
  • the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.
  • metals, alloys, electrically conductive compounds, and mixtures thereof can be appropriately used.
  • the material include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations.
  • examples of the material include indium tin oxide (In-Sn oxide, also called ITO), In-Si-Sn oxide (also called ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide.
  • examples of the material include alloys containing aluminum (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and alloys containing silver, such as an alloy of silver and magnesium, and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also called APC).
  • Such materials include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not listed above, rare earth metals such as europium and ytterbium, and alloys containing appropriate combinations of these, graphene, etc.
  • the light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transparent and semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode).
  • the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.
  • the light transmittance of the transparent electrode is 40% or more.
  • the visible light reflectance of the semi-transmissive/semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less.
  • the visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less.
  • the resistivity of these electrodes is preferably 1 ⁇ 10 ⁇ 2 ⁇ cm or less.
  • the EL layers 113R, 113G, and 113B are each provided in an island shape.
  • the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap.
  • the ends of adjacent EL layers may overlap as shown in FIG. 43A, but this is not limited to this. In other words, adjacent EL layers may not overlap and may be separated from each other.
  • the EL layers 113R, 113G, and 113B each have at least a light-emitting layer.
  • the light-emitting layer has one or more types of light-emitting materials.
  • a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used.
  • a material that emits near-infrared light can also be used as the light-emitting material.
  • Light-emitting materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.
  • the light-emitting layer may have one or more organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material).
  • the one or more organic compounds one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) can be used.
  • a bipolar substance a substance with high electron transport properties and hole transport properties
  • a TADF material may be used as the one or more organic compounds.
  • the light-emitting layer preferably has, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex.
  • ExTET Exciplex-Triple Energy Transfer
  • the energy transfer becomes smooth and light emission can be efficiently obtained.
  • the EL layer may have one or more of a layer containing a substance with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a substance with high electron blocking properties (electron blocking layer), a layer containing a substance with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a substance with high hole blocking properties (hole blocking layer).
  • the EL layer may contain one or both of a bipolar substance and a TADF material.
  • Eigen elements can be made of either low molecular weight compounds or high molecular weight compounds, and may contain inorganic compounds.
  • the layers constituting the luminescent element can be formed by deposition methods (including vacuum deposition methods), transfer methods, printing methods, inkjet methods, coating methods, etc.
  • the light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units).
  • the light-emitting unit has at least one light-emitting layer.
  • the tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer has the function of injecting electrons into one of the two light-emitting units and injecting holes into the other.
  • the tandem structure makes it possible to obtain a light-emitting element capable of emitting light with high brightness. Furthermore, the tandem structure can reduce the current required to obtain the same brightness compared to the single structure, thereby improving reliability.
  • the tandem structure may also be called a stack structure.
  • EL layer 113R has a structure having multiple light-emitting units that emit red light
  • EL layer 113G has a structure having multiple light-emitting units that emit green light
  • EL layer 113B has a structure having multiple light-emitting units that emit blue light.
  • a protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B.
  • the protective layer 131 and the substrate 152 are bonded via an adhesive layer 142.
  • the substrate 152 is provided with a light-shielding layer 117.
  • a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements.
  • the space between the substrates 152 and 151 is filled with an adhesive layer 142, and a solid sealing structure is applied.
  • the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied.
  • the adhesive layer 142 may be provided so as not to overlap with the light-emitting elements.
  • the space may also be filled with a resin different from the adhesive layer 142 provided in a frame shape.
  • the protective layer 131 is provided at least on the display section 162, and is preferably provided so as to cover the entire display section 162.
  • the protective layer 131 is preferably provided so as to cover not only the display section 162, but also the connection section 140 and the circuit section 164.
  • the protective layer 131 is also preferably provided up to the end of the display device 50A.
  • the connection section 197 has a portion where the protective layer 131 is not provided in order to electrically connect the FPC 172 and the conductive layer 166.
  • the reliability of the light-emitting elements can be improved.
  • the protective layer 131 may have a single layer structure or a laminated structure of two or more layers.
  • the conductivity of the protective layer 131 does not matter.
  • At least one of an insulating film, a semiconductor film, and a conductive film can be used as the protective layer 131.
  • the protective layer 131 has an inorganic film, which prevents oxidation of the common electrode 115 and prevents impurities (such as moisture and oxygen) from entering the light-emitting element, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.
  • An inorganic insulating film can be used for the protective layer 131.
  • materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides. Specific examples of these inorganic insulating films are as described above.
  • the protective layer 131 preferably contains a nitride or a nitride oxide, and more preferably contains a nitride.
  • the protective layer 131 may be an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, IGZO, or the like.
  • the inorganic film preferably has a high resistance, specifically, a higher resistance than the common electrode 115.
  • the inorganic film may further contain nitrogen.
  • the protective layer 131 has high transparency to visible light.
  • ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.
  • the protective layer 131 may be, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an IGZO film on the aluminum oxide film. By using this laminated structure, it is possible to prevent impurities (water, oxygen, etc.) from entering the EL layer side.
  • the protective layer 131 may have an organic film.
  • the protective layer 131 may have both an organic film and an inorganic film.
  • An example of an organic film that can be used for the protective layer 131 is an organic insulating film that can be used for the insulating layer 235.
  • connection portion 197 is provided in an area of the substrate 151 where the substrate 152 does not overlap.
  • the conductive layer 165 is electrically connected to the FPC 172 via the conductive layer 166 and the connection layer 242.
  • the conductive layer 165 is an example of a single-layer structure of a conductive layer obtained by processing the same conductive film as the conductive layer 112b.
  • the conductive layer 166 is an example of a single-layer structure of a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B.
  • the conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection portion 197 and the FPC 172 to be electrically connected via the connection layer 242.
  • the display device 50A is a top emission type. Light emitted by the light emitting elements is emitted towards the substrate 152. It is preferable to use a material that is highly transparent to visible light for the substrate 152.
  • the pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the opposing electrode (common electrode 115) contains a material that transmits visible light.
  • the light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, in the circuit section 164, etc.
  • a colored layer such as a color filter may be provided on the surface of substrate 152 facing substrate 151 or on protective layer 131. By providing a color filter over the light-emitting element, the color purity of the light emitted from the pixel can be increased.
  • the colored layers are colored layers that selectively transmit light in a specific wavelength range and absorb light in other wavelength ranges.
  • a red (R) color filter that transmits light in the red wavelength range
  • a green (G) color filter that transmits light in the green wavelength range
  • a blue (B) color filter that transmits light in the blue wavelength range
  • R red
  • G green
  • B blue
  • metal materials, resin materials, pigments, and dyes can be used.
  • the colored layers are formed at the desired positions by a printing method, an inkjet method, an etching method using photolithography, or the like.
  • optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 151).
  • optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light collecting film.
  • a surface protection layer such as an antistatic film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches due to use, and an impact absorbing layer may be arranged on the outside of the substrate 152.
  • a glass layer or a silica layer As the surface protection layer, it is possible to suppress the occurrence of surface contamination and scratches, which is preferable.
  • DLC diamond-like carbon
  • AlO x aluminum oxide
  • a polyester-based material a polycarbonate-based material, or the like
  • the substrates 151 and 152 may each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like.
  • a material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. If a flexible material is used for the substrates 151 and 152, the flexibility of the display device can be increased, and a flexible display can be realized.
  • a polarizing plate may also be used for at least one of the substrates 151 and 152.
  • the substrates 151 and 152 may each be made of polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of the substrates 151 and 152 may be made of glass having a thickness sufficient to provide flexibility.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • polyacrylonitrile resin acrylic resin
  • polyimide resin polymethyl methacrylate resin
  • a substrate with high optical isotropy has small birefringence (it can also be said that the amount of birefringence is small).
  • films with high optical isotropy include triacetyl cellulose (TAC, also known as cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.
  • curing adhesives such as photo-curing adhesives such as ultraviolet curing adhesives, reactive curing adhesives, heat curing adhesives, and anaerobic adhesives.
  • photo-curing adhesives such as ultraviolet curing adhesives, reactive curing adhesives, heat curing adhesives, and anaerobic adhesives.
  • These adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin.
  • materials with low moisture permeability such as epoxy resin are preferable.
  • Two-part mixed resins may also be used.
  • Adhesive sheets, etc. may also be used.
  • connection layer 242 an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), etc. can be used.
  • ACF anisotropic conductive film
  • ACP anisotropic conductive paste
  • FIG. 43B shows an example of a cross section of the display unit 162 of the display device 50B.
  • the display device 50B is mainly different from the display device 50A in that a light-emitting element having a common EL layer 113 and a colored layer (such as a color filter) are used in each subpixel of each color.
  • the configuration shown in FIG. 43B can be combined with the region including the FPC 172, the circuit portion 164, the laminated structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection portion 140, and the configuration of the end portion shown in FIG. 43A. Note that in the following description of the display device, the description of the same parts as those of the display device described above may be omitted.
  • the display device 50B shown in FIG. 43B has light emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.
  • the light-emitting element 130R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.
  • the light-emitting element 130G has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.
  • the light-emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.
  • Light-emitting elements 130R, 130G, and 130B each share an EL layer 113 and a common electrode 115.
  • a configuration in which a common EL layer 113 is provided for the subpixels of each color can reduce the number of manufacturing steps compared to a configuration in which a different EL layer is provided for each subpixel of each color.
  • the light-emitting elements 130R, 130G, and 130B shown in FIG. 43B emit white light.
  • the white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B to obtain light of the desired color.
  • a light-emitting element that emits white light preferably includes two or more light-emitting layers.
  • light-emitting layers can be selected such that the emission colors of the two light-emitting layers are complementary to each other. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration can be obtained in which the light-emitting element as a whole emits white light.
  • the emission colors of the three or more light-emitting layers can be combined to obtain a configuration in which the light-emitting element as a whole emits white light.
  • the EL layer 113 preferably has, for example, a light-emitting layer having a light-emitting material that emits blue light, and a light-emitting layer having a light-emitting material that emits visible light with a longer wavelength than blue.
  • the EL layer 113 preferably has, for example, a light-emitting layer that emits yellow light, and a light-emitting layer that emits blue light.
  • the EL layer 113 preferably has, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.
  • a tandem structure For light-emitting elements that emit white light, it is preferable to use a tandem structure. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having, in this order, a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green or green light, and a light-emitting unit that emits blue light, or a three-stage tandem structure having, in this order, a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green or green light, and red light, and a light-emitting unit that emits blue light, etc.
  • the number of layers and the order of colors of the light-emitting units can be, from the anode side, a two-layer structure of B and light-emitting unit X, a two-layer structure of B, Y, and B, or a three-layer structure of B, X, and B.
  • the number of layers and the order of colors of the light-emitting layers in light-emitting unit X can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R.
  • another layer may be provided between the two light-emitting layers.
  • a light-emitting element configured to emit white light may emit light of a specific wavelength, such as red, green, or blue, with the light being enhanced.
  • the light-emitting elements 130R, 130G, and 130B shown in FIG. 43B emit blue light.
  • the EL layer 113 has one or more light-emitting layers that emit blue light.
  • the blue light emitted by the light-emitting element 130B can be extracted.
  • a color conversion layer is provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 152, so that the blue light emitted by the light-emitting element 130R or the light-emitting element 130G can be converted into light with a longer wavelength, and red or green light can be extracted. Furthermore, it is preferable to provide a colored layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a colored layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G.
  • a part of the light emitted by the light-emitting element may be transmitted as it is without being converted by the color conversion layer.
  • the color conversion layer By extracting the light that has passed through the color conversion layer via the colored layer, light other than the desired color is absorbed by the colored layer, and the color purity of the light emitted by the subpixel can be increased.
  • a display device 50C shown in FIG. 44 differs from the display device 50B mainly in that it is a bottom emission type display device.
  • Light emitted by the light-emitting element is emitted toward the substrate 151. It is preferable to use a material that is highly transparent to visible light for the substrate 151. On the other hand, the translucency of the material used for the substrate 152 does not matter.
  • FIG. 44 shows an example in which the light-shielding layer 117 is provided on the substrate 151, the insulating layer 153 is provided on the light-shielding layer 117, and the transistors 205D, 205R (not shown), 205G, 207G, and 207B are provided on the insulating layer 153.
  • the colored layer 132R and the colored layer 132G are provided on the insulating layer 195, and the insulating layer 195 is provided on the colored layer 132R and the colored layer 132G.
  • the light-emitting element 130R which overlaps with the colored layer 132R, has a pixel electrode 111R, an EL layer 113, and a common electrode 115.
  • the light-emitting element 130G which overlaps with the colored layer 132G, has a pixel electrode 111G, an EL layer 113, and a common electrode 115.
  • the light-emitting element 130B which overlaps with the colored layer 132B, has a pixel electrode 111B, an EL layer 113, and a common electrode 115.
  • the pixel electrodes 111R, 111G, and 111B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom-emission display device, a metal with low electrical resistivity can be used for the common electrode 115, which makes it possible to suppress voltage drops caused by the resistance of the common electrode 115 and achieve high display quality.
  • the transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced, so that in a display device with a bottom emission structure, the pixel aperture ratio can be increased or the pixel size can be reduced.
  • a display device 50D shown in FIG. 45A differs from the display device 50A mainly in that a light receiving element 130S is included.
  • Display device 50D has a light-emitting element and a light-receiving element in each pixel.
  • display device 50D it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element.
  • the organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device that uses an organic EL element.
  • display unit 162 has one or both of an imaging function and a sensing function. For example, in addition to displaying an image using all of the sub-pixels of display device 50D, some of the sub-pixels can provide light as a light source, some other sub-pixels can perform light detection, and the remaining sub-pixels can display the image.
  • the display device 50D it is not necessary to provide a light receiving unit and a light source separately from the display device 50D, and the number of parts in the electronic device can be reduced. For example, it is not necessary to provide a separate biometric authentication device in the electronic device, or a capacitive touch panel for scrolling, etc. Therefore, by using the display device 50D, it is possible to provide an electronic device with reduced manufacturing costs.
  • the display device 50D can capture an image using the light receiving element.
  • the image sensor can be used to capture images for personal authentication using a fingerprint, palm print, iris, pulse shape (including vein shape and artery shape), face, etc.
  • the light receiving element can be used as a touch sensor (also called a direct touch sensor) or a non-contact sensor (also called a hover sensor, hover touch sensor, or touchless sensor).
  • a touch sensor can detect an object (such as a finger, hand, or pen) when the display device comes into direct contact with the object.
  • a non-contact sensor can detect an object even if the object does not come into contact with the display device.
  • the light receiving element 130S has a pixel electrode 111S on an insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 115 on the functional layer 113S.
  • Light Lin is incident on the functional layer 113S from outside the display device 50D.
  • the pixel electrode 111S is electrically connected to the conductive layer 112b of the transistor 205S through openings provided in the insulating layer 106, the insulating layer 195, and the insulating layer 235.
  • the ends of the pixel electrode 111S are covered by an insulating layer 237.
  • the common electrode 115 is a continuous film provided in common to the light receiving element 130S, the light emitting element 130R (not shown), the light emitting element 130G, and the light emitting element 130B.
  • the common electrode 115 shared by the light emitting element and the light receiving element is electrically connected to the conductive layer 123 provided in the connection portion 140.
  • the functional layer 113S has at least an active layer (also called a photoelectric conversion layer).
  • the active layer includes a semiconductor.
  • the semiconductor include inorganic semiconductors such as silicon, and organic semiconductors including organic compounds.
  • an organic semiconductor is used as the semiconductor in the active layer.
  • the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition), which is preferable because the manufacturing equipment can be shared.
  • the functional layer 113S may further include a layer containing a material with high hole transport properties, a material with high electron transport properties, or a bipolar material, as a layer other than the active layer.
  • the functional layer 113S may further include a layer containing a material with high hole injection properties, a hole blocking material, a material with high electron injection properties, or an electron blocking material.
  • the materials that can be used in the light-emitting element described above can be used for the functional layer 113S.
  • the light receiving element can be made of either a low molecular weight compound or a high molecular weight compound, and may contain an inorganic compound.
  • the layers that make up the light receiving element can be formed by a deposition method (including vacuum deposition), a transfer method, a printing method, an inkjet method, a coating method, etc.
  • Display device 50D shown in Figures 45B and 45C has a layer 353 having light receiving elements, a circuit layer 355, and a layer 357 having light emitting elements between substrate 151 and substrate 152.
  • Layer 353 has, for example, light receiving element 130S.
  • Layer 357 has, for example, light emitting elements 130R, 130G, and 130B.
  • Circuit layer 355 has a circuit that drives the light receiving element and a circuit that drives the light emitting element.
  • Circuit layer 355 has, for example, transistors 205R, 205G, and 205B.
  • circuit layer 355 may be provided with one or more of a switch, a capacitance, a resistance, wiring, and a terminal.
  • Figure 45B shows an example in which the light receiving element 130S is used as a touch sensor. As shown in Figure 45B, light emitted by the light emitting element in layer 357 is reflected by a finger 352 that touches the display device 50D, and the light receiving element in layer 353 detects the reflected light. This makes it possible to detect that the finger 352 has touched the display device 50D.
  • Figure 45C shows an example in which the light receiving element 130S is used as a non-contact sensor. As shown in Figure 45C, light emitted by a light emitting element in layer 357 is reflected by a finger 352 that is close to (i.e., not in contact with) the display device 50D, and the light receiving element in layer 353 detects the reflected light.
  • the display device 50E shown in FIG. 46A is an example of a display device to which the MML (metal maskless) structure is applied.
  • the display device 50E has a light-emitting element manufactured without using a fine metal mask.
  • the laminated structure from the substrate 151 to the insulating layer 235 and the laminated structure from the protective layer 131 to the substrate 152 are the same as those of the display device 50A, and therefore the description thereof will be omitted.
  • light-emitting elements 130R, 130G, and 130B are provided on insulating layer 235.
  • the light-emitting element 130R has a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114.
  • the light-emitting element 130R shown in FIG. 46A emits red light (R).
  • the layer 133R has a light-emitting layer that emits red light.
  • the layer 133R and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layer 124R and the conductive layer 126R can be referred to as a pixel electrode.
  • the light-emitting element 130G has a conductive layer 124G on the insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114.
  • the light-emitting element 130G shown in FIG. 46A emits green light (G).
  • the layer 133G has a light-emitting layer that emits green light.
  • the layer 133G and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layer 124G and the conductive layer 126G can be referred to as a pixel electrode.
  • the light-emitting element 130B has a conductive layer 124B on the insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114.
  • the light-emitting element 130B shown in FIG. 46A emits blue light (B).
  • the layer 133B has a light-emitting layer that emits blue light.
  • the layer 133B and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layer 124B and the conductive layer 126B can be referred to as a pixel electrode.
  • layers provided in an island shape for each light-emitting element are indicated as layer 133B, layer 133G, or layer 133R, and a layer shared by a plurality of light-emitting elements is indicated as common layer 114.
  • layers 133R, 133G, and 133B may be referred to as island-shaped EL layers or EL layers formed in an island shape, without including common layer 114.
  • Layer 133R, layer 133G, and layer 133B are separated from each other.
  • the EL layer in an island shape for each light-emitting element, it is possible to suppress leakage current between adjacent light-emitting elements. This makes it possible to prevent unintended light emission caused by crosstalk, and to realize a display device with extremely high contrast.
  • layers 133R, 133G, and 133B are all shown to have the same thickness, but this is not limited to this. Layers 133R, 133G, and 133B may each have a different thickness.
  • the conductive layer 124R is electrically connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layer 106, the insulating layer 195, and the insulating layer 235.
  • the conductive layer 124G is electrically connected to the conductive layer 112b of the transistor 205G
  • the conductive layer 124B is electrically connected to the conductive layer 112b of the transistor 205B.
  • the conductive layers 124R, 124G, and 124B are formed to cover the openings provided in the insulating layer 235.
  • Layer 128 is embedded in the recesses of the conductive layers 124R, 124G, and 124B, respectively.
  • Layer 128 has the function of planarizing the recesses of conductive layers 124R, 124G, and 124B.
  • Conductive layers 126R, 126G, and 126B that are electrically connected to conductive layers 124R, 124G, and 124B are provided on conductive layers 124R, 124G, and 124B and layer 128. Therefore, the regions that overlap with the recesses of conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, and the aperture ratio of the pixel can be increased. It is preferable to use a conductive layer that functions as a reflective electrode for conductive layer 124R and conductive layer 126R.
  • Layer 128 may be an insulating layer or a conductive layer.
  • Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for layer 128.
  • layer 128 is preferably formed using an insulating material, and is particularly preferably formed using an organic insulating material.
  • the organic insulating material that can be used for insulating layer 237 described above can be used for layer 128.
  • FIG. 46A shows an example in which the top surface of layer 128 has a flat portion, but the shape of layer 128 is not particularly limited.
  • the top surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.
  • the height of the upper surface of layer 128 and the height of the upper surface of conductive layer 124R may be the same or approximately the same, or may be different from each other.
  • the height of the upper surface of layer 128 may be lower or higher than the height of the upper surface of conductive layer 124R.
  • the end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or may cover the side of the end of the conductive layer 124R.
  • the ends of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape.
  • the ends of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees.
  • the layer 133R provided along the side of the pixel electrode has an inclined portion.
  • the conductive layers 124G, 126G and the conductive layers 124B, 126B are similar to the conductive layers 124R, 126R, so detailed description will be omitted.
  • conductive layer 126R The upper and side surfaces of conductive layer 126R are covered by layer 133R. Similarly, the upper and side surfaces of conductive layer 126G are covered by layer 133G, and the upper and side surfaces of conductive layer 126B are covered by layer 133B. Therefore, the entire area in which conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting area of light-emitting elements 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixel.
  • a portion of the top surface and the side surfaces of layers 133R, 133G, and 133B are covered with insulating layers 125 and 127.
  • a common layer 114 is provided on layers 133R, 133G, 133B, and insulating layers 125 and 127, and a common electrode 115 is provided on common layer 114.
  • Common layer 114 and common electrode 115 are each a continuous film provided in common to multiple light-emitting elements.
  • the insulating layer 237 shown in FIG. 43A and the like is not provided between the conductive layer 126R and the layer 133R.
  • the display device 50E does not have an insulating layer (also called a partition, bank, spacer, etc.) that contacts the pixel electrode and covers the upper end of the pixel electrode. Therefore, the distance between adjacent light-emitting elements can be made extremely narrow. This makes it possible to provide a high-definition or high-resolution display device.
  • a mask e.g., a photomask
  • a photomask for forming the insulating layer is not required, which reduces the manufacturing cost of the display device.
  • each of the layers 133R, 133G, and 133B has a light-emitting layer.
  • Each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer.
  • each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer.
  • each of the layers 133R, 133G, and 133B preferably has a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer. Since the surfaces of the layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, by providing one or both of the carrier transport layer and the carrier block layer on the light-emitting layer, it is possible to suppress exposure of the light-emitting layer to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting element.
  • the common layer 114 has, for example, an electron injection layer or a hole injection layer.
  • the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or a hole transport layer and a hole injection layer stacked together.
  • the common layer 114 is shared by the light emitting elements 130R, 130G, and 130B.
  • Insulating layer 125 covers the sides of layers 133R, 133G, and 133B via insulating layer 125.
  • the side surfaces (and even parts of the top surfaces) of layers 133R, 133G, and 133B are covered with at least one of insulating layers 125 and 127, which prevents the common layer 114 (or common electrode 115) from coming into contact with the pixel electrodes and the side surfaces of layers 133R, 133G, and 133B, thereby preventing short circuits in the light-emitting elements. This improves the reliability of the light-emitting elements.
  • the insulating layer 125 contacts the side surfaces of the layers 133R, 133G, and 133B. By configuring the insulating layer 125 to contact the layers 133R, 133G, and 133B, peeling of the layers 133R, 133G, and 133B can be prevented, and the reliability of the light-emitting element can be improved.
  • the insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses in the insulating layer 125. It is preferable that the insulating layer 127 covers at least a portion of the side surface of the insulating layer 125.
  • the gap between adjacent island-shaped layers can be filled, reducing the large unevenness of the surface on which layers (such as the carrier injection layer and the common electrode) are formed on the island-shaped layers, making it possible to make the surface flatter. This improves the coverage of the carrier injection layer, the common electrode, etc.
  • the common layer 114 and the common electrode 115 are provided on the layers 133R, 133G, and 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, there is a step between the region where the pixel electrode and the island-shaped EL layer are provided and the region (region between the light-emitting elements) where the pixel electrode and the island-shaped EL layer are not provided. In the display device of one embodiment of the present invention, the step can be flattened by having the insulating layer 125 and the insulating layer 127, and the coverage of the common layer 114 and the common electrode 115 can be improved. Therefore, poor connection due to step disconnection can be suppressed. In addition, the step can be suppressed from locally thinning the common electrode 115 and increasing the electrical resistance.
  • the upper surface of the insulating layer 127 has a shape with high flatness.
  • the upper surface of the insulating layer 127 may have at least one of a flat surface, a convex curved surface, and a concave curved surface.
  • the upper surface of the insulating layer 127 has a convex curved shape with a large radius of curvature.
  • An inorganic insulating film can be used for the insulating layer 125.
  • materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides. Specific examples of these inorganic insulating films are as described above.
  • the insulating layer 125 may have a single-layer structure or a laminated structure. In particular, aluminum oxide is preferable because it has a high selectivity with respect to the EL layer in etching and has a function of protecting the EL layer in the formation of the insulating layer 127 described later.
  • the insulating layer 125 may have a laminated structure of a film formed by the ALD method and a film formed by the sputtering method.
  • the insulating layer 125 may have a laminated structure of, for example, an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.
  • the insulating layer 125 preferably has a function as a barrier insulating layer against at least one of water and oxygen.
  • the insulating layer 125 preferably has a function of suppressing the diffusion of at least one of water and oxygen.
  • the insulating layer 125 preferably has a function of capturing or fixing (also called gettering) at least one of water and oxygen.
  • the insulating layer 125 functions as a barrier insulating layer, making it possible to suppress the intrusion of impurities (typically at least one of water and oxygen) that may diffuse from the outside into each light-emitting element. This configuration makes it possible to provide a highly reliable light-emitting element and further a highly reliable display device.
  • impurities typically at least one of water and oxygen
  • the insulating layer 125 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and causing deterioration of the EL layer. In addition, by lowering the impurity concentration in the insulating layer 125, the barrier properties against at least one of water and oxygen can be improved. For example, it is desirable that the insulating layer 125 has a sufficiently low hydrogen concentration or carbon concentration, or preferably both.
  • the insulating layer 127 provided on the insulating layer 125 has the function of flattening the unevenness of the insulating layer 125 formed between adjacent light-emitting elements. In other words, the presence of the insulating layer 127 has the effect of improving the flatness of the surface on which the common electrode 115 is formed.
  • an insulating layer containing an organic material can be suitably used.
  • the organic material it is preferable to use a photosensitive organic resin, for example, a photosensitive resin composition containing an acrylic resin.
  • acrylic resin does not only refer to polymethacrylic acid ester or methacrylic resin, but may refer to acrylic polymers in a broad sense.
  • the insulating layer 127 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins.
  • the insulating layer 127 may be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin.
  • PVA polyvinyl alcohol
  • the photosensitive resin may be a photoresist.
  • the photosensitive organic resin may be either a positive-type material or a negative-type material.
  • the insulating layer 127 may be made of a material that absorbs visible light. By having the insulating layer 127 absorb the light emitted from the light-emitting element, it is possible to suppress leakage of light from the light-emitting element to an adjacent light-emitting element through the insulating layer 127 (stray light). This can improve the display quality of the display device. In addition, since the display quality can be improved without using a polarizing plate in the display device, it is possible to reduce the weight and thickness of the display device.
  • Materials that absorb visible light include materials containing pigments such as black, materials containing dyes, resin materials with light absorbing properties (such as polyimide), and resin materials that can be used in color filters (color filter materials).
  • resin materials that can be used in color filters color filter materials.
  • by mixing three or more colors of color filter materials it is possible to create a resin layer that is black or close to black.
  • Fig. 46B shows an example of a cross section of the display unit 162 of the display device 50F.
  • the display device 50F is mainly different from the display device 50E in that a colored layer (such as a color filter) is provided in each subpixel of each color.
  • the configuration shown in Fig. 46B can be combined with the region including the FPC 172, the circuit portion 164, the laminated structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection portion 140, and the configuration of the end portion shown in Fig. 46A.
  • the display device 50F shown in FIG. 46B has light emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.
  • the light emitted by the light-emitting element 130R is extracted as red light to the outside of the display device 50F via the colored layer 132R.
  • the light emitted by the light-emitting element 130G is extracted as green light to the outside of the display device 50F via the colored layer 132G.
  • the light emitted by the light-emitting element 130B is extracted as blue light to the outside of the display device 50F via the colored layer 132B.
  • Each of the light-emitting elements 130R, 130G, and 130B has a layer 133. These three layers 133 are formed using the same material and in the same process. In addition, these three layers 133 are separated from one another. By providing an island-like EL layer for each light-emitting element, it is possible to suppress leakage current between adjacent light-emitting elements. This makes it possible to prevent unintended light emission due to crosstalk, and to realize a display device with extremely high contrast.
  • the light-emitting elements 130R, 130G, and 130B shown in FIG. 46B emit white light.
  • the white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B to obtain light of the desired color.
  • the light-emitting elements 130R, 130G, and 130B shown in FIG. 46B emit blue light.
  • the layer 133 has one or more light-emitting layers that emit blue light.
  • the blue light emitted by the light-emitting element 130B can be extracted.
  • a color conversion layer is provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 152, so that the blue light emitted by the light-emitting element 130R or the light-emitting element 130G can be converted into light with a longer wavelength, and red or green light can be extracted.
  • a display device 50G shown in FIG. 47 differs from the display device 50F mainly in that it is a bottom emission type display device.
  • Light emitted by the light-emitting element is emitted toward the substrate 151. It is preferable to use a material that is highly transparent to visible light for the substrate 151. On the other hand, the translucency of the material used for the substrate 152 does not matter.
  • FIG. 47 shows an example in which the light-shielding layer 117 is provided on the substrate 151, the insulating layer 153 is provided on the light-shielding layer 117, and the transistors 205D, 205R (not shown), 205G, and 205B are provided on the insulating layer 153.
  • the colored layers 132R, 132G, and 132B are provided on the insulating layer 195, and the insulating layer 235 is provided on the colored layers 132R, 132G, and 132B.
  • the light-emitting element 130R which overlaps with the colored layer 132R, has a conductive layer 124R, a conductive layer 126R, a layer 133, a common layer 114, and a common electrode 115.
  • the light-emitting element 130G which overlaps with the colored layer 132G, has a conductive layer 124G, a conductive layer 126G, a layer 133, a common layer 114, and a common electrode 115.
  • the light-emitting element 130B which overlaps with the colored layer 132B, has a conductive layer 124B, a conductive layer 126B, a layer 133, a common layer 114, and a common electrode 115.
  • the conductive layers 124R, 124G, 124B, 126R, 126G, and 126B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom emission display device, a metal with low electrical resistivity can be used for the common electrode 115, so that voltage drops caused by the resistance of the common electrode 115 can be suppressed, and high display quality can be achieved.
  • the transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced, so that in a display device with a bottom emission structure, the pixel aperture ratio can be increased or the pixel size can be reduced.
  • a display device 50H shown in FIG. 48 is a VA mode liquid crystal display device.
  • Substrate 151 and substrate 152 are bonded together by adhesive layer 144.
  • Liquid crystal 262 is sealed in the area surrounded by substrate 151, substrate 152, and adhesive layer 144.
  • Polarizing plate 260a is located on the outer surface of substrate 152
  • polarizing plate 260b is located on the outer surface of substrate 151.
  • a backlight can be provided outside polarizing plate 260a or polarizing plate 260b.
  • Transistors 205D, 205R, and 205G, a connection portion 197, a spacer 224, and the like are provided on the substrate 151.
  • the transistor 205D is provided in the circuit portion 164, and the transistors 205R and 205G are provided in the display portion 162.
  • the conductive layer 112b of the transistors 205R and 205G functions as a pixel electrode of the liquid crystal element 60.
  • the substrate 152 is provided with colored layers 132R and 132G, a light-shielding layer 117, an insulating layer 225, a conductive layer 263, etc.
  • the conductive layer 263 functions as a common electrode for the liquid crystal element 60.
  • Transistors 205D, 205R, and 205G each have a conductive layer 112a, a semiconductor layer 108, an insulating layer 106, a conductive layer 104, and a conductive layer 112b.
  • the conductive layer 112a functions as one of the source electrode and the drain electrode, and the conductive layer 112b functions as the other of the source electrode and the drain electrode.
  • the conductive layer 104 functions as a gate electrode.
  • a part of the insulating layer 106 functions as a gate insulating layer.
  • the display device 50H includes transistors of one embodiment of the present invention in both the display portion 162 and the circuit portion 164.
  • the pixel size can be reduced, leading to higher resolution.
  • the area occupied by the circuit portion 164 can be reduced, leading to a narrower frame.
  • Transistors 205D, 205R, and 205G are covered with an insulating layer 195.
  • the insulating layer 195 functions as a protective layer for transistors 205D, 205R, and 205G.
  • the subpixels of the display unit 162 each have a transistor, a liquid crystal element 60, and a colored layer.
  • a subpixel that emits red light has a transistor 205R, a liquid crystal element 60, and a colored layer 132R that transmits red light.
  • a subpixel that emits green light has a transistor 205G, a liquid crystal element 60, and a colored layer 132G that transmits green light.
  • a subpixel that emits blue light similarly has a transistor, a liquid crystal element 60, and a colored layer that transmits blue light.
  • the liquid crystal element 60 has a conductive layer 112b, a conductive layer 263, and a liquid crystal 262 sandwiched between them.
  • a conductive layer 264 is provided, which is located on the same plane as the conductive layer 112a.
  • the conductive layer 264 has a portion that overlaps with the conductive layer 112b via the insulating layer 110 (insulating layer 110a, insulating layer 110b, and insulating layer 110c).
  • a storage capacitance is formed by the conductive layer 112b, the conductive layer 264, and the insulating layer 110 between them. Note that it is sufficient that there is one or more insulating layers between the conductive layer 112b and the conductive layer 264, and one or two of the insulating layers 110 may be removed by etching.
  • an insulating layer 225 is provided to cover the colored layers 132R and 132G and the light-shielding layer 117.
  • the insulating layer 225 may function as a planarizing film.
  • the insulating layer 225 can make the surface of the conductive layer 263 roughly flat, so that the orientation state of the liquid crystal 262 can be made uniform.
  • an alignment film for controlling the alignment of the liquid crystal 262 may be provided on the surfaces of the conductive layer 263 and the insulating layer 195, etc. that come into contact with the liquid crystal 262 (see the alignment film 265 in Figures 50A and 50B).
  • the conductive layer 112b and the conductive layer 263 transmit visible light.
  • it can be a transmissive liquid crystal device.
  • the orientation of the liquid crystal 262 can be controlled by the voltage applied between the conductive layer 112b and the conductive layer 263, and the optical modulation of the light can be controlled.
  • the intensity of the light emitted through the polarizing plate 260b can be controlled.
  • the colored layer absorbs light other than a specific wavelength range of the incident light, so that the extracted light is, for example, red light.
  • a linear polarizing plate may be used as polarizing plate 260b, but a circular polarizing plate may also be used.
  • a linear polarizing plate and a quarter-wave retardation plate stacked together may be used as the circular polarizing plate.
  • polarizer 260b When a circular polarizer is used as polarizer 260b, a circular polarizer may also be used for polarizer 260a, or a normal linear polarizer may be used.
  • the desired contrast can be achieved by adjusting the cell gap, orientation, drive voltage, etc. of the liquid crystal element used in liquid crystal element 60 according to the type of polarizer used for polarizers 260a and 260b.
  • the conductive layer 263 is electrically connected to the conductive layer 166b provided on the substrate 151 side by the connector 223 at the connection portion 140.
  • the conductive layer 166b is connected to the conductive layer 165b through an opening provided in the insulating layer 110. This allows a potential or signal to be supplied to the conductive layer 263 from an FPC or IC arranged on the substrate 151 side.
  • the configuration shown in FIG. 48 shows an example in which the conductive layer 165b is formed in the same process using the same material as the conductive layer 112a, and an example in which the conductive layer 166b is formed in the same process using the same material as the conductive layer 112b.
  • conductive particles can be used.
  • the conductive particles particles of organic resin or silica, etc., whose surfaces are coated with a metal material can be used.
  • Nickel or gold is preferably used as the metal material because it can reduce the contact resistance. It is also preferable to use particles coated with two or more metal materials in layers, such as nickel further coated with gold. It is also preferable to use a material that undergoes elastic or plastic deformation as the connector 223. In this case, the conductive particles may be crushed in the vertical direction as shown in FIG. 48. This increases the contact area between the connector 223 and the conductive layer electrically connected thereto, thereby reducing the contact resistance and suppressing the occurrence of problems such as poor connection. It is preferable to arrange the connector 223 so that it is covered by the adhesive layer 144. For example, it is preferable to disperse the connector 223 in the adhesive layer 144 before hardening.
  • connection portion 197 is provided in a region near the end of the substrate 151.
  • the conductive layer 166a is electrically connected to the FPC 172 via the connection layer 242.
  • the conductive layer 166a is connected to the conductive layer 165a via an opening provided in the insulating layer 110.
  • the configuration shown in FIG. 48 shows an example in which the conductive layer 165a is formed in the same process using the same material as the conductive layer 112a, and the conductive layer 166a is formed in the same process using the same material as the conductive layer 112b.
  • ⁇ Configuration Example 9 of Display Device> 49 is a liquid crystal display device in the FFS mode.
  • the display device 50I differs from the display device 50H mainly in the configuration of the liquid crystal element 60.
  • a conductive layer 263 that functions as a common electrode of the liquid crystal element 60 is provided on the insulating layer 110, and an insulating layer 261 is provided on the conductive layer 263.
  • a conductive layer 112b that functions as the other of the source and drain electrodes of the transistor and as a pixel electrode of the liquid crystal element 60 is provided on the insulating layer 261.
  • An insulating layer 195 is provided on the conductive layer 112b.
  • the conductive layer 112b has a comb-like shape or a shape with slits in a plan view.
  • the conductive layer 263 is disposed so as to overlap the conductive layer 112b. In the area overlapping the colored layer, there is a portion on the conductive layer 263 where the conductive layer 112b is not disposed.
  • a capacitance is formed by stacking conductive layer 112b and conductive layer 263 with insulating layer 261 in between. This eliminates the need to form a separate capacitive element, and increases the aperture ratio of the pixel.
  • both the conductive layer 112b and the conductive layer 263 may have a comb-like top surface shape.
  • the display device 50I in the liquid crystal element 60, only one of the conductive layer 112b and the conductive layer 263 has a comb-like top surface shape, so that the conductive layer 112b and the conductive layer 263 partially overlap. This allows the capacitance between the conductive layer 112b and the conductive layer 263 to be used as a storage capacitance, eliminating the need to provide a separate capacitance element and increasing the aperture ratio of the display device.
  • ⁇ Configuration Example 10 of Display Device> In the display device 50J shown in Fig. 50A, the portion of the insulating layer 110b that overlaps with the liquid crystal element 60 is removed by etching.
  • the liquid crystal element 60 of the display device 50J has a portion in which the insulating layer 110a, the insulating layer 110c, and the conductive layer 112b are laminated in this order.
  • the conductive layer 112b functions as a pixel electrode of the liquid crystal element 60.
  • the conductive layer 112m functions as a common electrode of the liquid crystal element 60.
  • the conductive layer 112m is formed from the same conductive film as the conductive layer 112a.
  • either one or both of the insulating layers 106 and 195 may have a portion that overlaps with the liquid crystal element 60 removed by etching.
  • the insulating layer 195 may not be provided. This allows the electric field of the conductive layer 112b and the conductive layer 112m to be easily transmitted to the liquid crystal 262, enabling high-speed operation of the liquid crystal element 60. Furthermore, not only is the light transmittance in the portion that overlaps with the liquid crystal element 60 increased, but the effects of interface reflection and interface scattering can be suppressed.
  • either one of the insulating layers 110a and 110c may have a portion that overlaps with the liquid crystal element 60 removed by etching. This also allows the electric field of the conductive layer 112b and the conductive layer 112m to be easily transmitted to the liquid crystal 262. Furthermore, the capacitance between the conductive layer 112b and the conductive layer 112m may be increased in some cases.
  • both the conductive layer 112b and the conductive layer 112m may have a comb-like upper surface shape.
  • the conductive layer 112b and the conductive layer 112m are configured to partially overlap. This allows the capacitance between the conductive layer 112b and the conductive layer 112m to be used as a storage capacitance, eliminating the need to provide a separate capacitive element and increasing the aperture ratio of the display device.
  • a display device 50K shown in Fig. 50B differs from the display device 50I mainly in that a common electrode is provided over a pixel electrode.
  • a conductive layer 112b included in the transistor 100 functions as a pixel electrode in the liquid crystal element 60.
  • An insulating layer 106 and an insulating layer 195 are provided over the conductive layer 112b, and a conductive layer 263 is provided over the insulating layer 195.
  • the conductive layer 263 functions as a common electrode in the liquid crystal element 60.
  • the conductive layer 263 has a comb-like shape or a shape provided with slits in a plan view.
  • Fig. 51 shows cross-sectional views of three light-emitting elements and a connection part 140 of a display part 162 in each process.
  • Light-emitting elements can be fabricated using vacuum processes such as deposition, and solution processes such as spin coating and inkjet.
  • deposition methods include physical deposition (PVD) methods such as sputtering, ion plating, ion beam deposition, molecular beam deposition, and vacuum deposition, and chemical deposition (CVD).
  • PVD physical deposition
  • CVD chemical deposition
  • the functional layers (hole injection layer, hole transport layer, hole blocking layer, light-emitting layer, electron blocking layer, electron transport layer, electron injection layer, charge generation layer, etc.) contained in the EL layer can be formed by deposition (vacuum deposition, etc.), coating methods (dip coating, die coating, bar coating, spin coating, spray coating, etc.), printing methods (inkjet, screen (screen printing), offset (lithographic printing), flexo (letterpress), gravure, microcontact, etc.), etc.
  • the island-like layer (layer including the light-emitting layer) produced by the method for producing a display device described below is not formed using a fine metal mask, but is formed by depositing the light-emitting layer over one surface and then processing it using photolithography. This makes it possible to realize a high-definition display device or a display device with a high aperture ratio, which has been difficult to achieve until now. Furthermore, since the light-emitting layers can be produced separately for each color, it is possible to realize a display device that is extremely vivid, has high contrast, and has high display quality. Furthermore, by providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the production process of the display device can be reduced, and the reliability of the light-emitting element can be increased.
  • a display device is composed of three types of light-emitting elements, one that emits blue light, one that emits green light, and one that emits red light
  • three types of island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and processing by photolithography three times.
  • pixel electrodes 111R, 111G, and 111B and a conductive layer 123 are formed on a substrate 151 on which transistors 205R, 205G, and 205B (not shown) are provided ( Figure 51A).
  • the conductive film that becomes the pixel electrodes can be formed by, for example, sputtering or vacuum deposition. After forming a resist mask on the conductive film by a photolithography process, the conductive film can be processed to form pixel electrodes 111R, 111G, and 111B and conductive layer 123. The conductive film can be processed by one or both of wet etching and dry etching.
  • Film 133Bf (later layer 133B) includes a light-emitting layer that emits blue light.
  • an example is shown in which an island-shaped EL layer for a light-emitting element that emits blue light is first formed, and then an island-shaped EL layer for a light-emitting element that emits light of another color is formed.
  • the pixel electrodes of the light-emitting elements of the colors formed second or later may be damaged by the previous process. This may result in the driving voltage of the light-emitting elements of the colors formed second or later being higher.
  • an island-shaped EL layer of a light-emitting element that emits light with the shortest wavelength e.g., a blue light-emitting element.
  • the island-shaped EL layers in the order of blue, green, and red, or blue, red, and green.
  • the state of the interface between the pixel electrode and the EL layer in the blue light-emitting element can be kept good, and the drive voltage of the blue light-emitting element can be prevented from increasing. It also extends the life of the blue light-emitting element and improves its reliability. Furthermore, since the red and green light-emitting elements are less affected by increases in drive voltage compared to the blue light-emitting element, the drive voltage can be reduced and reliability can be improved for the entire display device.
  • the order in which the island-shaped EL layers are fabricated is not limited to the above, and may be, for example, red, green, and blue.
  • film 133Bf is not formed on conductive layer 123.
  • film 133Bf can be formed only in desired areas.
  • a light-emitting element can be manufactured through a relatively simple process.
  • the heat resistance temperature of the compounds contained in film 133Bf is preferably 100°C or higher and 180°C or lower, more preferably 120°C or higher and 180°C or lower, and more preferably 140°C or higher and 180°C or lower. This can improve the reliability of the light-emitting element.
  • the upper limit of the temperature that can be applied in the manufacturing process of the display device can be increased. This can therefore broaden the range of choices for materials and formation methods used in the display device, making it possible to improve yield and reliability.
  • the heat resistance temperature can be, for example, any one of the glass transition point, softening point, melting point, thermal decomposition temperature, and 5% weight loss temperature, preferably the lowest temperature among these.
  • the film 133Bf can be formed, for example, by a deposition method, specifically a vacuum deposition method.
  • the film 133Bf may also be formed by a transfer method, a printing method, an inkjet method, a coating method, or other methods.
  • a sacrificial layer 118B is formed on the film 133Bf and on the conductive layer 123 (FIG. 51A).
  • a resist mask is formed by a photolithography process on the film that will become the sacrificial layer 118B, the film can be processed to form the sacrificial layer 118B.
  • the sacrificial layer 118B is preferably provided so as to cover the ends of each of the pixel electrodes 111R, 111G, and 111B. This means that the ends of the layer 133B formed in a later process will be located outside the ends of the pixel electrode 111B. This makes it possible to use the entire upper surface of the pixel electrode 111B as a light-emitting region, thereby increasing the aperture ratio of the pixel. In addition, since the ends of the layer 133B may be damaged in a process after the formation of the layer 133B, it is preferable that they are located outside the ends of the pixel electrode 111B, that is, are not used as a light-emitting region. This makes it possible to suppress variation in the characteristics of the light-emitting element and increase reliability.
  • each process after the formation of layer 133B can be performed without pixel electrode 111B being exposed. If the edge of pixel electrode 111B is exposed, corrosion may occur during an etching process or the like. By suppressing corrosion of pixel electrode 111B, the yield and characteristics of the light-emitting element can be improved.
  • the sacrificial layer 118B in a position that overlaps the conductive layer 123. This makes it possible to prevent the conductive layer 123 from being damaged during the manufacturing process of the display device.
  • a film that is highly resistant to the processing conditions of the film 133Bf specifically, a film that has a large etching selectivity with respect to the film 133Bf, is used.
  • the sacrificial layer 118B is formed at a temperature lower than the heat resistance temperature of each compound contained in the film 133Bf.
  • the substrate temperature when forming the sacrificial layer 118B is typically 200°C or less, preferably 150°C or less, more preferably 120°C or less, more preferably 100°C or less, and even more preferably 80°C or less.
  • the deposition temperature of sacrificial layer 118B can be made high, which is preferable.
  • the substrate temperature when forming sacrificial layer 118B can be set to 100°C or higher, 120°C or higher, or 140°C or higher.
  • the higher the deposition temperature the denser the inorganic insulating film can be and the higher the barrier properties can be. Therefore, by depositing the sacrificial layer at such a temperature, damage to film 133Bf can be further reduced, and the reliability of the light-emitting element can be improved.
  • each of the other layers e.g., insulating film 125f
  • film 133Bf the deposition temperature of each of the other layers (e.g., insulating film 125f) formed on film 133Bf.
  • the sacrificial layer 118B can be formed by, for example, sputtering, ALD (including thermal ALD and PEALD), CVD, or vacuum deposition. It may also be formed by using the wet film formation method described above.
  • the sacrificial layer 118B (if the sacrificial layer 118B has a laminated structure, the layer provided in contact with the film 133Bf) is preferably formed using a formation method that causes less damage to the film 133Bf. For example, it is preferable to use the ALD method or the vacuum deposition method rather than the sputtering method.
  • the sacrificial layer 118B can be processed by wet etching or dry etching. It is preferable to process the sacrificial layer 118B by anisotropic etching.
  • the wet etching method By using the wet etching method, damage to the film 133Bf during processing of the sacrificial layer 118B can be reduced compared to when using the dry etching method.
  • a developer When using the wet etching method, it is preferable to use, for example, a developer, a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixed solution containing two or more of these.
  • TMAH tetramethylammonium hydroxide
  • a mixed acid-based chemical solution containing water, phosphoric acid, dilute hydrofluoric acid, and nitric acid may be used.
  • the chemical solution used in the wet etching process may be alkaline or acidic.
  • the sacrificial layer 118B may be, for example, one or more of a metal film, an alloy film, a metal oxide film, a semiconductor film, an inorganic insulating film, and an organic insulating film.
  • the sacrificial layer 118B can be made of metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, titanium, aluminum, yttrium, zirconium, and tantalum, or alloy materials containing such metal materials.
  • the sacrificial layer 118B can be made of metal oxides such as In-Ga-Zn oxide, indium oxide, In-Zn oxide, In-Sn oxide, indium titanium oxide (In-Ti oxide), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide), and indium tin oxide containing silicon.
  • metal oxides such as In-Ga-Zn oxide, indium oxide, In-Zn oxide, In-Sn oxide, indium titanium oxide (In-Ti oxide), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide), and indium tin oxide containing silicon.
  • element M (wherein M is one or more elements selected from aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) may be used in place of the above gallium.
  • semiconductor materials such as silicon or germanium can be used as materials that have high compatibility with semiconductor manufacturing processes.
  • oxides or nitrides of the above semiconductor materials can be used.
  • non-metallic materials such as carbon, or compounds thereof can be used.
  • metals such as titanium, tantalum, tungsten, chromium, and aluminum, or alloys containing one or more of these, can be used.
  • oxides containing the above metals, such as titanium oxide or chromium oxide, or nitrides such as titanium nitride, chromium nitride, or tantalum nitride can be used.
  • an inorganic insulating film that can be used for the protective layer 131 can be used.
  • oxides are preferable because they have higher adhesion to the film 133Bf than nitrides.
  • one or more of aluminum oxide, hafnium oxide, and silicon oxide can be suitably used for the sacrificial layer 118B.
  • an aluminum oxide film can be formed, for example, using the ALD method. Using the ALD method is preferable because it can reduce damage to the base (particularly the film 133Bf).
  • the sacrificial layer 118B can be a laminated structure of an inorganic insulating film (e.g., an aluminum oxide film) formed using the ALD method and an inorganic film (e.g., an In-Ga-Zn oxide film, a silicon film, or a tungsten film) formed using the sputtering method.
  • an inorganic insulating film e.g., an aluminum oxide film
  • an inorganic film e.g., an In-Ga-Zn oxide film, a silicon film, or a tungsten film
  • the same inorganic insulating film can be used for both the sacrificial layer 118B and the insulating layer 125 to be formed later.
  • an aluminum oxide film formed by ALD can be used for both the sacrificial layer 118B and the insulating layer 125.
  • the same film-forming conditions can be applied to the sacrificial layer 118B and the insulating layer 125, or different film-forming conditions can be applied to each of them.
  • the sacrificial layer 118B can be an insulating layer with high barrier properties against at least one of water and oxygen.
  • the sacrificial layer 118B is a layer that is removed in most or all in a later process, it is preferable that it is easy to process. Therefore, it is preferable to form the sacrificial layer 118B under conditions where the substrate temperature during film formation is lower than that of the insulating layer 125.
  • an organic material may be used for the sacrificial layer 118B.
  • the organic material may be a material that is soluble in a solvent that is chemically stable with respect to at least the film located at the top of the film 133Bf.
  • a material that dissolves in water or alcohol is preferably used.
  • the sacrificial layer 118B may be made of an organic resin such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, alcohol-soluble polyamide resin, or a fluororesin such as a perfluoropolymer.
  • PVA polyvinyl alcohol
  • polyvinyl butyral polyvinylpyrrolidone
  • polyethylene glycol polyglycerin
  • pullulan polyethylene glycol
  • polyglycerin polyglycerin
  • pullulan polyethylene glycol
  • pullulan polyglycerin
  • water-soluble cellulose water-soluble cellulose
  • alcohol-soluble polyamide resin or a fluororesin such as a perfluoropolymer.
  • the sacrificial layer 118B can be a laminated structure of an organic film (e.g., a PVA film) formed using either a vapor deposition method or the above-mentioned wet film formation method, and an inorganic film (e.g., a silicon nitride film) formed using a sputtering method.
  • an organic film e.g., a PVA film
  • an inorganic film e.g., a silicon nitride film
  • a portion of the sacrificial film may remain as a sacrificial layer.
  • the film 133Bf is processed using the sacrificial layer 118B as a hard mask to form layer 133B ( Figure 51B).
  • a laminated structure of layer 133B and sacrificial layer 118B remains on pixel electrode 111B.
  • Pixel electrodes 111R and 111G are exposed.
  • sacrificial layer 118B remains on conductive layer 123.
  • the film 133Bf is preferably processed by anisotropic etching.
  • anisotropic dry etching is preferable.
  • wet etching may be used.
  • the process of forming film 133Bf, the process of forming sacrificial layer 118B, and the process of forming layer 133B are repeated at least twice, changing the light-emitting material, to form a layered structure of layer 133R and sacrificial layer 118R on pixel electrode 111R, and a layered structure of layer 133G and sacrificial layer 118G on pixel electrode 111G (FIG. 51C).
  • layer 133R is formed to include a light-emitting layer that emits red light
  • layer 133G is formed to include a light-emitting layer that emits green light.
  • the materials that can be used for sacrificial layer 118B can be applied to sacrificial layers 118R and 118G, and both may be the same material or different materials may be used.
  • the side surfaces of layers 133B, 133G, and 133R are perpendicular or approximately perpendicular to the surface on which they are formed.
  • the angle between the surface on which they are formed and these side surfaces is 60 degrees or more and 90 degrees or less.
  • the distance between two adjacent layers of layers 133B, 133G, and 133R formed using photolithography can be narrowed to 8 ⁇ m or less, 5 ⁇ m or less, 3 ⁇ m or less, 2 ⁇ m or less, or 1 ⁇ m or less.
  • the distance can be defined as, for example, the distance between two adjacent opposing ends of layers 133B, 133G, and 133R. In this way, by narrowing the distance between the island-shaped EL layers, a display device with high definition and a large aperture ratio can be provided.
  • insulating film 125f which will later become insulating layer 125, is formed to cover the pixel electrode, layer 133B, layer 133G, layer 133R, sacrificial layer 118B, sacrificial layer 118G, and sacrificial layer 118R, and insulating layer 127 is formed on insulating film 125f ( Figure 51D).
  • the insulating film 125f prefferably with a thickness of 3 nm or more, 5 nm or more, or 10 nm or more, and 200 nm or less, 150 nm or less, 100 nm or less, or 50 nm or less.
  • the insulating film 125f is preferably formed by, for example, the ALD method.
  • the ALD method is preferable because it can reduce film formation damage and can form a film with high coating properties. It is preferable to form an aluminum oxide film as the insulating film 125f by, for example, the ALD method.
  • the insulating film 125f may be formed using a sputtering method, a CVD method, or a PECVD method, which have a faster film formation speed than the ALD method. This allows a highly reliable display device to be manufactured with high productivity.
  • the insulating film that becomes the insulating layer 127 is preferably formed by the above-mentioned wet film formation method (e.g., spin coating) using, for example, a photosensitive resin composition containing an acrylic resin.
  • a heat treatment also called pre-baking
  • visible light or ultraviolet light is irradiated to a part of the insulating film to expose the part.
  • development is performed to remove the exposed area of the insulating film.
  • a heat treatment also called post-baking
  • the shape of the insulating layer 127 is not limited to the shape shown in FIG. 51D.
  • the upper surface of the insulating layer 127 can have one or more of a convex curved surface, a concave curved surface, and a flat surface.
  • the insulating layer 127 may cover the side surface of at least one end of the insulating layer 125, the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R.
  • an etching process is performed using the insulating layer 127 as a mask to remove the insulating film 125f and parts of the sacrificial layers 118B, 118G, and 118R.
  • openings are formed in the sacrificial layers 118B, 118G, and 118R, respectively, and the top surfaces of the layers 133B, 133G, and 133R, and the conductive layer 123 are exposed.
  • parts of the sacrificial layers 118B, 118G, and 118R may remain at positions overlapping the insulating layer 127 and the insulating layer 125 (see sacrificial layers 119B, 119G, and 119R).
  • the etching process can be performed by dry etching or wet etching. If the insulating film 125f is formed using the same material as the sacrificial layers 118B, 118G, and 118R, this is preferable because the etching process can be performed in one go.
  • insulating layer 127 As described above, by providing insulating layer 127, insulating layer 125, sacrificial layer 118B, sacrificial layer 118G, and sacrificial layer 118R, it is possible to prevent connection failures caused by disconnected portions of common layer 114 and common electrode 115 between each light-emitting element, and increases in electrical resistance caused by locally thin portions. This allows the display device of one embodiment of the present invention to have improved display quality.
  • the common layer 114 and the common electrode 115 are formed in this order on the insulating layer 127, the layer 133B, the layer 133G, and the layer 133R ( Figure 51F).
  • the common layer 114 can be formed by a method such as a deposition method (including a vacuum deposition method), a transfer method, a printing method, an inkjet method, or a coating method.
  • the common electrode 115 can be formed by, for example, sputtering or vacuum deposition. Alternatively, a film formed by deposition and a film formed by sputtering can be laminated together.
  • the island-shaped layers 133B, 133G, and 133R are not formed using a fine metal mask, but are formed by forming a film over the entire surface and processing the film, so that the island-shaped layers can be formed with a uniform thickness.
  • This makes it possible to realize a high-definition display device or a display device with a high aperture ratio.
  • the layers 133B, 133G, and 133R can be prevented from contacting each other in adjacent subpixels. Therefore, it is possible to prevent leakage current from occurring between the subpixels. This makes it possible to prevent unintended light emission due to crosstalk, and to realize a display device with extremely high contrast.
  • the display device of one embodiment of the present invention can achieve both high definition and high display quality.
  • the electronic device of this embodiment has a display device of one embodiment of the present invention in a display portion.
  • the display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, it can be used in the display portion of various electronic devices.
  • the semiconductor device of one embodiment of the present invention can be applied to parts other than the display part of an electronic device.
  • the semiconductor device of one embodiment of the present invention in a control part of an electronic device, it is possible to reduce power consumption, which is preferable.
  • Electronic devices include, for example, electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of one embodiment of the present invention can be used favorably in electronic devices having a relatively small display area because it is possible to increase the resolution.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.
  • the display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • HD 1280 x 720 pixels
  • FHD (1920 x 1080 pixels
  • WQHD 2560 x 1440 pixels
  • WQXGA 2560 x 1600 pixels
  • 4K 3840 x 2160 pixels
  • 8K 8K
  • the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more.
  • the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.
  • the electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • wearable devices that can be worn on the head are described below using Figures 52A to 52D.
  • These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content.
  • a function to display AR content a function to display AR content
  • VR content a function to display VR content
  • SR content a function to display SR content
  • MR content a function to display MR content.
  • Electronic device 700A shown in FIG. 52A and electronic device 700B shown in FIG. 52B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.
  • a display device can be applied to the display panel 751. Therefore, the electronic device can display images with extremely high resolution.
  • Electronic device 700A and electronic device 700B can each project an image displayed on display panel 751 onto display area 756 of optical member 753. Because optical member 753 is translucent, the user can see the image displayed in the display area superimposed on the transmitted image visible through optical member 753. Therefore, electronic device 700A and electronic device 700B are each electronic devices capable of AR display.
  • Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image of the front as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.
  • an acceleration sensor such as a gyro sensor
  • the communication unit has a wireless communication device, and can supply video signals and the like via the wireless communication device.
  • a connector can be provided to which a cable through which a video signal and power supply potential can be connected.
  • Electronic device 700A and electronic device 700B are provided with a battery (not shown) and can be charged wirelessly, wired, or both.
  • the housing 721 may be provided with a touch sensor module.
  • the touch sensor module has a function of detecting that the outer surface of the housing 721 is touched.
  • the touch sensor module can detect a tap operation or a slide operation by the user and execute various processes. For example, a tap operation can execute processes such as pausing or resuming a video, and a slide operation can execute processes such as fast-forwarding or rewinding. Furthermore, by providing a touch sensor module on each of the two housings 721, the range of operations can be expanded.
  • touch sensors can be used as the touch sensor module.
  • various types can be adopted, such as the capacitance type, resistive film type, infrared type, electromagnetic induction type, surface acoustic wave type, and optical type.
  • a photoelectric conversion element When using an optical touch sensor, a photoelectric conversion element can be used as the light receiving element.
  • the active layer of the photoelectric conversion element can be made of either or both of an inorganic semiconductor and an organic semiconductor.
  • Electronic device 800A shown in Fig. 52C and electronic device 800B shown in Fig. 52D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832. Note that display unit 820, communication unit 822, and imaging unit 825 are omitted in Fig. 52D.
  • a display device can be applied to the display portion 820. Therefore, the electronic device can display images with extremely high resolution. This allows the user to feel a high sense of immersion.
  • the display unit 820 is provided inside the housing 821 at a position that can be seen through the lens 832. In addition, by displaying different images on the pair of display units 820, it is also possible to perform a three-dimensional display using parallax.
  • the electronic device 800A and the electronic device 800B can each be considered electronic devices for VR.
  • a user wearing the electronic device 800A or the electronic device 800B can view the image displayed on the display unit 820 through the lens 832.
  • Electric device 800A and electronic device 800B each preferably have a mechanism that can adjust the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that they have a mechanism that can adjust the focus by changing the distance between lens 832 and display unit 820.
  • the attachment unit 823 allows the user to attach the electronic device 800A or electronic device 800B to the head. Note that in FIG. 52C and other figures, the attachment unit 823 is shaped like the temples of glasses, but is not limited to this. The attachment unit 823 may be shaped like a helmet or band, for example, as long as it can be worn by the user.
  • the imaging unit 825 has a function of acquiring external information.
  • the data acquired by the imaging unit 825 can be output to the display unit 820.
  • An image sensor can be used for the imaging unit 825.
  • multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.
  • a distance measuring sensor capable of measuring the distance to an object
  • the imaging unit 825 is one aspect of the detection unit.
  • the detection unit for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection and Ranging) can be used.
  • LIDAR Light Detection and Ranging
  • the electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone.
  • a configuration having the vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This makes it possible to enjoy video and audio simply by wearing the electronic device 800A without the need for separate audio equipment such as headphones, earphones, or speakers.
  • Each of electronic devices 800A and 800B may have an input terminal.
  • the input terminal can be connected to a cable that supplies a video signal from a video output device or the like, and power for charging a battery provided within the electronic device.
  • the electronic device of one embodiment of the present invention may have a function of wireless communication with the earphone 750.
  • the earphone 750 has a communication unit (not shown) and has a wireless communication function.
  • the earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function.
  • the electronic device 700A shown in FIG. 52A has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device 800A shown in FIG. 52C has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device may have an earphone unit.
  • the electronic device 700B shown in FIG. 52B has an earphone unit 727.
  • the earphone unit 727 and the control unit may be configured to be connected to each other by wire.
  • a portion of the wiring connecting the earphone unit 727 and the control unit may be disposed inside the housing 721 or the attachment unit 723.
  • electronic device 800B shown in FIG. 52D has earphone unit 827.
  • earphone unit 827 and control unit 824 can be configured to be connected to each other by wire.
  • Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or mounting unit 823.
  • earphone unit 827 and mounting unit 823 may have magnets. This allows earphone unit 827 to be fixed to mounting unit 823 by magnetic force, which is preferable as it makes storage easier.
  • the electronic device may have an audio output terminal to which earphones or headphones can be connected.
  • the electronic device may also have one or both of an audio input terminal and an audio input mechanism.
  • a sound collection device such as a microphone can be used as the audio input mechanism.
  • the electronic device may be endowed with the functionality of a so-called headset.
  • electronic devices according to one embodiment of the present invention are suitable for both glasses-type devices (such as electronic device 700A and electronic device 700B) and goggle-type devices (such as electronic device 800A and electronic device 800B).
  • the electronic device of one embodiment of the present invention can transmit information to the earphones via wire or wirelessly.
  • the electronic device 6500 shown in FIG. 53A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 has a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508.
  • the display portion 6502 has a touch panel function.
  • the display device of one embodiment of the present invention can be applied to the display portion 6502.
  • FIG. 53B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.
  • a translucent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.
  • the display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).
  • a part of the display panel 6511 is folded back in the area outside the display unit 6502, and the FPC 6515 is connected to the folded back part.
  • An IC 6516 is mounted on the FPC 6515.
  • the FPC 6515 is connected to a terminal provided on a printed circuit board 6517.
  • the flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized.
  • the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small.
  • a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.
  • FIG 53C shows an example of a television device.
  • a television device 7100 has a display unit 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.
  • a display device can be applied to the display portion 7000.
  • the television set 7100 shown in FIG. 53C can be operated using an operation switch provided on the housing 7101 and a separate remote control 7111.
  • the display unit 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display unit 7000 with a finger or the like.
  • the remote control 7111 may have a display unit that displays information output from the remote control 7111.
  • the channel and volume can be operated using the operation keys or touch panel provided on the remote control 7111, and the image displayed on the display unit 7000 can be operated.
  • the television device 7100 is configured to include a receiver and a modem.
  • the receiver can receive general television broadcasts.
  • by connecting to a wired or wireless communication network via the modem it is also possible to carry out one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.
  • FIG. 53D shows an example of a notebook computer.
  • the notebook computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc.
  • the display unit 7000 is built into the housing 7211.
  • a display device can be applied to the display portion 7000.
  • Figures 53E and 53F show an example of digital signage.
  • the digital signage 7300 shown in FIG. 53E has a housing 7301, a display unit 7000, and a speaker 7303. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.
  • FIG. 53F shows digital signage 7400 attached to a cylindrical pole 7401.
  • Digital signage 7400 has a display unit 7000 that is provided along the curved surface of pole 7401.
  • a display device of one embodiment of the present invention can be applied to the display portion 7000.
  • the larger the display unit 7000 the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of an advertisement, for example.
  • a touch panel By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • the electronic device shown in Figures 54A to 54G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared), a microphone 9008, etc.
  • a display device of one embodiment of the present invention can be applied to the display portion 9001.
  • the electronic devices shown in Figures 54A to 54G have various functions. For example, they can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to control processing by various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc.
  • the functions of the electronic devices are not limited to these, and they can have various functions.
  • the electronic devices may have multiple display units.
  • the electronic devices may have a function to provide a camera or the like, capture still images or videos, and store them on a recording medium (external or built into the camera), display the captured images on the display unit, etc.
  • FIG. 54A is a perspective view showing a mobile information terminal 9101.
  • the mobile information terminal 9101 can be used as a smartphone, for example.
  • the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like.
  • the mobile information terminal 9101 can display text and image information on multiple surfaces.
  • FIG. 54A shows an example in which three icons 9050 are displayed.
  • Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mail, SNS, telephone calls, etc., the title of e-mail or SNS, the sender's name, the date and time, the remaining battery level, and radio wave strength.
  • an icon 9050 or the like may be displayed at the position where the information 9051 is displayed.
  • Figure 54B is a perspective view showing a mobile information terminal 9102.
  • the mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001.
  • information 9052, information 9053, and information 9054 are each displayed on different sides.
  • a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of a garment. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether or not to answer a call.
  • FIG. 54C is a perspective view showing a tablet terminal 9103.
  • the tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, internet communication, and computer games, for example.
  • the tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of the housing 9000, operation keys 9005 as operation buttons on the side of the housing 9000, and a connection terminal 9006 on the bottom.
  • FIG. 54D is a perspective view showing a wristwatch-type mobile information terminal 9200.
  • the mobile information terminal 9200 can be used, for example, as a smart watch (registered trademark).
  • the display surface of the display unit 9001 is curved, and display can be performed along the curved display surface.
  • the mobile information terminal 9200 can also make hands-free calls by communicating with, for example, a headset capable of wireless communication.
  • the mobile information terminal 9200 can also transmit data to and from other information terminals and charge itself via a connection terminal 9006. Charging may be performed by wireless power supply.
  • FIG. 54E to 54G are perspective views showing a foldable mobile information terminal 9201.
  • FIG. 54E is a perspective view of the mobile information terminal 9201 in an unfolded state
  • FIG. 54G is a perspective view of the mobile information terminal 9201 in a folded state
  • FIG. 54F is a perspective view of a state in the process of changing from one of FIG. 54E and FIG. 54G to the other.
  • the mobile information terminal 9201 has excellent portability when folded, and excellent display visibility due to a seamless wide display area when unfolded.
  • the display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055.
  • the display unit 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.
  • sample A having a transistor according to one embodiment of the present invention was fabricated.
  • the structure of the transistor in sample A can be referred to in the description of transistor 100 shown in FIG. 1B.
  • the fabrication method of sample A can be referred to in the description of embodiment 2.
  • an In-Sn-Si oxide (ITSO) film having a thickness of about 100 nm was formed by sputtering on the substrate 102, and then processed to obtain the conductive layer 112a.
  • the substrate 102 was a glass substrate.
  • a silicon nitride film with a thickness of about 30 nm was formed as the insulating film 110af, and a silicon oxynitride film with a thickness of about 500 nm was formed as the insulating film 110bf.
  • the insulating film 110af and the insulating film 110bf were formed by the PECVD method.
  • metal oxide layer 137 a metal oxide layer having a thickness of about 20 nm was formed as metal oxide layer 137 on insulating film 110bf.
  • the metal oxide layer 137 was removed.
  • a wet etching method was used to remove the metal oxide layer 137.
  • insulating film 110cf a silicon nitride film with a thickness of approximately 30 nm was formed as insulating film 110cf on insulating film 110bf by the PECVD method.
  • an In-Sn-Si oxide (ITSO) film with a thickness of approximately 100 nm was formed as conductive film 112bf on insulating film 110cf by sputtering.
  • the conductive film 112bf was then processed to obtain the conductive layer 112B.
  • the conductive layer 112B in the area overlapping the conductive layer 112a was removed to form the conductive layer 112b having the opening 143, and the insulating films 110af, 110bf, and 110cf in the area overlapping the conductive layer 112a were removed to form the insulating layer 110 having the opening 141.
  • the conductive layer 112B was removed using a wet etching method.
  • the insulating films 110af, 110bf, and 110cf were removed using a dry etching method.
  • metal oxide film 108f a metal oxide film with a thickness of about 20 nm was formed as metal oxide film 108f so as to cover openings 141 and 143.
  • the metal oxide film 108f was processed to obtain the semiconductor layer 108.
  • a silicon oxynitride film with a thickness of approximately 50 nm was deposited as the insulating layer 106 by the PECVD method.
  • a titanium film having a thickness of about 50 nm, an aluminum film having a thickness of about 200 nm, and a titanium film having a thickness of about 50 nm were each formed by sputtering. After that, each conductive film was processed to obtain the conductive layer 104.
  • a silicon oxynitride film with a thickness of approximately 300 nm was formed as the insulating layer 195 by the PECVD method.
  • the sample A was observed by a scanning electron microscope (SEM).
  • SEM scanning electron microscope
  • a transistor was observed in which the top shapes of the openings 141 and 143 were circular and the channel width W100 was about 6.3 ⁇ m (the width D141 of the opening 141 was 2.0 ⁇ m).
  • the channel length L100 was about 0.5 ⁇ m.
  • Figure 55 is an image (tilt view) taken at a magnification of 15,000 times with the stage tilted. As shown in Figure 55, it was confirmed that sample A had a good shape.
  • sample A was sliced using a focused ion beam (FIB), and the cross section was observed using a scanning transmission electron microscope (STEM).
  • FIB focused ion beam
  • STEM scanning transmission electron microscope
  • Figure 56A is a transmission electron (TE) image at a magnification of 20,000 times. As shown in Figure 56A, it was confirmed that sample A had a good cross-sectional shape.
  • TE transmission electron
  • FIG. 56B is a transmission electron (TE) image at a magnification of 3,000,000 times.
  • FIG. 56B also shows an enlarged STEM image of the semiconductor layer 108 and its vicinity.
  • a crystal lattice image was confirmed in the semiconductor layer 108.
  • nine solid lines are shown as auxiliary lines to make the layered crystals easier to understand. It was confirmed that the semiconductor layer 108 has a CAAC structure with the c-axis of the crystal oriented in the normal direction of the surface on which it is to be formed (see the arrow in FIG. 56B).
  • sample B was fabricated, which has a transistor according to one embodiment of the present invention.
  • the description of the transistor 100 shown in FIG. 11A can be referred to.
  • an In-Sn-Si oxide (ITSO) film having a thickness of about 100 nm was formed by sputtering on the substrate 102, and then processed to obtain the conductive layer 112a.
  • the substrate 102 a glass substrate having a size of 600 mm ⁇ 720 mm was used.
  • a silicon nitride film having a thickness of about 70 nm was formed as the first insulating film that becomes the insulating layer 110d
  • a silicon nitride film having a thickness of about 100 nm was formed as the second insulating film (insulating film 110af) that becomes the insulating layer 110a
  • a silicon oxynitride film having a thickness of about 500 nm was formed as the third insulating film (insulating film 110bf) that becomes the insulating layer 110b.
  • the first insulating film, the second insulating film, and the third insulating film were each formed successively in a vacuum using the PECVD method.
  • silane (SiH 4 ), nitrogen (N 2 ), and ammonia (NH 3 ) were used as the deposition gases used to form the first insulating film and the second insulating film (insulating film 110af), respectively.
  • the ammonia flow rate ratio during the formation of the first insulating film was set higher than the ammonia flow rate ratio during the formation of the second insulating film (insulating film 110af).
  • the metal oxide layer 137 was removed.
  • a wet etching method was used to remove the metal oxide layer 137.
  • a silicon nitride film having a thickness of about 50 nm was formed on the third insulating film (insulating film 110bf) as the fourth insulating film (insulating film 110cf) which becomes the insulating layer 110c, and a silicon nitride film having a thickness of about 100 nm was formed as the fifth insulating film which becomes the insulating layer 110e.
  • the fourth insulating film and the fifth insulating film were successively formed in a vacuum using the PECVD method. Note that silane (SiH 4 ), nitrogen (N 2 ) and ammonia (NH 3 ) were used as the deposition gases used to form the fourth insulating film (insulating film 110cf) and the fourth insulating film, respectively.
  • the ammonia flow rate ratio during the formation of the fifth insulating film was set higher than the ammonia flow rate ratio during the formation of the fourth insulating film (insulating film 110cf).
  • an In-Sn-Si oxide (ITSO) film with a thickness of approximately 100 nm was formed as conductive film 112bf on the fifth insulating film by sputtering.
  • the conductive film 112bf was then processed to obtain the conductive layer 112B.
  • the conductive layer 112B in the region overlapping with the conductive layer 112a was removed to form the conductive layer 112b having an opening 143
  • the first to fifth insulating films in the region overlapping with the conductive layer 112a were removed to form the insulating layer 110 having an opening 141.
  • the conductive layer 112B was removed by wet etching.
  • the first to fifth insulating films were removed by dry etching.
  • the top surface shapes of the openings 141 and 143 were circular.
  • metal oxide film 108f a metal oxide film with a thickness of about 20 nm was formed as metal oxide film 108f so as to cover openings 141 and 143.
  • the metal oxide film 108f was processed to obtain the semiconductor layer 108.
  • a silicon oxynitride film with a thickness of approximately 50 nm was deposited as the insulating layer 106 by the PECVD method.
  • a titanium film having a thickness of about 50 nm, an aluminum film having a thickness of about 200 nm, and a titanium film having a thickness of about 50 nm were each formed by sputtering. After that, each conductive film was processed to obtain the conductive layer 104.
  • a silicon oxynitride film with a thickness of approximately 300 nm was formed as the insulating layer 195 by the PECVD method.
  • the voltage applied to the gate electrode (hereinafter also referred to as the gate voltage (Vg or Vgs)) was set to -10 V to +10 V in 0.25 V increments.
  • the voltage applied to the source electrode (hereinafter also referred to as the source voltage (Vs)) was set to 0 V (comm), and the voltage applied to the drain electrode (hereinafter also referred to as the drain voltage (Vd or Vds)) was set to 0.1 V and 5.1 V.
  • a transistor with a channel width W100 of approximately 6.3 ⁇ m was measured.
  • the number of measurements was 120 within the surface of the 600 mm ⁇ 720 mm substrate.
  • the channel length L100 was approximately 0.5 ⁇ m.
  • the Id-Vg characteristics are shown in Figure 57.
  • the horizontal axis indicates the gate voltage (Vg) and the vertical axis indicates the drain current (Id).
  • the Id-Vg characteristics of 120 transistors are shown overlapping each other.
  • FIGS 58A, 58B, and 59 The probability distributions of threshold voltage (Vth), S value (also abbreviated as SS), and field effect mobility (also abbreviated as ⁇ FE) obtained from the above-mentioned Id-Vg characteristics are shown in Figures 58A, 58B, and 59.
  • Vth threshold voltage
  • S value also abbreviated as SS
  • ⁇ FE field effect mobility
  • sample B is normally off, has a large on-current, and has a small off-current. It was also confirmed that the in-plane variation of the electrical characteristics is small.
  • the average S value is 82.9 mV/dec, and it was confirmed that the interface between the semiconductor layer 108 and the gate insulating layer (insulating layer 106) is well formed.
  • the on-current per channel width is shown in Figure 60.
  • the horizontal axis shows the sample conditions, and the vertical axis shows the on-current divided by the channel width (Id/W).
  • the on-current used was the value when the drain voltage (Vd) was 5.1 V and the gate voltage (Vg) was 10 V.
  • TGSA TGSA type n-channel transistor using In-Ga-Zn oxide in the semiconductor layer
  • TGSA commercialized OS
  • P-type commercialized LTPS
  • the transistor of sample B has a channel length of submicron size, and thus can obtain an on-current approximately five times that of a p-channel LTPS transistor included in a commercially available display device.
  • GBT Gate Bias Temperature
  • PBTS Positive Bias Temperature Stress
  • NBTIS Negative Bias Temperature Illumination Stress
  • PBTS test a test in which a positive potential (positive bias) is applied to the gate relative to the source potential and drain potential and the device is held at high temperature
  • NBTS test a test in which a negative potential (negative bias) is applied to the gate and the device is held at high temperature
  • PBTIS Positive Bias Temperature Illumination Stress
  • NBTIS tests respectively.
  • the substrate on which the transistor is formed is kept at 60°C, and a voltage of 0.1 V is applied to the source and drain of the transistor, and 20 V is applied to the gate, and this state is maintained for one hour.
  • the test environment is dark.
  • the substrate on which the transistor is formed is kept at 60°C, and a voltage of 0 V is applied to the source and drain of the transistor, and -20 V is applied to the gate while irradiating with 5000 lx of white LED light, and this state is maintained for one hour.
  • the white LED light is irradiated from the glass substrate side.
  • a transistor with a channel width W100 of approximately 6.3 ⁇ m (width D141 of the opening 141 is 2.0 ⁇ m) was used.
  • the channel length L100 was approximately 0.5 ⁇ m.
  • the amount of change in threshold voltage before and after the PBTS test and before and after the NBTIS test is shown in Figure 61. As shown in Figure 61, the amount of change in threshold voltage was small in both the PBTS test and the NBTIS test, confirming good reliability.
  • an OLED panel (also called an OLED display, organic EL panel, or organic EL display) was manufactured as a display device that is one embodiment of the present invention.
  • a glass substrate measuring 600 mm x 720 mm was used to manufacture an OLED panel with a resolution of 513 ppi, an RGB stripe pixel arrangement, and an internal correction circuit.
  • the specifications of the manufactured OLED panel are shown in Table 1.
  • the structures of the transistors 100 and 200 shown in FIG. 11A can be referred to.
  • An oxide semiconductor (OS) was used for the semiconductor layers 108 and 208.
  • the channel length L100 of the transistor 100 which is a VFET, was set to about 0.5 ⁇ m, and the channel width W100 was set to about 6.3 ⁇ m (the width D141 of the opening 141 was 2.0 ⁇ m).
  • a VFET having an oxide semiconductor (OS) was used for the gate driver and the demultiplexer (DeMUX). By using a VFET, six transistors (6Tr) and two capacitance elements (2C) could be laid out in one subpixel (size 16.5 ⁇ m ⁇ 49.5 ⁇ m).
  • a tandem-structure OLED that emits white light is used as the light-emitting element, and a full-color display is achieved by using color filters.
  • Photographs of the display state of the OLED panel are shown in Figures 62A and 62B. It was confirmed that the pixel circuit, gate driver, and DeMUX all worked without any problems, and that a variety of images could be displayed.
  • sample C1 and C2 the contact resistance of materials that can be used for the conductive layers 112a and 112b and metal oxides that can be used for the semiconductor layer 108 was evaluated.
  • the transfer length method (TLM) was used for the evaluation.
  • two types of samples (samples C1 and C2) were prepared.
  • a conductive film was formed on a glass substrate by sputtering, and then processed to form a conductive layer.
  • a tungsten film with a thickness of about 100 nm was formed as the conductive film.
  • a copper film with a thickness of about 300 nm and an In-Sn-Si oxide (ITSO) film with a thickness of about 100 nm were formed on the copper film as the conductive film.
  • a metal oxide film with a thickness of approximately 100 nm was formed on the conductive layer, and then processed to form a semiconductor layer.
  • a silicon oxynitride film with a thickness of approximately 100 nm was formed using the PECVD method.
  • the I-V characteristics are shown in Figure 63.
  • the horizontal axis shows the source-drain voltage (Vd), and the vertical axis shows the drain current (Id).
  • sample C2 which uses In-Sn-Si oxide (ITSO) for the conductive film on the side in contact with the metal oxide film, has a linear I-V characteristic in which the drain current (Id) is proportional to the source-drain voltage. It was confirmed that the In-Sn-Si oxide (ITSO) film and the metal oxide film are in ohmic contact.
  • sample C1 which uses tungsten for the conductive film, has a non-linear I-V characteristic in which the drain current (Id) is not proportional to the source-drain voltage. It was confirmed that the tungsten film and the metal oxide film are in non-ohmic contact. Since tungsten has a high work function, it is possible that the interface between the tungsten film and the metal oxide film is in Schottky contact.
  • a conductive film was formed on the metal oxide film by sputtering.
  • an aluminum film with a thickness of about 100 nm was formed as the conductive film.
  • a molybdenum film with a thickness of about 100 nm was formed as the conductive film.
  • a tungsten film with a thickness of about 100 nm was formed as the conductive film.
  • a titanium film with a thickness of about 100 nm was formed as the conductive film.
  • an In-Sn-Si oxide (ITSO) film with a thickness of about 100 nm was formed as the conductive film.
  • ITSO In-Sn-Si oxide
  • the conductive film was removed to expose the metal oxide film.
  • a wet etching method was used to remove the conductive film.
  • the sheet resistance is shown in Figure 64.
  • the horizontal axis indicates the material of the conductive film, and the left vertical axis indicates the sheet resistance of the metal oxide (OS Sheet Resistance).
  • the right vertical axis indicates the carrier concentration of the metal oxide (OS Carrier Density) estimated from the sheet resistance.

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JP2016146422A (ja) * 2015-02-09 2016-08-12 株式会社ジャパンディスプレイ 表示装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2017167452A (ja) * 2016-03-18 2017-09-21 株式会社ジャパンディスプレイ 表示装置
JP2017168760A (ja) * 2016-03-18 2017-09-21 株式会社ジャパンディスプレイ 半導体装置

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JP2016146422A (ja) * 2015-02-09 2016-08-12 株式会社ジャパンディスプレイ 表示装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2017167452A (ja) * 2016-03-18 2017-09-21 株式会社ジャパンディスプレイ 表示装置
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