WO2024099415A1 - 一种电池片制备方法及电池片 - Google Patents

一种电池片制备方法及电池片 Download PDF

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Publication number
WO2024099415A1
WO2024099415A1 PCT/CN2023/130885 CN2023130885W WO2024099415A1 WO 2024099415 A1 WO2024099415 A1 WO 2024099415A1 CN 2023130885 W CN2023130885 W CN 2023130885W WO 2024099415 A1 WO2024099415 A1 WO 2024099415A1
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Prior art keywords
layer
battery cell
mask
cell substrate
mask layer
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PCT/CN2023/130885
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English (en)
French (fr)
Inventor
姚宇
李中天
申义铭
路承杰
黄肖儒
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苏州太阳井新能源有限公司
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Publication of WO2024099415A1 publication Critical patent/WO2024099415A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of photovoltaic cell and semiconductor manufacturing, and in particular to a cell preparation method and a cell.
  • the materials deposited on the cell substrate in sequence at low temperature are intrinsic amorphous silicon layer, doped amorphous silicon layer, and transparent conductive oxide layer (TCO layer).
  • the amorphous silicon layer is deposited by plasma enhanced chemical vapor deposition (PECVD), and the TCO layer is deposited by physical vapor deposition such as magnetron sputtering or reactive plasma deposition.
  • PECVD plasma enhanced chemical vapor deposition
  • TCO layer is deposited by physical vapor deposition such as magnetron sputtering or reactive plasma deposition.
  • material deposition is inevitable in the thickness direction of the cell substrate, i.e., the side wall.
  • the light-receiving side and the backlight side of a solar cell with double-sided electrodes are the two polarities of the cell, it is very important to form an insulating area on the side wall or the edge of one side to prevent local interconnection and short circuit of the two polarities.
  • the metal deposited on the side wall of the cell substrate is removed by post-etching, the metal deposited on the surface of the cell substrate will also be etched at the same time, making the post-etching method unusable unless the metal deposited on the surface of the cell substrate is protected during the post-etching process.
  • the anti-reflection layer or TCO layer on the cell substrate is usually formed by physical vapor deposition or chemical vapor deposition.
  • the cell substrate is usually placed on a tray with an opening, and the tray passes through a target section for depositing the light-receiving surface layer and a target section for depositing the backlight surface layer.
  • the position where the cell substrate contacts the tray is blocked, so transparent conductive oxide cannot be deposited to form a TCO layer, thereby exposing the doped semiconductor layer (such as an amorphous silicon or microcrystalline silicon layer) on the cell substrate.
  • the surface of the doped semiconductor layer 12 is in direct contact with external metal particles, which will reduce the efficiency of the prepared cell.
  • the surface of the doped semiconductor layer is in direct contact with the seed layer, which poses two risks: (1) the heat treatment (e.g., drying) process will cause the seed layer to diffuse into the cell substrate through the doped semiconductor layer, resulting in loss of electrical performance of the cell; and (2) the solution used to remove the seed layer contains copper ions, which are easily attached to the doped semiconductor layer during cleaning and diffuse into the cell during subsequent heat treatment and outdoor use of the cell, also resulting in loss of electrical performance of the cell.
  • An object of the present invention is to provide a method for preparing a battery cell, which at least solves one of the problems in the background technology.
  • An embodiment of the present invention provides a method for preparing a battery cell, comprising the following steps:
  • S11 forming a first mask layer on the first surface and/or the second surface of the battery cell substrate
  • S12 forming a mask opening on the first mask layer
  • S13 forming a second mask layer at the edge of the battery cell substrate, wherein the edge of the battery cell substrate at least includes the entire side wall of the battery cell substrate
  • S14 forming metal grid lines in the mask opening by electroplating
  • S15 removing the first mask layer and the second mask layer.
  • the first mask material is a photosensitive resin
  • the second mask material is a thermosetting resin
  • the surface of the battery cell substrate is divided into three regions A, B and C; the first surface of the battery cell substrate is composed of region A and region B, and the region B is adjacent to the edge of the first surface; on the first surface, the region B is annular, and the region B surrounds the region A; the region C is the entire side wall of the battery cell substrate;
  • the first mask layer covers the entire A area on the first surface and at least covers part of the B area on the first surface; the second mask layer covers the entire C area and at least covers part of the B area on the first surface; the first mask layer and the second mask layer partially overlap in the B area on the first surface.
  • the second surface of the battery cell substrate is composed of an A region and a B region, and the B region is adjacent to the edge of the second surface; on the second surface, the B region is annular, and the B region surrounds the A region; the first mask layer covers the entire A region on the second surface, and at least covers a portion of the B region on the second surface; the second mask layer covers at least a portion of the B region on the second surface, and the first mask layer and the second mask layer partially overlap in the B region on the second surface.
  • a cross-section of the second mask layer along the up-down direction is "C"-shaped.
  • the overlapping portion of the first mask layer and the second mask layer in region B is annular.
  • the edge of the first mask layer includes a first inclined thinning layer
  • the edge of the second mask layer includes a second inclined thinning layer
  • the first inclined thinning layer and the second inclined thinning layer overlap to form an overlapping portion of the first mask layer and the second mask layer in region B.
  • the coated second mask material sequentially covers along the edge of the first surface to form a first edge strip area, a second edge strip area, a third edge strip area and a fourth edge strip area, and the widths of the first edge strip area, the second edge strip area, the third edge strip area and the fourth edge strip area are d3, d4, d5 and d6 respectively, wherein the value ranges of d3, d4, d5 and d6 are all 0.2-5mm.
  • the left and right edges on the first surface of the battery cell substrate are first coated to form a first edge strip area and a third edge strip area, and then the upper and lower edges on the first surface of the battery cell substrate are coated to form a second edge strip area and a fourth edge strip area; the first edge strip area and the second edge strip area intersect, the first edge strip area and the fourth edge strip area intersect, the third edge strip area and the second edge strip area intersect, and the third edge strip area and the fourth edge strip area intersect.
  • the second mask material is coated on the edge of the first surface of the battery cell substrate in a counterclockwise or clockwise direction to form a ring-shaped area that intersects end to end.
  • the second mask layer is first dissolved and removed, and then the first mask layer is swollen and then separated from the battery cell substrate.
  • an anti-oxidation layer is disposed on the surface of the metal gate line.
  • the anti-oxidation layer covers the top and sidewalls of the metal gate line.
  • the anti-oxidation layer is obtained by a chemical replacement reaction.
  • step S13 is arranged after step S11 and before step S14; or, step S13 is arranged before step S11.
  • a first mask layer is firstly arranged on the first side and the second side of the battery cell substrate, the first mask layer does not completely cover the first side of the battery cell substrate and exposes the four sides of the first side of the battery cell substrate, the first mask layer does not completely cover the second side of the battery cell substrate and exposes the four sides of the second side of the battery cell substrate; then the second mask layer covers the four sides of the exposed first side and second side of the battery cell substrate, and the second mask layer covers the first mask layer, and the second mask layer does not cover the mask pattern.
  • the distance from one side of the first mask layer to the first side of the battery cell substrate is h1
  • the distance from one side of the mask pattern to the first side of the battery cell substrate is h2
  • the distance from one side of the second mask layer to the first side of the battery cell substrate is h3; then h1 is greater than 0 and h1 ⁇ h3 ⁇ h2.
  • the battery cell substrate includes a continuous first side, a second side and a third side, the first side and the third side are located on both sides of the second side, and the side length of the second side of the battery cell substrate is k1; the first mask layer is symmetrically distributed along the perpendicular bisector of the second side of the battery cell substrate, and the length of the first mask layer along the extension direction of the second side of the battery cell substrate is k2; along the extension direction of the second side of the battery cell substrate, the length of the mask pattern is k3, and the mask pattern is symmetrically distributed on the first mask layer along the perpendicular bisector of the second side of the battery cell substrate; the distance from one side of the mask pattern located on one side of the first side to the first side is h31, and the distance from the other side of the mask pattern located on one side of the third side to the third side is h32, and both h31 and h32 are within the value range of h3; then k1>k2 and 2h
  • the tolerance of k1 is ⁇ p; then k1-k2-p>0 and (k1+p-k2)/2 ⁇ h3 ⁇ (k1-p-k3)/2 are satisfied.
  • the metal gate line is a gate line with a width gradient.
  • the width of the second mask material covering the upper surface of the battery cell substrate is greater than the width of the second mask material covering the lower surface of the battery cell substrate.
  • the first surface of the cell substrate is a light-receiving surface and the second surface of the cell substrate is a backlight surface, so that the thickness of the first mask layer on the light-receiving surface is greater than the thickness of the first mask layer on the backlight surface.
  • the number of metal grid lines electroplated on the light-receiving surface is less than the number of metal grid lines electroplated on the backlight surface.
  • the battery cell preparation method further includes the following steps:
  • the value range of M is 40nm-80nm
  • the value range of N is 20-40um
  • the value range of T is 0.3-1.4mm.
  • the doped semiconductor layer and the TCO layer are sequentially arranged on the first surface and the second surface of the substrate structure layer in a direction away from the substrate structure layer, so that the thickness of the TCO layer on the first surface of the substrate structure layer is M to form a first TCO thinning layer, and/or, the thickness of the TCO layer on the second surface of the substrate structure layer is M to form a second TCO thinning layer.
  • step 33 is further included between step 31 and step 32, in which an isolation layer is disposed on the surface of the doped semiconductor layer.
  • step S34 is further included between step 31 and step 32 to clean and remove metal particles attached to the doped semiconductor layer.
  • step 21 is used to replace steps S11 and S12.
  • S21 forming a first mask layer having mask openings on the first surface and/or the second surface of the battery cell substrate.
  • the isolation layer only covers the defect pits on the TCO layer, or the isolation layer forms a new layer on the TCO layer and covers the defect pits at the same time.
  • Another object of the present invention is to provide a battery cell prepared by the above-mentioned battery cell preparation method.
  • a method for preparing a battery cell in an embodiment of the present invention has the following advantages:
  • a second mask layer is formed at the edge of the cell substrate, and the edge of the cell substrate includes at least the entire side wall of the cell substrate. This prevents the entire side wall of the cell substrate from being exposed, and avoids damage to the side wall of the cell substrate during the electroplating process of preparing metal grid lines, thereby improving the efficiency and yield of the prepared cell.
  • the second mask layer forms an insulating area on the side wall of the cell substrate, which can prevent short circuits caused by local interconnection of the double-sided electrodes.
  • a chemical replacement reaction is used on the metal gate line to obtain an anti-oxidation layer, and the anti-oxidation layer can be directly formed on the top and side walls of the metal gate line, which can better avoid damage to the metal gate line during subsequent processes and use.
  • a fine mask opening with a width of N is formed by printing and developing, and a metal grid line with a width of N is formed in the mask opening by electroplating, so that the spacing between adjacent metal grid lines on the same TCO layer can be reduced, that is, the number of metal grid lines on the same TCO layer will increase, and the shading area of all metal grid lines on the same TCO layer will not be enlarged; because the spacing between adjacent metal grid lines is reduced, the conductivity of all metal grid lines on the same TCO layer is improved, making it possible to reduce the thickness of the TCO layer.
  • the thickness of the TCO layer is made M to form a TCO thinning layer, and then according to the thickness of the TCO thinning layer, the metal grid lines are electroplated on the TCO thinning layer, and the width of the metal grid lines on the TCO thinning layer is controlled to be N, and the spacing between adjacent metal grid lines on the TCO thinning layer is T. Therefore, the thickness of the TCO layer can be reduced, saving the preparation cost of the battery cell, while maintaining or improving the efficiency of the prepared battery cell.
  • FIG1 is a schematic diagram of the area division on the surface of the battery cell substrate
  • FIG2 is a schematic diagram of the area division on the surface of the battery cell substrate including the F area;
  • FIG3 is a schematic structural diagram of the overlapping portion of the first mask layer and the second mask layer
  • FIG4 is a schematic diagram of the width dimension of the second mask layer
  • FIG5 is a schematic diagram of the coating process of the first second mask material
  • FIG6 is a schematic diagram of the coating process of the second mask material
  • FIG7 is a cross-sectional schematic diagram of a battery cell substrate after being covered with a first mask layer and a second mask layer;
  • FIG8 is a cross-sectional schematic diagram of the battery cell substrate after the second mask layer is dissolved
  • 9a-9g are cross-sectional schematic diagrams of a double-sided electrode battery cell during the preparation process in the first specific embodiment
  • 10a-10g are cross-sectional schematic diagrams of a double-sided electrode battery cell during the preparation process in the first specific embodiment
  • 11a-11g are cross-sectional schematic diagrams of a single-sided electrode battery cell during the preparation process in a second specific embodiment
  • 12a-12g are cross-sectional schematic diagrams of a single-sided electrode battery cell during the preparation process in a second specific embodiment
  • 13a, 13d and 13e are schematic cross-sectional views of a double-sided electrode battery cell substrate provided with a first mask layer and after the first mask layer is provided, respectively, in three preferred embodiments;
  • 13b and 13c are schematic diagrams of the dimensions of the double-sided electrode battery sheet substrate after the first mask layer is provided and the first mask layer is provided in two preferred embodiments respectively;
  • 15a-15b are schematic diagrams of the flow direction of coating the second mask material in two preferred embodiments.
  • 16a-16b are schematic structural diagrams of coating guide mechanisms in two preferred embodiments
  • FIG17 is a schematic diagram of the process of setting an isolation layer in the first specific implementation manner
  • FIG18 is a schematic diagram of a process of setting an isolation layer in a second specific implementation manner
  • 10-cell substrate 11-substrate structure layer, 111-crystalline silicon substrate layer, 112-intrinsic semiconductor layer, 113-thin film tunneling layer, 12-doped semiconductor layer, 13-TCO layer, 131-defect pits, 132-isolation layer, 14-seed layer, 15-conductive layer, 20-first mask layer, 21-first inclined thinning layer, 22-mask opening, 30-second mask layer, 31-second inclined thinning layer, 40-metal grid line, 210-"U"-shaped groove, 220-feed pipe, 230-blocking member, 240-discharge pipe.
  • the materials deposited on the cell substrate in sequence at low temperature are intrinsic amorphous silicon layer, doped amorphous silicon layer, and transparent conductive oxide layer (TCO layer).
  • the amorphous silicon layer is deposited by plasma enhanced chemical vapor deposition (PECVD), and the TCO layer is deposited by physical vapor deposition such as magnetron sputtering or reactive plasma deposition.
  • PECVD plasma enhanced chemical vapor deposition
  • TCO layer is deposited by physical vapor deposition such as magnetron sputtering or reactive plasma deposition.
  • material deposition is inevitable in the thickness direction of the cell substrate, i.e., the side wall.
  • the light-receiving side and the backlight side of the double-sided electrode cell are the two polarities of the cell, it is very important to form an insulating area on the side wall or the edge of one side to prevent local interconnection and short circuit of the two polarities.
  • the metal deposited on the side wall of the cell substrate is removed by post-etching, and the metal deposited on the surface of the cell substrate is also etched at the same time, making the post-etching method unusable unless the metal deposited on the surface of the cell substrate is protected during the post-etching process.
  • the embodiment of the present application proposes a method for preparing a cell, which improves the production process of the cell and avoids the deposition of metal on the side wall of the cell substrate.
  • the surface of the battery cell substrate 10 is divided into three areas A, B and C.
  • the first side of the battery cell substrate 10 is composed of area A and area B.
  • Area B is adjacent to the edge of the first side of the battery cell substrate 10.
  • Area B is a ring, and the ring here includes a round shape.
  • Area B surrounds area A, and area C is the entire side wall of the battery cell substrate 10; in the prior art, generally, a first mask layer 20 is completely coated on the first side of the battery cell substrate 10, and then the metal grid line 40 is prepared with the assistance of the first mask material.
  • the entire side wall of the battery cell substrate 10 is in a bare state. In the process of electroplating the metal grid line 40, the side wall of the battery cell substrate 10 will be damaged, thereby affecting the efficiency and yield of the prepared battery cell.
  • a method for preparing a battery cell comprises the following steps:
  • the first surface and the second surface are two opposite surfaces on the cell substrate 10.
  • the cell substrate 10 at least includes a substrate structure layer 11, a doped semiconductor layer 12 and a TCO layer 13 (wherein TCO is a transparent conductive oxide, the full name is transparent conductive oxide) from the inside to the outside.
  • the outermost layer of the first surface and/or the second surface of the cell substrate 10 can be the TCO layer 13.
  • the first mask layer 20 is formed on the TCO layer 13.
  • the TCO layer 13 includes any one or two of indium tin oxide (ITO), tungsten-doped indium oxide (IWO), aluminum-doped zinc oxide (ZnO z Al), gallium-doped zinc oxide (ZnO z GA) and Zn-in-Sn-O (ZITO).
  • the outermost layer of the first surface of the cell substrate 10 is the seed layer 14, and the outermost layer of the second surface of the cell substrate 10 is the seed layer 14 or the conductive layer 15; that is, the seed layer 14 or the conductive layer 15 is arranged outside the TCO layer 13, and the first mask layer 20 is formed on the seed layer 14 or the conductive layer 15.
  • the first mask layer 20 is formed on the seed layer 14 of the outermost layer of the first and second surfaces when the cell substrate 10 is a double-sided electrode substrate 10; when the outermost layer of the first surface of the cell substrate 10 is the seed layer 14, the outermost layer of the second surface of the cell substrate 10 is the conductive layer 15.
  • the first mask layer 20 is formed on the outermost seed layer 14 of the first surface and the outermost conductive layer 15 of the second surface.
  • the outermost layer of the cell substrate 10 includes at least one of the TCO layer 13, the seed layer 14 and the conductive layer 15.
  • the seed layer 14 can be electroplated on the first surface and/or the second surface of the cell substrate 10 by electroplating.
  • the seed layer 14 can be an activation layer composed of at least one material of aluminum, nickel, and palladium, or a TiW material layer or a TiN material layer.
  • the TiW material layer or the TiN material layer is mostly deposited by magnetron sputtering.
  • the cell substrate 10 is the substrate of a double-sided electrode cell, such as the substrate of a heterojunction battery. Taking Figure 1 as an example, the seed layer 14 completely covers the A area and the B area.
  • the seed layer 14 includes a single metal layer, a single metal alloy layer, or a multilayer structure consisting of at least two different single layers.
  • the material of the seed layer 14 can be copper, tin, cobalt, nickel, silver, tin-lead alloy, tin-silver alloy, copper-nickel alloy, copper-chromium alloy, copper-ruthenium alloy, copper-rhodium alloy, copper-silver alloy, copper-iridium alloy, copper-palladium alloy, copper-platinum alloy, copper-gold alloy and copper-rare earth alloy, copper-nickel-silver alloy and copper-nickel-rare earth metal alloy.
  • the material of the seed layer 14 is preferably copper, copper-nickel alloy, copper-tin alloy, copper-ruthenium alloy and copper-rhodium alloy.
  • the first mask layer 20 can be obtained by coating or deposition.
  • the first mask layer 20 is prepared on the seed layer 14 by coating, it needs to be dried; according to the coating thickness and material of the first mask layer 20, the drying time can be selected and set within the range of 5-15 minutes.
  • the material of the first mask layer 20 is a photosensitive resin, and the material of the photosensitive resin includes one or a mixed material of epoxy resin, acrylic resin, phenolic resin, novolac resin, melamine resin or polyurethane resin.
  • the photosensitive resin can also use organic materials such as benzocyclobutene, polyparaphenylene dimethyl, flare, polyimide, etc.
  • the positive photosensitive material can be a photosensitive material including novolac resin and naphthoquinone diazide compound as a photosensitizer.
  • the negative photosensitive material can be a photosensitive material including a base resin, diphenylsilanediol and an oxygen generator.
  • a coating mechanism is used to form the first mask layer 20, the coating mechanism includes a coating platform, a coating mold and a scraper, and the coating mold is provided with a coating hole that matches the size of the battery cell substrate 10.
  • Step S11 specifically includes:
  • the size of the coating hole is slightly smaller than the size of the cell substrate 10, that is, the edge of the coating hole is kept within the surface of the cell substrate 10, and the edge of the coating hole does not exceed the edge of the cell substrate 10.
  • the size of the cell substrate 10 is 166mm ⁇ 166mm ⁇ 130um
  • the size of the coating hole is 160mm ⁇ 160mm ⁇ 140um.
  • light can be irradiated to make a chemical reaction occur in a part of the area on the first mask layer 20, remove the part of the area on the first mask layer 20 where the chemical reaction occurs or remove the part of the area on the first mask layer 20 where the chemical reaction does not occur, and form a mask opening 22 on the first mask layer 20.
  • Making a chemical reaction occur in a part of the area on the first mask layer 20 by light irradiation is called printing; removing the part of the area on the first mask layer 20 where the chemical reaction occurs or the part of the area on the first mask layer 20 where the chemical reaction does not occur is called development; the purpose of printing and development is to obtain the mask opening 22.
  • the mask opening 22 passes through the first mask layer 20, and the bottom of the mask opening 22 is the TCO layer or the seed layer 14.
  • the purpose of forming the mask opening 22 is to expose the TCO layer 13 or the seed layer 14.
  • thermosetting resin may be a silicone resin, a polyamide resin, a polyolefin resin, a cyanate resin, a phenolic resin, a naphthalene resin or a fluorene resin.
  • the cell substrate 10 is a thin sheet structure, and the shape of the cell substrate 10 can be regarded as Rectangle or rectangle with at least one chamfered corner; when the cell substrate 10 is a rectangle with four chamfered corners, all the side walls of the cell substrate 10 include four flat side walls and four curved side walls; when the cell substrate 10 is a rectangle with four chamfered right angles, all the side walls of the cell substrate 10 include eight flat side walls; when the cell substrate 10 is a rectangle with two chamfered corners, all the side walls of the cell substrate 10 include four flat side walls and two curved side walls; when the cell substrate 10 is a rectangle, all the side walls of the cell substrate 10 include four flat side walls.
  • the shape of the cell substrate 10 may be illustrated as a rectangle or a square, which is only for the convenience of describing the principle of the present application. In actual production, the shape of the cell substrate 10 is more often expressed as a "rectangle" with four chamfered corners.
  • the second mask layer 30 is formed at the edge of the cell substrate 10 to protect the edge of the cell substrate 10.
  • Edge protection means covering the edge of the cell substrate 10, that is, forming the second mask layer 30 at the edge of the cell substrate 10 to prevent metal from being deposited on the side wall of the cell substrate 10 in the subsequent electroplating process. If the second mask layer 30 is only coated on the entire side wall of the cell substrate 10, the second mask layer 30 is easy to fall off, and a gap is easy to appear at the junction of the second mask layer 30 and the first mask layer 20, through which the outermost layer of the cell substrate 10 will be corroded; therefore, a continuous second mask layer 30 can be generated on the entire side wall and the edges of the upper and lower surfaces of the cell substrate 10.
  • the second mask layer 30 is similar to a shell with upper and lower openings, which can wrap the cell substrate 10 therein and expose the first and second surfaces.
  • the second mask layer 30 is similar to a shoe cover with a bottom opening, which can wrap the cell substrate 10 therein and expose the first and second surfaces, thereby reducing the risk of the second mask layer 30 falling off.
  • the cross-section of the second mask layer 30 along the upper and lower directions (or the thickness direction of the cell substrate 10) is a "C" shape, and the "C"-shaped structure can cover the cell substrate 10, thereby reducing the risk of the second mask layer 30 falling off.
  • the second mask layer 30 and the first mask layer 20 are coated at the junction of the second mask layer 30 and the first mask layer 20, thereby avoiding the problem of a gap being easily formed at the junction of the second mask layer 30 and the first mask layer 20.
  • the second mask layer 30 can be obtained by coating, and also needs to be dried after coating; according to the coating thickness and material of the second mask layer 30, the drying time can be selected and set within the range of 1-5 minutes.
  • the first mask layer 20 covers the entire A region on the first surface of the cell substrate 10, and at least covers part of the B region on the first surface of the cell substrate 10; the second mask layer 30 covers the entire C region, and at least covers part of the B region on the first surface of the cell substrate 10; and the first mask layer 20 and the second mask layer 30 have overlapping parts in the B region on the first surface of the cell substrate 10, so as to avoid the appearance of a gap at the junction of the second mask layer 30 and the first mask layer 20, resulting in the problem of corrosion of the outermost layer of the cell substrate 10.
  • the area covered by the second mask layer 30 is a continuous area, and the area covered by the first mask layer 20 on the first surface of the cell substrate 10 is a continuous area.
  • the edge of the aforementioned cell substrate 10 includes at least the C region, and may include all or part of the B region.
  • the overlapping part of the first mask layer 20 and the second mask layer 30 in the B region constitutes a ring, and the ring here includes a round shape, such as the F region shown in FIG. 2.
  • One side edge of the F region coincides with the edge of the surface of the cell substrate 10 where it is located, and the other side edge of the F region coincides with the edge of the A region or the other side edge of the F region is located in the B region.
  • the second mask layer 30 is first coated on the first surface of the cell substrate 10, the edge thickness of the second mask layer 30 gradually becomes thinner and is inclined toward the surface close to the cell substrate 10, forming a second inclined thinning layer 31, and then the first mask layer 20 is coated on the first surface of the cell substrate 10, the first mask layer 20 and the second mask layer 30 partially overlap, and the overlapping portion of the first mask layer 20 and the second inclined thinning layer 31 forms a first inclined thinning layer 21, and the first inclined thinning layer 21 is a thickness thinning layer of the first mask layer 20 and is inclined toward the surface away from the cell substrate 10.
  • the edge thickness of the second mask layer 30 gradually becomes thinner and is inclined toward the surface close to the cell substrate 10 forming a second inclined thinning layer 31, and then the first mask layer 20 is coated on the first surface of the cell substrate 10, the first mask layer 20 and the second mask layer 30 partially overlap, and the overlapping portion of the first mask layer 20 and the second inclined thinning layer 31 forms a first inclined thinning layer 21, and the first inclined th
  • the second inclined thinning layer 31 is an inclined surface structure
  • the first inclined thinning layer 21 is an inclined surface structure matched with the second inclined thinning layer 31.
  • the second inclined thinning layer 31 is a curved surface structure
  • the first inclined thinning layer 21 is a curved surface structure matched with the second inclined thinning layer 31.
  • the first mask layer 20 is firstly coated on the first surface of the cell substrate 10, the edge thickness of the first mask layer 20 gradually becomes thinner and tilts toward the surface close to the cell substrate 10, forming the first inclined thinning layer 21, and then the second mask layer 30 is coated on the first surface of the cell substrate 10, the second mask layer 30 and the first mask layer 20 partially overlap, and the overlapping part of the second mask layer 30 and the first inclined thinning layer 21 forms the second inclined thinning layer 31, and the second inclined thinning layer 31 is the thickness thinning layer of the second mask layer 30 and tilts toward the surface away from the cell substrate 10.
  • the first inclined thinning layer 21 is a bevel structure
  • the second inclined thinning layer 31 is a bevel structure that matches the first inclined thinning layer 21
  • the first inclined thinning layer 21 is a curved structure
  • the second inclined thinning layer 31 is a curved structure that matches the first inclined thinning layer 21.
  • the first inclined thinning layer 21 and the second inclined thinning layer 31 overlap to form the overlapping portion of the first mask layer 20 and the second mask layer 30 in the B region.
  • the first inclined thinning layer 21 is a bevel structure or a curved structure
  • the second inclined thinning layer 31 is also a bevel structure or a curved structure.
  • the contact area is expanded, so that the first mask layer 20 and the second mask layer 30 can be firmly combined together, reducing the risk of cracking at the junction of the first mask layer 20 and the second mask layer 30.
  • the second side of the cell substrate 10 is composed of region A and region B, and region B is adjacent to the edge of the second side; on the second side, region B is annular, and region B surrounds region A; the first mask layer 20 covers the second side.
  • the second mask layer 30 covers at least part of the B area on the second surface, and the first mask layer 20 and the second mask layer 30 partially overlap the B area on the second surface.
  • the second surface of the cell substrate 10 can also be applied to the technical solution of the first surface of the cell substrate 10.
  • the coated first mask material covers the forming area E
  • the coated second mask material covers the forming area D.
  • the areas E and D cover the entire first side of the cell substrate 10.
  • the cell substrate 10 is a square, and the side length of the cell substrate 10 is d0.
  • the specific value of d0 can be 156.75 mm, 158.75 mm, 166 mm, 182 mm or 210 mm.
  • the coated second mask material is formed along the first side.
  • the edge of the first surface is covered in sequence to form a first edge strip area, a second edge strip area, a third edge strip area and a fourth edge strip area, the widths of the first edge strip area, the second edge strip area, the third edge strip area and the fourth edge strip area are d3, d4, d5 and d6 respectively, and the value range of d3, d4, d5 and d6 is 0.2-5mm, preferably 0.3-1mm, so that the width of the area formed by the coated second mask material along the edge of the first surface is not too small, causing the second mask material to fall off easily, and at the same time making the coated
  • the width of the area formed by the second mask material covering along the edge of the first surface is not too large, which makes it difficult to remove the second mask material subsequently; preferably, the minimum value of d3, d4, d5 and d6 is not less than 0.2 mm, and the maximum value of d3, d4, d5 and d6 is not greater than 5 mm, so
  • region D may be region F in Figure 2
  • region E may be a single-layer first mask material coverage area.
  • the second surface of the cell substrate 10 is also a surface for electroplating metal grid lines 40, the above technical solution may also be applied, and the cell is a double-sided electrode cell.
  • first edge strip area, the second edge strip area, the third edge strip area and the fourth edge strip area may be rectangular areas, or may be rectangles with rounded corners or chamfered right angles.
  • the left and right edges on the first surface of the battery cell substrate 10 are first coated to form a first edge strip area D1 and a third edge strip area D3, and then the upper and lower edges on the first surface of the battery cell substrate 10 are coated to form a second edge strip area D2 and a fourth edge strip area D4; the first edge strip area D1 and the second edge strip area D2 intersect at an intersection area D12, the first edge strip area D1 and the fourth edge strip area D4 intersect at an intersection area D41, and the third edge strip area D2 and the fourth edge strip area D4 intersect at an intersection area D42.
  • the strip area D3 and the second edge strip area D2 intersect, and the intersection area is D23.
  • the third edge strip area D3 and the fourth edge strip area D4 intersect, and the intersection area is D34. This ensures that the second mask layer 30 can be completely closed to form a ring during the generation process. In the subsequent electroplating process, it can prevent metal ions from penetrating from the seams to the outermost layer of the cell substrate 10 and the side walls of the cell substrate 10, and it can also prevent the outermost layer of the cell substrate 10 from being corroded from the seams.
  • the second side of the cell substrate 10 is also a side of the electroplated metal grid line 40, the above technical solution can also be applied. At this time, the cell is a double-sided electrode cell.
  • the second mask material is applied on the edge of the first surface of the cell substrate 10 in a counterclockwise direction to form a region D.
  • the region D is annular and has only one intersection region, which is D41.
  • the second mask material may be applied on the edge of the first surface of the cell substrate 10 in a clockwise direction to form a region D.
  • the region D has only one intersection region, and the intersection region is small, which facilitates the subsequent removal of the second mask material.
  • the region D is formed continuously at one time, which is more efficient.
  • the second surface of the cell substrate 10 is also a surface for electroplating metal grid lines 40, the above technical solution may also be applied.
  • the cell is a double-sided electrode cell.
  • the second mask material may be first coated on three edges on the first surface of the cell substrate 10 in a counterclockwise (or clockwise) direction, and then coated on the fourth edge on the first surface of the cell substrate 10 to form a closed annular area D.
  • the material of the metal grid line 40 may be any one of copper, tin, silver and zinc and alloys thereof, and the metal grid line 40 may also be a stack of any two or more of copper, tin, silver and zinc.
  • the metal grid line 40 is a grid line with a width gradient, that is, the metal grid line 40 is divided into multiple layers distributed sequentially from top to bottom, and all the layers of the metal grid line 40 include a top layer located at the top, and there is at least one width expansion layer below the top layer, and the width of the width expansion layer is greater than the width of any layer above it.
  • step S15 includes first removing the first mask layer 20 and the second mask layer 30 , the seed layer 14 on the cell substrate 10 is then etched away; specifically, the seed layer 14 in the gaps between the metal grid lines 40 needs to be etched away, and the seed layer 14 at the root of the metal grid lines 40 connected to the TCO layer 13 is retained.
  • the first mask layer 20 and the second mask layer 30 can be removed by soaking or spraying with an alkaline solution, such as a NaOH solution; because the volume of the first mask layer 20 is much larger than that of the second mask layer 30, the second mask layer 30 is dissolved by soaking or spraying with an alkaline solution, and the first mask layer 20 is separated from the cell substrate 10 after foaming and swelling by soaking or spraying with an alkaline solution, without completely dissolving the first mask layer 20, which can improve the efficiency of removing the first mask layer 20 and reduce the amount of alkaline solution.
  • the first mask layer 20 separated from the cell substrate 10 is removed by filtering.
  • the cell from which the first mask layer 20 and the second mask layer 30 are removed is cleaned (e.g., washed with water) and dried, and then soaked in an acid solution to etch and remove the seed layer 14, and the acid solution here can be a sulfuric acid solution.
  • the acid solution here can be a sulfuric acid solution.
  • a dissolution gap X appears between the first mask layer 20 and the seed layer 14 .
  • the edge where the first mask layer 20 contacts the seed layer 14 can directly contact the alkaline solution, which can accelerate the foaming and swelling process of the first mask layer 20 , allowing the first mask layer 20 to quickly detach from the battery cell substrate 10 .
  • an anti-oxidation layer is provided on the surface of the metal grid line 40; the anti-oxidation layer may be a metal that is not easily oxidizable, such as tin or silver, or an alloy thereof, or an organic anti-oxidation layer.
  • the anti-oxidation layer may be obtained by electroplating (e.g., electroplating tin), or a tin protective layer or an organic anti-oxidation layer that wraps the entire metal grid line 40 (e.g., a copper grid line) may be formed by a chemical replacement reaction.
  • this step is arranged after step S14 and before step S15 to avoid oxidation damage to the metal gate line 40 in step S15; in this case, the anti-oxidation layer is formed before removing the first mask layer 20. If the anti-oxidation layer is obtained by electroplating, due to the obstruction of the first mask layer 20, the anti-oxidation layer can only form a protective layer on the top of the metal gate line 40, and cannot form a protective layer on the side wall of the metal gate line 40.
  • the side wall of the metal gate line 40 is still exposed and easily oxidized and corroded, so an anti-oxidation layer can be further formed on the side wall of the metal gate line 40; then, the anti-oxidation layer is obtained by chemical replacement reaction, and the anti-oxidation layer can be directly formed on the top and side wall of the metal gate line 40, which can better avoid step S15 from damaging the metal gate line 40, especially avoiding the side wall of the metal gate line 40 from being damaged in step S15.
  • the edge protection process of step S13 can be set after step S11 and before step S14. That is, the first mask material is first coated on the outermost layer of the battery cell substrate 10, and the first mask layer 20 is formed after drying; then the second mask material is coated on the edge and side wall of the battery cell substrate 10, and the second mask layer 30 is formed after drying.
  • the first mask layer 20 undergoes two drying processes, so that the first mask layer 20 is deeply attached to the outermost layer of the battery cell substrate 10, resulting in the first mask layer 20 not being easy to remove.
  • coating the first mask material on the outermost layer of the battery cell substrate 10 first can protect the outermost layer of the battery cell substrate 10 and prevent the outermost layer of the battery cell substrate 10 from being oxidized during the drying process, thereby improving the efficiency of the battery cell prepared by this method.
  • the cell substrate 10 of the double-sided electrode includes a substrate structure layer 11, and a doped semiconductor layer 12, a TCO layer 13 and a seed layer 14 are sequentially arranged on the first and second surfaces of the substrate structure layer 11 in a direction away from the substrate structure layer 11.
  • the first and second surfaces of the substrate structure layer 11 are two opposite surfaces.
  • the substrate structure layer 11 includes an N-type semiconductor layer (N-Si), and the doped semiconductor layers 12 on the first and second surfaces of the substrate structure layer 11 are P-type microcrystalline silicon layers (uc-Si(p)) and N-type microcrystalline silicon layers (uc-Si(n)), respectively, the TCO layer 13 is an ITO layer, and the seed layer 14 is a PVD Cu layer, and PVD Cu refers to a physical vapor deposition copper layer.
  • the first mask layer 20 is coated on the seed layer 14 on the first and second surfaces of the substrate structure layer 11 to obtain a structure as shown in FIG9b; preferably, the thickness of the first mask layer 20 is thin on all sides and thick in the middle.
  • the first mask layer 20 on the first and second surfaces of the substrate structure layer 11 is printed and developed to generate mask openings 22 thereon, and a structure as shown in FIG9c is obtained, wherein the mask openings 22 are all formed in the middle of the first mask layer 20, and no mask openings 22 are arranged on the four edges of the first mask layer 20, so as to prevent the subsequent second mask layer 30 from covering the mask openings 22 on the four edges of the first mask layer 20; preferably, the thickness of the first mask layer 20 is thin on all sides and thick in the middle, and the mask openings 22 are arranged on the central protrusion of the first mask layer 20, and the thinned portions on the four edges of the first mask layer 20 cooperate with the second mask layer 30, and the thinned portions on the four edges of the first mask layer 20 can drain and guide the coated second mask material, so as to facilitate the generation of the second mask layer 30.
  • the second mask layer 30 is coated on all the side walls of the cell substrate 10 and on the four edges of the first mask layer 20 on both sides of the substrate structure layer 11 to obtain the structure shown in FIG9d.
  • the second mask layer 30 forms a zigzag structure on the first mask layer 20 on both sides of the substrate structure layer 11.
  • the cross section of the second mask layer 30 forms a "C" shape along the thickness direction.
  • the metal grid line 40 is electroplated in the mask opening 22 on the first and second sides of the substrate structure layer 11 to obtain the structure shown in FIG9e.
  • the metal grid line 40 is preferably a copper grid line and a metal tin layer is electroplated thereon. The metal tin layer covers the top of the copper grid line.
  • the first mask layer 20 and the second mask layer 30 are removed to obtain the structure shown in FIG9f.
  • the seed layer 14 on the first and second sides of the substrate structure layer 11 is removed by etching to expose the metal grid line 40 to form a cell, and the structure shown in FIG9g is obtained.
  • the single-sided electrode cell substrate 10 includes a substrate structure layer 11, and a doped semiconductor layer 12 and a TCO layer 13 are sequentially arranged on the first and second surfaces of the substrate structure layer 11 in a direction away from the substrate structure layer 11, a seed layer 14 is arranged on the TCO layer 13 located on the first surface, and a conductive layer 15 is arranged on the TCO layer 13 located on the second surface, and the first and second surfaces of the substrate structure layer 11 are two opposite surfaces.
  • the substrate structure layer 11 includes an N-type semiconductor layer (N-Si), and the doped semiconductor layers 12 on the first and second surfaces of the substrate structure layer 11 are respectively P-type microcrystalline silicon layers (uc-Si(p)) and N-type microcrystalline silicon layers (uc-Si(n)), the TCO layer 13 is an ITO layer, and the seed layer 14 is a PVD Cu layer.
  • a first mask layer 20 is coated on the seed layer 14 and the conductive layer 15 to obtain a structure as shown in FIG10b, and preferably, the thickness of the first mask layer 20 is thin on all sides and thick in the middle.
  • the first mask layer 20 on the seed layer 14 is printed and developed to generate mask openings 22 thereon, and a structure as shown in FIG10c is obtained, wherein the mask openings 22 are all formed in the middle of the first mask layer 20, and no mask openings 22 are set on the four edges of the first mask layer 20, so as to prevent the subsequent second mask layer 30 from covering the mask openings 22 on the four edges of the first mask layer 20; preferably, the thickness of the first mask layer 20 is thin on all sides and thick in the middle, and the mask openings 22 are set on the central protrusion of the first mask layer 20, and the thinned portions on the four edges of the first mask layer 20 cooperate with the second mask layer 30, and the thinned portions on the four edges of the first mask layer 20 can drain and guide the coated second mask material, so as to facilitate the generation of the second mask layer 30.
  • the second mask layer 30 is coated on all the side walls of the cell substrate 10 and on the four edges of the first mask layer 20 on both sides of the substrate structure layer 11 to obtain the structure shown in FIG10d.
  • the second mask layer 30 forms a zigzag structure on the first mask layer 20 on both sides of the substrate structure layer 11.
  • the cross section of the second mask layer 30 forms a "C" shape along the thickness direction.
  • the metal grid line 40 is electroplated in the mask opening 22 on the first side of the substrate structure layer 11 to obtain the structure shown in FIG10e.
  • the metal grid line 40 is preferably a copper grid line and a metal tin layer is electroplated thereon.
  • the metal tin layer covers the top of the copper grid line.
  • the first mask layer 20 and the second mask layer 30 are removed to obtain the structure shown in FIG10f.
  • the seed layer 14 on the first side is etched to remove the metal grid line 40, and the cell is formed to obtain the structure shown in FIG10g.
  • the edge protection process of step S13 can be set before step S11. That is, the second mask material is first applied to the edge and side wall of the cell substrate 10, and the second mask layer 30 is formed after drying; then the first mask material is applied to the outermost layer of the cell substrate 10, and the first mask layer 20 is formed after drying.
  • the outermost layer of the cell substrate 10 in the process of drying the second mask material, the outermost layer of the cell substrate 10 is in a bare state and is easily oxidized, resulting in a decrease in the efficiency of the prepared cell; therefore, the process of drying the second mask material can be carried out in an inert gas protection environment to avoid oxidation of the outermost layer of the exposed cell substrate 10.
  • the first mask layer 20 coated on the outermost layer of the cell substrate 10 is only dried once, so that the first mask layer 20 is easy to be removed, which can improve the production efficiency of the cell.
  • Figures 11a-11g are schematic cross-sectional views of a double-sided electrode cell during the preparation process in the second specific implementation method.
  • the cell substrate 10 of the double-sided electrode includes a substrate structure layer 11, and a doped semiconductor layer 12, a TCO layer 13 and a seed layer 14 are sequentially arranged on the first and second surfaces of the substrate structure layer 11 in a direction away from the substrate structure layer 11.
  • the first and second surfaces of the substrate structure layer 11 are opposite sides.
  • the substrate structure layer 11 includes an N-type semiconductor layer (N-Si), and the doped semiconductor layers 12 on the first and second surfaces of the substrate structure layer 11 are respectively P-type microcrystalline silicon layers (uc-Si(p)) and N-type microcrystalline silicon layers (uc-Si(n)), the TCO layer 13 is an ITO layer, and the seed layer 14 is a PVD Cu layer.
  • the second mask layer 30 is coated on all side walls of the cell substrate 10 and on the four edges of the seed layer 14 on both sides of the substrate structure layer 11 to obtain the structure shown in FIG11b.
  • the second mask layer 30 forms a meandering structure on the seed layer 14 on both sides of the substrate structure layer 11.
  • the cross section of the second mask layer 30 forms a "C" shape along the thickness direction.
  • the first mask layer 20 is coated on both sides of the substrate structure layer 11 to generate the first mask layer 20.
  • the middle part of the first mask layer 20 fills the middle opening of the meandering structure and covers the seed layer 14.
  • the outer part of the first mask layer 20 covers the four edges of the meandering structure to obtain the structure shown in FIG11c.
  • the first mask layer 20 on the first and second surfaces of the substrate structure layer 11 is printed and developed to generate mask openings 22 thereon, and a structure as shown in FIG11d is obtained.
  • the mask openings 22 are all formed on the first mask layer 20 covering the seed layer 14, and the mask openings 22 are not arranged on the overlapping portion of the first mask layer 20 and the second mask layer 30, so as to avoid destroying the bonding force between the first mask layer 20 and the second mask layer 30, and at the same time reduce the risk of deformation of the mask opening 22 due to multilayer materials.
  • the metal grid lines 40 are electroplated in the mask openings 22 on both sides of the substrate structure layer 11 to obtain a structure as shown in FIG11e.
  • the metal grid lines 40 are preferably copper grid lines and a metal tin layer is electroplated thereon, and the metal tin layer covers the top of the copper grid lines.
  • the first mask layer 20 and the second mask layer 30 are removed to obtain a structure as shown in FIG11f; the seed layer 14 on the first and second surfaces of the substrate structure layer 11 is etched and removed to expose the metal grid lines 40, and a battery cell is formed to obtain a structure as shown in FIG11g.
  • Figures 12a-12g are cross-sectional schematic diagrams of a single-sided electrode cell during the preparation process in the second specific embodiment.
  • the single-sided electrode cell substrate 10 includes a substrate structure layer 11, and a doped semiconductor layer 12 and a TCO layer 13 are sequentially arranged on the first and second surfaces of the substrate structure layer 11 in a direction away from the substrate structure layer 11, a seed layer 14 is arranged on the TCO layer 13 on the first surface, and a conductive layer 15 is arranged on the TCO layer 13 on the second surface, and the first and second surfaces of the substrate structure layer 11 are opposite to each other.
  • the substrate structure layer 11 includes an N-type semiconductor layer (N-Si), the doped semiconductor layers 12 on the first and second surfaces of the substrate structure layer 11 are respectively a P-type microcrystalline silicon layer (uc-Si(p)) and an N-type microcrystalline silicon layer (uc-Si(n)), the TCO layer 13 is an ITO layer, and the seed layer 14 is a PVD Cu layer.
  • the second mask layer 30 is coated on all side walls of the cell substrate 10 and on the four edges of the seed layer 14 and the conductive layer 15 to obtain a structure as shown in FIG. 12b.
  • the second mask layer 30 forms a meandering structure on the seed layer 14 and the conductive layer 15, respectively.
  • the cross section of the second mask layer 30 forms a "C" shape.
  • the first mask layer 20 is coated on both sides of the substrate structure layer 11.
  • the middle part of the first mask layer 20 fills the middle opening of the meandering structure and covers the seed layer 14, and the outer part of the first mask layer 20 covers the four sides of the meandering structure.
  • the middle part of the first mask layer 20 fills the middle opening of the meandering structure and covers the conductive layer 15, and the outer part of the first mask layer 20 covers the four sides of the meandering structure, thereby obtaining a structure as shown in FIG12c.
  • the first mask layer 20 on the first surface of the substrate structure layer 11 is printed and developed to generate a mask opening 22 thereon, and a structure as shown in FIG12d is obtained.
  • the mask opening 22 is entirely formed on the first mask layer 20 covering the seed layer 14, and the mask opening 22 is not arranged on the overlapping portion of the first mask layer 20 and the second mask layer 30, so as to avoid destroying the bonding force between the first mask layer 20 and the second mask layer 30, and at the same time reduce the risk of deformation of the mask opening 22 due to multi-layer materials.
  • the metal grid line 40 is electroplated in the mask opening 22 to obtain a structure as shown in FIG12e, and the metal grid line 40 is preferably a copper grid line and a metal tin layer is electroplated thereon, and the metal tin layer covers the top of the copper grid line.
  • the first mask layer 20 and the second mask layer 30 are removed to obtain a structure as shown in FIG12f; the seed layer 14 is etched to remove the metal grid line 40, and a battery cell is formed to obtain a structure as shown in FIG12g.
  • the first mask layer 20 and the second mask layer 30 can both be material layers with uniform thickness.
  • a first mask layer 20 is firstly arranged on the first and second surfaces of the cell substrate 10, wherein the first mask layer 20 does not completely cover the first surface of the cell substrate 10 and exposes the four sides of the first surface of the cell substrate 10, and the first mask layer 20 does not completely cover the second surface of the cell substrate 10 and exposes the four sides of the second surface of the cell substrate 10, so as to avoid the first mask material applied when forming the first mask layer 20 from falling onto the coating platform and contaminating the coating platform; then the second mask layer 30 covers the four sides of the first and second surfaces of the exposed cell substrate 10, and the second mask layer 30 covers the first mask layer 20, and the second mask layer 30 does not cover the mask pattern, so as to ensure that there is an overlapping portion between the second mask layer 30 and the first mask layer 20, so as to avoid a gap at the junction of the second mask layer 30 and the first mask layer 20, and at the same time avoid the second mask layer 30 covering the mask pattern and affecting the subsequent electroplating grid lines.
  • the distance from one side of the first mask layer 20 to the first side of the cell substrate 10 is h1
  • the distance from one side of the mask pattern to the first side of the cell substrate 10 is h2
  • the distance from one side of the second mask layer 30 to the first side of the cell substrate 10 is h3, then h1 is greater than 0 and h1 ⁇ h3 ⁇ h2.
  • the first side of the cell substrate 10 is any side on the cell substrate 10, but not a chamfered side.
  • the battery cell substrate 10 includes a continuous first side, a second side and a third side, the first side and the third side are located on both sides of the second side, and the side length of the second side of the battery cell substrate 10 is k1; the first mask layer 20 is symmetrically distributed along the perpendicular bisector of the second side of the battery cell substrate 10, and the length of the first mask layer 20 along the extension direction of the second side of the battery cell substrate 10 is k2; along the extension direction of the second side of the battery cell substrate 10, the length of the mask pattern is k3, and the mask pattern is symmetrically distributed on the first mask layer 20 along the perpendicular bisector of the second side of the battery cell substrate 10; the distance from one side of the mask pattern on one side of the first side to the first side is h31, and the distance from the other side of the mask pattern on one side of the third side to the third side is h32, and both h31 and h32 are within the value range of h3;
  • the tolerance of k1 is ⁇ p; when the length of the second side of the battery cell substrate 10 is k1-p, k1-k2-p>0 and (k1-p-k2)/2 ⁇ h3 ⁇ (k1-p-k3)/2 are satisfied; when the length of the second side of the battery cell substrate 10 is k1+p, k1-k2+p>0 and (k1+p-k2)/2 ⁇ h3 ⁇ (k1+p-k3)/2 are satisfied; in a more preferred embodiment, k1-k2-p>0 and (k1+p-k2)/2 ⁇ h3 ⁇ (k1-p-k3)/2, h3 takes any value within this range, which can ensure that the first mask layer 20 and the second mask layer 30 are set for all battery cell substrates 10 within the tolerance range of ⁇ p.
  • the mask pattern is composed of the aforementioned mask openings 22 .
  • a second mask layer 30 is firstly arranged on the edge of the battery cell substrate 10, and then a first mask layer 20 is arranged.
  • the first mask layer 20 does not completely cover the second mask layer 30 on the first surface of the battery cell substrate 10, and the first mask layer 20 does not completely cover the second mask layer 30 on the second surface of the battery cell substrate 10.
  • a zigzag step is formed on the four edges of the first surface and the second surface of the battery cell substrate 10, respectively, to prevent the first mask material applied when forming the first mask layer 20 from falling onto the coating platform and contaminating the coating platform.
  • the metal grid line 40 obtained by screen printing has a height of 15um-20um and a line width of about 45um. Due to the limitation of the screen, the line width of the metal grid line 40 cannot be greatly reduced, and the aspect ratio cannot be improved.
  • a narrower mask opening 22 can be obtained by printing and developing, and then a narrower metal grid line 40 can be obtained by electroplating.
  • the height of the metal grid line 40 can reach 8um-15um, and the line width is 10um-20um. Therefore, the electroplating method can obtain a narrower metal grid line 40 and a metal grid line 40 with a larger aspect ratio, reduce the light shielding area of the metal grid line 40, and improve the efficiency of the prepared solar cell.
  • the first surface of the cell substrate 10 is the light-receiving surface
  • the second surface of the cell substrate 10 is the backlight surface
  • the depth of the mask opening 22 on the light-receiving surface is greater than the depth of the mask opening 22 on the backlight surface, and then the height of the metal grid line 40 on the light-receiving surface is greater than the height of the metal grid line 40 on the backlight surface, thereby improving the aspect ratio of the metal grid line 40 on the light-receiving surface and improving the efficiency of the prepared cell.
  • the thickness of the first mask layer 20 on the backlight surface is reduced, the amount used is reduced, and the cost can be saved.
  • the number of metal grid lines 40 electroplated on the light-receiving surface is less than the number of metal grid lines 40 on the backlight surface, and the width of the metal grid lines 40 electroplated on the light-receiving surface is less than the width of the metal grid lines 40 on the backlight surface, thereby reducing the shading area of the metal grid lines 40 on the light-receiving surface and further improving the aspect ratio of the metal grid lines 40 on the light-receiving surface, thereby improving the efficiency of the prepared battery cell.
  • the number of metal grid lines 40 on the backlight surface is relatively large, and the width of the metal grid lines 40 on the backlight surface is relatively large, thereby improving the conductive performance of the backlight surface of the prepared battery cell.
  • the substrate structure layer 11 includes a crystalline silicon substrate layer 111 and intrinsic semiconductor layers 112 arranged on both sides thereof; in a preferred embodiment, referring to Figure 14b, a thin film tunneling layer 113 is also arranged between the crystalline silicon substrate layer 111 and the intrinsic semiconductor layer 112, and the thin film tunneling layer 113 includes any one of silicon oxide ( SiO2 ), silicon nitride ( SiNx ), silicon oxynitride ( SiOxNy ), aluminum oxide ( Al2O3 ) and titanium oxide ( TiO2 ).
  • the drying time of the first coating material is shorter than the drying time of the second coating material; when the first coating material is the first mask material and the second coating material is the second mask material, the drying time of the first mask material is shorter than the drying time of the second mask material; when the first coating material is the second mask material and the second coating material is the first mask material, the drying time of the second mask material is shorter than the drying time of the first mask material.
  • the first coating material is also dried again. In order to avoid the first coating material from drying too long and causing over-curing, the drying time of the first coating material is shorter than the drying time of the second coating material.
  • the spraying point for coating the second mask material on the battery cell substrate 10 is set on the edge of the battery cell substrate 10, as shown in Figure 15a, the battery cell substrate 10 is placed horizontally, and the spraying point for coating the second mask material is set on the left edge of the battery cell substrate 10.
  • the second mask material when the second mask material is sprayed, when the second mask material contacts the surface of the battery cell substrate 10, it diffuses from the contact point to the surrounding area, to the right is the middle of the battery cell substrate 10, and to the left is the edge of the battery cell substrate 10.
  • the second mask material diffuses to the edge of the battery cell substrate 10, it will be accelerated and driven to flow downward along the left side wall of the battery cell substrate 10 under the action of gravity.
  • the second mask material has surface tension, and the second mask material on the left side wall will pull the second mask material on the left edge of the battery cell substrate 10 to move to the left. Under the guidance of the coating guide mechanism, the second mask material on the left side wall flows to the lower surface of the battery cell substrate 10. There is one spraying point for the second mask material, and spraying around the cell substrate 10 in one circle can complete spraying the second mask material on the cell substrate 10.
  • the cell substrate 10 is placed horizontally, and there are two spraying points for the second mask material, which are respectively set on the left edge and the right edge of the cell substrate 10, and the two spraying points simultaneously coat the left edge and the right edge of the cell substrate 10; after the coating of the left edge and the right edge of the cell substrate 10 is completed, the cell substrate 10 is rotated 90 degrees or the two spraying points are moved to the front and rear edges of the cell substrate 10, and then the front and rear edges of the cell substrate 10 are coated simultaneously. In other embodiments, there can be four spraying points, and the four edges of the cell substrate 10 are coated simultaneously or sequentially.
  • the coating guide mechanism includes a "U"-shaped groove 210 and a feed pipe 220 arranged on a side wall of the "U"-shaped groove 210, and the feed pipe 220 is connected to the "U"-shaped groove 210; during coating, the edge of the battery cell substrate 10 is inserted into the "U"-shaped groove 210, so that a "U"-shaped filling area is formed in the "U”-shaped groove 210, and the feed pipe 220 is located above the battery cell substrate 10.
  • the second mask material flows from the feed pipe 220 into the "U”-shaped filling area.
  • the second mask material fills the "U"-shaped filling area, and the coating of a section of the edge of the battery cell substrate 10 is completed.
  • the coating guide mechanism moves relative to the battery cell substrate 10 to complete the coating of subsequent continuous areas.
  • No blocking member is provided at the outlet of the “U”-shaped groove 210 , and the width (the length in the left-right direction in the figure) covered by the second mask material on the upper surface of the cell substrate 10 is greater than the width covered by the second mask material on the lower surface of the cell substrate 10 .
  • a blocking member 230 is provided at the outlet of the "U"-shaped groove 210 to limit the flow position of the second mask material on the upper and lower surfaces of the battery cell substrate 10, so as to keep the width of the second mask material covering the upper surface of the battery cell substrate 10 equal to the width of the second mask material covering the lower surface of the battery cell substrate 10.
  • a discharge pipe 240 is provided on the other side wall of the "U"-shaped groove 210, and the discharge pipe 240 is located below the battery cell substrate 10. In this embodiment, the second mask material can be fed from the discharge pipe 240 and then discharged from the feed pipe 220.
  • a method for preparing a battery cell comprises the following steps:
  • the mask opening 22 in this embodiment is formed at the same time as the first mask layer 20 is formed.
  • the first mask material is coated on a local area on the seed layer 14, and the area on the seed layer 14 not coated with the first mask material exposes the seed layer 14, and the area on the seed layer 14 not coated with the first mask material constitutes the mask opening 22.
  • step S21 includes the following steps:
  • a mask screen can accurately control the molding of the first mask layer 20 having the mask opening 22, especially when the viscosity of the first mask material is low, the shape of the mask opening 22 can be well controlled to avoid deformation of the mask opening 22 during the molding process.
  • the mask screen can be removed first, and then the first mask material is dried and cured to form the first mask layer 20 having the mask opening 22; or the mask screen can be removed during the drying process.
  • step S15 includes first removing the first mask layer 20 and the second mask layer 30 , and then etching to remove the seed layer 14 on the cell substrate 10 .
  • Example 1 This embodiment is improved on the basis of Example 1, and the technical details that are the same as those in Example 1 are omitted in this embodiment. It should be understood that the technical solutions and technical details in Example 1 can also be applied to this embodiment without violating the principles of this embodiment.
  • this embodiment provides a method for preparing a battery cell, comprising the following steps:
  • a TCO layer 13 is arranged on the substrate structure layer 11, so that the thickness of at least one TCO layer 13 is M to form a TCO thinning layer; there may be one or two TCO layers 13 on the substrate structure layer 11.
  • the thickness of the one TCO layer 13 can be M to form a TCO thinning layer;
  • the thickness of one of the two TCO layers 13 can be M to form a TCO thinning layer, or the thickness of both of the two TCO layers 13 can be M to form two TCO thinning layers.
  • the value range of M is 40nm-80nm
  • the value range of N is 20-40um
  • the value range of T is 0.3-1.4mm.
  • the value of M can be 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm or 75nm;
  • the value of N can be 20um, 22um, 24um, 26um, 28um, 30um, 32um, 34um, 36um, 38um or 40um, and the value of T can be 0.3mm, 0.4mm, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1.0mm, 1.1mm, 1.2mm, 1.3mm or 1.4mm.
  • a doped semiconductor layer 12 and a TCO layer 13 are sequentially arranged on the first surface and the second surface of the substrate structure layer 11 in a direction away from the substrate structure layer 11, so that the thickness of the TCO layer 13 on the first surface of the substrate structure layer 11 is M to form a first TCO thinning layer, and/or, the thickness of the TCO layer 13 on the second surface of the substrate structure layer 11 is M to form a second TCO thinning layer.
  • the thickness of the TCO layer 13 on the first side and the second side of the substrate structure layer 11 is M, and a first TCO thinning layer and a second TCO thinning layer are formed accordingly; in step 32, metal grid lines 40 are electroplated on the first TCO thinning layer and the second TCO thinning layer, and according to the thickness of the first TCO thinning layer, the width of the metal grid lines 40 on the first TCO thinning layer is controlled to be N, and the spacing between adjacent metal grid lines 40 on the first TCO thinning layer is T, and/or, according to the thickness of the second TCO thinning layer, the width of the metal grid lines 40 on the second TCO thinning layer is controlled to be N, and the spacing between adjacent metal grid lines 40 on the second TCO thinning layer is T.
  • the spacing is T.
  • the thickness of the TCO layer 13 on the first surface or the second surface of the substrate structure layer 11 is set to M to form a TCO thinning layer on the corresponding surface; in step 32, metal grid lines 40 are electroplated on the TCO thinning layer, and the width of the metal grid lines 40 on the TCO thinning layer is controlled to be N according to the thickness of the TCO thinning layer, and the spacing between adjacent metal grid lines 40 on the TCO thinning layer is T.
  • Reducing the thickness of the TCO layer 13 to form a TCO thinning layer will cause the conductivity of the TCO layer 13 to be weakened and the light transmittance to be improved; reducing the spacing between adjacent metal grid lines 40 can compensate for the conductivity of the TCO layer 13, so that the efficiency of the prepared battery cell will not be reduced due to the weakening of the conductivity of the TCO layer 13.
  • the number of metal grid lines 40 on the same TCO thinning layer will increase, which will increase the total shading area of all metal grid lines 40 on the same TCO thinning layer, and will reduce the efficiency of the prepared battery cell; using the electroplating method, narrower metal grid lines 40 can be obtained.
  • the method for forming the metal grid lines 40 in step S32 may adopt the technical solutions of embodiments 1-2 to improve the efficiency of the prepared solar cell.
  • a seed layer 14 is first provided on the TCO layer 13 on the first surface and/or the second surface of the substrate structure layer 11, the metal gate line 40 is electroplated on the seed layer 14, and then the seed layer 14 is etched away.
  • the anti-reflection layer or TCO layer 13 on the cell substrate 10 is usually formed by physical vapor deposition or chemical vapor deposition.
  • transparent conductive oxide needs to be deposited on both the light-receiving surface and the backlight surface to form the TCO layer 13.
  • the cell substrate 10 is usually placed on a tray with an opening, and the tray passes through a target section for depositing the light-receiving surface layer and a target section for depositing the backlight surface layer. The position where the cell substrate 10 contacts the tray is blocked, so transparent conductive oxide cannot be deposited to form the TCO layer 13, thereby exposing the doped semiconductor layer 12 (such as an amorphous silicon or microcrystalline silicon layer) on the cell substrate 10.
  • the doped semiconductor layer 12 such as an amorphous silicon or microcrystalline silicon layer
  • the surface of the doped semiconductor layer 12 is in direct contact with external metal particles, which will reduce the efficiency of the prepared cell.
  • the surface of the doped semiconductor layer 12 is in direct contact with the seed layer 14, which poses two risks: (1) the heat treatment (e.g., drying) process may cause the seed layer 14 to diffuse into the cell substrate 10 through the doped semiconductor layer 12, causing loss of electrical performance of the cell; (2) the solution for removing the seed layer 14 contains copper ions, which are easily attached to the doped semiconductor layer 12 during cleaning and diffuse into the cell substrate 10 during subsequent heat treatment and outdoor use of the cell, also causing loss of electrical performance of the cell.
  • the metal particles include metal elements on the seed layer 14, such as copper elements, and copper ions.
  • a cell preparation method in this embodiment further includes step 33 between step 31 and step 32, which is to provide an isolation layer 132 on the surface of the doped semiconductor layer 12.
  • the isolation layer 132 is provided on the surface of the doped semiconductor layer 12 by vapor deposition.
  • the cell substrate 10 includes a TCO layer 13, and there is a defect pit 131 on the TCO layer 13 that exposes the doped semiconductor layer 12, and an isolation layer 132 is used to cover the defect pit 131.
  • the isolation layer 132 only covers the defect pit 131 on the TCO layer 13, and does not increase the thickness of the cell substrate 10; in the solution in Figure 18, the isolation layer 132 forms a new layer on the TCO layer 13 and covers the defect pit 131 at the same time, so there is no need to identify the position of the defect pit 131 in advance, and the defect pit 131 can be quickly compensated.
  • the anti-reflection layer or TCO layer 13 basically covers the doped semiconductor layer 12 of the cell substrate 10, but due to defects in the manufacturing process, the anti-reflection layer or TCO layer 13 cannot completely cover the doped semiconductor layer 12 of the cell substrate 10, so that there is a partially exposed doped semiconductor layer 12.
  • an isolation layer 132 is provided (preferably deposited) on the partially exposed doped semiconductor layer 12, and the material of the isolation layer 132 can be the same as that of the anti-reflection layer or TCO layer 13.
  • the material of the anti-reflection layer can be silicon oxide, silicon nitride or aluminum oxide, etc.
  • step S34 is further included between step 31 and step 32: cleaning and removing metal particles attached to the doped semiconductor layer 12.
  • the cleaning solution is a mixed solution of an acid, a complexing agent, and an oxidant, and is sprayed without reuse or immersed in a large flow circulation.
  • step S35 is further included after step 32, forming an anti-reflection layer on the TCO layer 13.
  • the anti-reflection layer can increase the light transmittance of the prepared cell and further improve the efficiency of the prepared cell.
  • a method for preparing a battery cell includes the following steps:
  • the process of electroplating the metal grid line 40 in step S32 includes:
  • the isolation layer 132 may be a covering layer on the TCO thinning layer, and the sum of the thicknesses of the isolation layer 132 and the TCO thinning layer is M.
  • the mask opening 22 is obtained by printing and developing.
  • a fine mask opening 22 with a width of N is formed by printing and developing, and a metal grid line 40 with a width of N is formed in the mask opening 22 by electroplating, so that the spacing between adjacent metal grid lines 40 on the same TCO layer 13 can be reduced, that is, the number of metal grid lines 40 on the same TCO layer 13 will increase, and the shading area of all metal grid lines 40 on the same TCO layer 13 will not be enlarged; because the spacing between adjacent metal grid lines 40 is reduced, the conductivity of all metal grid lines 40 on the same TCO layer 13 is improved, making it possible to reduce the thickness of the TCO layer 13.
  • the thickness of the TCO layer 13 is made M to form a TCO thinning layer, and then the metal grid lines 40 are formed by electroplating on the TCO thinning layer according to the thickness of the TCO thinning layer, and the width of the metal grid lines 40 on the TCO thinning layer is controlled to be N, and the spacing between adjacent metal grid lines 40 on the TCO thinning layer is T. Therefore, the thickness of the TCO layer 13 is reduced, which saves the manufacturing cost of the battery cell, while maintaining or improving the efficiency of the manufactured battery cell.
  • steps S11 and S12 may be replaced by step S31 .
  • Step S31 forming a first mask layer having mask openings on the first surface and/or the second surface of the battery cell substrate.
  • An embodiment of the present invention further provides a battery cell, which is prepared by the method in Embodiment 1 to Embodiment 3, so the battery cell also has the characteristics and advantages of the method in Embodiment 1 to Embodiment 3.
  • the first surface of the cell substrate 10 refers to a surface of the cell substrate 10 or a surface of a material layer that is in direct or indirect contact with the surface.
  • a first mask layer 20 is disposed on a surface of the cell substrate 10, which can be expressed as a first mask layer 20 is disposed on the first surface of the cell substrate 10.
  • the inner surface of the seed layer 14 is connected to the TCO layer 13 on the cell substrate 10, if a second mask layer 30 is disposed on the outer surface of the first mask layer 20, it can also be expressed as a second mask layer 30 is disposed on the first surface of the cell substrate 10, and the second mask layer 30 is indirectly disposed on the outer surface of the seed layer 14.
  • the first surface of the cell substrate 10 can be a surface of the cell substrate 10, the outer surface of the first mask layer 20, or the outer surface of the second mask layer 30, and its specific meaning should be understood according to the context.
  • the side close to the inside of the cell substrate 10 is the inner side
  • the side away from the inside of the cell substrate 10 is the outer side.
  • the second side of the cell substrate 10 should also be understood in the same way.
  • the first surface of the substrate structure layer 11 refers to a surface of the substrate structure layer 11 or a surface of a material layer that is in direct or indirect contact with the surface.
  • a doped semiconductor layer 12 and a TCO layer 13 are sequentially arranged on a surface of the substrate structure layer 11 in a direction away from the substrate structure layer 11.
  • the doped semiconductor layer 12 is directly arranged on a surface of the substrate structure layer 11, and the TCO layer 13 is indirectly arranged on a surface of the substrate structure layer 11.
  • the first surface of the substrate structure layer 11 may be a surface of the substrate structure layer 11, an outer surface of the doped semiconductor layer 12, or an outer surface of the TCO layer 13.
  • the first surface of the substrate structure layer 11 and the first surface of the cell substrate 10 may be represented as the same surface.
  • the second surface of the substrate structure layer 11 should also be understood in the same way.

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Abstract

本发明公开了一种电池片制备方法，采用在电池片基体的边缘形成第二掩膜层，其中，电池片基体的边缘至少包括电池片基体的全部侧壁；避免电池片基体的全部侧壁处于裸露状态，在电镀制备金属栅线的过程中，避免对电池片基体的侧壁造成损伤，可以提升所制备的电池片的效率和良率。特别地，在制备双面电极电池片的过程中，第二掩膜层在电池片基体的侧壁上形成绝缘区，可以防止双面电极的局部互联导致的短路。

Description

一种电池片制备方法及电池片 技术领域
本发明涉及光伏电池片及半导体制造领域，具体涉及一种电池片制备方法及电池片。
背景技术
随着晶硅太阳能电池的结构向高开压的方向演化，各环节中的低温工艺得到了越来越多的应用。以硅基异质结电池为例，电池片基体上依次低温沉积的材料有本征非晶硅层、掺杂非晶硅层、透明导电氧化物层(TCO层)。通常非晶硅层的沉积方式为等离子体增强化学气相沉积(PECVD)，TCO层的沉积方式为物理气相沉积如磁控溅射或反应等离子体沉积。在物质从气相向固相转变的沉积中，电池片基体的厚度方向即侧壁也不可避免会发生材料沉积。由于具有双面电极的太阳能电池的受光面和背光面为电池的两个极性，因此在侧壁或某一面的边缘形成绝缘区来防止两个极性的局部互联短路就至关重要。
另一方面，采用电镀方式制备金属栅线的过程中，当含有金属离子的溶液接触电池片基体的侧壁时，在电镀过程中该侧壁也会沉积金属，因此在电池片基体的侧壁通常采用后刻蚀的方法对沉积的金属进行去除，从而减少侧壁短路现象的发生。然而后刻蚀往往对电池片基体的侧壁也有损伤，从而影响所制备的电池片的效率和良率。在电镀过程中，如果完全不对电池片基体的侧壁进行保护，电池片基体的侧壁上沉积的金属和电池片基体的表面上沉积的金属几乎一样厚，采用后刻蚀的方法对电池片基体的侧壁上沉积的金属进行去除，也会同时刻蚀电池片基体的表面上沉积的金属，使得后刻蚀的方法不可采用，除非后刻蚀的过程中，对电池片基体的表面上沉积的金属进行保护。
再一方面，TCO层的厚度增大，其导电性增强，但是透光性降低；TCO层13的厚度减小，其导电性减弱，但是透光性提升；现有的技术无法解决这一技术矛盾。
另外，电池片基体上的减反射层或TCO层，通常采用物理气相沉积或化学气相沉积的方法形成。对异质结电池来说，需要在受光面和背光面都沉积透明导电氧化物以形成TCO层，通常将电池片基体放置于具有开口的托盘上，托盘经过沉积受光面层的靶位段和沉积背光面层的靶位段。电池片基体与托盘接触的位置被遮挡，因此无法沉积透明导电氧化物以形成TCO层，进而暴露出电池片基体上的掺杂半导体层(例如非晶硅或微晶硅层)，该掺杂半导体层12的表面与外界的金属粒子直接接触，会降低所制备的电池片的效率。例如，在电镀铜的制程中，该掺杂半导体层的表面与种子层直接接触，这存在两个风险：(1)热处理(例如烘干)过程会导致种子层通过掺杂半导体层扩散到电池片基体内，造成电池片的电性能损失；(2)去除种子层的溶液中含有铜离子，在清洗时易附着到掺杂半导体层上，在后续热处理及电池片户外使用过程中扩散到电池片内，也会造成电池片的电性能损失。
发明内容
本发明的一个目的是提供一种电池片制备方法，至少解决背景技术中的问题之一。
本发明的实施例提供一种电池片制备方法，包括以下步骤：
S11、在电池片基体的第一面和/或第二面上形成第一掩膜层；S12、在第一掩膜层上形成掩膜开口；S13、在电池片基体的边缘形成第二掩膜层，所述电池片基体的边缘至少包括电池片基体的全部侧壁；S14、在掩膜开口中电镀形成金属栅线；S15、去除第一掩膜层和第二掩膜层。
在一些实施例中，所述第一掩膜材料为感光树脂，所述第二掩膜材料为热固化树脂。
在一些实施例中，将所述电池片基体的表面划分为A、B和C三个区域；所述电池片基体的第一面由A区域和B区域组成，所述B区域邻接所述第一面的边线；在所述第一面上，所述B区域为环形，所述B区域包围A区域；所述C区域为电池片基体的全部侧壁；
所述第一掩膜层覆盖第一面上的全部A区域，且至少覆盖第一面上的部分B区域；所述第二掩膜层覆盖全部C区域，且至少覆盖第一面上的部分B区域；所述第一掩膜层和第二掩膜层在第一面上的B区域部分重叠。
在一些实施例中，所述电池片基体的第二面由A区域和B区域组成，所述B区域邻接所述第二面的边线；在所述第二面上，所述B区域为环形，所述B区域包围A区域；所述第一掩膜层覆盖第二面上的全部A区域，且至少覆盖第二面上的部分B区域；所述第二掩膜层至少覆盖第二面上的部分B区域，所述第一掩膜层和第二掩膜层在第二面上的B区域部分重叠。
在一些实施例中，所述第二掩膜层沿上下方向的截面为“C”型。
在一些实施例中，所述第一掩膜层和第二掩膜层在B区域的重叠部分为环形。
在一些实施例中，所述第一掩膜层的边沿包括第一倾斜减薄层，所述第二掩膜层的边沿包括第二倾斜减薄层，所述第一倾斜减薄层和第二倾斜减薄层重叠构成第一掩膜层和第二掩膜层在B区域的重叠部分。
在一些实施例中，涂布的第二掩膜材料沿着第一面的边沿依次覆盖形成第一边沿条形区、第二边沿条形区、第三边沿条形区和第四边沿条形区，所述第一边沿条形区、第二边沿条形区、第三边沿条形区和第四边沿条形区的宽度依次为d3、d4、d5和d6，其中，d3、d4、d5和d6的取值范围均为0.2-5mm。
在一些实施例中，先对电池片基体的第一面上的左右两侧边沿涂布形成第一边沿条形区和第三边沿条形区，再对电池片基体的第一面上的上下两侧边沿涂布形成第二边沿条形区和第四边沿条形区；第一边沿条形区和第二边沿条形区相交，第一边沿条形区和第四边沿条形区相交，第三边沿条形区和第二边沿条形区相交，第三边沿条形区和第四边沿条形区相交。
在一些实施例中，沿逆时针或顺时针方向在电池片基体的第一面上的边沿上涂布第二掩膜材料，形成首尾相交的环形区域。
在一些实施例中，先将第二掩膜层溶解去除，再将第一掩膜层溶胀之后与电池片基体分离。
在一些实施例中，当金属栅线为易氧化金属，在金属栅线的表面上设置抗氧化层。
在一些实施例中，所述抗氧化层覆盖金属栅线的顶部和侧壁。
在一些实施例中，所述抗氧化层通过化学置换反应获得。
在一些实施例中，所述步骤S13设置在步骤S11之后，步骤S14之前；或者，所述步骤S13设置在步骤S11之前。
在一些实施例中，先在电池片基体的第一面和第二面上设置第一掩膜层，第一掩膜层不完全覆盖电池片基体的第一面并露出电池片基体的第一面的四边边沿，第一掩膜层不完全覆盖电池片基体的第二面并露出电池片基体的第二面的四边边沿；然后第二掩膜层覆盖露出的电池片基体的第一面和第二面的四边边沿，并且第二掩膜层覆盖到第一掩膜层之上，并且第二掩膜层不覆盖到掩膜图案上。
在一些实施例中，在电池片基体的同一侧边沿上，第一掩膜层的一边到电池片基体的第一边的距离为h1，掩膜图案的一边到电池片基体的第一边的距离为h2，第二掩膜层的一边到电池片基体的第一边的距离为h3；则满足h1大于0且h1<h3<h2。
在一些实施例中，电池片基体包括连续的第一边、第二边和第三边，第一边和第三边位于第二边的两侧，电池片基体的第二边的边长为k1；第一掩膜层沿电池片基体的第二边的中垂线对称分布，沿着电池片基体的第二边的延长方向，第一掩膜层的长度为k2；沿着电池片基体的第二边的延长方向，掩膜图案的长度为k3，掩膜图案沿电池片基体的第二边的中垂线对称分布在第一掩膜层上；位于第一边一侧的掩膜图案的一边到第一边的距离为h31,位于第三边一侧的掩膜图案的另一边到第三边的距离为h32，h31和h32均属于h3的取值范围内；则满足k1>k2且2h3+k2>k1且2h3+k3<k1。
在一些实施例中，k1的公差为±p；则满足k1-k2-p>0且(k1+p-k2)/2<h3<(k1-p-k3)/2。
在一些实施例中，所述金属栅线为具有宽度梯度的栅线。
在一些实施例中，第二掩膜材料在电池片基体上表面上覆盖的宽度大于第二掩膜材料在电池片基体下表面上覆盖的宽度。
在一些实施例中，当在电池片基体的第一面和第二面上形成第一掩膜层，电池片基体的第一面为受光面，电池片基体的第二面为背光面，使得受光面上的第一掩膜层的厚度大于背光面上的第一掩膜层的厚度。
在一些实施例中，电镀在受光面上的金属栅线的数量少于背光面上的金属栅线的数量。
在一些实施例中，电池片制备方法还包括以下步骤：
S31、在衬底结构层上设置TCO层，使得至少一个TCO层的厚度为M以形成TCO减薄层；
S32、在TCO减薄层上电镀金属栅线，根据一个TCO减薄层的厚度，控制该一个TCO减薄层上的金属栅线的宽度为N，且该一个TCO减薄层上相邻的金属栅线之间的距离为T；
其中，M的取值范围为40nm-80nm，N的取值范围为20-40um，T的取值范围为0.3-1.4mm。在一些实施例中，在衬底结构层的第一面和第二面上向远离衬底结构层的方向依次设置掺杂半导体层和TCO层，使得衬底结构层的第一面上TCO层的厚度为M以形成第一TCO减薄层，和/或，使得衬底结构层的第二面上TCO层的厚度为M以形成第二TCO减薄层。
在一些实施例中，步骤31和步骤32之间还包括步骤33，在掺杂半导体层的表面设置隔离层。
在一些实施例中，步骤31和步骤32之间还包括步骤S34，清洗去除附着在掺杂半导体层上的金属粒子。
在一些实施例中，采用步骤21替换步骤S11和S12，S21、在电池片基体的第一面和/或第二面上形成具有掩膜开口的第一掩膜层。
在一些实施例中，所述隔离层仅覆盖TCO层上的缺陷坑，或者，所述隔离层在TCO层上形成新的一层同时覆盖住缺陷坑。
本发明的另一个目的是提供一种电池片，采用上述的电池片制备方法制备获得。
本发明实施例中的一种电池片制备方法与现有技术相比，具有下列优点：
(1)本发明的实施例中在电池片基体的边缘形成第二掩膜层，电池片基体的边缘至少包括电池片基体的全部侧壁。避免电池片基体的全部侧壁处于裸露状态，在电镀制备金属栅线的过程中，避免对电池片基体的侧壁造成损伤，可以提升所制备的电池片的效率和良率。特别地，在制备双面电极电池片的过程中，第二掩膜层在电池片基体的侧壁上形成绝缘区，可以防止双面电极的局部互联导致的短路。
(2)本发明的实施例中通过设置隔离层，可以避免种子层通过掺杂半导体层扩散到电池片基体内，造成电池片的电性能损失的问题，提升了所制备的电池片的效率。
(3)本发明的实施例中在金属栅线上采用化学置换反应获得抗氧化层，可以直接在金属栅线的顶部和侧壁上均形成抗氧化层，可以更好地避免后续工艺及使用过程中损伤金属栅线。
(4)通过打印和显影的方法形成宽度为N的细小掩膜开口，通过电镀在掩膜开口中形成宽度为N的金属栅线，使得同一TCO层上相邻的金属栅线之间的间距能够减小，即同一TCO层上金属栅线的数量会增加，且不会因此扩大同一TCO层全部金属栅线的遮光面积；因为相邻的金属栅线之间的间距减小，同一TCO层全部金属栅线的导电性能提升，使得减小TCO层的厚度成为可能。因此，在制备电池片时，使得TCO层的厚度为M以形成TCO减薄层，再根据TCO减薄层的厚度，在TCO减薄层上电镀形成金属栅线，控制TCO减薄层上的金属栅线的宽度为N，且TCO减薄层上的相邻的金属栅线之间的间距为T。因而，TCO层的厚度得以减小，节约了电池片的制备成本，同时保持或者提升了所制备的电池片的效率。
附图说明
附图1为电池片基体表面上的区域划分示意图；
附图2为包含F区域的电池片基体表面上的区域划分示意图；
附图3为第一掩膜层和第二掩膜层重叠部分的结构示意图；
附图4为第二掩膜层的宽度尺寸示意图；
附图5为第一种第二掩膜材料的涂布过程示意图；
附图6为第二种第二掩膜材料的涂布过程示意图；
附图7为电池片基体覆盖第一掩膜层和第二掩膜层后的剖视示意图；
附图8为电池片基体溶解第二掩膜层后的剖视示意图；
附图9a-9g为第一种具体的实施方式中双面电极电池片在制备过程中的剖视示意图；
附图10a-10g为第一种具体的实施方式中双面电极电池片在制备过程中的剖视示意图；
附图11a-11g为第二种具体的实施方式中单面电极电池片在制备过程中的剖视示意图；
附图12a-12g为第二种具体的实施方式中单面电极电池片在制备过程中的剖视示意图；
附图13a、13d和13e分别为三个优选实施例中双面电极电池片基体设置第一掩膜层和第一掩膜层后的剖视示意图；
附图13b和13c分别为两个优选实施例中双面电极电池片基体设置第一掩膜层和第一掩膜层后的尺寸示意图；
附图14a-14b分别为两个优选实施例中衬底结构层的结构示意图；
附图15a-15b分别为两个优选实施例中涂布第二掩膜材料的流向示意图；
附图16a-16b分别为两个优选实施例中涂布引导机构的结构示意图；
附图17为第一种具体的实施方式中设置隔离层的过程示意图；
附图18为第二种具体的实施方式中设置隔离层的过程示意图；
10-电池片基体，11-衬底结构层，111-晶硅衬底层，112-本征半导体层，113-薄膜隧穿层，12-掺杂半导体层，13-TCO层，131-缺陷坑，132-隔离层，14-种子层，15-导电层，20-第一掩膜层，21-第一倾斜减薄层，22-掩膜开口，30-第二掩膜层，31-第二倾斜减薄层，40-金属栅线，210-“U”型槽，220-进料管，230-阻挡件，240-出料管。
具体实施方式
下面结合附图对本发明的较佳实施例进行详细阐述，以使本发明的优点和特征能更易于被本领域的技术人员理解。在此需要说明的是，对于这些实施方式的说明用于帮助理解本发明，但并不构成对本发明的限定。
随着晶硅太阳能电池的结构向高开压的方向演化，各环节中的低温工艺得到了越来越多的应用。以硅基异质结电池为例，电池片基体上依次低温沉积的材料有本征非晶硅层、掺杂非晶硅层、透明导电氧化物层(TCO层)。通常非晶硅层的沉积方式为等离子体增强化学气相沉积(PECVD)，TCO层的沉积方式为物理气相沉积如磁控溅射或反应等离子体沉积。在物质从气相向固相转变的沉积中，电池片基体的厚度方向即侧壁也不可避免会发生材料沉积。由于双面电极电池片的受光面和背光面为电池片的两个极性，因此在侧壁或某一面的边缘形成绝缘区来防止两个极性的局部互联短路就至关重要。
另一方面，采用电镀方式制备金属栅线的过程中，当含有金属离子的溶液接触电池片基体的侧壁时，在电镀过程中该侧壁也会沉积金属，因此在电池片基体的侧壁通常采用后刻蚀的方法对沉积的金属进行去除，从而减少侧壁短路现象的发生。然而后刻蚀往往对电池片基体的侧壁也有损伤，从而影响所制备的电池片的效率和良率。在电镀过程中，如果完全不对电池片基体的侧壁进行保护，电池片基体的侧壁上沉积的金属和电池片基体的表面上沉积的金属几乎一样厚，采用后刻蚀的方法对电池片基体的侧壁上沉积的金属进行去除，也会同时刻蚀电池片基体的表面上沉积的金属，使得后刻蚀的方法不可采用，除非后刻蚀的过程中，对电池片基体的表面上沉积的金属进行保护。基于此，本申请的实施例提出了一种电池片制备方法，改良电池片的生产过程，避免在电池片基体的侧壁上沉积金属。
请参考图1，将电池片基体10的表面划分为A、B和C三个区域，电池片基体10的第一面由A区域和B区域组成，B区域邻接电池片基体10的第一面的边线，B区域为环形，这里的环形包括回形，B区域包围A区域，C区域为电池片基体10的全部侧壁；现有技术中，一般会在电池片基体10的第一面上完全涂布生成第一掩膜层20，然后在第一掩膜材料的辅助下制备金属栅线40，然而电池片基体10的全部侧壁处于裸露状态，在电镀制备金属栅线40的过程中，会对电池片基体10的侧壁有所损伤，从而影响所制备的电池片的效率和良率。
实施例1
一种电池片制备方法，包括以下步骤：
S11、在电池片基体10的第一面和/或第二面上形成第一掩膜层20。
第一面和第二面为电池片基体10上相背的两面，电池片基体10自内向外至少依次包括衬底结构层11、掺杂半导体层12和TCO层13(其中，TCO为透明导电氧化物，全称为transparent conductive oxide)，电池片基体10的第一面和/或第二面的最外层可以为TCO层13，第一掩膜层20形成于TCO层13上，TCO层13包括氧化铟锡(ITO)，掺钨氧化铟(IWO)，掺铝氧化锌(ZnOzAl)，掺镓氧化锌(ZnOzGA)和Zn-in-Sn-O(ZITO)任意一种或两种。在优选的实施例中，电池片基体10的第一面的最外层为种子层14，电池片基体10的第二面的最外层为种子层14或者导电层15；即在TCO层13之外设置种子层14或者导电层15，第一掩膜层20形成于种子层14或者导电层15上。当电池片基体10的第一面和第二面的最外层均 为种子层14，此时当电池片基体10为双面电极的基体10，第一掩膜层20形成于第一面和第二面的最外层的种子层14上；当电池片基体10的第一面的最外层为种子层14，电池片基体10的第二面的最外层为导电层15，此时当电池片基体10为单面电极电池片的基体，第一掩膜层20分别形成于第一面的最外层种子层14上和第二面的最外层导电层15上。以上可知，电池片基体10的最外层包括TCO层13、种子层14和导电层15中的至少一种。
优选地，种子层14可以通过电镀方式被电镀在电池片基体10的第一面和/或第二面上。种子层14可以为铝、镍、钯至少一种材料构成的活化层或者TiW材料层或者TiN材料层。TiW材料层或者TiN材料层多以磁控溅射方式沉积获得。当电池片基体10的第一面和第二面上均设置有种子层14，此时电池片基体10为双面电极电池片的基体，例如异质结电池的基体。以图1为例，种子层14完全覆盖A区域和B区域。当电池片基体10水平放置，第一面为电池片基体10的上表面或下表面，对应地第二面为电池片基体10的下表面或上表面。种子层14包括单个金属层、单个金属合金层或者由至少两个不同单层的多层结构。例如，种子层14的材料可以为铜、锡、钴、镍、银、锡-铅合金、锡-银合金、铜-镍合金、铜-铬合金、铜-钌合金、铜-铑合金、铜-银合金、铜-铱合金、铜-钯合金、铜-铂合金、铜-金合金和铜-稀土合金、铜-镍-银合金和铜-镍-稀土金属合金。种子层14的材料优选为铜、铜-镍合金、铜-锡合金、铜-钌合金以及铜-铑合金。
优选地，第一掩膜层20可以通过涂布或者沉积的方式获得，当采用涂布方式在种子层14上制备第一掩膜层20，需要进行烘干；根据第一掩膜层20涂布的厚度以及材料，其烘干时间可以在5-15分钟的范围内选择设置。第一掩膜层20的材料为感光树脂，感光树脂的材料包括环氧树脂、丙烯酸树脂、酚醛树脂、酚醛清漆树脂、三聚氰胺树脂或聚氨酯树脂一种或者其混合材料等。感光树脂还可以采用苯并环丁烯、聚对亚苯基二甲基、flare、聚酰亚胺等有机材料。其中正型感光材料，可以是包括酚醛清漆树脂和作为感光剂的萘并醌二叠氮化合物的感光材料。其中负型感光材料，可以是包括基础树脂、二苯基硅烷二醇和氧产生剂等的感光材料。
具体地，采用涂布机构形成第一掩膜层20，涂布机构包括涂布平台、涂布模具和刮刀，涂布模具上开设有与电池片基体10的尺寸适配的涂布孔，步骤S11具体包括：
S111、将电池片基体10放置在涂布平台上，使得电池片基体10的第一面上朝上；
S112、将涂布模具(可以为网版)放置于电池片基体10的第一面上，并使得涂布模具的涂布孔与电池片基体10对正；
S113、向涂布孔内的电池片基体10上的第一面上涂布第一掩膜材料；
S114、采用刮刀对已涂布的第一掩膜材料进行平整；
S115、将已平整的第一掩膜材料烘干后形成第一掩膜层20；
S116、重复步骤S111-S115，在电池片基体10的第二面上形成第一掩膜层20。
为了避免涂布过程中液体形态的第一掩膜材料落到涂布平台上，涂布孔的尺寸略小于电池片基体10的尺寸，即涂布孔的边沿保持在电池片基体10的表面内，涂布孔的边沿不超过电池片基体10的边沿。例如，电池片基体10的尺寸为166mm×166mm×130um，涂布孔的尺寸为160mm×160mm×140um。
S12、在第一掩膜层20上形成掩膜开口22。
优选地，可以通过光照使得第一掩膜层20上部分区域发生化学反应，去除第一掩膜层20上发生化学反应的部分区域或者去除第一掩膜层20上未发生化学反应的部分区域，在第一掩膜层20上形成掩膜开口22。通过光照使得第一掩膜层20上部分区域发生化学反应，称为打印；去除第一掩膜层20上发生化学反应的部分区域或者第一掩膜层20上未发生化学反应的部分区域，称为显影；打印和显影的目的是为了获得掩膜开口22。本领域技术人员应该知道的是，掩膜开口22贯通第一掩膜层20，掩膜开口22的底部为TCO层或者种子层14，形成掩膜开口22的目的是为了暴露TCO层13或者种子层14。通过打印和显影工艺可以获得宽度更窄的掩膜开口22，后续可以电镀获得宽度更窄的金属栅线40，进而提升所制备的电池片的效率。
S13、在电池片基体10的边缘形成第二掩膜层30，所述电池片基体10的边缘至少包括电池片基体10的全部侧壁。第二掩膜层30的材料为热固化树脂。热固化树脂可以为硅树脂、聚酰胺树脂、聚烯烃树脂、氰酸盐树脂、酚醛树脂、萘树脂或芴树脂。电池片基体10为薄片状结构，电池片基体10的形状可以看作 矩形或者具有至少一个倒角的矩形；当电池片基体10为具有四个倒圆角的矩形，则电池片基体10的全部侧壁包括四个平面侧壁和四个弧面侧壁；当电池片基体10为具有四个倒直角的矩形，则电池片基体10的全部侧壁包括八个平面侧壁；当电池片基体10为具有两个倒圆角的矩形，则电池片基体10的全部侧壁包括四个平面侧壁和两个弧面侧壁；当电池片基体10为矩形，则电池片基体10的全部侧壁包括四个平面侧壁。在本实施例及后续实施例中，可能会将电池片基体10的形状示意为矩形或者正方形，这只是为了方便描述本申请的原理，实际生产中电池片基体10的形状更多地表现为具有四个倒角的“矩形”。
在电池片基体10的边缘形成第二掩膜层30，其目的是对电池片基体10进行边缘保护。边缘保护是指将电池片基体10的边缘覆盖住，即在电池片基体10的边缘形成第二掩膜层30，避免后续的电镀工艺中在电池片基体10的侧壁上沉积金属。如果仅仅是在电池片基体10的全部侧壁涂布生成第二掩膜层30，第二掩膜层30容易脱落，并且第二掩膜层30和第一掩膜层20交接处容易出现缝隙，通过该缝隙，电池片基体10的最外层会被腐蚀；因此，可以在电池片基体10的全部侧壁及上下表面的边沿生成连续的第二掩膜层30，第二掩膜层30类似一个上下开口的壳体，能够将电池片基体10包裹在其中而露出第一面和第二面，通俗地说第二掩膜层30类似于底部开口的鞋套，能够将电池片基体10包裹在其中而露出第一面和第二面，降低了第二掩膜层30脱落的风险。进一步地，如图7所示，第二掩膜层30沿上下方向(或者说电池片基体10的厚度方向)的截面为“C”型，该“C”型结构能够套住电池片基体10，降低了第二掩膜层30脱落的风险。另外，在第二掩膜层30和第一掩膜层20交接处同时涂布了第二掩膜层30和第一掩膜层20，避免了在第二掩膜层30和第一掩膜层20交接处容易出现缝隙的问题。第二掩膜层30可以通过涂布获得，涂布后也需要烘干；根据第二掩膜层30涂布的厚度以及材料，其烘干时间可以在1-5分钟的范围内选择设置。
以图1为例，第一掩膜层20覆盖电池片基体10的第一面上的全部A区域，同时至少覆盖池片基体10的第一面上的部分B区域；第二掩膜层30覆盖全部C区域，同时至少覆盖池片基体10的第一面上的部分B区域；并且第一掩膜层20和第二掩膜层30在池片基体10的第一面上的B区域存在重叠部分，以避免第二掩膜层30和第一掩膜层20的交接处出现缝隙，导致电池片基体10的最外层被腐蚀的问题。第二掩膜层30覆盖的区域为连续区域，在电池片基体10的第一面上第一掩膜层20覆盖的区域为连续区域。前述的电池片基体10的边缘至少包括C区域，可以包括全部或者部分B区域。优选地，第一掩膜层20和第二掩膜层30在B区域的重叠部分构成环形，这里的环形包括回形，例如图2中所示的F区域。F区域的一侧边线与其所在的电池片基体10的表面的边线重合，F区域的另一侧边线与A区域的边线重合或者F区域的另一侧边线位于B区域内。再参考图3，图3中的第(1)幅图，先将第二掩膜层30涂布在电池片基体10第一面上，第二掩膜层30的边沿厚度渐薄并向靠近电池片基体10的表面倾斜，形成第二倾斜减薄层31，然后将第一掩膜层20涂布在电池片基体10第一面上，第一掩膜层20和第二掩膜层30部分重叠，第一掩膜层20和第二倾斜减薄层31重叠的部分形成第一倾斜减薄层21，第一倾斜减薄层21为第一掩膜层20的厚度减薄层并向远离电池片基体10的表面倾斜。图3中的第(1)幅图中，第二倾斜减薄层31为斜面结构，第一倾斜减薄层21为与第二倾斜减薄层31配合的斜面结构。图3中的第(2)幅图中，第二倾斜减薄层31为弧面结构，第一倾斜减薄层21为与第二倾斜减薄层31配合的弧面结构。图3中的第(3)幅图，先将第一掩膜层20涂布在电池片基体10第一面上，第一掩膜层20的边沿厚度渐薄并向靠近电池片基体10的表面倾斜，形成第一倾斜减薄层21，然后将第二掩膜层30涂布在电池片基体10第一面上，第二掩膜层30和第一掩膜层20部分重叠，第二掩膜层30和第一倾斜减薄层21重叠的部分形成第二倾斜减薄层31，第二倾斜减薄层31为第二掩膜层30的厚度减薄层并向远离电池片基体10的表面倾斜。图3中的第(3)幅图中，第一倾斜减薄层21为斜面结构，第二倾斜减薄层31为与第一倾斜减薄层21配合的斜面结构；图3中的第(4)幅图中，第一倾斜减薄层21为弧面结构，第二倾斜减薄层31为与第一倾斜减薄层21配合的弧面结构。第一倾斜减薄层21和第二倾斜减薄层31重叠构成第一掩膜层20和第二掩膜层30在B区域的重叠部分，第一倾斜减薄层21为斜面结构或弧面结构，对应地，第二倾斜减薄层31也为斜面结构或弧面结构，通过对应地两个斜面结构或对应地两个弧面结构的接触配合，扩大了接触面积，使得第一掩膜层20和第二掩膜层30能够牢固结合在一起，降低了第一掩膜层20和第二掩膜层30结合处开裂的风险。
在其他实施例中，当电池片为双面电极电池片，电池片基体10的第二面由A区域和B区域组成，B区域邻接第二面的边线；在第二面上，B区域为环形，B区域包围A区域；第一掩膜层20覆盖第二面上 的全部A区域，且至少覆盖第二面上的部分B区域；第二掩膜层30至少覆盖第二面上的部分B区域，第一掩膜层20和第二掩膜层30在第二面上的B区域部分重叠。电池片基体10的第二面也可以适用上述电池片基体10的第一面的技术方案。
示例地，如图4所示，在电池片基体10的第一面上(电镀金属栅线40的一面)，涂布的第一掩膜材料覆盖形成区域E，涂布的第二掩膜材料覆盖形成区域D，区域E和区域D覆盖整个电池片基体10的第一面，电池片基体10为正方形，电池片基体10的边长为d0，d0的具体数值可以为156.75mm、158.75mm、166mm、182mm或者210mm，涂布的第二掩膜材料沿着第一面的边沿依次覆盖形成第一边沿条形区、第二边沿条形区、第三边沿条形区和第四边沿条形区，第一边沿条形区、第二边沿条形区、第三边沿条形区和第四边沿条形区的宽度依次为d3、d4、d5和d6，d3、d4、d5和d6的取值范围为0.2-5mm，优选为0.3-1mm，使得涂布的第二掩膜材料沿着第一面的边沿覆盖形成的区域的宽度不至于太小，导致第二掩膜材料容易脱落，同时使得涂布的第二掩膜材料沿着第一面的边沿覆盖形成的区域的宽度不至于太大，导致后续第二掩膜材料不易被去除；优选地，d3、d4、d5和d6中的最小值不小于0.2mm，d3、d4、d5和d6中的最大值不大于5mm，使得涂布的第二掩膜材料沿着第一面的边沿覆盖形成的区域的宽度不至于太小，导致第二掩膜材料容易脱落，同时使得涂布的第二掩膜材料沿着第一面的边沿覆盖形成的区域的宽度不至于太大，导致后续第二掩膜材料不易被去除；优选地，d3、d4、d5和d6的数值大小与d0的数值大小相关，d3、d4、d5和d6分别与d0的比值范围均为0.1％-3％，使得涂布的第二掩膜材料沿着第一面的边沿覆盖形成的区域的宽度不至于太小，导致第二掩膜材料容易脱落，同时使得涂布的第二掩膜材料沿着第一面的边沿覆盖形成的区域的宽度不至于太大，导致后续第二掩膜材料不易被去除。本实施例中，区域D可以为图2中区域F，区域E可以为单层的第一掩膜材料覆盖区。当电池片基体10的第二面也为电镀金属栅线40的一面，也可以适用上述技术方案，此时电池片为双面电极电池片。
需要说明的是，第一边沿条形区、第二边沿条形区、第三边沿条形区和第四边沿条形区可能是矩形区域，也可能是具有倒圆角或者倒直角的矩形。
示例地，如图5所示，先对电池片基体10的第一面上的左右两侧边沿涂布形成第一边沿条形区D1和第三边沿条形区D3，再对电池片基体10的第一面上的上下两侧边沿涂布形成第二边沿条形区D2和第四边沿条形区D4；第一边沿条形区D1和第二边沿条形区D2相交，相交区域为D12，第一边沿条形区D1和第四边沿条形区D4相交，相交区域为D41，第三边沿条形区D3和第二边沿条形区D2相交，相交区域为D23，第三边沿条形区D3和第四边沿条形区D4相交，相交区域为D34，保证了第二掩膜层30在生成过程中，自身的接缝能够完整闭合形成环形，在后续的电镀过程中，能够避免从接缝处渗透金属离子到电池片基体10的最外层以及电池片基体10的侧壁上，也能够避免从接缝处腐蚀电池片基体10的最外层。当电池片基体10的第二面也为电镀金属栅线40的一面，也可以适用上述技术方案，此时电池片为双面电极电池片。
示例地，如图6所示，沿逆时针方向在电池片基体10的第一面上的边沿上涂布第二掩膜材料，形成区域D，区域D为环形，区域D仅有一个相交区域，相交区域为D41。在其他实施例中，也可以沿顺时针方向在电池片基体10的第一面上的边沿上涂布第二掩膜材料，形成区域D。区域D仅有一个相交区域，相交区域面积小，方便后续去除第二掩膜材料，区域D为一次连续成形，效率更高。当电池片基体10的第二面也为电镀金属栅线40的一面，也可以适用上述技术方案，此时电池片为双面电极电池片。
在其他实施例中，可以先沿逆时针(或者顺时针)方向在电池片基体10的第一面上的三个边沿上涂布第二掩膜材料，再在电池片基体10的第一面上的第四个边沿上涂布第二掩膜材料，形成闭合的环形区域D。
S14、在掩膜开口22中电镀形成金属栅线40。
优选地，金属栅线40的材料可以为铜、锡、银和锌中的任意一种及其合金，金属栅线40也可以为铜、锡、银和锌中的任意两种以上构成的叠层。优选地，金属栅线40为具有宽度梯度的栅线，即该金属栅线40被划分为由上至下依次分布的多层，该金属栅线40的所有层中包括位于最上方的顶层，在该顶层的下方存在至少一个宽度扩大层，该宽度扩大层的宽度大于其上方任一层的宽度。
S15、去除第一掩膜层20和第二掩膜层30。
优选地，当电池片基体10上设置有种子层14，步骤S15包括，先去除第一掩膜层20和第二掩膜层 30，再刻蚀去除电池片基体10上的种子层14；具体地，需要刻蚀掉处于金属栅线40间隙中的种子层14，保留金属栅线40根部连接TCO层13的种子层14。
具体地，采用碱性溶液浸泡或者喷淋，例如NaOH溶液，可以去除第一掩膜层20和第二掩膜层30；因为第一掩膜层20的体积远大于第二掩膜层30的体积，采用碱性溶液浸泡或者喷淋将第二掩膜层30溶解，而采用碱性溶液浸泡或者喷淋使得第一掩膜层20发泡溶胀后脱离电池片基体10，不用完成溶解第一掩膜层20，这样可以提升去除第一掩膜层20的效率，降低碱性溶液的用量。脱离电池片基体10的第一掩膜层20经过过滤去除。当电池片基体10包括种子层14，将去除第一掩膜层20和第二掩膜层30的电池片，经过清洗(例如水洗)并烘干之后，再采用酸溶液浸泡以刻蚀去除种子层14，这里的酸溶液可以为硫酸溶液。如图8所示，第二掩膜层30先被溶解之后，使得第一掩膜层20和种子层14之间出现溶解间隙X，通过溶解间隙X，使得第一掩膜层20与种子层14接触的边沿能够直接接触到碱性溶液，可以加速第一掩膜层20发泡溶胀的过程，使得第一掩膜层20快速脱离电池片基体10。
优选地，当金属栅线40为易氧化金属，在金属栅线40的表面上设置抗氧化层；抗氧化层可以为锡或者银等不易氧化的金属及其合金或有机抗氧化层。抗氧化层可以通过电镀(例如电镀锡)获得，或者，采用化学置换反应形成包裹整个金属栅线40(例如铜栅线)的锡保护层或有机抗氧化层。更优先地，该步骤设置在步骤S14之后，步骤S15之前，避免步骤S15氧化损伤金属栅线40；在此种情况中，抗氧化层在去除第一掩膜层20之前形成，若采用电镀获得抗氧化层，因为第一掩膜层20的阻隔，抗氧化层只能在金属栅线40的顶部形成保护层，无法在金属栅线40的侧壁上形成保护层，当去除第一掩膜层20后，金属栅线40的侧壁仍然是裸露的，容易被氧化和腐蚀，因此可以进一步地在金属栅线40的侧壁上形成抗氧化层；然后，采用化学置换反应获得抗氧化层，可以直接在金属栅线40的顶部和侧壁上均形成抗氧化层，可以更好地避免步骤S15损伤金属栅线40，尤其是避免金属栅线40侧壁在步骤S15中受到损伤。
在第一种具体的实施方式中，步骤S13的边缘保护过程可以设置在步骤S11之后，步骤S14之前。即先在电池片基体10的最外层上涂布第一掩膜材料，烘干后形成第一掩膜层20；再对电池片基体10的边缘及侧壁涂布第二掩膜材料，烘干后形成第二掩膜层30。本实施方式中，第一掩膜层20经历了两次烘干过程，使得第一掩膜层20深度附着在电池片基体10的最外层上，导致第一掩膜层20不容易被去除。但是，先在电池片基体10的最外层上涂布第一掩膜材料，能够保护电池片基体10的最外层，避免电池片基体10的最外层在烘干过程中被氧化，进而提升本方法所制备的电池片的效率。
图9a-9g为第一种具体的实施方式中双面电极电池片在制备过程中的剖视示意图。如图9a所示，双面电极的电池片基体10包括衬底结构层11，衬底结构层11的第一面和第二面上向远离衬底结构层11的方向依次设置有掺杂半导体层12、TCO层13和种子层14。衬底结构层11的第一面和第二面为相背的两面。优选地，衬底结构层11包括N型半导体层(N-Si)，衬底结构层11的第一面和第二面上的掺杂半导体层12分别为P型微晶硅层(uc-Si(p))和N型微晶硅层(uc-Si(n))，TCO层13为ITO层，种子层14为PVD Cu层，PVD Cu是指物理气相沉积铜层。在衬底结构层11的第一面和第二面上的种子层14上分别涂布生成第一掩膜层20，获得如图9b所示的结构；优选地，第一掩膜层20的厚度为四周薄中部厚。对衬底结构层11的第一面和第二面上的第一掩膜层20进行打印和显影以在其上生成掩膜开口22，获得如图9c所示的结构，掩膜开口22全部形成于第一掩膜层20的中部上，第一掩膜层20的四边边沿上不设置掩膜开口22，避免后续第二掩膜层30覆盖掉第一掩膜层20的四边边沿上的掩膜开口22；优选地，第一掩膜层20的厚度为四周薄中部厚，掩膜开口22设置于第一掩膜层20的中部凸起上，第一掩膜层20四边边沿的减薄部与第二掩膜层30配合，第一掩膜层20四边边沿的减薄部能够为涂布的第二掩膜材料进行引流和导向，便于第二掩膜层30的生成。在电池片基体10的全部侧壁上以及衬底结构层11两面上的第一掩膜层20的四边边沿上涂布生成第二掩膜层30,获得如图9d所示的结构,第二掩膜层30在衬底结构层11两面上的第一掩膜层20上分别形成一个回形结构，沿厚度方向，第二掩膜层30的截面构成“C”形。在衬底结构层11的第一面和第二面上的掩膜开口22中电镀生成金属栅线40，获得如图9e所示的结构，金属栅线40优选为铜栅线并在其上电镀金属锡层，金属锡层覆盖铜栅线的顶部。去除第一掩膜层20和第二掩膜层30，获得如图9f所示的结构；刻蚀去除衬底结构层11的第一面和第二面上的的种子层14，露出金属栅线40，形成电池片，获得如图9g所示的结构。
图10a-10g为第一种具体的实施方式中单面电极电池片在制备过程中的剖视示意图。 如图10a所示，单面电极的电池片基体10包括衬底结构层11，衬底结构层11的第一面和第二面上向远离衬底结构层11的方向依次设置有掺杂半导体层12和TCO层13，位于第一面上的TCO层13上设置有种子层14，位于第二面上的TCO层13上设置有导电层15，衬底结构层11的第一面和第二面为相背的两面。优选地，衬底结构层11包括N型半导体层(N-Si)，衬底结构层11的第一面和第二面上的掺杂半导体层12分别为P型微晶硅层(uc-Si(p))和N型微晶硅层(uc-Si(n))，TCO层13为ITO层，种子层14为PVD Cu层。在种子层14和导电层15上分别涂布生成第一掩膜层20，获得如图10b所示的结构，优选地，第一掩膜层20的厚度为四周薄中部厚。对种子层14上的第一掩膜层20进行打印和显影以在其上生成掩膜开口22，获得如图10c所示的结构，掩膜开口22全部形成于第一掩膜层20的中部上，第一掩膜层20的四边边沿上不设置掩膜开口22，避免后续第二掩膜层30覆盖掉第一掩膜层20的四边边沿上的掩膜开口22；优选地，第一掩膜层20的厚度为四周薄中部厚，掩膜开口22设置于第一掩膜层20的中部凸起上，第一掩膜层20四边边沿的减薄部与第二掩膜层30配合，第一掩膜层20四边边沿的减薄部能够为涂布的第二掩膜材料进行引流和导向，便于第二掩膜层30的生成。在电池片基体10的全部侧壁上以及衬底结构层11两面上的第一掩膜层20的四边边沿上涂布生成第二掩膜层30,获得如图10d所示的结构，第二掩膜层30在衬底结构层11两面上的第一掩膜层20上分别形成一个回形结构，沿厚度方向，第二掩膜层30的截面构成“C”形。在衬底结构层11的第一面上的掩膜开口22中电镀生成金属栅线40，获得如图10e所示的结构，金属栅线40优选为铜栅线并在其上电镀金属锡层，金属锡层覆盖铜栅线的顶部。去除第一掩膜层20和第二掩膜层30，获得如图10f所示的结构；刻蚀去除第一面上的种子层14，露出金属栅线40，形成电池片，获得如图10g所示的结构。
在第二种具体的实施方式中，步骤S13的边缘保护过程可以设置在步骤S11之前。即先在电池片基体10的边缘及侧壁涂布第二掩膜材料，烘干后形成第二掩膜层30；再在电池片基体10的最外层上涂布第一掩膜材料，烘干后形成第一掩膜层20。本实施方式中，在烘干第二掩膜材料的过程中，电池片基体10的最外层处于裸露状态，容易被氧化，导致所制备的电池片的效率降低；因此，烘干第二掩膜材料的过程可以在惰性气体保护的环境下进行，避免裸露的电池片基体10的最外层被氧化。与第一种具体的实施方式相比，电池片基体10的最外层上涂布的第一掩膜层20只经过了一次烘干，使得第一掩膜层20容易被去除，能够提升电池片的生产制备效率。
图11a-11g为第二种具体的实施方式中双面电极电池片在制备过程中的剖视示意图。如图11a所示，双面电极的电池片基体10包括衬底结构层11，衬底结构层11的第一面和第二面上向远离衬底结构层11的方向依次设置有掺杂半导体层12、TCO层13和种子层14。衬底结构层11的第一面和第二面为相背的两面。优选地，衬底结构层11包括N型半导体层(N-Si)，衬底结构层11的第一面和第二面上的掺杂半导体层12分别为P型微晶硅层(uc-Si(p))和N型微晶硅层(uc-Si(n))，TCO层13为ITO层，种子层14为PVD Cu层。在电池片基体10的全部侧壁上以及衬底结构层11两面的种子层14的四边边沿上涂布生成第二掩膜层30，获得如图11b所示的结构，第二掩膜层30在衬底结构层11两面的种子层14上分别构成一个回形结构，沿厚度方向，第二掩膜层30的截面构成“C”形。在衬底结构层11两面上分别涂布生成第一掩膜层20，第一掩膜层20的中间部分填充在回形结构的中部开口中并且覆盖在种子层14上，第一掩膜层20的外围部分覆盖在回形结构的四边边沿上，获得如图11c所示的结构。对衬底结构层11的第一面和第二面上的第一掩膜层20进行打印和显影以在其上生成掩膜开口22，获得如图11d所示的结构，掩膜开口22全部形成于覆盖在种子层14上的第一掩膜层20上，掩膜开口22不设置在第一掩膜层20和第二掩膜层30的重叠部分上，避免破坏第一掩膜层20和第二掩膜层30之间的结合力，同时降低因为多层材料导致掩膜开口22变形的风险。在衬底结构层11两面上的掩膜开口22中电镀生成金属栅线40，获得如图11e所示的结构，金属栅线40优选为铜栅线并在其上电镀金属锡层，金属锡层覆盖铜栅线的顶部。去除第一掩膜层20和第二掩膜层30，获得如图11f所示的结构；刻蚀去除衬底结构层11的第一面和第二面上的的种子层14，露出金属栅线40，形成电池片，获得如图11g所示的结构。
图12a-12g为第二种具体的实施方式中单面电极电池片在制备过程中的剖视示意图。如图12a所示，单面电极的电池片基体10包括衬底结构层11，衬底结构层11的第一面和第二面上向远离衬底结构层11的方向依次设置有掺杂半导体层12和TCO层13，位于第一面上的TCO层13上设置有种子层14，位于第二面上的TCO层13上设置有导电层15，衬底结构层11的第一面和第二面为相背的两面。 优选地，衬底结构层11包括N型半导体层(N-Si)，衬底结构层11的第一面和第二面上的掺杂半导体层12分别为P型微晶硅层(uc-Si(p))和N型微晶硅层(uc-Si(n))，TCO层13为ITO层，种子层14为PVD Cu层。在电池片基体10的全部侧壁上以及种子层14和导电层15的四边边沿上涂布生成第二掩膜层30，获得如图12b所示的结构，第二掩膜层30在种子层14和导电层15上分别构成一个回形结构，沿厚度方向，第二掩膜层30的截面构成“C”形。在衬底结构层11两面上分别涂布生成第一掩膜层20，在衬底结构层11的第一面上，第一掩膜层20的中间部分填充在回形结构的中部开口中并且覆盖在种子层14上，第一掩膜层20的外围部分覆盖在回形结构的四边边沿上，在衬底结构层11的第二面上，第一掩膜层20的中间部分填充在回形结构的中部开口中并且覆盖在导电层15上，第一掩膜层20的外围部分覆盖在回形结构的四边边沿上，获得如图12c所示的结构。对衬底结构层11的第一面上的第一掩膜层20进行打印和显影以在其上生成掩膜开口22，获得如图12d所示的结构，掩膜开口22全部形成于覆盖在种子层14上的第一掩膜层20上，掩膜开口22不设置在第一掩膜层20和第二掩膜层30的重叠部分上，避免破坏第一掩膜层20和第二掩膜层30之间的结合力，同时降低因为多层材料导致掩膜开口22变形的风险。在掩膜开口22中电镀生成金属栅线40，获得如图12e所示的结构，金属栅线40优选为铜栅线并在其上电镀金属锡层，金属锡层覆盖铜栅线的顶部。去除第一掩膜层20和第二掩膜层30，获得如图12f所示的结构；刻蚀去除种子层14，露出金属栅线40，形成电池片，获得如图12g所示的结构。
需要说明的是，在上述的第一种具体的实施方式和第二种具体的实施方式中，第一掩膜层20和第二掩膜层30均可以为厚度均匀的材料层。
在优选的实施例中，如图13a所示，先在电池片基体10的第一面和第二面上设置第一掩膜层20，第一掩膜层20不完全覆盖电池片基体10的第一面并露出电池片基体10的第一面的四边边沿，第一掩膜层20不完全覆盖电池片基体10的第二面并露出电池片基体10的第二面的四边边沿，避免形成第一掩膜层20时涂布的第一掩膜材料落到涂布平台上污染涂布平台；然后第二掩膜层30覆盖露出的电池片基体10的第一面和第二面的四边边沿，并且第二掩膜层30覆盖到第一掩膜层20之上，并且第二掩膜层30不覆盖到掩膜图案上，保证第二掩膜层30和第一掩膜层20存在重叠部分，避免第二掩膜层30和第一掩膜层20的交接处出现缝隙，同时避免第二掩膜层30覆盖到掩膜图案上影响后续电镀栅线。
示例地，如图13b所示，在电池片基体10的同一侧边沿上，第一掩膜层20的一边到电池片基体10的第一边的距离为h1，掩膜图案的一边到电池片基体10的第一边的距离为h2，第二掩膜层30的一边到电池片基体10的第一边的距离为h3，则满足h1大于0且h1<h3<h2。电池片基体10的第一边为电池片基体10上任意的一边，但不是倒角边。
示例地，如图13c所示，电池片基体10包括连续的第一边、第二边和第三边，第一边和第三边位于第二边的两侧，电池片基体10的第二边的边长为k1；第一掩膜层20沿电池片基体10的第二边的中垂线对称分布，沿着电池片基体10的第二边的延长方向，第一掩膜层20的长度为k2；沿着电池片基体10的第二边的延长方向，掩膜图案的长度为k3，掩膜图案沿电池片基体10的第二边的中垂线对称分布在第一掩膜层20上；位于第一边一侧的掩膜图案的一边到第一边的距离为h31,位于第三边一侧的掩膜图案的另一边到第三边的距离为h32，h31和h32均属于h3的取值范围内；则满足k1>k2且2h3+k2>k1且2h3+k3<k1。优选地，k1的公差为±p；当电池片基体10的第二边的边长为k1-p时，则满足k1-k2-p>0且(k1-p-k2)/2<h3<(k1-p-k3)/2；当电池片基体10的第二边的边长为k1+p时，则满足k1-k2+p>0且(k1+p-k2)/2<h3<(k1+p-k3)/2；在更为优选的实施例中，k1-k2-p>0且(k1+p-k2)/2<h3<(k1-p-k3)/2，h3在该区间内取任意值，可以保证对公差±p范围内的全部电池片基体10实现第一掩膜层20和第二掩膜层30的设置。
需要说明的是，掩膜图案由前述的掩膜开口22组成。
在优选的实施例中，如图13d所示，先在电池片基体10的边缘设置第二掩膜层30，再设置第一掩膜层20，第一掩膜层20不完全覆盖电池片基体10的第一面上的第二掩膜层30，第一掩膜层20不完全覆盖电池片基体10的第二面上的第二掩膜层30，在电池片基体10的第一面和第二面的四边边沿上分别形成一个回形阶梯，避免形成第一掩膜层20时涂布的第一掩膜材料落到涂布平台上污染涂布平台。
在具体的实施例中，采用网版印刷获得的金属栅线40，其高度为15um-20um，线宽约为45um，受到网版的限制，金属栅线40的线宽无法大幅降低，高宽比也无法提升；而采用电镀方法获得的金属栅线40， 可以通过打印和显影获得更窄的掩膜开口22，进而电镀获得更窄的金属栅线40，金属栅线40的高度可以达到8um-15um，线宽为10um-20um。因此，采用电镀方法能够获得更窄的金属栅线40和高宽比更大的金属栅线40，降低了金属栅线40的遮光面积，可以提升所制备的电池片的效率。
在优选的实施例中，如图13e所示，当在电池片基体10的第一面和第二面上形成第一掩膜层20，电池片基体10的第一面为受光面，电池片基体10的第二面为背光面，使得受光面上的第一掩膜层20的厚度大于背光面上的第一掩膜层20的厚度。因此，在受光面上的掩膜开口22的深度大于背光面上的掩膜开口22的深度，进而在受光面上的金属栅线40的高度大于背光面上的金属栅线40的高度，提升了受光面上金属栅线40的高宽比，提升了所制备的电池片的效率。同时，背光面上的第一掩膜层20的厚度减薄，用量减少，可以节省成本。更优选地，电镀在受光面上的金属栅线40的数量少于背光面上的金属栅线40的数量，电镀在受光面上的金属栅线40的宽度小于背光面上的金属栅线40的宽度，降低了受光面上金属栅线40的遮光面积，且进一步提升了受光面上金属栅线40的高宽比，提升了所制备的电池片的效率，同时背光面上的金属栅线40的数量较多，背光面上的金属栅线40的宽度较大，提升了所制备的电池片的背光面的导电性能。
在更为具体的实施方式中，参考图14a，衬底结构层11包括晶硅衬底层111和设置在其两侧的本征半导体层112；在优选的实施例中，参考图14b，晶硅衬底层111和本征半导体层112之间还设置有薄膜隧穿层113，薄膜隧穿层113包括氧化硅(SiO2)、氮化硅(SiNx)、氮氧化硅(SiOxNy)、氧化铝(Al2O3)和氧化钛(TiO2)中的任一种。
在其他实施例中，在先涂布材料的烘干时间小于在后涂布材料的烘干时间；当在先涂布材料为第一掩膜材料，在后涂布材料为第二掩膜材料，那么第一掩膜材料的烘干时间小于在第二掩膜材料的烘干时间；当在先涂布材料为第二掩膜材料，在后涂布材料为第一掩膜材料，那么第二掩膜材料的烘干时间小于第一掩膜材料的烘干时间。对在后涂布材料进行烘干时也会对在先涂布材料进行再次烘干，为了避免在先涂布材料的烘干时间过长，导致过度固化，使得在先涂布材料的烘干时间小于在后涂布材料的烘干时间。
在优选的实施例中，电池片基体10上涂布第二掩膜材料的喷涂点设置在电池片基体10的边沿上，如图15a所示，电池片基体10水平放置，涂布第二掩膜材料的喷涂点设置在电池片基体10的左侧边沿上，喷涂第二掩膜材料时，第二掩膜材料接触到电池片基体10的表面时，由接触点向周围扩散，向右为电池片基体10的中部，向左为电池片基体10的边沿，当第二掩膜材料扩散到电池片基体10的边沿时，在重力作用下会加速带动第二掩膜材料沿电池片基体10的左侧侧壁向下流动，第二掩膜材料具有表面张力，左侧侧壁上的第二掩膜材料会拉动电池片基体10的左侧边沿上的第二掩膜材料向左移动，在涂布引导机构的引导下，使得左侧侧壁上的第二掩膜材料流动到电池片基体10的下表面上。第二掩膜材料的喷涂点为一个，围绕电池片基体10喷涂一圈即可完成在电池片基体10喷涂第二掩膜材料。如图15b所示，电池片基体10水平放置，第二掩膜材料的喷涂点为两个，分别设置在电池片基体10的左侧边沿和右侧边沿上，两个喷涂点同时对电池片基体10的左侧边缘和右侧边缘涂布；完成电池片基体10的左侧边缘和右侧边缘涂布后，电池片基体10旋转90度或者两个喷涂点移动到电池片基体10的前后边沿上，再同时对电池片基体10的前侧边缘和后侧边缘涂布。在其他实施例中，喷涂点可以为四个，分别同时或者依次对电池片基体10的四个边缘涂布。
进一步地，参考图16a，涂布引导机构包括包括“U”型槽210以及设置在“U”型槽210一个侧壁上的进料管220，进料管220连通“U”型槽210；涂布工作时，电池片基体10的边缘插入到“U”型槽210内，使得“U”型槽210内形成一个“U”型填充区，进料管220位于电池片基体10上方，第二掩膜材料从进料管220流入到“U”型填充区，第二掩膜材料填满“U”型填充区即完成电池片基体10的边缘上一段区域的涂布，然后沿着电池片基体10的边沿，涂布引导机构与电池片基体10相对移动，以完成后续连续区域的涂布。“U”型槽210的出口上未设置阻挡件，第二掩膜材料在电池片基体10上表面上覆盖的宽度(图中左右方向的长度)大于第二掩膜材料在电池片基体10下表面上覆盖的宽度。
如图16b所示，在“U”型槽210的出口上设置阻挡件230，限制第二掩膜材料在电池片基体10的上表面和下表面上的流动位置，可以保持第二掩膜材料在电池片基体10上表面上覆盖的宽度等于第二掩膜材料在电池片基体10下表面上覆盖的宽度，“U”型槽210的另一个侧壁上设置有出料管240，出料管240位于电池片基体10的下方。本实施例中，第二掩膜材料可以从出料管240进料，然后从进料管220出料。
实施例2
一种电池片制备方法，包括以下步骤：
S21、在电池片基体10的第一面和/或第二面上形成具有掩膜开口22的第一掩膜层20。
与实施例1不同的是，本实施例中的掩膜开口22是在形成第一掩膜层20的同时一起形成的，例如对在种子层14上的局部区域进行涂布第一掩膜材料，种子层14上未涂布第一掩膜材料的区域暴露出种子层14，种子层14上未涂布第一掩膜材料的区域构成掩膜开口22。
具体地，步骤S21包括以下步骤：
S211，在种子层14上设置掩膜网版；
S212，在掩膜网版的网孔中涂布第一掩膜材料；
S213，对掩膜网版的网孔中已涂布的第一掩膜材料进行平整；
S214，对掩膜网版的网孔中已平整的第一掩膜材料进行烘干固化；
S215，去除掩膜网版，在种子层14上形成具有掩膜开口22的第一掩膜层20。
采用掩膜网版能够精准控制具有掩膜开口22的第一掩膜层20的成型，特别是在第一掩膜材料粘度较低的情况下，可以较好地控制掩膜开口22的形状，避免掩膜开口22在成型的过程中变形。在其他实施例中，可以先去除掩膜网版，再对第一掩膜材料进行烘干固化形成具有掩膜开口22的第一掩膜层20；或者在烘干的过程中去除掩膜网版。
S13、在电池片基体10上的边缘形成第二掩膜层30，所述电池片基体10上的边缘至少包括电池片基体10的全部侧壁。
S14、在掩膜开口22中电镀形成金属栅线40。
S15、去除第一掩膜层20和第二掩膜层30。
优选地，当电池片基体10上设置有种子层14，步骤S15包括，先去除第一掩膜层20和第二掩膜层30，再刻蚀去除电池片基体10上的种子层14。
本实施是在实施例1的基础上进行改进的，与实施例1相同的技术细节本实施例做了省略，应该理解的是，在不违背本实施例原理的情况下，实施例1中的技术方案和技术细节也可以适用于本实施例。
实施例3
TCO层13的厚度增大，其导电性增强，但是透光性降低；TCO层13的厚度减小，其导电性减弱，但是透光性提升；现有的技术无法解决这一技术矛盾。
为此，本实施例提出一种电池片制备方法，包括以下步骤：
S31、在衬底结构层11上设置TCO层13，使得至少一个TCO层13的厚度为M以形成TCO减薄层；衬底结构层11上的TCO层13可能为一个或者两个，当衬底结构层11上的TCO层13为一个，可以使得这一个TCO层13的厚度为M以形成一个TCO减薄层；当衬底结构层11上的TCO层13为两个，可以使得这两个TCO层13中的一个的厚度为M以形成一个TCO减薄层，或者，可以使得这两个TCO层13中的两个的厚度均为M以形成两个TCO减薄层。
S32、在TCO减薄层上电镀金属栅线40，根据一个TCO减薄层的厚度，控制该一个TCO减薄层上的金属栅线40的宽度为N，且该一个TCO减薄层上的相邻的金属栅线40之间的间距为T；
其中，M的取值范围为40nm-80nm，N的取值范围为20-40um，T的取值范围为0.3-1.4mm。
优选地，M的取值可以为40nm,45nm,50nm,55nm,60nm,65nm,70nm或者75nm；N的取值可以为20um,22um,24um,26um,28um,30um,32um,34um,36um,38um或者40um，T的取值可以为0.3mm,0.4mm,0.5mm,0.6mm,0.7mm,0.8mm,0.9mm,1.0mm,1.1mm,1.2mm,1.3mm或者1.4mm。
优选地，步骤S31中，在衬底结构层11的第一面和第二面上向远离衬底结构层11的方向依次设置掺杂半导体层12和TCO层13，使得衬底结构层11的第一面上TCO层13的厚度为M以形成第一TCO减薄层，和/或，使得衬底结构层11的第二面上TCO层13的厚度为M以形成第二TCO减薄层。
当所制备的是双面电极电池片，步骤31中，使得衬底结构层11的第一面和第二面上TCO层13的厚度均为M，对应地形成第一TCO减薄层和第二TCO减薄层；步骤32中，在第一TCO减薄层和第二TCO减薄层上均电镀金属栅线40，根据第一TCO减薄层的厚度，控制第一TCO减薄层上的金属栅线40的宽度为N，且第一TCO减薄层上的相邻的金属栅线40之间的间距为T，和/或，根据第二TCO减薄层的厚度，控制第二TCO减薄层上的金属栅线40的宽度为N，且第二TCO减薄层上的相邻的金属栅线40之间 的间距为T。
当所制备的是单面电极电池片，步骤31中，使得衬底结构层11的第一面或第二面上TCO层13的厚度为M以在对应面上形成一个TCO减薄层；步骤32中，在该一个TCO减薄层上电镀金属栅线40，根据该一个TCO减薄层的厚度，控制该一个TCO减薄层上的金属栅线40的宽度为N，且该一个TCO减薄层上的相邻的金属栅线40之间的间距为T。
减小TCO层13的厚度形成TCO减薄层，会导致TCO层13的导电性减弱，透光性提升；缩小相邻的金属栅线40之间的间距，可以弥补TCO层13的导电性能，使得所制备的电池片不会因为TCO层13的导电性减弱导致而降低效率，然而同一TCO减薄层上金属栅线40的数量会增加，会增加同一TCO减薄层上全部金属栅线40的总遮光面积，又会降低所制备的电池片的效率；采用电镀的方法，可以获得更窄的金属栅线40，即使增加同一TCO减薄层上金属栅线40的数量，同一TCO减薄层上全部金属栅线40的总遮光面积也不会增加，甚至可能减小，最终使得所制备的电池片的效率得以提升，同时也节省了TCO材料的用量，节省了制备电池片的成本。
优选地，步骤S32中形成金属栅线40的方法可以采用实施例1-2的技术方案，以提升所制备的电池片的效率。
优选地，为了提升金属栅线40的电镀效果，在衬底结构层11的第一面和/或第二面上的TCO层13先设置种子层14，金属栅线40电镀于种子层14上，然后再将种子层14刻蚀去除。
电池片基体10上的减反射层或TCO层13，通常采用物理气相沉积或化学气相沉积的方法形成。对异质结电池来说，需要在受光面和背光面都沉积透明导电氧化物以形成TCO层13，通常将电池片基体10放置于具有开口的托盘上，托盘经过沉积受光面层的靶位段和沉积背光面层的靶位段。电池片基体10与托盘接触的位置被遮挡，因此无法沉积透明导电氧化物以形成TCO层13，进而暴露出电池片基体10上的掺杂半导体层12(例如非晶硅或微晶硅层)，该掺杂半导体层12的表面与外界的金属粒子直接接触，会降低所制备的电池片的效率。例如，在电镀铜的制程中，该掺杂半导体层12的表面与种子层14直接接触，这存在两个风险：(1)热处理(例如烘干)过程会导致种子层14通过掺杂半导体层12扩散到电池片基体10内，造成电池片的电性能损失；(2)去除种子层14的溶液中含有铜离子，在清洗时易附着到掺杂半导体层12上，在后续热处理及电池片户外使用过程中扩散到电池片基体10内，也会造成电池片的电性能损失。在上述电镀铜的制程中，金属粒子包括种子层14上的金属单质，例如铜单质，以及铜离子。
因此，本实施例中的一种电池片制备方法，步骤31和步骤32之间还包括步骤33，在掺杂半导体层12的表面设置隔离层132。优选地，通过气相沉积在掺杂半导体层12的表面设置隔离层132。
示例地，如图17和图18所示，电池片基体10包括TCO层13，TCO层13上有暴露掺杂半导体层12的缺陷坑131，采用隔离层132覆盖缺陷坑131。图17中的方案，隔离层132仅仅覆盖TCO层13上的缺陷坑131，不会额外增加电池片基体10的厚度；图18中的方案，隔离层132在TCO层13上形成新的一层同时覆盖住缺陷坑131，不必提前识别缺陷坑131的位置，能够快速弥补缺陷坑131。
本实施例通过设置隔离层132，可以避免金属粒子通过掺杂半导体层12扩散到电池片基体10内，造成电池片的电性能损失的问题，能够提升所制备的电池片的效率。需要说明的是，减反射层或TCO层13基本覆盖了电池片基体10的掺杂半导体层12，但是因为制造工艺的缺陷，导致减反射层或TCO层13无法完全覆盖电池片基体10的掺杂半导体层12，从而存在局部裸露的掺杂半导体层12，为了补充覆盖局部裸露的掺杂半导体层12，在局部裸露的掺杂半导体层12上设置(优选为沉积)隔离层132，隔离层132的材料可以和减反射层或TCO层13的材料相同。减反射层的材料可以为氧化硅、氮化硅或氧化铝等。
优选地，步骤31和步骤32之间还包括步骤S34：清洗去除附着在掺杂半导体层12上的金属粒子。具体地，清洗液为酸、络合剂、氧化剂的混合溶液，采用喷洒不复用的方式或浸泡式的大流量循环。通过清洗去除附着在掺杂半导体层12上金属粒子，可以避免在后续热处理及电池片户外使用过程中金属粒子扩散到所制备的电池片内，造成所制备的电池片的电性能损失的问题。
优选地，步骤32之后还包括步骤S35，在TCO层13上形成减反射层。减反射层可以增加所制备的电池片的透光性，进一步提升所制备的电池片的效率。
在具体的实施例中，一种电池片制备方法，包括以下步骤：
S31、在衬底结构层11的第一面和第二面上向远离衬底结构层11的方向依次设置掺杂半导体层12和 TCO层13，使得衬底结构层11的第一面上TCO层13的厚度为M以形成第一TCO减薄层，和/或，使得衬底结构层11的第二面上TCO层13的厚度为M以形成第二TCO减薄层；
S34、清洗去除附着在掺杂半导体层12上金属粒子；
S33、在掺杂半导体层12的表面设置隔离层132；
S32、根据第一TCO减薄层的厚度，控制第一TCO减薄层上的金属栅线40的宽度为N，且第一TCO减薄层上的相邻的金属栅线40之间的间距为T，和/或，根据第二TCO减薄层的厚度，控制第二TCO减薄层上的金属栅线40的宽度为N，且第二TCO减薄层上的相邻的金属栅线40之间的间距为T；
步骤S32中电镀金属栅线40的过程包括：
S11、在电池片基体的10第一面和/或第二面上形成第一掩膜层20；
S12、在第一掩膜层20上形成掩膜开口22；
S13、在电池片基体10的边缘形成第二掩膜层30，所述电池片基体10的边缘至少包括电池片基体10的全部侧壁；
S14、在掩膜开口22中电镀形成金属栅线40；
S15、去除第一掩膜层20和第二掩膜层30；
S35，在TCO层13上形成减反射层。
优选地，隔离层132可能是TCO减薄层上的覆盖层，隔离层132和TCO减薄层的厚度之和为M。
优选地，掩膜开口22通过打印和显影获得。通过打印和显影的方法形成宽度为N的细小掩膜开口22，通过电镀在掩膜开口22中形成宽度为N的金属栅线40，使得同一TCO层13上相邻的金属栅线40之间的间距能够减小，即同一TCO层13上金属栅线40的数量会增加，且不会因此扩大同一TCO层13全部金属栅线40的遮光面积；因为相邻的金属栅线40之间的间距减小，同一TCO层13全部金属栅线40的导电性能提升，使得减小TCO层13的厚度成为可能。因此，在制备电池片时，使得TCO层13的厚度为M以形成TCO减薄层，再根据TCO减薄层的厚度，在TCO减薄层上电镀形成金属栅线40，控制TCO减薄层上的金属栅线40的宽度为N，且TCO减薄层上的相邻的金属栅线40之间的间距为T。因而，TCO层13的厚度得以减小，节约了电池片的制备成本，同时保持或者提升了所制备的电池片的效率。
在另一种具体的实施例中，步骤S11和S12可以采用步骤S31替代，步骤S31：在电池片基体的第一面和/或第二面上形成具有掩膜开口的第一掩膜层。
本发明的实施例还提供一种电池片，采用实施例1-实施例3中的方法制备获得，因此该电池片也具备实施例1-实施例3中的方法的特征及优点。
需要说明的是，在实施例1-实施例3中，电池片基体10的第一面指的是电池片基体10的一个表面或者与该表面直接接触或者间接接触的某一材料层的一个表面，例如电池片基体10的一个表面上设置有第一掩膜层20，可以表述为电池片基体10的第一面上设置有第一掩膜层20，当电池片基体10的一个表面是种子层14的外侧表面，种子层14的内侧表面连接于电池片基体10上的TCO层13，如果再在第一掩膜层20的外侧表面上设置第二掩膜层30，也可以表述为电池片基体10的第一面上设置有第二掩膜层30，第二掩膜层30是间接设置在种子层14的外侧表面上。电池片基体10的第一面可以是电池片基体10的一个表面、第一掩膜层20的外侧表面或者第二掩膜层30的外侧表面，其具体意思应该根据语境进行理解。这里，靠近电池片基体10内部的一侧为内侧，远离电池片基体10内部的一侧为外侧。同理，电池片基体10的第二面也应该作相同的理解。
在实施例1-实施例3中，衬底结构层11的第一面指的是衬底结构层11的一个表面或者与该表面直接接触或者间接接触的某一材料层的一个表面，例如衬底结构层11的一个表面上向远离衬底结构层11的方向依次设置有掺杂半导体层12和TCO层13，这里，掺杂半导体层12是直接设置在衬底结构层11的一个表面上，TCO层13是间接设置在衬底结构层11的一个表面上，衬底结构层11的第一面可以是衬底结构层11的一个表面、掺杂半导体层12的外侧表面或者TCO层13的外侧表面。特别地，衬底结构层11的第一面与电池片基体10的第一面可能表示为同一个表面。同理，衬底结构层11的第二面也应该作相同的理解。
上述实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。

Claims (30)

  1. 一种电池片制备方法，其特征在于，包括以下步骤：
    S11、在电池片基体的第一面和/或第二面上形成第一掩膜层；
    S12、在第一掩膜层上形成掩膜开口；
    S13、在电池片基体的边缘形成第二掩膜层，所述电池片基体的边缘至少包括电池片基体的全部侧壁；
    S14、在掩膜开口中电镀形成金属栅线；
    S15、去除第一掩膜层和第二掩膜层。
  2. 根据权利要求1所述的电池片制备方法，其特征在于，所述第一掩膜材料为感光树脂，所述第二掩膜材料为热固化树脂。
  3. 根据权利要求1所述的电池片制备方法，其特征在于，将所述电池片基体的表面划分为A、B和C三个区域；所述电池片基体的第一面由A区域和B区域组成，所述B区域邻接所述第一面的边线；在所述第一面上，所述B区域为环形，所述B区域包围A区域；所述C区域为电池片基体的全部侧壁；
    所述第一掩膜层覆盖第一面上的全部A区域，且至少覆盖第一面上的部分B区域；所述第二掩膜层覆盖全部C区域，且至少覆盖第一面上的部分B区域；所述第一掩膜层和第二掩膜层在第一面上的B区域部分重叠。
  4. 根据权利要求3所述的电池片制备方法，其特征在于，所述电池片基体的第二面由A区域和B区域组成，所述B区域邻接所述第二面的边线；在所述第二面上，所述B区域为环形，所述B区域包围A区域；所述第一掩膜层覆盖第二面上的全部A区域，且至少覆盖第二面上的部分B区域；所述第二掩膜层至少覆盖第二面上的部分B区域，所述第一掩膜层和第二掩膜层在第二面上的B区域部分重叠。
  5. 根据权利要求4所述的电池片制备方法，其特征在于，所述第二掩膜层沿上下方向的截面为“C”型。
  6. 根据权利要求3所述的电池片制备方法，其特征在于，所述第一掩膜层和第二掩膜层在B区域的重叠部分为环形。
  7. 根据权利要求3所述的电池片制备方法，其特征在于，所述第一掩膜层的边沿包括第一倾斜减薄层，所述第二掩膜层的边沿包括第二倾斜减薄层，所述第一倾斜减薄层和第二倾斜减薄层重叠构成第一掩膜层和第二掩膜层在B区域的重叠部分。
  8. 根据权利要求1所述的电池片制备方法，其特征在于，涂布的第二掩膜材料沿着第一面的边沿依次覆盖形成第一边沿条形区、第二边沿条形区、第三边沿条形区和第四边沿条形区，所述第一边沿条形区、第二边沿条形区、第三边沿条形区和第四边沿条形区的宽度依次为d3、d4、d5和d6，其中，d3、d4、d5和d6的取值范围均为0.2-5mm。
  9. 根据权利要求8所述的电池片制备方法，其特征在于，电池片基体的边长为d0,所述d3、d4、d5和d6分别与d0的比值范围均为0.1％-3％。
  10. 根据权利要求1所述的电池片制备方法，其特征在于，先对电池片基体的第一面上的左右两侧边沿涂布形成第一边沿条形区和第三边沿条形区，再对电池片基体的第一面上的上下两侧边沿涂布形成第二边沿条形区和第四边沿条形区；第一边沿条形区和第二边沿条形区相交，第一边沿条形区和第四边沿条形区相交，第三边沿条形区和第二边沿条形区相交，第三边沿条形区和第四边沿条形区相交。
  11. 根据权利要求1所述的电池片制备方法，其特征在于，沿逆时针或顺时针方向在电池片基体的第一面上的边沿上涂布第二掩膜材料，形成首尾相交的环形区域。
  12. 根据权利要求1所述的电池片制备方法，其特征在于，步骤S15包括：先将第二掩膜层溶解去除，再将第一掩膜层溶胀之后与电池片基体分离。
  13. 根据权利要求1所述的电池片制备方法，其特征在于，当金属栅线为易氧化金属，在金属栅线的表面上设置抗氧化层。
  14. 根据权利要求13所述的电池片制备方法，其特征在于，所述抗氧化层覆盖金属栅线的顶部和侧壁。
  15. 根据权利要求14所述的电池片制备方法，其特征在于，所述抗氧化层通过化学置换反应获得。
  16. 根据权利要求1所述的电池片制备方法，其特征在于，所述步骤S13设置在步骤S11之后，步骤S14之前；或者，所述步骤S13设置在步骤S11之前。
  17. 根据权利要求1所述的电池片制备方法，其特征在于，先在电池片基体的第一面和第二面上设置第一掩膜层，第一掩膜层不完全覆盖电池片基体的第一面并露出电池片基体的第一面的四边边沿，第一掩膜层不完全覆盖电池片基体的第二面并露出电池片基体的第二面的四边边沿；然后第二掩膜层覆盖露出的电池片基体的第一面和第二面的四边边沿，并且第二掩膜层覆盖到第一掩膜层之上，并且第二掩膜层不覆盖到掩膜图案上。
  18. 根据权利要求17所述的电池片制备方法，其特征在于，在电池片基体的同一侧边沿上，第一掩膜层的一边到电池片基体的第一边的距离为h1，掩膜图案的一边到电池片基体的第一边的距离为h2，第二掩膜层的一边到电池片基体的第一边的距离为h3；则满足h1大于0且h1<h3<h2。
  19. 根据权利要求18所述的电池片制备方法，其特征在于，电池片基体包括连续的第一边、第二边和第三边，第一边和第三边位于第二边的两侧，电池片基体的第二边的边长为k1；第一掩膜层沿电池片基体的第二边的中垂线对称分布，沿着电池片基体的第二边的延长方向，第一掩膜层的长度为k2；沿着电池片基体的第二边的延长方向，掩膜图案的长度为k3，掩膜图案沿电池片基体的第二边的中垂线对称分布在第一掩膜层上；位于第一边一侧的掩膜图案的一边到第一边的距离为h31,位于第三边一侧的掩膜图案的另一边到第三边的距离为h32，h31和h32均属于h3的取值范围内；则满足k1>k2且2h3+k2>k1且2h3+k3<k1。
  20. 根据权利要求19所述的电池片制备方法，其特征在于，k1的公差为±p；则满足k1-k2-p>0且(k1+p-k2)/2<h3<(k1-p-k3)/2。
  21. 根据权利要求1所述的电池片制备方法，其特征在于，所述金属栅线为具有宽度梯度的栅线。
  22. 根据权利要求1所述的电池片制备方法，其特征在于，第二掩膜材料在电池片基体上表面上覆盖的宽度大于第二掩膜材料在电池片基体下表面上覆盖的宽度。
  23. 根据权利要求1-22任一项所述的电池片制备方法，其特征在于，当在电池片基体的第一面和第二面上形成第一掩膜层，电池片基体的第一面为受光面，电池片基体的第二面为背光面，使得受光面上的第一掩膜层的厚度大于背光面上的第一掩膜层的厚度。
  24. 根据权利要求1-22任一项所述的电池片制备方法，其特征在于，电镀在受光面上的金属栅线的数量少于背光面上的金属栅线的数量。
  25. 根据权利要求1-22中任一项所述的电池片制备方法，其特征在于，还包括以下步骤：
    S31、在衬底结构层上设置TCO层，使得至少一个TCO层的厚度为M以形成TCO减薄层；
    S32、在TCO减薄层上电镀金属栅线，根据一个TCO减薄层的厚度，控制该一个TCO减薄层上的金属栅线的宽度为N，且该一个TCO减薄层上相邻的金属栅线之间的距离为T；
    其中，M的取值范围为40nm-80nm，N的取值范围为20-40um，T的取值范围为0.3-1.4mm。
  26. 根据权利要求25所述的电池片制备方法，其特征在于，步骤S31中，在衬底结构层的第一面和第二面上向远离衬底结构层的方向依次设置掺杂半导体层和TCO层，使得衬底结构层的第一面上TCO层的厚度为M以形成第一TCO减薄层，和/或，使得衬底结构层的第二面上TCO层的厚度为M以形成第二TCO减薄层。
  27. 根据权利要求25所述的电池片制备方法，其特征在于，步骤31和步骤32之间还包括步骤33，在掺杂半导体层的表面设置隔离层。
  28. 根据权利要求25所述的电池片制备方法，其特征在于，步骤31和步骤32之间还包括步骤S34，清洗去除附着在掺杂半导体层上的金属粒子。
  29. 根据权利要求1所述的电池片制备方法，其特征在于，采用步骤21替换步骤S11和S12，
    S21、在电池片基体的第一面和/或第二面上形成具有掩膜开口的第一掩膜层。
  30. 一种电池片，其特征在于，采用权利要求1-29中任一项所述的电池片制备方法制备获得。
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