WO2024098783A1

WO2024098783A1 - Time correction method and apparatus

Info

Publication number: WO2024098783A1
Application number: PCT/CN2023/103446
Authority: WO
Inventors: 赵思蓉; 任慰; 代雷; 曾维林; 李宗鸿; 谢国琪
Original assignee: 华为技术有限公司
Priority date: 2022-11-11
Filing date: 2023-06-28
Publication date: 2024-05-16
Also published as: CN118041477A

Abstract

The present application relates to the field of communications, and discloses a time correction method and apparatus. The time correction method is applied to a computing device, the computing device comprises a master clock module and a slave clock module, and the method is applied to the slave clock module. The method comprises: when the master clock module and the slave clock module send time messages to each other at least twice, acquiring a plurality of timestamps of the master clock module and the slave clock module respectively transmitting and receiving the time messages, the master clock module and the slave clock module transmitting and receiving the time messages by means of a first channel, the first channel being realized by means of mapping between an Unix domain socket file installed in the master clock module and a virtual serial port installed in the slave clock module, and the virtual serial port being obtained by starting a VirtIO driver in the slave clock module by the master clock module; determining a time error of the slave clock module with respect to the master clock module according to the plurality of timestamps; and correcting the system time of the slave clock module according to the time error. The time correction precision of the slave clock module is improved.

Description

Time correction method and device

This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on November 11, 2022, with application number 202211414938.9 and application name “Time Correction Method and Device”, all contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the field of communications, and in particular to a time correction method and device.

Background technique

In an embedded system supported by virtualization technology, each virtual machine performs its own functional tasks without interfering with each other, thus ensuring that the failure of a virtual machine will not affect the normal operation of other virtual machines. However, frequent real-time data transmission is required between virtual machines to perform specific complex functional operations. For example, in a car, the brake system (virtual machine 1) needs to obtain data such as vehicle distance based on the radar system (virtual machine 2) to determine whether to brake at the moment.

The real-time communication function between virtual machines needs to ensure low latency and high reliability of the message transmission process. In some application scenarios with high time accuracy requirements, such as advanced driver assistance system (ADAS) application scenarios, the time error between virtual machines is not allowed to be less than microseconds. Therefore, it is necessary to perform time synchronization operations between the host and the virtual machine to reduce the time deviation between the two to the microsecond level to meet the needs of real-time communication between multiple virtual machines. However, the existing time synchronization methods have low accuracy.

Summary of the invention

The present application provides a time correction method and device for solving the problem of low accuracy of existing time synchronization methods.

In order to achieve the above objectives, this application adopts the following technical solutions:

In a first aspect, a time correction method is provided, which is applied to a slave clock module of a computing device, wherein the computing device further includes a master clock module, and the method includes:

When the master clock module and the slave clock module send time messages to each other at least twice, the master clock module and the slave clock module respectively send and receive multiple timestamps of the time messages; the master clock module and the slave clock module send and receive time messages through a first channel; the first channel is realized by mapping between the Unex domain socket file installed in the master clock module and the virtual serial port installed in the slave clock module, and the virtual serial port is obtained by the master clock module starting the VirtIO driver in the slave clock module; according to the multiple timestamps, the time error of the slave clock module relative to the master clock module is determined; and the system time of the slave clock module is corrected according to the time error.

In the first aspect, the slave clock module and the master clock module send and receive time messages through the first channel composed of the mapping between the Unex domain socket file and the virtual serial port, so that the slave clock module obtains multiple timestamps. Then the slave clock module determines the time error of the slave clock module relative to the master clock module based on the multiple timestamps, and then corrects the system time of the slave clock module according to the time error. The first channel is constructed using the VirtIO driver, and VirtIO is a shared physical memory communication method based on I/O virtualization, which does not rely on network communication and does not require protocol processing. It realizes the role of data replication through file mapping, reduces the load consumption of the slave clock module and the master clock module sending and receiving time messages and the impact of network delay, and then realizes lightweight time correction at the resource level, which can meet the time correction requirements of resource-constrained virtualization platforms. And the time error between the slave clock module and the master clock module is reduced from milliseconds to microseconds.

In one possible implementation, obtaining multiple timestamps includes:

Receive a first time message, the first time message carries a first timestamp representing the moment when the master clock module sends the first time message; record a second timestamp representing the moment when the master clock module receives the first time message; in response to the first time message, send a second time message to the master clock module, and record a third timestamp representing the moment when the slave clock module sends the second time message; receive a third time message sent by the master clock module to the slave clock module in response to the second time message, the third time message includes a fourth timestamp representing the time when the master clock module receives the second time message.

In this implementation, a response mechanism for the time message is designed so that the slave clock module can obtain multiple timestamps, and the multiple timestamps obtained have high accuracy.

In a possible implementation, the master clock module is a clock module of a master operating system, and the slave clock module is a clock module in a slave operating system, wherein the master operating system is an operating system of a computing device, and the slave operating system is an operating system of a virtual machine running on the computing device.

In a possible implementation, the virtio serial field and the Unex field are set in the startup configuration extensible markup language file of the slave clock module; the virtual serial port is obtained by the master clock module by starting the VirtIO driver in the slave clock module according to the startup configuration extensible markup language file with the virtio serial field and the Unex field added; wherein, one virtual serial port corresponds to one Unex domain socket file.

In this implementation, the VirtIO driver is used to build the first channel. VirtIO is a shared physical memory communication method based on I/O virtualization. It does not rely on network communication and does not require protocol processing. It implements data replication through file mapping, reduces the load consumption of sending and receiving time messages between the slave clock module and the master clock module, and the impact of network delays, thereby achieving lightweight time correction at the resource level, which can meet the time correction requirements of resource-constrained virtualization platforms.

In a possible implementation, correcting the system time of the slave clock module according to the time error includes:

The time error is input into a preset computer function to correct the system time of the slave clock module.

In this implementation, the system time of the slave clock module is corrected based on the time error by a preset computer function, and the correction efficiency is high.

In a possible implementation, after the slave clock module corrects the time of the slave clock module according to the time error, the method further includes:

In the case where the result of the preset computer function output indicates that the system time correction of the slave clock module fails, a plurality of time stamps are reacquired to recorrect the system time of the slave clock module.

In this implementation, a recalibration mechanism is designed in the event that the system time correction of the slave clock module fails. When the system time correction of the slave clock module fails, multiple timestamps can be reacquired to recalibrate the system time of the slave clock module, thereby improving the time correction accuracy.

In a second aspect, a time correction method is provided, which is applied to a computing device, wherein the computing device includes a master clock module and a slave clock module, and the method is applied to the master clock module, and the method includes:

At least two timestamps are sent to the slave clock module through the first channel, and the timestamps are used to correct the system time of the slave clock module that obtains the at least two timestamps; the at least two timestamps include a timestamp representing the moment when the master clock module sends a time message to the slave clock module, and a timestamp representing the moment when the master clock module receives a time message from the slave clock module; the first channel includes a mapping between the Unex domain socket file installed in the master clock module and the virtual serial port installed in the slave clock module, and the virtual serial port is obtained by the master clock module starting the VirtIO driver in the slave clock module.

In the second aspect, the slave clock module and the master clock module send and receive time messages through the first channel composed of the mapping between the Unex domain socket file and the virtual serial port, so that the slave clock module obtains multiple timestamps. The first channel is constructed using the VirtIO driver, and VirtIO is a shared physical memory communication method based on I/O virtualization. It does not rely on network communication and does not require protocol processing. It achieves data replication through file mapping, reduces the load consumption of sending and receiving time messages between the slave clock module and the master clock module, and the impact of network delay, thereby achieving lightweight time correction at the resource level, which can meet the time correction requirements of resource-constrained virtualization platforms.

In one possible implementation, at least two timestamps are sent to the slave clock module through the first channel, including: sending a first time message to the slave clock module, the first time message carrying a timestamp representing the moment when the master clock module sends the first time message to the slave clock module; receiving a second time message from the slave clock module, the second time message is a time message sent by the slave clock module to the master clock module in response to the first time message; in response to the second time message, sending a third time message to the slave clock module, the third time message including a timestamp representing the moment when the master clock module receives the second time message.

In a possible implementation, the startup configuration XML file of the slave clock module is provided with a virtio serial field and an unix field; the virtual serial port is configured by the master clock module according to the startup configuration file with the virtio serial field and the unix field added. Configure the Extensible Markup Language file and start the VirtIO driver in the slave clock module to obtain it; among them, one virtual serial port corresponds to one Unex domain socket file.

In a third aspect, the present application provides a time correction device, which may be a slave clock module or a chip or system on chip in a slave clock module. The time correction device may implement the functions performed by the slave clock module in the first aspect or a possible design of the first aspect, and the functions may be implemented by hardware or by hardware executing corresponding software.

In a fourth aspect, the present application provides a time correction device, which may be a main clock module or a chip or system on chip in the main clock module. The time correction device may implement the function performed by the main clock module in the second aspect or the possible design of the second aspect, and the function may be implemented by hardware or by hardware executing corresponding software.

In a fifth aspect, the present application provides a time correction device, the time correction device includes a processor, the processor is used to support the time correction device to execute the method of the first aspect or the second aspect. Further, the time correction device may also include a memory, the memory stores computer instructions, and the processor can execute the computer instructions to execute the method of the first aspect or the second aspect.

In a sixth aspect, the present application provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed, the method of the first aspect or the second aspect is executed.

In a seventh aspect, the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method of the first aspect or the second aspect described above.

In an eighth aspect, the present application provides a chip comprising a processor and a transceiver, wherein the processor and the transceiver are used to support a time correction device to execute the method of the first aspect or the second aspect.

In a ninth aspect, the present application provides a time correction system, which includes a master clock module and a slave clock module; wherein the master clock module is used to execute the method of the second aspect; and the slave clock module is used to execute the method of the first aspect.

Among them, the beneficial effects described in the third to ninth aspects of the present application can refer to the analysis of the beneficial effects of the first or second aspect, and will not be repeated here.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a time correction system provided in an embodiment of the present application;

FIG2 is a schematic diagram of a flow chart of a time correction method provided in an embodiment of the present application;

FIG3 is a schematic diagram of the structure of another time correction system provided in an embodiment of the present application;

FIG4 is a schematic diagram of a flow chart of another time correction method provided in an embodiment of the present application;

FIG5 is a schematic diagram of a flow chart of another time correction method provided in an embodiment of the present application;

FIG6 is a schematic diagram of the structure of another time correction system provided in an embodiment of the present application;

FIG7 is a schematic diagram of the structure of a time device provided in an embodiment of the present application;

FIG8 is a structural diagram of a time correction device provided in an embodiment of the present application;

FIG9 is a structural diagram of another time correction device provided in an embodiment of the present application;

FIG. 10 is a schematic diagram of the structure of another time correction system provided in an embodiment of the present application.

Detailed ways

The network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person of ordinary skill in the art can appreciate that with the evolution of the network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

Before introducing the embodiments of the present application, some terms involved in the embodiments of the present application are explained.

Message passing: A general term for a type of data time correction method between processes or software components in a computer system. It abstracts and encapsulates the data to be communicated into "messages". The two or more parties involved in the communication can transfer messages between processes or components by calling primitives such as message sending and receiving, thereby completing data communication.

Time synchronization: The process of providing a unified time scale for distributed systems through certain operations on local clocks.

For virtual machines deployed on the same physical machine, when the operating system starts, it is necessary to obtain the real-time clock (RTC) time for time initialization, and then calculate the current system time through the frequency count of the clock source (the kernel automatically selects the clock source with the highest precision value). The count values are stored in registers. For example, under the ARM processor (advanced RISC machines, ARM) 64 architecture, the host and virtual machine are set to obtain the current system time through the count value of the cntvct_el0 register. Because the same register cannot be read by multiple virtual machines at the same time, it is interrupted by interruptions during the reading and writing process of obtaining the count value, resulting in a time deviation of several milliseconds between the current time obtained by the virtual machine and the actual time. This is not conducive to ensuring low latency and high reliability of real-time communication for systems with high time accuracy. Therefore, it is necessary to perform time synchronization operations between the host and the virtual machine to reduce the time deviation between the two to the microsecond level to meet the needs of real-time communication between multiple virtual machines.

The general time synchronization method relies on the network between the host and the virtual machine for time synchronization, such as precise time protocol (PTP), Chrony time synchronization service, network time protocol (NTP) time synchronization service, etc. The above methods are aimed at the scenarios of cloud computing and virtualization platforms in high-performance computing, which are not limited by communication resources and are based on large communication resource consumption to achieve high-precision time synchronization.

However, for some resource-constrained virtualization platforms, such as embedded systems, it is impossible to support large communication resource consumption. If the above time synchronization methods are used to synchronize the time of resource-constrained virtualization platforms, the error between resource-constrained virtualization platforms can only be controlled at the millisecond level, not at the microsecond level, and the time synchronization accuracy is low.

In order to solve the above technical problems, an embodiment of the present application provides a time correction method. The method provided by the embodiment of the present application is described below in conjunction with the drawings in the specification.

The time correction method provided in the embodiment of the present application can be applied to various time correction systems, such as: long term evolution (LTE) system, fifth generation (5G) mobile time correction system, wireless fidelity (WiFi) system, future time correction system, or a system integrating multiple time correction systems, etc., which is not limited in the embodiment of the present application. Among them, 5G can also be called new radio (NR).

The time correction method provided in the embodiment of the present application is described below using the time correction system shown in FIG. 1 as an example.

FIG1 is a schematic diagram of a computing device provided by an embodiment of the present application. As shown in FIG1 , the computing device may include: a master clock module and a slave clock module. The master clock module may be a clock module of a master operating system, and the slave clock module may be a clock module of a guest operating system. The number of slave clock modules may be multiple, and two are used as an example in FIG1 . Messages can be transmitted bidirectionally between the master clock module and the slave clock module.

FIG2 shows a schematic flow chart of a time correction method provided by an embodiment of the present application. As shown in FIG2 , the method may include the following steps:

S210, obtaining multiple timestamps from a clock module.

Among them, the multiple timestamps include the timestamps of the moments when the master clock module and the slave clock module respectively send and receive time messages when the master clock module and the slave clock module send time messages to each other at least twice. The master clock module sends a time message to the slave clock module once, or the slave clock module sends a time message to the master clock module once, which is recorded as one mutual transmission. The multiple timestamps obtained include at least the timestamp of the master clock module sending a time message (recorded as message A), the timestamp of the slave clock module receiving the message A, the timestamp of another time message (recorded as message B) sent by the slave clock module in response to the message A, and the timestamp of the master clock module receiving the message B. That is to say, at least four timestamps are included.

The master clock module can be the main operating system; the slave clock module can be the guest operating system. The master clock module and the slave clock module send and receive time messages through the first channel; the first channel is established before the slave clock module obtains multiple timestamps, which is the preparatory work of the time correction method provided in the embodiment of the present application. The first channel is mapped between the Unex domain socket file installed by the master clock module and the virtual serial port installed by the slave clock module. The establishment process of the first channel is described below:

Install the Unex Unix domain socket file in the master clock module. And modify the startup configuration extensible markup language (XML) file corresponding to the slave clock module in the master clock module. Specifically, as shown in Figure 3, add the virtio serial field to the field corresponding to the controller attribute in the startup configuration XML file, and add the unix field to the field corresponding to the channel attribute in the startup configuration XML file. Then, the master clock module starts the VirtIO driver in the slave clock module according to the startup configuration XML file with the virtio serial field and the unix field added to install the virtual serial port in the slave clock module. Then, map the virtual serial port of the slave clock module to the unix domain socket file of the master clock module one by one, so that one virtual serial port corresponds to one Unex domain socket file, and finally obtain the first channel. Through the first channel, the master clock can be realized. Communication between the module and the slave clock module.

S220: The slave clock module determines a time error of the slave clock module relative to the master clock module according to the multiple timestamps.

The multiple timestamps can represent the time when the master clock module and the slave clock module send and receive time messages respectively when the master clock module and the slave clock module send time messages to each other at least twice. Furthermore, the time error of the slave clock module relative to the master clock module can be determined based on the multiple timestamps.

Optionally, the interval from sending a certain time message to receiving the time message is recorded as the transmission time, and the slave clock module can calculate the difference between any transmission time and the average of the transmission time as the time error of the slave clock module relative to the master clock module. It can be understood that the time error of the slave clock module relative to the master clock module is obtained according to the difference between the transmission time of a time message and the average of the transmission time of multiple time messages.

Exemplarily, when determining the time error, the time error can be calculated according to a time error calculation formula. Taking the calculation of the time error based on the timestamps corresponding to the two times when the master clock module and the slave clock module send time messages to each other as an example, the time error calculation formula can be:

Time error = (T ₂ - T ₁ ) - [(T ₂ - T ₁ ) + (T ₄ - _{T 3} )] / 2

Among them, _T1 represents the timestamp of the time when the time message is sent for the first time, _T2 represents the timestamp of the time when the time message is received for the second time, _T3 represents the timestamp of the time when the time message is sent for the second time, and _T4 represents the timestamp of the time when the time message is received for the first time.

The time error calculation is performed based on the time error calculation formula. Although a small amount of time is consumed in reading the data each time the timestamp is transmitted in S210, according to the time error calculation formula, the transmission time of a time message (the sum of the net transmission time and the above-mentioned small amount of time) and the average of the transmission time of multiple time messages both include the small amount of time. By subtracting them, they can offset each other, thereby increasing the accuracy of the time error and being able to accurately calculate the time error of the slave clock module relative to the master clock module.

S230: The slave clock module corrects the system time of the slave clock module according to the time error.

After the time error of the slave clock module relative to the master clock module is determined, the system time of the slave clock module can be corrected according to the time error.

Furthermore, the system time of the slave clock module can be corrected by inputting the time error into a preset computer function. Exemplarily, the preset computer function can be selected as adjtime.

In an embodiment of the present application, the slave clock module and the master clock module receive and send time messages through the first channel composed of the mapping between the Unex domain socket file and the virtual serial port, so that the slave clock module obtains multiple timestamps. Then the slave clock module determines the time error of the slave clock module relative to the master clock module based on the multiple timestamps, and then corrects the system time of the slave clock module based on the time error. The first channel is constructed using the VirtIO driver, and VirtIO is a shared physical memory communication method based on I/O virtualization, which does not rely on network communication and does not require protocol processing. It realizes the role of data replication through file mapping, reduces the load consumption of the slave clock module and the master clock module sending and receiving time messages and the impact of network delay, and then realizes lightweight time correction at the resource level, which can meet the time correction requirements of resource-constrained virtualization platforms. And the time error between the slave clock module and the master clock module is reduced from milliseconds to microseconds.

In one embodiment, as shown in FIG. 4 , S210, obtaining multiple timestamps from a clock module may include:

S410, the master clock module sends a first time message to the slave clock module, and correspondingly, the slave clock module receives the first time message from the master clock module.

The first time message carries a first timestamp, and the first timestamp represents the time when the main clock module sends the first time message.

S420, recording a second timestamp from the clock module.

The second timestamp represents the time when the main clock module receives the first time message.

S430, the slave clock module sends a second time message to the master clock module in response to the first time message, and records a third timestamp. Accordingly, the master clock module receives the second time message. The second time message may not carry content data.

The third timestamp represents the time when the second time message is sent from the clock module.

S440: The master clock module sends a third time message to the slave clock module in response to the second time message. Correspondingly, the slave clock module receives the third time message.

The third time message includes a fourth timestamp, and the fourth timestamp represents the time when the master clock module receives the second time message.

In the embodiment of the present application, a response mechanism for designing a time message enables a slave clock module to obtain multiple timestamps, and the multiple timestamps obtained have high accuracy.

In one embodiment, after S230: the slave clock module corrects the time of the slave clock module according to the time error, as shown in FIG5 , the method may further:

S510 , when the result output by the preset computer function indicates that the system time correction of the slave clock module fails, reacquire a plurality of time stamps to recorrect the system time of the slave clock module.

The preset computer function can output a result indicating whether the correction of the system time of the slave clock module is successful, taking the adjtime function as an example. If the correction is successful, TRUE is output; if the correction fails, FALSE is output. In the case where the output result indicates that the correction fails, multiple timestamps can be re-acquired according to the time error calculated in S220 to re-correct the system time of the slave clock module.

In an embodiment of the present application, a re-correction mechanism is designed in the event that the system time correction of the slave clock module fails. When the system time correction of the slave clock module fails, multiple timestamps can be re-acquired to re-correct the system time of the slave clock module, thereby improving the time correction accuracy.

The time correction method provided in the embodiment of the present application can be applied to computing devices of various architectures, and can be applied to X86 architecture and ARM64 architecture, for example. As shown in FIG6 , in a computing device of X86 architecture or ARM64 architecture, both the master clock module and the slave clock module are Ubuntu operating systems, and based on the creation steps of the first channel introduced in S210, two unix domain socket files vm1.ctl and vm2.ctl are created on the master clock module; two virtual serial ports vport2p1 and vport2p2 are generated on the slave clock module, and vm1.ctl and vm2.ctl are mapped one-to-one with vport2p1 and vport2p2, respectively.

Based on the above embodiment, after the computing device of the X86 architecture or the ARM64 architecture executes the time correction method provided in the embodiment of the present application, the time error between the master clock module and the slave clock module is calculated to test the correction effect. At the same time, the time error between the master clock module and the slave clock module is calculated after time correction using the Chrony time synchronization service as a control group. The test results are shown in Table 1.

Table 1

Table 1 shows that on the X86 architecture, the time correction method provided in the embodiment of the present application can reduce the time error between the virtual machine and the host to about 40 microseconds (us), and stabilize it at the microsecond level, while the existing time synchronization technology Chrony time synchronization service can only reduce the time error between the virtual machine and the host to about 2000us (i.e. 2 milliseconds (ms)).

On the ARM64 architecture, the time correction method provided in the embodiment of the present application can reduce the time error between the virtual machine and the host to about 400us, while the Chrony time synchronization service can only reduce it to about 4100us (ie 4ms).

It can be seen from the above tests that the time correction method provided in the embodiment of the present application has high time correction accuracy and can reduce the time error between the slave clock module and the master clock module from the millisecond level to the microsecond level.

The above mainly introduces the scheme provided by the embodiment of the present application from the perspective of interaction between each node. It is understandable that each node, such as the master clock module and the slave clock module, includes a hardware structure and/or software module corresponding to each function in order to realize the above functions. Those skilled in the art should easily realize that, in combination with the algorithm steps of each example described in the embodiment disclosed herein, the method of the embodiment of the present application can be implemented in the form of hardware, software, or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

The embodiment of the present application can divide the functional modules of the master clock module and the slave clock module according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical functional division. It can be implemented in practice. There are other ways to divide it.

In specific implementation, the computing device shown in the present application may adopt the composition structure shown in Figure 7 or include the components shown in Figure 7. Figure 7 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application. When the computing device has the function of the master clock module described in the embodiment of the present application, the computing device may be a master clock module or a chip or system on chip in the master clock module. When the computing device has the function of the slave clock module described in the embodiment of the present application, the computing device may be a slave clock module or a chip or system on chip in the slave clock module.

As shown in FIG7 , the computing device may include a processor 701, a communication line 702, and a memory 704. The processor 701 and the memory 704 may be connected via the communication line 702. In an example, the processor 701 may include one or more CPUs, such as CPU0 and CPU1 in FIG7 .

As an optional implementation, the computing device includes multiple processors. For example, in addition to the processor 701 in FIG. 7 , it may also include a processor 707 .

The processor 701 may be a central processing unit (CPU), a general-purpose processor, a network processor (NP), a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic device (PLD), or any combination thereof. The processor 701 may also be other devices with processing functions, such as circuits, devices, or software modules.

The communication line 702 is used to transmit information between the various components included in the computing device.

Furthermore, the computing device may also include a memory 704. The memory 704 is used to store instructions, wherein the instructions may be computer programs.

Among them, the memory 704 can be a read-only memory (ROM) or other types of static storage devices that can store static information and/or instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and/or instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage, magnetic disk storage media or other magnetic storage devices, and the optical disc storage includes a compressed optical disc, a laser disc, an optical disc, a digital versatile disc, or a Blu-ray disc, etc.

It should be noted that the memory 704 can exist independently of the processor 701, or can be integrated with the processor 701. The memory 704 can be used to store instructions or program codes or some data, etc. The memory 704 can be located in the computing device or outside the computing device, without limitation. When the processor 701 executes the instructions stored in the memory 704, the method provided in the embodiment of the present application can be implemented.

It should be noted that the computing device may be a desktop computer, a portable computer, a network server, a mobile phone, a tablet computer, a wireless terminal, an embedded device, a chip system, or a device having a similar structure as shown in FIG7. In addition, the composition structure shown in FIG7 does not constitute a limitation on the time correction device. In addition to the components shown in FIG7, the computing device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

FIG8 shows a structural diagram of a time correction device, which is applied to a slave clock module. Each module in the device shown in FIG8 has the function of implementing the corresponding steps in FIG2 and can achieve its corresponding technical effects. The corresponding beneficial effects of the steps executed by each module can be referred to the description of the corresponding steps in FIG2, and will not be repeated here. The functions can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions. For example, the time correction device includes:

The transceiver module 810 is used to obtain multiple timestamps.

The multiple timestamps include timestamps of the moments when the master clock module and the slave clock module send and receive time messages respectively when the master clock module and the slave clock module send and receive time messages to each other at least twice. The master clock module and the slave clock module send and receive time messages through a first channel. The first channel is implemented by mapping between the Unex domain socket file installed by the master clock module and the virtual serial port installed by the slave clock module, and the virtual serial port is obtained by the master clock module starting the VirtIO driver in the slave clock module.

The processing module 820 is used to determine the time error of the slave clock module relative to the master clock module according to the multiple timestamps.

The processing module 820 is further configured to correct the system time of the slave clock module according to the time error.

In one embodiment, the transceiver module 810 is specifically configured to:

A first time message is received, where the first time message carries a first timestamp, and the first timestamp represents a time when the master clock module sends the first time message.

A second timestamp is recorded, where the second timestamp represents the time when the master clock module receives the first time message.

In response to the first time message, a second time message is sent to the master clock module, and a third time stamp is recorded, wherein the third time stamp represents the time when the slave clock module sends the second time message.

A third time message is received, where the third time message is sent by the master clock module to the slave clock module in response to the second time message, and the third time message includes a fourth timestamp, where the fourth timestamp indicates the time when the master clock module receives the second time message.

In one embodiment, the master clock module is a clock module of a master operating system, and the slave clock module is a guest operating system.

In one embodiment, a virtio serial field and an unexchange field are set in a boot configuration extensible markup language file of a slave clock module.

The virtual serial port is obtained by the master clock module by starting the VirtIO driver in the slave clock module according to the startup configuration XML file with the virtio serial field and the Unex field added. Among them, one virtual serial port corresponds to one Unex domain socket file.

In one embodiment, the processing module 820 is specifically configured to:

In one embodiment, the processing module 820 is further configured to:

After the slave clock module corrects the time of the slave clock module according to the time error, and the result output by the preset computer function indicates that the system time correction of the slave clock module fails, multiple time stamps are reacquired to recorrect the system time of the slave clock module.

FIG9 shows a structural diagram of a time correction device, which is applied to a main clock module. Each module in the device shown in FIG9 has the function of implementing the corresponding steps in FIG2 and can achieve its corresponding technical effects. The corresponding beneficial effects of the steps executed by each module can be referred to the description of the corresponding steps in FIG2, and will not be repeated here. The functions can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions. For example, the time correction device includes:

The sending module 910 is used to send at least two time messages to the slave clock module through the first channel.

The time message includes a timestamp of the time when the master clock module sends the time message; the first channel is realized by mapping the Unex domain socket file installed by the master clock module with the virtual serial port installed by the slave clock module, and the virtual serial port is obtained by the master clock module starting the VirtIO driver in the slave clock module.

In one embodiment, the apparatus further includes a receiving module 920;

A sending module 910 is used to send a first time message to the slave clock module, where the first time message carries a first timestamp, and the first timestamp indicates the time when the master clock module sends the first time message;

A receiving module 920, configured to receive a second time message from a slave clock module;

The sending module 910 is used to send a third time message to the slave clock module in response to the second time message, where the third time message includes a fourth timestamp, and the fourth timestamp indicates the time when the master clock module receives the second time message.

In one embodiment, the master clock module is a clock module of a master operating system; the slave clock module is a clock module of a guest operating system.

In one embodiment, a virtio serial field and a Unex field are set in the startup configuration extensible markup language file of the slave clock module; the virtual serial port is obtained by the master clock module by starting the VirtIO driver in the slave clock module according to the startup configuration extensible markup language file with the virtio serial field and the Unex field added; wherein, one virtual serial port corresponds to one Unex domain socket file.

FIG10 is a structural diagram of a time correction system provided in an embodiment of the present application. The time correction system is a time correction system corresponding to a time correction scenario. As shown in FIG10 , the time correction system may include:

A master clock module 110 and a slave clock module 120 .

The master clock module 110 is used to send at least two time messages to the slave clock module 120 through the first channel.

The time message includes a timestamp of the time when the master clock module 110 sends the time message. The first channel is realized by mapping between the Unex domain socket file installed by the master clock module 110 and the virtual serial port installed by the slave clock module 120. The virtual serial port is obtained by the master clock module 110 starting the VirtIO driver in the slave clock module 120.

The slave clock module 120 is configured to receive at least two time messages and record the timestamp of the moment when the at least two time messages are received, and to send at least one time message to the master clock module 110 in response to the first time message of the at least two time messages, and record the timestamp of the moment when the at least one time message is sent.

The slave clock module 120 is further used to determine the time error of the slave clock module 120 relative to the master clock module 110 according to the received timestamp and the recorded timestamp.

The slave clock module 120 is further used to correct the system time of the slave clock module 120 according to the time error.

The embodiment of the present application also provides a computer-readable storage medium. All or part of the processes in the above method embodiments can be completed by a computer program to instruct the relevant hardware, and the program can be stored in the above computer-readable storage medium. When the program is executed, it can include the processes of the above method embodiments. The computer-readable storage medium can be a terminal device of any of the above embodiments, such as: an internal storage unit including a data sending end and/or a data receiving end, such as a hard disk or memory of the terminal device. The above computer-readable storage medium can also be an external storage device of the above terminal device, such as a plug-in hard disk equipped on the above terminal device, a smart memory card (smart media card, SMC), a secure digital (secure digital, SD) card, a flash card (flash card), etc. Further, the above computer-readable storage medium can also include both the internal storage unit of the above terminal device and an external storage device. The above computer-readable storage medium is used to store the above computer program and other programs and data required by the above terminal device. The above computer-readable storage medium can also be used to temporarily store data that has been output or is to be output.

The present application also provides a computer instruction. All or part of the process in the above method embodiment can be completed by computer instructions to instruct related hardware (such as computers, processors, network devices, and terminals, etc.). The program can be stored in the above computer-readable storage medium.

The embodiment of the present application also provides a chip system. The chip system can be composed of a chip, or can include a chip and other discrete devices, without limitation. The chip system includes a processor and a transceiver, and all or part of the processes in the above method embodiment can be completed by the chip system, such as the chip system can be used to implement the functions performed by the master clock module in the above method embodiment, or to implement the functions performed by the slave clock module in the above method embodiment.

In one possible design, the above-mentioned chip system also includes a memory, which is used to store program instructions and/or data. When the chip system is running, the processor executes the program instructions stored in the memory so that the chip system performs the functions performed by the main clock module in the above-mentioned method embodiment or performs the functions performed by the slave clock module in the above-mentioned method embodiment.

In the embodiments of the present application, the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

In the embodiments of the present application, the memory may be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), etc., or a volatile memory (volatile memory), such as a random-access memory (RAM). The memory is any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory in the embodiments of the present application may also be a circuit or any other device that can realize a storage function, for storing instructions and/or data.

It should be noted that the terms "first" and "second" in the specification, claims and drawings of the present application are used to distinguish different objects rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

It should be understood that in the embodiments of the present application, "at least one (item)" refers to one or more, "multiple" refers to two or more, "at least two (items)" refers to two or three and more than three, and "and/or" is used to describe the association relationship of the associated objects, indicating that there can be three relationships. For example, "A and/or B" can represent: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character "/" generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following (items)" or similar expressions refers to any combination of these items, including any combination of single items (items) or plural items (items). For example, at least one of a, b or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple. It should be understood that in the embodiments of the present application, "B corresponding to A" means that B is associated with A. For example, B can be determined based on A. It should also be understood that determining B based on A does not mean determining B based only on A, but B can also be determined based on A and/or other information. The “connection” mentioned in the examples refers to various connection modes such as direct connection or indirect connection to achieve communication between devices, and the embodiments of the present application do not impose any limitation on this.

Unless otherwise specified, the "transmission" (transmit/transmission) appearing in the embodiments of the present application refers to bidirectional transmission, including sending and/or receiving actions. Specifically, the "transmission" in the embodiments of the present application includes the sending of data, the receiving of data, or the sending of data and the receiving of data. In other words, the data transmission here includes uplink and/or downlink data transmission. Data may include channels and/or signals, uplink data transmission is uplink channel and/or uplink signal transmission, and downlink data transmission is downlink channel and/or downlink signal transmission. The "network" and "system" appearing in the embodiments of the present application express the same concept, and the time correction system is a communication network.

Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit. If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device, such as: a single-chip microcomputer, a chip, etc., or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, ROM, RAM, disks, or optical disks.

The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application shall be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

A time correction method, characterized in that it is applied to a slave clock module of a computing device, wherein the computing device also includes a master clock module, and the method comprises:

Acquire multiple timestamps, the multiple timestamps including timestamps of the moments when the master clock module and the slave clock module respectively send and receive the time messages when the master clock module and the slave clock module send and receive the time messages to each other at least twice; the master clock module and the slave clock module send and receive time messages through a first channel; the first channel is realized by mapping between the Unex domain socket file installed by the master clock module and the virtual serial port installed by the slave clock module, and the virtual serial port is obtained by the master clock module starting the VirtIO driver in the slave clock module;

Determining a time error of the slave clock module relative to the master clock module according to the multiple timestamps;

The system time of the slave clock module is corrected according to the time error.
The time correction method according to claim 1, wherein obtaining multiple timestamps comprises:

receiving a first time message, the first time message carrying a first timestamp, the first timestamp representing the time when the master clock module sends the first time message;

Recording a second timestamp, where the second timestamp represents the time when the master clock module receives the first time message;

In response to the first time message, send a second time message to the master clock module, and record a third timestamp, wherein the third timestamp indicates the time when the slave clock module sends the second time message;

A third time message is received, where the third time message is sent by the master clock module to the slave clock module in response to the second time message, and the third time message includes a fourth timestamp, where the fourth timestamp indicates the moment when the master clock module receives the second time message.
The time correction method according to claim 1 or 2 is characterized in that the master clock module is a clock module of a master operating system, and the slave clock module is a clock module in a slave operating system, wherein the master operating system is the operating system of the computing device, and the slave operating system is the operating system of a virtual machine running on the computing device.
The time correction method according to any one of claims 1-3 is characterized in that a virtio serial field and a Unex field are set in the startup configuration extensible markup language file of the slave clock module; the virtual serial port is obtained by the master clock module by starting the VirtIO driver in the slave clock module according to the startup configuration extensible markup language file to which the virtio serial field and the Unex field are added; wherein one virtual serial port corresponds to one Unex domain socket file.
The time correction method according to any one of claims 1 to 4, characterized in that the step of correcting the system time of the slave clock module according to the time error comprises:

The time error is input into a preset computer function to correct the system time of the slave clock module.
The time correction method according to claim 5, characterized in that after correcting the time of the slave clock module according to the time error, the method further comprises:

When the result output by the preset computer function indicates that the system time correction of the slave clock module fails, a plurality of time stamps are reacquired to recorrect the system time of the slave clock module.
A time correction method, characterized in that it is applied to a master clock module of a computing device, wherein the computing device also includes a slave clock module, and the method comprises:

At least two timestamps are sent to the slave clock module through a first channel, and the timestamps are used to correct the system time of the slave clock module that obtains the at least two timestamps; the at least two timestamps include a timestamp representing the moment when the master clock module sends a time message to the slave clock module, and a timestamp representing the moment when the master clock module receives a time message from the slave clock module; the first channel is realized by mapping between the Unex domain socket file installed by the master clock module and the virtual serial port installed by the slave clock module, and the virtual serial port is obtained by the master clock module starting the VirtIO driver in the slave clock module.
The time correction method according to claim 7, characterized in that the sending of at least two timestamps to the slave clock module through the first channel comprises:

Sending a first time message to the slave clock module, where the first time message carries a timestamp indicating the time when the master clock module sends the first time message to the slave clock module;

Receive a second time message from the slave clock module, wherein the second time message is a time message received by the slave clock module in response to the A time message sent by a first time message to the master clock module;

In response to the second time message, a third time message is sent to the slave clock module, the third time message including a timestamp indicating a time when the master clock module receives the second time message.
The time correction method according to claim 7 or 8 is characterized in that the master clock module is a clock module of a master operating system, and the slave clock module is a clock module in a slave operating system, wherein the master operating system is the operating system of the computing device, and the slave operating system is the operating system of a virtual machine running on the computing device.
The time correction method according to any one of claims 7 to 9 is characterized in that a virtio serial field and a Unex field are set in the startup configuration extensible markup language file of the slave clock module; the virtual serial port is obtained by the master clock module by starting the VirtIO driver in the slave clock module according to the startup configuration extensible markup language file to which the virtio serial field and the Unex field are added; wherein one virtual serial port corresponds to one Unex domain socket file.
A time correction device, characterized in that it is applied to a slave clock module of a computing device, the computing device also includes a master clock module, and the device includes:

A transceiver module, used for obtaining a plurality of timestamps, wherein the plurality of timestamps include timestamps of the moments when the master clock module and the slave clock module respectively send and receive the time messages when the master clock module and the slave clock module send and receive the time messages to each other at least twice; the master clock module and the slave clock module send and receive time messages through a first channel; the first channel is realized by mapping between a Unex domain socket file installed by the master clock module and a virtual serial port installed by the slave clock module, and the virtual serial port is obtained by the master clock module starting a VirtIO driver in the slave clock module;

A processing module, configured to determine a time error of the slave clock module relative to the master clock module according to the multiple timestamps;

The processing module is further used to correct the system time of the slave clock module according to the time error.
The time correction device according to claim 11, characterized in that the transceiver module is specifically used to:

receiving a first time message, the first time message carrying a first timestamp, the first timestamp representing the time when the master clock module sends the first time message;

Recording a second timestamp, where the second timestamp represents the time when the master clock module receives the first time message;

In response to the first time message, send a second time message to the master clock module, and record a third timestamp, wherein the third timestamp indicates the time when the slave clock module sends the second time message;

A third time message is received, where the third time message is sent by the master clock module to the slave clock module in response to the second time message, and the third time message includes a fourth timestamp, where the fourth timestamp indicates the time when the master clock module receives the second time message.
The time correction device according to claim 11 or 12 is characterized in that the master clock module is a clock module of a master operating system, and the slave clock module is a clock module in a slave operating system, wherein the master operating system is the operating system of the computing device, and the slave operating system is the operating system of a virtual machine running on the computing device.
The time correction device according to any one of claims 11 to 13, characterized in that a virtio serial field and a unexus field are set in the startup configuration extensible markup language file of the slave clock module;

The virtual serial port is obtained by the master clock module by starting the VirtIO driver in the slave clock module according to the startup configuration extensible markup language file to which the virtio serial field and the Unex field are added; wherein, one virtual serial port corresponds to one Unex domain socket file.
The time correction device according to any one of claims 11 to 14, characterized in that the processing module is specifically used to:

The time error is input into a preset computer function to correct the system time of the slave clock module.
The time correction device according to claim 15, characterized in that the processing module is further used for:

After the slave clock module corrects the time of the slave clock module according to the time error, and the result output by the preset computer function indicates that the system time correction of the slave clock module fails, the time of the slave clock module is re-corrected.
A time correction device, characterized in that it is applied to a master clock module of a computing device, the computing device also includes a slave clock module, and the device includes:

A sending module is used to send at least two timestamps to the slave clock module through a first channel, and the timestamps are used to correct the system time of the slave clock module that obtains the at least two timestamps; the at least two timestamps include a timestamp representing the moment when the master clock module sends a time message to the slave clock module, and a timestamp representing the moment when the master clock module receives a time message from the slave clock module; the first channel includes a mapping between a Unex domain socket file installed by the master clock module and a virtual serial port installed by the slave clock module, and the virtual serial port is obtained by the master clock module starting the VirtIO driver in the slave clock module.
The time correction device according to claim 17, characterized in that the device further comprises a receiving module;

The sending module is used to send a first time message to the slave clock module, where the first time message carries a timestamp representing the moment when the master clock module sends the first time message to the slave clock module;

The receiving module is used to receive a second time message from the slave clock module, where the second time message is a time message sent by the slave clock module to the master clock module in response to the first time message;

The sending module is used to send a third time message to the slave clock module in response to the second time message, and the third time message includes a timestamp representing the moment when the master clock module receives the second time message.
The time correction device according to claim 17 or 18 is characterized in that the master clock module is a clock module of a master operating system; and the slave clock module is a clock module of a guest operating system.
The time correction device according to any one of claims 17 to 19, characterized in that a virtio serial field and a unexus field are set in the startup configuration extensible markup language file of the slave clock module;

The virtual serial port is obtained by the master clock module by starting the VirtIO driver in the slave clock module according to the startup configuration extensible markup language file to which the virtio serial field and the Unex field are added; wherein, one virtual serial port corresponds to one Unex domain socket file.
A time correction device, characterized in that the time correction device comprises a processor, and the processor is used to support the time correction device to execute the method as described in any one of claims 1-10.
A computer-readable storage medium, characterized in that the computer-readable storage medium stores computer instructions, and when the computer instructions are executed, the method according to any one of claims 1 to 10 is executed.
A time correction system, characterized in that the time correction system comprises: a master clock module and a slave clock module;

The master clock module is used to send at least two time messages to the slave clock module through the first channel; the time message includes a timestamp of the moment when the master clock module sends the time message; the first channel is realized by mapping between the Unex domain socket file installed by the master clock module and the virtual serial port installed by the slave clock module, and the virtual serial port is obtained by the master clock module starting the VirtIO driver in the slave clock module;

The slave clock module is used to receive the at least two time messages and record the timestamp of the moment when the at least two time messages are received; and in response to the first time message of the at least two time messages, send at least one time message to the master clock module, and record the timestamp of the moment when the at least one time message is sent;

The slave clock module is further used to determine the time error of the slave clock module relative to the master clock module according to the received timestamp and the recorded timestamp;

The slave clock module is further used to correct the system time of the slave clock module according to the time error.