CN105703865A - Method and device for automatically acquiring unsymmetrical delay of 1588 links - Google Patents
Method and device for automatically acquiring unsymmetrical delay of 1588 links Download PDFInfo
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- CN105703865A CN105703865A CN201410687456.XA CN201410687456A CN105703865A CN 105703865 A CN105703865 A CN 105703865A CN 201410687456 A CN201410687456 A CN 201410687456A CN 105703865 A CN105703865 A CN 105703865A
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Abstract
The present invention provides a method and device for automatically acquiring unsymmetrical delay of 1588 links. The method includes the following steps that: a 1588 time synchronization protocol is operated on a master clock and a slave clock separately, a first group of timestamps is obtained, a 1588 transmitting link and receiving link are set between the master clock and the slave clock; a reversion protocol is operated on the master clock and the slave clock separately, the 1588 receiving link and the 1588 transmitting link at the master clock side and the slave clock side are reversed; the 1588 time synchronization protocol is operated on the master clock and the slave clock, a second group of timestamps is obtained; and the unsymmetrical delay of the 1588 transmitting link and receiving link between the master clock and the slave clock is calculated according to the obtained first group of timestamps and the second group of timestamps. According to the method and device of the invention, the reversion protocol is operated, so that effective conduction of a reversion process can be ensured, a situation that the links cannot be restored after being reversed can be prevented, and reliability can be improved, and at the same time, a large quantity of labor cost and high instrument test cost can be saved, time can be saved, and efficiency can be improved.
Description
Technical field
The present invention relates to communication technical field, particularly relate to method and the device of a kind of automatic acquisition 1588 link asymmetry time delay。
Background technology
Along with the high speed development of communication network, 1588 time synchronization protocols are more and more applied in communication network。Providing the method how realizing time synchronized in 1588 agreements, a basic premise condition is that physical link is symmetrical。But in real network, inevitably there is asymmetric problem, namely the transmission delay of receiving-transmitting chain is unequal, 1588 time synchronization protocols are then used to calculate time deviation, the asymmetry error amount of half does not calculate in deviation value, time deviation is made to can not get correct correction, thus reducing time synchronized quality。When asymmetry time delay is serious, the time of even resulting in cannot synchronize。
What solve asymmetry latency issue challenge is how acquisition time delay。Obtain asymmetry time delay at present, the method being generally adopted artificial acquisition。This method needs to be undertaken by expensive instrument and meter, for instance: time synchronization tester, OTDR (optical time domain reflectometer), oscillograph etc., not only workload is big, inefficiency, and needs professional to operate, and pertinent instruments carries inconvenience。Therefore manually obtain time-delay method and be difficult to popularity enforcement。
In prior art, it was also proposed that understand the scheme of symmetry latency issue by no means, for instance:
Utilize the mode correcting synchronisation errors of reverse circuit, but yet suffer from some problem: during reverse circuit, how to consult between two equipment？How to ensure that flow process effectively carries out？When there are abnormal conditions, how to ensure that reverse circuit recovers original state？If these problems can not get solving, then the reliability of this scheme will be unable to ensure, it is impossible to effectively implements in actual environment。
Utilize light loopback device and single fiber bi-directional co-wavelength optical module, it is achieved the calculating of time error。This scheme needs to install special device at light path two ends, and exploitativeness is poor, and does not support that transmission link is the situation of circuit。
Utilize 1:2 beam splitter and two pairs of receipts light outlets, it is achieved the calculating of time error。But beam splitter is relatively big to the decay of optical signal, does not support that transmission link is the situation of circuit equally。
To sum up, a kind of low cost is needed badly and significantly more efficient scheme solves the problem of asymmetry time delay in 1588 links。
Summary of the invention
It is an object of the invention to provide a kind of method of automatic acquisition 1588 link asymmetry time delay and device, by running turning protocol, ensure effectively carrying out of reversed process, it is prevented that situation about cannot recover after switching, improve the reliability obtaining 1588 link asymmetry time delays。
In order to achieve the above object, a kind of method that the invention provides automatic acquisition 1588 link asymmetry time delay, including:
Run 1588 time synchronization protocols at master clock with from clock respectively, obtain first group of timestamp, wherein master clock and be provided with 1588 receiving-transmitting chains between clock；
Respectively at master clock with from clock runs turning protocol, switch master clock side 1588 and receive link and 1588 and send links, and switch and receive link and 1588 from clock side 1588 and send links；
Run 1588 time synchronization protocols at master clock with from clock respectively, obtain second group of timestamp；
According to the first group of timestamp obtained and second group of timestamp, calculate master clock and from 1588 receiving-transmitting chain asymmetry time delays between clock。
Wherein, run 1588 time synchronization protocols at master clock with from clock respectively, obtain first group of timestamp, specifically include:
Send synchronization Sync (a) message by master clock to from clock, obtain master clock and send the time stamp T synchronizing Sync (a) message1With the time stamp T receiving synchronization Sync (a) message from clock2；
By from time clockwise master clock forward delay interval request Delay_req (a) message, obtain from clock forward delay interval ask Delay_req (a) message time stamp T3With the time stamp T that master clock reception delay asks Delay_req (a) message4。
Wherein, respectively at master clock with from clock runs turning protocol, switch master clock side 1588 and receive link and 1588 and send links, and switch and receive link and 1588 from clock side 1588 and send links, specifically include:
When master clock enters and switches readiness, timing switches preparation request message to from clock transmission；
Switch preparation request message according to what receive from clock, respond to master clock and switch preparation and complete message and readiness is switched in entrance；
Complete message according to the preparation of switching that master clock receives, stop switching preparation request message to sending from clock, and switch the receiving-transmitting chain of master clock, send Diagnosis of Links message to from clock；
In the first limiting time, do not receive Diagnosis of Links message from clock, then proceed to change to from the receiving-transmitting chain of clock；
In the second limiting time, after receiving-transmitting chain is switched, receive Diagnosis of Links message from clock, message will have been switched and sent to master clock。
Wherein, respectively at master clock with from 1588 time synchronization protocols clock, obtain second group of timestamp, specifically include:
Send synchronization Sync (b) message by master clock to from clock, obtain master clock and send the timestamp synchronizing Sync (b) messageWith the timestamp receiving synchronization Sync (b) message from clock
By from time clockwise master clock forward delay interval request Delay_req (b) message, obtain from clock forward delay interval ask Delay_req (b) message timestampWith the timestamp that master clock reception delay asks Delay_req (b) message
Wherein, according to the first group of timestamp obtained and second group of timestamp, calculate master clock and from 1588 receiving-transmitting chain asymmetry time delays between clock, specifically include:
By time stamp T2With time stamp T1Subtract each other, it is thus achieved that the very first time is poor；
By time stamp T4With time stamp T3Subtract each other, it is thus achieved that the second time difference；
By timestampWith timestampSubtract each other, it is thus achieved that the 3rd time difference；
By timestampWith timestampSubtract each other, it is thus achieved that the 4th time difference；
Carry out computing by the very first time obtained is poor, the second time difference, the 3rd time difference and the 4th time difference, obtain master clock and from 1588 receiving-transmitting chain asymmetry time delays between clock。
The embodiment of the present invention additionally provides the device of a kind of automatic acquisition 1588 link asymmetry time delay, including:
Turning protocol processing module, for running turning protocol at master clock with from clock respectively；
Switch module, for switching master clock side and the 1588 reception links from clock side and 1588 transmission links according to the control of turning protocol processing module；
1588 protocol process module, run 1588 time synchronization protocols at master clock with from clock for running in turning protocol processing module respectively before and after turning protocol, obtain first group of timestamp and second group of timestamp；
Delay process module, for according to the acquired first group of timestamp of 1588 protocol process module and second group of timestamp, calculates master clock and from 1588 receiving-transmitting chain asymmetry time delays between clock。
Wherein, turning protocol processing module includes: for running the first turning protocol processing unit of turning protocol on master clock and for running the second turning protocol processing unit of turning protocol from clock；
Switch module to include: receive the first switch unit of link and 1588 transmission links and for switching from the 1588 of clock side the second switch units receiving links and 1588 transmission links according to the control of the second turning protocol processing unit for switching the 1588 of master clock side according to the control of the first turning protocol processing unit；
Delay process module includes: for according to first group of timestamp and second group of timestamp, calculate the first delay process unit of master clock side 1588 receiving-transmitting chain asymmetry time delay and for according to first group of timestamp and second group of timestamp, calculating the second delay process unit from clock side 1588 receiving-transmitting chain asymmetry time delay。
Wherein, 1588 protocol process module include: the one 1588 protocol processing unit and the 2nd 1588 protocol processing unit, wherein
Master clock sends Sync (a) message to from clock by the one 1588 protocol processing unit, and records transmission time stamp T1, after receiving Sync (a) message from clock, the 2nd 1588 protocol processing unit record receive time stamp T2；Master clock is sent by the one 1588 protocol processing unit and carries time stamp T1Follow_up (a) message to from clock, after receiving Follow_up (a) message from clock, the 2nd 1588 protocol processing unit obtain time stamp T1；Send Delay_req (a) message to master clock from clock by the 2nd 1588 protocol processing unit, and record transmission time stamp T3, after master clock receives Delay_req (a) message, the one 1588 protocol processing unit record receive time stamp T4；Master clock is sent by the one 1588 protocol processing unit and carries time stamp T4Delay_resp (a) message to from clock, after receiving Delay_resp (a) message from clock, the 2nd 1588 protocol processing unit obtain time stamp T4, time stamp T1, time stamp T2, time stamp T3And time stamp T4Belong to first group of timestamp；
Master clock sends Sync (b) message to from clock by the one 1588 protocol processing unit, and records transmission timestampAfter receiving Sync (b) message from clock, the 2nd 1588 protocol processing unit record receive timestampMaster clock is sent by the one 1588 protocol processing unit and carries timestampFollow_up (b) message to from clock, after receiving Follow_up (b) message from clock, the 2nd 1588 protocol processing unit obtain timestampSend Delay_req (b) message to master clock from clock by the 2nd 1588 protocol processing unit, and record transmission timestampAfter master clock receives Delay_req (b) message, the one 1588 protocol processing unit record receive timestampMaster clock is sent by the one 1588 protocol processing unit and carries timestampDelay_resp (b) message to from clock, after receiving Delay_resp (b) message from clock, the 2nd 1588 protocol processing unit obtain timestampTimestampTimestampTimestampAnd timestampBelong to second group of timestamp。
Wherein, the first switch unit is internal or external at master clock, and the second switch unit is internal or external at from clock。
Wherein, the first delay process unit or the second delay process unit include:
First obtains subelement, for by time stamp T2With time stamp T1Subtract each other, it is thus achieved that the very first time is poor；
Second obtains subelement, for by time stamp T4With time stamp T3Subtract each other, it is thus achieved that the second time difference；
3rd obtains subelement, for by timestampWith timestampSubtract each other, it is thus achieved that the 3rd time difference；
4th obtains subelement, for by timestampWith timestampSubtract each other, it is thus achieved that the 4th time difference；
Computing subelement, for obtain the very first time is poor, the second time difference, the 3rd time difference and the 4th time difference carry out computing, obtain master clock and from 1588 receiving-transmitting chain asymmetry time delays between clock。
The invention has the beneficial effects as follows: by running turning protocol, ensure that reversed process effectively carries out, it is prevented that situation about cannot recover after switching occurs, improve the reliability obtaining 1588 link asymmetry time delays；Compared with traditional artificial acquisition scheme, it is not necessary to professional participates in, it is not necessary to by special test instrunment, a large amount of cost of labor and great number test instrunment cost can be saved, and save the acquisition time, improve efficiency。
Accompanying drawing explanation
Fig. 1 represents that the embodiment of the present invention obtains the method step flow chart of 1588 link asymmetry time delays automatically；
Fig. 2 represents that the embodiment of the present invention obtains the flow chart of steps obtaining first group of timestamp in the method for 1588 link asymmetry time delays automatically；
Fig. 3 represents that the embodiment of the present invention obtains automatically and obtains first group of timestamp in the method for 1588 link asymmetry time delays and realize process schematic；
Fig. 4 represents that the embodiment of the present invention obtains automatically and runs turning protocol flow chart of steps in the method for 1588 link asymmetry time delays；
Fig. 5 embodiment of the present invention automatically obtains master clock in the method for 1588 link asymmetry time delays and runs turning protocol flow chart；
Fig. 6 embodiment of the present invention automatically obtains in the method for 1588 link asymmetry time delays and runs turning protocol flow chart from clock；
Fig. 7 represents that the embodiment of the present invention obtains the flow chart of steps obtaining second group of timestamp in the method for 1588 link asymmetry time delays automatically；
Fig. 8 represents that the embodiment of the present invention obtains automatically and obtains second group of timestamp in the method for 1588 link asymmetry time delays and realize process schematic；
Fig. 9 represents that the embodiment of the present invention obtains in the method for 1588 link asymmetry time delays automatically and calculates 1588 link asymmetry delaying step flow charts；
Figure 10 represents that the embodiment of the present invention obtains the built-in master-salve clock system embodiment schematic diagram of switch unit in the device of 1588 link asymmetry time delays automatically；
Figure 11 represents that the embodiment of the present invention obtains the external master-salve clock system embodiment schematic diagram of switch unit in the device of 1588 link asymmetry time delays automatically；
Figure 12 represents that the embodiment of the present invention obtains turning protocol processing module block diagram in the device of 1588 link asymmetry time delays automatically；
Figure 13 represents that the embodiment of the present invention obtains in the device of 1588 link asymmetry time delays automatically and switches module frame chart；
Figure 14 represents that the embodiment of the present invention obtains in the device of 1588 link asymmetry time delays automatically and utilizes photoswitch to realize the embodiment schematic diagram of switch unit switch function；
Figure 15 represents that the embodiment of the present invention obtains in the device of 1588 link asymmetry time delays automatically and utilizes relay to realize the embodiment schematic diagram of switch unit switch function；
Figure 16 represents that the embodiment of the present invention obtains the embodiment schematic diagram utilizing circuit realiration switch unit switch function in the device of 1588 link asymmetry time delays automatically；
Figure 17 (a) and Figure 17 (b) represent that the embodiment of the present invention automatically obtains master-salve clock switch unit in the device of 1588 link asymmetry time delays and switches receiving-transmitting chain and realize process schematic；
Figure 18 represents that the embodiment of the present invention obtains 1588 protocol process module block diagrams in the device of 1588 link asymmetry time delays automatically；
Figure 19 represents that the embodiment of the present invention obtains delay process module frame chart in the device of 1588 link asymmetry time delays automatically；
Figure 20 represents that the embodiment of the present invention obtains delay process unit block diagram in the device of 1588 link asymmetry time delays automatically。
Detailed description of the invention
For making the technical problem to be solved in the present invention, technical scheme and advantage clearly, it is described in detail below in conjunction with the accompanying drawings and the specific embodiments。
The present invention is directed to and prior art adopts artificial acquisition in the relatively costly and prior art that 1588 link asymmetry time delay schemes need professional to cause by special test instrunment automatically obtain 1588 links
The problem of exploitativeness difference in the scheme of asymmetry time delay, provide method and the device of a kind of automatic acquisition 1588 link asymmetry time delay, by running turning protocol, ensure effectively carrying out of reversed process, prevent situation about cannot recover after switching, improve the reliability obtaining 1588 link asymmetry time delays。
As it is shown in figure 1, a kind of method that the embodiment of the present invention provides automatic acquisition 1588 link asymmetry time delay, including:
Step S100, run 1588 time synchronization protocols at master clock with from clock respectively, obtain first group of timestamp, wherein master clock and be provided with 1588 receiving-transmitting chains between clock；
Step S200, respectively at master clock with from clock runs turning protocol, switch master clock side 1588 and receive link and 1588 and send links, and switch and receive link and 1588 from clock side 1588 and send links；
Step S300, run 1588 time synchronization protocols at master clock with from clock respectively, obtain second group of timestamp；
Step S400, according to the first group of timestamp obtained and second group of timestamp, calculate master clock and from 1588 receiving-transmitting chain asymmetry time delays between clock。
Concrete, running before turning protocol, by master clock and from clock runs 1588 time synchronization protocols obtain master clocks to send from clock synchronize Sync (a) message and from time clockwise master clock forward delay interval request Delay_req (a) message first group of timestamp；After running turning protocol, by master clock and from clock runs 1588 time synchronization protocols obtain master clocks to from clock send synchronize Sync (b) message and from time clockwise master clock forward delay interval request Delay_req (b) message second group of timestamp, according to first group of timestamp and second group of timestamp, in conjunction with the formula calculating 1588 link asymmetry time delays, draw master clock and from 1588 receiving-transmitting chain asymmetry time delays between clock。By running turning protocol, ensure effectively carrying out of reversed process, it is prevented that situation about cannot recover after switching, improve the reliability obtaining 1588 link asymmetry time delays。
In the above embodiment of the present invention, as in figure 2 it is shown, step S100 includes:
Step S101, by master clock to from clock send synchronize Sync (a) message, obtain master clock send synchronize Sync (a) message time stamp T1With the time stamp T receiving synchronization Sync (a) message from clock2；
Step S102, by from time clockwise master clock forward delay interval request Delay_req (a) message, obtain from clock forward delay interval ask Delay_req (a) message time stamp T3With the time stamp T that master clock reception delay asks Delay_req (a) message4。
Concrete, obtain the flow process of first group of timestamp as shown in Figure 3: send Sync (a) message to from clock by master clock, and record transmission time stamp T1, after receiving message from clock, record receives time stamp T2；Then master clock sends and carries time stamp T1Follow_up (a) message to from clock, after receiving message from clock, time stamp T can be obtained1；By sending Delay_req (a) message to master clock from clock, and record transmission time stamp T3, after master clock receives message, record receives time stamp T4；Then master clock sends and carries time stamp T4Delay_req (a) message to from clock, after receiving message from clock, time stamp T can be obtained4。Just required first group timestamp can be being obtained from clock side。
In the above embodiment of the present invention, as shown in Figure 4, step S200 includes:
Step S201, master clock enter switch readiness time, timing to from clock send switch preparation request message；
Step S202, according to switching preparation request message from what clock received, respond to master clock and switch preparation and complete message and readiness is switched in entrance；
Step S203, the preparation of switching received according to master clock complete message, stop switching preparation request message to sending from clock, and switch the receiving-transmitting chain of master clock, send Diagnosis of Links message to from clock；
Step S204, in the first limiting time, do not receive Diagnosis of Links message from clock, then proceed to change to from the receiving-transmitting chain of clock；
Step S205, in the second limiting time, after receiving-transmitting chain is switched, receive Diagnosis of Links message from clock, message will have been switched and sent to master clock。
Concrete, as shown in Figure 5 and Figure 6, after master clock enters and switches readiness, timing switches preparation request message to from clock transmission, judge whether to receive from clock and switch preparation request message, if received, then respond and switch preparation and complete message to master clock, and enter switch readiness, otherwise exit flow process。
Master clock judges whether to receive to be switched preparation and completes message, if received, then stop transmission and switch preparation request message, and switch the receiving-transmitting chain of master clock side, send Diagnosis of Links message to from clock, switch preparation complete message if do not received in limiting time, then stop transmission and switch preparation request message, transmission switches cancellation message to from clock, and stopping is switched, report and alarm。
Judge whether do not receive Diagnosis of Links message in limiting time and switch cancellation message from clock, if do not received, determine that master clock side receiving-transmitting chain is switched, then switch from clock side receiving-transmitting chain, if receiving Diagnosis of Links message from clock or switching cancellation message, then stop switching, report and alarm；
After having switched from clock side receiving-transmitting chain, judge whether Diagnosis of Links message can be received, if can receive, then send and switched message to master clock, reported and switched；If not receiving Diagnosis of Links message in limiting time, then again switch from clock side receiving-transmitting chain, report and alarm；
Master clock judges whether to receive has switched message, if received, then having reported and has switched, having switched message if do not received in limiting time, then again switch master clock side receiving-transmitting chain, report and alarm。
Switching 1588 receiving-transmitting chains is completed through running above-mentioned turning protocol。
In the above embodiment of the present invention, as it is shown in fig. 7, step S300 includes:
Step S301, by master clock to from clock send synchronize Sync (b) message, obtain master clock send synchronize Sync (b) message timestampWith the timestamp receiving synchronization Sync (b) message from clock
Step S302, by from time clockwise master clock forward delay interval request Delay_req (b) message, obtain from clock forward delay interval ask Delay_req (b) message timestampWith the timestamp that master clock reception delay asks Delay_req (b) message
Concrete, obtain the flow process of second group of timestamp as shown in Figure 8: send Sync (b) message to from clock by master clock, and record transmission timestampAfter receiving message from clock, record receives timestampThen master clock sends and carries timestampFollow_up (b) message to from clock, after receiving message from clock, timestamp can be obtainedBy sending Delay_req (b) message to master clock 102 from clock, and record transmission timestampAfter master clock receives message, record receives timestampThen master clock sends and carries timestampDelay_resp (b) message to from clock, after receiving message from clock, timestamp can be obtainedJust required second group timestamp can be being obtained from clock side。
In the above embodiment of the present invention, as it is shown in figure 9, step S400 specifically includes:
Step S401, by time stamp T2With time stamp T1Subtract each other, it is thus achieved that the very first time is poor；
Step S402, by time stamp T4With time stamp T3Subtract each other, it is thus achieved that the second time difference；
Step S403, by timestampWith timestampSubtract each other, it is thus achieved that the 3rd time difference；
Step S404, by timestampWith timestampSubtract each other, it is thus achieved that the 4th time difference；
Step S405, carry out computing by poor, the second time difference, the 3rd time difference to the very first time obtained and the 4th time difference, obtain master clock and from 1588 receiving-transmitting chain asymmetry time delays between clock。
According to the first group of timestamp obtained and second group of timestamp, calculating 1588 link asymmetry delay values, specific formula for calculation is:
In order to better realize above-mentioned purpose, the embodiment of the present invention also provides for the device of a kind of automatic acquisition 1588 link asymmetry time delay, as shown in Figure 10 and Figure 11, and including:
Turning protocol processing module 10, for running turning protocol at master clock with from clock respectively, as shown in figure 12, turning protocol processing module 10 includes the first turning protocol processing unit 110 for running turning protocol on master clock and for running the second turning protocol processing unit 120 of turning protocol from clock；
Switch module 20, for switching master clock side and the 1588 reception links from clock side and 1588 transmission links according to the control of turning protocol processing module 10, as shown in figure 13, switch module 20 to include: receive the first switch unit 210 of link and 1588 transmission links and for switching from the 1588 of clock side the second switch units 220 receiving links and 1588 transmission links according to the control of the second turning protocol processing unit 120 for switching the 1588 of master clock side according to the control of the first turning protocol processing unit 110。As illustrated in figures 14-16, respectively utilizing the embodiment schematic diagram of photoswitch, relay and circuit realiration the first switch unit 210 and the second switch unit 220 switch function, the first switch unit 210 that Figure 17 (a), (b) are master clock side and the second switch unit 220 from clock side are switched receiving-transmitting chain and are realized process schematic。
1588 protocol process module 30, run 1588 time synchronization protocols at master clock with from clock for running in turning protocol processing module 10 respectively before and after turning protocol, obtain first group of timestamp and second group of timestamp；As shown in figure 18,1588 protocol process module 30 include: the one 1588 protocol processing unit the 310 and the 2nd 1588 protocol processing unit 320, wherein
Master clock sends Sync (a) message to from clock by the one 1588 protocol processing unit 310, and records transmission time stamp T1, after receiving Sync (a) message from clock, the 2nd 1588 protocol processing unit 320 record reception time stamp T2；Master clock is sent by the one 1588 protocol processing unit 310 and carries time stamp T1Follow_up (a) message to from clock, after receiving Follow_up (a) message from clock, the 2nd 1588 protocol processing unit 320 obtain time stamp T1；Send Delay_req (a) message to master clock from clock by the 2nd 1588 protocol processing unit 320, and record transmission time stamp T3, master clock is recorded reception time stamp T by the one 1588 protocol processing unit 310 after receiving Delay_req (a) message4；Master clock is sent by the one 1588 protocol processing unit 310 and carries time stamp T4Delay_resp (a) message to from clock, after receiving Delay_resp (a) message from clock, the 2nd 1588 protocol processing unit 320 obtain time stamp T4, time stamp T1, time stamp T2, time stamp T3And time stamp T4Belong to first group of timestamp；
Master clock sends Sync (b) message to from clock by the one 1588 protocol processing unit 310, and records transmission timestampAfter receiving Sync (b) message from clock, the 2nd 1588 protocol processing unit 320 record reception timestampMaster clock is sent by the one 1588 protocol processing unit 310 and carries timestampFollow_up (b) message to from clock, after receiving Follow_up (b) message from clock, the 2nd 1588 protocol processing unit 320 obtain timestampSend Delay_req (b) message to master clock from clock by the 2nd 1588 protocol processing unit 320, and record transmission timestampMaster clock is recorded reception timestamp by the one 1588 protocol processing unit 310 after receiving Delay_req (b) messageMaster clock is sent by the one 1588 protocol processing unit 310 and carries timestampDelay_resp (b) message to from clock, after receiving Delay_resp (b) message from clock, the 2nd 1588 protocol processing unit 320 obtain timestampTimestampTimestampTimestampAnd timestampBelong to second group of timestamp。
Delay process module 40, for according to the acquired first group of timestamp of 1588 protocol process module 30 and second group of timestamp, calculates master clock and from 1588 receiving-transmitting chain asymmetry time delays between clock。As shown in figure 19, delay process module 40 includes: for according to first group of timestamp and second group of timestamp, calculate the first delay process unit 410 of master clock side 1588 receiving-transmitting chain asymmetry time delay and for according to first group of timestamp and second group of timestamp, calculating the second delay process unit 420 from clock side 1588 receiving-transmitting chain asymmetry time delay。
In the above embodiment of the present invention, the first switch unit 210 is internal or external at master clock, and the second switch unit 220 is internal or external at from clock。
In the above embodiment of the present invention, as shown in figure 20, the first delay process unit 410 or the second delay process unit 420 include:
First obtains subelement 411, for by time stamp T2With time stamp T1Subtract each other, it is thus achieved that the very first time is poor；
Second obtains subelement 412, for by time stamp T4With time stamp T3Subtract each other, it is thus achieved that the second time difference；
3rd obtains subelement 413, for by timestampWith timestampSubtract each other, it is thus achieved that the 3rd time difference；
4th obtains subelement 414, for by time stamp T4With timestampSubtract each other, it is thus achieved that the 4th time difference；
Computation delay processes subelement 415, for obtain the very first time is poor, the second time difference, the 3rd time difference and the 4th time difference carry out computing, obtain master clock and from 1588 receiving-transmitting chain asymmetry time delays between clock。
The embodiment of the present invention obtains the method for 1588 link asymmetry time delays automatically by running turning protocol, ensure effectively carrying out of reversed process, prevent situation about cannot recover after switching, improve the reliability obtaining 1588 link asymmetry time delays, the method participates in without professional simultaneously, it is not necessary to by special test instrunment, can save a large amount of cost of labor and great number test instrunment cost, save the acquisition time, improve efficiency。
The device automatically obtaining 1588 link asymmetry time delays that the embodiment of the present invention provides be should device in aforementioned manners, then all embodiments of said method are all suitable in this device, and all can reach same or analogous beneficial effect。
The above is the preferred embodiment of the present invention; it should be pointed out that, for those skilled in the art, under the premise without departing from principle of the present invention; can also making some improvements and modifications, these improvements and modifications also should be regarded as protection scope of the present invention。
Claims (10)
1. the method for an automatic acquisition 1588 link asymmetry time delay, it is characterised in that described method includes:
Run 1588 time synchronization protocols at master clock with from clock respectively, obtain first group of timestamp, wherein said master clock and described be provided with 1588 receiving-transmitting chains between clock；
Respectively at described master clock and described from running turning protocol clock, switch described master clock side 1588 and receive link and 1588 and send links, and switch and described receive link and 1588 from clock side 1588 and send links；
Respectively at described master clock with described run 1588 time synchronization protocols from clock, obtain second group of timestamp；
According to the described first group of timestamp obtained and described second group of timestamp, calculate described master clock and described 1588 receiving-transmitting chain asymmetry time delays between clock。
2. the method for claim 1, it is characterised in that described run 1588 time synchronization protocols at master clock with from clock respectively, obtains first group of timestamp, specifically includes:
Send synchronization Sync (a) message to described from clock by described master clock, obtain described master clock and send the described time stamp T synchronizing Sync (a) message1The described time stamp T synchronizing Sync (a) message is received from clock with described2；
By described from time clockwise described in master clock forward delay interval request Delay_req (a) message, obtain the described time stamp T sending described latency request Delay_req (a) message from clock3With the time stamp T that described master clock receives described latency request Delay_req (a) message4。
3. method as claimed in claim 2, it is characterized in that, described respectively at described master clock and described from running turning protocol clock, switch described master clock side 1588 and receive link and 1588 transmission links, and link and 1588 transmission links described in switching, are received from clock side 1588, specifically include:
When described master clock enters and switches readiness, timing switches preparation request message to described from clock transmission；
According to described from clock receive described in switch preparation request message, respond to described master clock and switch preparation and complete message and readiness is switched in entrance；
According to described master clock receive described in switch preparation and complete message, stop to described from clock send described in switch preparation request message, and switch the receiving-transmitting chain of described master clock, send Diagnosis of Links message to described from clock；
In the first limiting time, described do not receive described Diagnosis of Links message from clock, then proceed to change to the described receiving-transmitting chain from clock；
In the second limiting time, described in after receiving-transmitting chain is switched, receive described Diagnosis of Links message from clock, message will have been switched and sent to described master clock。
4. method as claimed in claim 3, it is characterised in that described respectively at described master clock and described 1588 time synchronization protocols from clock, obtains second group of timestamp, specifically includes:
Send synchronization Sync (b) message to described from clock by described master clock, obtain described master clock and send the described time stamp T synchronizing Sync (b) message1 1The described time stamp T synchronizing Sync (b) message is received from clock with described2 1；
By described from time clockwise described in master clock forward delay interval request Delay_req (b) message, obtain the described time stamp T sending described latency request Delay_req (b) message from clock3 1With the time stamp T that described master clock receives described latency request Delay_req (b) message4 1。
5. method as claimed in claim 4, it is characterised in that described according to the described first group of timestamp obtained and described second group of timestamp, calculates described master clock and described 1588 receiving-transmitting chain asymmetry time delays between clock, specifically includes:
By described time stamp T2With described time stamp T1Subtract each other, it is thus achieved that the very first time is poor；
By described time stamp T4With described time stamp T3Subtract each other, it is thus achieved that the second time difference；
By described time stamp T2 1With described time stamp T1 1Subtract each other, it is thus achieved that the 3rd time difference；
By described time stamp T4 1With described time stamp T3 1Subtract each other, it is thus achieved that the 4th time difference；
Carry out computing by the described very first time obtained is poor, the second time difference, the 3rd time difference with the 4th time difference, obtain described master clock and described 1588 receiving-transmitting chain asymmetry time delays between clock。
6. the device of an automatic acquisition 1588 link asymmetry time delay, it is characterised in that described device includes:
Turning protocol processing module, for running turning protocol at master clock with from clock respectively；
Switch module, for switching described master clock side according to the control of described turning protocol processing module and described receiving links and 1588 from the 1588 of clock side and send links；
1588 protocol process module, for running before and after turning protocol at described master clock in described turning protocol processing module respectively and described running 1588 time synchronization protocols from clock, obtain first group of timestamp and second group of timestamp；
Delay process module, for the first group timestamp acquired according to described 1588 protocol process module and second group of timestamp, calculates described master clock and described 1588 receiving-transmitting chain asymmetry time delays between clock。
7. device as claimed in claim 6, it is characterized in that, described turning protocol processing module includes: for run on described master clock turning protocol the first turning protocol processing unit and for described from the second turning protocol processing unit running turning protocol clock；
Described module of switching includes: receives the first switch unit of link and 1588 transmission links for switching the 1588 of described master clock side according to the control of described first turning protocol processing unit and sends the second switch unit of link for switching the described 1588 reception links and 1588 from clock side according to the control of described second turning protocol processing unit；
Described delay process module includes: for according to first group of timestamp and second group of timestamp, calculate the first delay process unit of described master clock side 1588 receiving-transmitting chain asymmetry time delay and for according to described first group of timestamp and second group of timestamp, calculating described from the second delay process unit of clock side 1588 receiving-transmitting chain asymmetry time delay。
8. device as claimed in claim 7, it is characterised in that described 1588 protocol process module include: the one 1588 protocol processing unit and the 2nd 1588 protocol processing unit, wherein
Described master clock sends Sync (a) message to described from clock by described one 1588 protocol processing unit, and records transmission time stamp T1, described after clock reception Sync (a) message, described 2nd 1588 protocol processing unit record receive time stamp T2；Described master clock is sent by described one 1588 protocol processing unit and carries described time stamp T1Follow_up (a) message to described from clock, described receive after Follow_up (a) message from clock, described 2nd 1588 protocol processing unit obtain described time stamp T1；Described send Delay_req (a) message to described master clock from clock by described 2nd 1588 protocol processing unit, and record transmission time stamp T3, after described master clock receives Delay_req (a) message, described one 1588 protocol processing unit record receive time stamp T4；Described master clock is sent by described one 1588 protocol processing unit and carries described time stamp T4Delay_resp (a) message to described from clock, described receive after Delay_resp (a) message from clock, described 2nd 1588 protocol processing unit obtain described time stamp T4, described time stamp T1, time stamp T2, time stamp T3And time stamp T4Belong to first group of timestamp；
Described master clock sends Sync (b) message to described from clock by described one 1588 protocol processing unit, and records transmission time stamp T1 1, described after clock reception Sync (b) message, described 2nd 1588 protocol processing unit record receive time stamp T2 1；Described master clock is sent by described one 1588 protocol processing unit and carries described time stamp T1 1Follow_up (b) message to described from clock, described receive after Follow_up (b) message from clock, described 2nd 1588 protocol processing unit obtain described time stamp T1 1；Described send Delay_req (b) message to described master clock from clock by described 2nd 1588 protocol processing unit, and record transmission time stamp T3 1, after described master clock receives Delay_req (b) message, described one 1588 protocol processing unit record receive time stamp T4 1；Described master clock is sent by described one 1588 protocol processing unit and carries described time stamp T4 1Delay_resp (b) message to described from clock, described receive after Delay_resp (b) message from clock, described 2nd 1588 protocol processing unit obtain described time stamp T4 1, described time stamp T1 1, time stamp T2 1, time stamp T3 1And time stamp T4 1Belong to second group of timestamp。
9. device as claimed in claim 8, it is characterised in that described first switch unit is internal or external at described master clock, described second switch unit is internal or external at described from clock。
10. device as claimed in claim 9, it is characterised in that described first delay process unit or described second delay process unit include:
First obtains subelement, for by described time stamp T2With described time stamp T1Subtract each other, it is thus achieved that the very first time is poor；
Second obtains subelement, for by described time stamp T4With described time stamp T3Subtract each other, it is thus achieved that the second time difference；
3rd obtains subelement, for by described time stamp T2 1With described time stamp T1 1Subtract each other, it is thus achieved that the 3rd time difference；
4th obtains subelement, for by described time stamp T4 1With described time stamp T3 1Subtract each other, it is thus achieved that the 4th time difference；
Computing subelement, carries out computing for the described very first time obtained is poor, the second time difference, the 3rd time difference with the 4th time difference, obtains described master clock and described 1588 receiving-transmitting chain asymmetry time delays between clock。
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| PCT/CN2015/078413 WO2016082466A1 (en) | 2014-11-25 | 2015-05-06 | Method and device for automatically acquiring 1588 link asymmetrical delay |
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| CN111342926A (en) * | 2020-02-28 | 2020-06-26 | 盛科网络（苏州）有限公司 | Method for optimizing time synchronization of PTP (precision time protocol) in asymmetric network |
| CN114124616A (en) * | 2022-01-25 | 2022-03-01 | 浙江中控研究院有限公司 | Clock synchronization optimization method based on EPA bus structure |
| WO2024098783A1 (en) * | 2022-11-11 | 2024-05-16 | 华为技术有限公司 | Time correction method and apparatus |
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| CN112039621B (en) * | 2019-06-04 | 2022-11-29 | 中国信息通信研究院 | Time synchronization method and system |
| CN112187395B (en) * | 2020-11-02 | 2022-07-15 | 上海欣诺通信技术股份有限公司 | Time synchronization method and device in distributed system |
| CN114221732B (en) * | 2021-12-23 | 2024-08-09 | 北京四方继保工程技术有限公司 | High-precision ping-pong synchronization method and system with synchronization quality |
| CN115562045A (en) * | 2022-11-09 | 2023-01-03 | 徐州市检验检测中心 | Delay compensation control method of remote control loader |
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| CN102291196A (en) * | 2011-08-17 | 2011-12-21 | 中兴通讯股份有限公司 | Implementation method and device for detecting asymmetrical time delay of 1588 link circuit automatically |
| CN102394741A (en) * | 2011-12-13 | 2012-03-28 | 杭州华三通信技术有限公司 | Method for realizing precision time synchronization based on IEEE1588 and apparatus thereof |
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| WO2024098783A1 (en) * | 2022-11-11 | 2024-05-16 | 华为技术有限公司 | Time correction method and apparatus |
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