WO2024095788A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
WO2024095788A1
WO2024095788A1 PCT/JP2023/037902 JP2023037902W WO2024095788A1 WO 2024095788 A1 WO2024095788 A1 WO 2024095788A1 JP 2023037902 W JP2023037902 W JP 2023037902W WO 2024095788 A1 WO2024095788 A1 WO 2024095788A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
lead
sealing resin
die pad
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/037902
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
禎将 藤定
光俊 齊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to CN202380076015.3A priority Critical patent/CN120153478A/zh
Priority to JP2024554392A priority patent/JPWO2024095788A1/ja
Publication of WO2024095788A1 publication Critical patent/WO2024095788A1/ja
Priority to US19/193,464 priority patent/US20250309062A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/464—Additional interconnections in combination with leadframes
    • H10W70/466—Tape carriers or flat leads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/871—Bond wires and strap connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/886—Die-attach connectors and strap connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/761—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors
    • H10W90/766—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • This disclosure relates to a semiconductor device.
  • Patent Document 1 discloses an example of a semiconductor device that includes a first semiconductor element and a first lead that is electrically connected to the first semiconductor element.
  • the first semiconductor element is a switching element such as a MOSFET.
  • the first lead includes a first pad to which the first semiconductor element is electrically connected, and a first terminal that is connected to the first pad.
  • the semiconductor device disclosed in Patent Document 1 further includes a sealing resin that covers the first semiconductor element.
  • the sealing resin has a resin through hole that penetrates the first pad in the thickness direction.
  • a fastening member such as a bolt is inserted into the resin through hole.
  • the back surface of the first pad surrounds the resin through hole.
  • the back surface of the pad is covered with the sealing resin.
  • the back surface of the pad may be exposed from the sealing resin.
  • the creepage distance from the back surface of the pad to the fastening member is relatively short. This may result in a decrease in the dielectric strength voltage of the semiconductor device.
  • One of the objectives of this disclosure is to provide a semiconductor device that is an improvement over conventional semiconductor devices.
  • one of the objectives of this disclosure is to provide a semiconductor device that can improve the dielectric strength while suppressing a decrease in heat dissipation.
  • the semiconductor device provided by the first aspect of the present disclosure includes a die pad having a through-hole penetrating in a first direction, a semiconductor element bonded to the die pad, and a mounting portion penetrating in the first direction and surrounded by the through-hole as viewed in the first direction, and a sealing resin covering the semiconductor element.
  • the die pad has a first portion including a back surface facing the first direction, and a second portion having the through-hole and connected to the first portion. As viewed in the first direction, the second portion is located on one side of the first portion in a second direction perpendicular to the first direction. The back surface is exposed from the sealing resin. The second portion is covered by the sealing resin.
  • the semiconductor device provided by the second aspect of the present disclosure includes a die pad having a back surface facing a first direction, a semiconductor element bonded to the die pad, and a sealing resin having an attachment portion penetrating in the first direction and covering the semiconductor element.
  • the entire die pad is located on one side of the attachment portion in a second direction perpendicular to the first direction.
  • the back surface is exposed from the sealing resin.
  • the above configuration makes it possible to improve the dielectric strength while suppressing the deterioration of heat dissipation.
  • FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 2 is a plan view of the semiconductor device shown in FIG.
  • FIG. 3 is a plan view corresponding to FIG. 2, seen through the sealing resin.
  • FIG. 4 is a bottom view of the semiconductor device shown in FIG.
  • FIG. 5 is a front view of the semiconductor device shown in FIG.
  • FIG. 6 is a cross-sectional view taken along line VI-VI in FIG.
  • FIG. 7 is a cross-sectional view taken along line VII-VII in FIG.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG.
  • FIG. 9 is a partially enlarged view of FIG. FIG.
  • FIG. 10 is a plan view of the semiconductor device according to the second embodiment of the present disclosure, seen through the sealing resin.
  • 11 is a bottom view of the semiconductor device shown in FIG.
  • FIG. 12 is a cross-sectional view taken along line XII-XII in FIG.
  • FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG.
  • FIG. 14 is a plan view of a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 15 is a plan view corresponding to FIG. 14, seen through the sealing resin.
  • 16 is a bottom view of the semiconductor device shown in FIG.
  • FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG.
  • FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG.
  • a semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 9.
  • the semiconductor device A10 is generally used in a power conversion circuit such as an inverter.
  • the package format of the semiconductor device A10 is a TO (Transistor Outline).
  • the semiconductor device A10 includes a semiconductor element 10, a die pad 20, a first lead 21, a second lead 22, a third lead 23, a conductive bonding layer 29, a conductive member 31, a wire 32, and a sealing resin 40.
  • FIG. 3 shows the sealing resin 40 through the view for ease of understanding. In FIG. 3, the sealing resin 40 through the view is shown by an imaginary line (two-dot chain line).
  • first direction z An example of a direction perpendicular to the first direction z will be referred to as the "second direction x.”
  • second direction x An example of a direction perpendicular to both the first direction z and the second direction x will be referred to as the "third direction y.”
  • the semiconductor element 10 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
  • the semiconductor element 10 may be a field effect transistor including a MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor) or a bipolar transistor such as an IGBT (Insulated Gate Bipolar Transistor).
  • the semiconductor element 10 is an n-channel type MOSFET with a vertical structure.
  • the multiple semiconductor elements 10 include a compound semiconductor substrate.
  • the composition of the compound semiconductor substrate includes silicon carbide (SiC).
  • the semiconductor element 10 has a first electrode 11, a second electrode 12, and a gate electrode 13.
  • the first electrode 11 is located on the side facing the mounting surface 201 of the die pad 20, which will be described later, in the first direction z.
  • a current corresponding to the power before being converted by the semiconductor element 10 flows through the first electrode 11.
  • the first electrode 11 corresponds to the drain electrode of the semiconductor element 10.
  • the second electrode 12 is located on the opposite side to the first electrode 11 in the first direction z.
  • a current corresponding to the power converted by the semiconductor element 10 flows through the second electrode 12.
  • the second electrode 12 corresponds to the source electrode of the semiconductor element 10.
  • the gate electrode 13 is located on the same side as the second electrode 12 in the first direction z.
  • a gate voltage for driving the semiconductor element 10 is applied to the gate electrode 13.
  • the area of the gate electrode 13 is smaller than the area of the second electrode 12.
  • the die pad 20 is a conductive member on which the semiconductor element 10 is mounted, as shown in FIG. 3 and FIG. 6 to FIG. 8.
  • the die pad 20, together with the first lead 21, the second lead 22, and the third lead 23, are obtained from the same lead frame.
  • the lead frame is copper (Cu) or a copper alloy. Therefore, the composition of each of the die pad 20, the first lead 21, the second lead 22, and the third lead 23 includes copper.
  • the die pad 20 has a mounting surface 201 and a back surface 202.
  • the mounting surface 201 faces the side facing the semiconductor element 10 in the first direction z.
  • the mounting surface 201 is covered with the sealing resin 40.
  • the back surface 202 faces the opposite side to the mounting surface 201 in the first direction z.
  • the back surface 202 is plated with, for example, tin (Sn). The back surface 202 is exposed from the sealing resin 40.
  • the die pad 20 has a first portion 20A and a second portion 20B connected to the first portion 20A.
  • the second portion 20B When viewed in the first direction z, the second portion 20B is located on one side of the first portion 20A in the second direction x.
  • the second portion 20B is covered with sealing resin 40.
  • Each of the first portion 20A and the second portion 20B includes a mounting surface 201.
  • the first portion 20A includes a back surface 202.
  • the second portion 20B is provided with a through portion 203.
  • the through portion 203 penetrates the second portion 20B in the first direction z.
  • the through portion 203 is circular when viewed in the first direction z.
  • the first dimension t1 in the first direction z of the first portion 20A is greater than the second dimension t2 in the first direction z of the second portion 20B.
  • the dimension of the second portion 20B in the second direction x is greater than the dimension of the back surface 202 in the second direction x.
  • the conductive bonding layer 29 bonds the die pad 20 and the semiconductor element 10.
  • the first electrode 11 of the semiconductor element 10 is conductively bonded to the mounting surface 201 of the die pad 20 via the conductive bonding layer 29. This allows the first electrode 11 to be electrically connected to the die pad 20.
  • the first electrode 11 is conductively bonded to each of the mounting surface 201 of the first part 20A of the die pad 20 and the mounting surface 201 of the second part 20B of the die pad 20.
  • the conductive bonding layer 29 is, for example, solder.
  • the conductive bonding layer 29 may be a sintered metal.
  • the first lead 21 includes a portion extending in the second direction x, and is connected to the first portion 20A of the die pad 20. As a result, the first lead 21 is electrically connected to the first electrode 11 of the semiconductor element 10. Therefore, the first lead 21 corresponds to the drain terminal of the semiconductor device A10.
  • the first lead 21 is located on the opposite side of the second portion 20B of the die pad 20 in the second direction x with respect to the first portion 20A.
  • the first lead 21 has a covering portion 211 and an exposed portion 212.
  • the covering portion 211 is connected to the first portion 20A of the die pad 20 and is covered with the sealing resin 40. When viewed in the third direction y, the covering portion 211 is bent.
  • the exposed portion 212 is connected to the covering portion 211 and is exposed from the sealing resin 40.
  • the exposed portion 212 protrudes from the sealing resin 40 on the side opposite to the side on which the die pad 20 is located in the second direction x.
  • the surface of the exposed portion 212 is, for example, tin-plated.
  • the second lead 22 is located away from the die pad 20, as shown in Figures 3 and 6.
  • the second lead 22 extends in the second direction x.
  • the second lead 22 is electrically connected to the second electrode 12 of the semiconductor element 10. Therefore, the second lead 22 corresponds to the source terminal of the semiconductor device A10.
  • the second lead 22 is located next to the first lead 21 in the third direction y.
  • the second lead 22 has a covering portion 221, an exposed portion 222, and a first bonding surface 223.
  • the covering portion 221 is covered with the sealing resin 40.
  • the exposed portion 222 is connected to the covering portion 221 and is exposed from the sealing resin 40.
  • the exposed portion 222 protrudes from the sealing resin 40 on the side opposite to the side on which the die pad 20 is located in the second direction x.
  • the surface of the exposed portion 222 is plated with tin, for example.
  • the first bonding surface 223 faces the same side as the mounting surface 201 of the die pad 20 in the first direction z.
  • the first bonding surface 223 is included as part of the covering portion 221.
  • the first bonding surface 223 is located on the side on which the semiconductor element 10 is located in the first direction z from the mounting surface 201.
  • the third lead 23 is located away from the die pad 20, as shown in Figures 3 and 7.
  • the third lead 23 extends in the second direction x.
  • the third lead 23 is electrically connected to the gate electrode 13 of the semiconductor element 10. Therefore, the third lead 23 corresponds to the gate terminal of the semiconductor device A10.
  • the third lead 23 is located on the opposite side of the second lead 22 with respect to the first lead 21 in the third direction y.
  • the third lead 23 has a covering portion 231, an exposed portion 232, and a second bonding surface 233.
  • the covering portion 231 is covered with the sealing resin 40.
  • the exposed portion 232 is connected to the covering portion 231 and is exposed from the sealing resin 40.
  • the exposed portion 232 protrudes from the sealing resin 40 on the side opposite to the side on which the die pad 20 is located in the second direction x.
  • the surface of the exposed portion 232 is plated with tin, for example.
  • the second bonding surface 233 faces the same side as the mounting surface 201 of the die pad 20 in the first direction z.
  • the second bonding surface 233 is included in a part of the covering portion 231. In the first direction z, the position of the second bonding surface 233 is the same (or approximately the same) as the position of the first bonding surface 223 of the second lead 22.
  • the first lead 21, the second lead 22, and the third lead 23 are arranged along the third direction y.
  • the exposed portion 212 of the first lead 21, the exposed portion 222 of the second lead 22, and the exposed portion 232 of the third lead 23 all have the same height h from the bottom surface 42 of the sealing resin 40 described below.
  • the conductive member 31 is conductively bonded to the second electrode 12 of the semiconductor element 10 and the first bonding surface 223 of the second lead 22.
  • the second lead 22 is conductive to the second electrode 12.
  • the conductive member 31 contains copper or a copper alloy.
  • the conductive member 31 is a metal clip. Alternatively, the conductive member 31 may be a wire.
  • the conductive member 31 has a first bonding portion 311 and a second bonding portion 312.
  • the first bonding portion 311 is located at one end of the conductive member 31 and is conductively bonded to the second electrode 12 via the conductive bonding layer 29.
  • the second bonding portion 312 is located at the other end of the conductive member 31 and is conductively bonded to the first bonding surface 223 via the conductive bonding layer 29.
  • the wire 32 is conductively bonded to the gate electrode 13 of the semiconductor element 10 and the second bonding surface 233 of the third lead 23. This allows the third lead 23 to be electrically connected to the gate electrode 13.
  • the wire 32 is, for example, a wire containing either aluminum or gold (Au).
  • the sealing resin 40 covers the semiconductor element 10, the conductive member 31 and the wire 32. As shown in Figures 6 to 8, the sealing resin 40 covers a portion of each of the die pad 20, the first lead 21, the second lead 22 and the third lead 23.
  • the sealing resin 40 has electrical insulation properties.
  • the sealing resin 40 is made of a material that contains, for example, black epoxy resin.
  • the sealing resin 40 has a top surface 41, a bottom surface 42, two first side surfaces 43, two second side surfaces 44 and two openings 45.
  • the top surface 41 faces the same side as the mounting surface 201 of the die pad 20 in the first direction z.
  • the bottom surface 42 faces the opposite side to the top surface 41 in the first direction z.
  • the back surface 202 of the first portion 20A of the die pad 20 is exposed from the bottom surface 42.
  • the two first side surfaces 43 are located apart from each other in the second direction x.
  • Each of the two first side surfaces 43 is connected to the top surface 41 and the bottom surface 42.
  • the exposed portion 212 of the first lead 21, the exposed portion 222 of the second lead 22, and the exposed portion 232 of the third lead 23 each protrude in the second direction x from one of the two first side surfaces 43.
  • the two second side surfaces 44 are positioned apart from each other in the third direction y.
  • Each of the two second side surfaces 44 is connected to the top surface 41 and the bottom surface 42.
  • the two openings 45 are positioned apart from each other in the third direction y.
  • Each of the two openings 45 is recessed toward the inside of the sealing resin 40 from both the top surface 41 and one of the two second side surfaces 44.
  • a portion of the mounting surface 201 of the second portion 20B of the die pad 20 is exposed from each of the two openings 45.
  • the sealing resin 40 has an attachment portion 46 that penetrates in the first direction z from the top surface 41 to the bottom surface 42.
  • the attachment portion 46 when viewed in the first direction z, the attachment portion 46 is surrounded by the penetration portion 203 of the second part 20B of the die pad 20. In other words, when viewed in the first direction z, the attachment portion 46 is contained within the penetration portion 203.
  • the sealing resin 40 has an inner circumferential surface 461 that is connected to the top surface 41 and the bottom surface 42 and defines the mounting portion 46.
  • the mounting portion 46 includes a first hole edge 46A that is the boundary between the inner circumferential surface 461 and the top surface 41, and a second hole edge 46B that is the boundary between the inner circumferential surface 461 and the bottom surface 42.
  • the first hole edge 46A surrounds the second hole edge 46B.
  • the second dimension t2 in the first direction z of the second portion 20B of the die pad 20 and the third dimension t3 in the first direction z of the portion of the sealing resin 40 extending from the bottom surface 42 to the second portion 20B are different from each other.
  • the second dimension t2 is greater than the third dimension t3.
  • the semiconductor device A10 includes a die pad 20 having a through-hole 203 penetrating in the first direction z, a semiconductor element 10 bonded to the die pad 20, and a sealing resin 40 having an attachment portion 46 penetrating in the first direction z and covering the semiconductor element 10.
  • the attachment portion 46 is surrounded by the through-hole 203.
  • the die pad 20 has a first portion 20A including a back surface 202, and a second portion 20B having a through-hole 203.
  • the second portion 20B is located on one side of the first portion 20A in the second direction x.
  • the back surface 202 is exposed from the sealing resin 40.
  • the second portion 20B is covered by the sealing resin 40.
  • the entire back surface 202 exposed from the sealing resin 40 is located away from the attachment portion 46 on one side of the second direction x.
  • the first dimension t1 in the first direction z of the first portion 20A is greater than the second dimension t2 in the first direction z of the second portion 20B.
  • the second portion 20B is sandwiched between the sealing resin 40 in the first direction z. This prevents the die pad 20 from falling off the sealing resin 40.
  • the die pad 20 has a mounting surface 201 that faces the opposite side to the back surface 202 in the first direction z.
  • Each of the first part 20A and the second part 20B includes a mounting surface 201.
  • the semiconductor element 10 is conductively bonded to each of the mounting surface 201 of the first part 20A and the mounting surface 201 of the second part 20B.
  • the dimension of the second portion 20B in the second direction x is greater than the dimension of the back surface 202 of the first portion 20A in the second direction x. This configuration ensures a sufficient area for the mounting surface 201 of the die pad 20 to which the semiconductor element 10 is conductively bonded, while further increasing the creepage distance from the attachment portion 46 of the sealing resin 40 to the back surface 202.
  • the second dimension t2 of the second portion 20B in the first direction z is greater than the third dimension t3 of the portion of the sealing resin 40 extending from the bottom surface 42 to the second portion 20B in the first direction z.
  • This configuration can reduce the thermal resistance of the second portion 20B in the first direction z. This can improve the heat dissipation of the semiconductor device A10.
  • the sealing resin 40 has an inner circumferential surface 461 that is connected to each of the top surface 41 and the bottom surface 42 and defines the mounting portion 46.
  • the mounting portion 46 includes a first hole edge 46A that is the boundary between the inner circumferential surface 461 and the top surface 41, and a second hole edge 46B that is the boundary between the inner circumferential surface 461 and the bottom surface 42. When viewed in the first direction z, the first hole edge 46A surrounds the second hole edge 46B. This configuration allows the mold to be more smoothly removed from the mounting portion 46 when forming the sealing resin 40 in the manufacture of the semiconductor device A10. This prevents damage to the mounting portion 46.
  • FIG. 10 is a perspective view of the sealing resin 40 for ease of understanding.
  • the transmitted sealing resin 40 is shown by imaginary lines.
  • semiconductor device A20 the configuration of the die pad 20 is different from that of semiconductor device A10.
  • the second portion 20B of the die pad 20 has a bent portion 204.
  • the bent portion 204 is located on one side of the second portion 20B in the second direction x and extends in the third direction y.
  • the second portion 20B is connected to the first portion 20A of the die pad 20 by the bent portion 204.
  • the bent portion 204 is bent.
  • the second portion 20B of the die pad 20 does not include the mounting surface 201. Therefore, the semiconductor element 10 is conductively joined only to the first portion 20A of the die pad 20. Furthermore, in the semiconductor device A20, the first dimension t1 in the first direction z of the first portion 20A is equal to the second dimension t2 in the first direction z of the second portion 20B (excluding the bent portion 204).
  • the semiconductor device A20 includes a die pad 20 having a through-hole 203 penetrating in the first direction z, a semiconductor element 10 bonded to the die pad 20, and a sealing resin 40 having an attachment portion 46 penetrating in the first direction z and covering the semiconductor element 10.
  • the attachment portion 46 is surrounded by the through-hole 203.
  • the die pad 20 has a first portion 20A including a back surface 202 and a second portion 20B having a through-hole 203.
  • the second portion 20B is located on one side of the first portion 20A in the second direction x.
  • the back surface 202 is exposed from the sealing resin 40.
  • the second portion 20B is covered by the sealing resin 40.
  • the semiconductor device A20 can also improve the dielectric strength while suppressing a decrease in heat dissipation. Furthermore, the semiconductor device A20 has a configuration common to the semiconductor device A10, thereby achieving the same effects as the semiconductor device A10.
  • FIG. 15 is a perspective view of the sealing resin 40 for ease of understanding. In Fig. 15, the transmitted sealing resin 40 is shown by imaginary lines.
  • semiconductor device A30 the configuration of the die pad 20 and the sealing resin 40 differs from that of semiconductor device A10.
  • the die pad 20 does not have a first portion 20A and a second portion 20B. Furthermore, the die pad 20 does not have a through portion 203.
  • the die pad 20 has a mounting surface 201, a back surface 202, and an overhanging portion 205.
  • the overhanging portion 205 is flush with the mounting surface 201 in the first direction z.
  • the overhanging portion 205 is located on the opposite side to the side on which the first lead 21 is located in the second direction x.
  • the overhanging portion 205 extends in the third direction y.
  • the overhanging portion 205 is sandwiched between the sealing resin 40 in the first direction z.
  • the entire die pad 20 is located to one side of the mounting portion 46 of the sealing resin 40 in the second direction x.
  • the sealing resin 40 does not have two openings 45. Therefore, in the die pad 20, only the back surface 202 is exposed from the sealing resin 40.
  • the semiconductor device A30 includes a die pad 20 having a back surface 202 facing the first direction z, a semiconductor element 10 bonded to the die pad 20, and a sealing resin 40 having an attachment portion 46 penetrating in the first direction z and covering the semiconductor element 10.
  • the entire die pad 20 is located on one side of the attachment portion 46 in the second direction x.
  • the back surface 202 is exposed from the sealing resin 40.
  • the semiconductor device A30 can also improve the dielectric strength while suppressing a decrease in heat dissipation.
  • the semiconductor device A30 has a configuration common to the semiconductor device A10, thereby achieving the same effects as the semiconductor device A10.
  • Appendix 1 a die pad having a through-portion penetrating in a first direction; a semiconductor element bonded to the die pad; a mounting portion that penetrates in the first direction and is surrounded by the through portion as viewed in the first direction, and a sealing resin that covers the semiconductor element, the die pad has a first portion including a back surface facing the first direction, and a second portion in which the through portion is provided and which is connected to the first portion, the second portion is located on one side of the first portion in a second direction perpendicular to the first direction, the rear surface is exposed from the sealing resin, The second portion is covered with the sealing resin.
  • Appendix 2. 2.
  • Appendix 3. the sealing resin has a bottom surface facing the same side as the back surface in the first direction, 3.
  • Appendix 4. the die pad has a mounting surface facing a side opposite to the back surface in the first direction, each of the first portion and the second portion includes the mounting surface; 4.
  • the semiconductor device according to claim 3, wherein the semiconductor element is bonded to the mounting surface.
  • Appendix 5. 5. The semiconductor device according to claim 4, wherein the semiconductor element is conductively bonded to the mounting surface.
  • the semiconductor element has a first electrode located on a side facing the mounting surface in the first direction, the first electrode is conductively bonded to the mounting surface; 10.
  • Appendix 11. The semiconductor device of claim 10, wherein the first lead is connected to the first portion.
  • Appendix 12. 12. The semiconductor device according to claim 11, wherein the first lead is located on the opposite side of the second portion from the first portion in the second direction.
  • Appendix 13 Further comprising a second lead; the semiconductor element has a second electrode located on an opposite side to the first electrode in the first direction; the second lead is electrically connected to the second electrode, 13.
  • each of the first lead, the second lead, and the third lead includes a portion protruding from the sealing resin on a side opposite to the side on which the die pad is located in the second direction. Appendix 16.
  • the sealing resin has a top surface facing a side opposite to the bottom surface in the first direction, and an inner circumferential surface connected to the top surface and the bottom surface and defining the mounting portion, the mounting portion includes a first hole edge that is a boundary between the inner circumferential surface and the top surface, and a second hole edge that is a boundary between the inner circumferential surface and the bottom surface, 16.
  • a die pad having a back surface facing a first direction; a semiconductor element bonded to the die pad; a mounting portion that penetrates in the first direction and a sealing resin that covers the semiconductor element, the entirety of the die pad is located on one side of the attachment portion in a second direction perpendicular to the first direction, The back surface of the semiconductor device is exposed from the sealing resin.

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
PCT/JP2023/037902 2022-11-04 2023-10-19 半導体装置 Ceased WO2024095788A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202380076015.3A CN120153478A (zh) 2022-11-04 2023-10-19 半导体装置
JP2024554392A JPWO2024095788A1 (https=) 2022-11-04 2023-10-19
US19/193,464 US20250309062A1 (en) 2022-11-04 2025-04-29 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022177196 2022-11-04
JP2022-177196 2022-11-04

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US19/193,464 Continuation US20250309062A1 (en) 2022-11-04 2025-04-29 Semiconductor device

Publications (1)

Publication Number Publication Date
WO2024095788A1 true WO2024095788A1 (ja) 2024-05-10

Family

ID=90930254

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/037902 Ceased WO2024095788A1 (ja) 2022-11-04 2023-10-19 半導体装置

Country Status (4)

Country Link
US (1) US20250309062A1 (https=)
JP (1) JPWO2024095788A1 (https=)
CN (1) CN120153478A (https=)
WO (1) WO2024095788A1 (https=)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117160U (ja) * 1983-01-28 1984-08-07 サンケン電気株式会社 絶縁物封止半導体装置
JPH0233442U (https=) * 1988-08-26 1990-03-02
JPH0655261U (ja) * 1992-09-30 1994-07-26 日本インター株式会社 樹脂封止型半導体装置
US20090212417A1 (en) * 2008-02-22 2009-08-27 Yong Wae Chet Semiconductor Device
JP2012059927A (ja) * 2010-09-09 2012-03-22 Rohm Co Ltd 半導体装置および半導体装置の製造方法
WO2022014300A1 (ja) * 2020-07-13 2022-01-20 ローム株式会社 半導体装置、および半導体装置の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117160U (ja) * 1983-01-28 1984-08-07 サンケン電気株式会社 絶縁物封止半導体装置
JPH0233442U (https=) * 1988-08-26 1990-03-02
JPH0655261U (ja) * 1992-09-30 1994-07-26 日本インター株式会社 樹脂封止型半導体装置
US20090212417A1 (en) * 2008-02-22 2009-08-27 Yong Wae Chet Semiconductor Device
JP2012059927A (ja) * 2010-09-09 2012-03-22 Rohm Co Ltd 半導体装置および半導体装置の製造方法
WO2022014300A1 (ja) * 2020-07-13 2022-01-20 ローム株式会社 半導体装置、および半導体装置の製造方法

Also Published As

Publication number Publication date
CN120153478A (zh) 2025-06-13
JPWO2024095788A1 (https=) 2024-05-10
US20250309062A1 (en) 2025-10-02

Similar Documents

Publication Publication Date Title
US8629467B2 (en) Semiconductor device
JP4865829B2 (ja) 半導体装置およびその製造方法
CN102593081A (zh) 包括散热器的半导体器件
JP7686645B2 (ja) 半導体装置、および半導体装置の製造方法
US20220301965A1 (en) Semiconductor device
US20240258219A1 (en) Semiconductor device
JP2025166256A (ja) 半導体装置、および半導体装置の製造方法
WO2023112677A1 (ja) 半導体装置および半導体装置の製造方法
WO2025142335A1 (ja) 半導体装置
JP2009130055A (ja) 半導体装置
WO2024095788A1 (ja) 半導体装置
US20240030080A1 (en) Semiconductor device
WO2023149257A1 (ja) 半導体装置
JP7154202B2 (ja) 非絶縁型パワーモジュール
US12400972B2 (en) Semiconductor device for suppressing excessive wetting and spreading of bonding layer
JP7704594B2 (ja) 半導体装置
WO2025158862A1 (ja) 半導体装置および車両
JP5758816B2 (ja) パワー半導体装置
WO2024034359A1 (ja) 半導体装置
US20250357412A1 (en) Semiconductor device and method for manufacturing the same
US20240047315A1 (en) Semiconductor device
WO2026094711A1 (ja) 半導体装置
WO2024203066A1 (ja) 半導体装置および車両
JP2026035927A (ja) 半導体装置
WO2023218943A1 (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23885550

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2024554392

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: CN2023800760153

Country of ref document: CN

Ref document number: 202380076015.3

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE

WWP Wipo information: published in national office

Ref document number: 202380076015.3

Country of ref document: CN

122 Ep: pct application non-entry in european phase

Ref document number: 23885550

Country of ref document: EP

Kind code of ref document: A1