WO2024093319A1 - 一种超导量子比特读出装置、超导量子芯片和量子计算机 - Google Patents

一种超导量子比特读出装置、超导量子芯片和量子计算机 Download PDF

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Publication number
WO2024093319A1
WO2024093319A1 PCT/CN2023/104621 CN2023104621W WO2024093319A1 WO 2024093319 A1 WO2024093319 A1 WO 2024093319A1 CN 2023104621 W CN2023104621 W CN 2023104621W WO 2024093319 A1 WO2024093319 A1 WO 2024093319A1
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Prior art keywords
capacitor
readout
circuit
pole
coupling unit
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PCT/CN2023/104621
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English (en)
French (fr)
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龙俊伶
戴坤哲
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华为技术有限公司
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Publication of WO2024093319A1 publication Critical patent/WO2024093319A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control

Definitions

  • the present application relates to the field of communications, and in particular to a superconducting quantum bit readout device, a superconducting quantum chip and a quantum computer.
  • Quantum computing is a new type of computing method based on quantum mechanics that utilizes properties such as quantum superposition and entanglement. In some specific problems, such as large number decomposition and quantum chemical simulation, quantum computing has the advantage of exponential acceleration compared to classical computing in theory.
  • Superconducting quantum bits are currently one of the most promising physical systems for realizing quantum computing.
  • the mainstream solution for superconducting quantum bit readout is to dispersion couple a linear resonant cavity to the superconducting bit, and then read the state of the bit by detecting the response of the resonant cavity.
  • This type of resonant cavity used to read out bits is also called a readout cavity.
  • the readout cavity and the readout line are generally coupled by capacitance or mutual inductance. The microwave photons on the readout line used to detect the response of the readout cavity will first enter the readout cavity, and then return to the readout line and carry the information of the bit state.
  • the embodiments of the present application provide a superconducting quantum bit readout device, a superconducting quantum chip and a quantum computer, which both ensure the fidelity of the readout signal and avoid the shortening of the relaxation time of the bit.
  • an embodiment of the present application provides a superconducting quantum bit readout device.
  • the superconducting quantum bit readout device includes: a superconducting quantum bit unit, a filter readout cavity, a readout line, a first coupling unit, and a second coupling unit.
  • the filter readout cavity is coupled to the superconducting quantum bit unit through the first coupling unit, and the filter readout cavity is coupled to the readout line through the second coupling unit.
  • the superconducting quantum bit unit is used to store microwave photons in a quantum state.
  • the readout line is used to transmit a read-in signal to the filter readout cavity.
  • the filter readout cavity is used to modulate the read-in signal according to the quantum state of the microwave photon to obtain a readout signal, and transmit the readout signal to the readout line.
  • the filter readout cavity is also used to filter microwave photons in a quantum state to suppress microwave photons in a quantum state from being transmitted through the filter readout cavity to the readout line.
  • the filter readout cavity allows the readout signal to be transmitted to the readout line, and suppresses the microwave photons in the quantum state from being transmitted to the readout line through the filter readout cavity, thereby avoiding the microwave photons in the quantum state from being dissipated through the filter readout cavity, and also avoiding the shortening of the relaxation time of the bit. Therefore, the present application can accelerate the readout speed of the signal to improve the readout fidelity while ensuring that the bit relaxation time is not shortened, or, if the coupling strength of the filter readout cavity and the readout line is maintained, the bit relaxation time can be extended while the readout speed remains unchanged. In other words, the present application takes into account the two factors of readout fidelity and bit relaxation time.
  • the filter readout cavity provided by the present application is an integrated device, and the overall size of the device is relatively small, and the filter channel will not affect the readout channel, and will not affect the readout signal while realizing filtering.
  • the S21 frequency response curve corresponding to the structure including the filter readout cavity, the first coupling unit and the second coupling unit includes at least one resonance point and at least one pole, the frequency difference between the readout signal and the resonance point is less than a first preset value, and the frequency difference between the microwave photon in the quantum state and the pole is less than a second preset value.
  • the first preset value is 20MHz
  • the second preset value is 4GHz.
  • the resonance point represents a microwave mode
  • the read-in signal can be input to the filter readout cavity by the readout line
  • the readout signal can be output to the readout line by the filter readout cavity.
  • the pole represents a microwave blocking point, and the microwave photon in the quantum state is reflected by the filter readout cavity and cannot pass through the filter.
  • the transmission from the readout cavity to the readout line prevents microwave photons in the quantum state from being dissipated through the filtered readout cavity, thus avoiding the shortening of the relaxation time of the bit.
  • the filter readout cavity includes an inductor, a first capacitor, a second capacitor, and a third capacitor.
  • the first end of the inductor is connected to the first coupling unit and the second coupling unit, and the connection point is connected to the first end of the first capacitor and the first end of the second capacitor, the second end of the first capacitor is grounded, the second end of the inductor is connected to the second end of the second capacitor, and the connection point is connected to the first end of the third capacitor, and the second end of the third capacitor is grounded.
  • the frequency of the resonance point is greater than the frequency of the pole.
  • the filter readout cavity adopts a lumped floating design.
  • the filter readout cavity is mainly composed of a capacitor and an inductor in parallel. Both ends of the parallel circuit are grounded through capacitors.
  • the superconducting quantum bit unit and the readout line are coupled to the same end of the filter readout cavity. Due to the lumped design, the size can be made smaller and the integration is higher.
  • the filter readout cavity includes an inductor, a first capacitor, a second capacitor, and a third capacitor.
  • the first end of the inductor is connected to the first coupling unit, and the connection point is connected to the first end of the first capacitor and the first end of the second capacitor, the second end of the first capacitor is grounded, the second end of the inductor is connected to the second coupling unit, and the connection point is connected to the first end of the third capacitor and the second end of the second capacitor, and the second end of the third capacitor is grounded.
  • the frequency of the resonance point is less than the frequency of the pole.
  • the filter readout cavity adopts a lumped floating design.
  • the filter readout cavity is mainly composed of a capacitor and an inductor in parallel. Both ends of the parallel circuit are grounded through capacitors, and the superconducting quantum bit unit and the readout line are coupled to different ends of the filter readout cavity. Due to the use of a lumped design, the size can be made smaller and the integration is higher. In addition, since the frequency of the resonance point is less than the frequency of the pole, it is convenient to adjust the frequency of the pole downward so that the frequency of the pole is close to the frequency of the resonance point.
  • the microwave photons in the quantum state can pass through the filter readout cavity and be transmitted to the readout line, so that the microwave photons in the quantum state are restored to the 0 state, completing the operation of resetting the superconducting quantum bit unit, which helps to improve the efficiency of the system.
  • the first coupling unit includes a coupling capacitor
  • the second coupling unit includes a coupling capacitor, which enhances the feasibility of the present solution.
  • the filter readout cavity includes a pole generating circuit, a first connecting circuit, and a second connecting circuit.
  • the first end of the first connecting circuit is connected to the first coupling unit
  • the first end of the second connecting circuit is connected to the second coupling unit
  • the second end of the first connecting circuit is connected to the second end of the second connecting circuit
  • the connecting point is connected to the pole generating circuit.
  • the frequency of the pole depends on the pole generating circuit, the frequency of the resonance point is greater than the frequency of the pole, or the frequency of the resonance point is less than the frequency of the pole.
  • a distributed cavity design is adopted, which makes it easier to obtain a higher quality factor from the perspective of micro-nano processing.
  • the frequencies of the poles and resonance points can be flexibly adjusted through pole generation circuits with different designs to meet the needs of different scenarios, for example, the design facilitates the operation of resetting the superconducting quantum bit unit.
  • the pole generation circuit includes a third transmission line and a first capacitor, the first end of the third transmission line is connected to the second end of the first connection circuit and the second end of the second connection circuit, the second end of the third transmission line is connected to the first end of the first capacitor, and the second end of the first capacitor is grounded.
  • the pole generation circuit includes an LC parallel circuit and a first capacitor, the first end of the LC parallel circuit is connected to the second end of the first connection circuit and the second end of the second connection circuit, the second end of the LC parallel circuit is connected to the first end of the first capacitor, and the second end of the first capacitor is grounded.
  • the pole generation circuit includes an LC parallel circuit and a first capacitor, the first end of the LC parallel circuit is connected to the first end of the first capacitor, the second end of the first capacitor is connected to the second end of the first connection circuit and the second end of the second connection circuit, and the second end of the LC parallel circuit is grounded.
  • This implementation provides multiple implementations of the pole generation circuit, improving the scalability of the solution.
  • the first connection circuit includes an LC parallel circuit or a transmission line
  • the second connection circuit includes an LC parallel circuit or a transmission line. This implementation provides multiple implementations of the first connection circuit and the second connection circuit, thereby improving the flexibility of the solution.
  • the first coupling unit includes a coupling capacitor
  • the second coupling unit includes a coupling capacitor
  • the first coupling unit includes a coupling capacitor
  • the second coupling unit includes a coupling inductor. This implementation provides multiple implementations of the first coupling unit and the second coupling unit, so that different coupling modes can be selected according to actual needs.
  • the filter readout cavity includes a first pole generating circuit, a second pole generating circuit, a connecting circuit, a first capacitor, and a second capacitor.
  • the first end of the connecting circuit is connected to the first coupling unit, and the connecting point is connected to the first pole generating circuit and the first end of the first capacitor, the second end of the first capacitor is grounded, the second end of the connecting circuit is connected to the second coupling unit, and the connecting point is connected to the second pole generating circuit and the first end of the second capacitor, and the second end of the second capacitor is grounded.
  • the S21 frequency response curve includes a first pole and a second pole, the frequency of the first pole depends on the first pole generating circuit, and the frequency of the second pole depends on the second pole generating circuit.
  • the filtering bandwidth is significantly improved.
  • the pole generation circuit 11 and the pole generation circuit 14 can be designed so that the frequency of the first pole is close to the second pole, so that the filtering interval covered by the two poles is connected to form a larger filtering interval. If the frequencies of the two poles are made the same in design, the filtering effect will become stronger due to the superposition of the two poles compared to the case of a single pole. In addition, the frequencies of the two poles and the resonance point can be flexibly adjusted through pole generation circuits of different designs to meet the needs of different scenarios, for example, by designing to facilitate the operation of resetting the superconducting quantum bit unit.
  • the first pole generating circuit includes a first transmission line and a third capacitor, the first end of the first transmission line is connected to the first end of the first capacitor, and the connection point is connected to the first end of the connection circuit and the first coupling unit, the second end of the first transmission line is connected to the first end of the third capacitor, and the second end of the third capacitor is grounded.
  • the first pole generating circuit includes a first LC parallel circuit and a third capacitor, the first end of the first LC parallel circuit is connected to the first end of the first capacitor, and the connection point is connected to the first end of the connection circuit and the first coupling unit, the second end of the first LC parallel circuit is connected to the first end of the third capacitor, and the second end of the third capacitor is grounded.
  • the first pole generating circuit includes a first LC parallel circuit and a third capacitor, the first end of the first LC parallel circuit is connected to the first end of the third capacitor, the second end of the third capacitor is connected to the first end of the first capacitor, and the connection point is connected to the first end of the connection circuit and the first coupling unit, and the second end of the first LC parallel circuit is grounded.
  • the second pole generating circuit includes a second transmission line and a fourth capacitor, the first end of the second transmission line is connected to the first end of the second capacitor, and the connection point is connected to the second end of the connection circuit and the second coupling unit, the second end of the second transmission line is connected to the first end of the fourth capacitor, and the second end of the fourth capacitor is grounded.
  • the second pole generating circuit includes a second LC parallel circuit and a fourth capacitor, the first end of the second LC parallel circuit is connected to the first end of the second capacitor, and the connection point is connected to the second end of the connection circuit and the second coupling unit, the second end of the second LC parallel circuit is connected to the first end of the fourth capacitor, and the second end of the fourth capacitor is grounded.
  • the second pole generating circuit includes a second LC parallel circuit and a fourth capacitor, the first end of the second LC parallel circuit is connected to the first end of the fourth capacitor, the second end of the fourth capacitor is connected to the first end of the second capacitor, and the connection point is connected to the second end of the connection circuit and the second coupling unit, and the second end of the second LC parallel circuit is grounded.
  • connection circuit includes a capacitor, and the frequency of the first pole and the frequency of the second pole are both lower than the frequency of the resonance point.
  • connection circuit includes an LC parallel circuit or a transmission line, and the frequency of the first pole and the frequency of the second pole are both higher than the frequency of the resonance point.
  • the first coupling unit includes a coupling capacitor
  • the second coupling unit includes a coupling capacitor
  • the superconducting quantum bit readout device further includes a controller, which is used to adjust the control signal loaded into the filter readout cavity to adjust the frequency of the resonance point and the frequency of the pole.
  • a controller which is used to adjust the control signal loaded into the filter readout cavity to adjust the frequency of the resonance point and the frequency of the pole.
  • an adjustable inductor or capacitor may be used in the filter readout cavity, and the controller outputs a control signal to the filter readout cavity, and the control signal may specifically be a bias current or a bias voltage.
  • the controller may adjust the capacitance or inductance in the filter readout cavity by changing the control signal, thereby adjusting the frequency of the resonance point and the frequency of the pole in the S21 frequency response curve, thereby achieving dynamic adjustment of the frequency of the resonance point and the frequency of the pole.
  • an embodiment of the present application provides a superconducting quantum chip.
  • the superconducting quantum chip includes a plurality of superconducting quantum bit readout devices as described in any embodiment of the first aspect above, wherein the plurality of superconducting quantum bit readout devices are distributed in an array, and each two adjacent superconducting quantum bit readout devices are coupled to each other.
  • an embodiment of the present application provides a quantum computer.
  • the quantum computer includes: a dilution refrigerator, a measurement and control system, and a superconducting quantum chip as described in the second aspect above.
  • the dilution refrigerator is used to provide a low-temperature environment.
  • the measurement and control system is used to manipulate the state of the quantum bit to perform computing operations and read the state of the quantum bit.
  • the superconducting quantum chip is placed in a low-temperature environment, and the measurement and control system controls the microwave source and modulates the pulse signal according to the requirements of the computing operation, inputs a series of microwave pulse sequences into the superconducting quantum chip, and operates the bit quantum state. After all operations are completed, the measurement and control system outputs a measurement pulse signal to the superconducting quantum chip, obtains the state of the superconducting quantum bit through the returned signal, and obtains the calculation result.
  • the filter readout cavity allows the readout signal to be transmitted to the readout line, and suppresses the microwave photons in the quantum state from being transmitted to the readout line through the filter readout cavity, avoiding the microwave photons in the quantum state from being dissipated through the filter readout cavity, and also avoiding the shortening of the relaxation time of the bit. Therefore, the present application can accelerate the readout speed of the signal to improve the readout fidelity while ensuring that the bit relaxation time is not shortened, or, if the coupling strength of the filter readout cavity and the readout line is maintained, the bit relaxation time can be extended while the readout speed is unchanged. In other words, the present application takes into account the two factors of readout fidelity and bit relaxation time.
  • the filter readout cavity provided by the present application is an integrated device, and the overall size of the device is relatively small, and the filter channel will not affect the readout channel, and the readout signal will not be affected while filtering is realized.
  • FIG1 is a schematic diagram of a structure of a quantum computer
  • FIG2 is a schematic diagram of a structure of a superconducting quantum chip
  • FIG3 is a schematic diagram of a first structure of a superconducting quantum bit readout device in an embodiment of the present application
  • FIG4 is a first schematic diagram of an S21 frequency response curve in an embodiment of the present application.
  • FIG5 is a schematic diagram of a second structure of a superconducting quantum bit readout device in an embodiment of the present application.
  • FIG6 is a second schematic diagram of an S21 frequency response curve in an embodiment of the present application.
  • FIG7 is a schematic diagram of a third structure of a superconducting quantum bit readout device in an embodiment of the present application.
  • FIG8 is a third schematic diagram of the S21 frequency response curve in the embodiment of the present application.
  • FIG9 is a schematic diagram of a fourth structure of a superconducting quantum bit readout device in an embodiment of the present application.
  • FIG10 is a fifth structural schematic diagram of a superconducting quantum bit readout device in an embodiment of the present application.
  • FIG11 is a sixth structural schematic diagram of a superconducting quantum bit readout device in an embodiment of the present application.
  • FIG12 is a schematic diagram of several structures of pole generation circuits in an embodiment of the present application.
  • FIG13 is a schematic diagram of several structures of connection circuits in an embodiment of the present application.
  • FIG14 is a fourth schematic diagram of the S21 frequency response curve in the embodiment of the present application.
  • FIG15 is a fifth schematic diagram of the S21 frequency response curve in the embodiment of the present application.
  • FIG16 is a seventh structural schematic diagram of a superconducting quantum bit readout device in an embodiment of the present application.
  • FIG17 is a schematic diagram of several structures of connection circuits in an embodiment of the present application.
  • FIG18 is a sixth schematic diagram of the S21 frequency response curve in the embodiment of the present application.
  • FIG19 is a seventh schematic diagram of the S21 frequency response curve in the embodiment of the present application.
  • FIG. 20 is a schematic diagram of the eighth structure of the superconducting quantum bit readout device in an embodiment of the present application.
  • the embodiments of the present application provide a superconducting quantum bit readout device, a superconducting quantum chip and a quantum computer, which not only ensure the fidelity of the readout signal, but also avoid the shortening of the relaxation time of the bit.
  • the terms "first”, “second”, etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described here can be implemented in an order other than that illustrated or described here.
  • Superconducting quantum computing is a quantum computing solution based on superconducting circuits.
  • Superconducting circuits are microwave circuits composed of basic components such as capacitors, inductors, transmission lines, and Josephson junctions.
  • Superconducting circuit chips work in an ultra-low temperature environment provided by a dilution refrigerator to achieve superconductivity.
  • Superconducting quantum circuits are highly compatible with existing integrated circuit technologies in terms of design, preparation, and measurement. The energy levels and couplings of quantum bits can be designed and controlled very flexibly, and have great potential for scalability. The following is an introduction to quantum computers in superconducting quantum computing scenarios.
  • FIG1 is a schematic diagram of the structure of a quantum computer.
  • the quantum computer includes: a dilution refrigerator 1 for providing a low-temperature environment, a superconducting quantum chip 2 for realizing a quantum computing information carrier, and a measurement and control system 3 for manipulating the state of quantum bits for computing operations and reading the state of quantum bits.
  • the superconducting quantum chip 2 is placed in a low-temperature environment, and the measurement and control system 3 controls the microwave source and modulates the pulse signal according to the needs of the computing operation, inputs a series of microwave pulse sequences into the superconducting quantum chip 2, and operates the bit quantum state.
  • the measurement and control system 3 outputs a measurement pulse signal to the superconducting quantum chip 2, obtains the state of the superconducting quantum bit through the returned signal, and obtains the calculation result.
  • FIG2 is a schematic diagram of a structure of a superconducting quantum chip.
  • the superconducting quantum chip includes a plurality of superconducting quantum bit readout devices 31 arranged in a two-dimensional array and a coupler 32 for coupling the plurality of superconducting quantum bit readout devices.
  • the two-dimensional array arrangement shown in FIG2 is only a specific example. In practical applications, the superconducting quantum chip may also be arranged in other forms, which will not be described in detail here. limited.
  • FIG3 is a schematic diagram of the first structure of the superconducting quantum bit readout device in the embodiment of the present application.
  • the superconducting quantum bit readout device includes: a filter readout cavity 10, a superconducting quantum bit unit 20, a readout line 30, a first coupling unit 40 and a second coupling unit 50.
  • the filter readout cavity 10 is coupled to the superconducting quantum bit unit 20 through the first coupling unit 40
  • the filter readout cavity 10 is coupled to the readout line 30 through the second coupling unit 50.
  • the filter readout cavity 10, the first coupling unit 40 and the second coupling unit 50 can all be a circuit network composed of capacitors, inductors, transmission lines, or a combination thereof, wherein the capacitors and inductors can be fixed or adjustable. It should be understood that the filter readout cavity 10 can be regarded as a resonant cavity for reading out the state of a superconducting quantum bit, and the filter readout cavity 10 can also perform reflective filtering on the superconducting quantum bit.
  • the superconducting quantum bit unit 20 is used to store microwave photons in a quantum state, and the quantum state of the microwave photons is used to encode quantum information, which can reflect the state of the superconducting quantum bit, that is, the physical entity of the superconducting quantum bit is the microwave photons that carry quantum information, and the microwave photons in the quantum state can be coupled to the filter readout cavity 10 through the first coupling unit 40.
  • the microwave photons in the classical state on the readout line 30 first enter the filter readout cavity 10, and then return to the readout line 30 after modulation and carry the information of the state of the superconducting quantum bit.
  • the present application refers to the signal transmitted from the readout line 30 to the filter readout cavity 10 as a "read-in signal”, and the signal transmitted from the filter readout cavity 10 to the readout line 30 as a "readout signal”.
  • the filter readout cavity 10 modulates the read-in signal according to the quantum state of the microwave photon to obtain a readout signal, and transmits the readout signal to the readout line 30. It should be understood that the state of the superconducting quantum bit reflected by the readout signal will collapse to the 0 state or the 1 state, so it is possible to determine whether the state of the superconducting quantum bit is the 0 state or the 1 state according to the readout signal, that is, the information of the state of the superconducting quantum bit.
  • the filter readout cavity 10 is also used to reflectively filter the microwave photons in the quantum state from the superconducting quantum bit unit 20, thereby suppressing the microwave photons in the quantum state from being transmitted through the filter readout cavity 10 to the readout line 30.
  • the S21 frequency response curve corresponding to the partial structure including the filter readout cavity 10, the first coupling unit 40 and the second coupling unit 50 includes at least one resonance point (mode) and at least one pole (pole).
  • the resonance point refers to the frequency point where the attenuation dB tends to zero in the S21 frequency response curve of the circuit
  • the pole refers to the frequency point where the attenuation dB tends to negative infinity in the S21 frequency response curve of the circuit.
  • FIG4 is a first schematic diagram of the S21 frequency response curve in an embodiment of the present application.
  • the frequency difference between the readout signal and the resonance point is less than the first preset value
  • the frequency difference between the read-in signal and the resonance point is less than the second preset value
  • the frequency difference between the microwave photon in the quantum state and the pole is less than the second preset value.
  • the first preset value is 20MHz
  • the second preset value is 4GHz.
  • the present application makes the frequency of the resonance point equal to or close to the frequency of the readout signal and the read-in signal by design, and makes the frequency of the microwave photon in the quantum state equal to or close to the frequency of the pole, and the frequency of the resonance point has a large detuning with the frequency of the pole.
  • the resonance point represents a microwave mode
  • the read-in signal can be input into the filter readout cavity 10 by the readout line 30, and the readout signal can be output from the filter readout cavity 10 to the readout line.
  • the pole represents a microwave blocking point, and the microwave photon in the quantum state is reflected by the filter readout cavity 10, so that it cannot be transmitted to the readout line 30 through the filter readout cavity 10.
  • the filter readout cavity allows the readout signal to be transmitted to the readout line, and suppresses the microwave photons in the quantum state from being transmitted to the readout line through the filter readout cavity, thereby avoiding the microwave photons in the quantum state from being dissipated through the filter readout cavity, and thus avoiding the shortening of the relaxation time of the bit. Therefore, the present application can accelerate the readout speed of the signal to improve the readout fidelity while ensuring that the bit relaxation time is not shortened, or, if the coupling strength of the filter readout cavity and the readout line is maintained, the bit relaxation time can be extended while the readout speed remains unchanged.
  • the present application takes into account the two factors of readout fidelity and bit relaxation time.
  • the filter readout cavity provided by the present application is an integrated device, and the overall size of the device is relatively small, and the filter channel will not affect the readout channel, and will not affect the readout signal while realizing filtering.
  • the structure of the filter readout cavity includes but is not limited to the examples provided below. As long as the structure allows the readout signal to pass through and can block microwave photons in a quantum state, it is within the protection scope of this application.
  • FIG5 is a schematic diagram of the second structure of the superconducting quantum bit readout device in the embodiment of the present application.
  • the filter readout cavity 10 includes an inductor 101, a capacitor 102, a capacitor 103 and a capacitor 104.
  • the first end of the inductor 101 is connected to the first coupling unit 40 and the second coupling unit 50, and the connection point is connected to the first end of the capacitor 102 and the first end of the capacitor 103, the second end of the capacitor 102 is grounded, the second end of the inductor 101 is connected to the second end of the capacitor 103, and the connection point is connected to the first end of the capacitor 104, and the second end of the capacitor 104 is grounded.
  • the first coupling unit 40 and the second coupling unit 50 use coupling capacitors.
  • Figure 6 is a second schematic diagram of the S21 frequency response curve in the embodiment of the present application.
  • Figure 6 shows the S21 frequency response curve corresponding to the embodiment shown in Figure 5 above. It can be seen that in this embodiment, the frequency of the resonance point is greater than the frequency of the pole.
  • FIG7 is a schematic diagram of the third structure of the superconducting quantum bit readout device in the embodiment of the present application.
  • the filter readout cavity 10 includes an inductor 101, a capacitor 102, a capacitor 103 and a capacitor 104.
  • the first end of the inductor 101 is connected to the first coupling unit 40, and the connection point is connected to the first end of the capacitor 102 and the first end of the capacitor 103, the second end of the capacitor 102 is grounded, the second end of the inductor 101 is connected to the second coupling unit 50, and the connection point is connected to the first end of the capacitor 103 and the second end of the capacitor 104, and the second end of the capacitor 104 is grounded.
  • the first coupling unit 40 and the second coupling unit 50 use coupling capacitors.
  • Figure 8 is a third schematic diagram of the S21 frequency response curve in the embodiment of the present application.
  • Figure 8 shows the S21 frequency response curve corresponding to the embodiment shown in Figure 7 above. It can be seen that in this embodiment, the frequency of the resonance point is less than the frequency of the pole.
  • the filter readout cavity 10 adopts a lumped floating design, and the filter readout cavity 10 is mainly composed of a capacitor and an inductor in parallel, and both ends of the parallel circuit are grounded through capacitors.
  • the embodiment shown in FIG. 5 is a same-end coupling design, that is, the superconducting quantum bit unit 20 and the readout line 30 are coupled to the same end of the filter readout cavity 10.
  • the embodiment shown in FIG. 7 is a heterodyne coupling design, that is, the superconducting quantum bit unit 20 and the readout line 30 are coupled to different ends of the filter readout cavity 10.
  • the capacitance size in the filter readout cavity 10 in the embodiments shown in FIG. 5 and FIG. 7 is about 1fF to 1pF, and the inductance size is about 0.1nH to 30nH. It should be understood that the resonance point and pole shown in FIG. 6 and FIG. 8 are only examples, and the frequency of the resonance point and the frequency of the pole can be flexibly adjusted by changing the size of the capacitance and/or inductance in the filter readout cavity 10.
  • the embodiments shown in Figures 5 and 7 above can be made smaller and more integrated due to the use of a lumped design.
  • the heterodyne coupling design shown in Figure 7 facilitates the operation of resetting the superconducting quantum bit unit. It should be understood that after completing a quantum calculation, the microwave photons in the quantum state need to be restored to the 0 state to facilitate the next quantum calculation, and it takes a certain amount of time for the microwave photons in the quantum state to return to the 0 state.
  • the frequency of the resonance point is less than the frequency of the pole, which is convenient for downward adjustment of the frequency of the pole so that the frequency of the pole is close to the frequency of the resonance point, then the microwave photons in the quantum state can pass through the filter readout cavity 10 and be transmitted to the readout line 30, so that the microwave photons in the quantum state are restored to the 0 state, completing the operation of resetting the superconducting quantum bit unit, which helps to improve the efficiency of the system.
  • Fig. 9 is a schematic diagram of the fourth structure of the superconducting quantum bit readout device in the embodiment of the present application.
  • the filter readout cavity 10 includes a pole generation circuit 11, a connection circuit 12 and a connection circuit 13, the first end of the connection circuit 12 is connected to the first coupling unit 40, the first end of the connection circuit 13 is connected to the second coupling unit 50, the second end of the connection circuit 12 is connected to the second end of the connection circuit 13, and the connection point is connected to the pole generation circuit 11.
  • the first coupling unit 40 and the second coupling unit 50 use coupling capacitors.
  • FIG10 is a fifth structural schematic diagram of the superconducting quantum bit readout device in the embodiment of the present application.
  • the filter readout cavity 10 may not include the connection circuit 12 and the connection circuit 13, that is, the pole generation circuit 11 is directly connected to the first coupling unit 40 and the second coupling unit 50.
  • the filter readout cavity 10 may also include only the connection circuit 12 or the connection circuit 13, and no drawings are provided here for display.
  • Fig. 11 is a sixth structural schematic diagram of the superconducting quantum bit readout device in the embodiment of the present application. As shown in Fig. 11, different from the structures shown in Fig. 9 and Fig. 10, the first coupling unit 40 uses a coupling capacitor and the second coupling unit 50 uses a coupling inductor.
  • the frequency of the pole depends on the pole generating circuit 11.
  • the frequency of the resonance point can be made greater than the frequency of the pole, or the frequency of the resonance point can be made less than the frequency of the pole.
  • the structure of the pole generating circuit 11 includes but is not limited to the example provided in FIG. 12 , and those skilled in the art can flexibly transform the above examples, which will not be shown one by one here.
  • FIG12 is a schematic diagram of several structures of the pole generation circuit in the embodiment of the present application.
  • the pole generation circuit 11 includes a transmission line 111 and a capacitor 112, the first end of the transmission line 111 is connected to the second end of the connection circuit 12 and the second end of the connection circuit 13, the second end of the transmission line 111 is connected to the first end of the capacitor 112, and the second end of the capacitor 112 is grounded.
  • the pole generation circuit 11 includes an LC parallel circuit 113 and a capacitor 112, the first end of the LC parallel circuit 113 is connected to the second end of the connection circuit 12 and the second end of the connection circuit 13, the second end of the LC parallel circuit is connected to the first end of the capacitor 112, and the second end of the capacitor 112 is grounded.
  • the pole generating circuit 11 includes an LC parallel circuit 113 and a capacitor 112, wherein a first end of the LC parallel circuit 113 is connected to a first end of the capacitor 112, a second end of the capacitor 112 is connected to a second end of the connection circuit 12 and a second end of the connection circuit 13, and a second end of the LC parallel circuit 113 is grounded.
  • the capacitors shown in the dotted boxes in Examples B and C of FIG12 are unavoidable parasitic capacitors.
  • FIG13 is a schematic diagram of several structures of the connection circuit in the embodiment of the present application.
  • the connection circuit 12 can adopt an LC parallel circuit or a transmission line
  • the connection circuit 13 can adopt an LC parallel circuit or a transmission line.
  • the capacitance in the LC parallel circuit is an unavoidable parasitic capacitance.
  • the capacitance is about 1fF to 1pF
  • the inductance is about 0.1nH to 30nH
  • the transmission line length is about 0 to 25mm.
  • FIG14 is a fourth schematic diagram of the S21 frequency response curve in the embodiment of the present application.
  • FIG14 shows the S21 frequency response curve corresponding to the embodiment shown in FIG9 or FIG10 above.
  • the pole generating circuit 11 is designed so that the frequency of the resonance point is greater than the frequency of the pole.
  • the pole generating circuit 11 is designed so that the frequency of the resonance point is less than the frequency of the pole. Taking the example A shown in FIG12 as an example of the pole generating circuit 11, the frequency of the resonance point and the frequency of the pole can be adjusted by changing the length of the transmission line 111 and/or the size of the capacitor 112.
  • Figure 15 is a fifth schematic diagram of the S21 frequency response curve in the embodiment of the present application.
  • Figure 15 shows the S21 frequency response curve corresponding to the embodiment shown in Figure 11 above. It can be seen that in this embodiment, the frequency of the resonance point is less than the frequency of the pole.
  • FIG16 is a seventh structural schematic diagram of a superconducting quantum bit readout device in an embodiment of the present application.
  • the filter readout cavity 10 includes a pole generating circuit 11, a pole generating circuit 14, a connecting circuit 15, a capacitor 105, and a capacitor 106.
  • the first end of the connecting circuit 15 is connected to the first coupling unit 40, and the connecting point is connected to the pole generating circuit 11 and the first end of the capacitor 105, the second end of the capacitor 105 is grounded, the second end of the connecting circuit 15 is connected to the second coupling unit 50, and the connecting point is connected to the pole generating circuit 14 and the first end of the capacitor 106, and the second end of the capacitor 106 is grounded.
  • the first coupling unit 40 and the second coupling unit 50 use coupling capacitors. It should be understood that capacitors 105 and 106 are unavoidable parasitic capacitors.
  • the S21 frequency response curve corresponding to the embodiment shown in FIG16 includes pole 1 and pole 2, wherein the frequency of pole 1 depends on pole generating circuit 11, and the frequency of pole 2 depends on pole generating circuit 14.
  • Pole generating circuit 11 and pole generating circuit 14 can both adopt the several structures shown in FIG12 above, which are not specifically limited here.
  • Fig. 17 is a schematic diagram of several structures of the connection circuit in the embodiment of the present application.
  • the connection circuit 15 can adopt an LC parallel circuit, a transmission line or a capacitor. It should be understood that the capacitor in the LC parallel circuit is an unavoidable parasitic capacitor.
  • the capacitance in the filter readout cavity 10 is about 1fF to 1pF
  • the inductance is about 0.1nH to 30nH
  • the transmission line length is about 0 to 25mm.
  • Figure 18 is a sixth schematic diagram of the S21 frequency response curve in the embodiment of the present application.
  • Figure 18 shows the S21 frequency response curve corresponding to the capacitor used in the connection circuit 15 in the embodiment shown in Figure 16 above. It can be seen that in this embodiment, the frequency of pole 1 and the frequency of pole 2 are both lower than the frequency of the resonance point.
  • FIG19 is a seventh schematic diagram of the S21 frequency response curve in the embodiment of the present application.
  • FIG19 shows the S21 frequency response curve corresponding to the connection circuit 15 using an LC parallel circuit or a transmission line in the embodiment shown in FIG16 above. It can be seen that in this embodiment, the frequency of pole 1 and the frequency of pole 2 are both greater than the frequency of the resonance point.
  • the pole generation circuit 11 and the pole generation circuit 14 can be designed so that the frequencies of poles 1 and pole 2 are close, so that the filtering intervals covered by the two poles are connected to form a larger filtering interval, such as around 4.5 GHz to 5.5 GHz in FIG18 and around 5.5 GHz to 6.7 GHz in FIG19. If the frequencies of the two poles are made the same in design, then compared with the case of a single pole, the filtering effect of the embodiment shown in FIG16 will become stronger due to the superposition of the two poles. In addition, the frequencies of the two poles and the resonance point can be flexibly adjusted through pole generation circuits of different designs to meet the needs of different scenarios, for example, by designing to facilitate the operation of resetting the superconducting quantum bit unit.
  • the number of pole generating circuits in the filter readout cavity 10 can be further expanded to achieve more poles.
  • the specific implementation method is known to those skilled in the art and will not be repeated here.
  • FIG20 is a schematic diagram of the eighth structure of the superconducting quantum bit readout device in the embodiment of the present application.
  • the superconducting quantum bit readout device further includes a controller 60.
  • An adjustable inductor or capacitor may be used in the filter readout cavity 10.
  • a superconducting quantum interference device SQUID
  • the loop device can generally be used as an adjustable inductor.
  • the inductance of the SQUID can be changed by changing the magnetic flux in the SQUID loop.
  • the controller 60 outputs a control signal to the filter readout cavity 10.
  • the control signal can specifically be a bias current or a bias voltage.
  • the control can adjust the capacitance or inductance in the filter readout cavity 10 by changing the control signal, thereby adjusting the frequency of the resonance point and the frequency of the pole in the S21 frequency response curve, thereby achieving dynamic adjustment of the frequency of the resonance point and the frequency of the pole.

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Abstract

本申请公开了一种超导量子比特读出装置、超导量子芯片和量子计算机，既保证了读出信号的保真度，又避免了比特的弛豫时间缩短。该超导量子比特读出装置包括：超导量子比特单元、滤波读出腔、读出线、第一耦合单元和第二耦合单元。滤波读出腔通过第一耦合单元与超导量子比特单元耦合，滤波读出腔通过第二耦合单元与读出线耦合。超导量子比特单元用于存储处于量子态的微波光子。读出线用于将读入信号传输至滤波读出腔。滤波读出腔用于根据微波光子的量子态对读入信号进行调制得到读出信号，并将读出信号传输至读出线。滤波读出腔还用于对处于量子态的微波光子进行过滤，以抑制处于量子态的微波光子透过滤波读出腔传输至读出线。

Description

一种超导量子比特读出装置、超导量子芯片和量子计算机
本申请要求于2022年10月31日提交中国国家知识产权局、申请号为202211347857.1、申请名称为“一种超导量子比特读出装置、超导量子芯片和量子计算机”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种超导量子比特读出装置、超导量子芯片和量子计算机。
背景技术
量子计算是基于量子力学利用量子叠加和纠缠的等特性的一种新型计算方式。在一些特定问题，如大数分解、量子化学模拟上量子计算相比于经典计算理论上有着指数级加速的优势。超导量子比特目前是最有希望实现量子计算的物理系统之一。目前超导量子比特读出的主流方案是将一个线性谐振腔色散耦合到超导比特，然后通过探测谐振腔的响应而读取比特的状态。这类用于读出比特的谐振腔又被称作读出腔。读出腔与读出线一般通过电容或者互感耦合。读出线上用于探测读出腔响应的微波光子会先进入读出腔，然后再回到读出线并携带着比特状态的信息。
一般来说，读出腔与读出线的耦合越强，微波光子进出读出腔的速度越快也就是读出时间越短。由于超导量子比特具有有限的弛豫时间，读出时间越短，比特在读出时间内状态因为弛豫发生改变的概率越小，从而读出保真度就越高。因而，从读出保真度的角度来讲，读出腔与读出线的耦合越强越好。但是，由于比特本身也耦合到了读出腔，比特会透过读出腔耗散到到读出线这个带有损耗的环境中从而引起比特的弛豫时间缩短，这个效应被称为Purcell效应。从比特的弛豫时间的角度来讲，读出腔与读出线的耦合越弱越好。因而，读出保真度与比特弛豫时间是一对相互矛盾的因素。
发明内容
本申请实施例提供了一种超导量子比特读出装置、超导量子芯片和量子计算机，既保证了读出信号的保真度，又避免了比特的弛豫时间缩短。
第一方面，本申请实施例提供了一种超导量子比特读出装置。该超导量子比特读出装置包括：超导量子比特单元、滤波读出腔、读出线、第一耦合单元和第二耦合单元。滤波读出腔通过第一耦合单元与超导量子比特单元耦合，滤波读出腔通过第二耦合单元与读出线耦合。超导量子比特单元用于存储处于量子态的微波光子。读出线用于将读入信号传输至滤波读出腔。滤波读出腔用于根据微波光子的量子态对读入信号进行调制得到读出信号，并将读出信号传输至读出线。滤波读出腔还用于对处于量子态的微波光子进行过滤，以抑制处于量子态的微波光子透过滤波读出腔传输至读出线。
在该实施方式中，滤波读出腔允许读出信号传输至读出线，并抑制处于量子态的微波光子透过滤波读出腔传输到读出线，避免了处于量子态的微波光子透过滤波读出腔而耗散，也就避免了比特的弛豫时间缩短。因此，本申请可以在保证比特弛豫时间不缩短的情况下，加速信号的读出速度从而提升读出保真度，或者，如果保持滤波读出腔与读出线的耦合强度，可以在读出速度不变的情况下，延长比特弛豫时间。也就是说，本申请兼顾了读出保真度与比特弛豫时间这两个因素。另外，本申请提供的滤波读出腔是一个集成器件，器件的整体尺寸较小，滤波通道不会影响读出通道，在实现滤波的同时不会对读出信号造成影响。
在一些可能的实施方式中，包括滤波读出腔、第一耦合单元和第二耦合单元的结构所对应的S21频率响应曲线包括至少一个谐振点和至少一个极点，读出信号与谐振点的频率差值小于第一预设值，处于量子态的微波光子与极点的频率差值小于第二预设值。例如，第一预设值为20MHz，第二预设值为4GHz。应理解，谐振点表示一种微波模式，读入信号可以由读出线输入到滤波读出腔，并且，读出信号可以由滤波读出腔输出到读出线。极点表示微波阻断点，处于量子态的微波光子被滤波读出腔反射，从而无法透过滤波 读出腔传输到读出线，避免了处于量子态的微波光子透过滤波读出腔而耗散，也就避免了比特的弛豫时间缩短。
在一些可能的实施方式中，滤波读出腔包括电感、第一电容、第二电容和第三电容。电感的第一端与第一耦合单元和第二耦合单元连接、且连接点与第一电容的第一端和第二电容的第一端连接，第一电容的第二端接地，电感的第二端与第二电容的第二端连接、且连接点与第三电容的第一端连接，第三电容的第二端接地。谐振点的频率大于极点的频率。
在该实施方式中，滤波读出腔采用了集总浮地式设计，滤波读出腔主要由一个电容和一个电感并联而成，该并联电路两端均通过电容接地，超导量子比特单元和读出线耦合到滤波读出腔的同一端。由于采用了集总的设计可以将尺寸做的更小，集成度更高。
在一些可能的实施方式中，滤波读出腔包括电感、第一电容、第二电容和第三电容。电感的第一端与第一耦合单元连接、且连接点与第一电容的第一端和第二电容的第一端连接，第一电容的第二端接地，电感的第二端与第二耦合单元连接、且连接点与第三电容的第一端和第二电容的第二端连接，第三电容的第二端接地。谐振点的频率小于极点的频率。
在该实施方式中，滤波读出腔采用了集总浮地式设计，滤波读出腔主要由一个电容和一个电感并联而成，该并联电路两端均通过电容接地，超导量子比特单元和读出线耦合到滤波读出腔的不同端。由于采用了集总的设计可以将尺寸做的更小，集成度更高。并且，由于谐振点的频率小于极点的频率，便于向下调节极点的频率，使得极点的频率与谐振点的频率接近，那么处于量子态的微波光子可以穿过滤波读出腔传输至读出线，从而处于量子态的微波光子恢复到0态，完成超导量子比特单元重置的操作，有助于提升系统的效率。
在一些可能的实施方式中，第一耦合单元包括耦合电容，第二耦合单元包括耦合电容，增强了本方案的可实现性。
在一些可能的实施方式中，滤波读出腔包括极点生成电路、第一连接电路和第二连接电路。第一连接电路的第一端与第一耦合单元连接，第二连接电路的第一端与第二耦合单元连接，第一连接电路的第二端与第二连接电路的第二端连接、且连接点与极点生成电路连接。极点的频率取决于极点生成电路，谐振点的频率大于极点的频率，或者，谐振点的频率小于极点的频率。
在该实施方式中，采用了分布式腔的设计，从微纳加工的角度看更容易获得更高的品质因子。通过不同设计的极点生成电路可以灵活调节极点和谐振点的频率，从而满足不同场景的需求，例如，通过设计以便于实现超导量子比特单元重置的操作。
在一些可能的实施方式中，极点生成电路包括第三传输线和第一电容，第三传输线的第一端与第一连接电路的第二端和第二连接电路的第二端连接，第三传输线的第二端与第一电容的第一端连接，第一电容的第二端接地。或者，极点生成电路包括LC并联电路和第一电容，LC并联电路的第一端与第一连接电路的第二端和第二连接电路的第二端连接，LC并联电路的第二端与第一电容的第一端连接，第一电容的第二端接地。或者，极点生成电路包括LC并联电路和第一电容，LC并联电路的第一端与第一电容的第一端连接，第一电容的第二端与第一连接电路的第二端和第二连接电路的第二端连接，LC并联电路的第二端接地。该实施方式提供了极点生成电路的多种实现方式，提高了本方案的扩展性。
在一些可能的实施方式中，第一连接电路包括LC并联电路或传输线，第二连接电路包括LC并联电路或传输线。该实施方式提供了第一连接电路和第二连接电路的多种实现方式，提高了本方案的灵活性。
在一些可能的实施方式中，第一耦合单元包括耦合电容，第二耦合单元包括耦合电容。或者，第一耦合单元包括耦合电容，第二耦合单元包括耦合电感。该实施方式提供了第一耦合单元和第二耦合单元的多种实现方式，便于根据实际需求选择不同的耦合方式。
在一些可能的实施方式中，滤波读出腔包括第一极点生成电路、第二极点生成电路、连接电路、第一电容和第二电容。连接电路的第一端与第一耦合单元连接、且连接点与第一极点生成电路和第一电容的第一端连接，第一电容的第二端接地，连接电路的第二端与第二耦合单元连接、且连接点与第二极点生成电路和第二电容的第一端连接，第二电容的第二端接地。S21频率响应曲线包括第一极点和第二极点，第一极点的频率取决于第一极点生成电路，第二极点的频率取决于第二极点生成电路。
该实施方式中，由于极点数量增加到2个，滤波带宽显著提升。可以通过设计极点生成电路11和极点生成电路14，使得第一极点与第二极点的频率接近，从而实现两个极点覆盖的滤波区间连接起来形成一个更大的滤波区间。如果在设计上将两个极点的频率做到相同，那么相较于单极点的情况，滤波效果会由于两个极点的叠加变得更强。并且，通过不同设计的极点生成电路可以灵活调节两个极点和谐振点的频率，从而满足不同场景的需求，例如，通过设计以便于实现超导量子比特单元重置的操作。
在一些可能的实施方式中，第一极点生成电路包括第一传输线和第三电容，第一传输线的第一端与第一电容的第一端连接、且连接点与连接电路的第一端和第一耦合单元连接，第一传输线的第二端与第三电容的第一端连接，第三电容的第二端接地。或者，第一极点生成电路包括第一LC并联电路和第三电容，第一LC并联电路的第一端与第一电容的第一端连接、且连接点与连接电路的第一端和第一耦合单元连接，第一LC并联电路的第二端与第三电容的第一端连接，第三电容的第二端接地。或者，第一极点生成电路包括第一LC并联电路和第三电容，第一LC并联电路的第一端与第三电容的第一端连接，第三电容的第二端与第一电容的第一端连接、且连接点与连接电路的第一端和第一耦合单元连接，第一LC并联电路的第二端接地。
在一些可能的实施方式中，第二极点生成电路包括第二传输线和第四电容，第二传输线的第一端与第二电容的第一端连接、且连接点与连接电路的第二端和第二耦合单元连接，第二传输线的第二端与第四电容的第一端连接，第四电容的第二端接地。或者，第二极点生成电路包括第二LC并联电路和第四电容，第二LC并联电路的第一端与第二电容的第一端连接、且连接点与连接电路的第二端和第二耦合单元连接，第二LC并联电路的第二端与第四电容的第一端连接，第四电容的第二端接地。或者，第二极点生成电路包括第二LC并联电路和第四电容，第二LC并联电路的第一端与第四电容的第一端连接，第四电容的第二端与第二电容的第一端连接、且连接点与连接电路的第二端和第二耦合单元连接，第二LC并联电路的第二端接地。
在一些可能的实施方式中，连接电路包括电容，第一极点的频率和第二极点的频率都小于谐振点的频率。或者，连接电路包括LC并联电路或传输线，第一极点的频率和第二极点的频率都大于谐振点的频率。该实施方式提供了连接电路的多种实施方式，便于根据实际需求选择不同的连接电路。
在一些可能的实施方式中，第一耦合单元包括耦合电容，第二耦合单元包括耦合电容。
在一些可能的实施方式中，超导量子比特读出装置还包括控制器，控制器用于调节加载到滤波读出腔的控制信号，以调节谐振点的频率和极点的频率。例如，滤波读出腔中可以采用可调的电感或电容，控制器向滤波读出腔输出控制信号，该控制信号具体可以是偏置电流或偏置电压，控制通过改变控制信号可以调节滤波读出腔中的电容或电感，从而调节S21频率响应曲线中谐振点的频率和极点的频率，实现了谐振点的频率和极点的频率动态可调。
第二方面，本申请实施例提供了一种超导量子芯片。该超导量子芯片包括多个如上述第一方面任一实施方式介绍的超导量子比特读出装置，多个超导量子比特读出装置呈阵列分布，每相邻两个超导量子比特读出装置相互耦合。
第三方面，本申请实施例提供了一种量子计算机。该量子计算机包括：稀释制冷机、测控系统和如上述第二方面介绍的超导量子芯片。稀释制冷机用于提供低温环境。测控系统用于操控量子比特状态进行计算操作和读取量子比特状态。超导量子芯片置于低温环境中，测控系统按照计算操作的需求控制微波源以及调制脉冲信号，将一系列微波脉冲序列输入到超导量子芯片，对比特量子态进行操作。所有操作完成后，测控系统再输出测量脉冲信号到超导量子芯片，通过返回的信号获取超导量子比特的状态，得到计算结果。
本申请实施例中，滤波读出腔允许读出信号传输至读出线，并抑制处于量子态的微波光子透过滤波读出腔传输到读出线，避免了处于量子态的微波光子透过滤波读出腔而耗散，也就避免了比特的弛豫时间缩短。因此，本申请可以在保证比特弛豫时间不缩短的情况下，加速信号的读出速度从而提升读出保真度，或者，如果保持滤波读出腔与读出线的耦合强度，可以在读出速度不变的情况下，延长比特弛豫时间。也就是说，本申请兼顾了读出保真度与比特弛豫时间这两个因素。另外，本申请提供的滤波读出腔是一个集成器件，器件的整体尺寸较小，滤波通道不会影响读出通道，在实现滤波的同时不会对读出信号造成影响。
附图说明
图1为量子计算机的一种结构示意图；
图2为超导量子芯片的一种结构示意图；
图3为本申请实施例中超导量子比特读出装置的第一种结构示意图；
图4为本申请实施例中S21频率响应曲线的第一种示意图；
图5为本申请实施例中超导量子比特读出装置的第二种结构示意图；
图6为本申请实施例中S21频率响应曲线的第二种示意图；
图7为本申请实施例中超导量子比特读出装置的第三种结构示意图；
图8为本申请实施例中S21频率响应曲线的第三种示意图；
图9为本申请实施例中超导量子比特读出装置的第四种结构示意图；
图10为本申请实施例中超导量子比特读出装置的第五种结构示意图；
图11为本申请实施例中超导量子比特读出装置的第六种结构示意图；
图12为本申请实施例中极点生成电路的几种结构示意图；
图13为本申请实施例中连接电路的几种结构示意图；
图14为本申请实施例中S21频率响应曲线的第四种示意图；
图15为本申请实施例中S21频率响应曲线的第五种示意图；
图16为本申请实施例中超导量子比特读出装置的第七种结构示意图；
图17为本申请实施例中连接电路的几种结构示意图；
图18为本申请实施例中S21频率响应曲线的第六种示意图；
图19为本申请实施例中S21频率响应曲线的第七种示意图；
图20为本申请实施例中超导量子比特读出装置的第八种结构示意图。
具体实施方式
本申请实施例提供了一种超导量子比特读出装置、超导量子芯片和量子计算机，既保证了读出信号的保真度，又避免了比特的弛豫时间缩短。需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请可主要应用于超导量子计算场景，超导量子计算是基于超导电路的量子计算方案。超导电路是由电容、电感、传输线、约瑟夫森结等基本元件构成的微波电路。超导电路芯片工作在由稀释制冷机提供的超低温环境以实现超导。超导量子电路在设计，制备和测量等方面与现有的集成电路技术具有较高的兼容性，对量子比特的能级与耦合可以实现非常灵活的设计与控制，极具规模化的潜力。下面对超导量子计算场景下的量子计算机进行介绍。
图1为量子计算机的一种结构示意图。如图1所示，量子计算机包括：用于提供低温环境的稀释制冷机1，用于实现量子计算信息载体的超导量子芯片2，以及用于操控量子比特状态进行计算操作和读取量子比特状态的测控系统3。超导量子芯片2置于低温环境中，测控系统3按照计算操作的需求控制微波源以及调制脉冲信号，将一系列微波脉冲序列输入到超导量子芯片2，对比特量子态进行操作。所有操作完成后，测控系统3再输出测量脉冲信号到超导量子芯片2，通过返回的信号获取超导量子比特的状态，得到计算结果。
图2为超导量子芯片的一种结构示意图。如图2所示，超导量子芯片包括呈二维阵列排布的多个超导量子比特读出装置31以及将多个超导量子比特读出装置耦合起来的耦合器32。应理解，图2所示的二维阵列排布只是一种具体示例，在实际应用中超导量子芯片也可以采用其他形式的排布方式，具体此处不做 限定。
图3为本申请实施例中超导量子比特读出装置的第一种结构示意图。如图3所示，超导量子比特读出装置包括：滤波读出腔10、超导量子比特单元20、读出线30、第一耦合单元40和第二耦合单元50。其中，滤波读出腔10通过第一耦合单元40与超导量子比特单元20耦合，滤波读出腔10通过第二耦合单元50与读出线30耦合。需要说明的是，滤波读出腔10、第一耦合单元40和第二耦合单元50都可以是由电容、电感、传输线，或者他们组合而成的电路网络，其中的电容和电感可以是固定的或可调的。应理解，滤波读出腔10可以视为一种用于读出超导量子比特的状态的谐振腔，并且该滤波读出腔10还可以对超导量子比特进行反射式过滤。
具体地，超导量子比特单元20用于存储处于量子态的微波光子，微波光子的量子态用于编码得到量子信息，该量子信息可以反映超导量子比特的状态，即超导量子比特的物理实体为承载量子信息的微波光子，处于量子态的微波光子可以通过第一耦合单元40耦合到滤波读出腔10。读出线30上处于经典态的微波光子先进入滤波读出腔10，然后经过调制再回到读出线30并携带超导量子比特状态的信息。为了便于介绍，本申请将从读出线30传输至滤波读出腔10的信号称为“读入信号”，将从滤波读出腔10传输至读出线30的信号称为“读出信号”。
滤波读出腔10根据微波光子的量子态对读入信号进行调制得到读出信号，并将读出信号传输至读出线30。应理解，读出信号反映的超导量子比特的状态会坍缩到0态或1态，因此可以根据读出信号确定超导量子比特的状态是0态或1态，即超导量子比特状态的信息。此外，滤波读出腔10还用于对来自超导量子比特单元20的处于量子态的微波光子进行反射式过滤，从而抑制处于量子态的微波光子透过滤波读出腔10传输至读出线30。
需要说明的是，包括滤波读出腔10、第一耦合单元40和第二耦合单元50的部分结构所对应的S21频率响应曲线包括至少一个谐振点(mode)和至少一个极点(pole)。应理解，谐振点指电路的S21频率响应曲线中衰减dB趋于零的频点，极点指电路的S21频率响应曲线中衰减dB趋于负无穷的频点。
图4为本申请实施例中S21频率响应曲线的第一种示意图。其中，读出信号与谐振点的频率差值小于第一预设值，读入信号与谐振点的频率差值小于第二预设值，处于量子态的微波光子与极点的频率差值小于第二预设值。例如，第一预设值为20MHz，第二预设值为4GHz。也就是说，本申请通过设计使得谐振点的频率与读出信号以及读入信号的频率相等或接近，并使得处于量子态的微波光子的频率与极点的频率相等或接近，谐振点的频率与极点的频率有较大的失谐。应理解，谐振点表示一种微波模式，读入信号可以由读出线30输入到滤波读出腔10，并且，读出信号可以由滤波读出腔10输出到读出线。极点表示微波阻断点，处于量子态的微波光子被滤波读出腔10反射，从而无法透过滤波读出腔10传输到读出线30。
通过本申请的设计可以看出：滤波读出腔允许读出信号传输至读出线，并抑制处于量子态的微波光子透过滤波读出腔传输到读出线，避免了处于量子态的微波光子透过滤波读出腔而耗散，也就避免了比特的弛豫时间缩短。因此，本申请可以在保证比特弛豫时间不缩短的情况下，加速信号的读出速度从而提升读出保真度，或者，如果保持滤波读出腔与读出线的耦合强度，可以在读出速度不变的情况下，延长比特弛豫时间。也就是说，本申请兼顾了读出保真度与比特弛豫时间这两个因素。另外，本申请提供的滤波读出腔是一个集成器件，器件的整体尺寸较小，滤波通道不会影响读出通道，在实现滤波的同时不会对读出信号造成影响。
下面提供几种滤波读出腔的具体结构，应理解，在实际应用中滤波读出腔的结构包括但不限于以下提供的示例，只要是允许读出信号通过并能阻断处于量子态的微波光子的结构均在本申请的保护范围内。
图5为本申请实施例中超导量子比特读出装置的第二种结构示意图。如图5所示，滤波读出腔10包括电感101、电容102、电容103和电容104。电感101的第一端与第一耦合单元40和第二耦合单元50连接、且连接点与电容102的第一端和电容103的第一端连接，电容102的第二端接地，电感101的第二端与电容103的第二端连接、且连接点与电容104的第一端连接，电容104的第二端接地。第一耦合单元40和第二耦合单元50采用的是耦合电容。
图6为本申请实施例中S21频率响应曲线的第二种示意图。图6展示了上述图5所示的实施例所对应的S21频率响应曲线，可以看出，在该实施例中谐振点的频率大于极点的频率。
图7为本申请实施例中超导量子比特读出装置的第三种结构示意图。如图7所示，滤波读出腔10包括电感101、电容102、电容103和电容104。电感101的第一端与第一耦合单元40连接、且连接点与电容102的第一端和电容103的第一端连接，电容102的第二端接地，电感101的第二端与第二耦合单元50连接、且连接点与电容103的第一端和电容104的第二端连接，电容104的第二端接地。第一耦合单元40和第二耦合单元50采用的是耦合电容。
图8为本申请实施例中S21频率响应曲线的第三种示意图。图8展示了上述图7所示的实施例所对应的S21频率响应曲线，可以看出，在该实施例中谐振点的频率小于极点的频率。
需要说明的是，上述图5和图7所示的实施例中滤波读出腔10采用了集总浮地式设计，滤波读出腔10主要由一个电容和一个电感并联而成，该并联电路两端均通过电容接地。其中，图5所示的实施例为同端耦合设计，即超导量子比特单元20和读出线30耦合到滤波读出腔10的同一端。图7所示的实施例为异端耦合设计，即超导量子比特单元20和读出线30耦合到滤波读出腔10的不同端。在一些可能的实施方式中，图5和图7所示的实施例中滤波读出腔10中电容大小在1fF～1pF左右，电感大小在0.1nH～30nH左右。应理解，图6和图8中所示的谐振点和极点只是一种示例，可以通过改变滤波读出腔10中电容和/或电感的大小灵活调节谐振点的频率和极点的频率。
还需要说明的是，上述图5和图7所示的实施例由于采用了集总的设计可以将尺寸做的更小，集成度更高。另外，对于图7所示的异端耦合设计，便于实现超导量子比特单元重置的操作。应理解，完成一次量子计算后需要使得处于量子态的微波光子恢复到0态以便于下一次量子计算，而处于量子态的微波光子恢复到0态需要一定的时间。若采用图7所示的异端耦合设计，谐振点的频率小于极点的频率，便于向下调节极点的频率，使得极点的频率与谐振点的频率接近，那么处于量子态的微波光子可以穿过滤波读出腔10传输至读出线30，从而处于量子态的微波光子恢复到0态，完成超导量子比特单元重置的操作，有助于提升系统的效率。
图9为本申请实施例中超导量子比特读出装置的第四种结构示意图。如图9所示，滤波读出腔10包括极点生成电路11、连接电路12和连接电路13，所述连接电路12的第一端与所述第一耦合单元40连接，所述连接电路13的第一端与所述第二耦合单元50连接，所述连接电路12的第二端与所述连接电路13的第二端连接、且连接点与所述极点生成电路11连接。第一耦合单元40和第二耦合单元50采用的是耦合电容。
图10为本申请实施例中超导量子比特读出装置的第五种结构示意图。如图10所示，区别于上述图9所示的结构，滤波读出腔10也可以不包括连接电路12和连接电路13，即极点生成电路11直接与第一耦合单元40和第二耦合单元50连接。在一些可能的实施方式中，滤波读出腔10也可以只包括连接电路12或连接电路13，此处不再提供附图展示。
图11为本申请实施例中超导量子比特读出装置的第六种结构示意图。如图11所示，区别于上述图9和图10所示的结构，第一耦合单元40采用耦合电容，第二耦合单元50采用耦合电感。
应理解，在上述图9、图10和图11所示的实施例中，极点的频率取决于极点生成电路11，通过调节极点生成电路可以使得谐振点的频率大于所述极点的频率，或者，所述谐振点的频率小于所述极点的频率。下面提供极点生成电路11的几种结构，其中，极点生成电路11的结构包括但不限于图12提供的示例，本领域技术人员可以基于上述示例进行灵活变换，此处不再一一展示。
图12为本申请实施例中极点生成电路的几种结构示意图。如图12的A示例所示，极点生成电路11包括传输线111和电容112，所述传输线111的第一端与所述连接电路12的第二端和所述连接电路13的第二端连接，所述传输线111的第二端与所述电容112的第一端连接，所述电容112的第二端接地。如图12的B示例所示，极点生成电路11包括LC并联电路113和电容112，所述LC并联电路113的第一端与所述连接电路12的第二端和所述连接电路13的第二端连接，所述LC并联电路的第二端与所述电容112的第一端连接，所述电容112的第二端接地。如图12的C示例所示，极点生成电路11包括LC并联电路113和电容112，所述LC并联电路113的第一端与所述电容112的第一端连接，所述电容112的第二端与所述连接电路12的第二端和所述连接电路13的第二端连接，所述LC并联电路113的第二端接地。应理解，如图12的B示例和C示例中虚线框所示的电容是无法避免的寄生电容。
图13为本申请实施例中连接电路的几种结构示意图。如图13所示，连接电路12可以采用LC并联电路或传输线，同理，连接电路13可以采用LC并联电路或传输线。应理解，LC并联电路中的电容是无法避免的寄生电容。
应理解，在图12和图13所示的结构中，作为一个示例，电容大小在1fF～1pF左右，电感大小在0.1nH～30nH左右，传输线长度在0～25mm左右。
图14为本申请实施例中S21频率响应曲线的第四种示意图。图14展示了上述图9或图10所示的实施例所对应的S21频率响应曲线。在一种可能的实施方式中，通过设计的极点生成电路11使得谐振点的频率大于所述极点的频率。在另一种可能的实施方式中，通过设计的极点生成电路11使得谐振点的频率小于所述极点的频率。以极点生成电路11采用图12所示的A示例为例，可以通过改变传输线111的长度和/或电容112的大小来调节谐振点的频率和极点的频率。
图15为本申请实施例中S21频率响应曲线的第五种示意图。图15展示了上述图11所示的实施例所对应的S21频率响应曲线，可以看出，在该实施例中谐振点的频率小于极点的频率。
需要说明的是，上述图9、图10和图11所示的实施例采用了分布式腔的设计，从微纳加工的角度看更容易获得更高的品质因子。通过不同设计的极点生成电路可以灵活调节极点和谐振点的频率，从而满足不同场景的需求，例如，通过设计以便于实现超导量子比特单元重置的操作。
图16为本申请实施例中超导量子比特读出装置的第七种结构示意图。如图16所示，滤波读出腔10包括极点生成电路11、极点生成电路14、连接电路15、电容105和电容106。所述连接电路15的第一端与所述第一耦合单元40连接、且连接点与所述极点生成电路11和所述电容105的第一端连接，所述电容105的第二端接地，所述连接电路15的第二端与所述第二耦合单元50连接、且连接点与所述极点生成电路14和所述电容106的第一端连接，所述电容106的第二端接地。第一耦合单元40和第二耦合单元50采用的是耦合电容。应理解，电容105和电容106是无法避免的寄生电容。
应理解，图16所示的实施例对应的S21频率响应曲线包括极点1和极点2，其中，极点1的频率取决于极点生成电路11，极点2的频率取决于极点生成电路14。极点生成电路11和极点生成电路14都可以采用上述图12所示的几种结构，具体此处不做限定。
图17为本申请实施例中连接电路的几种结构示意图。如图17所示，连接电路15可以采用LC并联电路、传输线或电容。应理解，LC并联电路中的电容是无法避免的寄生电容。
应理解，在图16所示的实施例中，作为一个示例，滤波读出腔10中电容大小在1fF～1pF左右，电感大小在0.1nH～30nH左右，传输线长度在0～25mm左右。
图18为本申请实施例中S21频率响应曲线的第六种示意图。图18展示了上述图16所示实施例中连接电路15采用电容所对应的S21频率响应曲线，可以看出，在该实施例中极点1的频率和极点2的频率都小于谐振点的频率。
图19为本申请实施例中S21频率响应曲线的第七种示意图。图19展示了上述图16所示实施例中连接电路15采用LC并联电路或传输线所对应的S21频率响应曲线，可以看出，在该实施例中极点1的频率和极点2的频率都大于谐振点的频率。
需要说明的是，在图16所示实施例中，由于极点数量增加到2个，滤波带宽显著提升。可以通过设计极点生成电路11和极点生成电路14，使得极点1与极点2的频率接近，从而实现两个极点覆盖的滤波区间连接起来形成一个更大的滤波区间，例如图18中4.5GHz～5.5GHz附近和图19中5.5GHz～6.7GHz附近。如果在设计上将两个极点的频率做到相同，那么相较于单极点的情况，图16所示实施例的滤波效果会由于两个极点的叠加变得更强。并且，通过不同设计的极点生成电路可以灵活调节两个极点和谐振点的频率，从而满足不同场景的需求，例如，通过设计以便于实现超导量子比特单元重置的操作。
还需要说明的是，基于上面各实施例的介绍，滤波读出腔10中极点生成电路的数量还可以进一步扩展从而实现更多的极点，具体实现方式本领域技术人员可知，此处不再赘述。
图20为本申请实施例中超导量子比特读出装置的第八种结构示意图。如图20所示，在一些可能的实施方式中，超导量子比特读出装置还包括控制器60。滤波读出腔10中可以采用可调的电感或电容，例如，超导量子干涉器SQUID(superconducting quantum interference device)是由两个约瑟夫森结并联构成 的环路器件，一般可用作可调电感。通过改变SQUID环路中的磁通可以改变SQUID的电感。控制器60向滤波读出腔10输出控制信号，该控制信号具体可以是偏置电流或偏置电压，控制通过改变控制信号可以调节滤波读出腔10中的电容或电感，从而调节S21频率响应曲线中谐振点的频率和极点的频率，实现了谐振点的频率和极点的频率动态可调。
需要说明的是，以上实施例仅用以说明本申请的技术方案，而非对其限制。尽管参照前述实施例对本申请进行了详细说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (17)

  1. 一种超导量子比特读出装置，其特征在于，包括：超导量子比特单元、滤波读出腔、读出线、第一耦合单元和第二耦合单元，所述滤波读出腔通过所述第一耦合单元与所述超导量子比特单元耦合，所述滤波读出腔通过所述第二耦合单元与所述读出线耦合；
    所述超导量子比特单元用于存储处于量子态的微波光子；
    所述读出线用于将读入信号传输至所述滤波读出腔；
    所述滤波读出腔用于根据所述微波光子的量子态对所述读入信号进行调制得到读出信号，并将所述读出信号传输至所述读出线；
    所述滤波读出腔还用于对所述微波光子进行过滤，以抑制所述微波光子透过所述滤波读出腔传输至所述读出线。
  2. 根据权利要求1所述的超导量子比特读出装置，其特征在于，包括所述滤波读出腔、所述第一耦合单元和所述第二耦合单元的结构所对应的S21频率响应曲线包括至少一个谐振点和至少一个极点，所述读出信号与所述谐振点的频率差值小于第一预设值，所述微波光子与所述极点的频率差值小于所述第二预设值。
  3. 根据权利要求2所述的超导量子比特读出装置，其特征在于，所述滤波读出腔包括电感、第一电容、第二电容和第三电容，所述电感的第一端与所述第一耦合单元和所述第二耦合单元连接、且连接点与所述第一电容的第一端和所述第二电容的第一端连接，所述第一电容的第二端接地，所述电感的第二端与所述第二电容的第二端连接、且连接点与所述第三电容的第一端连接，所述第三电容的第二端接地；所述谐振点的频率大于所述极点的频率。
  4. 根据权利要求2所述的超导量子比特读出装置，其特征在于，所述滤波读出腔包括电感、第一电容、第二电容和第三电容，所述电感的第一端与所述第一耦合单元连接、且连接点与所述第一电容的第一端和所述第二电容的第一端连接，所述第一电容的第二端接地，所述电感的第二端与所述第二耦合单元连接、且连接点与所述第三电容的第一端和所述第二电容的第二端连接，所述第三电容的第二端接地；所述谐振点的频率小于所述极点的频率。
  5. 根据权利要求3或4所述的超导量子比特读出装置，其特征在于，所述第一耦合单元包括耦合电容，所述第二耦合单元包括耦合电容。
  6. 根据权利要求2所述的超导量子比特读出装置，其特征在于，所述滤波读出腔包括极点生成电路、第一连接电路和第二连接电路，所述第一连接电路的第一端与所述第一耦合单元连接，所述第二连接电路的第一端与所述第二耦合单元连接，所述第一连接电路的第二端与所述第二连接电路的第二端连接、且连接点与所述极点生成电路连接；所述极点的频率取决于所述极点生成电路，所述谐振点的频率大于所述极点的频率，或者，所述谐振点的频率小于所述极点的频率。
  7. 根据权利要求6所述的超导量子比特读出装置，其特征在于，所述极点生成电路包括第三传输线和第一电容，所述第三传输线的第一端与所述第一连接电路的第二端和所述第二连接电路的第二端连接，所述第三传输线的第二端与所述第一电容的第一端连接，所述第一电容的第二端接地；
    或者，
    所述极点生成电路包括LC并联电路和第一电容，所述LC并联电路的第一端与所述第一连接电路的第二端和所述第二连接电路的第二端连接，所述LC并联电路的第二端与所述第一电容的第一端连接，所述第一电容的第二端接地；
    或者，
    所述极点生成电路包括LC并联电路和第一电容，所述LC并联电路的第一端与所述第一电容的第一端连接，所述第一电容的第二端与所述第一连接电路的第二端和所述第二连接电路的第二端连接，所述LC并联电路的第二端接地。
  8. 根据权利要求6或7所述的超导量子比特读出装置，其特征在于，所述第一连接电路包括LC并联电路或传输线，所述第二连接电路包括LC并联电路或传输线。
  9. 根据权利要求6至8中任一项所述的超导量子比特读出装置，其特征在于，所述第一耦合单元包括 耦合电容，所述第二耦合单元包括耦合电容；
    或者，
    所述第一耦合单元包括耦合电容，所述第二耦合单元包括耦合电感。
  10. 根据权利要求2所述的超导量子比特读出装置，其特征在于，所述滤波读出腔包括第一极点生成电路、第二极点生成电路、连接电路、第一电容和第二电容，所述连接电路的第一端与所述第一耦合单元连接、且连接点与所述第一极点生成电路和所述第一电容的第一端连接，所述第一电容的第二端接地，所述连接电路的第二端与所述第二耦合单元连接、且连接点与所述第二极点生成电路和所述第二电容的第一端连接，所述第二电容的第二端接地；所述S21频率响应曲线包括第一极点和第二极点，所述第一极点的频率取决于所述第一极点生成电路，所述第二极点的频率取决于所述第二极点生成电路。
  11. 根据权利要求10所述的超导量子比特读出装置，其特征在于，所述第一极点生成电路包括第一传输线和第三电容，所述第一传输线的第一端与所述第一电容的第一端连接、且连接点与所述连接电路的第一端和所述第一耦合单元连接，所述第一传输线的第二端与所述第三电容的第一端连接，所述第三电容的第二端接地；
    或者，
    所述第一极点生成电路包括第一LC并联电路和第三电容，所述第一LC并联电路的第一端与所述第一电容的第一端连接、且连接点与所述连接电路的第一端和所述第一耦合单元连接，所述第一LC并联电路的第二端与所述第三电容的第一端连接，所述第三电容的第二端接地；
    或者，
    所述第一极点生成电路包括第一LC并联电路和第三电容，所述第一LC并联电路的第一端与所述第三电容的第一端连接，所述第三电容的第二端与所述第一电容的第一端连接、且连接点与所述连接电路的第一端和所述第一耦合单元连接，所述第一LC并联电路的第二端接地。
  12. 根据权利要求10或11所述的超导量子比特读出装置，其特征在于，所述第二极点生成电路包括第二传输线和第四电容，所述第二传输线的第一端与所述第二电容的第一端连接、且连接点与所述连接电路的第二端和所述第二耦合单元连接，所述第二传输线的第二端与所述第四电容的第一端连接，所述第四电容的第二端接地；
    或者，
    所述第二极点生成电路包括第二LC并联电路和第四电容，所述第二LC并联电路的第一端与所述第二电容的第一端连接、且连接点与所述连接电路的第二端和所述第二耦合单元连接，所述第二LC并联电路的第二端与所述第四电容的第一端连接，所述第四电容的第二端接地；
    或者，
    所述第二极点生成电路包括第二LC并联电路和第四电容，所述第二LC并联电路的第一端与所述第四电容的第一端连接，所述第四电容的第二端与所述第二电容的第一端连接、且连接点与所述连接电路的第二端和所述第二耦合单元连接，所述第二LC并联电路的第二端接地。
  13. 根据权利要求10至12中任一项所述的超导量子比特读出装置，其特征在于，所述连接电路包括电容，所述第一极点的频率和所述第二极点的频率都小于所述谐振点的频率；
    或者，
    所述连接电路包括LC并联电路或传输线，所述第一极点的频率和所述第二极点的频率都大于所述谐振点的频率。
  14. 根据权利要求10至13中任一项所述的超导量子比特读出装置，其特征在于，所述第一耦合单元包括耦合电容，所述第二耦合单元包括耦合电容。
  15. 根据权利要求2至14中任一项所述的超导量子比特读出装置，其特征在于，所述超导量子比特读出装置还包括控制器；
    所述控制器用于调节加载到所述滤波读出腔的控制信号，以调节所述谐振点的频率和所述极点的频率。
  16. 一种超导量子芯片，其特征在于，包括多个如权利要求1至15中任一项所述的超导量子比特读出装置，多个所述超导量子比特读出装置呈阵列分布，每相邻两个所述超导量子比特读出装置相互耦合。
  17. 一种量子计算机，其特征在于，包括：稀释制冷机、测控系统和如权利要求16所述的超导量子芯片。
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