WO2024093124A1

WO2024093124A1 - Switch standard unit, switch, and layout design method

Info

Publication number: WO2024093124A1
Application number: PCT/CN2023/086028
Authority: WO
Inventors: 王宇哲
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-11-04
Filing date: 2023-04-03
Publication date: 2024-05-10
Also published as: CN118036537A

Abstract

A switch standard unit, a switch, and a layout design method. The switch standard unit comprises a switch input part, a switch output part and a connecting part, all of which are arranged in a framework area, wherein the switch input part and the switch output part are arranged on the same layer and extend in a first direction; the connecting part is arranged on a different layer from the switch input part and the switch output part, and comprises a first connecting structure and a second connecting structure, which are spaced apart from each other in the first direction and both extend in a second direction; and the first connecting structure is connected to the switch input part, and the second connecting structure is connected to the switch output part.

Description

Switch standard cell, switch and layout design method

This application claims the priority of the Chinese patent application filed with the China Patent Office on November 4, 2022, with application number 202211379157.0 and application name “Switch standard unit, switch and layout design method”, all contents of which are incorporated by reference in this application.

Technical Field

The present disclosure relates to but is not limited to a switch standard unit, a switch, and a layout design method.

Background technique

Integrated circuit design can usually be divided into full custom design and semi-custom design. Full custom design can better improve device performance, but it is time-consuming and difficult to fully realize automated design. Semi-custom design can be based on gate arrays or standard cell libraries to achieve fully automated design. Therefore, designs based on gate arrays or standard cell libraries can improve layout design efficiency.

Summary of the invention

An embodiment of the present disclosure provides a switch standard unit, comprising: a switch input portion, a switch output portion, and a connection portion disposed in a frame area;

The switch input portion and the switch output portion are arranged in the same layer and extend in a first direction;

The connection part is arranged in different layers with the switch input part and the switch output part, and includes a first connection structure and a second connection structure arranged at intervals along the first direction and both extending in the second direction; the first connection structure is connected to the switch input part, and the second connection structure is connected to the switch output part.

In some embodiments, the frame region includes a first frame unit and a second frame unit arranged along the second direction;

The switch input part is located in the first frame unit, and the switch output part is located in the second frame unit; a part of the first connecting structure is located in the first frame unit, and another part is located in the second frame unit; a part of the second connecting structure is located in the first frame unit, and another part is located in the second frame unit.

In some embodiments, the switch input portion is connected to the first connection structure through a first conductive via, and the switch output portion is connected to the second connection structure through a second conductive via.

In some embodiments, the shortest distance between the edge of the first conductive via in the first direction and the edge of the first connecting structure in the first direction is greater than or equal to the first preset distance; the shortest distance between the edge of the first conductive via in the second direction and the edge of the first connecting structure in the second direction is greater than or equal to the second preset distance;

The shortest distance between the edge of the second conductive hole in the first direction and the edge of the second connecting structure in the first direction is greater than or equal to the first preset distance; the shortest distance between the edge of the second conductive hole in the second direction and the edge of the second connecting structure in the second direction is greater than or equal to the second preset distance.

In some embodiments, a minimum distance between the first connection structure and the second connection structure in the first direction is greater than or equal to a third preset distance.

In some embodiments, the standard cell includes a first power wiring portion and a second power wiring portion that are arranged at intervals in the first direction and extend along the second direction;

The switch input portion, the switch output portion, and the connection portion are located between the first power wiring portion and the second power wiring portion.

In some embodiments, the first power wiring portion, the second power wiring portion, and the connection portion are arranged in the same layer.

An embodiment of the present disclosure provides a switch, comprising a switch input portion, a switch output portion, and a connecting portion disposed on a substrate;

In some embodiments, the switch input portion and the switch output portion are located in a first metal layer, and the connecting portion is located in a second metal layer that is farther away from the substrate than the first metal layer.

An embodiment of the present disclosure provides a layout design method, including:

Obtaining a circuit schematic diagram, the circuit schematic diagram comprising at least one switch and at least one gate-level circuit unit;

Obtaining a connection relationship and a state of a switch according to a circuit schematic diagram; wherein the connection relationship includes at least one of a connection relationship between a switch and a gate-level circuit unit, a connection relationship between a plurality of switches, and a connection relationship between a plurality of gate-level circuit units;

When the switch is in an off state, the switch standard unit involved in the above embodiment and the standard unit corresponding to the gate-level circuit unit are called for splicing according to the connection relationship;

When the switch is in the on state, the switch standard unit involved in the above embodiment is called according to the connection relationship to splice the standard unit corresponding to the gate-level circuit unit, and a bridge portion is arranged between the first connection structure and the second connection structure so that the first connection structure and the second connection structure are connected through the bridge portion.

In some embodiments, the bridge portion is disposed in the same layer as the first connection structure and the second connection structure.

In some embodiments, obtaining the connection relationship and the state of the switch according to the circuit schematic diagram specifically includes:

A gate-level netlist is obtained according to the circuit schematic, and a connection relationship and a state of a switch are determined according to the gate-level netlist.

In some embodiments, when two switch standard units are adjacently spliced, a minimum distance between connection portions of the two switch standard units is greater than or equal to a fourth preset distance.

In some embodiments, when a circuit schematic includes a plurality of switches and any two switches are connected, the two switches are connected via wiring disposed in the polysilicon layer.

In some embodiments, the standard unit corresponding to the gate-level circuit unit includes a third power wiring portion and a fourth power wiring portion, and the interval between the third power wiring portion and the fourth power wiring portion is the same as the interval between the first power wiring portion and the second power wiring portion in the switch standard unit; when the switch standard unit and the standard unit corresponding to the gate-level circuit unit are spliced, the first power wiring portion and the third power wiring portion are aligned and spliced so that the two are connected, and the second power wiring portion and the fourth power wiring portion are aligned and spliced so that the two are connected.

The switch standard unit, switch and layout design method provided by the present disclosure include a frame area and a switch input part, a switch output part and a connection part arranged in the frame area. The connection part includes a first connection structure and a second connection structure arranged at intervals in a first direction. The first connection structure connects the switch input part, and the second connection structure connects the switch output part. The switch input part serves as one end of the switch standard unit, and the switch output part serves as the other end of the switch standard unit. The layout structure design of the switch standard unit corresponding to the switch in the disconnected state is realized, which facilitates the use of automatic tools to automatically layout and route the switch standard unit, greatly reduces the design time during the initial layout design, and quickly solves the design problem. In addition, the switch input part and the switch output part are extended in the first direction, so that the first connection structure is connected to the first connection structure. The first connection structure and the second connection structure extend in the second direction, which are both helpful to simplify the wiring when automatically generating the layout of the integrated circuit. In addition, the switch standard unit can be modified according to the disconnection or connection state of the switch during layout design. When modifying, only a bridge portion needs to be set between the first connection structure and the second connection structure. After modification, the metal layer design rules can still be met, and there will be no short circuit problem. Moreover, the modification involves only one layer of metal, which reduces the revision level.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

FIG1 is a circuit diagram of an inverter;

FIG2 is a schematic diagram of a layout of a standard unit corresponding to an inverter;

FIG3 is a schematic diagram of a layout of a switch standard unit provided by the present disclosure;

FIG4 is a schematic diagram of a layout of another switch standard unit provided by the present disclosure;

FIG5 is a circuit diagram of the switch standard unit provided in FIG3 ;

FIG6 is a circuit diagram of the switch standard unit provided in FIG4 ;

FIG7 is a schematic diagram of the connection between the standard unit corresponding to the inverter and the switch standard unit provided by the present disclosure;

FIG8 is a schematic diagram of the structure of a switch provided by the present disclosure;

FIG9 is a schematic diagram of a flow chart of a layout design method provided by the present disclosure;

FIG10 is a circuit schematic diagram of an integrated circuit provided by the present disclosure;

FIG11 is a schematic diagram of a layout of an integrated circuit provided by the present disclosure.

Reference numerals:

100, switch standard unit; 101, frame area; 1011, first frame unit; 1012, second frame unit; 102, switch input unit; 103, switch output unit; 104, connection unit; 1041, first connection structure; 1042, second connection structure; 105, first power wiring unit; 106, second power wiring unit; 107, first conductive hole; 108, second conductive hole; 109, bridge unit; 110, substrate; 131, switch standard unit corresponding to the first switch; 131, switch standard unit corresponding to the second switch; 133, switch standard unit corresponding to the third switch; 134, switch standard unit corresponding to the fourth switch;

200, a first P-type transistor region; 211, a first P-type doping region; 212, a second P-type doping region; 213, a first source portion; 214, a first drain portion; 215, a first gate portion; 221, a first contact plug; 222, a second contact plug; 223, a third contact plug; 224, a fourth contact plug; 225, a fifth contact plug; 226, a sixth contact plug; 231, a third conductive hole; 232, a fourth conductive hole; 233, a fifth conductive hole;

300, a first N-type transistor region; 311, a first N-type doping region; 312, a second N-type doping region; 313, a second source portion; 314, a second drain portion; 315, a second gate portion; 321, a seventh contact plug; 322, an eighth contact plug; 323, a ninth contact plug; 324, a tenth contact plug; 325, an eleventh contact plug; 326, a twelfth contact plug; 331, a sixth conductive hole; 332, a seventh conductive hole; 333, an eighth conductive hole; 401, a first wiring portion; 402, a second wiring portion; 403, a thirteenth contact plug; 404, a fourteenth contact plug;

501, third power wiring section; 502, fourth power wiring section; 600, inverter frame area; 601, third frame unit; 602, fourth frame unit; 603, fifth frame unit; 700, standard unit corresponding to the inverter; 711, standard unit corresponding to the first inverter; 722, standard unit corresponding to the second inverter; P1, first P-type transistor; N1, first N-type transistor; V1, first direction; V2, second direction; K1, first switch; K2, second switch; K3, third switch; K4, fourth switch; Inv1, first inverter; Inv2, second inverter.

The above drawings have shown clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments.

Detailed ways

Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

The design of integrated circuits can usually be divided into full-custom design and semi-custom design. Full-custom design is a design method based on the transistor level, in which all components, interconnections and layouts of the circuit are directly designed. For example: for each transistor, its unique aspect ratio and other parameters are customized; for each critical path, the specific parasitic dispersion parameters are adjusted by adjusting the polysilicon doping concentration or metal material, width and other parameters of the wiring.

Full custom design can improve the performance of components, but it is time-consuming and difficult to fully realize automated design. Semi-custom design can be based on gate arrays or standard cell libraries. Standard cell libraries are the basis of automated design of VLSI.

Standard cell library refers to some basic logic units in circuit design, such as gate circuits, multi-way switches, triggers, etc., which are pre-designed according to the best design principles and placed in the standard cell library. When performing integrated design, it is only necessary to call the required standard cells from the standard cell library according to the circuit requirements, perform automatic logic synthesis and automatic layout and routing, and improve design efficiency.

The design of a standard cell library usually includes the following processes:

First, the design of the standard cell library. This means determining the technical indicators of the basic logic cells in the standard cell library according to the purpose of the standard cell library and the process it is targeting. For example: the basic design size of the basic logic cell, the maximum operating frequency of the basic logic cell, the power consumption of the basic logic cell, etc.

Secondly, the circuit design of the standard cell library refers to designing device sizes with different driving capabilities according to the requirements of various technical indicators of the basic logic unit.

Thirdly, the layout design of the standard cell library refers to determining the basic parameters of the layout design based on the relevant process parameters and the technical indicators of the basic logic cells in the standard cell library, such as: the cell height, line width, number of lines, and area division of the layout design.

Finally, the layout design of the standard cell library is optimized, such as area and performance optimization.

Typically, in the cell layout structure of a standard cell library, the height of each cell needs to meet the metal layer design rules.

Based on the above design rules, the following describes a layout of a standard cell of an inverter, which is stored in a standard cell library. If an integrated circuit includes an inverter, when designing the layout of the integrated circuit based on the circuit schematic of the integrated circuit, the standard cell of the inverter in the standard cell library can be directly called for automatic logic synthesis and automatic layout and routing to generate the layout of the integrated circuit.

FIG1 is a circuit diagram of an inverter, wherein the inverter includes a first P-type transistor P1 and a first N-type transistor N1, wherein the source of the first P-type transistor P1 is connected to a first power supply, the source of the first N-type transistor N1 is connected to a second power supply, and the gate of the first P-type transistor P1 is connected to the gate of the first N-type transistor N1 as an input terminal In of the inverter. The drain of the P-type transistor P1 is connected to the drain of the first N-type transistor N1 to serve as the output terminal Out of the inverter. The voltage provided by the first power supply is the power supply voltage VCC, and the voltage provided by the second power supply is the ground voltage VSS.

2 is a schematic diagram of a layout of a standard unit of an inverter. A standard unit of an inverter includes an inverter frame region 600 and a first P-type transistor region 200 , a first N-type transistor region 300 , a first wiring portion 401 and a second wiring portion 402 located in the inverter frame region 600 .

The first P-type transistor region 200 and the first N-type transistor region 300 are arranged on both sides of the inverter frame region 600. The first wiring portion 401 and the second wiring portion 402 are arranged in the middle of the inverter frame region 600.

The first P-type transistor region 200 includes a first P-type doping region 211 , a second P-type doping region 212 , a first source portion 213 , a first drain portion 214 , and a first gate portion 215 .

The first P-type doping region 211 and the second P-type doping region 212 are located at both sides of the first gate portion 215 , the first source portion 213 is located above the first P-type doping region 211 , and the first drain portion 214 is located above the second P-type doping region 212 .

The first source portion 213 and the first P-type doping region 211 are in contact with each other through the first contact plug 221 , the second contact plug 222 and the third contact plug 223 , and the first drain portion 214 and the second P-type doping region 212 are in contact with each other through the fourth contact plug 224 , the fifth contact plug 225 and the sixth contact plug 226 .

The first source portion 213 serves as the source of the first P-type transistor P1, and the first drain portion 214 serves as the drain of the first P-type transistor P1. A third power wiring portion 501 is further provided above the first source portion 213 and the first drain portion 214. The first source portion 213 is connected to the third power wiring portion 501 through the third conductive via 231, the fourth conductive via 232, and the fifth conductive via 233, so that the source of the first P-type transistor P1 is connected to the first power supply.

2 , the first N-type transistor region 300 includes a first N-type doping region 311 , a second N-type doping region 312 , a second source portion 313 , a second drain portion 314 , and a second gate portion 315 .

The first N-type doping region 311 and the second N-type doping region 312 are located at both sides of the second gate portion 315 , the second source portion 313 is located above the first N-type doping region 311 , and the second drain portion 314 is located above the second N-type doping region 312 .

The second source portion 313 and the first N-type doping region 311 are in contact with each other through the seventh contact plug 321 , the eighth contact plug 322 and the ninth contact plug 323 , and the second drain portion 314 and the second N-type doping region 312 are in contact with each other through the tenth contact plug 324 , the eleventh contact plug 325 and the twelfth contact plug 326 .

The second source portion 313 serves as the source of the first N-type transistor N1, and the second drain portion 314 serves as the drain of the first N-type transistor N1. A fourth power wiring portion 502 is further provided above the second source portion 313 and the second drain portion 314. The second source portion 313 is connected to the fourth power wiring portion 502 through the sixth conductive via 331, the seventh conductive via 332, and the eighth conductive via 333, so that the source of the first N-type transistor N1 is connected to the second power supply.

The first wiring portion 401 , the second wiring portion 402 , the first source portion 213 , the first drain portion 214 , the second source portion 313 , and the second drain portion 314 are formed of the same metal layer.

One end of the first wiring portion 401 contacts one end of the first drain portion 214 , and the other end of the first wiring portion 401 contacts one end of the second drain portion 314 , thereby connecting the drain of the first P-type transistor P1 and the drain of the first N-type transistor N1 .

The second wiring portion 402 is connected to the first gate portion 215 through the thirteenth contact plug 403, and the second wiring portion 402 is also connected to the second gate portion 315 through the fourteenth contact plug 404. The first gate portion 215 serves as the gate of the first P-type transistor P1, and the second gate portion 315 serves as the gate of the first N-type transistor N1. The gate of the first P-type transistor P1 and the gate of the first N-type transistor N1 are connected through the second wiring portion 402.

In some embodiments, the inverter frame region 600 includes three frame units, which are marked as the third frame unit 601, The first P-type transistor region 200 and the first N-type transistor region 300 are located in the fourth frame unit 602 and the fifth frame unit 603 , the first wiring portion 401 is located in the fifth frame unit 603 , and the second wiring portion 402 is located in the third frame unit 601 and the fourth frame unit 602 .

In some embodiments, the inverter frame region 600 includes two frame units, which are marked as a fourth frame unit 602 and a fifth frame unit 603 respectively, the first P-type transistor region 200 and the first N-type transistor region 300 are located in the fourth frame unit 602 and the fifth frame unit 603, the first wiring portion 401 is located in the fifth frame unit 603, and the second wiring portion 402 is only located in the fourth frame unit 602.

The present disclosure provides a switch standard cell 100, which is stored in a standard cell library. If an integrated circuit includes a switch, when designing the layout of the integrated circuit based on the circuit schematic diagram of the integrated circuit, the switch standard cell 100 in the standard cell library can be directly called to perform automatic logic synthesis and automatic layout and routing to generate the layout of the integrated circuit.

FIG3 shows a switch standard unit 100 according to an embodiment of the present disclosure. The switch standard unit 100 includes a frame area 101 and a switch input portion 102 , a switch output portion 103 and a connection portion 104 disposed in the frame area 101 .

The switch input part 102 and the switch output part 103 are arranged in the same layer, that is, the switch input part 102 and the switch output part 103 are located in the same metal layer, and the switch input part 102 and the switch output part 103 both extend in the first direction V1. The switch is a two-terminal device, the switch input part 102 is one end of the switch standard unit 100, and the switch output part 103 is the other end of the switch standard unit 100.

The connection part 104 is arranged in different layers from the switch input part 102 and the switch output part 103. That is, the connection part 104 and the switch input part 102 are located in different metal layers, and the connection part 104 and the switch output part 103 are located in different metal layers.

The connection part 104 includes a first connection structure 1041 and a second connection structure 1042, which are arranged at intervals along the first direction V1, and both extend in the second direction V2. The first connection structure 1041 is connected to the switch input part 102, and the second connection structure 1042 is connected to the switch output part 103.

5 is a schematic diagram of a circuit corresponding to the switch standard unit 100. The switch input unit 102 is one end of the switch standard unit 100, corresponding to one end L of the switch K. The switch output unit 103 is the other end of the switch standard unit 100, corresponding to the other end R of the switch K. By setting a first connection structure 1041 and a second connection structure 1042 arranged at intervals along a first direction V1, the first connection structure 1041 is connected to the switch input unit 102, and the second connection structure 1042 is connected to the switch output unit 103, so that the switch input unit 102 and the switch output unit 103 are disconnected, and the corresponding switch of the switch standard unit 100 is in a disconnected state.

As shown in Figures 4 and 6, when automatically generating the layout of an integrated circuit, if the switch used in the circuit schematic of the integrated circuit is in the on state, then when calling the above-mentioned switch standard unit 100, a bridge portion 109 can be arranged between the first connection structure 1041 and the second connection structure 1042, so that the first connection structure 1041 and the second connection structure 1042 are connected through the bridge portion 109, the switch input portion 102 and the switch output portion 103 are connected, and the corresponding switch of the switch standard unit 100 is in the on state.

By extending the switch input portion 102 and the switch output portion 103 in the first direction V1, the wiring layout between the switch standard cell 100 and other standard cells is facilitated, and the wiring between the switch standard cell 100 and other standard cells is simplified. Other standard cells may be other types of standard cells, such as inverter standard cells, or may be standard cells of the same type, that is, other standard cells are also switch standard cells 100.

By allowing the first connection structure 1041 and the second connection structure 1042 to extend in the second direction V2, if it is necessary to use When the switch standard unit 100 corresponds to the switch in the on state, it is only necessary to arrange the bridge portion 109 at any position between the first connection structure 1041 and the second connection structure 1042 to generate the switch standard unit 100 corresponding to the switch in the on state. The position of the bridge portion 109 can be adjusted as needed to simplify the layout wiring of the integrated circuit.

In some embodiments, the switch input portion 102 and the switch output portion 103 are located in a first metal layer, and the connection portion 104 is located in a second metal layer relatively far from the frame area 101. By such an arrangement, when the switch standard unit 100 corresponding to the switch is modified according to the disconnection or connection state of the switch, since the modified metal layer is located in a metal layer far from the frame area 101, the modified layout level can be reduced.

In the above technical solution, the switch standard unit 100 includes a switch input part 102, a switch output part 103 and a connection part 104 arranged in the frame area 101, and the connection part 104 includes a first connection structure 1041 and a second connection structure 1042 arranged at intervals in the first direction V1, the first connection structure 1041 connects the switch input part 102, and the second connection structure 1042 connects the switch output part 103, the switch input part 102 serves as one end of the switch standard unit 100, and the switch output part 103 serves as the other end of the switch standard unit 100, so as to realize the layout structure design of the switch standard unit 100 corresponding to the switch in the disconnected state, facilitate the use of automatic tools to automatically layout and route the switch standard unit 100, greatly reduce the design time when the layout is first designed, and quickly solve the design problem. In addition, the switch input part 102 and the switch output part 103 are extended in the first direction V1, and the first connection structure 1041 and the second connection structure 1042 are extended in the second direction V2, which are conducive to simplifying the wiring when the layout of the integrated circuit is automatically generated. In addition, during the layout design, the switch standard unit 100 can be modified according to the disconnected or connected state of the switch. During the modification, only a bridge portion 109 needs to be set between the first connection structure 1041 and the second connection structure 1042. After the modification, the metal layer design rules can still be met, and there will be no short circuit problem. Moreover, the modification involves only one layer of metal, which reduces the number of revision levels.

In some embodiments, the frame area 101 includes a first frame unit 1011 and a second frame unit 1012 arranged along the second direction V2. The switch input unit 102 is located in the first frame unit 1011 and extends in the first direction V1 in the first frame unit 1011. The switch output unit 103 is located in the second frame unit 1012 and extends in the first direction V1 in the second frame unit 1012. By making the switch input unit 102 located in the first frame unit 1011 and the switch output unit 103 located in the second frame, the switch input unit 102 and the switch output unit 103 are isolated from each other, and short circuit between the switch input unit 102 and the switch output unit 103 due to too close distance is avoided, and the switch input unit 102 and the switch output unit 103 can also be ensured to meet the metal layer design rules.

A portion of the first connection structure 1041 is located in the first frame unit 1011, and another portion of the first connection structure 1041 is located in the second frame unit 1012. A portion of the second connection structure 1042 is located in the first frame unit 1011, and another portion of the second connection structure 1042 is located in the second frame unit 1012. By such an arrangement, if it is necessary to use the switch standard unit 100 corresponding to the switch in the on state, the bridge portion 109 can be arranged in the area corresponding to the first frame unit 1011 and the second frame unit 1012, and the switch standard unit 100 corresponding to the switch in the on state can be generated. The bridge portion 109 can be arranged in a relatively large area to meet different needs.

In some embodiments, the switch input part 102 is connected to the first connection structure 1041 through the first conductive via 107, and the switch output part 103 is connected to the second connection structure 1042 through the second conductive via 108. By such an arrangement, the switch input part 102 located at different layers is electrically connected to the first connection structure 1041, and the switch output part 103 located at different layers is electrically connected to the second connection structure 1042.

In some embodiments, the shortest distance between the edge of the first conductive via 107 in the first direction V1 and the edge of the first connection structure 1041 in the first direction V1 is greater than or equal to the first preset distance. The shortest distance between the edge in the direction V2 and the edge of the first connection structure 1041 in the second direction V2 is greater than or equal to the second preset distance.

As shown in Figure 7, the shortest distance G1 between the upper edge of the first conductive hole 107 in the first direction V1 and the upper edge of the first connecting structure 1041 in the first direction V1 is greater than or equal to the first preset distance, and the shortest distance G2 between the lower edge of the first conductive hole 107 in the first direction V1 and the lower edge of the first connecting structure 1041 in the first direction V1 is greater than or equal to the first preset distance.

The shortest distance F1 between the left edge of the first conductive via 107 in the second direction V2 and the left edge of the first connection structure 1041 in the second direction V2 is greater than or equal to the second preset distance.

The first preset distance and the second preset distance are set according to metal layer design rules.

By such arrangement, the transmission of electrical signals between the first conductive via 107 and the first connection structure 1041 is ensured.

The shortest distance between the edge of the second conductive via 108 in the first direction V1 and the edge of the second connection structure 1042 in the first direction V1 is greater than or equal to the first preset distance. The shortest distance between the edge of the second conductive via 108 in the second direction V2 and the edge of the second connection structure 1042 in the second direction V2 is greater than or equal to the second preset distance.

As shown in FIG7 , the shortest distance G3 between the upper edge of the second conductive via 108 in the first direction V1 and the upper edge of the second connection structure 1042 in the first direction V1 is greater than or equal to the first preset distance. The shortest distance G4 between the lower edge of the second conductive via 108 in the first direction V1 and the lower edge of the second connection structure 1042 in the first direction V1 is greater than or equal to the first preset distance. The shortest distance F2 between the right edge of the second conductive via 108 in the second direction V2 and the right edge of the second connection structure 1042 in the second direction V2 is greater than or equal to the second preset distance.

By such arrangement, the transmission of electrical signals between the second conductive via 108 and the second connection structure 1042 is ensured.

In some embodiments, a minimum distance between the first connection structure 1041 and the second connection structure 1042 in the first direction V1 is greater than or equal to a third preset distance.

As shown in FIG. 7 , the shortest distance H between the lower edge of the first connection structure 1041 in the first direction V1 and the upper edge of the second connection structure 1042 in the first direction V1 is greater than or equal to the third preset distance.

By such an arrangement, it is ensured that there is no short circuit between the first connection structure 1041 and the second connection structure 1042 due to too small a distance.

3 , the switch standard unit 100 includes a first power wiring portion 105 and a second power wiring portion 106. The first power wiring portion 105 and the second power wiring portion 106 are arranged alternately in a first direction V1, and extend along a second direction V2.

The switch input portion 102 , the switch output portion 103 and the connection portion 104 are all located between the first power wiring portion 105 and the second power wiring portion 106 .

By providing the first power wiring section 105 and the second power wiring section 106 in the switch standard cell 100, it is convenient to wire between the switch standard cell 100 and the power supply, and the wiring when automatically generating the layout of the integrated circuit is simplified. The first power wiring section 105 and the second power wiring section 106 are provided outside the switch input section 102, the switch output section 103 and the connection section 104, without affecting the layout of the core part of the switch standard cell 100.

In some embodiments, the first power wiring portion 105, the second power wiring portion 106 and the connecting portion 104 are arranged on the same layer. Since the first power wiring portion 105, the second power wiring portion 106 and the connecting portion 104 are far apart, short circuit will not occur when they are arranged on the same layer, thereby ensuring the reliability of the switch standard unit 100.

As shown in FIG. 8 , an embodiment of the present disclosure provides a switch, the switch comprising a substrate 110 and a The switch input part 102, the switch output part 103 and the connection part 104 are provided on the substrate.

The switch input portion 102 and the switch output portion 103 are arranged on the same layer, that is, the switch input portion 102 and the switch output end are located on the same metal layer, and the switch input portion 102 and the switch output portion 103 extend in the first direction V1.

The switch is a two-terminal device, the switch input portion 102 is one end of the switch, and the switch output portion 103 is the other end of the switch.

The connection part 104 is arranged in different layers from the switch input part 102 and the switch output part 103, that is, the connection part 104 and the switch input part 102 are located in different metal layers. The connection part 104 includes a first connection structure 1041 and a second connection structure 1042. The first connection structure 1041 and the second connection structure 1042 are arranged at intervals along the first direction V1, and the first connection structure 1041 and the second connection structure 1042 both extend in the second direction V2. The first connection structure 1041 is connected to the switch input part 102, and the second connection structure 1042 is connected to the switch output part 103.

The switch input part 102 serves as one end of the switch, and the switch output part 103 serves as the other end of the switch. The first connection structure 1041 and the second connection structure 1042 are arranged at intervals along the first direction V1, so that the first connection structure 1041 is connected to the switch input part 102, and the second connection structure 1042 is connected to the switch output part 103, so that the switch input part 102 and the switch output part 103 in the switch are in a disconnected state.

In the above technical solution, the switch includes a substrate 110 and a switch input part 102, a switch output part 103 and a connecting part 104 arranged on the substrate 110. The connecting part 104 includes a first connecting structure 1041 and a second connecting structure 1042 arranged at intervals in a first direction V1. The first connecting structure 1041 is connected to the switch input part 102, and the second connecting structure 1042 is connected to the switch output part 103. The switch input part 102 serves as one end of the switch standard unit 100, and the switch output part 103 serves as the other end of the switch standard unit 100. This is conducive to designing the switch standard unit 100 based on the switch structure, facilitating the use of automatic tools to automatically layout and route the switch standard unit 100, and realizing automatic generation of the layout of the integrated circuit, which greatly reduces the design time when the layout is initially designed and quickly solves the design problems.

In some embodiments, the switch input portion 102 and the switch output portion 103 are located in a first metal layer, and the connection portion 104 is located in a second metal layer relatively far from the substrate 110 relative to the first metal layer. By such an arrangement, the switch standard unit 100 is designed based on the structure of the switch, and when the switch standard unit 100 is modified according to the disconnection or connection state of the switch, the modified metal layer is located in a metal layer far from the substrate 110, and the modification layout level can be reduced.

8 , the switch includes a first power wiring portion 105 and a second power wiring portion 106. The first power wiring portion 105 and the second power wiring portion 106 are arranged in a first direction V1 and extend in a second direction V2.

By setting the first power wiring section 105 and the second power wiring section 106 in the switch, when the switch standard unit 100 is involved based on the switch, it is convenient to wire the switch standard unit 100 and the power supply, and the wiring when the layout of the integrated circuit is automatically generated is simplified. The first power wiring section 105 and the second power wiring section 106 are set outside the switch input section 102, the switch output section 103 and the connection section 104, and the layout of the core part of the switch standard unit 100 is not affected.

In some embodiments, the first power wiring portion 105, the second power wiring portion 106 and the connecting portion 104 are arranged on the same layer. When the switch standard unit 100 is designed based on the switch, since the first power wiring portion 105, the second power wiring portion 106 and the connecting portion 104 are far apart, they are arranged on the same layer without short circuit, thereby ensuring the reliability of the switch.

As shown in FIG9 , an embodiment of the present disclosure provides a layout design method, which is applied to electronic devices. The layout design method includes the following steps:

S101, obtaining a circuit schematic diagram.

The circuit schematic diagram includes at least one switch and at least one gate-level circuit unit, and the circuit schematic diagram is used to characterize the connection relationship between the at least one switch and the at least one gate-level circuit unit.

S102: Obtain the connection relationship and the state of the switch according to the circuit schematic.

The connection relationship includes one or more combinations of a connection relationship between a switch and a gate-level circuit unit, a connection relationship between multiple switches, and a connection relationship between multiple gate-level circuit units.

In some embodiments, when the circuit schematic includes a switch and a gate-level circuit unit, a connection relationship between the switch and the gate-level circuit unit is obtained.

In some embodiments, when the circuit schematic includes a switch and at least one gate-level circuit unit, the connection relationship between the switch and one or more gate-level circuit units is obtained. The connection relationship between multiple gate-level circuit units can also be obtained.

In some embodiments, when the circuit schematic includes multiple switches and multiple gate-level circuit units, the connection relationship between each switch and one or more gate-level circuit units, or the connection relationship between each switch and one or more other switches is obtained, and the connection relationship between the gate-level circuit unit and one or more other gate-level circuits can also be obtained.

In some embodiments, information is directly extracted from the circuit schematic to obtain the connection relationship and the state of the switch, wherein the state of the switch includes an off state or an on state.

In some embodiments, a gate-level netlist is obtained according to a circuit schematic, and a connection relationship and a state of a switch are determined according to the gate-level netlist.

S103 , when the switch is in an off state, calling the switch standard cell 100 and the standard cell corresponding to the gate-level circuit cell for splicing.

The switch corresponding to the switch standard unit 100 is in an off state by default. When the switch is in an off state in the circuit schematic, the switch standard unit 100 and the standard unit corresponding to the gate-level circuit unit are directly called for splicing. Splicing means arranging and aligning the switch standard unit 100 and the standard unit corresponding to the gate-level circuit unit adjacent to each other, and then wiring and connecting the two standard units to achieve mutual connection between the two standard units.

In some embodiments, the standard cell corresponding to the gate-level circuit cell includes a third power wiring portion 501 and a fourth power wiring portion 502. The interval between the third power wiring portion 501 and the fourth power wiring portion 502 is the same as the interval between the first power wiring portion 105 and the second power wiring portion 106 in the switch standard cell 100.

When the switch standard cell 100 is spliced with the standard cell corresponding to the gate-level circuit cell, the first power wiring portion 105 is aligned with the third power wiring portion 501 to connect the two, and the second power wiring portion 106 is aligned with the fourth power wiring portion 502 to connect the two.

Continuing to refer to FIG. 7 , taking the gate-level circuit unit as an inverter as an example, when the standard cell 700 corresponding to the inverter is spliced with the switch standard cell 100, the length of the third power wiring portion 501 in the standard cell 700 corresponding to the inverter in the first direction is the same as the length of the first power wiring portion 105 in the switch standard cell 100 in the first direction, the length of the fourth power wiring portion 502 in the standard cell 700 corresponding to the inverter in the first direction is the same as the length of the second power wiring portion 106 in the switch standard cell 100 in the first direction, and the interval between the third power wiring portion 501 and the fourth power wiring portion 502 in the standard cell 700 corresponding to the inverter is the same as the interval between the first power wiring portion 105 and the second power wiring portion 106 in the switch standard cell 100. By setting in this way, the standard cell 700 corresponding to the inverter and the switch standard cell 100 are connected. When the switch standard units 100 are aligned and spliced, the first power wiring portion 105 and the third power wiring portion 501 are aligned and connected, and the second power wiring portion 106 and the fourth power wiring portion 502 are aligned and connected.

S104 , when the switch is in the on state, call the switch standard unit 100 and the standard unit corresponding to the gate-level circuit unit for splicing, and arrange a bridge portion 109 between the first connection structure 1041 and the second connection structure 1042 so that the first connection structure 1041 and the second connection structure 1042 are connected through the bridge portion 109 .

Among them, when the switch is in the on state, after calling the switch standard unit 100 and the standard unit corresponding to the gate-level circuit unit for splicing, it is also necessary to arrange a bridge portion 109 between the first connection structure 1041 and the second connection structure 1042 of the switch standard unit 100, so that the first connection structure 1041 and the second connection structure 1042 are connected through the bridge portion 109, and the switch corresponding to the modified switch standard unit 100 changes from the default off state to the on state.

In some embodiments, the bridge portion 109 is disposed at the same layer as the first connection structure 1041 and the second connection structure 1042 , so that when the switch standard unit 100 is modified according to the switch state, the modification level of the layout is reduced.

In the above technical solution, when performing layout design, the circuit original diagram is obtained, and the connection relationship and the state of the switch are obtained according to the circuit schematic diagram. When the switch is in the disconnected state, the switch standard unit 100 is directly called to splice with the standard unit corresponding to the gate-level circuit unit. When the switch is in the connected state, the switch standard unit 100 is called to splice with the standard unit corresponding to the gate-level circuit unit, and a bridge portion 109 is arranged between the first connection structure 1041 and the second connection structure 1042 so that the first connection structure 1041 and the second connection structure 1042 are connected through the bridge portion 109, so as to realize automatic generation of the layout of the integrated circuit, greatly reduce the design time when the layout is first designed, and quickly solve the design problem. In addition, when designing the layout, the switch standard unit 100 can be modified according to the disconnected or connected state of the switch. When modifying, only the bridge portion 109 needs to be set between the first connection structure 1041 and the second connection structure 1042. After modification, it can still meet the metal layer design rules, and there will be no short circuit problem. In addition, when modifying, only one layer of metal is involved, reducing the revision level.

In some embodiments, when a circuit schematic includes multiple switches and any two switches are connected, the two switches are connected through wiring arranged on the polysilicon layer. Accordingly, the switch standard cells 100 corresponding to the two switches are also connected through wiring on the polysilicon layer. By setting in this way, the connection is convenient and the wiring on the metal layer can be saved.

In some embodiments, the gate-level circuit units are connected by wiring arranged on a metal layer. The metal layer may be a first metal layer. By so arranging, the connection is convenient and the wiring on the second metal layer can be saved.

In some embodiments, when two switch standard units 100 are adjacently spliced, the minimum spacing between the connection portions 104 of the two switch standard units 100 is greater than or equal to a fourth preset distance, and the fourth preset distance is set according to the metal layer design rule. By setting in this way, when two switch standard units 100 are spliced, the conductive portions of the same layer will not be short-circuited.

In some embodiments, the minimum spacing between the conductive parts located in the same layer of two adjacent standard cells is greater than or equal to the fourth preset distance. For example: Continuing to refer to FIG. 7, the standard cell 700 corresponding to the inverter is arranged adjacent to the switch standard cell 100, the minimum spacing between the first wiring part 401 in the inverter and the connection part of the switch standard cell 100 is greater than or equal to the fourth preset distance, and the minimum spacing J between the second wiring part 402 in the inverter and the connection part of the switch standard cell 100 is greater than or equal to the fourth preset distance. By setting in this way, when two standard cells are spliced, the conductive parts of the same layer will not be short-circuited.

The following is a circuit schematic diagram shown in FIG10 to illustrate the layout design method provided by the present disclosure. The specific process is as follows:

S201, obtaining a circuit schematic.

As shown in Fig. 10, the circuit schematic diagram includes four switches and two inverters. The four switches are marked as a first switch K1, a second switch K2, a third switch K3 and a fourth switch K4, and the two inverters are marked as a first inverter Inv1 and a second inverter Inv2.

S202: Obtain the connection relationship and the state of the switch according to the circuit schematic.

The connection relationship between the two switches is obtained: the first end of the first switch K1 is connected to the first end of the third switch K3, the second end of the first switch K1 is connected to the first end of the second switch K2, and the second end of the third switch K3 is connected to the second end of the fourth switch K4.

A connection relationship between the two inverters is obtained: the output end of the first inverter Inv1 is connected to the input end of the second inverter Inv2.

The connection relationship between the inverter and the switch is obtained: the second end of the first switch K1 is connected to the input end of the first inverter Inv1, the output end of the second inverter Inv2 is connected to the first end of the fourth switch K4, and the second end of the second switch K2 is connected to the ground end.

The first switch K1 and the fourth switch K4 are in an off state, and the second switch K2 and the third switch K3 are in an on state.

S203, calling the switch standard cell 131 corresponding to the first switch K1, the switch standard cell 132 corresponding to the second switch K2, the switch standard cell 133 corresponding to the third switch K3, the switch standard cell 134 corresponding to the fourth switch K4, the standard cell 711 corresponding to the first inverter Inv1, and the standard cell 712 corresponding to the second inverter Inv2 for splicing.

That is, the switch standard cell 131 corresponding to the first switch K1, the switch standard cell 132 corresponding to the second switch K2, the switch standard cell 133 corresponding to the third switch K3, the switch standard cell 134 corresponding to the fourth switch K4, the standard cell 711 corresponding to the first inverter Inv1, and the standard cell 712 corresponding to the second inverter Inv2 are arranged adjacent to each other and aligned in sequence, and then automatic wiring connections are performed in the above standard cells according to the connection relationship.

A bridge 109 is arranged between the first connection structure 1041 and the second connection structure 1042 in the switch standard unit 132 corresponding to the second switch K2 , and a bridge 109 is arranged between the first connection structure 1041 and the second connection structure 1042 in the switch standard unit 133 corresponding to the third switch K3 .

Through the above steps, the layout structure shown in FIG. 11 is generated.

Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

A switch standard unit (100) comprises: a switch input portion (102), a switch output portion (103) and a connection portion (104) arranged in a frame area (101);

The switch input portion (102) and the switch output portion (103) are arranged in the same layer and extend in a first direction;

The connecting portion (104) is arranged in different layers from the switch input portion (102) and the switch output portion (103), and comprises a first connecting structure (1041) and a second connecting structure (1042) which are arranged at intervals along a first direction and both extend in a second direction; the first connecting structure (1041) is connected to the switch input portion (102), and the second connecting structure (1042) is connected to the switch output portion (103).
The switch standard unit (100) according to claim 1, wherein the frame area (101) comprises a first frame unit (1011) and a second frame unit (1012) arranged along the second direction;

The switch input portion (102) is located in the first frame unit (1011), and the switch output portion (103) is located in the second frame unit (1012); a portion of the first connection structure (1041) is located in the first frame unit (1011), and another portion is located in the second frame unit (1012); a portion of the second connection structure (1042) is located in the first frame unit (1011), and another portion is located in the second frame unit (1012).
The switch standard unit (100) according to claim 1 or 2, wherein the switch input portion (102) is connected to the first connection structure (1041) through a first conductive hole (107), and the switch output portion (103) is connected to the second connection structure (1042) through a second conductive hole (108).
The switch standard unit (100) according to claim 3, wherein the shortest distance between the edge of the first conductive hole (107) in the first direction and the edge of the first connection structure (1041) in the first direction is greater than or equal to a first preset distance; the shortest distance between the edge of the first conductive hole (107) in the second direction and the edge of the first connection structure (1041) in the second direction is greater than or equal to a second preset distance;

The shortest distance between the edge of the second conductive hole (108) in the first direction and the edge of the second connecting structure (1042) in the first direction is greater than or equal to a first preset distance; the shortest distance between the edge of the second conductive hole (108) in the second direction and the edge of the second connecting structure (1042) in the second direction is greater than or equal to a second preset distance.
The switch standard unit (100) according to claim 4, wherein a minimum spacing between the first connection structure (1041) and the second connection structure (1042) in the first direction is greater than or equal to a third preset distance.
The switch standard unit (100) according to any one of claims 1 to 5, wherein:

The standard unit comprises a first power wiring portion (105) and a second power wiring portion (106) which are arranged at intervals in the first direction and extend along the second direction;

The switch input portion (102), the switch output portion (103), and the connection portion (104) are located between the first power wiring portion (105) and the second power wiring portion (106).
The switch standard unit (100) according to claim 6, wherein the first power wiring portion (105), the second power wiring portion (106) and the connection portion (104) are arranged in the same layer.
A switch comprises a switch input portion (102), a switch output portion (103) and a connecting portion (104) arranged on a substrate (110);

The switch input portion (102) and the switch output portion (103) are arranged in the same layer and extend in a first direction;

The connecting portion (104) is arranged in different layers from the switch input portion (102) and the switch output portion (103), and comprises a first connecting structure (1041) and a second connecting structure (1042) which are arranged at intervals along a first direction and both extend in a second direction; the first connecting structure (1041) is connected to the switch input portion (102), and the second connecting structure (1042) is connected to the switch output portion (103).
The switch according to claim 8, wherein the switch input portion (102) and the switch output portion (103) are located on a first metal layer, and the connecting portion (104) is located on a second metal layer away from the substrate (110) relative to the first metal layer.
A layout design method, comprising:

Obtaining a circuit schematic diagram, wherein the circuit schematic diagram includes at least one switch and at least one gate-level circuit unit;

Obtaining a connection relationship and a state of the switch according to the circuit schematic; wherein the connection relationship includes at least one of a connection relationship between the switch and the gate-level circuit unit, a connection relationship between a plurality of the switches, and a connection relationship between a plurality of the gate-level circuit units;

When the switch is in an off state, calling the switch standard unit (100) according to any one of claims 1 to 7 and the standard unit corresponding to the gate-level circuit unit for splicing according to the connection relationship;

When the switch is in an on state, the switch standard unit (100) according to any one of claims 1 to 7 is called to be spliced with the standard unit corresponding to the gate-level circuit unit according to the connection relationship, and a bridge portion (109) is arranged between the first connection structure (1041) and the second connection structure (1042) so that the first connection structure (1041) and the second connection structure (1042) are connected through the bridge portion (109).
The layout design method according to claim 10, wherein the bridge portion (109) is arranged in the same layer as the first connection structure (1041) and the second connection structure (1042).
The layout design method according to claim 10 or 11, wherein obtaining the connection relationship and the state of the switch according to the circuit schematic diagram specifically includes:

A gate-level netlist is obtained according to the circuit schematic, and the connection relationship and the state of the switch are determined according to the gate-level netlist.
The layout design method according to any one of claims 10 to 12, wherein when two switch standard units (100) are adjacently spliced, a minimum spacing between the connecting portions (104) of the two switch standard units (100) is greater than or equal to a fourth preset distance.
According to the layout design method according to any one of claims 10 to 12, when the circuit schematic includes a plurality of the switches and any two of the switches are connected, the two switches are connected via wiring arranged in the polysilicon layer.
According to the layout design method according to any one of claims 10 to 12, wherein the standard cell corresponding to the gate-level circuit unit includes a third power wiring portion and a fourth power wiring portion, and the interval between the third power wiring portion and the fourth power wiring portion is the same as the interval between the first power wiring portion (105) and the second power wiring portion (106) in the switch standard cell (100); when the switch standard cell (100) is spliced with the standard cell corresponding to the gate-level circuit unit, the first power wiring portion (105) is aligned and spliced with the third power wiring portion so that the two are connected, and the second power wiring portion (106) is aligned and spliced with the fourth power wiring portion so that the two are connected.