JP6524493B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit in which a desired circuit is formed by arranging and connecting a plurality of standard cells including a transistor having a gate electrode in combination.

Generally, in the standard cell, at least one size in two directions (so-called vertical direction and horizontal direction) orthogonal to each other is standardized to several types, for example, approximately three types. The so-called vertical size is called the "height" of a standard cell, and this height is standardized and standardized to about three types. Here, since the size (height) of this cell is confused with the structural height in the vertical direction with the semiconductor substrate to cause misunderstanding, the size of the cell is not referred to as “height”. Instead, this size is hereinafter conveniently referred to as "standard cell length".
Even if the standard cell length of the standard cell is several types in the entire LSI, the same length is used when viewed locally, such as in the same circuit block, for efficient cell padding.
Therefore, various types of standard cells having the same standard cell length are prepared and registered in the library. Generally, the pattern of the internal wiring and the like of the standard cell has a limited arrangement space in the standard cell length direction.

  On the other hand, there are various sizes in the direction (so-called lateral direction) orthogonal to the common cell length direction of the standard cell depending on the size of the gate circuit. Hereinafter, the cell size in the direction orthogonal to the common cell length is referred to as “arbitrary cell length” for convenience.

In a logic circuit designed using a standard cell method, normally, an NMOS transistor and a PMOS transistor are connected in series between the VDD line and the VSS line to make an inverter sharing a gate the most basic circuit configuration. The most basic standard cell of the logic circuit, when the VDD line and the VSS line are alternately arranged in parallel, the distance between the VDD line center and the VSS line center is the standard cell length, and the direction along the VDD line or the VSS line Is the arbitrary cell length direction. Then, the most basic standard cell is designed by appropriately increasing or decreasing the size of the arbitrary cell length according to the circuit size of the standard cell. Such a basic standard cell has a standard cell length corresponding to one CMOS pair corresponding to the total length of the gates of NMOS and PMOS. Such a basic cell is hereinafter referred to as a "single height cell" because it has a height corresponding to a single CMOS pair.
The layout of a standard cell having such a standard cell length corresponding to one CMOS pair is described, for example, in Patent Document 1.

JP H10-173055 A

  However, there is no problem if the circuit to be realized by a standard cell is a basic logic gate circuit such as an inverter or a NAND circuit, but depending on the size of the circuit, a single height cell configuration may not be suitable.

For example, there are standard cells having a circuit configuration that requires common gates of several CMOS pairs to be driven in phase.
In this standard cell, although the PMOS transistor gate and NMOS transistor gate of each CMOS pair are connected by the gate line itself such as polysilicon, it is necessary to further short-circuit several gate lines. Therefore, the gate lines are connected to each other by the upper layer wiring (usually, the first-layer metal wiring). However, in the standard cell, many other internal wirings are required to connect the gate of a transistor to the source or drain of another transistor, and in some cases, it may not be possible to secure a space for connecting gate lines by upper wiring.

  Even if a space can be secured, a complicatedly bent wiring design is required, which may lower the workability of design and mask fabrication, leading to an increase in cost.

If space can not be secured, the standard cell specification can only increase the standard cell length to allow room or use the upper layer wiring.
However, when the standard cell length is increased, waste occurs in a portion other than the CMOS pair of the cell and a small scale basic circuit such as an inverter. Further, when a wire in the upper layer, for example, the second metal wire layer is used, this places a space for arranging other wires which are determined to be formed in the second metal wire layer.

  The present invention provides a cost-effective cell layout configuration that is less likely to waste space when including a standard cell for implementing a circuit that drives a plurality of complementary transistor pairs (for example, CMOS pairs) in phase. A semiconductor integrated circuit is provided.

  In the semiconductor integrated circuit according to the present invention, a desired circuit is formed by arranging and connecting a plurality of standard cells whose cell length is standardized between the pair of opposing sides in combination, and connecting them to each other. Complementary common mode drive type standard cell is included in the standard cell of. The complementary in-phase drive type standard cell is a cell including a plurality of complementary transistor pairs having complementary conductivity types and gate electrodes connected to each other, and N (≧ 2) pairs of the complementary transistor pairs are driven in phase. Further, the complementary in-phase drive type standard cell has a cell length M times that of the standard cell length M (N.gtoreq.M.gtoreq.2) times the basic cell length corresponding to one pair of the complementary transistor pair, and the standardized cell length. Size is specified. Then, in the complementary in-phase drive type standard cell, common gate electrodes of at least M pairs of N complementary transistor pairs driven in phase are linearly arranged in the direction of the M-fold cell length.

  In the present invention, preferably, a single height cell which is a standard cell of the basic cell length and a multi-height cell which is a complementary in-phase drive standard cell of the M-fold cell length form the desired circuit. Are placed adjacent to each other. In addition, preferably, the multi-height cell has a power supply line arrangement structure in which the single height cell and the power supply line can be shared when arranged adjacent to each other.

  According to the above configuration of the semiconductor integrated circuit of the present invention, when it is necessary to electrically short for in-phase driving, the gate electrodes of the plurality of complementary transistor pairs driven in-phase are common gate lines themselves. It is integrally formed. Therefore, the number of internal interconnections for gate line shorting is reduced accordingly, and no wasted space occurs. In addition, it is not necessary to form internal wiring of complicated shape.

  According to the above preferred configuration, since the power supply line sharing structure is provided with the adjacent single height cells, the advantage of the standard cell arrangement method is not impaired. At this time, the single height cell may be set as a minimum necessary basic cell length suitable for a small scale circuit. Since the standard cell length of the multi-height cell is a multiple of the basic cell length, even if the standard cell length of the multi-height cell is large, the power supply sharing structure with other surrounding cells can be secured. Also, in this case, since the single height cell has the necessary minimum size suitable for a small scale circuit, no space waste occurs in that sense.

  According to the present invention, when including a standard cell for realizing a circuit that drives a plurality of complementary transistor pairs (for example, a CMOS pair) in phase, a space waste is less likely to occur, and a cost-effective cell arrangement A semiconductor integrated circuit of the configuration can be provided.

It is a figure which shows typically the plane of the integrated circuit in connection with the 1st-3rd embodiment paying attention to cell arrangement. It is a layout figure for demonstrating the disadvantage of the layout method of a single height. It is an equivalent circuit schematic of the 1st application example in a 1st embodiment. FIG. 7 is a first layout diagram of a first application example in the first embodiment. It is a layout figure of comparative example 1 in a 1st embodiment. It is an equivalent circuit schematic of the 2nd application example in a 1st embodiment. FIG. 7 is a first layout diagram of a second application example in the first embodiment. It is a 2nd layout figure of the example of the 2nd application in a 1st embodiment. It is a layout figure of comparative example 2 in a 1st embodiment. It is an equivalent circuit schematic of the 3rd application example in a 1st embodiment. It is a layout figure of the example of the 3rd application in a 1st embodiment. It is an equivalent circuit schematic of the 4th application example in 1st Embodiment. It is a layout figure of the 4th application example in a 1st embodiment. It is a layout figure in a 2nd embodiment. It is a layout figure in a 3rd embodiment. It is a 1st layout figure of the example of a change. It is a 2nd layout figure of the example of a change.

Embodiments of the present invention will be described by taking double height and triple height circuit cells as major examples with reference to the drawings.
1. First embodiment: An embodiment in which a double height cell to which the present invention is applied is shown by four application examples (circuit examples). In Application Examples 1 and 2, the effects of the application of the present invention will be described using Comparative Examples 1 and 2.
2. Second Embodiment: Embodiment of a triple height cell to which the present invention is applied.
3. Third embodiment: an embodiment of an L-shaped cell (the same function as a triple height cell is realized by a double height) to which the present invention is applied.
4. Variations: Two variations on substrate contacts will be described.

<1. First embodiment>
[1. Overall layout]
FIG. 1 is a view schematically showing a plane of an integrated circuit according to the embodiment, focusing on cell arrangement.
Each square area in FIG. 1 is called a cell. The cell indicated by the symbol "SC" is a standard cell. The standard cell SC is a functional circuit cell such as an inverter or a NAND gate which is designed in advance, standardized, and registered in a library. The standard cell SC is a set of data, but may also refer to a part of a device manufactured based on the data. Although details will be described later, in the design of a semiconductor integrated circuit, standard cells registered in a library are combined and arranged. Due to the arrangement, the power supply voltage line and the reference voltage line (for example, the GND line) are substantially connected to each other on data. A desired circuit is obtained by connecting signal lines and the like after placement. The placement and routing up to this point is work on data by the design support apparatus.

Although FIG. 1 is a schematic plan view focusing on the cell arrangement of the semiconductor integrated circuit, it is also applicable as a cell arrangement diagram on data.
In the semiconductor integrated circuit 1 shown in FIG. 1, standard cells SC of various sizes are arranged in combination to realize a desired circuit. Here, the desired circuit can be realized as long as it is a logic circuit, depending on what the functional circuits of the individual standard cells SC are and how they are combined. FIG. 1 is a generalized diagram and it is optional what the desired circuit itself is.

  The standard cell design method is used in the design of an application specific integrated circuit (ASIC) or an application specific standard product (ASSP). An ASIC is an IC specifically developed and manufactured for a specific application for each customer, and an ASSP is an IC developed and manufactured as a general-purpose component for a plurality of customers.

Here, the size of the standard cell SC will be described.
Generally, in the standard cell SC, the cell length in the direction along one of the two orthogonal sides is standardized and standardized. This cell length direction is hereinafter referred to as "standard cell length direction". The size in the standard cell length direction (standard cell length) is not limited to one type in the entire IC, and may be several types, for example, three types. However, up to now, the standard cell length has been made uniform to one when viewed locally, such as one circuit block or a circuit that achieves a desired function. In the embodiment of the present invention, it is one of the major features that a plurality of standard cell lengths exist in a local circuit such as one circuit block or a circuit for achieving a desired function.

  Regarding this feature, in the example of FIG. 1, as the standard cell SC, the normal single-height standard cell SHSC and the multi-height standard cell MHSC are mixed. Here, as the multi-height standard cell MHSC, a double-height standard cell WHSC whose standard cell length is twice that of the single-height standard cell SHSC, and a triple-height standard cell THSC whose triple cell length is three times are exemplified.

  In the direction orthogonal to the standard cell length direction, the cell size can be arbitrarily determined. However, it is general that the size (defined by the number of grids) that can be taken discretely is determined, even if it is arbitrary, in consideration of design efficiency and consistency requirements. Hereinafter, the direction orthogonal to the standard cell length direction is referred to as “arbitrary cell length direction”.

As shown in FIG. 1, in the circuit block, VDD lines and VSS lines long in the arbitrary cell length direction are alternately arranged in the standard cell length direction. The distance between the VDD line and the VSS line corresponds to the height of the single height standard cell SHSC.
Furthermore, the double-height standard cell WHSC includes a type in which two VSS lines are arranged along both end sides in the standard cell length direction, and the VDD line passes through the center between them as indicated by a symbol “WHSC1”. Also, conversely to this, the double-height standard cell WHSC includes the type indicated by the symbol “WHSC2” in which two VDD lines are arranged along both end sides and the VSS line penetrates the center between them. It may be unified to one of these two types, but here two types are mixed in terms of placement efficiency.

[Single height layout]
Next, the reasons for mixing single-height standard cells SHSC and multi-height standard cells MHSC in the same circuit block will be clarified by describing the disadvantages of the main method of designing with only single-height cells.

FIGS. 2A to 2C show three types of single-height standard cells designed by a single-height layout method to form a CMOS logic circuit.
In these single-height standard cells SHSC_1, SHSC_2 and SHSC_3, a P-type impurity region 13P to be a source or drain of a PMOS transistor and an N-type impurity region 13N to be a source or drain of an NMOS transistor are between VDD and VSS lines Are arranged in parallel. This is because the CMOS logic circuit is based on an inverter. Polysilicon gate electrodes 20A and 20B forming an inverter input are orthogonal to a rectangular region including P-type impurity region 13P (hereinafter referred to as "PMOS active region 13P" with the same reference numeral as P-type impurity region 13P) It is wired straight. Further, polysilicon gate electrodes 20A and 20B are also applied to a rectangular region including N-type impurity region 13N (hereinafter, referred to as "NMOS active region 13N" with the same reference numeral as N-type impurity region 13N). They are arranged in a straight line so as to be orthogonal (FIGS. 2A and 2C). Therefore, the single-height standard cell has a height (standard cell length) corresponding to the complementary transistor pair (pair of NMOS and PMOS).

  In such a standard cell configuration, vertically long common gate electrodes (hereinafter referred to as CMOS gate lines) of the complementary transistor pair are arranged side by side. For this reason, the number of internal interconnections connecting the CMOS gate lines or the CMOS gate lines and other nodes (such as the source and drain of the transistor) increases. In addition, since it is necessary to arrange many internal wirings in a limited space, the wiring pattern becomes absolutely complicated. As a result, the number of vertexes and refracted portions increases in the layout figure of metal or polysilicon, and the shape becomes complicated.

In the advanced process, the more complicated the pattern shape, the more the design rules are restricted. In addition, if the pattern shape is complicated, optical proximity correction (OPC) processing in mask production takes time, or it is disadvantageous in terms of design for production (DFM). Here, DFM (Design For Manufacturing) is a technology for solving problems in LSI manufacturing at the design stage, and if the shape is simple in the cell layout, it is possible to mount a device with less variation in manufacturing time. This perspective is important.
Furthermore, due to the difficulty of the OPC correction, this may cause the yield of the actual device to be reduced.
The above is the first disadvantage in designing a logic circuit using only the single height standard cell SHSC.

The second disadvantage is that space is apt to be wasted.
Standard cells used for clock trees and the like may be laid out with different size ratios of PMOS and NMOS so that the clock delay is the same. For example, there may be a case where a standard cell (SHSC_2: FIG. 2B) in which the PMOS size is increased is larger than a normal standard cell (SHSC_1: FIG. 2A). Alternatively, there may be a standard cell (SHSC_3: FIG. 2C) in which the size of the NMOS transistor is reduced.

  In this case, when the PMOS active region 13P is increased in the lateral direction, a space is generated in the formation region of the NMOS transistor as shown in FIG. 2B. Conversely, if the NMOS active region 13N is reduced vertically, there is no increase in the area of the standard cell SC itself, but the area use efficiency itself decreases. These are waste of space for necessary functions, which is one of the reasons why high-density mounting can not be performed.

  In the embodiment of the present invention, a configuration of a complementary transistor pair (for example, a CMOS pair) type standard cell capable of eliminating these two disadvantages is proposed. The present invention is applied to a complementary in-phase drive type standard cell in which a plurality of complementary transistor pairs are driven in phase among complementary transistor pair type standard cells.

  Hereinafter, the layout configuration of the complementary in-phase drive type double-height standard cell WHSC to which the present invention is applied will be shown together with a circuit example in three examples.

[First application example]
FIG. 3 shows an equivalent circuit of a half adder cell as a circuit example of a standard cell SC to which the present invention is applied. The half adder shown in FIG. 3 is roughly divided into a carry out unit (CO unit) and a 1-bit addition unit (Sum unit). The half adder receives the first and second input bits (A1, A2), and the half add bit (S) which is the half add result of the first digit, and the carry out bit (hereinafter referred to as the digit) It is a circuit that outputs the raising bit (CO).
In FIG. 3, the gates of the CMOS pairs to which the same inputs and the like are given are indicated by bidirectional arrows.

  The carry out portion (CO) has a NAND circuit composed of two PMOS transistors P1 and P2 and two NMOS transistors N1 and N2, and an inverter composed of one PMOS transistor P3 and one NMOS transistor N3. Both are connected by a wire (internal wire 31) indicated by the symbol "31", and a reverse carry bit (NCO) appears there. The first input bit A1 is provided to the "P1 and N1" CMOS pair, and the second input bit A2 is provided to the "P2 and N2" CMOS pair.

  The 1-bit addition unit (Sum) includes four PMOS transistors P4 to P7 and four NMOS transistors N4 to N7, and includes inverted carry bits (NCO) and first and second input bits (A1 and A2). As input. The 1-bit addition unit (Sum) is a circuit that performs 1-bit addition, but the output is also 1 bit. Therefore, when the first input bit A1 and the second input bit A2 are both “1 (for example, H level)”, the 1-bit addition unit (Sum) is an inverted carry bit that is “0 (for example, L level)”. With the help of (NCO), perform half addition operation to set the output to "0".

  In such a configuration, when input bit pair (A1, A2) = (L, L), PMOS transistors P1 and P2 are turned on, so “NCO = H, CO = L” and a carry occurs. Absent. Further, since both PMOS transistors P5 and P6 are turned on, the inversion half addition bit (NS) = “H” which is the potential of internal connection line 33 forming the input node of the final stage inverter is set. The addition bit (S) = “L” is output.

  When the input bit pair (A1, A2) = (H, L), the PMOS transistor P1 is turned off, but the PMOS transistor P2 is turned on. There is no rise. Further, since the NMOS transistors N4 and N5 are both turned on, the inversion half addition bit (NS) = "L", and the half addition bit (S) = "H" is output.

  In the case of the input bit pair (A1, A2) = (L, H), the PMOS transistor P2 is turned off, but the PMOS transistor P1 is turned on. Therefore, similarly, “NCO = H, CO = L” and the digit There is no rise. Further, since the NMOS transistors N4 and N6 are both turned on, the inversion half addition bit (NS) = "L", and the half addition bit (S) = "H" is output.

  Then, in the case of the input bit pair (A1, A2) = (H, H), since the low side NMOS transistors N1 and N2 are both turned on contrary to the above, “NCO = L, CO = H” and so on. And a carry occurs. On the other hand, because of the influence of "NCO = L", even if the PMOS transistors P5 and P6 are off, the PMOS transistor P4 in parallel with it is turned on, so the inversion half addition bit (NS) = "H" and the half addition bit (S ) = "L" is output.

FIG. 4 is a layout diagram of the circuit of FIG. 3 designed by applying the present invention.
The standard cell illustrated in FIG. 4 is an example of the double-height standard cell WHSC1 (FIG. 1) in which a VDD line is disposed at the center.
In the double-height standard cell WHSC1, the VDD line 30D is arranged such that the center in the standard cell length direction (longitudinal direction) is elongated in the arbitrary cell length direction (horizontal direction). In addition, a VSS line 30S1 passing through one cell outer frame short side in the lateral direction as the width center and a VSS line 30S2 passing the other cell outer frame short side as the width center are parallel to each other and parallel to the VDD line 30D. Wired to. The VDD line 30D and the two VSS lines 30S1 and 30S2 are formed by patterning the first wiring layer (1M).

  The circuit (CO portion) generating the carry bit (CO) described in FIG. 3 is disposed in the lower half of the cell, sharing the VSS line 30S1 and the VDD line 30D. Further, a circuit (Sum unit) for generating a half addition bit (S) is disposed in the upper half of the cell, sharing the VSS line 30S2 and the VDD line 30D.

  The active regions of the same conductivity type, here PMOS active regions 11P and 12P, are arranged in line symmetry with the center line of the power supply line (VDD line 30D) passing through the inside of the cell as the axis of symmetry. Also, an NMOS active region 11N is disposed between the PMOS active region 11P and the VSS line 30S1, and an NMOS active region 12N is disposed between the PMOS active region 12P and the VSS line 30S2.

These four active regions are isolated and surrounded by the element isolation insulating layer 10, and the arrangement shape is horizontally long parallel to the power supply line.
Since the number of transistors in the CO portion is 6 while that in the Sum portion is 8, the PMOS active region 12P and the NMOS active region 12N have a shape longer than the NMOS active region 11N and the PMOS active region 11P. There is.

Three common gate electrodes 21 to 23 are linearly arranged by penetrating these four active regions in the longitudinal direction (standard cell length direction).
The common gate electrode 21 constitutes a common gate of the transistors (P1, N1, P5, N5) to which the first input bit A1 is input in FIG. 3, and in FIG. It shows the position.
The common gate electrode 22 constitutes a common gate of the transistors (P2, N2, P6, N6) to which the second input bit A2 is input in FIG. 3, and the common gate electrode 23 is an inverted carry in FIG. A common gate of transistors (P3, N3, P4, N4) to which a bit (NCO) is input is configured. The formation positions of these transistors are indicated by the same reference numerals in FIG.

  On the other hand, since the common gate electrode 24 of the remaining two transistors (P7, N7) needs to receive the inverted half added bit (NS) in the Sum portion, the other common gate passes through the PMOS active region 12P and the NMOS active region 12N. It is arranged shorter than the electrode.

  The internal wirings 31 to 35 shown in FIG. 3 appropriately connect sources, drains, and gates of different transistors in the shape as shown in FIG. 4 as wirings of the first wiring layer (1M) having the same reference numerals. Are arranged for. The specific connection relationship is omitted because it is apparent with reference to FIG.

[Features of layout according to invention application]
The first feature of such a layout is that the connection rule with the single layout power supply line arrangement is maintained. That is, the relationship between the VSS line 30S1 and the VDD line 30D and the relationship between the VSS line 30S2 and the VDD line 30D correspond to the standard cell length of the single height standard cell SHSC (FIG. 1). This correspondence makes it possible to share the power supply line when the single height cell is adjacent to the double height cell. Therefore, the double-height standard cell WHSC1 has the standard cell lengths of a plurality M (≧ 2, here, M = 2) with the standard cell length of the single-height cell as the basic cell length.

As a second feature, gate electrodes of a plurality of M (here, M = 2) pairs of complementary transistor pairs driven in phase are linearly arranged as a common gate electrode.
The common use of the gate electrode reduces the number of internal interconnections and allows other internal interconnections to have room for interconnections. If the arrangement of the internal wiring layer has a margin, wiring may be possible without complicated shapes, which may bring an advantage of improving yield and ease of manufacturing. In addition, since it is not necessary to connect between the gates using the upper layer wiring, a margin is also created in the arrangement of the upper layer wiring. In the case of this circuit example in particular, it is not necessary to connect between the gates in the second wiring layer in the upper layer as in the comparative example to be described later. Accompany.

  The third feature is that (M-1) power supply lines passing through the middle, in this case M = 2, one active line (11N and 12N) of the same conductivity type is centered on one VDD line 30D. It is arranged symmetrically.

  Further, as a fourth feature, in the portion of the element isolation insulating layer 10 located within the separation width of the two active regions, all gate electrodes overlapping the same are common gate electrodes 21 to 23 of the complementary transistor pair driven in phase. It has become. On the other hand, the common gate electrode 24 is not a common electrode of a plurality of complementary transistor pairs but a common electrode of an NMOS transistor and a PMOS transistor in one complementary transistor pair. Such an electrode does not overlap with the portion of the element isolation insulating layer 10 located within the separation width of the two active regions (it overlaps with the element isolation region at a portion outside this element isolation region portion).

  The meaning of this fourth feature is obvious when not considered. That is, in this active region separation width, it is assumed that two gate electrodes respectively coming from above and below extend and are separated within the active region separation width. In that case, in addition to the alignment margin (tolerance) for reliably overlapping each gate electrode with the active region in consideration of photomask misalignment, a separation space of the electrode itself is required. Therefore, there is a limit to the reduction between the active regions.

  On the other hand, in the case of the layout of FIG. 4 to which the present invention is applied, since the gate electrode is not separated, it is not necessary to consider the above-mentioned tolerance in this part and, of course, no separation space is necessary. What is necessary is a separation width necessary for element separation, but if it can be ensured, the two active regions can be brought close to each other, and a margin is created in the standard cell length direction. Since the standard cell length is determined to be M times the single height cell, there is no way to change it except by reviewing the basic cell length. The occurrence of this margin contributes to enlarging the transistor size by enlarging the channel width (generally called gate width) in the direction of the defined standard cell length, or to the arrangement of other internal wiring layers. Bring some room. If there is room in the arrangement of the internal wiring layers, wiring may be possible without complex shapes, which brings an advantage of improved yield and ease of manufacturing.

The above features are the same for triple heights described later.
Next, in order to make the above features and effects clearer, comparative examples to which the present invention is not applied will be described.

Comparative Example 1
FIG. 5 is a layout diagram of Comparative Example 1 in the case where the same circuit as FIG. 4 (FIG. 3) is realized by a horizontally long single height cell.
Basically, FIG. 4 and FIG. 5 are very similar except for the common use of the gate electrode, and the same configuration is given the same reference numeral and the description is omitted.

In FIG. 5, the CO portion and the Sum portion are disposed in parallel between the common VDD line 30D and the VSS line 30S, and receive power supply from both of them.
Further, the common gate electrodes 21 in the linear arrangement which was one in FIG. 4 are divided into two common gate electrodes 21A and 21B each of which is equivalent to one CMOS pair in FIG. Similarly, one common gate electrode 22 is divided into two left and right common gate electrodes 22A and 22B, and one common gate electrode 23 is divided into two right and left common gate electrodes 23A and 23B. ing.

  Since the common gate line is divided into two, it is necessary to electrically short between the gate electrodes shown by the double-sided arrows in FIG.

In order to achieve these connections, as a first solution, it is conceivable to achieve lateral connection with the common gate electrode itself (gate / polysilicon layer).
In order to short the common gate electrodes 21A and 21B, for example, the space between the PMOS active region 11P or 12P and the VDD line 30D needs to be expanded in the standard cell length direction. Further, in order to make the common gate electrodes 22A and 22B short-circuit each other, for example, it is necessary to expand the space between the NMOS active region 11N or 12N and the VSS line 30S in the standard cell length direction. Even in this case, since the common gate electrodes 23A and 23B can not be short-circuited with each other, the remaining pair of common gate electrodes can not but be short-circuited using the first wiring layer (1M). .

  In the first plan, it is necessary to extend the cell length in the standard cell length direction to secure the placement space for two common gate electrodes, but this is a large waste of space in the entire standard cell array. Because it occurs, it can not be adopted at all.

Therefore, as a second solution, a method of using the second wiring layer (2M) can be considered.
In FIG. 5, if the branches for the active region contacts of the power supply lines (30D, 30S) and the internal wirings (31 to 33) are retracted, at least one of them is the first layer for the short circuit of the common gate lines. It seems to be able to secure the placement space of the eye wiring layer (1M). However, it is impossible in terms of space to connect all three wires, and at least one wire must use the second wiring layer (2M) in the upper layer.

On the other hand, the first input bit A1, the second input bit A2 and the half addition bit (S) do not show the connection with the adjacent cell (not shown) in FIG. The second wiring layer (2M) may be used to connect to the adjacent cells, but the pattern of FIG. 5 does not require this. These three bit input / output lines can be achieved by changing the pattern of the first wiring layer (1M).
Even in such a case, the arrangement of FIG. 5 which requires the use of the second wiring layer (2M) only for the connection between the common gate electrodes wastes use of the wiring layer resources, resulting in a significant increase in cost. There is a disadvantage that causes

Thus, there is a disadvantage that both of the first and second plans are likely to cause a significant cost increase. The arrangement of FIG. 4 is superior to the comparative example of FIG. 5 in that such disadvantages are not caused.
It should be noted that in FIG. 4 there is an empty space corresponding to the small number of transistors in the CO portion, and this empty space does not occur in FIG. However, this free space is a free space in the arbitrary cell length direction, and as can be seen from FIG. 1, a large number of free spaces in the arbitrary cell length direction originally exist. Therefore, even if the size in the arbitrary cell length direction is slightly increased by the application of the present invention, the cost increase is not affected, or even if it is very slight. Rather, the application of the present invention that the standard cell length does not need to be extended or the upper layer wiring need not be used outweighs the disadvantage of increasing the size in the arbitrary cell length direction. Application of the present invention is effective in cost reduction.

  Further, the application of the present invention reduces the vertexes and the refracted portions in the layout figure of the first wiring layer (1M) and the wiring pattern of polysilicon and simplifies the shape. The application of the present invention brings about the benefit from the point of view of design for production (DFM) that reduces the number of mask manufacturing processes including OPC processing and the number of design processes, thereby further reducing the manufacturing cost and improving the yield. .

[Second application example]
6A and 6B show circuit symbols and equivalent circuit diagrams of clock buffer cells as another application example.
The clock buffer is a cell in which even-numbered stages of inverters are cascaded as shown in FIG. 6A, and the clock buffer is designed such that the duty ratio of the clock output from that cell is as equal as possible. For this reason, it is general that the PMOS size is larger or the NMOS size is smaller than that of a normal buffer.

  In the specific circuit of the clock buffer, as shown in FIG. 6B, each of the inverters INV1 and INV2 connected in cascade in FIG. 6A is configured by connecting two inverters in parallel. As described above, when the inverters INV1 and INV2 of the first and second stages are realized by connecting two inverters in parallel, the driving power of the inverters can be secured, and the present invention can be easily applied.

FIG. 7 shows an example in which the circuit diagram of FIG. 6 is laid out with double height.
In this layout diagram, the VDD line 31D is long in the center of the standard cell length in the arbitrary cell length direction, and in parallel with this, two VSS lines 31S1 and 31S2 centering on the two short sides on both sides of the standard cell length. Is arranged. These three power supply lines are formed using the second wiring layer (2M).

  The specific circuit configuration in the cell and the connection relationship are omitted because the circuit itself is simple. Here, the element isolation insulating layer 10, the PMOS active regions 11P and 12P, and the NMOS active regions 11N and 12N are arranged in the same manner as in the first application example as the configuration of the same reference numerals as in the first application example. In the first application example, the contact to the active region is achieved by providing the branch portion of the power supply line, but here, the power supply connection line 39D1, 39D2, formed of the first wiring layer (1M) This is achieved by providing 39S1 and 39S2.

  The internal wirings 36 and 37 are formed from the first wiring layer (1M) as a connection wiring between the inverters INV1 and INV2 as shown in FIG. 6 (B). The internal wiring 38 is formed of the first wiring layer (1M) as an output wiring of the inverter INV2, and the lower layer of the VDD line 31D is long in the standard cell length direction.

  Similar to the common gate electrodes 21 to 23 (FIG. 4) of the first application example, the common gate electrodes 25 and 26 are arranged long in parallel with each other in the standard cell length direction. The CMOS pair formed by the arrangement of the common gate lines is shown in the layout diagram of FIG. 7 with the same reference numerals as in FIG. 6B.

  Also in this layout, as in FIG. 4, the PMOS transistor can be formed to a region near the VDD line which can not be used in a normal single height cell. In addition, layout design is possible with a simple wiring layer pattern without expanding the size in the standard cell length direction in the wiring layer up to the first wiring layer (1M). Therefore, the size of the PMOS can be increased without causing an increase in cell area or an increase in free space, and a low-cost semiconductor integrated circuit with a high yield can be realized.

FIG. 8 is a layout diagram having a VSS line 31S long in the arbitrary cell length direction through the center in the standard cell length direction. Such a layout is also possible in the first application example of FIG.
8 differs from FIG. 7 in that a VSS line 31S is provided at the center, and VDD lines 31D1 and 31D2 are provided along cell short sides on both sides in the standard cell length direction. Along with this, the arrangement of the NMOS transistor and the PMOS transistor in the standard cell length direction is opposite to that in FIG. The other configuration is the same as FIG. 7 in FIG.

Comparative Example 2
FIG. 9 is a layout diagram of a cell as a comparative example to FIGS. 7 and 8.

  In the lateral layout of FIG. 9, the PMOS active region can not be brought close to the VDD line as shown in FIG. 7, and the NMOS active region can not be brought close to the VSS line as shown in FIG. In FIG. 9, the transistor size is restricted from these two points, and there is a disadvantage that the area can not be increased. Further, since each of the common gate electrodes 25 and 26 has an H shape, there is a disadvantage that the arrangement area is larger in the arbitrary cell length direction than in the case of FIGS. 7 and 8 in the linear shape. Furthermore, the shape of the internal wiring that combines the functions of the internal wirings 36 and 37 in FIG. 7 and FIG. For this reason, the cell size of an arbitrary cell length is also large at this point, and there is a disadvantage that when the cells are further miniaturized, the OPC processing becomes difficult and the possibility of lowering the yield is high.

  In other words, in the layout to which the present invention of FIGS. 7 and 8 is applied, the disadvantages associated with FIG. 9 are eliminated.

[Third application example]
FIG. 10 shows an equivalent circuit diagram of a third application example related to a modification of the second application example.
Compared with FIG. 6B, the clock buffer shown in FIG. 10 is provided with a PMOS transistor P10a having one larger size instead of the PMOS transistors P11 and P12 in the inverter INV1 of FIG. 6B. The same applies to the inverter INV2. That is, in place of the PMOS transistors P13 and P14 of FIG. 6B, a PMOS transistor P10b having a large size is provided.

FIG. 11 shows a plan view of a cell that implements the circuit of FIG.
Comparing FIG. 11 with FIG. 7, the PMOS active regions 12P and 11P separated in FIG. 7 are replaced with one vertically elongated PMOS active region 13P. Therefore, the isolation region (a part of the element isolation insulating layer 10) between the active regions required in FIG. 7 becomes unnecessary, and the size of the PMOS transistor can be increased accordingly. Alternatively, if the size of the PMOS transistor is the same, there is a margin for increasing the size of the NMOS transistor.
In addition, the modification of FIG. 8 with respect to FIG. 7 is similarly possible with respect to FIG.

Fourth application example
12 (A) and 12 (B) show circuit symbols and equivalent circuit diagrams of cells of a clock buffer capable of branched output as another application example in which FIG. 6 is modified.
The circuit of FIG. 12 differs from the circuit of FIG. 6 in that the inverter INV2 in the subsequent stage is divided into an inverter INV2A and an inverter INV2B, and each has an output node. In FIG. 12B, an internal wire 38A forming an output node of the inverter INV2A and an internal wire 38B forming an output node of the inverter INV2B are provided separately. The other configurations are basically the same as in FIG. 12 and FIG.

FIG. 13 shows an example in which the circuit diagram of FIG. 12 is laid out with double height.
The branch output type clock buffer does not have to cross the internal wiring of the output node with the central VDD line 31D in response to the output node being separated by the internal wiring 38A and the internal wiring 38B. Therefore, as shown in FIG. 13, the VDD line 31D (and the VSS lines 31S1 and 31S2) can be formed by the first wiring layer (1M). The connection between the power supply line and each active region is achieved by a branch line extending from the main line of each power supply line. The other configuration of FIG. 13 is the same as that of FIG.

<2. Second embodiment>
The second embodiment shows a triple height cell whose standard cell length is three times the basic cell length as a modification of FIG. 7 or FIG.

FIG. 14 shows a layout according to the second embodiment.
For example, if it is considered that the upper two rows of double height portions in FIG. 14 are the same as in FIG. 8, the lowermost portion is added to FIG. Alternatively, if it is considered that the lower two double height portions are the same as in FIG. 7, the uppermost portion is added to FIG. In FIG. 14, in the former view, the additional part is shown with a new code.
The equivalent circuit realized by the layout diagram of FIG. 14 is such that each of the inverters INV1 and INV2 of FIG. 6B has a 3-parallel inverter configuration.

  In the additional part (lower part), the code "10P" indicates a PMOS active region, and the code "10N" indicates an NMOS active region. Further, a VSS line indicated by a code "31D0" is newly added. A power connection line 39S2 and a power connection line 39D2 formed of the first wiring layer (1M) are provided on the VSS line 31D0 and the VDD line 31D1, respectively. The power supply connection line 39S2 and the power supply connection line 39D2 are branch lines for connecting the NMOS active region 10N and the PMOS active region 10P to the power supply line, respectively.

Although the internal wiring (36 + 37) is commonly wired long for the three basic cells of the standard cell length, this means that it is possible to connect two basic cells in FIGS. 7 and 8 as well. It is not a special feature of triple height cells.
The other configuration can basically be described by analogical application from the double height cell of FIGS. 7 and 8.

The modification from double height cells to triple height cells can be developed in the same manner for multi heights of triple height and more.
Also, the advantages of double height cells are followed in the same way for multi-height cells of triple or more.

<3. Third embodiment>
For triple or more multi-height cells, application to non-rectangular cells that are totally L-shaped can be possible.
As shown in FIG. 1, in the layout example of the standard cell system, generally, a large number of gaps are easily formed in the arbitrary cell length direction, but there are many cases where there is no margin in the standard cell length direction. Therefore, when it is desired to increase the number of CMOS pairs while limiting the height in the standard cell length direction, if a part thereof is accommodated in an L-shaped bending portion in the arbitrary cell length direction, there is no waste in the arrangement area There are also many.

  The third embodiment responds to such a request. For example, a layout as shown in FIG. 15 can be adopted.

  In FIG. 15, by combining the double height cell of FIG. 7 with the layout of the CMOS pair on the right side of the single height cell of FIG. 9, a cell having three CMOS pairs similar to FIG. 14 is realized. However, the use of the metal wiring layer is unified to the use of the two-layer metal wiring of FIG. Further, the common gate line indicated by reference numeral “27” has a planar shape which is branched in the lower layer of the VDD line 31D to be compatible with 3 CMOS. This constitutes a first stage three parallel inverter. In the subsequent third parallel inverter, the common gate electrode 28 and the H-type common gate electrode 26 (see FIG. 9) are commonly connected by the internal wiring (36 + 37) formed of the first wiring layer (1M) There are three CMOS pairs. In addition, a power supply branch line connected to the NMOS active region 12N is indicated by a code “39S0”, and a power supply branch line connected to the PMOS active region 12P is indicated by a code “39D0”. The description of the other configuration has already been described in FIG. 7 and FIG.

  In this embodiment, the same function as the triple height cell can be realized with the same standard cell length as the double height cell. This means that in the case where a large number of triple height cells are arranged, the layout of FIG. 14 or the layout of FIG. it can. This brings a great advantage that a more efficient layout is possible. However, in FIG. 15, since the common gate line 27 is branched at the intersection with the VDD line 31D, the PMOS active region 12P and the PMOS active region 11P can not be made very close to each other. However, the layout shown in FIG. 15 is useful because it has the above-mentioned great advantage that compensates for it.

  If the third embodiment is included, the number N of the complementary transistor pair driven in phase and the number M of the complementary transistor pair corresponding to the standard cell length of the multi-height layout do not necessarily match. That is, a multi-height layout of the above-described N and M satisfying the relationship of "NNM ≧ 2" is possible.

<4. Modified example>
Next, the modification regarding a substrate contact is shown.
In the first to third embodiments described above, the substrate contacts are not shown in the layout.

  FIGS. 16 and 17 show two examples of how to make a substrate contact. In these figures, the substrate contact portion is shown in detail in FIG. 4, but the same substrate contact method can be applied to other layout diagrams as well.

  Essentially, in the case where the gate / polysilicon layer wiring (common gate line) is passed to the place where there is a substrate contact, as shown in FIG. 14, the substrate contact SCH and the impurity region are appropriately deleted only where the gate / polysilicon layer passes. Here, the substrate contact SCH is also called a tap. More specifically, in the tap structure, a higher concentration N-type impurity region 14N is formed on the surface of the tap region connected to the PMOS active region 12P and the PMOS active region 11P on the substrate deep side of the element isolation insulating layer 10 ing. The substrate contact SCH is a connection plug between the N-type impurity region 14N and the first wiring layer (1M). Thus, the PMOS transistors formed in the PMOS active regions 11P and 12P are used by connecting their channel formation regions to the VDD voltage supplied from the VDD line 30D. Also, the source region of the PMOS transistor is powered by the branch from the VDD line 30D and the contact connected to the branch.

  On the other hand, also in the VSS lines 30S1 and 30S2, a large number of substrate contacts SCH are arranged for the same purpose. The substrate contact SCH at this location is provided to connect the NMOS active region 11N or 12N to the VSS voltage. Strictly speaking, a channel formation region or a substrate formed in the NMOS active region 11N or 12N is connected to the VSS voltage. That is, in this tap structure, P-type impurity region 14P of higher concentration is formed on the surface portion of the tap region connected to NMOS active region 11N or NMOS active region 12N on the substrate deep side of element isolation insulating layer 10. ing. The substrate contact SCH is a connection plug between the P-type impurity region 14P and the first wiring layer (1M). As a result, the channel formation regions of the NMOS transistors formed in the NMOS active regions 11N and 12N are connected to the VSS voltage and used. Also, the source region of the NMOS transistor is powered by the branch from the VSS line 30S1 or 30S2 and the contact connected to the branch.

Alternatively, as shown in FIG. 17, a circuit cell is prepared separately as a tapless cell having no substrate contact SCH (referred to as a tap), instead, a tap cell 2 is separately prepared and used in combination.
Since the tap cells 2 are appropriately disposed in the gaps appropriately formed in the arbitrary cell direction of FIG. 1, by providing the tap cells 2, it is considered that the arrangement of the circuit cells is not affected.

The following advantages can be obtained in the first to third embodiments described above.
First, it is possible to reduce metal wiring (internal wiring) wired in the lateral direction (arbitrary cell length direction), and metal wiring resources are effectively used.

  Second, as metal wiring resources increase, it becomes unnecessary to use higher layer metals.

  Thirdly, since the polysilicon gate wiring (common gate line) is wired to a place which does not exist in the case where the present invention is not applied, the polysilicon gate wiring wired in the lateral direction is eliminated, and the polysilicon wiring Resources increase.

Fourth, the shape of polysilicon gate wiring is simplified.
Fifth, by simplifying the shape of the polysilicon gate wiring, the layout area increases or the layout becomes easy in the diffusion area (active area).

  Sixth, by facilitating the layout of metal, polysilicon, and diffusion regions, the complexity of the figure is eliminated, which is effective in terms of design for production (DFM).

Seventh, it is possible to increase the PMOS size at a portion where the circuit cell is multi-height and the VDD line is shared, and the mounting area efficiency of the transistor can be improved.
Similarly, it is possible to increase the size of the NMOS at a portion where the circuit cell is multi-height and the VSS line is shared, and also in this point, the mounting area efficiency of the transistor can be improved.

  The above advantages take advantage of the fact that CMOS circuits are typically connected to the gate terminals of PMOS and NMOS transistors which are paired. For example, in the case of an inverter, a signal is connected to each gate terminal of one CMOS pair. In the first to third embodiments, when the input signal of the cell or the signal in the cell is connected to the gate terminals of a plurality of CMOS pairs, the CMOS pairs are intentionally laid out by multi-height. It is arranged vertically.

  Reference Signs List 1: semiconductor integrated circuit 2: tap cell 10: element isolation insulating layer 11N, 12N: NMOS active region 11P, 12P, 13P: PMOS active region 14N: N-type impurity region 14P: P-type impurity region 21 , 21A, 21B, 22, 22A, 22B, 23, 23A, 23B, 24, 25, 26, 27, 28 ... common gate electrode, 30D etc. ... VDD line, 30S etc. ... VSS line, 31-38 ... internal wiring, 39D1 etc. ... Power supply connection line, SHSC ... Single height standard cell, WHSC ... Double height standard cell, MHSC ... Multi height standard cell, THSC ... Triple height standard cell, 1 M ... First layer wiring layer, 2 M ... 2nd wiring layer

Claims (21)

A first power supply line extending in a first direction different from the second direction;
A second power supply line extending in the first direction;
A first active region of a first conductivity type different from the second conductivity type;
A second active region of the second conductivity type;
A third active region of the first conductivity type;
A fourth active region of the second conductivity type;
Multi-height standard cell,
A first gate electrode formed to drive a plurality of complementary transistor pairs;
A second gate electrode shorter than the first gate electrode,
A branch line disposed between the first gate electrode and the second gate electrode;
Have
One of the second power supply lines is disposed between one of the first power supply lines and the other one of the first power supply lines,
The first active region and the second active region are disposed between one of the first power supply line and one of the second power supply line,
The third active region is separated from the first active region and the second active region by an element isolation region;
The fourth active region is separated from the second active region and the third active region by an element isolation region, and the third active region and the fourth active region are connected to the second power supply line. Disposed between one of the first and second power supply lines,
The cell length of the multi-height standard cell is a distance in the second direction from one of the first power supply lines to another one of the first power supply lines,
The first gate electrode extends along the second direction in the multi-height standard cell, and includes at least the first active region, the second active region, the third active region, and the third active region. Overlap with the fourth active area,
The second gate electrode extends along the second direction in the multi-height standard cell and overlaps at least the first active region,
The branch line extends from the first gate electrode to the second gate electrode in the first direction. Further includes a single height standard cell,
The cell length of the single height standard cell is
The semiconductor integrated circuit according to claim 1, wherein a distance from one of the second power supply lines to one of the first power supply lines in the second direction. The semiconductor integrated circuit according to claim 2, wherein the third active region continuously extends in the first direction from the multi-height standard cell to the single-height standard cell. The single height standard cell includes a third gate electrode,
The semiconductor integrated circuit according to claim 2, wherein the third gate electrode overlaps at least the third active region. The semiconductor integrated circuit according to any one of claims 2 to 4, wherein a cell length of the multi-height standard cell is an integral multiple of a cell length of the single-height standard cell. The semiconductor integrated circuit according to any one of claims 2 to 4, wherein a cell length of the multi-height standard cell is twice a cell length of the single-height standard cell. The semiconductor integrated circuit according to any one of claims 1 to 6, wherein the branch line is in contact with a side portion of the first gate electrode. The semiconductor integrated circuit according to any one of claims 1 to 7, wherein the branch line is in contact with an end of the second gate electrode. The semiconductor integrated circuit according to any one of claims 1 to 8, wherein the branch line is disposed between a substrate and one of the first power supply lines. The semiconductor integrated circuit according to any one of claims 1 to 9, wherein the branch line extends from the first gate electrode to the second gate electrode. The semiconductor integrated circuit according to any one of claims 1 to 10, wherein the branch line is formed of a conductive material. The semiconductor integrated circuit according to any one of claims 1 to 11, wherein the first gate electrode and the second gate electrode are formed of a conductive material. The semiconductor integrated circuit according to any one of claims 1 to 12, wherein the first gate electrode intersects one of the second power supply lines. The semiconductor integrated circuit according to any one of claims 1 to 13, wherein the gate layer includes the first gate electrode, the second gate electrode, and the branch line. The semiconductor integrated circuit according to claim 14, wherein the first layer includes a wire. The semiconductor integrated circuit according to claim 15, wherein the second layer includes the first power supply line and the second power supply line. The semiconductor integrated circuit according to claim 16, wherein the gate layer, the first layer, and the second layer are arranged in order. The semiconductor integrated circuit according to claim 16, wherein the gate layer is disposed below the first layer and the second layer. The multi-height standard cell includes a transistor,
The semiconductor integrated circuit according to claim 15, wherein the wiring is connected to a source or drain region of the transistor. The semiconductor integrated circuit according to claim 15, wherein the wiring intersects with one of the second power supply lines at an intersection, and one of the second power supply lines is physically separated from the wiring at the intersection. The semiconductor integrated circuit according to any one of claims 1 to 20, wherein a metal layer includes the first power supply line and the second power supply line.

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