WO2024088555A1 - Boîtier semi-conducteur - Google Patents

Boîtier semi-conducteur Download PDF

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Publication number
WO2024088555A1
WO2024088555A1 PCT/EP2022/087677 EP2022087677W WO2024088555A1 WO 2024088555 A1 WO2024088555 A1 WO 2024088555A1 EP 2022087677 W EP2022087677 W EP 2022087677W WO 2024088555 A1 WO2024088555 A1 WO 2024088555A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor package
pcb
main surface
integrated circuit
metal layer
Prior art date
Application number
PCT/EP2022/087677
Other languages
English (en)
Inventor
Lasse Petteri PALM
Mirko Bernardoni
Samir Mouhoubi
Original Assignee
Huawei Digital Power Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Digital Power Technologies Co., Ltd. filed Critical Huawei Digital Power Technologies Co., Ltd.
Publication of WO2024088555A1 publication Critical patent/WO2024088555A1/fr

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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Definitions

  • the disclosure relates to the field of chip embedding and packaging technology for power packaging.
  • the disclosure relates to a semiconductor package and a second semiconductor package including said semiconductor package.
  • a 90 degree flipped power package is disclosed to enable modular vertical assembly of power electronics modules.
  • Chip embedding technology is a relatively new packaging technology that is nowadays used also for power packaging.
  • the main benefit of the embedding technology is that it allows to reduce the parasitic inductances and to maximize the electrical performance of the modules and at the same time to reduce the package size.
  • CE Chip Embedding
  • the normal chip embedding technology has similar challenges like other traditional packaging technologies to balance the signals between components in multidie configuration. Balancing of the routing between components in 2D configuration and in multidie configurations can be in most of the cases very challenging.
  • This disclosure provides a solution for overcoming the above-described problems with packaging and chip embedding technology, in particular the balancing of the routing between components in 2D configuration and in multidie configurations.
  • This disclosure presents a new type of high performance single or multidie package where the embedded dies are stacked and mounted vertically inside the final package.
  • the final package may be denoted as second semiconductor package hereinafter.
  • the manufacturing can be done horizontally by using normal CE/ECP embedding process and stacking several of these layers with embedded components above each other and connecting the layers together with plated sidewalls during the embedding by using normal PCB manufacturing processes.
  • the solution presented in this disclosure allows to improve the electrical performance of the modules by shortening and optimizing the connection between the dies and the package footprint and balancing the connections between e.g. paralleled components.
  • This disclosure presents characteristics and structure of stacked and by 90 degrees rotated multidie package modules and how such modules are manufactured.
  • a laminate-based package includes one or several stacked power dies.
  • the package is rotated by 90 degrees so that the power dies are vertically inside the package and the package has at least one partially metallized side wall that will be used as solder pads.
  • One or several power dies are embedded inside a laminate with CE/ECP technology.
  • Package is separated with dicing or cutting process so that one side of the plated via or slot is exposed.
  • the package is flipped by 90 degrees prior to the mounting to the PCB board. 5) The dies are vertically positioned inside the package.
  • the package can contain one, two or several layer with embedded dies.
  • the package can be used like a normal power package, e.g. a power package with paralleled power dies.
  • the modules can be in half bridge configuration, for example.
  • the techniques described in this disclosure can be applied to single and parallel (multiple) devices, integrated power stages/converters, e.g. buck, boost, buck/boost converters, halfbridge stages, etc.
  • integrated power stages/converters e.g. buck, boost, buck/boost converters, halfbridge stages, etc.
  • the disclosure provides a general solution that can be applied to a multitude of power electronics circuits and components.
  • the disclosed solution can be applied in power die packages for single die, multidie, paralleled dies, half bridges, power stages, DrMOS, and other types of power modules.
  • the solution can be applied with Si, SiC, GaN or other wide band-gap semiconductors and ultrawide bad-gap materials, e.g. Ga2O3.
  • the solution can be applied for lateral, vertical and semi-vertical current flow devices.
  • the solution can be applied with or without integrated passives and/or logic dies (e.g. driver, controller, etc.).
  • the solution can also be used for other types of modules without power dies.
  • FR-4 Composite material that is widely used PCB laminate. It consist of epoxy resin that is reinforced with woven glass fiber.
  • CE/ECP Chip embedding or embedded component packaging. Packaging technology where bare dies typically with Cu metallization are embedded inside PCB material and connected to the Cu routing on the package with plated pvias.
  • PTH Mechanically or laser drilled hole with typically 20-30pm plated Cu on the side walls.
  • LTI Lead Tip Inspection is a method used especially in automotive and it allows optical inspection to check the soldering quality of all connection.
  • the pads on the package are exposed on the side of the package allowing the solder wetting and fillet on the side wall.
  • chip embedding technologies are described. There are several different types of embedding processes available: In a typical chip embedding process, the electronic components (chips, capacitors, resistors, etc.) are either placed inside an opening in a PCB core layer or soldered on a two or multilayer PCB board. The actual embedding inside the final PCB board can be performed by laminating FR4 prepregs or other polymer sheets above and below the core layer that holds the components to be embedded.
  • the electrical connection between the embedded components and the PCB metal layers can be formed by soldering the component terminals to the inner laminate layers and subsequently laminating the PCB layers together.
  • the components can be electrically connected by galvanically filled micro vias which is more robust, since there is no remelting of solder inside the package or board, which has to be considered when mounting the other components to the outer layers of the PCB by additional reflow processes.
  • the micro vias are usually formed after lamination by laser drilling from the top surface through the thin laminate layer to the active chip pads or to the terminals of an embedded component package.
  • Cu copper
  • This conductivity establishes an electrical connection between different Cu layers and/or components and Cu tracks. It also enhances mechanical stability and reduces the overall resistance to support smooth current flow.
  • the average Cu plating thickness is minimum 20 pm.
  • side wall connections are described. These side wall connections can be plated and arranged on an outer surface of the package. To manufacture these side wall connections PCB processes can be used. On panel level, large plated through holes can be mechanically drilled or oval slots can be mechanically milled along the package outline before plating/separation. After drill ing/milling electroless and electrochemical plating processes can be applied to plate a metal layer, e.g., a metal layer of 20-30pm Cu, on the through holes or the oval slots.
  • a metal layer e.g., a metal layer of 20-30pm Cu
  • the plated through holes or slots can be cut in half such that a section of the through hole or slot is left to one side of the cut and another section is left to the opposite size of the cut, where the cutting line defines the package outline.
  • the disclosure relates to a semiconductor package comprising: at least one integrated circuit comprising at least one first connection terminal and at least one second connection terminal for an electrical connection of the at least one integrated circuit; an encapsulant encapsulating at least part of the at least one integrated circuit, the encapsulant comprising a first main surface and a second main surface opposing the first main surface, and one or more side walls between the first main surface and the second main surface; a first metal layer placed upon a portion of a first side wall of the one or more side walls of the encapsulant, wherein the first metal layer forms a first connector for electrically connecting the at least one first connection terminal of the at least one integrated circuit; and a second metal layer placed upon another portion of the first side wall of the encapsulant, wherein the second metal layer forms a second connector for electrically connecting the at least one second connection terminal of the at least one integrated circuit; wherein the first connector and the second connector of the semiconductor package are configured for attachment to respective metal traces of a printed circuit board, PC
  • Such a semiconductor package provides the technical advantage of a fully balanced power package where the integrated circuits, e.g. power dies, can be connected parallel or in half bridge configuration or in other configuration.
  • the components can be mounted vertically inside the final package, hereinafter also referred to as the second semiconductor package, and multiple components can be stacked together.
  • the semiconductor package allows to minimize the current path length and fully balance the source, drain and gate connections due to symmetrical current paths to both, source and gate pads or to the both drain pads in case of parallel die package.
  • the high side (HS) and low side (LS) switches can be embedded inside different layers that are stacked to each other's.
  • the semiconductor package allows to minimize the distance between drain and source connection and maximize the line width and depending on the configuration to optimize and minimize the Vin and Vswh or Pgnd and Vswh connection paths. In half bridge configuration the semiconductor package allows also partial shielding. The semiconductor package also allows to improve the thermal performance of the package while the generated heat can be conducted away from the power dies also from the package side walls.
  • the at least one integrated circuit can be a vertical device, e.g. as shown in Figure 1 , or a lateral device, e.g. as shown in Figure 10.
  • the device can have three terminals although only two of them are described here.
  • the first main surface and the second main surface form two main areas of the semiconductor package, each main area covering a larger area than any one of the side walls of the encapsulant.
  • the semiconductor package can be fabricated as a flat package with two main surfaces and flat side walls between the main surfaces. Such fabrication can be efficiently performed by using normal PCB fabrication techniques.
  • the first metal layer is placed both, upon the portion of the first side wall and upon a portion of the first main surface; and/or wherein the second metal layer is placed both, upon the other portion of the first side wall and upon another portion of the first main surface.
  • the first metal layer and the second metal layer can be electrically contacted from two sides of the semiconductor package.
  • a large contact area is available that extends over two sides of the package for contacting the first and second metal layers and the respective connection terminals.
  • the first metal layer is placed upon an edge portion of the encapsulant, the edge portion comprising the portion of the first side wall, the portion of the first main surface and a portion of a second side wall contiguous to the first side wall; and/or wherein the second metal layer is placed upon another edge portion of the encapsulant, the other edge portion comprising the other portion of the first side wall, the other portion of the first main surface and a portion of a third side wall opposing the second side wall.
  • the respective terminal of the integrated circuit can be electrically contacted from three sides of the semiconductor package. A large contact area is available for contacting the respective terminal enabling a flexible contacting design.
  • the encapsulant comprises two or more PCB layers, each PCB layer having a first main PCB surface and a second main PCB surface opposing the first main PCB surface; and the first main PCB surface and the second main PCB surface of the two or more PCB layers are arranged in parallel to the first main surface and the second main surface of the encapsulant.
  • the semiconductor package can be produced as a multi-layer PCB board which can be vertically mounted and a symmetrical double-side cooling can be implemented for the semiconductor package.
  • the vertical direction is the direction of the vertical axis with respect to the PCB onto which the semiconductor package (e.g. the multi-layer PCB board) is to be mounted, e.g. the axis that is orthogonal to the mounting PCB.
  • the semiconductor package comprises: at least one first via configured to route at least one third connection terminal of a first integrated circuit to a portion of the second metal layer placed on the first main surface; and at least one second via configured to route the at least one first connection terminal of the first integrated circuit to a portion of the first metal layer placed on the second main surface.
  • the vias can route the connection terminals of the integrated circuits to the respective first and second main surfaces of the encapsulant for external connection to the mounting PCB.
  • the semiconductor package comprises: at least one first via configured to route at least one third connection terminal of a first integrated circuit to a portion of the second metal layer placed on the first main surface; and at least one second via configured to route at least one second connection terminal of a second integrated circuit to a portion of the second metal layer placed on the second main surface.
  • the vias can route the connection terminals of the integrated circuits to the respective first and second main surfaces of the encapsulant for external connection to the mounting PCB.
  • the first integrated circuit and the second integrated circuit form a parallel die configuration. Therefore, in a parallel die configuration, the semiconductor package allows to minimize the current path length and fully balance the source, drain and gate connections due to symmetrical current paths to both drain pads.
  • the semiconductor package comprises: at least one first via configured to route at least one third connection terminal of a first integrated circuit to a portion of the second metal layer placed on the first main surface; and at least one third via configured to route at least one first connection terminal of a second integrated circuit to a portion of the first metal layer placed on the second main surface.
  • an IC with three connection terminals such as a MOSFET or IGBT can be fully balanced in this semiconductor package.
  • This allows to advantageously apply the semiconductor package in a multitude of power electronics circuits and components such as an integrated power stage or converter, e.g. buck, boost, buck/boost converter, half-bridge stage, etc.
  • the first integrated circuit and the second integrated circuit form a half bridge configuration.
  • the semiconductor package allows to minimize the current path length and fully balance the source, drain and gate connections due to symmetrical current paths to both, source and gate pads.
  • at least the first integrated circuit and the second integrated circuit are stacked between the first main surface and the second main surface of the encapsulant.
  • Such configuration provides the advantage that both integrated circuits can be stacked over each other. This results in symmetric orientation of both integrated circuits with respect to each other, thereby allowing to reduce the influence of parasitic components in the assembly. The influence of parasitic components can be compensated because of the same line lengths due to the symmetry of the ICs.
  • an aspect ratio of each of the stacked integrated circuits is higher than 1. This provides improved thermal dissipation. Due to drain-source on resistance (Rdson) non-uniformity caused by thermal distribution, Rdson in semiconductor devices is high at the center of the die and less high at the edges. This property is valid for any semiconductor device, in particular, lateral devices and vertical devices. For example, the die is hot in the center and cold at the edges. An aspect ratio higher than 1 can improve thermal dissipation.
  • the disclosure relates to a second semiconductor package comprising: the semiconductor package according to the first aspect described above; and a printed circuit board, PCB, comprising a first metal trace and a second metal trace; wherein the semiconductor package is mounted by the first side wall onto the PCB, the first connector of the PCB being attached to the first metal trace and the second connector of the PCB being attached to the second metal trace of the PCB.
  • the PCB onto which the semiconductor package is mounted can be a flat board with a main surface onto which both, the first metal trace and the second metal trace are printed or attached.
  • Such a second semiconductor package also referred to as “final product”, provides a fully balanced power package where the integrated circuits, e.g. power dies, can be connected parallel or in half bridge configuration or in other configuration.
  • the components can be mounted vertically inside the final package and multiple components can be stacked together.
  • the semiconductor package allows to minimize the current path length and fully balance the source, drain and gate connections due to symmetrical current paths.
  • the second semiconductor package allows to improve the thermal performance of the package while the generated heat can be conducted away from the power dies also from the package sides.
  • each of the first main surface and the second main surface of the encapsulant form an angle within a threshold range around 90 degrees with a main surface of the PCB.
  • semiconductor packages according to the first aspect can be mounted vertically inside the final package (second semiconductor package) and multiple of such semiconductor packages can be stacked together.
  • the at least one integrated circuit comprises a first main die surface and a second main die surface opposing the first main die surface, wherein both, the first main die surface and the second main die surface form an angle within a threshold range around 90 degrees with the main surface of the PCB. This means that the die is arranged in an angle of 90 degree with the PCB surface including small deviations from the 90°.
  • Integrated circuits can be mounted vertically inside the semiconductor package and inside the final package and multiple of such integrated circuits can be stacked together.
  • the first metal layer is placed both, upon the portion of the first side wall and upon a portion of the first main surface; wherein a solder fillet is applied to the first side wall and the first main surface for electrically and mechanically connecting the semiconductor package with the PCB.
  • Solder filled provides a large electrical contact ranging over the first main surface and the first side wall. This results in mechanical stability and improved electrical and thermal conductivity.
  • Embodiments of the disclosure may comprise the following features: i) Flipping the dies and the package 90 degree. Accordingly, small footprint, effective, short, large cross section and symmetrical connection between the dies and the footprint is provided. ii) Use of plated side walls as a footprint. Accordingly, the package foot print can be on the side wall of the package and allows to flip the package with 90 degree prior to assembly. A footprint that extends also to the side wall of the package allows LTI inspection. iii) Balanced and symmetrical source, drain and gate connections. This provides improved efficiency and switching behaviors.
  • Embodiment 1 presents a solution to manufacture half bridge modules.
  • Embodiment 2 presents a solution to manufacture parallel power dies.
  • Embodiment 3 presents a solution how to split a Gallium-Nitride (GaN) die into smaller stripe-sized dies and connect multiple smaller GaN dies parallel inside the package.
  • Embodiment 4 presents the manufacturing process how these stacked and by 90 degrees flipped power components or modules can be manufactured.
  • the idea presented in this disclosure is not only limited to these embodiments also other type of configurations can be manufactured, e.g., power stage/DrMOS (driver + LS and HS mosfet), etc.
  • Figure 1 shows a side view and a cross section view (AB) of a semiconductor package 100 vertically mounted on a PCB 190 according to the disclosure;
  • Figure 2 shows a 3D view of the PCB mounted semiconductor package 100 of Figure 1;
  • Figure 3 shows cross section views of different embodiments 100a, 100b, 100c, 100d of a semiconductor package vertically mounted on a PCB 190;
  • Figure 4 shows two side views 400a, 400b of a half bridge semiconductor package and two side views 400c, 400d after 90 degree flipping;
  • Figure 5 shows a schematic diagram of an exemplary process flow 500 for producing embedded power cores according to the disclosure
  • Figure 6 shows a schematic diagram of an exemplary process flow 600 for producing a semiconductor package 100 according to the disclosure
  • Figure 7 shows different side views of a parallel die package 710 according to an embodiment where dies are facing in the same direction;
  • Figure 8 shows different side views of a parallel die package 810 according to an embodiment where dies are facing in different directions
  • Figure 9 shows different side views of a half bridge package 910 according to an embodiment
  • Figure 10 shows a cross sectional view of a lateral semiconductor device 1000 according to an embodiment
  • Figure 11 shows schematic diagrams of a standard square-sized layout 1102 of a power device and an improved rectangular layout 1103 of a power device according to the disclosure; and Figure 12 shows a side view 1201, a cross section 1202 and a footprint 1203 of a semiconductor package with paralleled dies according to an embodiment.
  • Figure 1 shows a side view and a cross section view (AB) of a semiconductor package 100 vertically mounted on a PCB 190 according to the disclosure.
  • the semiconductor package 100 comprises: at least one integrated circuit 140, an encapsulant 150, a first metal layer 110 and a second metal layer 120.
  • the at least one integrated circuit 140 comprises at least one first connection terminal 141 and at least one second connection terminal 143 for an electrical connection of the at least one integrated circuit 140.
  • the encapsulant 150 is encapsulating at least part of the at least one integrated circuit 140.
  • the encapsulant 150 comprises a first main surface 150a and a second main surface 150b opposing the first main surface 150a, and one or more side walls 151 , 152, 153, 154 between the first main surface 150a and the second main surface 150b as can be seen from Figure 1.
  • the first metal layer 110 is placed upon a portion of a first side wall 151 of the one or more side walls 151 , 152, 153, 154 of the encapsulant 150.
  • the first metal layer 110 forms a first connector 181 for electrically connecting the at least one first connection terminal 141 of the at least one integrated circuit 140.
  • the second metal layer 120 is placed upon another portion of the first side wall 151 of the encapsulant 150.
  • the second metal layer 120 forms a second connector 182 for electrically connecting the at least one second connection terminal 143 of the at least one integrated circuit 140.
  • the first connector 181 and the second connector 182 of the semiconductor package 100 are configured for attachment to respective metal traces 191 , 192 of a printed circuit board, PCB 190, as can be seen from Figure 1 .
  • the at least one integrated circuit 140 can be a vertical device, e.g., as shown in Figure 1 , or a lateral device, e.g., as shown in Figure 10.
  • the device can have three terminals although only two of them are described here.
  • the first main surface 150a and the second main surface 150b form two main areas of the semiconductor package 100, each main area covering a larger area than any one of the side walls of the encapsulant 150.
  • the first metal layer 110 may be placed both, upon the portion of the first side wall 151 and upon a portion of the first main surface 150a.
  • the second metal layer 120 may be placed both, upon the other portion of the first side wall 151 and upon another portion of the first main surface 150a.
  • the first metal layer 110 may be placed upon an edge portion of the encapsulant 150 which edge portion comprises the portion of the first side wall 151 , the portion of the first main surface 150a and a portion of a second side wall 152 contiguous to the first side wall 151, as can be seen from the left-side view of Figure 1.
  • the second metal layer 120 may be placed upon another edge portion of the encapsulant 150, the other edge portion comprising the other portion of the first side wall 151 , the other portion of the first main surface 150a and a portion of a third side wall 153 opposing the second side wall 152, as can be seen from the left-side view of Figure 1.
  • the encapsulant 150 may comprise two or more PCB layers, each PCB layer having a first main PCB surface and a second main PCB surface opposing the first main PCB surface.
  • the first main PCB surface and the second main PCB surface of the two or more PCB layers may be arranged in parallel to the first main surface 150a and the second main surface 150b of the encapsulant 150.
  • the semiconductor package may comprise at least one first via 113 configured to route at least one third connection terminal 142 of a first integrated circuit 140 to a portion of the second metal layer 120 placed on the first main surface 150a as can be seen from the right-side view of Figure 1.
  • the semiconductor package may comprise at least one second via 111 , as can be seen from the right-side view of Figure 1 , configured to route the at least one first connection terminal 141 of the first integrated circuit 140 to a portion of the first metal layer 110 placed on the second main surface 150b.
  • the semiconductor package 100 may comprise: at least one first via 113 configured to route at least one third connection terminal 142 of a first integrated circuit 140 to a portion of the second metal layer 120 placed on the first main surface 150a as can be seen from the rightside view of Figure 1.
  • the semiconductor package 100 may comprise at least one second via 116 configured to route at least one second connection terminal 162 of a second integrated circuit 160 to a portion of the second metal layer 120 placed on the second main surface 150b as can be seen from the right-side view of Figure 1.
  • the first integrated circuit 140 and the second integrated circuit 160 may form a parallel die configuration.
  • the semiconductor package 100 may comprise: at least one first via 113 configured to route at least one third connection terminal 142 of a first integrated circuit 140 to a portion of the second metal layer 120 placed on the first main surface 150a as can be seen from the rightside view of Figure 1.
  • the at least one third via 114 may be configured to route at least one first connection terminal 161 of a second integrated circuit 160 to a portion of the first metal layer 110 placed on the second main surface 150b.
  • the first integrated circuit 140 and the second integrated circuit 160 may form a half bridge configuration.
  • At least the first integrated circuit 140 and the second integrated circuit 160 may be stacked between the first main surface 150a and the second main surface 150b of the encapsulant 150 as can be seen from the right-side view of Figure 1.
  • An aspect ratio of each of the stacked integrated circuits can be higher or equal than 1. In this configuration (without GaN) the aspect ratio can be 1.
  • Figure 1 also shows a second semiconductor package 200, also referred to as the final product.
  • the second semiconductor package comprises: the semiconductor package 100 as described above; and a printed circuit board, PCB, 190 comprising a first metal trace 191 and a second metal trace 192.
  • the semiconductor package 100 is mounted by the first side wall 151 onto the PCB 190.
  • the first connector 181 of the PCB 190 is attached to the first metal trace 191 and the second connector 182 of the PCB 190 is attached to the second metal trace 192 of the PCB 190.
  • Each of the first main surface 150a and the second main surface 150b of the encapsulant 150 may form an angle within a threshold range around 90 degrees with a main surface 195 of the PCB 190.
  • the encapsulant 150 is arranged in an angle of 90 degree with the PCB surface 195 including small deviations from the 90°.
  • the at least one integrated circuit 140 comprises a first main die surface 140a and a second main die surface 140b opposing the first main die surface 140a. Both, the first main die surface 140a and the second main die surface 140b may form an angle within a threshold range around 90 degrees with the main surface 195 of the PCB 190.
  • the die is arranged in an angle of 90 degree with the PCB surface 195 including small deviations from the 90°.
  • the first metal layer 110 may be placed both, upon the portion of the first side wall 151 and upon a portion of the first main surface 150a.
  • a solder fillet 201 may be applied to the first side wall 151 and the first main surface 150a for electrically and mechanically connecting the semiconductor package 100 with the PCB 190.
  • Figure 2 shows a 3D view of the PCB mounted semiconductor package 100 of Figure 1.
  • Figure 2 illustrates an embodiment that is to manufacture a laminate-based package 100 that has at least partially metallized side walls that can be used as solder pads.
  • the package 100 can be mounted on the substrate 190, e.g., PCB, so that it is flipped by 90 degrees (dies are inside the package vertically) and metallized sided walls are used as solder pads.
  • the package can contain one, two or several layer with embedded dies.
  • the pads can locate underneath the flipped package and on both ends of the flipped package, for example.
  • the semiconductor package 100 is vertically mounted on the PCB 190.
  • the first metal layer 110 can be placed both, upon the portion of the first side wall 151 and upon a portion of the first main surface 150a.
  • a solder fillet 201 can be applied to the first side wall 151 and the first main surface 150a or the first side wall 151 and the second main surface 150b (as shown in Figure 2) for electrically and mechanically connecting the semiconductor package 100 with the PCB 190.
  • Figure 3 shows cross section views of different embodiments 100a, 100b, 100c, 100d of a semiconductor package vertically mounted on a PCB 190.
  • connection terminals corresponds to the configuration of the connection terminals as shown in Figure 1.
  • Figure 3 presents different stacking options and configurations.
  • the package can include other components, e.g., driver, passives, etc.
  • the pads can locate underneath and on both ends of the 90° flipped package.
  • a single die configuration is illustrated, where the source and the drain pads of the die are routed to the opposite sides of the flipped package.
  • the package can contain two or more PCB layers.
  • the semiconductor package 100a comprises at least one first via 113 configured to route the third connection terminal 142 of the single integrated circuit 140 to a portion of the second metal layer 120 placed on the first main surface 150a.
  • the semiconductor package 100a comprises at least one second via 111 configured to route the first connection terminal 141 of the single integrated circuit 140 to a portion of the first metal layer 110 placed on the second main surface 150b.
  • a multi die configuration is illustrated, including three or more dies (or integrated circuits).
  • the dies can be connected in parallel or in another configuration.
  • a dual die configuration is illustrated, where two dies are located inside the same package and the dies are facing in different directions.
  • This third configuration illustrates the paralleled dies configuration, but it can also be a half bridge configuration.
  • the semiconductor package 100c comprises at least one first via 113 configured to route at least one third connection terminal 142 of a first integrated circuit 140 to a portion of the second metal layer 120 placed on the first main surface 150a.
  • the semiconductor package 100c comprises at least one second via 116 configured to route at least one second connection terminal 162 of a second integrated circuit 160 to a portion of the second metal layer 120 placed on the second main surface 150b.
  • the first integrated circuit 140 and the second integrated circuit 160 may form a parallel die configuration.
  • a fourth configuration of the semiconductor package 100d a dual die configuration is illustrated, where two dies are located inside the same package and the dies are facing to the same direction.
  • This third configuration illustrates the half bridge configuration.
  • the routing in the picture can be applied for the paralleled dies configuration but can also be done for the half bridge configuration.
  • the semiconductor package 100d comprises at least one first via
  • the semiconductor package 100d comprises at least one third via
  • first integrated circuit 140 and the second integrated circuit 160 may form a paralleled dies configuration (shown here), but they may also form a half bridge configuration (not shown here).
  • Figure 4 shows two side views 400a, 400b of a half bridge semiconductor package and two side views 400c, 400d after 90 degrees flipping.
  • This half bridge semiconductor package corresponds to a first embodiment of the semiconductor package as mentioned above.
  • High Side (HS) 401 and Low Side (LS) 402 are in different layers and connected together with plated side walls 403 and optionally with Plated Through Holes (PTH).
  • PTH Plated Through Holes
  • the modules After embedding and PCB manufacturing the modules are separated and mounted on the final PCB board by flipping the modules by 90°.
  • the solder pads are on one side of the module and can be extended also to other sides.
  • both gate pads are marked as GL (Gate low side) and GH (Gate high side) and terminals VSWH, PG ND and VI N are shown.
  • a half bridge package is presented. At least one power die is embedded in a PCB layer and stack at least two of these layers with embedded dies together.
  • the connections between the HS and LS power dies can be performed with plated PTHs or slots that are diced half during package separation. If needed additional though holes or hybrid bonding can be used to make the connection between HS and LS more effective.
  • additional PCB layers that may include Cu structures or embedded Cu blocks to improve the thermal performance, can be added.
  • the module is flipped by 90° and mounted on the PCB so that the dies are vertically inside the package.
  • additional routing or other process can be used to remove the PCB areas between the routed Cu slots.
  • Different kinds of processes to manufacture the plated side wall connections are existing in PCB industry and those can be used to manufacture plated side wall connections in this disclosure.
  • Figure 5 shows a schematic diagram of an exemplary process flow 500 for producing embedded power cores according to the disclosure.
  • Figure 5 illustrates embedding of at least two power dies 140 inside separate PCB core layers that are laminated with respect to each other, and the components are connected together and to the footprint with plated side wall connections.
  • the plated side wall connections can be manufactured with plated and normal PTH and/or routing process. An example of such manufacturing flow how core layers with embedded components can be manufactured is presented in Figure 5.
  • bare dies with Cu metallization are embedded inside an opening of the core layer.
  • the opening of the core layer can be implemented for example by laser cutting (also routing, punching, etc. can be used).
  • a tape is laminated on the bottom side of the core layer and the die is placed inside the opening and attached to the tape with a pick and placement machine.
  • a prepreg sheet and a Cu foil are prelaminated on the top side of the core layer with a vacuum laminator. Then the bonding tape is removed and another prepreg and Cu foil are laminated on the bottom side (during second lamination the pre laminated prepreg is also fully cured). After lamination vias to the die from both sides are drilled with laser drilling. The dies are connected and the vias filled with electroless and electrochemical plating. Finally, the Cu is structured with lithography and etching processes.
  • the process flow 500 comprises multiple process steps or process blocks and can be described as follows.
  • a first step 501 may comprise: providing a printed circuit board, PCB, core layer 520, e.g., FR4 laminate, having a top side and a bottom side opposing the top side.
  • core layer 520 e.g., FR4 laminate
  • a second step 502, 503 may comprise: cutting at least one opening 521 in the PCB core layer 520, the at least one opening 521 extending from the top side to the bottom side of the PCB core layer 520. This can be implemented by mechanical drilling, laser cutting, punching, routing, etc., for example.
  • a third step 504 may comprise: attaching a bonding tape 522 to the PCB core layer 520, e.g., by tape lamination, the bonding tape 522 covering the at least one opening 521 of the PCB core layer 520 from the bottom side.
  • a fourth step 505 may comprise: placing at least one electronic chip, e.g., an integrated circuit 140 as shown above with respect to Figures 1 to 4, inside the at least one opening 521 of the PCB core layer 520 and attaching the at least one electronic chip 140 to the bonding tape 522.
  • at least one electronic chip e.g., an integrated circuit 140 as shown above with respect to Figures 1 to 4
  • a fifth step 506 may comprise: applying a first lamination layer 523 on the top side of the PCB core layer 520 to form an embedded component package embedding the at least one electronic chip 140, the embedded component package 550 comprising a top side above the top side of the PCB core layer 520 and a bottom side below the bottom side of the PCB core layer 520, and attaching a first metal foil 524, e.g., a Cu foil attached by lamination, on the top side of the embedded component package 550.
  • a first metal foil 524 e.g., a Cu foil attached by lamination
  • a sixth step 507 may comprise: removing the bonding tape 522 from the bottom side of the embedded component package 550, applying a second lamination layer 525 on the bottom side of the embedded component package 550 and attaching a second metal foil 526, e.g., a Cu foil attached by lamination, on the bottom side of the embedded component package 550.
  • a second metal foil 526 e.g., a Cu foil attached by lamination
  • a seventh step 508 may comprise: cutting at least one microvia 527, e.g., by pvia drilling, into the embedded component package 550 to expose at least one first connection terminal, e.g., at least one first connection terminal 141 as shown in Figures 1 to 4, of the at least one electronic chip 140.
  • An eighth step 509 may comprise: disposing a photoresist layer 527 on the top side and/or on the bottom side of the embedded component package 550, e.g., by lithography, and forming one or more openings in the photoresist layer to form a photoresist pattern 528 on the top side and/or on the bottom side of the embedded component package 550.
  • a ninth step 510 may comprise: metal plating, e.g., by pattern plating, the top side or the bottom side of the embedded component package 550 to provide electrically and thermally connections of the at least one first connection terminal 141 of the at least one electronic chip 140 according to the photoresist pattern 528 on the top side or the bottom side of the embedded component package.
  • structuring at this phase may be done only on one side, either top side or bottom side.
  • Structuring of the second side can be done after laminating two layers together.
  • both sides can be structured at the same time, e.g., stacking three or more layers together or laminating additional build-up layer on both sides of the package afterwards, see for example layup 601 in Figure 6.
  • a tenth step 511 may comprise: removing the photoresist layer 527 and parts of the first metal foil 524 covered by the photoresist layer 527 from the top side of the embedded component package and removing, e.g., by etching, the photoresist layer and parts of the second metal foil covered by the photoresist layer from the bottom side of the embedded component package 550.
  • Figure 6 shows a schematic diagram of an exemplary process flow 600 for producing a semiconductor package 100 according to the disclosure.
  • This process flow 600 corresponds to a fourth embodiment of the semiconductor package as mentioned above.
  • At least two power dies are embedded inside separate PCB cores and laminate these cores together and connect the dies with plated PTHs or slots that are diced half during package separation. Instead of dicing also e.g., routing can be used.
  • a first step in the manufacturing process is the layup 601 , 602 and lamination 603 step where two core layers with embedded dies, e.g., manufactured as described above with respect to Figure 5 (normal CE/ECP embedding process can be used) are laminated together with normal PCB vacuum lamination process.
  • the layup can be with additional build up layers 601 or without build up layers 602.
  • the layup may include at least following layers:
  • Cu foil 621 (not needed if core layer with embedded dies is structured only from one side);
  • Prepreg 622 (not needed if core layer with embedded dies is structured only from one side;
  • Prepreg 626 (not needed if core layer with embedded dies is structures only from one side).
  • the 90 degrees flipped package is illustrated with die metallization 641 , pvia 642 and die outline 643.
  • This process to manufacture the stacked package may be using normal PCB and chip embedding processes.
  • This can be used for several different kinds of packages such as parallel common source or drain package, half bridge package.
  • the die size is the same in half bridge package, the HS and LS die can also have different sizes. It can also be used for single die and other types of multidie packages.
  • the layers with embedded components that are laminated together can be manufactured with various different kinds of chip embedding or package embedding processes. Due to the plated side wall connections the component can be flipped by 90 degrees and soldering is easier, lead tip inspection (LTI) possible and the reliability is improved. Due to the large area plated sidewalls the Cu cross section is increased and allows higher current carrying capability and lower the current density in Cu lines. The metallized side walls can also be used for effective heat extraction. 3D stacking allows to minimize the package size and increase the power density. Flipping of the package allows to reduce the signal length from die to footprint and balancing the connections.
  • Figure 7 shows different side views of a parallel die package 710 according to an embodiment where dies are facing in the same direction.
  • a cross section view of the parallel dies package 710 is shown in the bottom of Figure 7. From left side to right side of Figure 7, the different four layers L1 , L2, L3 and L4 are shown.
  • the first layer L1 illustrates a first metallization 701 of the die and a solder mask SM1, 706 above the first metallization 701.
  • the second layer L2 illustrates a second metallization 702 of the die.
  • the third layer L3 illustrates a third metallization 703 of the die.
  • the fourth layer L4 illustrates a fourth metallization 704 of the die and a solder mask SM2, 705 below that fourth metallization 704.
  • the structure of the parallel die package 710 may correspond to the structures as described above with respect to Figures 1 to 4.
  • Figure 8 shows different side views of a parallel die package 810 according to an embodiment where in one example, dies are facing in different directions. This is only an example, metallization and routing can be done in various different ways.
  • a cross section view of the parallel dies package 810 is shown in the bottom of Figure 8. From left side to right side of Figure 8, the different four layers L1 , L2, L3 and L4 are shown.
  • the first layer L1 illustrates a first metallization 801 of the die and a solder mask SM1, 806 above the first metallization 801.
  • the second layer L2 illustrates a second metallization 802 of the die.
  • the third layer L3 illustrates a third metallization 803 of the die.
  • the fourth layer L4 illustrates a fourth metallization 804 of the die and a solder mask SM2, 805 below that fourth metallization 804.
  • the structure of the parallel die package 810 may correspond to the structures as described above with respect to Figures 1 to 4.
  • Figure 9 shows different side views of a half bridge package 910 according to an embodiment.
  • a cross section view of the half bridge package 910 is shown in the bottom of Figure 9. From left side to right side of Figure 9, the different four layers L1 , L2, L3 and L4 are shown.
  • the first layer L1 illustrates a first metallization 901 of the die and a solder mask SM1, 906 above the first metallization 901.
  • the second layer L2 illustrates a second metallization 902 of the die.
  • the third layer L3 illustrates a third metallization 903 of the die.
  • the fourth layer L4 illustrates a fourth metallization 904 of the die and a solder mask SM2, 905 below that fourth metallization 904.
  • the structure of the parallel die package 810 may correspond to the structures as described above with respect to Figures 1 to 4.
  • Figure 10 shows a cross sectional view of a lateral semiconductor device 1000 according to an embodiment.
  • the lateral semiconductor device 1000 comprises a Source terminal 1001 , a Gate terminal 1003 and a Drain terminal 1002 which are placed on one side of the die.
  • a distance Lgs, 1011 between Source 1001 and Gate 1003 terminal is much small compared to a distance Lgd, 1012 between Gate 1003 and Drain 1002 terminal due to the high voltage at Drain terminal 1002.
  • Such lateral power devices suffer from inherent Electro-Migration (EM) constraints 1010 at drain side.
  • EM Electro-Migration
  • This lateral semiconductor device 1000 corresponds to a third embodiment of the semiconductor package as mentioned above.
  • This third embodiment describes a technique how the yield, reliability (electro-migration) and electrical and thermal performance of the GaN component can be improved. It is understood that the GaN technology is used here as an example but can be extended to any semiconductor device, technology, and concept.
  • Figure 11 shows schematic diagrams of a standard square-sized layout 1102 of a power device and an improved rectangular layout 1103 of a power device according to the disclosure.
  • the main idea of this third embodiment mentioned above is to change the layout configuration of a power semiconductor device as illustrated in Figure 11 , where GaN HEMT is given as an example.
  • the standard layout 1102 of a power device is a square/rectangle shape. The reason for this shape is to generate the maximum die size that fits a given package in order to maximize the current density and cost per die.
  • Embodiment 3 allows for applying redundancy in high stringent applications such as space, automotive, etc. Besides, unlike standard device where a defect causes the destruction of the full product, in this case since several dies are in parallel, if one is defective, the rest of the dies are still functional.
  • Embodiment 3 The following advantages can be provided by Embodiment 3:
  • terminal connections can be balanced and the signal length is symmetrical;
  • Figure 12 shows a side view 1201, a cross section 1202 and a footprint 1203 of a semiconductor package with paralleled dies according to an embodiment.
  • This semiconductor device with paralleled dies corresponds to a second embodiment of the semiconductor package as mentioned above.
  • At least one power die 1210 is embedded in PCB layer 1220 and stack two or more layers with embedded dies together.
  • These power dies may be GaN power dies, for example.
  • connections between the embedded dies are done with plated slots 1220 or PTHs that are diced half during package separation. If needed additional through holes or hybrid bonding can be used to improve the connection between paralleled source and drain pads.
  • PCB layers with power dies additional PCB layers that may include Cu structures or embedded Cu blocks can be added to improve the thermal performance. After separation the module is flipped by 90° and mounted on the PCB so that the dies are vertically inside the package.
  • additional routing or other process can be used to remove the PCB areas between the routed Cu slots.
  • Different kinds of processes are existing in PCB industry for this.
  • the benefit of this technique is that all connections between the source, drain and gate are symmetrical and well balanced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

L'invention concerne un boîtier de semi-conducteur (100) comprenant : un circuit intégré (140) comprenant au moins une première borne de connexion (141) et au moins une seconde borne de connexion (143) ; un agent d'encapsulation (150) encapsulant au moins une partie du ou des circuits intégrés (140) ; une première couche métallique (110) ; et une seconde couche métallique (120). La première couche métallique (110) est placée sur une partie d'une première paroi latérale (151) de l'agent d'encapsulation (150). La première couche métallique (110) forme un premier connecteur (181) pour connecter électriquement la ou les premières bornes de connexion (141) du circuit intégré (140). La seconde couche métallique (120) est placée sur une autre partie de la (même) première paroi latérale (151) de l'agent d'encapsulation (150). La seconde couche métallique (120) forme un second connecteur (182) pour connecter électriquement la ou les secondes bornes de connexion (143) du circuit intégré (140). Le premier connecteur (181) et le second connecteur (182) du boîtier de semi-conducteur (100) sont conçus pour être fixés à des traces métalliques respectives (191, 192) d'une carte de circuit imprimé, PCB (190).
PCT/EP2022/087677 2022-10-23 2022-12-23 Boîtier semi-conducteur WO2024088555A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/EP2022/079494 WO2024088494A1 (fr) 2022-10-23 2022-10-23 Boîtier de semi-conducteur
EPPCT/EP2022/079494 2022-10-23

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