WO2024087846A1

WO2024087846A1 - Differential power amplification circuit and radio frequency chip

Info

Publication number: WO2024087846A1
Application number: PCT/CN2023/114970
Authority: WO
Inventors: 许靓; 郭嘉帅
Original assignee: 深圳飞骧科技股份有限公司
Priority date: 2022-10-26
Filing date: 2023-08-25
Publication date: 2024-05-02
Also published as: CN115580245A

Abstract

A differential power amplification circuit (100) and a radio frequency chip. The differential power amplification circuit (100) comprises: a signal input end (1), an input matching circuit (2), a driving-stage power unit (3), a power difference unit (4), a last-stage power unit having a first last-stage power unit (5) and a second last-stage power unit (6) which are connected in parallel, a power synthesis unit (8), an output matching circuit (7), and a signal output end (9), which are connected in sequence. The differential power amplification circuit (100) further comprises a first capacitor (C01) and a second capacitor (C02), which form a cross-coupling capacitor group, wherein a first end of the first capacitor (C01) is connected to an input end of the first last-stage power unit (5), and a second end of the first capacitor (C01) is connected to an output end of the second last-stage power unit (6); and a first end of the second capacitor (C02) is connected to an input end of the second last-stage power unit (6), and a second end of the second capacitor (C02) is connected to an output end of the first last-stage power unit (5). The differential power amplification circuit (100) can improve both the gain of the radio frequency chip and the capability of suppressing second-order and third-order harmonics of a dominant frequency.

Description

Differential power amplifier circuit and RF chip

Technical Field

The present invention relates to the field of wireless communication technology, and in particular to a differential power amplifier circuit and a radio frequency chip.

Background technique

As humans enter the information age, wireless communication technology has developed rapidly. From mobile phones, wireless LANs, Bluetooth, etc., it has become an indispensable part of social life and development. The progress of wireless communication technology is inseparable from the development of differential power amplifier circuits. At present, in wireless transceiver systems, differential power amplifier circuits are one of the important components.

The existing differential power amplifier circuits in the N77 and N79 frequency bands in 5G-NR are higher frequency bands than Sub-3G. Therefore, they attenuate faster during propagation, the path loss is relatively large, and the coverage of a single carrier is limited. In order to improve user experience and reduce the cost of operators to build base stations, 3GPP has defined a new power standard Power Class 2 (PC2), which means that the output power of wireless terminal equipment is further increased by 3dB on the basis of the original Power Class 3. When the output power of wireless terminal equipment is increased to PC2, it can compensate for the greater propagation loss at higher TDD frequencies and reduce the cost of operators to build expensive base stations.

However, the overall gain of the above differential power amplifier circuit is relatively low. In addition, by introducing a higher-order circuit amplification structure, the overall power consumption of the PA will further increase, and the efficiency will be significantly reduced.

Summary of the invention

In view of the above deficiencies in the prior art, the present invention proposes a differential power amplifier circuit and a radio frequency chip that have the ability to simultaneously improve the gain of the radio frequency chip and suppress harmonics of the main frequency, so as to solve the above technical problems.

In order to solve the above technical problems, the present invention adopts the following technical solutions:

In a first aspect, an embodiment of the present invention provides a differential power amplifier circuit, comprising a signal input terminal, an input matching circuit, a driving stage power unit, a power differential unit, a final stage power unit having a first final stage power unit and a second final stage power unit connected in parallel, a power synthesis unit, an output matching circuit, and a signal output terminal, connected in sequence.

The differential power amplifier circuit further includes a first capacitor and a second capacitor forming a cross-coupled capacitor group;

A first end of the first capacitor is connected to an input end of the first final-stage power unit, and a second end of the first capacitor is connected to an output end of the second final-stage power unit;

A first end of the second capacitor is connected to an input end of the second final-stage power unit, and a second end of the second capacitor is connected to an output end of the first final-stage power unit.

Preferably, the first final stage power unit includes a first transistor, the base of the first transistor serving as the input end of the first final stage power unit is respectively connected to the first end of the first capacitor and the first output end of the power differential unit, the collector of the first transistor serving as the output end of the first final stage power unit is respectively connected to the first end of the second capacitor and the first input end of the power synthesis unit, and the emitter of the first transistor is grounded.

Preferably, the second final stage power unit includes a second transistor, the base of the second transistor serving as the input end of the second final stage power unit is respectively connected to the first end of the second capacitor and the second output end of the power differential unit, the collector of the second transistor serving as the output end of the second final stage power unit is respectively connected to the second end of the first capacitor and the second input end of the power synthesis unit, and the emitter of the second transistor is grounded.

Preferably, the power synthesis unit comprises a combining transformer balun, a fifth capacitor, a sixth capacitor and a seventh capacitor;

The first end of the primary coil of the combining transformer balun is connected to the output end of the first final-stage power unit as the first input end of the power combining unit, and the second end of the primary coil of the combining transformer balun is connected to the output end of the second final-stage power unit as the second input end of the power combining unit;

A first end of the fifth capacitor is connected to a middle tap of the primary coil of the combining transformer balun, and a second end of the fifth capacitor is grounded;

The first end of the sixth capacitor is respectively connected to the first end of the fifth capacitor and the first power supply voltage, and the second end of the sixth capacitor is grounded;

A first end of the secondary coil of the combining transformer balun is connected to the signal output end as the output end of the power combining unit, and a second end of the secondary coil of the combining transformer balun is connected in series with the seventh capacitor and then grounded.

Preferably, the differential power amplifier circuit also includes a first tuning circuit and a second tuning circuit respectively connected to the first end of the primary coil of the combining transformer balun and the second end of the primary coil of the combining transformer balun; the first tuning circuit and the second tuning circuit are both used to suppress the second-order harmonic of the main frequency of the differential power amplifier circuit.

Preferably, the first tuning circuit comprises a ninth capacitor and a first inductor; the first end of the ninth capacitor is connected to the first end of the primary coil of the combining transformer balun, the second end of the ninth capacitor is connected to the first end of the first inductor, and the second end of the first inductor is grounded;

The second tuning circuit includes a tenth capacitor and a second inductor; a first end of the tenth capacitor is connected to the second end of the primary coil of the combining transformer balun, and a second end of the second inductor is grounded.

Preferably, the output matching circuit includes an eleventh capacitor and a third inductor, the first end of the eleventh capacitor is connected to the first end of the secondary coil of the combining transformer balun, the second end of the eleventh capacitor is connected to the first end of the third inductor, and the second end of the third inductor is grounded.

Preferably, the power differential unit includes a differential transformer balun, a third resistor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor and a fifteenth capacitor;

The first end and the second end of the primary coil of the differential transformer balun are respectively connected to the two ends of the third resistor;

A first end of the twelfth capacitor is connected to a first end of the primary coil of the differential transformer balun, and a second end of the twelfth capacitor is grounded;

The second end of the primary coil of the differential transformer balun is respectively connected to the first end of the thirteenth capacitor, the first end of the fifteenth capacitor and the second power supply voltage, and the second end of the thirteenth capacitor and the second end of the fifteenth capacitor are respectively grounded;

The first end of the secondary coil of the differential transformer balun and the second end of the secondary coil of the differential transformer balun serve as the first output end and the second output end of the power differential unit, respectively, and are connected to the first final-stage power unit and the second final-stage power unit, respectively;

A first end of the fourteenth capacitor is connected to a middle tap of the secondary coil of the differential transformer balun, and a second end of the fourteenth capacitor is grounded.

Preferably, the driving stage power unit includes a sixteenth capacitor, a third triode, a fourth resistor and a first bias circuit;

A first end of the sixteenth capacitor is connected to the input matching circuit, and a second end of the sixteenth capacitor is connected to the base of the third transistor;

The collector of the third triode is connected to the input of the power differential unit, and the emitter of the third triode is grounded;

A first end of the fourth resistor is connected to the base of the third transistor, and a second end of the fourth resistor is connected to the first bias circuit.

In a second aspect, an embodiment of the present invention provides a radio frequency chip, comprising the above-mentioned differential power amplifier circuit.

Compared with the related art, in the embodiment of the present invention, by sequentially connecting the signal input end, the input matching circuit, the driving stage power unit, the power differential unit, the final stage power unit having the first final stage power unit and the second final stage power unit connected in parallel, the power synthesis unit, the output matching circuit and the signal output end, the differential power amplifier circuit also includes a first capacitor and a second capacitor forming a cross-coupled capacitor group; the first end of the first capacitor is connected to the input end of the first final stage power unit, and the second end of the first capacitor is connected to the output end of the second final stage power unit; the first end of the second capacitor is connected to the input end of the second final stage power unit, and the second end of the second capacitor is connected to the output end of the first final stage power unit; the influence of Cbc on the final stage power unit can be reduced, through The input of the power synthesis unit is respectively connected to the output end of the first final stage power unit and the output end of the second final stage power unit, so as to realize power synthesis of the two differential signals and then output them, which can have the ability to simultaneously improve the gain of the RF chip and suppress the harmonics of the main frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:

FIG1 is a module diagram of a differential power amplifier circuit in an embodiment of the present invention;

FIG2 is a circuit diagram of a differential power amplifier circuit according to an embodiment of the present invention;

FIG3 is a circuit diagram of a driving stage power unit in an embodiment of the present invention;

FIG. 4 is a circuit diagram of a first final-stage power unit and a second final-stage power unit in an embodiment of the present invention.

Among them, 100, differential power amplifier circuit, 1, signal input terminal, 2, input matching circuit, 3, driving stage power unit, 31, fourth resistor, 32, sixteenth capacitor, 33, third transistor, 34, first bias circuit, 4, power differential unit, 5, first final stage power unit, 51, first resistor, 52, third capacitor, 53, first transistor, 6, second final stage power unit, 61, second resistor, 62, fourth capacitor, 63, second transistor, 7, output matching circuit, 8, power synthesis unit, 9, signal output terminal. 10, first tuning circuit, 11, second tuning circuit.

Detailed ways

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of this application; the terms used in the specification of the application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second" and "third" in the specification and claims of this application or the above-mentioned drawings are intended to cover non-exclusive inclusions. Etc. is used to distinguish different objects, not to describe a specific order.

Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

Embodiment 1

Please refer to Figures 1-4, a differential power amplifier circuit 100 provided in an embodiment of the present invention includes a signal input terminal 1 (RFin), an input matching circuit 2, a driving stage power unit 3, a power differential unit 4, a first final stage power unit 5, a second final stage power unit 6, an output matching circuit 7, a power synthesis unit 8 and a signal output terminal 9 (RFout) connected in sequence.

Signal input terminal 1 is used to connect single-ended input signals.

The first end of the input matching circuit 2 is connected to the signal input end 1 and is used to match and output the input signal.

The first end of the driving stage power unit 3 is connected to the second end of the input matching circuit 2 for driving the input signal to output.

The first end of the power differential unit 4 is connected to the second end of the driving stage power unit 3, and is used to convert the received input signal into two differential signals.

The differential power amplifier circuit 100 further includes a first capacitor C01 and a second capacitor C02 forming a cross-coupled capacitor group.

A first end of the first capacitor C01 is connected to an input end of the first final-stage power unit 5 , and a second end of the first capacitor C01 is connected to an output end of the second final-stage power unit 6 .

A first end of the second capacitor C02 is connected to an input end of the second final-stage power unit 6 , and a second end of the second capacitor C02 is connected to an output end of the first final-stage power unit 5 .

Specifically, the input signal inputted from the signal input terminal 1 is received by the input matching circuit 2, matched and outputted to the driving stage power unit 3, power amplified by the driving stage power unit 3, connected to the second end of the driving stage power unit 3 through the first end of the power differential unit 4, used to convert the received amplified input signal into two differential signals, which are respectively outputted to the first final stage power unit 5 and the second final stage power unit 6, and feedback is performed through the first final stage power unit 5 and the second final stage power unit 6 to increase the operating frequency. The first end of the first capacitor C01 is connected to the input end of the first final stage power unit 5, and the second end of the first capacitor C01 is connected to the output end of the second final stage power unit 6. The first end of the second capacitor C02 is connected to the input end of the second final stage power unit 6, and the second end of the second capacitor C02 is connected to the output end of the first final stage power unit 5. In this way, a cross-coupled first capacitor C01 and a second capacitor C02 are introduced at the output end of the differential pair, and the RF signal amplified and output by the differential pair is compensated to another common emitter power amplifier, that is, the cross-coupled first capacitor C01 and the second capacitor C02 are equivalent to the base nodes corresponding to the first final stage power unit 5 and the second final stage power unit 6 respectively, which introduces the effect of negative capacitance to neutralize the influence of Cbc.

By connecting the first end of the output matching circuit 7 to the output end of the first final power unit 5, and grounding the second end of the output matching circuit 7, the input of the power synthesis unit 8 is respectively connected to the output end of the first final power unit 5 and the output end of the second final power unit 6, so as to realize power synthesis of the two differential signals and output them to the signal output end 9; the harmonics of the main frequency of the circuit can be effectively suppressed.

In this embodiment, the first final power unit 5 includes a first transistor 53, the base of the first transistor 53 is connected to the first end of the first capacitor C01 and the first output end of the power differential unit 4 as the input end of the first final power unit 5, and the collector of the first transistor 53 is connected to the first end of the second capacitor C02 and the first input end of the power synthesis unit 8 as the output end of the first final power unit 5. The emitter of the first transistor 53 is grounded.

The first final power unit 5 also includes a third capacitor 52 and a first resistor 51. The first end of the third capacitor 52 is connected to the first output end, the second end of the third capacitor 52 is connected to the base of the first transistor 53, the collector of the first transistor 53 is respectively connected to the first end of the second capacitor C02 and the input of the power synthesis unit 8, the first resistor 51 is connected between the third capacitor 52 and the first transistor 53 and is connected in series with the first end of the first capacitor C01, and the emitter of the first transistor 53 is grounded. After the differential signal is isolated by the third capacitor 52, the first transistor 53 amplifies the differential signal and transmits it to the power synthesis unit 8 for synthesis. The first resistor 51 is used to stabilize the circuit and connect an external bias circuit.

In this embodiment, the second final stage power unit 6 includes a second transistor 62, the base of the second transistor 62 is connected to the first end of the second capacitor C02 and the second output end of the power differential unit 4 as the input end of the second final stage power unit 6, the collector of the second transistor 62 is connected to the second end of the first capacitor C01 and the second input end of the power synthesis unit 8 as the output end of the second final stage power unit 6, and the emitter of the second transistor 63 is grounded.

The second final power unit 6 also includes a fourth capacitor 62 and a second resistor 61, wherein the first end of the fourth capacitor 62 is connected to the second output end, the second end of the fourth capacitor 62 is connected to the base of the second transistor 63, the collector of the second transistor 63 is respectively connected to the second end of the first capacitor C01 and the input of the power synthesis unit 8, the second resistor 61 is connected between the fourth capacitor 62 and the second transistor 63 and is connected in series with the first end of the second capacitor C02, the second end of the second capacitor C02 is connected to the collector of the first transistor 53, and the emitter of the second transistor 63 is grounded. After the differential signal is isolated by the fourth capacitor 62, the differential signal is amplified by the second transistor 63 and transmitted to the power synthesis unit 8 for synthesis.

Specifically, by connecting the collector of the second transistor 63 to the second end of the first capacitor C01 and the input of the power synthesis unit 8 respectively, the first end of the first capacitor C01 is connected between the third capacitor 52 and the first transistor 53, and the first end of the second capacitor C02 is connected to the input of the power synthesis unit 8. One end is connected to the collector of the first transistor 53, and the second end of the second capacitor C02 is connected between the fourth capacitor 62 and the second transistor 63, so that the base of the first transistor 53 and the second transistor 63 introduces the function of negative capacitance to neutralize the influence of Cbc.

In this embodiment, the power combining unit 8 includes a combining transformer balun TF2, a fifth capacitor C05, a sixth capacitor C06 and a seventh capacitor C07.

The first end of the primary coil of the combining transformer balun TF2 is connected to the output end of the first final stage power unit 5 as the first input end of the power synthesis unit 8, and the second end of the primary coil of the combining transformer balun TF2 is connected to the output end of the second final stage power unit 6 as the second input end of the power synthesis unit 8.

A first end of the fifth capacitor C05 is connected to a middle tap of the primary coil of the combining transformer balun, and a second end of the fifth capacitor C05 is grounded.

The first end of the sixth capacitor C06 is connected to the first end of the fifth capacitor C05 and the first power supply voltage VCC1 respectively, the second end of the sixth capacitor C06 is grounded, the first end of the secondary coil of the combining transformer balun TF2 is connected to the signal output end 9 as the output end of the power synthesis unit 8, and the second end of the secondary coil of the combining transformer balun TF2 is connected to the ground after being connected in series with the seventh capacitor C07. By connecting the fifth capacitor C05 and the sixth capacitor C06 to the first primary coil of the combining transformer balun TF2, and connecting the seventh capacitor C07 to the balanced port of the first secondary coil, the combining transformer balun TF2 is used to suppress harmonics.

In this embodiment, the differential power amplifier circuit 100 also includes a first tuning circuit 10 and a second tuning circuit 11 respectively connected to the first end of the primary coil of the combining transformer balun TF2 and the second end of the primary coil of the combining transformer balun TF2; the first tuning circuit 10 and the second tuning circuit 11 are both used to suppress the second-order harmonic of the main frequency of the differential power amplifier circuit 100.

In this embodiment, the first tuning circuit 10 includes a ninth capacitor C09 and a first inductor L01 connected in series with a first end of the ninth capacitor C09, the first end of the ninth capacitor C09 is connected to a first end of the primary coil of the combining transformer balun TF2, the second end of the ninth capacitor C09 is connected to a first end of the first inductor L01, and the second end of the first inductor L01 is connected to a first end of the primary coil of the combining transformer balun TF2. Ground.

The second tuning circuit 11 includes a tenth capacitor C10 and a second inductor L02 connected in series with a first end of the tenth capacitor C10, the first end of the tenth capacitor C10 is connected to the second end of the primary coil of the balun of the combining transformer, and the second end of the second inductor L02 is grounded. The first inductor L01 and the second inductor L02 are connected in series with the ninth capacitor C09 and the tenth capacitor C10, respectively, and the second-order harmonics of the main frequency are suppressed by the series resonant circuit composed of the ninth capacitor C09 and the first inductor L01, and the second-order harmonics of the main frequency are also suppressed by the series resonant circuit composed of the tenth capacitor C10 and the second inductor L02.

In this embodiment, the output matching circuit 7 includes an eleventh capacitor C11 and a third inductor L03 connected in series with a first end of the eleventh capacitor C11, the first end of the eleventh capacitor C11 is connected to a first end of the secondary coil of the combiner transformer balun TF2, the second end of the eleventh capacitor C11 is connected to a first end of the third inductor L03, and one end of the third inductor L03 is grounded. By connecting the eleventh capacitor C11 and the third inductor L03 connected in series to the first output end of the first secondary coil of the combiner transformer balun TF2, the third-order harmonic of the main frequency can be suppressed.

In this embodiment, the power differential unit 4 includes a differential transformer Balun TF1, a third resistor R03, a twelfth capacitor C12, a thirteenth capacitor C13, a fourteenth capacitor C14 and a fifteenth capacitor C15, the first end and the second end of the primary coil of the differential transformer Balun TF1 are respectively connected to the two ends of the third resistor R03, the first end of the twelfth capacitor C12 is connected to the first end of the primary coil of the differential transformer Balun TF1, and the second end of the twelfth capacitor C12 is grounded. The first end of the primary coil of the differential transformer Balun TF1 is respectively connected to the first end of the thirteenth capacitor C13, the first end of the fifteenth capacitor C15 and the second power supply voltage VCC2, the second end of the thirteenth capacitor C13 and the second end of the fifteenth capacitor C15 are respectively grounded, the first end of the secondary coil of the differential transformer Balun TF1 and the second end of the secondary coil of the differential transformer Balun TF1 serve as the first output end and the second output end of the power differential unit 4, respectively, and are respectively connected to the first final power unit 5 and the second final power unit 6; the first end of the fourteenth capacitor C14 is connected to the middle tap selected by the secondary of the differential transformer Balun TF1, The second end of the fourteenth capacitor C14 is grounded. By connecting the third resistor R03 at both ends of the primary coil of the differential transformer balun TF1, the isolation of the ports at both ends of the primary coil of the differential transformer balun TF1 can be improved, thereby facilitating the suppression of the third-order harmonics of the circuit main frequency.

In this embodiment, the driving stage power unit 3 includes a sixteenth capacitor 32, a third transistor 33, a fourth resistor 31 and a first bias circuit 34, the first end of the sixteenth capacitor 32 is connected to the input matching circuit 2, the second end of the fourth capacitor 62 is connected to the base of the third transistor 33, the collector of the third transistor 33 is connected to the input of the power differential unit 4, the emitter of the third transistor 33 is grounded, the first end of the fourth resistor 31 is connected to the base of the third transistor 33, and the second end of the fourth resistor 31 is connected to the first bias circuit 34.

Embodiment 2

An embodiment of the present invention provides a radio frequency chip, including the differential power amplifier circuit 100 of the first embodiment.

It should be noted that the various embodiments described above with reference to the accompanying drawings are only used to illustrate the present invention rather than to limit the scope of the present invention. Those skilled in the art should understand that modifications or equivalent substitutions made to the present invention without departing from the spirit and scope of the present invention should be included within the scope of the present invention. In addition, unless otherwise indicated by the context, words appearing in the singular include the plural form, and vice versa. In addition, unless otherwise specified, all or part of any embodiment may be used in combination with all or part of any other embodiment.

Claims

A differential power amplifier circuit comprises a signal input terminal, an input matching circuit, a driving stage power unit, a power differential unit, a final stage power unit having a first final stage power unit and a second final stage power unit connected in parallel, a power synthesis unit, an output matching circuit and a signal output terminal, wherein:

The differential power amplifier circuit further includes a first capacitor and a second capacitor forming a cross-coupled capacitor group;

A first end of the first capacitor is connected to an input end of the first final-stage power unit, and a second end of the first capacitor is connected to an output end of the second final-stage power unit;

A first end of the second capacitor is connected to an input end of the second final-stage power unit, and a second end of the second capacitor is connected to an output end of the first final-stage power unit.
The differential power amplifier circuit according to claim 1 is characterized in that the first final-stage power unit includes a first transistor, the base of the first transistor is connected to the first end of the first capacitor and the first output end of the power differential unit as the input end of the first final-stage power unit, the collector of the first transistor is connected to the first end of the second capacitor and the first input end of the power synthesis unit as the output end of the first final-stage power unit, and the emitter of the first transistor is grounded.
The differential power amplifier circuit according to claim 2 is characterized in that the second final-stage power unit includes a second transistor, the base of the second transistor is connected to the first end of the second capacitor and the second output end of the power differential unit as the input end of the second final-stage power unit, the collector of the second transistor is connected to the second end of the first capacitor and the second input end of the power synthesis unit as the output end of the second final-stage power unit, and the emitter of the second transistor is grounded.
The differential power amplifier circuit according to claim 3, characterized in that the power synthesis unit comprises a combining transformer balun, a fifth capacitor, a sixth capacitor and a seventh capacitor;

The first end of the primary coil of the combining transformer balun is connected to the output end of the first final power unit as the first input end of the power combining unit, and the second end of the primary coil of the combining transformer balun is connected to the output end of the first final power unit as the second input end of the power combining unit. to the output end of the second final-stage power unit;

A first end of the fifth capacitor is connected to a middle tap of the primary coil of the combining transformer balun, and a second end of the fifth capacitor is grounded;

The first end of the sixth capacitor is respectively connected to the first end of the fifth capacitor and the first power supply voltage, and the second end of the sixth capacitor is grounded;

A first end of the secondary coil of the combining transformer balun is connected to the signal output end as the output end of the power combining unit, and a second end of the secondary coil of the combining transformer balun is connected in series with the seventh capacitor and then grounded.
The differential power amplifier circuit according to claim 4 is characterized in that the differential power amplifier circuit also includes a first tuning circuit and a second tuning circuit respectively connected to the first end of the primary coil of the combining transformer balun and the second end of the primary coil of the combining transformer balun; the first tuning circuit and the second tuning circuit are both used to suppress the second-order harmonic of the main frequency of the differential power amplifier circuit.
The differential power amplifier circuit according to claim 5 is characterized in that the first tuning circuit comprises a ninth capacitor and a first inductor; a first end of the ninth capacitor is connected to a first end of the primary coil of the combining transformer balun, a second end of the ninth capacitor is connected to a first end of the first inductor, and a second end of the first inductor is grounded;

The second tuning circuit includes a tenth capacitor and a second inductor; a first end of the tenth capacitor is connected to the second end of the primary coil of the combining transformer balun, and a second end of the second inductor is grounded.
The differential power amplifier circuit according to claim 4 is characterized in that the output matching circuit includes an eleventh capacitor and a third inductor, the first end of the eleventh capacitor is connected to the first end of the secondary coil of the combining transformer balun, the second end of the eleventh capacitor is connected to the first end of the third inductor, and the second end of the third inductor is grounded.
The differential power amplifier circuit according to claim 2, characterized in that the power differential unit comprises a differential transformer balun, a third resistor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor and a fifteenth capacitor;

The first end and the second end of the primary coil of the differential transformer balun are respectively connected to the first The two ends of the three resistors are connected;

A first end of the twelfth capacitor is connected to a first end of the primary coil of the differential transformer balun, and a second end of the twelfth capacitor is grounded;

The second end of the primary coil of the differential transformer balun is respectively connected to the first end of the thirteenth capacitor, the first end of the fifteenth capacitor and the second power supply voltage, and the second end of the thirteenth capacitor and the second end of the fifteenth capacitor are respectively grounded;

The first end of the secondary coil of the differential transformer balun and the second end of the secondary coil of the differential transformer balun serve as the first output end and the second output end of the power differential unit, respectively, and are connected to the first final-stage power unit and the second final-stage power unit, respectively;

A first end of the fourteenth capacitor is connected to a middle tap of the secondary coil of the differential transformer balun, and a second end of the fourteenth capacitor is grounded.
The differential power amplifier circuit according to claim 1, characterized in that the driving stage power unit comprises a sixteenth capacitor, a third transistor, a fourth resistor and a first bias circuit;

A first end of the sixteenth capacitor is connected to the input matching circuit, and a second end of the sixteenth capacitor is connected to the base of the third transistor;

The collector of the third triode is connected to the input of the power differential unit, and the emitter of the third triode is grounded;

A first end of the fourth resistor is connected to the base of the third transistor, and a second end of the fourth resistor is connected to the first bias circuit.
A radio frequency chip, characterized by comprising the differential power amplifier circuit according to any one of claims 1 to 9.