WO2024087210A1 - 显示基板、其制作方法、显示面板及显示装置 - Google Patents

显示基板、其制作方法、显示面板及显示装置 Download PDF

Info

Publication number
WO2024087210A1
WO2024087210A1 PCT/CN2022/128391 CN2022128391W WO2024087210A1 WO 2024087210 A1 WO2024087210 A1 WO 2024087210A1 CN 2022128391 W CN2022128391 W CN 2022128391W WO 2024087210 A1 WO2024087210 A1 WO 2024087210A1
Authority
WO
WIPO (PCT)
Prior art keywords
platform
base substrate
layer
organic layer
substrate
Prior art date
Application number
PCT/CN2022/128391
Other languages
English (en)
French (fr)
Inventor
方业周
田亮
武新国
王凤国
王志翔
蔚国将
黄波
郭智昂
刘耀祖
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/128391 priority Critical patent/WO2024087210A1/zh
Priority to CN202280003876.4A priority patent/CN118265946A/zh
Publication of WO2024087210A1 publication Critical patent/WO2024087210A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, a display panel and a display device.
  • Liquid Crystal Display has the advantages of light weight, low power consumption, high image quality, low radiation and easy portability. It has gradually replaced traditional cathode ray tube display (CRT) and is widely used in modern information equipment, such as augmented reality (AR)/virtual reality (VR) display devices, laptops, televisions, mobile phones and digital products.
  • CTR cathode ray tube display
  • AR augmented reality
  • VR virtual reality
  • the display substrate, the manufacturing method thereof, the display panel and the display device provided by the embodiments of the present disclosure are specifically described as follows:
  • an embodiment of the present disclosure provides a display substrate, comprising:
  • An organic layer is located on one side of the base substrate, the organic layer includes a flat layer and a plurality of supporting structures, wherein the flat layer includes a plurality of vias, the supporting structures are located on a side of the flat layer away from the base substrate and are integrally arranged with the flat layer, and the orthographic projection of the supporting structures on the base substrate does not overlap with the orthographic projection of the vias on the base substrate.
  • the organic layer further includes a plurality of platform structures located on a side of the planar layer away from the base substrate and integrally arranged with the planar layer, and the vias extend to penetrate the platform structures.
  • a minimum distance between an outer surface of the platform structure on a side away from the via hole and the via hole is greater than or equal to 5 ⁇ m.
  • the display substrate provided in the embodiments of the present disclosure further includes a plurality of transistors located between the organic layer and the base substrate, and a plurality of pixel electrodes located on a side of the organic layer away from the base substrate;
  • the plurality of via holes include a plurality of first via holes, wherein the first via holes connect the first electrode of the transistor and the pixel electrode;
  • the plurality of platform structures include a plurality of first platform structures, and the first platform structures are penetrated by the first via holes.
  • part of the first platform structure is integrally arranged with each of the supporting structures.
  • the minimum distance between the first platform structure and the supporting structure is less than 2 ⁇ m.
  • the aperture of the via hole gradually increases in the direction in which the organic layer moves away from the base substrate, and the minimum distance between the top port of the first via hole and the supporting structure is greater than or equal to 2 ⁇ m.
  • the display substrate provided in the embodiments of the present disclosure further includes a plurality of first connection portions, wherein the first connection portions connect the support structure and the first platform structure.
  • the display substrate provided in the embodiments of the present disclosure further includes a common electrode located between the layer where the plurality of pixel electrodes are located and the organic layer, and a plurality of switching electrodes in the same layer and with the same material as the first electrode of the transistor;
  • the plurality of via holes further include a plurality of second via holes, wherein the second via holes connect the common electrode and the switching electrode;
  • the plurality of platform structures include a plurality of second platform structures, and the second platform structures are penetrated by the second via holes.
  • each of the second platform structures is integrally arranged with part of the first platform structure, and the second platform structure and the supporting structure are respectively integrally arranged with different first platform structures.
  • the above-mentioned display substrate provided in the embodiments of the present disclosure further includes a plurality of second connecting portions, wherein the second connecting portions connect the second platform structure and the first platform structure.
  • the thickness of the platform structure in the above-mentioned display substrate provided by the embodiments of the present disclosure, is substantially the same as the thickness of the support structure.
  • the surface of the organic layer away from the base substrate is uneven.
  • the display substrate provided in the embodiments of the present disclosure further includes a plurality of gate lines located between the organic layer and the base substrate and extending along a first direction and arranged along a second direction, wherein the first direction is arranged to intersect with the second direction;
  • the size of the support structure gradually decreases, and the support structure includes a top end away from the side of the base substrate, and the width of the top end in the first direction is greater than or equal to 6 ⁇ m and less than or equal to 12 ⁇ m; the length of the support structure in the second direction is greater than or equal to 25 ⁇ m and less than or equal to 50 ⁇ m.
  • the slope angle of the support structure is greater than or equal to 30° and less than or equal to 60°.
  • the thickness of the planar layer in the direction where the organic layer is away from the base substrate is greater than 2 ⁇ m.
  • the thickness of the platform structure in the above-mentioned display substrate provided by the embodiments of the present disclosure, is greater than or equal to 0.5 ⁇ m and less than or equal to 1.2 ⁇ m.
  • an embodiment of the present disclosure provides a method for manufacturing the above-mentioned display substrate, comprising:
  • An organic layer is formed on the base substrate by using a semi-transmittance mask plate, wherein the organic layer includes a flat layer and a plurality of supporting structures, wherein the flat layer includes a plurality of vias, the supporting structures are located on a side of the flat layer away from the base substrate and are integrally arranged with the flat layer, and the orthographic projection of the supporting structures on the base substrate does not overlap with the orthographic projection of the vias on the base substrate.
  • an organic layer is formed on the base substrate using a semi-transmittance mask, specifically including:
  • the opaque area of the semi-transmittance mask is used to form a plurality of supporting structures, a first flat portion blocked by the supporting structure, a plurality of platform structures, and a second flat portion blocked by the platform structure; the semi-transmittance area of the semi-transmittance mask is used to form a third flat portion that is not blocked by the supporting structure and the platform structure; the fully transparent area of the semi-transmittance mask is used to form a plurality of via holes that penetrate the platform structure and the second flat portion, and the flat layer of the organic layer includes the first flat portion, the second flat portion, and the third flat portion.
  • the transmittance of the semi-transparent area of the semi-transparent mask is greater than or equal to 15% and less than or equal to 35%.
  • an embodiment of the present disclosure further provides a display panel, comprising a display substrate and a counter substrate arranged opposite to each other, and a liquid crystal layer located between the display substrate and the counter substrate, wherein the display substrate is the above-mentioned display substrate provided in the embodiment of the present disclosure.
  • the counter substrate includes a black matrix
  • the orthographic projection of the platform on the base substrate is located within the orthographic projection of the black matrix on the base substrate.
  • an embodiment of the present disclosure provides a display device, including a backlight module and a display panel located on the light-emitting side of the backlight module, wherein the display panel is the above-mentioned display panel provided in the embodiment of the present disclosure.
  • FIG1 is a schematic diagram of a structure of a display panel in the related art
  • FIG2 is a schematic structural diagram of a display substrate provided in an embodiment of the present disclosure.
  • Fig. 3 is a cross-sectional view along line I-I' in Fig. 2;
  • Fig. 4 is a cross-sectional view along line II-II' in Fig. 2;
  • FIG5 is a schematic structural diagram of the light shielding layer in FIG2 ;
  • FIG6 is a schematic diagram of the structure of the active layer in FIG2;
  • FIG7 is a schematic diagram of the structure of the layer where the gate lines are located in FIG2;
  • FIG8 is a schematic diagram of the structure of the interlayer dielectric layer and the gate insulating layer in FIG2;
  • FIG9 is a schematic diagram of the structure of the layer where the data line is located in FIG2;
  • FIG10 is a schematic diagram of the structure of the flat layer in FIG2 ;
  • FIG11 is a schematic diagram of the structure of the common electrode in FIG2 ;
  • FIG12 is a schematic diagram of the structure of the inorganic insulating layer in FIG2 ;
  • FIG13 is a schematic structural diagram of the pixel electrode in FIG2 ;
  • FIG14 is a picture of diamond-shaped bosses and vias formed in an organic layer using a semi-transmittance mask
  • FIG15 is another picture of diamond-shaped bosses and vias formed in an organic layer using a semi-transmittance mask
  • FIG16 is a schematic diagram of a partial structure of an organic layer provided in an embodiment of the present disclosure.
  • FIG17 is a schematic diagram of another partial structure of an organic layer provided in an embodiment of the present disclosure.
  • FIG18 is a schematic diagram of a connection between a support structure and a first platform structure provided in an embodiment of the present disclosure
  • FIG19 is a schematic diagram of another connection between the support structure and the first platform structure provided by an embodiment of the present disclosure.
  • FIG20 is a schematic diagram of another connection between the support structure and the first platform structure provided by an embodiment of the present disclosure.
  • FIG21 is a schematic diagram of a connection between a first platform structure and a second platform structure provided in an embodiment of the present disclosure
  • FIG22 is another schematic diagram of a connection between a first platform structure and a second platform structure provided by an embodiment of the present disclosure
  • FIG23 is another schematic diagram of a connection between a first platform structure and a second platform structure provided in an embodiment of the present disclosure
  • FIG24 is a flow chart of a method for manufacturing a display substrate provided in an embodiment of the present disclosure.
  • FIG25 is a schematic diagram of using a semi-transmittance mask to manufacture an organic layer according to an embodiment of the present disclosure
  • Fig. 26 is a cross-sectional view along line III-III' in Fig. 25;
  • FIG27 is a schematic diagram of a structure of a display panel provided in an embodiment of the present disclosure.
  • FIG28 is a schematic diagram of another structure of a display panel provided in an embodiment of the present disclosure.
  • FIG29 is a schematic diagram of another structure of a display panel provided in an embodiment of the present disclosure.
  • FIG30 is a schematic diagram of a structure of a display device provided in an embodiment of the present disclosure.
  • FIG31 is a schematic diagram of another structure of a display device provided in an embodiment of the present disclosure.
  • FIG. 32 is another schematic diagram of the structure of the display device provided in the embodiment of the present disclosure.
  • FIG1 shows a solution of using a support structure (Smart PS, SPS) to support the spacer (PS) in the related art.
  • the stability of the film thickness and size (CD) are poor.
  • the two coating (Coating), exposure, and development processes of the organic layer greatly reduce the process stability and have an adverse effect on the uniformity of the supporting force of the spacer (PS), thereby increasing the risks of stripes (PS Mura) and insufficient transmittance caused by uneven force on the spacer (PS).
  • the embodiment of the present disclosure provides a display substrate, as shown in FIGS. 2 to 13, comprising:
  • Base substrate 101 optionally, the base substrate 101 is a rigid substrate, such as a glass substrate;
  • the organic layer 102 is located on one side of the base substrate 101.
  • the organic layer 102 includes a flat layer 1021 and a plurality of supporting structures 1022, wherein the flat layer 1021 includes a plurality of vias h, and the supporting structures 1022 are located on a side of the flat layer 1021 away from the base substrate 101 and are integrally arranged with the flat layer 1021, and the orthographic projection of the supporting structure 1022 on the base substrate 101 and the orthographic projection of the vias h on the base substrate 101 do not overlap with each other;
  • the material of the organic layer 102 may include at least one of organic insulating materials such as polymethyl methacrylate (also known as acrylic), polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, phenolic epoxy resin, etc., which is not limited here.
  • the flat layer 1021 can play the role of flattening the film layer below and preventing the generation of parasitic capacitance between the conductive film layer below the flat layer 1021 (for example, the source and drain metal layer of the transistor 103) and the conductive film layer above the flat layer 1021 (for example, the layer where the common electrode 104 is located), and the support structure 1022 can play the role of supporting the spacer (PS).
  • PS spacer
  • the via h penetrating the flat layer 1021 can be used to connect the pixel electrode 105 and the first electrode 1031 of the transistor 103, or to achieve electrical connection between the common electrode 104 and the switching electrode 106; and because the support structure 1022 is located on the side of the flat layer 1021 away from the base substrate 101, the orthographic projection of the support structure 1022 on the base substrate 101 and the orthographic projection of the via h on the base substrate 101 are arranged not to overlap each other, which can avoid the support structure 1022 from blocking the via h, thereby ensuring that the support structure 1022 and the via h can play their corresponding roles normally.
  • the present disclosure reduces one patterning (Mask) process and curing process of the organic layer 102 by making the support structure 1022 and the flat layer 1021 integrally arranged, that is, using one organic layer 102 to simultaneously form the flat layer 1021 and the support structure 1022, thereby alleviating the capacity pressure of the exposure machine and reducing the process fluctuations caused by two patterning (Mask) processes and two curing processes, thereby improving the size (CD) and film thickness uniformity of the support structure 1022, making the support force uniformity of the support structure 1022 on the spacer (PS) better, and ultimately improving the uniformity of the display quality.
  • Mosk patterning
  • CD size
  • PS spacer
  • a half-tone mask can be used to form different morphologies in different regions of the organic layer 102.
  • the opaque region i.e., the region with a transmittance approximately equal to 0%
  • the fully transparent region i.e., the region with a transmittance approximately equal to 100%
  • the half-transparent region i.e., the region with a transmittance greater than 0% and less than 100%
  • the half-transparent region i.e., the region with a transmittance greater than 0% and less than 100%
  • the half-transparent region can be used to form a pattern of at least a portion of the flat layer 1021 not blocked by the support structure 1022.
  • "approximately equal to” can be understood as being equal or within a reasonable error (e.g., ⁇ 5%) caused by factors such as
  • the inventors have found that if the distance between the semi-transparent area and the fully transparent area is too close, they will affect each other, not only making the morphology of the via h formed in the fully transparent area poor, but also causing the semi-transparent area to be overexposed, and the flat layer 1021 formed in the semi-transparent area to be uneven.
  • the mutual influence between the fully transparent area and the semi-transparent area can be reduced by increasing the distance between the fully transparent area and the semi-transparent area, thereby forming a via h and a flat layer 1021 with better morphology.
  • a plurality of platform structures 1023 integrated with the flat layer 1021 can be provided on the side of the flat layer 1021 in the organic layer 102 away from the base substrate 101, and the via h is extended to penetrate the platform structure 1021.
  • FIG14 and FIG15 respectively show pictures of diamond convex platform BP and via h formed in the organic layer using a semi-transmissive mask
  • FIG14 is a picture of diamond convex platform BP and via h formed in the organic layer using a semi-transmissive mask with a distance of 3.5 ⁇ m between the full light-transmitting area and the semi-transmissive area
  • FIG15 is a picture of diamond convex platform BP and via h formed in the organic layer using a semi-transmissive mask with a distance of 5 ⁇ m between the full light-transmitting area and the semi-transmissive area.
  • the minimum distance s1 between the outer surface of the platform structure 1023 away from the via h and the via h can be greater than or equal to 5 ⁇ m.
  • the minimum distance s1 between the outer surface of the platform structure 1023 away from the via h and the via h can be set to be equal to 5 ⁇ m; when the resolution of the actual product is small and the pixel size is large, the minimum distance s1 between the outer surface of the platform structure 1023 away from the via h and the via h can be set to be greater than 5 ⁇ m and less than the pixel size.
  • the mutual influence between the full light-transmitting area and the semi-light-transmitting area can also be reduced by using low-sensitivity organic materials with a higher precision exposure machine. In the future, it is expected that the transition zone between the full light-transmitting area and the semi-light-transmitting area can be eliminated.
  • the via h is a via whose aperture gradually increases in the direction Z where the organic layer 102 is away from the base substrate 101
  • the platform structure 1023 is a platform whose size gradually decreases in the direction Z where the organic layer 102 is away from the base substrate 101.
  • the minimum distance s1 between the outer surface of the platform structure 1023 away from the side of the via h and the via h can be understood as the distance between the top port of the largest aperture in the via h to the outer surface of the top of the smallest size in the platform structure 1023.
  • the semi-transmittance mask includes three areas, namely, a fully transparent area, a semi-transparent area and an opaque area, the area between the fully transparent area and the semi-transparent area is an opaque area.
  • the platform structure 1023 can be formed by the opaque area.
  • the support structure 1022 protruding relative to the flat layer 1021 in the present disclosure is also formed by the opaque area.
  • the thickness of the platform structure 1023 and the support structure 1022, both of which are formed by the opaque area can be roughly the same.
  • “roughly the same” can be understood as being the same or within the range of reasonable errors (e.g., ⁇ 5%) caused by factors such as manufacturing and measurement.
  • the thickness of the platform structure 1023 in the display substrate provided by the embodiments of the present disclosure, in the direction Z in which the organic layer 102 is away from the base substrate 101, the thickness of the platform structure 1023 may be greater than or equal to 0.5 ⁇ m and less than or equal to 1.2 ⁇ m, for example, the thickness of the platform structure 1023 may be 0.5 ⁇ m, 0.6 ⁇ m, 0.7 ⁇ m, 0.8 ⁇ m, 0.9 ⁇ m, 1 ⁇ m, 1.1 ⁇ m, 1.2 ⁇ m, etc.
  • the thickness of the platform structure 1023 is set to be between 0.5 ⁇ m and 1.2 ⁇ m in the present disclosure. And because the thickness of the platform structure 1023 is substantially the same as the thickness of the support structure 1022, the thickness of the support structure 1022 may also be between 0.5 ⁇ m and 1.2 ⁇ m.
  • the support structure 1022 within this thickness range may stably support the spacer (PS).
  • the higher the transmittance of the semi-transparent area the higher the step difference (equivalent to the thickness of the support structure 1022) formed between the support structure 1022 formed in the opaque area and the flat layer 1021 blocked by it, and the flat layer 1022 formed in the semi-transparent area under the same dose (Dose) of light.
  • the transmittance of the semi-transparent area is too small, in order to achieve the corresponding step difference (equivalent to the thickness of the support structure 1022), a larger dose (Dose) of light is required, and a large dose (Dose) of light is likely to make the via h formed in the fully transparent area too large; on the contrary, if the transmittance of the semi-transparent area is too large, in order to achieve the required step difference (equivalent to the thickness of the support structure 1022), a very small dose (Dose) of light is required, and a small dose (Dose) of light is likely to make the via h formed in the fully transparent area too small, and may even not form a via h that completely penetrates the organic layer 102.
  • the transmittance of the semi-transparent zone can be set to be greater than or equal to 15% and less than or equal to 35% in the present disclosure, for example, the transmittance of the semi-transparent zone is 15%, 20%, 25%, 30%, 35%, etc.
  • a plurality of gate lines 107 may be further included, which are located between the organic layer 102 and the base substrate 101 and extend along the first direction X and are arranged along the second direction Y, and the first direction X and the second direction Y are arranged crosswise; in the direction Z in which the organic layer 102 is away from the base substrate 101, the size of the support structure 1022 gradually decreases, and the support structure 1022 includes a top end away from the base substrate 101, and the width w of the top end in the first direction X is greater than or equal to 6 ⁇ m and less than or equal to 12 ⁇ m, for example, the top width w of the support structure 1022 is 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m, 10 ⁇ m, 11 ⁇ m, 12 ⁇ m, etc.
  • the minimum requirement for the top width w of the support structure 1022 is 6 ⁇ m to better match the spacer (PS) and achieve the minimum requirement for the supporting force; in order to more stably support the spacer (PS), the top width w of the support structure 1022 can be made larger (for example, 12 ⁇ m).
  • the top width w of the support structure 1022 in the present disclosure should not be too large.
  • the top width w of the support structure 1022 is 10 ⁇ m, which can better meet the supporting force requirements and avoid affecting the pixel transmittance.
  • the length l of the support structure 1022 in the second direction Y can be set to be greater than or equal to 25 ⁇ m and less than or equal to 50 ⁇ m.
  • the length l of the support structure 1022 in the second direction Y is 25 ⁇ m, 30 ⁇ m, 35 ⁇ m, 40 ⁇ m, 45 ⁇ m, 50 ⁇ m, etc.
  • the slope angle ⁇ of the support structure 1022 is greater than or equal to 30° and less than or equal to 60°.
  • the slope angle ⁇ of the support structure 1022 is 30°, 35°, 40°, 45°, 50°, 55°, 60°, etc., so that the side slope of the support structure 1022 is relatively gentle, ensuring that the coating of the common electrode 104, the inorganic insulating layer 108, and the pixel electrode 105 produced subsequently at the support structure 1022 is free of crack (Crack) and peeling (Peeling) risks.
  • the top width w of the support structure 1022 shown in Figure 16 is about 6.5 ⁇ m
  • the bottom width of the support structure 1022 is about 8 ⁇ m
  • the thickness of the support structure 1022 is about 1 ⁇ m
  • the slope angle ⁇ of the support structure 1022 is about 35°, which is beneficial to ensure that the common electrode 104, inorganic insulating layer 108, and pixel electrode 105 produced subsequently are well coated at the support structure 1022 without any defects.
  • the slope angle ⁇ of the flat layer 1021 at the via h is greater than or equal to 50° and less than or equal to 60°, for example, the slope angle ⁇ of the flat layer 1021 at the via h is 50°, 51°, 52°, 53°, 54°, 55°, 56°, 57°, 58°, 59°, 60°, etc.
  • the slope angle ⁇ of the flat layer 1021 at the via h is within this angle range, which can not only make the top port aperture of the via h smaller, ensure the process limit (Margin) between the via h and the related film layer, but also ensure the good overlap of the pixel electrode 105 or the common electrode 104 in the via h.
  • the slope angle ⁇ of the flat layer 1021 at the via h is about 55°, and protected by the platform structure 1023, the morphology of the via h is good.
  • the aperture of the via h gradually increases, and the via h includes a bottom port close to the base substrate 101, and the aperture D of the bottom port is greater than or equal to 4 ⁇ m and less than or equal to 7 ⁇ m, for example, the aperture D of the bottom port of the via h is 4 ⁇ m, 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, etc.
  • the aperture D of the bottom port of the via h is set to be greater than or equal to 4 ⁇ m and less than or equal to 7 ⁇ m, which can ensure that the morphology of the via h is good, as shown in FIG. 17.
  • the thickness of the flat layer 1021 in the direction Z where the organic layer 102 is away from the base substrate 101 may be greater than 2 ⁇ m.
  • the thickness of the flat layer 1021 in the direction Z where the organic layer 102 is away from the base substrate 101 is about 2.5 ⁇ m, so that the flat layer 1021 can well play the role of flattening the underlying film layer and preventing the generation of parasitic capacitance between the conductive film layer below the flat layer 1021 (for example, the source and drain metal layer of the transistor 103) and the conductive film layer above the flat layer 1021 (for example, the layer where the common electrode 104 is located).
  • the surface of the organic layer 102 away from the base substrate 101 may be uneven, that is, the surface of the organic layer 102 away from the base substrate 101 is rough, thereby increasing the contact area between the organic layer 102 and the common electrode 104, thereby improving the adhesion between the organic layer 102 and the common electrode 104, and preventing the film layer where the common electrode 104 is located from peeling.
  • ion bombarding the surface of the organic layer 102 away from the base substrate 101, the surface of the organic layer 102 away from the base substrate 101 becomes uneven.
  • a plurality of transistors 103 are located between the organic layer 102 and the base substrate 101, and a plurality of pixel electrodes 105 are located on the side of the organic layer 102 away from the base substrate 101;
  • the plurality of via holes h include a plurality of first via holes h 1 , and the first via holes h 1 connect the first pole 1031 of the transistor 103 with the pixel electrode 105;
  • the plurality of platform structures 1023 include a plurality of first platform structures 10231, and the first platform structures 10231 are penetrated by the first via holes h 1 , so as to form the first via holes h 1 with better morphology through the protection of the first platform structures 10231.
  • part of the first platform structures 10231 are integrally arranged with each supporting structure 1022. Because the first via hole h1 has a certain slope, if the support structure 1022 falls on the slope of the first via hole h1 , the support structure 1022 will lose its supporting function; therefore, in some embodiments, the top port of the first via hole h1 is approximately 1 ⁇ m larger than the bottom port on one side. In order to ensure the process limit (Margin), the distance s3 between the top port of the first via hole h1 and the bottom end of the support structure 1022 should be greater than or equal to 2 ⁇ m.
  • the minimum distance s2 between the first platform structure 10231 and the support structure 1022 (since the first platform structure 10231 and the support structure 1022 are both platforms whose sizes gradually decrease in the direction Z in which the organic layer 102 is away from the base substrate 101, therefore, the minimum distance s2 between the first platform structure 10231 and the support structure 1022 can be understood as the distance between the bottom end of the first platform structure 10231 and the bottom end of the support structure 1022) is very small (for example, less than 2 ⁇ m)
  • the first platform structure 10231 can be connected to the support structure 1022, so that the first platform structure 10231 and the support structure 1022 are combined into one; such a setting can also prevent a very small semi-transparent area from being pre-sandwiched between the opaque area used to form the first platform structure 10231 and the opaque area used to form the support structure 1022, causing the morphology of the
  • whether the first platform structure 10231 is integrated with the support structure 1022 may be determined according to actual pixel design, because when the distance between the fully light-transmitting area for forming the first via hole h1 and the semi-light-transmitting area for forming the flat layer 1021 (which may be equivalent to the minimum distance s1 between the outer surface of the first platform structure 10231 on the side away from the first via hole h1 and the first via hole h1 ) is greater than 5 ⁇ m, the existence of the first platform structure 10231 may satisfy the minimum distance s3 between the top port of the first via hole h1 and the support structure 1022 (since the first via hole h1 is a via hole whose aperture gradually increases in the direction Z in which the organic layer 102 is away from the base substrate 101, and the support structure 1022 is a platform whose size gradually decreases in the direction Z in which the organic layer 102 is away from the base substrate 101, therefore, the minimum distance s3 between the top port of the first via hole
  • the first platform structure 10231 and the supporting structure 1022 is greater than or equal to 2 ⁇ m, so whether the first platform structure 10231 and the supporting structure 1022 are combined into one is not a problem in design and process, and can be determined according to the actual pixel design. Under the condition that the full light-transmitting area and the semi-light-transmitting area do not affect each other, whether the first platform structure 10231 and the supporting structure 1022 are combined into one is within the scope of the present disclosure.
  • the support structure 1022 and the first platform structure 10231 may be provided separately, or in some embodiments, for the support structure 1022 and the first platform structure 10231 provided integrally, as shown in FIG10 , the first platform structure 10231 and the support structure 1022 may be directly connected, or, as shown in FIG18 to FIG20 , the first platform structure 10231 and the support structure 1022 may be connected via a first connection portion Lk 1.
  • the a side of the first platform structure 10231 may be directly extended to contact with the support structure 1022 to form the first connection portion LK 1 ; or, as shown in FIG19 , the b side of the first platform structure 10231 may be directly extended to contact with the support structure 1022 to form the first connection portion LK 1 ; or, as shown in FIG20 , the two vertices of the c side of the first platform structure 10231 may be directly connected to the support structure 1022 to form the first connection portion LK 1 .
  • the liquid crystal may have alignment and flow problems here, and the width of the first connection part LK 1 shown in FIG. 20 is relatively small.
  • the first connection part LK 1 shown in FIG. 19 can be used.
  • FIG. 10, FIG. 18 to FIG. 20 are all illustrated by taking the first platform structure 10231 as an octagonal platform as an example.
  • the first platform structure 10231 can also be a polygonal platform such as a quadrilateral platform or a hexagonal platform.
  • the edges and corners of the first platform structure 10231, the support structure 1022 and the first connection part LK 1 will not be so sharp but will form arc angles. Therefore, the first platform structure 10231, the support structure 1022 and the first connection part LK 1 can also include arc segments.
  • the common electrode 104 is located between the layer where the multiple pixel electrodes 105 are located and the organic layer 102, and the switching electrode 106 can be provided in the same layer and with the same material as the first electrode 1031 of the transistor 103;
  • the multiple via holes h also include multiple second via holes h2 , and the second via holes h2 connect the common electrode 104 and the switching electrode 106;
  • the multiple platform structures 1023 include multiple second platform structures 10232, and the second platform structures 10232 are penetrated by the second via holes h2 , so as to form second via holes h2 with better morphology through the protection of the second platform structures 10232.
  • each second platform structure 10232 is integrally arranged with part of the first platform structure 10231, and the second platform structure 10232 and the supporting structure 1022 are respectively integrally arranged with different first platform structures 10231.
  • the first platform structure 10231 and the second platform structure 10232 can be connected so that the first platform structure 10231 and the second platform structure 10232 are combined into one.
  • the first platform structure 10231 and the second platform structure 10232 may be separately provided, or in some embodiments, for the first platform structure 10231 and the second platform structure 10232 provided as one, as shown in FIG10, the second platform structure 10232 and the first platform structure 10231 may be directly connected, or, as shown in FIG21 to FIG23, the first platform structure 10231 and the second platform structure 10232 have a certain distance in the first direction and/or the second direction.
  • the second platform structure 10232 and the first platform structure 10231 may be connected via a second connection portion Lk 2 .
  • the first platform structure 10231 and the second platform structure 10232 have a certain distance in both the first direction and the second direction.
  • the centers of the first via hole h1 and the second via hole h2 that penetrate the first platform structure 10231 and the second platform structure 10232 may be staggered in the first direction and the second direction.
  • the d side of the first platform structure 10231 may be directly extended to contact the second platform structure 10232, and the e side of the second platform structure 10232 may be extended to contact the first platform structure 10231 to form the second connection portion LK 2 ; or the center line of the first via hole h1 and the second via hole h2 that penetrate the first platform structure 10231 and the second platform structure 10232 may be along the first/second direction or the third direction, wherein the third direction is different from the first direction and the second direction as shown in FIG.
  • the two vertices of the f side of the first platform structure 10231 may be directly connected to the second platform structure 10232 to form the second connection portion LK 2 ; Or, as shown in FIG23, the two vertices of the g side of the second platform structure 10232 can be directly connected to the first platform structure 10231 to form the second connection portion LK2 .
  • FIG10, FIG21 to FIG23 are all illustrated by taking the second platform structure 10232 as an octagonal platform as an example.
  • the second platform structure 10232 can also be a polygonal platform such as a quadrilateral platform or a hexagonal platform.
  • the edges and corners of the second platform structure 10232 may not be so sharp but may form arc angles. Therefore, the second platform structure 10232 may also include arc segments.
  • “same layer, same material” refers to a layer structure formed by using the same film-forming process to form a film layer for making a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to a mask (also called a photomask). Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or at different heights or have different thicknesses.
  • a common electrode line 109 provided in the same layer and with the same material as the gate line 107 may also be included.
  • the common electrode line 109 is electrically connected to the switching electrode 106 through a third via hole h3 penetrating the interlayer dielectric layer 110, and then provides a signal to the common electrode 104 through the switching electrode 106; and the existence of the common electrode line 109 can also effectively reduce the overall resistance of the common electrode 104, which is conducive to maintaining the signal uniformity on the common electrode 104.
  • the transistor 103 in addition to the first electrode 1031, may also include a second electrode 1032, a gate 1033 and an active layer 1034, wherein the first electrode 1031 may be a source electrode and the second electrode 1032 may be a drain electrode, or the first electrode 1031 may be a drain electrode and the second electrode 1032 may be a source electrode.
  • the materials of the first electrode 1031, the second electrode 1032 and the gate 1033 may include metal materials or alloy materials, such as a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, for example, the multilayer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum and titanium (Ti/Al/Ti); the material of the active layer 1034 may include amorphous silicon, polycrystalline silicon or an oxide semiconductor (for example, indium gallium zinc oxide).
  • the transistor 103 may be a bottom-gate transistor, a top-gate transistor, a double-gate transistor, etc.
  • the transistor 103 may be a P-type transistor or an N-type transistor, wherein the P-type transistor is turned on when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs ⁇ V th , and is turned off when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs ⁇ V th; the N-type transistor is turned on when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs >V th , and is turned off when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs >V th, and is turned off when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs >V th.
  • the transistor is turned off when gs and its threshold voltage V th satisfy the relationship V gs ⁇ V th .
  • the first electrode 1031 can be electrically connected to the active layer 1034 through a fourth via hole h4 penetrating the interlayer dielectric layer 110 and the gate insulating layer 111
  • the second electrode 1032 can be electrically connected to the active layer 1034 through a fifth via hole h5 penetrating the interlayer dielectric layer 110 and the gate insulating layer 111.
  • a single patterning process can be used to simultaneously form the fourth via hole h4 and the fifth via hole h5 penetrating the interlayer dielectric layer 110 and the gate insulating layer 111, so as to avoid patterning the interlayer dielectric layer 110 and the gate insulating layer 111 separately to form vias.
  • the shape of the active layer 1034 can be approximately U-shaped; as shown in FIG7 , the portion where the gate line 107 overlaps with the active layer 1034 can be used as the gate 1033.
  • the gate line 107 and the active layer 1034 have two overlapping portions, so that the transistor 103 has two gates, forming a dual-gate transistor; of course, in some embodiments, the shape of the active layer 1034 can also be approximately I-shaped, and the corresponding transistor 103 can be a single-gate transistor.
  • the portion of the data line 112 that overlaps with one end of the active layer 1034 can be used as the second pole 1032, and in order to facilitate the second pole 1032 to overlap the active layer 1034, the portion of the data line 112 that serves as the second pole 1032 can be widened.
  • a light shielding layer 113 may be further provided under the active layer 1034 in the present disclosure.
  • the light shielding layer 113 in order to improve the transmittance of the display substrate, only blocks the channel region of the active layer 1034 (equivalent to the region where the gate 1033 is located).
  • the light shielding layer 113 blocks the channel region of the active layer 1034 and extends 1 ⁇ m on one side compared to the channel region of the active layer 1034 (equivalent to the region where the gate 1033 is located) in the first direction X.
  • the pixel electrode 105 may be a slit electrode, and the common electrode 104 may be a planar electrode.
  • the common electrode 104 has a hollow structure k at a position corresponding to the first via hole h1
  • the inorganic insulating layer 108 has a sixth via hole h6 at a position corresponding to the first via hole h1 , so that the pixel electrode 105 is electrically connected to the first electrode 1031 of the transistor 103 through the sixth via hole h6 , the hollow structure k and the first via hole h1 .
  • the material of the pixel electrode 105 and the material of the common electrode 104 may be transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO).
  • the above-mentioned display substrate provided in the embodiments of the present disclosure may also include other components that should be understood by ordinary technicians in the field (such as an orientation layer located on the side of the pixel electrode 105 away from the base substrate 101), which are not elaborated here and should not be regarded as a limitation of the present disclosure.
  • the embodiment of the present disclosure also provides a method for manufacturing the above-mentioned display substrate. Since the principle of solving the problem by the manufacturing method is similar to the principle of solving the problem by the above-mentioned display substrate, the implementation of the manufacturing method provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned display substrate, and the repeated parts will not be repeated.
  • the method for manufacturing the substrate may include the following steps:
  • S2402. Form an organic layer on the base substrate using a semi-transmittance mask plate, wherein the organic layer includes a flat layer and a plurality of supporting structures, wherein the flat layer includes a plurality of vias, the supporting structure is located on a side of the flat layer away from the base substrate and is integrally arranged with the flat layer, and an orthographic projection of the supporting structure on the base substrate and an orthographic projection of the vias on the base substrate do not overlap with each other.
  • the above-mentioned step S2402 forming an organic layer on the base substrate using a semi-transmittance mask plate, can be specifically implemented in the following manner:
  • the opaque area NA of the semi-transmittance mask is used to form a plurality of support structures 1022, a first flat portion 10211 blocked by the support structure 1022, a plurality of platform structures 1023, and a second flat portion 10212 blocked by the platform structure 1023;
  • the semi-transmittance area HA of the semi-transmittance mask is used to form a third flat portion 10213 not blocked by the support structure 1022 and the platform structure 1023;
  • the full light-transmittance area FA of the semi-transmittance mask is used to form a plurality of via holes h penetrating the platform structure 1023 and the second flat portion 10212, and the flat layer 1021 of the organic layer 102 includes the first flat portion 10211, the second flat portion 10212, and the third flat portion 10213.
  • the transmittance of the semi-transmittance area of the semi-transmittance mask is greater than or equal to 15% and less than or equal to 35%.
  • the patterning process involved in forming each layer structure may include not only part or all of the process such as deposition, photoresist coating, mask template masking, exposure, development, etching, photoresist stripping, etc., but also other process, which is subject to the graphics of the required composition formed in the actual manufacturing process, and is not limited here.
  • a post-baking process may also be included after development and before etching.
  • the deposition process may be chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition, which is not limited here.
  • the embodiment of the present disclosure further provides a display panel, as shown in FIG. 27 and FIG. 28, comprising a display substrate 001 and an opposing substrate 002 disposed opposite to each other, and a liquid crystal layer 003 located between the display substrate 001 and the opposing substrate 002, wherein the display substrate 001 is the above-mentioned display substrate 001 provided in the embodiment of the present disclosure.
  • the display panel Since the principle of solving the problem by the display panel is similar to the principle of solving the problem by the above-mentioned display substrate, the implementation of the display panel provided in the embodiment of the present disclosure can refer to the implementation of the above-mentioned display substrate, and the repeated parts will not be repeated.
  • the opposing substrate 002 includes a black matrix 201, and the orthographic projection of the platform structure 1023 (which may include a first platform structure 10231 and a second platform structure 10232) on the base substrate 101 is located within the orthographic projection of the black matrix 201 on the base substrate 101, so as to shield the platform structure 1023 through the black matrix BM to prevent light leakage at the platform structure 1023.
  • the orthographic projection of the platform structure 1023 which may include a first platform structure 10231 and a second platform structure 10232
  • the counter substrate 002 may further include a substrate 202, a color resist (not shown in the figure), etc.
  • the black matrix 201 is a grid-like structure
  • the color resist may be located in the grid of the grid-like structure
  • the orthographic projection of the pixel electrode 105 on the base substrate 101 is located in the orthographic projection of the color resist on the base substrate 101
  • the color resist may include red light color resist, green light color resist, blue light color resist, etc.
  • the above-mentioned counter substrate 002 provided in the embodiment of the present disclosure may also include other components that should be understood by those of ordinary skill in the art (for example, an alignment layer located at the side of the black matrix 201 layer facing the liquid crystal layer 003), which will not be described in detail here, nor should it be used as a limitation to the present disclosure.
  • other components that should be understood by those of ordinary skill in the art (for example, an alignment layer located at the side of the black matrix 201 layer facing the liquid crystal layer 003), which will not be described in detail here, nor should it be used as a limitation to the present disclosure.
  • the display panel provided by the embodiment of the present disclosure may further include a frame sealant located between the display substrate 001 and the counter substrate 002 and surrounding the liquid crystal layer 003, a first polarizer located on the side of the display substrate 001 away from the counter substrate 002, and a second polarizer located on the side of the counter substrate 002 away from the display substrate 001, wherein the light transmission axis of the first polarizer is perpendicular to the light transmission axis of the second polarizer.
  • a frame sealant located between the display substrate 001 and the counter substrate 002 and surrounding the liquid crystal layer 003, a first polarizer located on the side of the display substrate 001 away from the counter substrate 002, and a second polarizer located on the side of the counter substrate 002 away from the display substrate 001, wherein the light transmission axis of the first polarizer is perpendicular to the light transmission axis of the second polarizer.
  • the embodiment of the present disclosure further provides a display device, including a backlight module and a display panel located on the light-emitting side of the backlight module, wherein the display panel is the above-mentioned display panel provided in the embodiment of the present disclosure. Since the principle of solving the problem by the display device is similar to the principle of solving the problem by the above-mentioned display panel, the implementation of the display device provided in the embodiment of the present disclosure can refer to the implementation of the above-mentioned display panel, and the repeated parts will not be repeated.
  • the above-mentioned backlight module provided by the embodiments of the present disclosure may be a direct-type backlight module or an edge-type backlight module.
  • the edge-type backlight module may include a light bar, a reflective sheet, a light guide plate, a diffuser, a prism group, etc., which are stacked, and the light bar is located on one side of the thickness direction of the light guide plate.
  • the direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightness enhancement film, etc., which are stacked on the light-emitting side of the matrix light source, and the reflective sheet includes an opening that is arranged opposite to the position of each lamp bead in the matrix light source.
  • the lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).
  • Submillimeter or even micron-scale micro-LEDs are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because the light emission of inorganic light-emitting diodes is based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting diodes that emit light based on organic matter, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life. And when micro-LEDs are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving the brightness and contrast of the screen, it can also solve the glare phenomenon caused by traditional dynamic backlighting between the bright and dark areas of the screen, optimizing the visual experience.
  • OLEDs organic light-emitting diodes
  • the above-mentioned display device provided by the embodiment of the present disclosure can be applied to medium and large-sized vehicle display products (as shown in FIG. 30 ), touch screens (TPC, as shown in FIG. 31 ), and displays (MNT, as shown in FIG. 32 ).
  • TPC touch screens
  • MNT displays
  • FIG. 32 the small-sized application scenario does not have large bending and vibration, and it is not necessary to adopt the solution of the present disclosure to ensure that the display substrate 001 and the opposing substrate 002 can have large sliding without being affected; secondly, the small size pursues high resolution (PPI), and there is not enough space to meet the solution of the present disclosure.
  • PPI high resolution
  • FIG. 30 specifically shows that the display device of the present disclosure is integrated in the central area of the steering wheel SS in the vehicle display product, and FIG. 30 shows the display area AA of the display device and the box BX carrying the steering wheel SS.
  • the box BX may be provided with power supply, control circuit, radiator and other components, which are not limited here; in some embodiments, the display device of the present disclosure can also be set independently of the steering wheel SS, for example, it can be a large central control screen set near the steering wheel SS, or a large-screen roof sunroof set on the top of the car, or the display device can be used as a car window, which is not limited here.
  • FIG31 shows a return key H (i.e., Home key), a display area AA, and a camera C of a touch screen.
  • FIG32 shows a display area AA and a base B of a display.
  • the above-mentioned display device may also include but is not limited to: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip.
  • the control chip is a central processing unit, a digital signal processor, a system chip (SoC), etc.
  • the control chip may also include a memory, and may also include a power module, etc., and realize the power supply and signal input and output functions through additionally provided wires, signal lines, etc.
  • the control chip may also include a hardware circuit and a computer executable code, etc.
  • the hardware circuit may include a conventional very large scale integration (VLSI) circuit or gate array and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include a field programmable gate array, a programmable array logic, a programmable logic device, etc.
  • VLSI very large scale integration
  • the above-mentioned structure does not constitute a limitation on the above-mentioned display device provided in the embodiment of the present disclosure.
  • the above-mentioned display device provided in the embodiment of the present disclosure may include more or less of the above-mentioned components, or combine certain components, or arrange different components.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板、其制作方法、显示面板及显示装置，包括:衬底基板（101）；有机层（102），位于衬底基板（101）的一侧，有机层（102）包括平坦层（1021）和多个支撑结构（1022），其中，平坦层（1021）包括多个过孔，支撑结构（1022）位于平坦层（1021）远离衬底基板（101）的一侧且与平坦层（1021）一体设置，支撑结构（1022）在衬底基板（101）上的正投影与过孔在衬底基板（101）上的正投影互不交叠。

Description

显示基板、其制作方法、显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、其制作方法、显示面板及显示装置。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有重量轻、耗电少、画质高、辐射低和携带方便等优点，已逐渐取代传统的阴极射线管显示装置(Cathode Ray Tube display，CRT)，而被广泛应用于现代化信息设备，如增强现实(AR)/虚拟现实(VR)显示设备、笔记本电脑、电视、移动电话和数字产品等。
发明内容
本公开实施例提供的显示基板、其制作方法、显示面板及显示装置，具体方案如下：
一方面，本公开实施例提供了一种显示基板，包括：
衬底基板；
有机层，位于所述衬底基板的一侧，所述有机层包括平坦层和多个支撑结构，其中，所述平坦层包括多个过孔，所述支撑结构位于所述平坦层远离所述衬底基板的一侧且与所述平坦层一体设置，所述支撑结构在所述衬底基板上的正投影与所述过孔在所述衬底基板上的正投影互不交叠。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述有机层还包括位于所述平坦层远离所述衬底基板一侧且与所述平坦层一体设置的多个平台结构，所述过孔延伸至贯穿所述平台结构。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述平台结构远离所述过孔一侧的外表面与所述过孔之间的最小距离大于等于5μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述有机层与所述衬底基板之间的多个晶体管，以及位于所述有机层远离所述衬底基板一侧的多个像素电极；
所述多个过孔包括多个第一过孔，所述第一过孔连接所述晶体管的第一极与所述像素电极；
所述多个平台结构包括多个第一平台结构，所述第一平台结构被所述第一过孔贯穿。
在一些实施例中，在本公开实施例提供的上述显示基板中，部分所述第一平台结构与各所述支撑结构一体设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一平台结构与所述支撑结构之间的最小距离小于2μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，在所述有机层远离所述衬底基板的方向上，所述过孔的孔径逐渐增大，所述第一过孔的顶部端口到所述支撑结构之间的最小距离大于等于2μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括多个第一连接部，所述第一连接部连接所述支撑结构与所述第一平台结构。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述多个像素电极所在层与所述有机层之间的公共电极，以及与所述晶体管的第一极同层、同材料的多个转接电极；
所述多个过孔还包括多个第二过孔，所述第二过孔连接所述公共电极与所述转接电极；
所述多个平台结构包括多个第二平台结构，所述第二平台结构被所述第二过孔贯穿。
在一些实施例中，在本公开实施例提供的上述显示基板中，各所述第二平台结构与部分所述第一平台结构一体设置，且所述第二平台结构、所述支撑结构分别与不同的所述第一平台结构一体设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括多个 第二连接部，所述第二连接部连接所述第二平台结构与所述第一平台结构。
在一些实施例中，在本公开实施例提供的上述显示基板中，在所述有机层远离所述衬底基板的方向上，所述平台结构的厚度与所述支撑结构的厚度大致相同。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述有机层远离所述衬底基板一侧的表面凹凸不平。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述有机层与所述衬底基板之间且沿第一方向延伸、沿第二方向排布的多条栅线，所述第一方向与所述第二方向交叉设置；
在所述有机层远离所述衬底基板的方向上，所述支撑结构的尺寸逐渐减小，所述支撑结构包括远离所述衬底基板一侧的顶端，所述顶端在所述第一方向上的宽度大于等于6μm且小于等于12μm；所述支撑结构在所述第二方向上的长度大于等于25μm且小于等于50μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述支撑结构的坡度角大于等于30°且小于等于60°。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述平坦层在所述有机层远离所述衬底基板的方向上的厚度大于2μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，在所述有机层远离所述衬底基板的方向上，所述平台结构的厚度大于等于0.5μm且小于等于1.2μm。
另一方面，本公开实施例提供了一种上述显示基板的制作方法，包括：
提供一衬底基板；
采用半透过率掩膜板在所述衬底基板上形成有机层，所述有机层包括平坦层和多个支撑结构，其中，所述平坦层包括多个过孔，所述支撑结构位于所述平坦层远离所述衬底基板的一侧且与所述平坦层一体设置，所述支撑结构在所述衬底基板上的正投影与所述过孔在所述衬底基板上的正投影互不交叠。
在一些实施例中，在本公开实施例提供的上述制作方法中，采用半透过率掩膜板在所述衬底基板上形成有机层，具体包括：
采用所述半透过率掩膜板的不透光区形成多个支撑结构、被所述支撑结构遮挡的第一平坦部、多个平台结构、以及被所述平台结构遮挡的第二平坦部；采用所述半透过率掩膜板的半透光区形成未被所述支撑结构和所述平台结构遮挡的第三平坦部；采用所述半透过率掩膜板的全透光区形成贯穿所述平台结构和所述第二平坦部的多个过孔，所述有机层的平坦层包括所述第一平坦部、所述第二平坦部和所述第三平坦部。
在一些实施例中，在本公开实施例提供的上述制作方法中，所述半透过率掩膜板的半透光区的透过率大于等于15％且小于等于35％。
另一方面，本公开实施例还提供了一种显示面板，包括相对而置的显示基板和对向基板，以及位于所述显示基板与所述对向基板之间的液晶层，其中，所述显示基板为本公开实施例提供的上述显示基板。
在一些实施例中，在本公开实施例提供的上述显示面板中，所述对向基板包括黑矩阵，所述平台在所述衬底基板上的正投影位于所述黑矩阵在所述衬底基板上的正投影内。
另一方面，本公开实施例提供了一种显示装置，包括背光模组、以及位于所述背光模组出光侧的显示面板，其中，所述显示面板为本公开实施例提供的上述显示面板。
附图说明
图1为相关技术中显示面板的一种结构示意图；
图2为本公开实施例提供的显示基板的一种结构示意图；
图3为沿图2中I-I’线的截面图；
图4为沿图2中II-II’线的截面图；
图5为图2中遮光层的结构示意图；
图6为图2中有源层的结构示意图；
图7为图2中栅线所在层的结构示意图；
图8为图2中层间介质层与栅绝缘层的结构示意图；
图9为图2中数据线所在层的结构示意图；
图10为图2中平坦层的结构示意图；
图11为图2中公共电极的结构示意图；
图12为图2中无机绝缘层的结构示意图；
图13为图2中像素电极的结构示意图；
图14为采用半透过率掩膜板在有机层中所形成的菱形凸台和过孔的一种图片；
图15为采用半透过率掩膜板在有机层中所形成的菱形凸台和过孔的又一种图片；
图16为本公开实施例提供的有机层的一种局部结构示意图；
图17为本公开实施例提供的有机层的又一种局部结构示意图；
图18为本公开实施例提供的支撑结构与第一平台结构的一种连接示意图；
图19为本公开实施例提供的支撑结构与第一平台结构的又一种连接示意图；
图20为本公开实施例提供的支撑结构与第一平台结构的又一种连接示意图；
图21为本公开实施例提供的第一平台结构与第二平台结构的一种连接示意图；
图22为本公开实施例提供的第一平台结构与第二平台结构的又一种连接示意图；
图23为本公开实施例提供的第一平台结构与第二平台结构的又一种连接示意图；
图24为本公开实施例提供的显示基板的制作方法的流程图；
图25为本公开实施例提供的采用半透过率掩膜板制作有机层的示意图；
图26为沿图25中III-III’线的截面图；
图27为本公开实施例提供的显示面板的一种结构示意图；
图28为本公开实施例提供的显示面板的又一种结构示意图；
图29为本公开实施例提供的显示面板的又一种结构示意图；
图30为本公开实施例提供的显示装置的一种结构示意图；
图31为本公开实施例提供的显示装置的又一种结构示意图；
图32为本公开实施例提供的显示装置的又一种结构示意图。
附图标记：
衬底基板-101，有机层-102，平坦层-1021，第一平坦部-10211，第二平坦部-10212，第三平坦部-10213，支撑结构-1022，平台结构-1023，第一平台结构-10231，第二平台结构-10232，晶体管-103，第一极-1031，第二极-1032，栅极-1033，有源层-1034，公共电极-104，像素电极-105，转接电极-106，栅线-107，无机绝缘层-108，公共电极线-109，层间介质层-110，栅绝缘层-111，数据线-112，遮光层-113；显示基板-001，对向基板-002，液晶层-003，黑矩阵-201，衬底-202。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同， 而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着液晶显示产品走进人们生活的方方面面，人们对液晶显示产品的显示效果越来越关注，要求越来越严格。精细化的设计和工艺是必然要求。其中，中大尺寸车载产品、触控屏(TPC)、显示器(MNT)等产品因环境温度变化或产品受到外力作用冲击，会对产品显示有影响。这是因为目前这些产品中位于对向基板(CF)上的隔垫物(PS)设计效果不佳，导致显示基板(array)与对向基板之间对盒偏移形成条纹(PS Mura)、漏光等不良。并且当液晶面板强度不足时，在受到外力冲击后隔垫物(PS)会存在滑入平坦(PLN)层的过孔的风险，失去隔垫物(PS)维持盒厚均一性的作用，产生不可恢复性色斑，造成条纹(PS Mura)不良。
通过在显示基板(array)上设置支撑结构(Smart PS，SPS)来实现对隔垫物(PS)的稳定支撑，可以有效改善上述技术问题，降低产品不良，提高液晶显示产品的品质和良率，降低成本。图1所示为相关技术中采用支撑结构(Smart PS，SPS)来支撑隔垫物(PS)的一种方案。由图1可见，在该方案中，需在显示基板(Array)中形成两个有机层，其中一个有机层为平坦(PLN)层，起到平坦下方膜层、并防止下方膜层与公共电极(CITO)、像素电极(PITO)形成寄生电容的作用；另一个有机层为支撑结构(Smart PS，SPS)的膜层，可有效防止隔垫物(PS)滑入平坦(PLN)层的过孔中，从而使得隔垫物(PS)可以更好地发挥维持盒厚均一性的作用。然而目前的瓶颈之一就是有机层专用的曝光机，图1所示的方案造成了较大的产能压力；且因有机层的厚度较大，所以膜厚、尺寸(CD)稳定性均较差，两次有机层的涂覆(Coating)、曝光、显影工艺，大大降低了工艺稳定性，对隔垫物(PS)支撑力的均一性造成不良的影响，从而增加了隔垫物(PS)受力不均引起的条纹(PS Mura)、透过率不足等风险。
为了改善相关技术中存在的上述技术问题，本公开实施例提供了一种显 示基板，如图2至图13所示，包括：
衬底基板101，可选地，衬底基板101为刚性基板，例如玻璃基板；
有机层102，位于衬底基板101的一侧，有机层102包括平坦层1021和多个支撑结构1022，其中，平坦层1021包括多个过孔h，支撑结构1022位于平坦层1021远离衬底基板101的一侧且与平坦层1021一体设置，支撑结构1022在衬底基板101上的正投影与过孔h在衬底基板101上的正投影互不交叠；可选地，有机层102的材料可以包括聚甲基丙烯酸甲酯(也称为亚克力)、聚丙烯酸树脂、聚环氧丙烯酸树脂、感光性聚酰亚胺树脂、聚酯丙烯酸酯、聚氨酯丙烯酸酯树脂、酚醛环氧树脂等有机绝缘材料中的至少一种，在此不做限定。
在本公开实施例提供的上述显示基板中，平坦层1021可以起到平坦下方膜层、并防止平坦层1021的下方导电膜层(例如晶体管103的源漏金属层)与平坦层1021的上方导电膜层(例如公共电极104所在层)之间产生寄生电容的作用，支撑结构1022可以起到支撑隔垫物(PS)的作用，贯穿平坦层1021的过孔h可用于连接像素电极105与晶体管103的第一极1031，或者，用于实现公共电极104与转接电极106的电连接；且由于支撑结构1022位于平坦层1021远离衬底基板101的一侧，设置支撑结构1022在衬底基板101上的正投影与过孔h在衬底基板101上的正投影互不交叠，可以避免支撑结构1022遮挡过孔h，保证了支撑结构1022、过孔h可以正常起到相应的作用。
相较于相关技术中采用两个有机层102分别形成平坦层1021和支撑结构1022的方案，本公开通过使支撑结构1022与平坦层1021一体设置，即利用一个有机层102同时形成平坦层1021和支撑结构1022，可减少有机层102的一道构图(Mask)工艺、固化工艺，从而减轻了曝光机产能压力，同时减小了因两次构图(Mask)工艺和两次固化工艺造成的工艺波动，提高了支撑结构1022的尺寸(CD)及膜厚均一性，使得支撑结构1022对隔垫物(PS)的支撑力均一性较好，最终提升了显示画质的均一性。
在一些实施例中，在本公开实施例提供的上述显示基板中，可利用半透 过率掩膜板(Half-Tone Mask，HTM)在有机层102的不同区域形成不同的形貌。例如可利用半透过率掩膜板的不透光区(即透过率大致等于0％的区域)来形成支撑结构1022所在区的图案，利用半透过率掩膜板的全透光区(即透过率大致等于100％的区域)来形成过孔h所在区的图案，并利用半透过率掩膜板的半透光区(即透过率大于0％且小于100％的区域)形成未被支撑结构1022遮挡的平坦层1021的至少部分区域的图案。本公开中“大致等于”可以理解为相等或在因制作、测量等因素造成的合理误差(例如±5％)范围内。
然而，发明人发现半透光区和全透光区之间距离太近的话，会相互造成影响，不仅使得全透光区对应形成的过孔h形貌不佳，还会造成半透光区存在过曝，半透光区对应形成的平坦层1021不平整。在一些实施例中，可通过增大全透过区与半透光区之间的距离，来减小全透光区与半透光区之间的相互影响，从而形成形貌较好的过孔h和平坦层1021。基于此，如图3、图4和图10所示，可在有机层102中平坦层1021远离衬底基板101一侧设置与平坦层1021一体的多个平台结构1023，并使过孔h延伸至贯穿平台结构1021。
图14和图15分别示出了采用半透过率掩膜板在有机层中所形成的菱形凸台BP和过孔h的图片，其中，图14为采用全透光区与半透光区之间距离3.5μm的半透过率掩膜板在有机层中所形成的菱形凸台BP和过孔h的图片，图15为采用全透光区与半透光区之间距离5μm的半透过率掩膜板在有机层中所形成的菱形凸台BP和过孔h的图片。对比图14和图15可知，在全透光区与半透光区之间距离3.5μm的情况下，全透光区对应形成的过孔h有边缘毛刺，形貌不佳，且不透光区对应形成的菱形凸台BP的坡度角不佳，未形成明显的菱形；在全透光区与半透光区之间距离5μm的情况下，全透光区对应形成的过孔h形貌良好，且不透光区对应形成的菱形凸台BP表现出完整的菱形形貌。
由以上内容可知，在全透光区与半透光区之间距离5μm以上时，二者之间的相互影响很小。因此，在本公开实施例提供的上述显示基板中，如图3和图4所示，平台结构1023远离过孔h一侧的外表面与过孔h之间的最小距 离s 1可以大于等于5μm。可选地，在实际产品的分辨率较大、像素尺寸较小的情况下，可设置平台结构1023远离过孔h一侧的外表面与过孔h之间的最小距离s 1等于5μm；在实际产品的分辨率较小、像素尺寸较大的情况下，可设置平台结构1023远离过孔h一侧的外表面与过孔h之间的最小距离s 1大于5μm且小于像素尺寸。在一些实施例中，还可以通过使用低感的有机材料搭配精度更高的曝光机来减小全透光区和半透光区之间的相互影响，未来有望可将全透光区和半透光区之间的过渡区取消。
继续参见图3和图4可知，过孔h为在有机层102远离衬底基板101的方向Z上孔径逐渐增大的过孔，平台结构1023为在有机层102远离衬底基板101的方向Z上尺寸逐渐减小的平台，在本公开中，平台结构1023远离过孔h一侧的外表面与过孔h之间的最小距离s 1可以理解为过孔h中最大孔径的顶部端口到平台结构1023中最小尺寸的顶部的外表面之间的距离。
由于半透过率掩膜板包括全透光区、半透光区与不透光区三种区域，因此，位于全透光区与半透光区之间的区域为不透光区，基于此，在本公开实施例提供的上述显示基板中，平台结构1023可采用不透光区形成。另外，本公开中相对于平坦层1021凸出设置的支撑结构1022也是采用不透光区形成的。在有机层102远离衬底基板101的方向Z上，均由不透光区形成的平台结构1023和支撑结构1022二者的厚度可以大致相同。本公开中“大致相同”可以理解为相同或在因制作、测量等因素造成的合理误差(例如±5％)范围内。
在一些实施例中，在本公开实施例提供的上述显示基板中，在有机层102远离衬底基板101的方向Z上，平台结构1023的厚度可以大于等于0.5μm且小于等于1.2μm，例如平台结构1023的厚度可以为0.5μm、0.6μm、0.7μm、0.8μm、0.9μm、1μm、1.1μm、1.2μm等。平台结构1023的厚度越大，所形成的支撑结构102形状越稳定，对过孔h的保护效果越好，但较大厚度的平台结构1023会增加工艺难度，因此，在综合考虑支撑效果与制作工艺的情况下，本公开中设置平台结构1023的厚度在0.5μm到1.2μm之间。且由于平台结构1023的厚度和支撑结构1022的厚度大致相同，因此支撑结构1022的厚度也 可以在0.5μm到1.2μm之间，在此厚度范围内的支撑结构1022可以稳定支撑隔垫物(PS)。
需要说明的是，半透光区的透过率越高，相同剂量(Dose)光照下，不透光区所形成的支撑结构1022及其遮挡的平坦层1021、与半透光区形成的平坦层1022之间形成的段差(相当于支撑结构1022的厚度)越高。但是如果半透光区的透过率太小，为了达成相应段差(相当于支撑结构1022的厚度)，则需要更大剂量(Dose)的光照，大剂量(Dose)的光照易使得全透光区形成的过孔h过大；相反，半透光区的透过率太大，为了达成所需段差(相当于支撑结构1022的厚度)，则需采用很小剂量(Dose)的光照，小剂量(Dose)的光照易使得全透光区形成的过孔h过小，甚至可能不会形成完全贯穿有机层102的过孔h。因此，为在满足相应段差(相当于支撑结构1022的厚度)的同时，保证所制作的过孔h大小适宜，本公开中可以设置半透光区的透过率大于等于15％且小于等于35％，例如半透光区的透过率为15％、20％、25％、30％、35％等。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2至图4、图7和图16所示，还可以包括位于有机层102与衬底基板101之间且沿第一方向X延伸、沿第二方向Y排布的多条栅线107，第一方向X与第二方向Y交叉设置；在有机层102远离衬底基板101的方向Z上，支撑结构1022的尺寸逐渐减小，支撑结构1022包括远离衬底基板101一侧的顶端，顶端在第一方向X上的宽度w大于等于6μm且小于等于12μm，例如支撑结构1022的顶端宽度w为6μm、7μm、8μm、9μm、10μm、11μm、12μm等。支撑结构1022的顶端宽度w的最小需求为6μm才能与隔垫物(PS)更好地匹配，达成支撑力的最低要求；为更稳定地支撑隔垫物(PS)，支撑结构1022的顶端宽度w可以做的较大(例如12μm)。但是在考虑到像素透过率(也可以称为像素开口率)及支撑结构1022的图案(Pattern)设计限制的情况下，本公开中支撑结构1022的顶端宽度w不宜过大，可选地，支撑结构1022的顶端宽度w为10μm，既可以较好地满足支撑力要求，又可以避免影响像素透过率。
在一些实施例中，在本公开实施例提供地上述显示基板中，为防止支撑结构1022与隔垫物(PS)搭接不良，以保证支撑结构1022稳定支撑隔垫物(PS)，如图10所示，可以设置支撑结构1022在第二方向Y上的长度l大于等于25μm且小于等于50μm，例如支撑结构1022在第二方向Y上的长度l为25μm、30μm、35μm、40μm、45μm、50μm等。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图3、图4和图16所示，支撑结构1022的坡度角α大于等于30°且小于等于60°，例如支撑结构1022的坡度角α为30°、35°、40°、45°、50°、55°、60°等，以使得支撑结构1022的侧面坡度较平缓，保证后续制作的公共电极104、无机绝缘层108、像素电极105在支撑结构1022处的镀膜无裂纹(Crack)不良和剥离(Peeling)风险。图16所示支撑结构1022的顶端宽度w约6.5μm，支撑结构1022的底端宽度约为8μm，支撑结构1022的厚度约为1μm，支撑结构1022的坡度角α约35°，利于保证后续制作的公共电极104、无机绝缘层108、像素电极105在支撑结构1022处的镀膜良好，无不良发生。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图3、图4和图17所示，平坦层1021在过孔h处的坡度角β大于等于50°且小于等于60°，例如平坦层1021在过孔h处的坡度角β为50°、51°、52°、53°、54°、55°、56°、57°、58°、59°、60°等。平坦层1021在过孔h处的坡度角β在此角度范围内，既可使得过孔h的顶部端口孔径较小，保证过孔h与相关膜层之间的工艺极限(Margin)，又可以保证像素电极105或公共电极104在过孔h内的良好搭接。结合图17可见，平坦层1021在过孔h处的坡度角β约为55°，且受平台结构1023的保护，过孔h的形貌较好。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图3、图4和图17所示，在有机层102远离衬底基板101的方向Z上，过孔h的孔径逐渐增大，过孔h包括靠近衬底基板101的底部端口，该底部端口的孔径D大于等于4μm且小于等于7μm，例如过孔h的底部端口孔径D为4μm、5μm、6μm、7μm等。平坦层1021在过孔h处的坡度角β大于等于50°且小于等于 60°的一些情况下，为形成形貌完好的过孔h，需保证过孔h的底部端口比顶部端口单边小1.4-2μm，例如1.7μm左右，双边即3.4μm，因此，过孔h的底部端口的孔径D需保证大于4μm。本公开中设置过孔h的底部端口的孔径D大于等于4μm且小于等于7μm，可以保证过孔h的形貌较好，如图17所示。
在一些实施例中，在本公开实施例提供的上述显示基板中，平坦层1021在有机层102远离衬底基板101的方向Z上的厚度可以大于2μm，例如平坦层1021在有机层102远离衬底基板101的方向Z上的厚度约为2.5μm，以使得平坦层1021可以很好地起到平坦下方膜层、并防止平坦层1021的下方导电膜层(例如晶体管103的源漏金属层)与平坦层1021的上方导电膜层(例如公共电极104所在层)之间产生寄生电容的作用。
在一些实施例中，在本公开实施例提供的上述显示基板中，有机层102远离衬底基板101一侧的表面可以凹凸不平，即有机层102远离衬底基板101一侧的表面较粗糙，从而增加有机层102与公共电极104之间的接触面积，进而提高有机层102与公共电极104之间的粘附力，防止公共电极104所在膜层发生剥离(Peeling)不良。可选地，通过对有机层102远离衬底基板101一侧的表面进行离子轰击(Descum)，使得有机层102远离衬底基板101一侧的表面变得凹凸不平。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2、图3和图10所示，多个晶体管103位于有机层102与衬底基板101之间，多个像素电极105位于有机层102远离衬底基板101的一侧；多个过孔h包括多个第一过孔h 1，第一过孔h 1连接晶体管103的第一极1031与像素电极105；多个平台结构1023包括多个第一平台结构10231，第一平台结构10231被第一过孔h 1贯穿，以通过第一平台结构10231的保护形成形貌较好的第一过孔h 1。可选地，图10、图18至图20所示，部分第一平台结构10231与各支撑结构1022一体设置。因为第一过孔h 1是有一定坡度的，支撑结构1022若落在第一过孔h 1的斜坡上，将导致支撑结构1022失去支撑作用；因此，在一些实施例中，第一过孔h 1的顶部端口比底部端口单边要大约1μm，为了保证工艺极 限(Margin)，第一过孔h 1的顶部端口到支撑结构1022底端之间的距离s 3应大于等于2μm。并且考虑到第一平台结构10231环绕第一过孔h 1设置，因此，在本公开中若第一平台结构10231与支撑结构1022之间的最小距离s 2(由于第一平台结构10231和支撑结构1022均为在有机层102远离衬底基板101的方向Z上尺寸逐渐减小的平台，因此，第一平台结构10231与支撑结构1022之间的最小距离s 2可理解为第一平台结构10231的底端与支撑结构1022的底端之间的距离)非常小(例如小于2μm)，则可将第一平台结构10231与支撑结构1022连接起来，使得第一平台结构10231与支撑结构1022合二为一；这样设置还可以防止用于形成第一平台结构10231的不透光区与用于形成支撑结构1022的不透光区之间预夹极小的半透光区，造成该半透光区对应形成的平坦层1021的形貌异常。
当然，在一些实施例中，可根据实际像素设计来决定第一平台结构10231是否与支撑结构1022合为一处，因为在用于形成第一过孔h 1的全透光区与用于形成平坦层1021的半透光区之间的距离(可以相当于第一平台结构10231远离第一过孔h 1一侧的外表面与第一过孔h 1之间的最小距离s 1)大于5μm的情况下，第一平台结构10231的存在可以满足第一过孔h 1的顶部端口到支撑结构1022之间的最小距离s 3(由于第一过孔h 1为在有机层102远离衬底基板101的方向Z上孔径逐渐增大的过孔，支撑结构1022为在有机层102远离衬底基板101的方向Z上尺寸逐渐减小的平台，因此，第一过孔h 1的顶部端口到支撑结构1022之间的最小距离s 3可理解为第一过孔h 1的顶部端口与支撑结构1022的底端之间的距离)大于等于2μm的条件，所以是否将第一平台结构10231与支撑结构1022合为一处，在设计和工艺上都是没有问题的，可根据实际像素设计来决定，在满足全透光区与半透光区互不影响的条件下，第一平台结构10231与支撑结构1022是否合为一处均在本公开范围内。
支撑结构1022与第一平台结构10231可分开设置，或者在一些实施例中，针对一体设置的支撑结构1022与第一平台结构10231，如图10所示，第一平台结构10231与支撑结构1022可以直接相连，或者，如图18至图20所示， 第一平台结构10231与支撑结构1022可以通过第一连接部Lk 1相连。可选地，如图18所示，可以直接将第一平台结构10231的a边延长至与支撑结构1022接触，来形成第一连接部LK 1；或者，如图19所示，可以直接将第一平台结构10231的b边延长至与支撑结构1022接触，来形成第一连接部LK 1；或者，如图20所示，可以直接将第一平台结构10231的c边两个顶点连接至支撑结构1022，来形成第一连接部LK 1。考虑到图18所示第一连接部LK 1有尖角，液晶在此可能会有排列和流动问题，图20所示第一连接部LK 1的宽度较小，因此为避免影响液晶排列和流动，并保证工艺稳定性，在具体实施时，可采用图19所示的第一连接部LK 1。需要说明的是，图10、图18至图20均以第一平台结构10231为八边形平台为例进行示意，在本公开中第一平台结构10231还可以为四边形平台、六边形平台等多边形平台，在一些实施例中，受曝光精度等因素的影响，第一平台结构10231、支撑结构1022以及第一连接部LK 1的棱角处不会那么尖锐而是会形成弧角，因此，第一平台结构10231支撑结构1022以及第一连接部LK 1还可以包括圆弧段。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图2、图4图9和图10所示，公共电极104位于多个像素电极105所在层与有机层102之间的，转接电极106可以与晶体管103的第一极1031同层、同材料设置；多个过孔h还包括多个第二过孔h 2，第二过孔h 2连接公共电极104与转接电极106；多个平台结构1023包括多个第二平台结构10232，第二平台结构10232被第二过孔h 2贯穿，以通过第二平台结构10232的保护形成形貌较好的第二过孔h 2。可选地，各第二平台结构10232与部分第一平台结构10231一体设置，且第二平台结构10232、支撑结构1022分别与不同的第一平台结构10231一体设置，可选地，在与第二平台结构10232一体设置的第一平台结构10231、以及与支撑结构1022一体设置的第一平台结构10231之间具有一个独立设置的第一平台结构10231。在本公开中若第一平台结构10231与第二平台结构10232之间的距离非常小(例如小于2μm)，可将第一平台结构10231与第二平台结构10232连接起来，使得第一平台结构10231与第二平台结构10232 合二为一，这样可以防止用于形成第一平台结构10231的不透光区与用于形成第二平台结构10232的不透光区之间预夹极小的半透光区，造成该半透光区对应形成的平坦层1021的形貌异常。
第一平台结构10231与第二平台结构10232可分开单独设置，或者在一些实施例中，针对一体设置的第一平台结构10231与第二平台结构10232，如图10所示，第二平台结构10232与第一平台结构10231可以直接相连，或者，如图21至图23所示，第一平台结构10231与第二平台结构10232在第一方向和/或者第二方向上具有一定距离。第二平台结构10232与第一平台结构10231可以通过第二连接部Lk 2相连。可选地，如图21所示，第一平台结构10231与第二平台结构10232在第一方向和第二方向上均具有一定距离，可选的，贯穿第一平台结构10231与第二平台结构10232的第一过孔h1与第二过孔h2的中心可在第一方向和第二方向错开，可以直接将第一平台结构10231的d边延长至与第二平台结构10232接触，并将第二平台结构10232的e边延长至与第一平台结构10231接触，来形成第二连接部LK 2；或者贯穿第一平台结构10231与第二平台结构10232的第一过孔h1与第二过孔h2的中心连线沿第一/第二方向或者第三方向，其中第三方向不同于第一方向和第二方向如图22所示，可以直接从第一平台结构10231的f边的两个顶点与第二平台结构10232连接，来形成第二连接部LK 2；或者，如图23所示，可以直接将第二平台结构10232的g边两个顶点连接至第一平台结构10231，来形成第二连接部LK 2。需要说明的是，图10、图21至图23均以第二平台结构10232为八边形平台为例进行示意，在本公开中第二平台结构10232还可以为四边形平台、六边形平台等多边形平台，在一些实施例中，受曝光精度等因素的影响，第二平台结构10232的棱角处可能不会那么尖锐而是会形成圆弧角，因此，第二平台结构10232还可以包括圆弧段。
需要说明的是，在本公开中，“同层、同材料”指的是采用同一成膜工艺形成用于制作特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。即一次构图工艺对应一道掩模板(mask，也称光罩)。根据特定图形 的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而所形成层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形可能处于相同的高度或者具有相同的厚度、也可能处于不同的高度或者具有不同的厚度。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图4、图7至图9所示，还可以包括与栅线107同层、同材料设置的公共电极线109，公共电极线109通过贯穿层间介质层110的第三过孔h 3与转接电极106电连接，进而通过转接电极106为公共电极104提供信号；并且，公共电极线109的存在还可以有效降低公共电极104的整体电阻，利于保持公共电极104上的信号均一性。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图3和图4所示，晶体管103除了具有第一极1031之外，还可以包括第二极1032、栅极1033和有源层1034，其中，第一极1031可以为源极、第二极1032可以为漏极，或者，第一极1031可以为漏极、第二极1032可以为源极。第一极1031、第二极1032和栅极1033的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti)；有源层1034的材料可以包括非晶硅、多晶硅或氧化物半导体(例如，氧化锢稼锌)。可选地，晶体管103可以为底栅型晶体管、顶栅型晶体管、双栅型晶体管等。在一些实施例中，晶体管103可以为P型晶体管或N型晶体管，其中，P型晶体管在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系式V gs<V th时导通，在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系式V gs≥V th时截止；N型晶体管在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系式V gs＞V th时导通，在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系式V gs≤V th时截止。
参见图3、图4、图8和图9可见，第一极1031可以通过贯穿层间介质层110和栅绝缘层111的第四过孔h 4与有源层1034电连接，第二极1032可以通过贯穿层间介质层110和栅绝缘层111的第五过孔h 5与有源层1034电连 接；在具体实施时，可在涂覆层间介质层110的材料和栅绝缘层111的材料之后，采用一次构图工艺，同时形成贯穿层间介质层110和栅绝缘层111的第四过孔h 4和第五过孔h 5，以避免分别对层间介质层110和栅绝缘层111进行构图形成过孔。
另外，如图6所示，有源层1034的形状可近似为U型；如图7所示，栅线107与有源层1034交叠的部分可作为栅极1033，本公开中栅线107与有源层1034具有两个交叠部分，使得晶体管103具有两个栅极，形成了双栅晶体管；当然，在一些实施例中，有源层1034的形状也可以可近似为I型，对应的晶体管103可以为单栅晶体管。如图9所示，可将数据线112中与有源层1034的一个端部交叠的部分作为第二极1032，且为了便于第二极1032搭接有源层1034，可以将数据线112中作为第二极1032的部分加宽设置。
在一些实施例中，如图3至图5所示，为了避免光线影响有源层1034而导致晶体管103出现漏电流，本公开中还可以在有源层1034的下方设置遮光层113，在一些实施例中，为提高显示基板的透过率，遮光层113仅遮挡有源层1034的沟道区(相当于栅极1033所在区)，示例性的，遮光层113遮挡有源层1034的沟道区且在第一方向X上相较于有源层1034的沟道区(相当于栅极1033所在区)单边延伸出1μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图13所示，像素电极105可以为狭缝电极，公共电极104为面状电极。可选地，如图11和图12所示，公共电极104在对应第一过孔h 1的位置具有镂空结构k，无机绝缘层108在对应第一过孔h 1的位置具有第六过孔h 6，以使得像素电极105通过贯穿设置的第六过孔h 6、镂空结构k和第一过孔h 1与晶体管103的第一极1031电连接。在一些实施例中，像素电极105的材料、以及公共电极104的材料分别可以为氧化铟锡(ITO)、氧化铟锌(IZO)等透明导电材料。
在一些实施例中，在本公开实施例提供的上述显示基板中，还可以包括本领域的普通技术人员应该理解具有的其它的组成部分(例如位于像素电极105远离衬底基板101一侧的取向层)，在此不做赘述，也不应作为对本公开 的限制。
基于同一发明构思，本公开实施例还提供了一种上述显示基板的制作方法。由于该制作方法解决问题的原理与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该制作方法的实施可以参见上述显示基板的实施，重复之处不再赘述。
基板的制作方法，如图24所示，可以包括以下步骤：
S2401、提供一衬底基板；
S2402、采用半透过率掩膜板在衬底基板上形成有机层，有机层包括平坦层和多个支撑结构，其中，平坦层包括多个过孔，支撑结构位于平坦层远离衬底基板的一侧且与平坦层一体设置，支撑结构在衬底基板上的正投影与过孔在衬底基板上的正投影互不交叠。
在一些实施例中，在本公开实施例提供的上述制作方法中，上述步骤S2402、采用半透过率掩膜板在衬底基板上形成有机层，具体可以通过以下方式进行实现：
如图25和图26所示，采用半透过率掩膜板的不透光区NA形成多个支撑结构1022、被支撑结构1022遮挡的第一平坦部10211、多个平台结构1023、以及被平台结构1023遮挡的第二平坦部10212；采用半透过率掩膜板的半透光区HA形成未被支撑结构1022和平台结构1023遮挡的第三平坦部10213；采用半透过率掩膜板的全透光区FA形成贯穿平台结构1023和第二平坦部10212的多个过孔h，有机层102的平坦层1021包括第一平坦部10211、第二平坦部10212和第三平坦部10213。可选地，半透过率掩膜板的半透光区的透过率大于等于15％且小于等于35％。
需要说明的是，在本公开实施例提供的上述制作方法中，形成各层结构涉及到的构图工艺，不仅可以包括沉积、光刻胶涂覆、掩模板掩模、曝光、显影、刻蚀、光刻胶剥离等部分或全部的工艺过程，还可以包括其他工艺过程，具体以实际制作过程中形成所需构图的图形为准，在此不做限定。例如，在显影之后和刻蚀之前还可以包括后烘工艺。其中，沉积工艺可以为化学气 相沉积法、等离子体增强化学气相沉积法或物理气相沉积法，在此不做限定。
基于同一发明构思，本公开实施例还提供了一种显示面板，如图27和图28所示，包括相对而置的显示基板001和对向基板002，以及位于显示基板001与对向基板002之间的液晶层003，其中，显示基板001为本公开实施例提供的上述显示基板001。由于该显示面板解决问题的原理与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该显示面板的实施可以参见上述显示基板的实施，重复之处不再赘述。
在一些实施例中，在本公开实施例提供的上述显示面板中，如图29所示，对向基板002包括黑矩阵201，平台结构1023(可以包括第一平台结构10231和第二平台结构10232)在衬底基板101上的正投影位于黑矩阵201在衬底基板101上的正投影内，以通过黑矩阵BM遮挡平台结构1023，防止平台结构1023处漏光。
可选地，如图27和图28所示，对向基板002还可以包括衬底202、色阻(图中未示出)等。可选地，黑矩阵201为网格状结构，色阻可以位于网格状结构的网格内，像素电极105在衬底基板101上的正投影位于色阻在衬底基板101上的正投影内，色阻可以包括红光色阻、绿光色阻、蓝光色阻等。在一些实施例中，在本公开实施例提供的上述对向基板002中，还可以包括本领域的普通技术人员应该理解具有的其它的组成部分(例如位于黑矩阵201所在层面向液晶层003一侧的取向层)，在此不做赘述，也不应作为对本公开的限制。
在一些实施例中，本公开实施例提供的上述显示面板还可以包括位于显示基板001与对向基板002之间且包围液晶层003的封框胶，位于显示基板001远离对向基板002一侧的第一偏光片，以及位于对向基板002远离显示基板001一侧的第二偏光片等，其中，第一偏光片的透光轴与第二片偏光片的透光轴相互垂直。另外，对于本领域的普通技术人员应该理解具有的其它的组成部分，在此不做赘述，也不应作为对本公开的限制。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括背光模 组、以及位于背光模组出光侧的显示面板，其中，显示面板为本公开实施例提供的上述显示面板。由于该显示装置解决问题的原理与上述显示面板解决问题的原理相似，因此，本公开实施例提供的该显示装置的实施可以参见上述显示面板的实施，重复之处不再赘述。
在一些实施例中，本公开实施例提供的上述背光模组可以为直下式背光模组，也可以为侧入式背光模组。可选地，侧入式背光模组可以包括灯条、层叠设置的反射片、导光板、扩散片、棱镜组等，灯条位于导光板厚度方向的一侧。直下式背光模组可以包括矩阵光源、在矩阵光源出光侧层叠设置的反射片、扩散板和增亮膜等，反射片包括与矩阵光源中各灯珠的位置正对设置的开孔。灯条中的灯珠、矩阵光源中的灯珠可以为发光二极管(LED)，例如微型发光二极管(Mini LED、Micro LED等)。
亚毫米量级甚至微米量级的微型发光二极管和有机发光二极管(OLED)一样属于自发光器件。其与有机发光二极管一样，有着高亮度、超低延迟、超大可视角度等一系列优势。并且由于无机发光二极管发光是基于性质更加稳定、电阻更低的金属半导体实现发光，因此它相比基于有机物实现发光的有机发光二极管来说，有着功耗更低、更耐高温和低温、使用寿命更长的优势。且在微型发光二极管作为背光源时，能够实现更精密的动态背光效果，在有效提高屏幕亮度和对比度的同时，还能解决传统动态背光在屏幕亮暗区之间造成的眩光现象，优化视觉体验。
可选地，本公开实施例提供地上述显示装置可适用于中大尺寸的车载显示产品(如图30所示)、触控屏(TPC，如图31所示)、显示器(MNT，如图32所示)，这主要是因为，首先小尺寸的应用场景没有大的弯曲、震动，不需要采用本公开的方案来保证显示基板001和对向基板002可以有大的滑动而不受影响；其次，小尺寸追求高分辨率(PPI)，没有充足的空间来满足本公开的方案。具体的，在图30中具体示出了车载显示产品中将本公开的显示装置集成在方向盘SS的中央区域，且在图30中示出了显示装置的显示区AA、以及承载方向盘SS的箱体BX，箱体BX内部可设置有电源、控制电路、 散热器等部件，在此不做限定；在一些实施例中，本公开的显示装置还可以独立于方向盘SS设置，例如可以为设置在方向盘SS附近的中控大屏、或为设置在车子顶部的大屏车顶天窗、或可以利用显示装置作为车窗使用，在此不做限定。在图31中示出了触控屏的返回键H(即Home键)、显示区AA和摄像头C。图32示出了显示器的显示区AA和底座B。对于在大尺寸的车载显示产品、触控屏、显示器中，对于本领域的普通技术人员应该理解具有的其它的组成部分，在此不做赘述，也不应作为对本公开的限制。
在一些实施例中，在本公开实施例提供的上述显示装置中，还可以包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、显示单元、用户输入单元、接口单元以及控制芯片等部件。可选地，控制芯片为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。另外，本领域技术人员可以理解的是，上述结构并不构成对本公开实施例提供的上述显示装置的限定，换言之，在本公开实施例提供的上述显示装置中可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (23)

  1. 一种显示基板，其中，包括：
    衬底基板；
    有机层，位于所述衬底基板的一侧，所述有机层包括平坦层和多个支撑结构，其中，所述平坦层包括多个过孔，所述支撑结构位于所述平坦层远离所述衬底基板的一侧且与所述平坦层一体设置，所述支撑结构在所述衬底基板上的正投影与所述过孔在所述衬底基板上的正投影互不交叠。
  2. 如权利要求1所述的显示基板，其中，所述有机层还包括位于所述平坦层远离所述衬底基板一侧且与所述平坦层一体设置的多个平台结构，所述过孔延伸至贯穿所述平台结构。
  3. 如权利要求2所述的显示基板，其中，所述平台结构远离所述过孔一侧的外表面与所述过孔之间的最小距离大于等于5μm。
  4. 如权利要求2或3所述的显示基板，其中，还包括位于所述有机层与所述衬底基板之间的多个晶体管，以及位于所述有机层远离所述衬底基板一侧的多个像素电极；
    所述多个过孔包括多个第一过孔，所述第一过孔连接所述晶体管的第一极与所述像素电极；
    所述多个平台结构包括多个第一平台结构，所述第一平台结构被所述第一过孔贯穿。
  5. 如权利要求4所述的显示基板，其中，部分所述第一平台结构与各所述支撑结构一体设置。
  6. 如权利要求5所述的显示基板，其中，所述第一平台结构与所述支撑结构之间的最小距离小于2μm。
  7. 如权利要求2所述的显示基板，其中，在所述有机层远离所述衬底基板的方向上，所述过孔的孔径逐渐增大，所述第一过孔的顶部端口到所述支撑结构之间的最小距离大于等于2μm。
  8. 如权利要求5～7任一项所述的显示基板，其中，还包括多个第一连接部，所述第一连接部连接所述支撑结构与所述第一平台结构。
  9. 如权利要求4所述的显示基板，其中，还包括位于所述多个像素电极所在层与所述有机层之间的公共电极，以及与所述晶体管的第一极同层、同材料的多个转接电极；
    所述多个过孔还包括多个第二过孔，所述第二过孔连接所述公共电极与所述转接电极；
    所述多个平台结构包括多个第二平台结构，所述第二平台结构被所述第二过孔贯穿。
  10. 如权利要求9所述的显示基板，其中，各所述第二平台结构与部分所述第一平台结构一体设置，且所述第二平台结构、所述支撑结构分别与不同的所述第一平台结构一体设置。
  11. 如权利要求10所述的显示基板，其中，还包括多个第二连接部，所述第二连接部连接所述第二平台结构与所述第一平台结构。
  12. 如权利要求2～11任一项所述的显示基板，其中，在所述有机层远离所述衬底基板的方向上，所述平台结构的厚度与所述支撑结构的厚度大致相同。
  13. 如权利要求1～12任一项所述的显示基板，其中，所述有机层远离所述衬底基板一侧的表面凹凸不平。
  14. 如权利要求1～13任一项所述的显示基板，其中，还包括位于所述有机层与所述衬底基板之间且沿第一方向延伸、沿第二方向排布的多条栅线，所述第一方向与所述第二方向交叉设置；
    在所述有机层远离所述衬底基板的方向上，所述支撑结构的尺寸逐渐减小，所述支撑结构包括远离所述衬底基板一侧的顶端，所述顶端在所述第一方向上的宽度大于等于6μm且小于等于12μm；所述支撑结构在所述第二方向上的长度大于等于25μm且小于等于50μm。
  15. 如权利要求1～14任一项所述的显示基板，其中，所述支撑结构的坡 度角大于等于30°且小于等于60°。
  16. 如权利要求1～15任一项所述的显示基板，其中，所述平坦层在所述有机层远离所述衬底基板的方向上的厚度大于2μm。
  17. 如权利要求1～16任一项所述的显示基板，其中，在所述有机层远离所述衬底基板的方向上，所述平台结构的厚度大于等于0.5μm且小于等于1.2μm。
  18. 一种如权利要求1～17任一项所述的显示基板的制作方法，其中，包括：
    提供一衬底基板；
    采用半透过率掩膜板在所述衬底基板上形成有机层，所述有机层包括平坦层和多个支撑结构，其中，所述平坦层包括多个过孔，所述支撑结构位于所述平坦层远离所述衬底基板的一侧且与所述平坦层一体设置，所述支撑结构在所述衬底基板上的正投影与所述过孔在所述衬底基板上的正投影互不交叠。
  19. 如权利要求18所述的制作方法，其中，采用半透过率掩膜板在所述衬底基板上形成有机层，具体包括：
    采用所述半透过率掩膜板的不透光区形成多个支撑结构、被所述支撑结构遮挡的第一平坦部、多个平台结构、以及被所述平台结构遮挡的第二平坦部；采用所述半透过率掩膜板的半透光区形成未被所述支撑结构和所述平台结构遮挡的第三平坦部；采用所述半透过率掩膜板的全透光区形成贯穿所述平台结构和所述第二平坦部的多个过孔，所述有机层的平坦层包括所述第一平坦部、所述第二平坦部和所述第三平坦部。
  20. 如权利要求18或19所述的制作方法，其中，所述半透过率掩膜板的半透光区的透过率大于等于15％且小于等于35％。
  21. 一种显示面板，其中，包括相对而置的显示基板和对向基板，以及位于所述显示基板与所述对向基板之间的液晶层，其中，所述显示基板为如权利要求1～17任一项所述的显示基板。
  22. 如权利要求21所述的显示面板，其中，所述对向基板包括黑矩阵，所述平台在所述衬底基板上的正投影位于所述黑矩阵在所述衬底基板上的正投影内。
  23. 一种显示装置，其中，包括背光模组、以及位于所述背光模组出光侧的显示面板，其中，所述显示面板为如权利要求21或22所述的显示面板。
PCT/CN2022/128391 2022-10-28 2022-10-28 显示基板、其制作方法、显示面板及显示装置 WO2024087210A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2022/128391 WO2024087210A1 (zh) 2022-10-28 2022-10-28 显示基板、其制作方法、显示面板及显示装置
CN202280003876.4A CN118265946A (zh) 2022-10-28 2022-10-28 显示基板、其制作方法、显示面板及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/128391 WO2024087210A1 (zh) 2022-10-28 2022-10-28 显示基板、其制作方法、显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2024087210A1 true WO2024087210A1 (zh) 2024-05-02

Family

ID=90829784

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/128391 WO2024087210A1 (zh) 2022-10-28 2022-10-28 显示基板、其制作方法、显示面板及显示装置

Country Status (2)

Country Link
CN (1) CN118265946A (zh)
WO (1) WO2024087210A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006201218A (ja) * 2005-01-18 2006-08-03 Seiko Epson Corp 電気光学装置、電気光学装置の製造方法、及び電子機器
KR20080079141A (ko) * 2007-02-26 2008-08-29 엘지디스플레이 주식회사 이중 컬럼스페이서구조의 액정표시소자 및 그 제조방법
CN101789426A (zh) * 2009-01-26 2010-07-28 Nec液晶技术株式会社 薄膜晶体管阵列基板及其制造方法、和液晶显示装置
KR20150076348A (ko) * 2013-12-26 2015-07-07 엘지디스플레이 주식회사 액정표시패널
CN114236926A (zh) * 2021-12-20 2022-03-25 绵阳惠科光电科技有限公司 阵列基板及显示面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006201218A (ja) * 2005-01-18 2006-08-03 Seiko Epson Corp 電気光学装置、電気光学装置の製造方法、及び電子機器
KR20080079141A (ko) * 2007-02-26 2008-08-29 엘지디스플레이 주식회사 이중 컬럼스페이서구조의 액정표시소자 및 그 제조방법
CN101789426A (zh) * 2009-01-26 2010-07-28 Nec液晶技术株式会社 薄膜晶体管阵列基板及其制造方法、和液晶显示装置
KR20150076348A (ko) * 2013-12-26 2015-07-07 엘지디스플레이 주식회사 액정표시패널
CN114236926A (zh) * 2021-12-20 2022-03-25 绵阳惠科光电科技有限公司 阵列基板及显示面板

Also Published As

Publication number Publication date
CN118265946A (zh) 2024-06-28

Similar Documents

Publication Publication Date Title
US9823522B2 (en) COA type liquid crystal display panel and method for manufacturing the same
US9933667B2 (en) Liquid crystal panel and manufacture method thereof
WO2020206721A1 (zh) 显示面板及制作方法、显示模组
WO2020133714A1 (zh) 显示面板及显示模组、电子装置
US20240250176A1 (en) Array substrate, display device and fabrication method
WO2014190727A1 (zh) 阵列基板及其制造方法、显示装置
US9070599B2 (en) Array substrate, manufacturing method thereof and display device
US20170139293A1 (en) Liquid crystal panel and array substrate
US20220199959A1 (en) Display panel and formation method thereof, and display apparatus
US8178262B2 (en) Method for fabricating color filter layer
WO2021196362A1 (zh) 低温多晶硅显示面板及其制作方法、液晶显示装置
US20190219853A1 (en) Coa substrate, manufacturing method therefor, display panel, and display device
CN107870490B (zh) 显示装置
WO2019041482A1 (zh) 显示面板及其制造方法
WO2024017343A1 (zh) 显示面板及其制作方法、显示装置
US20240049551A1 (en) Display panel
US20220384766A1 (en) Display panel and display device
US10503034B2 (en) Manufacturing method of a TFT substrate and structure
US11567379B2 (en) Display panel and display device
WO2024087210A1 (zh) 显示基板、其制作方法、显示面板及显示装置
US10483497B2 (en) OLED substrate and manufacturing method thereof and display device
US11887990B2 (en) Method for manufacturing array substrate
KR101408257B1 (ko) 액정표시장치 및 그 제조방법
WO2020155469A1 (zh) 显示面板及其制作方法
US20240361652A1 (en) Display panel and manufacturing method thereof, and electronic device

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202280003876.4

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22963191

Country of ref document: EP

Kind code of ref document: A1