WO2024087180A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024087180A1
WO2024087180A1 PCT/CN2022/128320 CN2022128320W WO2024087180A1 WO 2024087180 A1 WO2024087180 A1 WO 2024087180A1 CN 2022128320 W CN2022128320 W CN 2022128320W WO 2024087180 A1 WO2024087180 A1 WO 2024087180A1
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WO
WIPO (PCT)
Prior art keywords
edge
outer ring
routing
area
display panel
Prior art date
Application number
PCT/CN2022/128320
Other languages
English (en)
French (fr)
Inventor
陈天赐
马宏伟
罗昶
张毅
王思雨
文平
王威
王裕
代俊秀
曾扬
魏立恒
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/128320 priority Critical patent/WO2024087180A1/zh
Publication of WO2024087180A1 publication Critical patent/WO2024087180A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • This article relates to but is not limited to the field of display technology, and in particular to a display panel and a display device.
  • touch technology provides a new human-computer interaction interface, which is more direct and user-friendly.
  • Touch technology is integrated with flat display technology to form a display touch device, which can make the flat display device have a touch function.
  • Embodiments of the present disclosure provide a display panel and a display device.
  • this embodiment provides a display panel, comprising: an effective area and an edge area located on at least one side of the effective area, the edge area comprising an antenna projection area and a non-antenna projection area located on at least one side of the antenna projection area.
  • the effective area comprises: a substrate, and a display structure layer and a touch structure layer sequentially arranged on the substrate.
  • the edge area comprises: an isolation dam and an edge grounding trace arranged on the substrate. The edge grounding trace is located on a side of the isolation dam away from the effective area. The overlapping area of the edge grounding trace and the antenna projection area is smaller than the overlapping area of the edge grounding trace and the non-antenna projection area.
  • the overlapping area of the edge ground trace and the antenna projection area accounts for less than or equal to 7% of the antenna projection area.
  • a portion of the edge grounding trace located in the antenna projection area close to the effective area is a first trace
  • a portion of the edge grounding trace located in the non-antenna projection area close to the effective area is a second trace.
  • a distance between an edge of the first trace close to the effective area and an edge of the substrate is greater than a distance between an edge of the second trace close to the effective area and an edge of the substrate.
  • the edge grounding routing includes: an outer ring routing, an inner ring routing, and a plurality of first connecting routings; the plurality of first connecting routings connect the inner ring routing and the outer ring routing; the outer ring routing is located on a side of the inner ring routing away from the effective area; the plurality of first connecting routings are located in the non-antenna projection area.
  • the inner ring routing includes: at least two inner ring routing segments and an inner ring connecting segment connecting adjacent inner ring routing segments; the distance between the inner ring connecting segment and the edge of the substrate is greater than the distance between the inner ring routing segment and the edge of the substrate.
  • the inner loop routing does not overlap with the antenna projection area, and an inner loop connecting section of the inner loop routing is located on a side of the antenna projection area close to the effective area.
  • the inner ring wiring is provided with a plurality of first openings, and the plurality of first openings are arranged in at least one row along a direction from the effective area toward the edge area.
  • the outer ring routing does not overlap with the antenna projection area, and the outer ring routing includes at least: two outer ring routing segments located in the non-antenna projection area.
  • the outer ring routing includes: at least two outer ring routing segments and an outer ring connecting segment connecting adjacent outer ring routing segments; the at least two outer ring routing segments are located in the non-antenna projection area; and the distance between the outer ring connecting segment and the edge of the substrate is greater than the distance between the outer ring routing segment and the edge of the substrate.
  • the width of the outer ring connecting segment of the outer ring routing is smaller than the width of the outer ring routing segment.
  • the width of the outer ring connecting segment of the outer ring routing is substantially the same as the width of the inner ring connecting segment of the inner ring routing.
  • the outer loop connection section of the outer loop routing is located on a side of the antenna projection area close to the inner loop routing.
  • the outer ring connecting segment is provided with a plurality of second openings, and the plurality of second openings are arranged in at least one row along a direction from the effective area toward the edge area.
  • the outer loop connection segment of the outer loop routing at least partially overlaps with the antenna projection area.
  • the outer ring routing further includes: a plurality of outer ring extension segments, the plurality of outer ring extension segments are respectively connected to a side of the outer ring connecting segment close to an edge of the substrate and extend to an edge of the substrate; the plurality of outer ring extension segments at least partially overlap with the antenna projection area.
  • At least one of the plurality of outer ring extension segments has an orthographic projection on the substrate that is rectangular or T-shaped.
  • the outer ring routing also includes: at least one second connecting routing; the outer ring connecting segment of the outer ring routing is connected to the inner ring connecting segment of the inner ring routing through the at least one second connecting routing; and the resistance of the second connecting routing is substantially the same as the resistance of the first connecting routing.
  • the first connection trace and the second connection trace are serpentine traces when projected on the substrate.
  • a plurality of anti-static capacitors are arranged between the outer ring routing segment of the outer ring routing and the adjacent inner ring routing segment of the inner ring routing, and at least one anti-static capacitor includes a first electrode plate and a second electrode plate, the first electrode plate and the outer ring routing segment are an integral structure, and the second electrode plate is located on a side of the first electrode plate close to the inner ring routing segment.
  • the first electrode plate has a plurality of first comb-tooth portions facing the second electrode plate
  • the second electrode plate has a plurality of second comb-tooth portions facing the first electrode plate
  • the plurality of first comb-tooth portions and the plurality of second comb-tooth portions are interspersed with each other.
  • the first electrode plate of the anti-static capacitor is grounded, and the second electrode plate is a dummy conductive structure.
  • the touch structure layer includes: at least one touch conductive layer and a second touch insulating layer located on a side of the at least one touch conductive layer away from the base substrate, and an edge of the second touch insulating layer overlaps with the anti-static capacitor.
  • the touch control structure layer includes: at least one touch control conductive layer; the edge ground trace and the touch control conductive layer are in the same layer structure.
  • the at least one touch conductive layer includes a touch trace, and the edge ground trace is located on a side of the touch trace away from the active area.
  • the touch structure layer includes: a first touch conductive layer, a second touch conductive layer, and a first touch insulating layer located between the first touch conductive layer and the second touch conductive layer, and a boundary of the first touch insulating layer is located on a side of the edge ground trace close to the effective area.
  • an edge of the substrate base plate is flush with an edge of the edge ground trace.
  • an embodiment of the present disclosure provides a display device, comprising a display panel and an antenna structure as described above, wherein the antenna structure is located on a side of the base substrate of the display panel away from the touch structure layer, and the antenna projection area of the display panel overlaps with the orthographic projection of the antenna structure on the display panel.
  • an embodiment of the present disclosure provides a display device, including a display panel and an antenna structure.
  • the display panel includes an effective area and an edge area located on at least one side of the effective area, and the edge area includes an antenna projection area and a non-antenna projection area located on at least one side of the antenna projection area.
  • the effective area of the display panel includes: a substrate, and a display structure layer and a touch structure layer sequentially arranged on the substrate.
  • the edge area of the display panel includes: a touch lead and an edge grounding trace arranged on the substrate, and the edge grounding trace is located on a side of the touch lead away from the effective area.
  • the touch lead and the edge grounding trace are at least partially arranged in the same layer.
  • the antenna structure overlaps the antenna projection area of the display panel in the orthographic projection of the display panel.
  • the overlapping area of the edge grounding trace and the antenna projection area is smaller than the overlapping area of the edge grounding trace and the non-antenna projection area.
  • the antenna structure is located on a side of the base substrate of the display panel away from the touch structure layer.
  • a portion of the edge ground trace located in the antenna projection area close to the effective area is a first trace
  • a portion of the edge ground trace located in the non-antenna projection area close to the effective area is a second trace; a distance between an edge of the first trace close to the effective area and an edge of the substrate is greater than a distance between an edge of the second trace close to the effective area and an edge of the substrate.
  • FIG1A is a schematic diagram showing the conduction of negative charges generated by friction on the cover surface of a display panel
  • FIG1B is a schematic diagram showing that negative charges generated by friction on the cover plate surface form a negative electric field in the display panel
  • FIG2 is a schematic diagram showing an arrangement of a plurality of display touch control substrates on a display motherboard
  • FIG3 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • Fig. 4 is a schematic diagram of a partial cross section along the P-P' direction in Fig. 3;
  • FIG5 is a partial enlarged schematic diagram of area S1 in FIG3 ;
  • FIG6 is a schematic diagram of the planar position of a display panel and an antenna structure according to at least one embodiment of the present disclosure
  • FIG7 is a schematic diagram of the cross-sectional position of a display panel and an antenna structure according to at least one embodiment of the present disclosure
  • FIG8A is a partial schematic plan view of region S2 in FIG6 ;
  • FIG8B is a schematic diagram of the edge ground routing in FIG8A ;
  • FIG9 is a schematic partial cross-sectional view along the Q-Q' direction in FIG8A;
  • FIG10 is a partial plan view of the edge grounding wiring of the area S3 in FIG6 ;
  • FIG. 11 is a partial plan view of the area S3 in FIG. 6 before fine cutting according to the second cutting path X2;
  • FIG12 is a schematic diagram of the arrangement of connection lines according to at least one embodiment of the present disclosure.
  • FIG13 is another partial schematic plan view of the edge grounding routing of the area S3 in FIG6 ;
  • FIG14 is another partial schematic plan view of the edge grounding wiring of the area S3 in FIG6 ;
  • FIG15 is another partial schematic plan view of the edge grounding routing of the area S3 in FIG6 ;
  • FIG16 is another partial schematic plan view of the edge grounding routing of the area S3 in FIG6 ;
  • FIG. 17 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the ordinal numbers such as “first”, “second”, and “third” in the present disclosure are provided to avoid confusion of constituent elements, rather than to limit the quantity.
  • the "plurality” in the present disclosure means a quantity of two or more.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal connection of two elements.
  • electrical connection includes the situation where constituent elements are connected together through an element with some electrical function.
  • elements with some electrical function There is no special restriction on “elements with some electrical function” as long as they can transmit electrical signals between connected constituent elements. Examples of “elements with some electrical function” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode.
  • a channel region refers to a region where current mainly flows.
  • one of the electrodes is called the first pole and the other electrode is called the second pole.
  • the first pole can be a source electrode or a drain electrode
  • the second pole can be a drain electrode or a source electrode.
  • the gate electrode of the transistor is called the control pole.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced with “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • width refers to the length of the trace in a direction perpendicular to the extending direction of the trace within the extending plane of the trace.
  • a extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, line segment or strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.
  • a extends along direction B means "the main part of A extends along direction B".
  • the display panel may integrate a touch structure.
  • the display panel may include an organic light emitting diode (OLED) display substrate, or may be a quantum dot light emitting diode (QLED, Quantum Dot Light Emitting Diodes) display substrate, or may be a plasma display device (PDP) display substrate, or may be an electrophoretic display (EPD) display substrate, or may be a liquid crystal display (LCD) substrate.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • EPD electrophoretic display
  • LCD liquid crystal display
  • the display panel may include an OLED display substrate, and the OLED display substrate may include: a substrate substrate, a driving circuit layer disposed on the substrate substrate, a light emitting element layer disposed on the driving circuit layer, and an encapsulation layer disposed on the light emitting element layer.
  • the touch structure is disposed on the encapsulation layer of the display substrate to form a touch structure on thin film encapsulation (Touch on Thin Film Encapsulation, referred to as Touch on TFE) structure, and the display structure and the touch structure are integrated together, which has the advantages of being light, thin, and foldable, and can meet the product requirements of flexible folding, narrow frame, etc.
  • Touch on TFE thin film encapsulation
  • Touch on TFE structures mainly include Flexible Multi-Layer On Cell (FMLOC) structure and Flexible Single-Layer On Cell (FSLOC) structure.
  • FMLOC structure is based on the working principle of mutual capacitance detection.
  • two layers of metal are used to form the driving (Tx) electrode and the sensing (Rx) electrode.
  • the integrated circuit (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode.
  • the FSLOC structure is based on the working principle of self-capacitance (or voltage) detection.
  • a single layer of metal is used to form the touch electrode.
  • the integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.
  • Figure 1A is a schematic diagram of the conduction of negative charges generated by friction on the cover plate surface of the display panel.
  • Figure 1B is a schematic diagram of the negative charges generated by friction on the cover plate surface forming a negative electric field in the display panel.
  • Figures 1A and 1B both show a cross-sectional structure of a display panel.
  • the display panel may include: a heat dissipation film layer (SCF) 11, a carrier film layer (U-film) 12, a display touch control substrate 13, a polarizer (POL) 14, an optically clear adhesive (OCA) layer 15, and a cover plate (CG) 16, which are arranged in sequence.
  • the cover plate 16 may be a glass cover plate.
  • the heat dissipation film layer 11 may include a conductive heat dissipation layer 111 and a non-conductive heat dissipation layer 112, which are stacked in sequence.
  • the carrier film layer 12 may include a first carrier layer 121 and a second carrier layer 122, which are stacked in sequence.
  • the material of the first carrier layer 121 may be polyethylene terephthalate (PET), and the material of the second carrier layer 122 may be a pressure sensitive adhesive (PSA).
  • the display touch control substrate 13 may include: a base substrate 131, a display structure layer 132, and a touch control structure layer 133, which are arranged in sequence.
  • the display structure layer 132 may include: a driving circuit layer (e.g., including a plurality of pixel circuits) and a light emitting element layer (e.g., including a plurality of light emitting elements).
  • the pixel circuit is electrically connected to the light emitting element and is configured to drive the light emitting element to emit light.
  • the driving circuit layer may include at least: a semiconductor layer 134 (e.g., an active layer including a transistor), a power supply line 135 (e.g., a low voltage line VSS), and a signal line 136.
  • a semiconductor layer 134 e.g., an active layer including a transistor
  • a power supply line 135 e.g., a low voltage line VSS
  • a signal line 136 In the frame area of the display panel, ink 17 is applied between the cover plate 16 and the optical adhesive layer 15.
  • the metal film layer (for example, the power supply line 135 and the signal line 136) of the display structure layer 132 of the display touch substrate 13 and the metal film layer of the touch structure layer 133 can conduct away static electricity, most of the static electricity is more transmitted from the edge of the display panel where there is no metal layer to the lower layer in sequence.
  • the cover plate 16, the optical adhesive layer 15, the polarizer 14, the display touch substrate 13 and the second carrier layer 122 of the carrier film layer 12 all have high conductivity for negative charges
  • the ink 17 and the non-conductive heat dissipation layer 112 of the heat dissipation film layer 11 have medium conductivity for negative charges
  • the first carrier layer 121 of the carrier film layer 12 has low conductivity for negative charges.
  • the negative charges generated on the surface of the cover plate 16 will be transferred from the edge of the display panel to the lower layer, passing through the optical adhesive layer 15, the polarizer 14, the insulating layer of the display touch substrate 13 and the base substrate 131 in sequence, and gather on the side of the base substrate 131 of the display touch substrate 13 away from the cover plate 16 (i.e., the back side) to form a negative electric field.
  • the negative electric field formed on the display touch substrate 13 will cause the threshold voltage (Vth) of the transistor of the driving circuit layer to be positively biased, thereby causing the display touch substrate 13 to light up.
  • Vth threshold voltage
  • the display panel often shows a poor display of a green screen.
  • the display panel needs to be assembled with the antenna structure. After the display panel and the antenna structure are assembled, the metal film layer overlapping the antenna structure in the display panel will affect the antenna structure, causing the antenna structure's omnidirectional receiving sensitivity (TIS, Total Isotropic Sensitivity) and signal reception and transmission to be attenuated, affecting the performance of the antenna structure.
  • TIS omnidirectional receiving sensitivity
  • TIS Total Isotropic Sensitivity
  • the present embodiment provides a display panel, comprising: an effective area, an edge area located on at least one side of the effective area, the edge area comprising an antenna projection area and a non-antenna projection area located on at least one side of the antenna projection area.
  • the effective area comprises: a substrate, and a display structure layer and a touch structure layer sequentially arranged on the substrate.
  • the edge area comprises: an isolation dam and an edge grounding trace arranged on the substrate.
  • the edge grounding trace is located on a side of the isolation dam away from the effective area.
  • the overlapping area of the edge grounding trace and the antenna projection area is smaller than the overlapping area of the edge grounding trace and the non-antenna projection area.
  • the antenna projection area may be a projection area of the antenna structure on the display panel.
  • the antenna projection area and the non-antenna projection area may both be located on a side of the isolation dam in the edge area away from the effective area.
  • the antenna projection area and the non-antenna projection area may not overlap.
  • the non-antenna projection area may surround the antenna projection area; or, the non-antenna projection area and the antenna projection area may be adjacent in one direction. This embodiment is not limited to this.
  • the display panel provided in this embodiment can lead out the negative charge generated on the cover plate surface of the display panel by setting an edge grounding line in the edge area of the display panel, thereby blocking the electrostatic conduction path, reducing the negative electric field formed inside the display panel, and improving the brightness of the display structure layer caused by the negative electric field.
  • the influence of the edge grounding line on the omnidirectional receiving sensitivity and signal reception and transmission of the antenna structure can be reduced, and the shielding interference of the edge grounding line on the antenna signal can be reduced, thereby ensuring the performance of the antenna structure.
  • the overlapping area of the edge grounding trace and the antenna projection area may account for less than or equal to 7% of the antenna projection area. Among them, the overlapping area of the edge grounding trace and the antenna projection area may account for less than or equal to 7% of the antenna projection area. Among them, the overlapping area of the edge grounding trace and the antenna projection area may account for less than or equal to 7% of the antenna projection area. In some examples, the edge grounding trace and the antenna projection area may not overlap. In other words, the overlapping area of the edge grounding trace and the antenna projection area may be 0.
  • the edge grounding trace by setting the edge grounding trace to completely avoid the antenna structure, the negative charge generated on the cover surface of the display panel can be derived and shielding interference with the antenna signal can be avoided.
  • the overlapping area of the edge grounding trace and the antenna projection area may account for about 7% of the antenna projection area.
  • the edge grounding trace by setting the edge grounding trace to partially avoid the antenna structure, the negative charge generated on the cover surface of the display panel can be derived, and the shielding interference with the antenna signal can be reduced, so that the electrostatic derivation of the display panel and the performance of the antenna structure can achieve better results.
  • the edge grounding routing may include: an outer ring routing, an inner ring routing, and a plurality of first connection routings.
  • the plurality of first connection routings connect the inner ring routing and the outer ring routing.
  • the inner ring routing, the outer ring routing, and the plurality of first connection routings may be an integral structure.
  • the outer ring routing may be located on the side of the inner ring routing away from the effective area.
  • the plurality of first connection routings may be located in a non-antenna projection area, in other words, the plurality of first connection routings may not overlap with the antenna projection area.
  • the inner ring routing, the first connection routing, and the outer ring routing may be used to export the negative charge generated on the cover plate surface of the display panel, thereby blocking the electrostatic conduction path and improving the display effect of the display panel.
  • the orthographic projection of the first connecting line on the substrate may be a serpentine line.
  • a serpentine line is a meandering curve. For example, after one end of the line extends a distance in one direction, it bends and twists and extends a distance in the opposite direction of the direction, bends and twists again and extends in the direction, and bends and twists repeatedly several times to form a serpentine line.
  • the resistance of the edge grounding line can be increased, thereby preventing electrostatic breakdown and playing a protective role.
  • the inner ring routing may include: at least two inner ring routing segments and an inner ring connecting segment connecting adjacent inner ring routing segments.
  • the distance between the inner ring connecting segment and the edge of the substrate substrate may be greater than the distance between the inner ring routing segment and the edge of the substrate substrate.
  • the inner ring routing may not overlap with the antenna projection area, and the inner ring connecting segment of the inner ring routing may be located on the side of the antenna projection area close to the effective area.
  • the inner ring routing remains continuous near the antenna projection area to ensure that the negative charge generated on the cover surface of the display panel is guided out, thereby blocking the electrostatic conduction path and improving the display effect of the display panel.
  • the distance between a certain trace and the edge of the substrate may refer to the distance between the trace and the most adjacent edge of the substrate.
  • the edge of the substrate may be flush with the edge of the edge ground trace.
  • the outer ring routing may not overlap with the antenna projection area.
  • the outer ring routing may include: two outer ring routing segments located in the non-antenna projection area. The two outer ring routing segments do not overlap with the antenna projection area.
  • the antenna projection area may not be provided with an outer ring routing.
  • the outer ring routing may include: at least two outer ring routing segments, and an outer ring connecting segment connecting adjacent outer ring routing segments. At least two outer ring routing segments are located in the non-antenna projection area. The distance between the outer ring connecting segment and the edge of the substrate substrate may be greater than the distance between the outer ring routing segment and the edge of the substrate substrate. In some examples, the outer ring connecting segment of the outer ring routing may be located on the side of the antenna projection area close to the inner ring routing. For example, the outer ring connecting segment and the antenna projection area may not overlap.
  • the antenna projection area is bypassed by setting the outer ring connecting segment to be retracted into the effective area, thereby reducing the overlapping area of the edge ground routing and the antenna projection area, thereby improving the shielding interference of the edge ground routing on the antenna signal.
  • the outer ring routing remains continuous near the antenna projection area to ensure that the negative charge generated on the cover plate surface of the display panel is led out, thereby blocking the electrostatic conduction path and improving the display effect of the display panel.
  • the outer ring connecting segment of the outer ring routing may overlap with the antenna projection area.
  • the width of the outer ring connecting segment may be less than the width of the outer ring routing segment.
  • the overlapping area between the outer ring trace and the antenna projection area is reduced to improve the shielding interference of the edge ground trace on the antenna signal.
  • the portion of the edge grounding trace located on the antenna projection area close to the effective area is the first trace
  • the portion of the edge grounding trace located on the non-antenna projection area close to the effective area is the second trace.
  • the distance between the edge of the first trace close to the effective area and the edge of the substrate substrate may be greater than the distance between the edge of the second trace close to the effective area and the edge of the substrate substrate.
  • the first trace may include only the inner ring trace, or may include an inner ring trace and an outer ring trace that are not connected to each other, or may include an inner ring trace and an outer ring trace that are connected to each other.
  • the second trace may include an inner ring trace, an outer ring trace, and a first connecting trace connecting the inner ring trace and the outer ring trace.
  • This embodiment is not limited to this.
  • the edge grounding trace is set to be retracted to one side of the effective area to completely avoid or partially avoid the antenna projection area, which can ensure the effect of exporting the negative charge generated on the cover surface of the display panel and reduce the shielding interference to the antenna signal.
  • the touch structure layer may include: at least one touch conductive layer; the edge grounding trace and the touch conductive layer may be in the same layer structure.
  • the touch structure layer may include multiple touch conductive layers, the edge grounding trace may be in the same layer structure as the touch conductive layer closest to the cover plate, and the cover plate may be located on the side of the touch structure layer away from the base substrate.
  • At least one touch conductive layer may include a touch trace, and the edge ground trace may be located on a side of the touch trace away from the active area.
  • the touch trace may include: a plurality of second panel crack detection lines. In the edge area, a plurality of touch leads, a protection line, a first ground trace, and a plurality of second panel crack detection lines may be sequentially arranged in a direction away from the active area.
  • the display panel of this embodiment is described below by means of some examples.
  • a flexible display panel is used as an example for explanation.
  • a display motherboard is first prepared, and then the display motherboard is cut, so that the display motherboard is divided into multiple display touch substrates, and the separated display touch substrates can be used to form a single display panel.
  • FIG. 2 is a schematic diagram of the arrangement of multiple display touch substrates on a display motherboard. As shown in FIG. 2, multiple substrate areas 200 on the display motherboard 100 are arranged regularly and periodically, and the cutting area 300 is located outside the substrate area 200.
  • the substrate area 200 includes at least an active area AA and a binding area B1 located on at least one side of the active area AA.
  • the active area AA may include multiple sub-pixels arranged regularly, and the binding area B1 may include a fan-out area and a binding pin.
  • a first cutting path X1 and a second cutting path X2 are provided in the cutting area 300. After all the film layers of the display motherboard are prepared, the cutting equipment performs rough cutting and fine cutting along the first cutting path X1 and the second cutting path X2, respectively, to form a display touch substrate.
  • FIG3 is a schematic diagram of a display panel of at least one embodiment of the present disclosure.
  • the display panel of this example is illustrated by taking an FMLOC structure as an example. However, this embodiment is not limited to this. In other examples, the display panel may be an FSLOC structure with a single touch conductive layer.
  • the display panel in a plane parallel to the display panel, may include: an active area AA, and a peripheral area located outside the active area AA.
  • the peripheral area may include: a binding area B1 located on one side of the active area AA and an edge area B2 located on the other side of the active area AA.
  • the active area AA may be either a touch area or a display area.
  • the touch area and the display area in the following description both refer to the active area AA.
  • the touch area may include at least a plurality of regularly arranged touch electrodes
  • the edge area B2 includes at least a plurality of touch leads and an edge grounding trace 35
  • the binding area B1 includes at least pins that connect the plurality of touch leads and the edge grounding trace 35 to an external control device.
  • the touch structure may be a mutual capacitance structure.
  • the touch area may include a plurality of first touch units 310 and a plurality of second touch units 320.
  • the first touch unit 310 may have a linear shape extending along the first direction D1, and the plurality of first touch units 310 may be arranged in sequence along the second direction D2;
  • the second touch unit 320 may have a linear shape extending along the second direction D2, and the plurality of second touch units 320 may be arranged in sequence along the first direction D1.
  • the first direction D1 intersects with the second direction D2, for example, the first direction D1 may be perpendicular to the second direction D2.
  • Each first touch unit 310 may include a plurality of first touch electrodes 311 and a first connection portion 312 arranged in sequence along the first direction D1, and the first touch electrodes 311 and the first connection portion 312 are alternately arranged and electrically connected in sequence.
  • Each second touch unit 320 may include a plurality of second touch electrodes 321 arranged in sequence along the second direction D2, and the plurality of second touch electrodes 321 are arranged at intervals, and adjacent second touch electrodes 321 are electrically connected to each other through the second connection portion 322.
  • the film layer where the second connection portion 322 is located may be different from the film layer where the first touch electrode 311 and the second touch electrode 321 are located.
  • the first touch electrodes 311 and the second touch electrodes 321 may be alternately arranged in the third direction D3, and the third direction D3 may intersect both the first direction D1 and the second direction D2.
  • a plurality of first touch electrodes 311, a plurality of second touch electrodes 321 and a plurality of first connecting portions 312 may be arranged in the same layer on the touch layer, and may be formed by the same patterning process, and the first touch electrodes 311 and the first connecting portions 312 may be interconnected integral structures.
  • the second connecting portion 322 may be arranged in the bridging layer, and the adjacent second touch electrodes 321 may be electrically connected to each other through vias, and a touch insulating layer may be arranged between the touch layer and the bridging layer.
  • a plurality of first touch electrodes 311, a plurality of second touch electrodes 321 and a plurality of second connecting portions 322 may be arranged in the same layer on the touch layer, and the second touch electrodes 321 and the second connecting portions 322 may be interconnected integral structures, and the first connecting portion 312 may be arranged in the bridging layer, and the adjacent first touch electrodes 311 may be electrically connected to each other through vias.
  • the first touch electrode may be a driving (Tx) electrode
  • the second touch electrode may be a sensing (Rx) electrode.
  • the first touch electrode may be a sensing (Rx) electrode
  • the second touch electrode may be a driving (Tx) electrode.
  • this embodiment is not limited to this.
  • the first touch electrode 311 and the second touch electrode 321 may have a rhombus shape, such as a regular rhombus, a horizontally long rhombus, or a vertically long rhombus.
  • the first touch electrode 311 and the second touch electrode 321 may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons, which is not limited in the present disclosure.
  • the first touch electrode 311 and the second touch electrode 321 may be in the form of transparent conductive electrodes.
  • the first touch electrode 311 and the second touch electrode 321 may be in the form of a metal grid, the metal grid is formed by interweaving a plurality of metal wires, the metal grid includes a plurality of grid patterns, and the grid pattern is a polygon formed by a plurality of metal wires.
  • the first touch electrode 311 and the second touch electrode 321 in the form of a metal grid have the advantages of low resistance, small thickness, and fast response speed.
  • the binding area B1 is located on one side of the active area AA, and along the direction away from the active area AA (e.g., the second direction D2), the binding area B1 may include: a first fan-out area 201, a bending area 202, a second fan-out area 203, an anti-static area 204, a driver chip area 205, and a binding pin area 206 arranged in sequence.
  • the first fan-out area 201 may be provided with a signal transmission line and a touch lead of the display substrate.
  • the signal transmission line of the display substrate may include at least a high-voltage line VDD, a low-voltage line VSS, and a plurality of data transmission lines.
  • the plurality of data transmission lines are configured to connect the data line (Data Line) of the display area in a fan-out routing manner, and the high-voltage line VDD and the low-voltage line VSS are configured to connect the high-level power line and the low-level power line of the display substrate, respectively.
  • the plurality of touch leads are configured to be connected to the plurality of pins of the binding pin area 206 in correspondence.
  • the bending area 202 may be provided with a groove, and the groove is configured to bend the second fan-out area 203, the anti-static area 204, the driver chip area 205 and the binding pin area 206 to the back of the effective area AA.
  • the second fan-out area 203 may be provided with a plurality of touch leads and a plurality of data transmission lines led out in a fan-out routing manner.
  • the anti-static area 204 may be provided with an anti-static circuit, and the anti-static circuit is configured to eliminate static electricity.
  • the driver chip area 205 may be provided with a source driver circuit (Driver IC), and the source driver circuit is configured to be electrically connected to the plurality of data transmission lines of the second fan-out area 203.
  • the driver chip area 205 may be provided with a touch and display driver integrated circuit (TDDI, Touch and Display Driver Integration).
  • the binding pin area 206 may be provided with a plurality of pins (PIN), and the plurality of pins are electrically connected to the plurality of touch leads and the plurality of signal transmission lines of the source driver circuit correspondingly, and are connected to an external control device through a bound flexible circuit board (FPC).
  • PIN pins
  • FPC bound flexible circuit board
  • the edge region B2 is located on multiple sides of the active region AA away from the binding region B1.
  • the binding region B1 may be located on the lower side of the active region AA
  • the edge region B2 may be located on the upper side, the left side, and the right side of the active region AA.
  • the edge region B2 is provided with at least an edge grounding trace 35 and a plurality of touch leads.
  • the edge grounding trace 35 may extend from the edge region B2 to the binding region B1, and be electrically connected to the ground pin in the binding pin area 206 of the binding region B1.
  • the plurality of touch leads may include a plurality of driving leads and a plurality of sensing leads.
  • the first touch electrode is a driving electrode and the second touch electrode is a sensing electrode.
  • the first end of the driving lead is electrically connected to the first touch electrode, and the second end of the driving lead extends along the edge area B2 to the binding area B1.
  • the first end of the sensing lead is electrically connected to the second touch electrode, and the second end of the sensing lead extends along the edge area B2 to the binding area B1.
  • this embodiment is not limited to this.
  • a first cutting line and a second cutting line are provided outside the binding area B1 and the edge area B2, the second cutting line is a fine cutting line, located outside the binding area B1 and the edge area B2, and the shape of the second cutting line is the same as the outer contour of the binding area B1 and the edge area B2.
  • the first cutting line is a rough cutting line, located outside the second cutting line, and the shape of the first cutting line can be substantially the same as the contour of the second cutting line.
  • the edge of the edge grounding trace 35 away from the active area AA can be obtained by the second cutting line.
  • this embodiment is not limited to this.
  • FIG4 is a schematic diagram of a partial cross-section along the P-P’ direction in FIG3.
  • the display panel of the effective area AA may include: a base substrate 30, a display structure layer 41 and a touch structure layer 31 sequentially arranged on the base substrate 30.
  • the display structure layer 41 may include: a driving circuit layer 42, a light-emitting structure layer 43 and an encapsulation layer 44 sequentially arranged on the base substrate 30.
  • the touch structure layer 31 uses the encapsulation layer 44 as a substrate.
  • the display structure layer may include other film layers, and other film layers may be arranged between the touch structure layer and the encapsulation layer, which is not limited in the present disclosure.
  • the base substrate 30 may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together.
  • the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc.
  • the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the base substrate, and the material of the semiconductor layer may be amorphous silicon (a-Si).
  • a-Si amorphous silicon
  • the driving circuit layer 42 of the active area AA may include transistors and storage capacitors constituting the pixel circuit.
  • a transistor e.g., a first transistor 421 of a pixel circuit of a sub-pixel of the active area AA is used as an example for illustration.
  • FIG. 4 a transistor (e.g., a first transistor 421) of a pixel circuit of a sub-pixel of the active area AA is used as an example for illustration. In some examples, as shown in FIG.
  • the driving circuit layer 42 of the active area AA may include: a semiconductor layer, a first insulating layer 411, a first gate metal layer, a second insulating layer 412, a second gate metal layer, a third insulating layer 413, a first source-drain metal layer, a fourth insulating layer 414, a first flat layer 415, a second source-drain metal layer, and a second flat layer 416, which are sequentially arranged on the substrate 30.
  • the semiconductor layer includes at least: an active layer of the first transistor 421.
  • the first gate metal layer includes at least: a gate electrode of the first transistor 421, a first capacitor plate of a capacitor of the pixel circuit.
  • the second gate metal layer includes at least: a second capacitor plate of a capacitor of the pixel circuit.
  • the first source-drain metal layer includes at least: a first pole and a second pole of the first transistor 421.
  • the second source-drain metal layer at least includes: an anode connection electrode 428 , and the anode connection electrode 428 is configured to connect the anode of the light-emitting element and the pixel circuit.
  • the first insulating layer 411, the second insulating layer 412, the third insulating layer 413 and the fourth insulating layer 414 may be inorganic insulating layers, and the first planar layer 415 and the second planar layer 416 may be organic insulating layers.
  • the first insulating layer 411, the second insulating layer 412, the third insulating layer 413 and the fourth insulating layer 414 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the first insulating layer 411 and the second insulating layer 412 may be referred to as a gate insulating (GI) layer
  • the third insulating layer 413 may be referred to as an interlayer insulating (ILD) layer
  • the fourth insulating layer 414 may be referred to as a passivation (PVX) layer.
  • the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti/Al/T
  • the semiconductor layer may be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide material
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • sexithiophene or polythiophene sexithiophene or polythiophene
  • the light emitting structure layer 43 of the active area AA may include: an anode 431, a pixel definition layer 434, an organic light emitting layer 432, and a cathode 433.
  • the anode 431 is disposed on the second flat layer 416, and is electrically connected to the anode connection electrode 428 through a via hole provided on the second flat layer 416.
  • the pixel definition layer 434 is disposed on the anode 431 and the second flat layer 416, and a pixel opening is disposed thereon, and the pixel opening exposes at least a portion of the surface of the anode 431, the organic light emitting layer 432 is disposed in the pixel opening, and the cathode 433 is disposed on the organic light emitting layer 432, and the organic light emitting layer 432 emits light of corresponding color under the action of voltage applied by the anode 431 and the cathode 433.
  • the pixel definition layer 434 may be made of materials such as polyimide, acrylic, or polyethylene terephthalate.
  • the encapsulation layer 44 of the effective area AA may include a stacked first encapsulation layer 441, a second encapsulation layer 4442, and a third encapsulation layer 443.
  • the first encapsulation layer 441 and the third encapsulation layer 443 may be made of inorganic materials
  • the second encapsulation layer 442 may be made of organic materials
  • the second encapsulation layer 442 is arranged between the first encapsulation layer 441 and the third encapsulation layer 443 to ensure that external water vapor cannot enter the light-emitting structure layer 43.
  • the touch structure layer 31 of the active area AA may include: a buffer layer (omitted in FIG4 ), a first touch conductive layer (TMA), a first touch insulating layer (TLD) 301, a second touch conductive layer (TMB) and a second touch insulating layer (TOC) 302 stacked in sequence.
  • the first touch conductive layer may be the aforementioned bridge layer
  • the second touch conductive layer may be the aforementioned touch layer.
  • the first touch conductive layer may include a second connecting portion 322, and the second touch conductive layer may include a first touch electrode 311, a second touch electrode 321 and a first connecting portion 312.
  • the buffer layer and the first touch insulating layer 301 may be made of inorganic materials, and the second touch insulating layer 302 may be made of organic materials.
  • the buffer layer and the first touch insulating layer 301 may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the second touch insulating layer 302 may be made of polyimide (PI) or the like. However, this embodiment is not limited to this.
  • the edge region B2 may include: a first sub-edge region B21, a second sub-edge region B22, and a third sub-edge region B23 along a direction away from the active region AA.
  • the first sub-edge region B21 includes at least: a gate drive circuit, a plurality of touch leads 313, and a first ground trace 331.
  • the touch leads 313 and the first ground trace 331 may be a double-layer trace structure.
  • a touch lead 313 may include an electrically connected first sub-lead 313a and a second sub-lead 313b.
  • the first ground trace 331 may include an electrically connected first sub-ground trace 331a and a second sub-ground trace 331b.
  • the second sub-edge region B22 is located on a side of the first sub-edge region B21 away from the active region AA, and the second sub-edge region B22 includes at least: a first isolation dam 513, a second isolation dam 514, and at least one (for example, three) first panel crack detection (PCD, Panel Crack Detection) line 516.
  • the first panel crack detection line 516 may be configured to detect the display structure layer 41.
  • the third sub-edge region B23 is located on a side of the second sub-edge region B12 away from the active area AA and may include at least: a crack dam 515 and an edge grounding trace 35.
  • the display panel of the first sub-edge region B21 may include: a base substrate 30 and a driving circuit layer 42, a first flat layer 415, a second flat layer 416, a first connection electrode 512, an isolation column 511, a cathode 433, an encapsulation layer 44, a plurality of first sub-leads 313a and a first sub-grounding trace 331a disposed on the encapsulation layer 44, a first touch insulating layer 301, a plurality of second sub-leads 313b and a second sub-grounding trace 331b disposed on the first touch insulating layer 301, and a second touch insulating layer 302.
  • the driving circuit layer 42 of the first sub-edge region B21 may include transistors and storage capacitors constituting a gate driving circuit.
  • the gate driving circuit of the first sub-edge region B21 may include a scanning driving circuit and a light emitting control driving circuit.
  • the edge region B2 is illustrated by taking a transistor (e.g., the second transistor 422) and a capacitor (e.g., the first capacitor 424) of the scan driving circuit, and a transistor (e.g., the third transistor 423) and a capacitor (e.g., the second capacitor 425) of the light emitting control driving circuit as examples.
  • the film layer structure of the driving circuit layer of the first sub-edge region B21 may be similar to the film layer structure of the driving circuit layer of the active region AA, so it is not described in detail here.
  • the first sub-grounding trace 331a and the plurality of first sub-leads 313a may be in the same layer structure as the first touch conductive layer
  • the second sub-grounding trace 331b and the plurality of second sub-leads 313b may be in the same layer structure as the second touch conductive layer
  • the plurality of first sub-leads 313a and the plurality of second sub-leads 313b may be electrically connected one by one, thereby realizing a touch lead 313 with a double-layer routing structure.
  • the first sub-grounding trace 331a and the second sub-grounding trace 331b are electrically connected to realize a first grounding trace 331 with a double-layer routing structure.
  • a guard line may be provided between the touch lead 313 and the first grounding trace 331, and the guard line 315 may include an electrically connected first guard sub-line 315a and a second guard sub-line 315b, the first guard sub-line 315a and the first touch conductive layer may be in the same layer structure, and the second guard sub-line 315b and the second touch conductive layer may be in the same layer structure.
  • the protection line 315 can be a double-layer routing structure.
  • At least one (for example, two) second panel crack detection lines 314 can also be set on the side of the first grounding line 331 away from the touch lead 313 and the protection line 315.
  • the second panel crack detection line 314 can be configured to detect the touch structure layer 31.
  • the second panel crack detection line 314 and the second touch conductive layer can be the same layer structure.
  • the first grounding line 331, the touch lead 313 and the protection line 315 can be a single-layer routing structure, for example, it can be the same layer structure as the first touch conductive layer or it can be the same layer structure as the second touch conductive layer.
  • the display panel of the second sub-edge region B22 may include: a base substrate 30 and a composite insulating layer disposed on the base substrate 30 , a first panel crack detection line 516 , a low voltage line 426 , a second connection electrode 427 , an isolation dam (e.g., a first isolation dam 513 and a second isolation dam 514 ), a first encapsulation layer 441 , a third encapsulation layer 443 , a first touch insulating layer 301 and a second touch insulating layer 302 .
  • the composite insulating layer may include: a first insulating layer 411 to a third insulating layer 413 stacked on the base substrate 30 .
  • the first panel crack detection line 516 may be disposed on the second insulating layer 412 and may be in the same layer structure as the second gate metal layer.
  • the low voltage line 426 may be in the same layer structure as the first source and drain metal layer of the driving circuit layer 42
  • the second connection electrode 427 may be in the same layer structure as the second source and drain metal layer of the driving circuit layer 42 .
  • the cathode 433 can be electrically connected to the second connection electrode 427 through the first connection electrode 512
  • the first connection electrode 512 can be electrically connected to the low voltage line 426 through the second connection electrode 427.
  • the first isolation dam 513 is located on the side of the second isolation dam 514 close to the active area AA.
  • the second isolation dam 514 can be formed by stacking a first dam base, a second dam base, a third dam base and a fourth dam base.
  • the first isolation dam 513 can be formed by stacking a second dam base, a third dam base and a fourth dam base.
  • the first dam base can be the same layer structure as the first flat layer 415
  • the second dam base can be the same layer structure as the second flat layer 416
  • the third dam base can be the same layer structure as the pixel definition layer 434
  • the fourth dam base can be the same layer structure as the isolation column 511.
  • this embodiment is not limited to this.
  • the display panel of the third sub-edge region B23 may include a crack dam 515 and an edge grounding trace 35 disposed on the base substrate 30.
  • the crack dam 515 is formed on the composite insulating layer, and the crack dam 515 may include a plurality of cracks disposed at intervals, and the cracks may expose the base substrate 30.
  • the first flat layer 415 may cover the crack dam 515.
  • the edge grounding trace 35 may be disposed on the first flat layer 415 covering the crack dam 515.
  • the second touch insulating layer 302 may expose a portion of the surface of the edge grounding trace 35.
  • the first touch insulating layer 301 and the edge grounding trace 35 may not overlap in their orthographic projections on the base substrate 30.
  • the boundary of the first touch insulating layer 301 may be located on a side of the edge grounding trace 35 close to the active area AA.
  • the orthographic projection of the edge grounding trace 35 on the base substrate 30 may partially overlap with the orthographic projection of the crack dam 515 on the base substrate 30.
  • this embodiment is not limited to this.
  • the orthographic projections of the first touch insulating layer 301 and the edge grounding trace 35 on the base substrate 30 may partially overlap.
  • the concave-convex crack dam 515 formed in the edge area B2 is used to avoid affecting the film structure of the active area AA and the first sub-edge area B21 during the display motherboard cutting process.
  • the multiple spaced cracks can not only reduce the force on the active area AA and the first sub-edge area B21, but also cut off the cracks from being transmitted in the direction of the active area AA and the first sub-edge area B21.
  • the edge grounding trace 35 and the second touch conductive layer can be in the same layer structure.
  • this embodiment is not limited to this.
  • the edge grounding trace can be in the same layer structure as any conductive layer of the touch structure layer close to the base substrate.
  • the negative charge generated by friction on the surface of the cover plate can be guided out by using the edge grounding trace 35.
  • the second touch conductive layer has a larger thickness and a smaller resistance than the first touch conductive layer, and the second touch conductive layer is closer to the cover plate than other conductive layers, by providing the edge grounding trace 35 in the same layer as the second touch conductive layer, most of the static electricity can be effectively guided out, thereby reducing the negative electric field formed inside the display panel and improving the lighting problem caused by the negative electric field.
  • the orthographic projection of the edge grounding trace 35 on the base substrate 30 may not overlap with the orthographic projection of other conductive layers on the base substrate 30.
  • Fig. 5 is a partial enlarged schematic diagram of the area S1 in Fig. 3.
  • Fig. 5 simply illustrates the positions of the gate drive electrode 420 and multiple wirings (for example, including the first ground wiring 331, multiple touch leads 313, protection lines 315, multiple first panel crack detection lines 516, multiple second panel crack detection lines 314, and edge ground wiring 35) in the edge area B2, and omits the other structures.
  • multiple wirings for example, including the first ground wiring 331, multiple touch leads 313, protection lines 315, multiple first panel crack detection lines 516, multiple second panel crack detection lines 314, and edge ground wiring 35
  • the first ground trace 331 may be located on a side of the plurality of touch leads 313 away from the active area AA
  • the protection line 315 may be located between the first ground trace 331 and the plurality of touch leads 313
  • the second panel crack detection line 314 may be located on a side of the first ground trace 331 away from the protection line 315 and the plurality of touch leads 313.
  • the orthographic projections of the first ground trace 331 and the second panel crack detection line 314 on the substrate substrate may overlap with the orthographic projection of the gate drive circuit 420 on the substrate substrate.
  • the orthographic projection of the first panel crack detection line 516 on the substrate substrate may be located between the orthographic projection of the edge ground trace 35 on the substrate substrate and the orthographic projection of the second panel crack detection line 314 on the substrate substrate.
  • the metal trace closest to the side of the orthographic projection of the edge ground trace 35 on the substrate substrate close to the active area AA may be the first panel crack detection line 516.
  • the edge ground trace 35 and the first ground trace 331 may be electrically connected to the same ground pin in the binding region, or may be electrically connected to different ground pins, which is not limited in this embodiment.
  • the width of the edge grounding trace 35 may be greater than the width of the first grounding trace 331.
  • the width of the trace refers to the width of the trace on the display touch substrate formed after being cut by the cutting device.
  • the spacing L1 between the edge grounding trace 35 and the closest first panel crack detection line 516 may be approximately 65 microns to 150 microns, for example, approximately 120 microns.
  • the spacing L2 between the edge grounding trace 35 and the closest second panel crack detection line 314 may be approximately 220 microns to 280 microns, for example, approximately 256 microns.
  • this embodiment is not limited to this.
  • FIG6 is a schematic diagram of the planar position of the display panel and the antenna structure of at least one embodiment of the present disclosure.
  • FIG7 is a schematic diagram of the cross-sectional position of the display panel and the antenna structure of at least one embodiment of the present disclosure.
  • FIG7 only illustrates the base substrate 30, the display structure layer 41, the touch structure layer 31, the polarizer 14, the optical adhesive layer 15 and the cover plate 16 of the display panel 10, and omits illustrating other structures.
  • the antenna structure 50 may be located on a side of the base substrate 30 of the display panel 10 away from the touch structure layer 31.
  • the antenna structure 50 may partially overlap with the display panel 10.
  • the orthographic projection of the antenna structure 50 on the display panel 10 may be located in the edge area B2 of the peripheral area.
  • the overlapping area between the antenna structure 50 and the display panel 10 may be the antenna projection area 500 of the display panel 10.
  • the antenna projection area 500 may be located in the edge area B2 on the right side of the display panel 10.
  • the antenna projection area 500 may be rectangular.
  • the length of the antenna projection area 500 may be approximately 100 millimeters (mm) to 140 mm, such as approximately 122 mm, and the width of the antenna projection area 500 may be approximately 0.10 mm to 0.17 mm, such as approximately 0.15 mm.
  • the antenna projection area 500 may include an upper edge, a lower edge, a left edge, and a right edge; wherein the right edge of the antenna projection area 500 may be flush with the right edge of the display panel 10.
  • the left edge of the antenna projection area 500 may be parallel to the right edge, and the upper edge may be parallel to the lower edge.
  • the orthographic projection of the upper edge of the antenna structure 50 on the display panel 10 may coincide with the upper edge of the antenna projection area 500
  • the orthographic projection of the lower edge of the antenna structure 50 on the display panel 10 may coincide with the lower edge of the antenna projection area 500
  • the orthographic projection of the left edge of the antenna structure 50 on the display panel 10 may coincide with the left edge of the antenna projection area 500
  • the right edge of the antenna structure 50 may not overlap with the display panel 10.
  • the right side of the antenna structure 50 may protrude from the right edge of the display panel 10.
  • this embodiment is not limited to this.
  • the orthographic projection of the right edge of the antenna structure 50 on the display panel 10 may coincide with the right edge of the antenna projection area 500.
  • the orthographic projection of the antenna structure 50 on the display panel 10 may be located in the edge area B2 on the left side of the display panel 10.
  • the non-antenna projection area 501 may surround the antenna projection area 500 on both sides of the second direction D2 and on one side of the first direction D1.
  • the area other than the antenna projection area 500 in the third sub-edge area of the edge area B2 may be the non-antenna projection area 501.
  • the display structure layer 41 has no metal film layer in the antenna projection area 500, and the metal film layer in the antenna projection area 500 only includes the edge ground trace 35.
  • the edge ground trace 35 By setting the edge ground trace 35 to bypass the antenna projection area 500, or reducing the overlapping area between the edge ground trace 35 and the antenna projection area 500, the metal film layer above the antenna structure 50 can be reduced, thereby improving the shielding interference of the display panel 10 to the antenna signal.
  • the edge grounding trace and the second touch conductive layer are taken as the same layer structure.
  • the direction along the effective area AA toward the edge area B2 can be the fourth direction D4, and the direction in the same plane as the fourth direction D4 and intersecting the fourth direction D4 is the fifth direction D5.
  • the fifth direction D5 is in the same plane as the fourth direction D4, and the fifth direction D5 can be perpendicular to the fourth direction D5.
  • the first direction D1 can be parallel to the fourth direction D4, and the second direction D2 can be parallel to the fifth direction D5.
  • FIG8A is a partial plan view of area S2 in FIG6.
  • FIG8B is a schematic view of the edge grounding trace in FIG8A.
  • FIG9 is a partial cross-sectional schematic view along the Q-Q' direction in FIG8A.
  • FIG8A and FIG8B show the partial structure of the edge grounding trace in the non-antenna projection area.
  • FIG10 is a partial plan view of the edge grounding trace in area S3 in FIG6.
  • FIG11 is a partial plan view of area S3 in FIG6 before fine cutting according to the second cutting path X2.
  • FIG10 shows the structure of the edge grounding trace in the antenna projection area and the adjacent non-antenna projection area.
  • the dotted line marked area in FIG10 is the antenna projection area 500, and the area outside the antenna projection area 500 is the non-antenna projection area.
  • Area 500a in FIG11 may be the projection area corresponding to the antenna structure on the display motherboard.
  • the antenna structure may be assembled with the display panel after the display motherboard is cut to obtain the display panel. This embodiment is not limited to this.
  • the edge grounding trace 35 may include: an outer ring trace 351 and an inner ring trace 352.
  • the outer ring trace 351 may be located on the side of the inner ring trace 352 away from the effective area.
  • the edge of the outer ring trace 351 away from the inner ring trace 352 may be obtained by cutting according to the second cutting line X2.
  • the outer ring trace 351 may include: an outer ring trace segment located in the non-antenna projection area (for example, outer ring trace segments 3511 and 3512), an outer ring connecting segment 3513 connecting adjacent outer ring trace segments, and an outer ring extension segment 3514 at least partially located in the antenna projection area 500.
  • the inner ring trace 352 may include: an inner ring trace segment located in the non-antenna projection area (for example, inner ring trace segments 3521 and 3522), and an inner ring connecting segment 3523 connecting adjacent inner ring trace segments.
  • the outer ring routing segment 3512 of the outer ring routing 351 and the inner ring routing segment 3522 of the inner ring routing 352 may be electrically connected through a plurality of first connection routings 353.
  • the plurality of first connection routings 353 may be located between the outer ring routing segment 3512 of the outer ring routing 351 and the inner ring routing segment 3522 of the inner ring routing 352.
  • One end of a single first connection routing 353 is electrically connected to the outer ring routing segment 3512 of the outer ring routing 351, and the other end is electrically connected to the inner ring routing segment 3522 of the inner ring routing 352.
  • the outer ring routing segment 3512 of the outer ring routing 351, the inner ring routing segment 3522 of the inner ring routing 352, and the plurality of first connection routings 353 may be an integral structure.
  • a plurality of first openings 3520 may be provided on the inner ring routing segment 3522 of the inner ring routing 352.
  • the plurality of first openings 3520 may be arranged in a row along the fourth direction D4.
  • the plurality of first openings 3520 may be arranged in sequence along the fifth direction D5 perpendicular to the fourth direction D4.
  • the orthographic projection of the first opening 3520 on the substrate substrate may be a rectangle.
  • the size of the first opening 3520 may be substantially the same as the size of the sub-pixel in the effective area, and the interval between adjacent first openings 3520 may be substantially the same as the interval between adjacent sub-pixels in the effective area.
  • the size of the orthographic projection of the first opening 3520 on the substrate substrate may be approximately 5 microns ⁇ 5 microns.
  • the orthographic projection of the first opening on the substrate substrate may be other shapes such as a circle or an ellipse.
  • the plurality of first openings may be arranged in multiple columns (for example, two columns or three columns) along the fourth direction. In this example, by providing the first opening in the inner ring wiring segment, the direct contact area between the edge ground wiring and the second touch insulating layer can be reduced, thereby reducing the risk of film peeling.
  • the resistance of a single first connection trace 353 may be about 10 ohms to 20 ohms, for example, about 10 ohms.
  • the orthographic projection of the first connection trace 353 on the substrate substrate may be a serpentine trace.
  • a single first connection trace 353 may include a plurality of first extension segments 353a and second extension segments 353b connected in sequence.
  • the first extension segment 353a may extend along the fourth direction D4, and the second extension segment 353b may extend along the fifth direction D5.
  • the second extension segment 353b, the first extension segment 353a and the second extension segment 353b connected in sequence may form a detour.
  • a single first connection trace 353 may include multiple detours.
  • the number of detours of a single first connection trace 353 may be about 3 to 5.
  • a single first connection trace 353 may include 3 detours.
  • the length of the first extension section 353a i.e., the length along the fourth direction D4
  • the length of the second extension section 353b i.e., the length along the fifth direction D5).
  • the width of the first extension section 353a i.e., the length along the fifth direction D5 and the width of the second extension section 353b (i.e., the length along the fourth direction D4) can be substantially the same.
  • the width of the first extension section 353a can be approximately 3 microns to 5 microns, such as approximately 5 microns.
  • the spacing between adjacent second extension sections 353b can be approximately 3 microns to 5 microns, such as approximately 5 microns.
  • the spacing between the second extension section 353b and the outer ring routing segment 3512 of the adjacent outer ring routing 351, and the spacing between the second extension section 353b and the inner ring routing segment 3522 of the adjacent inner ring routing 352 can be substantially the same as the spacing between adjacent second extension sections 353b.
  • this embodiment is not limited to this.
  • the length of the first extension segment of the first connecting line can be greater than the length of the second extension segment, and the first extension segment, the second extension segment, and the first extension segment connected in sequence can form a detour, and the multiple detours can be arranged in sequence along the fifth direction.
  • the outer ring routing segment of the outer ring routing and the inner ring routing segment of the inner ring routing are electrically connected by the first connecting line, and the length of the first connecting line is extended by multiple foldings, so that the grounding resistance can be increased, thereby increasing the resistance of the edge grounding routing and improving the electrostatic protection effect.
  • a plurality of anti-static capacitors 354 may be provided between the outer ring routing segment 3512 of the outer ring routing 351 and the inner ring routing segment 3522 of the inner ring routing 352.
  • the anti-static capacitors 354 may be arranged in the interval between the adjacent first connection routings 353.
  • At least one anti-static capacitor 354 may include a first plate 354a and a second plate 354b.
  • the first plate 354a and the outer ring routing segment 3512 of the outer ring routing 351 may be an integral structure.
  • the second plate 354b may be located on one side of the first plate 354a close to the inner ring routing segment 3522 of the inner ring routing 352.
  • the first plate 354a may be grounded, and the second plate 354b may be a dummy conductive structure.
  • the outer ring routing segment 3512 of the outer ring routing 351, the inner ring routing segment 3522 of the inner ring routing 352, the first connecting routing 353 and the first electrode 354a of the anti-static capacitor 354 can be an integrated structure.
  • the first electrode 354a can have a plurality of first comb teeth facing the second electrode 354b
  • the second electrode 354b can have a plurality of second comb teeth facing the first electrode 354a.
  • the plurality of first comb teeth and the second comb teeth can be interlaced with each other.
  • the overlapping area of the two plates can be increased in a limited space, the capacitor spacing can be reduced, and the capacitance can be increased.
  • this embodiment is not limited to this.
  • the anti-static capacitor can be charged when passing through instantaneous high-voltage static electricity, which plays a voltage-dividing role and improves the risk of electrostatic breakdown.
  • the outer ring routing segments 3511 and 3512 may be located along the fifth direction D5 on opposite sides of the antenna projection area 500.
  • the structure of the outer ring routing segment 3511 and the inner ring routing segment 3521 may refer to the structure between the outer ring routing segment 3512 and the inner ring routing segment 3522, so it will not be described in detail here.
  • the distance between the inner ring routing segment 3521 (or 3522) of the inner ring routing 352 and the second cutting road X2 can be smaller than the distance between the inner ring connecting segment 3523 and the second cutting road X2.
  • the position of the second cutting road X2 can form the right edge of the display panel.
  • the antenna projection area 500 of the display panel may be rectangular, and the antenna projection area 500 may include an upper edge, a lower edge, a left edge, and a right edge.
  • the upper edge and the lower edge of the antenna projection area 500 may be substantially parallel, for example, they may extend along the fourth direction D4, and the left edge and the right edge may be substantially parallel, for example, they may extend along the fifth direction D5.
  • the left edge of the antenna projection area 500 may be located on the side of the right edge close to the effective area.
  • the right edge of the antenna projection area 500 may be flush with the right edge of the base substrate of the display panel.
  • the inner circle connection segment 3523 is connected between the inner circle routing segments 3521 and 3522.
  • the inner circle connection segment 3523 and the inner circle routing segments 3521 and 3522 may be an integral structure.
  • the inner circle routing segments 3521 and 3522 of the inner circle routing 352 may extend along the fifth direction D5, and the inner circle connection segment 3523 may shrink inward in the opposite direction of the fourth direction D4, i.e., shrink toward the side close to the effective area, so as to bypass the antenna projection area 500.
  • the inner ring connection segment 3523 may include a first connection segment 3523a, a second connection segment 3523b, and a third connection segment 3523c connected in sequence.
  • the first connection segment 3523a may be connected to the inner ring routing segment 3521
  • the third connection segment 3523c may be connected to the inner ring routing segment 3522.
  • the second connection segment 3523b is connected between the first connection segment 3523a and the third connection segment 3523c.
  • the first connection segment 3523a may extend along the sixth direction D6, the second connection segment 3523b may extend along the fifth direction D5, and the third connection segment 3523c may extend along the seventh direction D7.
  • the clockwise angle between the first connection segment 3523a and the second connection segment 3523b may be greater than 90 degrees and less than 180 degrees
  • the clockwise angle between the second connection segment 3523b and the third connection segment 3523c may be greater than 90 degrees and less than 180 degrees.
  • the sixth direction D6 may intersect the fifth direction D5 and the fourth direction D4, and the seventh direction D7 may intersect the fourth direction D4, the fifth direction D5, and the sixth direction D6.
  • the sixth direction D6 may be perpendicular to the seventh direction D7.
  • this embodiment is not limited to this.
  • first connecting segment 3523a and the third connecting segment 3523c may both extend along the fourth direction D4, so that the clockwise angle between the first connecting segment 3523a and the second connecting segment 3523b may be approximately 90 degrees, and the clockwise angle between the second connecting segment 3523b and the third connecting segment 3523c may be approximately 90 degrees.
  • first connection segment 3523a, the second connection segment 3523b and the third connection segment 3523c of the inner circle connection segment 3523 may all be straight line segments.
  • this embodiment is not limited to this.
  • the first connection segment and the third connection segment of the inner circle connection segment may be broken line segments or arc segments.
  • the width of the inner ring connection segment 3523 may be substantially the same as the width of the inner ring routing segment 3521 (or 3522).
  • the inner ring connection segment 3523 may be provided with a plurality of first openings 3520.
  • the plurality of first openings 3520 may be arranged in a row along the fourth direction D4.
  • the arrangement of the first openings in the inner ring connection segment may be the same as the arrangement of the first openings in the inner ring routing segment, so it will not be described in detail here. However, this embodiment is not limited to this.
  • the number of columns of the first openings provided on the inner ring routing segment may be greater than the number of columns of the first openings provided on the inner ring connection segment.
  • the plurality of first openings of the inner ring routing segment may be arranged in a plurality of columns, and the plurality of first openings of the inner ring connection segment may be arranged in a row.
  • the distance between the outer ring routing segment 3511 (or 3512) of the outer ring routing 351 and the second cutting path X2 can be less than the distance between the outer ring connecting segment 3523 and the second cutting path X2.
  • the edges of the outer ring routing segments 3511 and 3512 away from the effective area are obtained after cutting according to the second cutting path X2.
  • the outer ring connection segment 3513 is connected between the outer ring routing segments 3511 and 3512.
  • the outer ring connection segment 3513 and the outer ring routing segments 3511 and 3512 may be an integral structure.
  • the outer ring routing segments 3511 and 3512 of the outer ring routing 351 may extend along the fifth direction D5, and the outer ring connection segment 3513 may shrink inward in the opposite direction of the fourth direction D4, that is, shrink toward the side close to the effective area to bypass the antenna projection area 500, so that the outer ring connection segment 3523 of the outer ring routing 351 is located on the side of the antenna projection area 500 close to the inner ring routing 352.
  • the outer ring connection segment 3513 may include: a fourth connection segment 3513a, a fifth connection segment 3513b, and a sixth connection segment 3513c connected in sequence.
  • the fourth connection segment 3513a may be connected to the outer ring routing segment 3511
  • the sixth connection segment 3513c may be connected to the outer ring routing segment 3512.
  • the fifth connection segment 3513b is connected between the fourth connection segment 3513a and the sixth connection segment 3513c.
  • the fourth connection segment 3513a may extend along the sixth direction D6, the fifth connection segment 3513b may extend along the fifth direction D5, and the sixth connection segment 3513c may extend along the seventh direction D7.
  • the clockwise angle between the fourth connection segment 3513a and the fifth connection segment 3513b may be greater than 90 degrees and less than 180 degrees, and the clockwise angle between the fifth connection segment 3513b and the sixth connection segment 3513c may be greater than 90 degrees and less than 180 degrees.
  • this embodiment is not limited to this.
  • the fourth connecting segment 3513a and the sixth connecting segment 3513c can both extend along the fourth direction D4, so that the clockwise angle between the fourth connecting segment 3513a and the fifth connecting segment 3513b can be approximately 90 degrees, and the clockwise angle between the fifth connecting segment 3513b and the sixth connecting segment 3513c can be approximately 90 degrees.
  • the fourth connection segment 3513a, the fifth connection segment 3513b and the sixth connection segment 3513c of the outer ring connection segment 3513 can all be straight line segments. However, this embodiment does not limit this. In other examples, the fourth connection segment and the sixth connection segment of the outer ring connection segment can be broken line segments or arc segments. In this example, the routing form of the outer ring connection segment 3513 can be similar to the routing form of the inner ring connection segment 3523. However, this embodiment does not limit this.
  • the width of the outer ring connection segment 3513 may be smaller than the width of the outer ring routing segment 3511 (or 3512).
  • the width of the outer ring connection segment 3513 may be substantially the same as the width of the inner ring connection segment 3523.
  • the width of the outer ring connection segment 3513 and the width of the inner ring connection segment 3523 may be approximately 15 microns to 25 microns, such as approximately 20 microns.
  • the electrical connection between adjacent outer ring routing segments and the electrical connection between adjacent inner ring routing segments can be ensured, and space occupation can be avoided.
  • a plurality of second openings 3510 may be provided on the outer ring connecting segment 3513.
  • the plurality of second openings 3510 may be arranged in a row along the fourth direction D4.
  • the structure of the second openings 3510 may refer to the structure of the first openings 3520, and the arrangement of the second openings 3510 in the outer ring connecting segment 3513 may be the same as the arrangement of the first openings in the inner ring connecting segment, so it will not be described in detail here.
  • this embodiment is not limited to this.
  • the number of rows of the first openings provided on the inner ring connecting segment may be different from the number of rows of the second openings provided on the outer ring connecting segment.
  • one end of the plurality of outer ring extension segments 3514 of the outer ring routing 351 is connected to the outer ring connecting segment 3513, and the other end can extend to the edge of the substrate along the fourth direction D4.
  • the plurality of outer ring extension segments 3514 and the outer ring connecting segment 3513 can be connected to form a comb-shaped structure.
  • the plurality of outer ring extension segments 3514 can be arranged in sequence between the outer ring routing segments 3511 and 3512 along the fifth direction D5.
  • the shapes and sizes of the plurality of outer ring extension segments 3514 can be substantially the same.
  • the orthographic projection of a single outer ring extension segment 3514 on the substrate can be a rectangle.
  • this embodiment is not limited thereto. In other examples, the shapes or sizes of the plurality of outer ring extension segments can be different.
  • the width F1 of the outer ring routing segment 3511 (or 3512) of the outer ring routing 351 can be about 50 microns to 70 microns, for example, about 60 microns.
  • the distance F2 between the outer ring connecting segment 3513 of the outer ring routing 352 and the edge of the display panel can be about 130 microns to 170 microns, for example, about 150 microns.
  • the distance F3 between adjacent outer ring extension segments 3514 can be about 1500 microns to 2300 microns, for example, about 2000 microns.
  • the distance between the outer ring extension segment 3514 and the adjacent outer ring routing segment 3511 (or 3512) can be roughly the same as the distance between the adjacent outer ring extension segments.
  • the length of at least one outer ring extension segment 3514 along the fourth direction D4 can be roughly the same as the distance between the outer ring connecting segment 3513 and the edge of the display panel.
  • the length F4 of at least one outer ring extension segment 3514 along the fifth direction D5 can be about 130 microns to 170 microns, for example, about 150 microns.
  • the distance F5 between the outer ring connecting section 3513 of the outer ring wiring 351 and the inner ring connecting section 3523 of the inner ring wiring 352 may be approximately 30 micrometers to 40 micrometers, for example, approximately 35 micrometers. However, this embodiment is not limited thereto.
  • the outer ring metal layer 361 can be cut off along the second cutting path X2 to obtain the outer ring routing segment, and the outer ring extension segment 3514 can be cut off along the second cutting path X2.
  • the width F7 of the portion cut by the outer ring metal layer 361 to form the outer ring routing segment can be about 60 microns to 80 microns, such as about 70 microns.
  • the width F8 of the portion cut by the outer ring metal layer 361 to form the outer ring extension segment can be about 50 microns to 70 microns, such as about 60 microns.
  • the fifth connection segment 3513b of the outer ring connection segment 3513 and the second connection segment 3523b of the inner ring connection segment 3523 may be electrically connected via a plurality of second connection traces 355.
  • FIG. 11A only illustrates two second connection traces 355.
  • the plurality of second connection traces 355 may be located between the outer ring connection segment 3513 of the outer ring trace 351 and the inner ring connection segment 3523 of the inner ring trace 352.
  • One end of a single second connection trace 355 is electrically connected to the outer ring connection segment 3513 of the outer ring trace 351, and the other end is electrically connected to the inner ring connection segment 3513 of the inner ring trace 352.
  • the outer ring connection segment 3513 of the outer ring trace 351, the inner ring connection segment 3523 of the inner ring trace 352, and the plurality of second connection traces 355 may be an integral structure.
  • the resistance of a single second connection trace 355 may be substantially the same as the resistance of a single first connection trace 353, for example, may be approximately 10 ohms.
  • the orthographic projection of the second connecting line 355 on the substrate substrate may be a serpentine line.
  • the length F6 of the second connecting line 355 along the fifth direction D5 may be approximately 120 microns to 150 microns, for example, approximately 135 microns.
  • the outer ring connecting section of the outer ring line and the inner ring connecting section of the inner ring line are electrically connected by the second connecting line, and the length of the second connecting line is extended by multiple folding back, so that the grounding resistance can be increased, thereby increasing the resistance of the edge grounding line and improving the electrostatic protection effect.
  • the number of first connection traces 353 and second connection traces 355 can be matched according to the total resistance and capacitance of the edge ground traces to avoid setting too many connection traces, which may cause external charge to be introduced due to too small parallel resistance, making the electrostatic discharge (ESD) test fail, or setting too few connection traces, which may cause the circuit to be burned out by the instantaneous ESD surge current due to process risks.
  • the total number of first connection traces and second connection traces can be less than or equal to 40.
  • the total number of first connection traces and second connection traces can be about 20 to 40, such as about 6, 19, or 40.
  • FIG12 is a schematic diagram of the arrangement of the connection routing of at least one embodiment of the present disclosure.
  • the edge ground routing may include 19 connection routings.
  • the 19 connection routings may be arranged in the edge areas of the upper side, the left side, and the right side, respectively, wherein the edge area of the upper side may be arranged with 5 first connection routings 353, the edge area of the left side may be arranged with 7 first connection routings 353, and the edge area of the right side may be arranged with 1 first connection routing 353 and 6 second connection routings 355.
  • this embodiment is not limited to this.
  • the edge areas of the upper side, the left side, and the right side may each have 2 connection routings.
  • the edge area of the upper side may be arranged with 10 connection routings, and the edge areas of the left side and the right side may each have 15 connection routings.
  • the arrangement positions of the connection lines in the left and right edge regions may be symmetrical with respect to the center line of the display panel in the first direction D1, and the arrangement positions of the connection lines in the upper edge region may be symmetrical with respect to the center line of the display panel in the first direction D1.
  • this embodiment is not limited to this.
  • by controlling the number of connection lines the resistance of the edge grounding line can be increased, and the risk of electrostatic breakdown of the adjacent metal film layer can be reduced.
  • the orthographic projection of the second touch insulating layer 302 on the base substrate 30 may partially overlap with the orthographic projection of the edge grounding trace on the base substrate 30.
  • the second touch insulating layer 302 may cover the inner ring trace 352 but not the outer ring trace 351.
  • the edge of the second touch insulating layer 302 may overlap with the anti-static capacitor 354.
  • by adopting an opening design for the outer ring connecting section 3512 of the inner ring trace 352 and the outer ring trace 351 it is possible to avoid large-area direct contact between the edge grounding trace and the second touch insulating layer 302, and to avoid film peeling.
  • the overlap area between the edge ground trace and the antenna projection area 500 may be less than or equal to 7% of the total area of the antenna projection area 500.
  • the overlap area between the multiple outer ring extensions of the outer ring trace and the antenna projection area may account for less than 7% of the antenna projection area.
  • the overlap area between the edge ground trace and the antenna projection area may account for less than the overlap area between the edge ground trace and the non-antenna projection area in the non-antenna projection area.
  • FIG. 13 is another partial plan view of the edge grounding trace of region S3 in FIG. 6 .
  • the orthographic projection of the outer ring extension section 3514 of the outer ring trace 351 on the substrate substrate may be T-shaped.
  • a single outer ring extension section 3514 may include: a first outer ring extension portion 3514a and a second outer ring extension portion 3514b connected to each other.
  • the first outer ring extension portion 3514a may be located on a side of the second outer ring extension portion 3514b close to the inner ring trace 352.
  • the first outer ring extension portion 3514a may be electrically connected to the outer ring connection section 3513.
  • One end of the second outer ring extension portion 3514b is electrically connected to the first outer ring extension portion 3514a, and the other end extends to the edge of the display panel.
  • the length of the first outer ring extension portion 3514a along the fifth direction D5 may be less than the length of the second outer ring extension portion 3514b along the fifth direction D5.
  • a larger length of the outer ring extension section may be retained along the edge of the display panel, thereby facilitating the derivation of the edge charge of the display panel.
  • the length F14 of the first outer ring extension 3514a along the fifth direction D5 can be about 130 microns to 170 microns, such as about 150 microns.
  • the distance F13 between adjacent second outer ring extensions 3514b can be about 900 microns to 1100 microns, such as about 1000 microns.
  • the length of the second outer ring extension 3514b along the fourth direction D4 can be substantially the same as the width of the outer ring routing segment 3511.
  • the length F12 of the second outer ring extension 3514b along the fourth direction D4 can be about 50 microns to 70 microns, such as about 60 microns, and the length F11 along the fifth direction D5 can be about 1000 microns to 1300 microns, such as about 1150 microns.
  • edge grounding wiring of this embodiment can refer to the description of the aforementioned embodiment, and thus will not be described in detail here.
  • FIG14 is another partial plan view of the edge grounding trace of area S3 in FIG6.
  • the outer ring trace may include: an outer ring trace segment located in a non-antenna projection area (e.g., outer ring trace segments 3511 and 3512), an outer ring connecting segment 3513 at least partially located in the antenna projection area 500, and a plurality of outer ring extension segments 3514 located in the antenna projection area 500.
  • the outer ring connection segment 3513 may extend along the fifth direction D5.
  • the outer ring connection segment 3513 may be a straight line segment.
  • the outer ring connection segment may be a broken line segment or a curved line segment.
  • the spacing F15 between the outer ring connection segment 3513 and the inner ring connection segment 3523 may be approximately 80 microns to 100 microns, for example, 90 microns.
  • the width of the outer ring connection segment 3513 may be approximately the same as the width of the inner ring connection segment 3523, for example, approximately 20 microns.
  • the distance between the side of the outer ring connection segment 3513 away from the edge of the display panel and the edge of the display panel may be approximately the same as the distance between the side of the outer ring routing segment 3511 (or 3512) away from the edge of the display panel and the edge of the display panel.
  • the side of the outer ring connection segment 3513 away from the edge of the display panel may be approximately flush with the side of the outer ring routing segment 3511 (or 3512) away from the edge of the display panel.
  • this embodiment is not limited to this.
  • one end of the plurality of outer ring extension segments 3514 is connected to the outer ring connection segment 3513, and the other end may extend to the edge of the display panel.
  • the plurality of outer ring extension segments 3514 and the outer ring connection segment 3513 may be connected to form a comb-shaped structure.
  • the length F17 of a single outer ring extension segment 3514 along the fifth direction D5 may be approximately 130 microns to 170 microns, such as approximately 150 microns; the spacing F18 between adjacent outer ring extension segments 3514 may be approximately 1800 microns to 2200 microns, such as approximately 2000 microns.
  • this embodiment is not limited thereto.
  • the outer ring connection segment 3513 and the inner ring connection segment 3523 may be electrically connected via a plurality of second connection traces 355.
  • FIG. 14 only illustrates two second connection traces 355.
  • the plurality of second connection traces 355 may be located between the outer ring connection segment 3513 of the outer ring trace 351 and the inner ring connection segment 3523 of the inner ring trace 352.
  • One end of a single second connection trace 355 is electrically connected to the outer ring connection segment 3513 of the outer ring trace 351, and the other end is electrically connected to the inner ring connection segment 3513 of the inner ring trace 352.
  • the outer ring connection segment 3513 of the outer ring trace 351, the inner ring connection segment 3523 of the inner ring trace 352, and the plurality of second connection traces 355 may be an integral structure. At least a portion of the single second connection trace 355 may be located within the antenna projection area 500.
  • the resistance of a single second connection line 355 may be substantially the same as the resistance of a single first connection line 353, for example, may be approximately 10 ohms.
  • the orthographic projection of the second connection line 355 on the substrate substrate may be a serpentine line.
  • the length F16 of the second connection line 355 along the fifth direction D5 may be approximately 100 microns to 120 microns, for example, may be approximately 109 microns.
  • the outer ring connection section of the outer ring line and the inner ring connection section of the inner ring line are electrically connected by the second connection line, and the length of the second connection line is extended by multiple folding backs, so that the grounding resistance can be increased, thereby increasing the resistance of the edge grounding line and improving the electrostatic protection effect.
  • the outer ring connecting section and the outer ring extending section of the edge grounding trace in this example are located in the antenna projection area, and the area of the edge grounding trace located in the antenna projection area is smaller than the area of the edge grounding trace in the non-antenna projection area. This will not cause a large area of metal shielding of the antenna signal. Moreover, by electrically connecting the outer ring connecting section and the inner ring trace through the second connecting trace, static electricity can be better exported and static electricity injuries caused by ESD testing can be prevented.
  • edge grounding wiring of this embodiment can refer to the description of the aforementioned embodiment, and thus will not be described in detail here.
  • FIG. 15 is another partial plan view of the edge grounding routing of area S3 in FIG. 6 .
  • the outer ring routing 351 may include: outer ring routing segments 3511 and 3512 located in the non-antenna projection area.
  • the outer ring routing 351 does not overlap with the antenna projection area 500, and the outer ring routing segments 3511 and 3512 of the outer ring routing 351 may be disconnected in the antenna projection area 500.
  • the distance F19 between the inner ring connecting segment 3523 of the inner ring routing 352 and the edge of the display panel may be approximately 40 microns to 50 microns, for example, may be approximately 45 microns.
  • the antenna projection area is avoided by retracting the inner ring routing 352 to one side of the effective area.
  • the outer ring routing is disconnected to avoid, so that there is no metal film layer in the antenna projection area, and the edge grounding routing does not overlap with the antenna projection area, thereby reducing the shielding interference of the edge grounding routing on the antenna signal, thereby ensuring the performance of the antenna structure.
  • the inner circle routing 352 and the outer circle routing 351 can be electrically connected through the first connecting routing, thereby ensuring that the negative charge generated on the cover surface of the display panel can be discharged, blocking the electrostatic conduction path, reducing the negative electric field formed inside the display panel, and improving the brightening of the display structure layer caused by the negative electric field.
  • edge grounding wiring of this embodiment can refer to the description of the aforementioned embodiment, and thus will not be described in detail here.
  • FIG. 16 is another partial plan view of the edge grounding routing of area S3 in FIG. 6 .
  • the outer ring routing 351 may include: an outer ring routing segment (e.g., outer ring routing ends 3511 and 3512), and an outer ring connecting segment 3513 connecting adjacent outer ring routing segments.
  • the outer ring routing segments 3511 and 3512 and the outer ring connecting segment 3513 may be located in a non-antenna projection area.
  • the outer ring routing 351 does not overlap with the antenna projection area 500, and the outer ring routing segments 3511 and 3512 of the outer ring routing 351 may be disconnected in the antenna projection area 500 and connected through the outer ring connecting segment 3513 in the non-antenna projection area.
  • the width of the outer ring connecting segment 3513 may be less than the width of the outer ring routing segment, and may be substantially the same as the width of the inner ring connecting segment 3523.
  • the outer ring connecting segment 3513 and the inner ring connecting segment 3523 may be electrically connected through a plurality of second connecting routings 355.
  • the inner and outer rings can be electrically connected through the first connecting line and the second connecting line, thereby ensuring that the negative charge generated on the cover surface of the display panel can be guided out, blocking the electrostatic conduction path, reducing the negative electric field formed inside the display panel, and improving the brightness of the display structure layer caused by the negative electric field.
  • edge grounding wiring of this embodiment can refer to the description of the aforementioned embodiment, and thus will not be described in detail here.
  • the display panel provided in this embodiment is provided with an edge grounding line, and the edge grounding line is made to partially or completely avoid the antenna projection area. This can reduce the shielding interference of the display panel on the antenna signal while ensuring that the negative charge generated on the cover surface of the display panel is exported to ensure the display effect of the display panel, thereby ensuring the performance of the antenna structure.
  • the present embodiment also provides a display panel, including a display panel and an antenna structure.
  • the display panel includes an effective area and an edge area located on at least one side of the effective area, and the edge area includes an antenna projection area and a non-antenna projection area located on at least one side of the antenna projection area.
  • the effective area of the display panel includes: a substrate, and a display structure layer and a touch structure layer sequentially arranged on the substrate.
  • the edge area of the display panel includes: a touch lead and an edge grounding trace arranged on the substrate, and the edge grounding trace is located on a side of the touch lead away from the effective area.
  • the touch lead and the edge grounding trace are at least partially arranged in the same layer.
  • the antenna structure overlaps with the antenna projection area of the display panel in the orthographic projection of the display panel.
  • the overlapping area of the edge grounding trace and the antenna projection area is smaller than the overlapping area of the edge grounding trace and the non-antenna projection area.
  • the antenna structure may be located on a side of the base substrate of the display panel away from the touch structure layer.
  • a portion of the edge grounding trace located in the antenna projection area close to the effective area is a first trace
  • a portion of the edge grounding trace located in the non-antenna projection area close to the effective area is a second trace.
  • the distance between the edge of the first trace close to the effective area and the edge of the substrate is greater than the distance between the edge of the second trace close to the effective area and the edge of the substrate.
  • the structure of the display panel provided in this embodiment can be referred to the description of the aforementioned embodiment, and thus will not be described in detail here.
  • the display panel provided in this embodiment can reduce the shielding interference of the display panel on the antenna signal while ensuring that the negative charge generated on the cover surface of the display panel is guided out to ensure the display effect of the display panel, thereby ensuring the performance of the antenna structure.
  • FIG17 is a schematic diagram of a display device of at least one embodiment of the present disclosure.
  • the present embodiment provides a display device 91, comprising a display panel 910 and an antenna structure 920 of the aforementioned embodiment.
  • the orthographic projection of the antenna structure 920 on the display panel 910 may overlap with the antenna projection area of the display panel 910.
  • the display panel 910 may be an OLED display panel with an integrated touch structure.
  • the display device 91 may be any product or component with display and touch functions, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame or a navigator.
  • the display device 91 may be a wearable display device, such as one that can be worn on a human body in some manner.
  • the display device 91 may be a smart watch, a smart bracelet, etc.
  • the present embodiment is not limited to this.

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Abstract

一种显示面板(10)，包括：有效区域(AA)、以及位于有效区域(AA)至少一侧的边缘区域(B2)。边缘区域(B2)包括天线投影区域(500)和位于天线投影区域(500)至少一侧的非天线投影区域(501)。有效区域(AA)包括：衬底基板(30)、以及依次设置在衬底基板(30)上的显示结构层(41)和触控结构层(31)。边缘区域(B2)包括：设置在衬底基板(30)上的隔离坝(513、514)和边缘接地走线(35)。边缘接地走线(35)位于隔离坝(513、514)远离有效区域(AA)的一侧。边缘接地走线(35)与天线投影区域(500)的交叠面积小于边缘接地走线(35)与非天线投影区域(501)的交叠面积。

Description

显示面板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示面板及显示装置。
背景技术
随着便携式电子显示设备的发展，触控技术提供了一种新的人机互动界面，其在使用上更直接、更人性化。将触控技术与平面显示技术整合在一起，形成显示触控装置，可以使得平面显示装置具有触控功能。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示面板及显示装置。
一方面，本实施例提供一种显示面板，包括：有效区域以及位于有效区域至少一侧的边缘区域，边缘区域包括天线投影区域和位于所述天线投影区域至少一侧的非天线投影区域。有效区域包括：衬底基板、以及依次设置在衬底基板上的显示结构层和触控结构层。边缘区域包括：设置在衬底基板上的隔离坝和边缘接地走线。边缘接地走线位于隔离坝远离有效区域的一侧。所述边缘接地走线与所述天线投影区域的交叠面积小于所述边缘接地走线与所述非天线投影区域的交叠面积。
在一些示例性实施方式中，所述边缘接地走线与所述天线投影区域的交叠面积在所述天线投影区域的占比小于或等于7％。
在一些示例性实施方式中，所述边缘接地走线位于所述天线投影区域靠近所述有效区域一侧的部分为第一走线，所述边缘接地走线位于所述非天线投影区域靠近所述有效区域一侧的部分为第二走线。所述第一走线靠近所述有效区域一侧的边缘与所述衬底基板的边缘之间的距离，大于所述第二走线靠近所述有效区域一侧的边缘与所述衬底基板的边缘之间的距离。
在一些示例性实施方式中，所述边缘接地走线包括：外圈走线、内圈走线、以及多个第一连接走线；所述多个第一连接走线连接所述内圈走线和所述外圈走线；所述外圈走线位于所述内圈走线远离所述有效区域的一侧；所述多个第一连接走线位于所述非天线投影区域。
在一些示例性实施方式中，所述内圈走线包括：至少两个内圈走线段以及连接相邻内圈走线段的内圈连接段；所述内圈连接段与所述衬底基板的边缘之间的距离大于所述内圈走线段与所述衬底基板的边缘之间的距离。
在一些示例性实施方式中，所述内圈走线与所述天线投影区域没有交叠，所述内圈走线的内圈连接段位于所述天线投影区域靠近所述有效区域的一侧。
在一些示例性实施方式中，所述内圈走线开设有多个第一开孔，所述多个第一开孔沿着所述有效区域朝向所述边缘区域的方向设置为至少一列。
在一些示例性实施方式中，所述外圈走线与所述天线投影区域没有交叠，所述外圈走线至少包括：位于所述非天线投影区域的两个外圈走线段。
在一些示例性实施方式中，所述外圈走线包括：至少两个外圈走线段以及连接相邻外圈走线段的外圈连接段；所述至少两个外圈走线段位于所述非天线投影区域。所述外圈连接段与所述衬底基板的边缘之间的距离大于所述外圈走线段与所述衬底基板的边缘之间的距离。
在一些示例性实施方式中，所述外圈走线的外圈连接段的宽度小于外圈走线段的宽度。
在一些示例性实施方式中，所述外圈走线的外圈连接段的宽度与所述内圈走线的内圈连接段的宽度大致相同。
在一些示例性实施方式中，所述外圈走线的外圈连接段位于所述天线投影区域靠近所述内圈走线的一侧。
在一些示例性实施方式中，所述外圈连接段开设有多个第二开孔，所述多个第二开孔沿着所述有效区域朝向所述边缘区域的方向设置为至少一列。
在一些示例性实施方式中，所述外圈走线的外圈连接段与所述天线投影区域至少部分交叠。
在一些示例性实施方式中，所述外圈走线还包括：多个外圈延伸段，所 述多个外圈延伸段分别与所述外圈连接段靠近所述衬底基板的边缘的一侧连接，并延伸至所述衬底基板的边缘；所述多个外圈延伸段与所述天线投影区域至少部分交叠。
在一些示例性实施方式中，所述多个外圈延伸段中的至少一个外圈延伸段在所述衬底基板的正投影为矩形或T字型。
在一些示例性实施方式中，所述外圈走线还包括：至少一个第二连接走线；所述外圈走线的外圈连接段通过所述至少一个第二连接走线与所述内圈走线的内圈连接段连接；所述第二连接走线的电阻与所述第一连接走线的电阻大致相同。
在一些示例性实施方式中，所述第一连接走线和第二连接走线在所述衬底基板的正投影为蛇形走线。
在一些示例性实施方式中，所述外圈走线的外圈走线段和相邻的所述内圈走线的内圈走线段之间设置多个防静电电容，至少一个防静电电容包括第一极板和第二极板，所述第一极板与所述外圈走线段为一体结构，所述第二极板位于所述第一极板靠近所述内圈走线段的一侧。
在一些示例性实施方式中，所述第一极板具有面向所述第二极板的多个第一梳齿部，所述第二极板具有面向所述第一极板的多个第二梳齿部，所述多个第一梳齿部和多个第二梳齿部相互穿插。
在一些示例性实施方式中，所述防静电电容的第一极板接地，所述第二极板为虚设的导电结构。
在一些示例性实施方式中，所述触控结构层包括：至少一个触控导电层以及位于所述至少一个触控导电层远离所述衬底基板一侧的第二触控绝缘层，所述第二触控绝缘层的边缘与所述防静电电容存在交叠。
在一些示例性实施方式中，所述触控结构层包括：至少一个触控导电层；所述边缘接地走线与所述触控导电层为同层结构。
在一些示例性实施方式中，所述至少一个触控导电层包括触控走线，所述边缘接地走线位于所述触控走线远离所述有效区域的一侧。
在一些示例性实施方式中，所述触控结构层包括：第一触控导电层、第 二触控导电层、以及位于所述第一触控导电层和所述第二触控导电层之间的第一触控绝缘层，所述第一触控绝缘层的边界位于所述边缘接地走线靠近所述有效区域的一侧。
在一些示例性实施方式中，在所述边缘区域，所述衬底基板的边缘与所述边缘接地走线的边缘平齐。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示面板以及天线结构，所述天线结构位于所述显示面板的衬底基板远离触控结构层的一侧，所述显示面板的天线投影区域与所述天线结构在所述显示面板的正投影存在交叠。
另一方面，本公开实施例提供一种显示装置，包括显示面板以及天线结构。所述显示面板包括有效区域、以及位于所述有效区域至少一侧的边缘区域，所述边缘区域包括天线投影区域和位于所述天线投影区域至少一侧的非天线投影区域。所述显示面板的有效区域包括：衬底基板、以及依次设置在所述衬底基板上的显示结构层和触控结构层。所述显示面板的边缘区域包括：设置在所述衬底基板上的触控引线和边缘接地走线，所述边缘接地走线位于所述触控引线远离所述有效区域的一侧。所述触控引线与所述边缘接地走线至少部分同层设置。所述天线结构在所述显示面板的正投影与所述显示面板的天线投影区域存在交叠。所述边缘接地走线与所述天线投影区域的交叠面积小于所述边缘接地走线与所述非天线投影区域的交叠面积。
在一些示例性实施方式中，所述天线结构位于所述显示面板的衬底基板远离所述触控结构层的一侧。
在一些示例性实施方式中，所述边缘接地走线位于所述天线投影区域靠近所述有效区域一侧的部分为第一走线，所述边缘接地走线位于所述非天线投影区域靠近所述有效区域一侧的部分为第二走线；所述第一走线靠近所述有效区域一侧的边缘与所述衬底基板的边缘之间的距离，大于所述第二走线靠近所述有效区域一侧的边缘与所述衬底基板的边缘之间的距离。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1A为显示面板的盖板表面摩擦产生的负电荷的传导示意图；
图1B为盖板表面摩擦产生的负电荷在显示面板内形成负电场的示意图；
图2为一种显示母板上包括多个显示触控基板的排布示意图；
图3为本公开至少一实施例的显示面板的示意图；
图4为图3中沿P-P’方向的局部剖面示意图；
图5为图3中区域S1的局部放大示意图；
图6为本公开至少一实施例的显示面板与天线结构的平面位置示意图；
图7为本公开至少一实施例的显示面板与天线结构的剖面位置示意图；
图8A为图6中区域S2的局部平面示意图；
图8B为图8A中边缘接地走线的示意图；
图9为图8A中沿Q-Q’方向的局部剖面示意图；
图10为图6中区域S3的边缘接地走线的局部平面示意图；
图11为图6中区域S3在未按照第二切割道X2进行精切割之前的局部平面示意图；
图12为本公开至少一实施例的连接走线的排布示意图；
图13为图6中区域S3的边缘接地走线的另一局部平面示意图；
图14为图6中区域S3的边缘接地走线的另一局部平面示意图；
图15为图6中区域S3的边缘接地走线的另一局部平面示意图；
图16为图6中区域S3的边缘接地走线的另一局部平面示意图；
图17为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为一种或多种形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。其中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏极)与源电极(源电极端子、源区域或源极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本公开中，为区分晶体管除栅电极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源电极或者漏电极，第二极可以为漏电极或源电极，另外，将晶体管的栅电极称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本公开中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“大致相同”是指数值相差10％以内的情况。
在本公开中，“宽度”表示在走线的延伸平面内，与走线延伸方向垂直的方向的长度。
在本说明书中，A沿着B方向延伸是指，A可以包括主体部分和与主体部分连接的次要部分，主体部分是线、线段或条形状体，主体部分沿着B方向伸展，且主体部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。本说明书中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
本公开实施例提供的显示面板可以集成触控结构。显示面板可以包括有机发光二极管(OLED)显示基板，或者可以是量子点发光二极管(QLED，Quantum Dot Light Emitting Diodes)显示基板，或者可以是等离子体显示装置(PDP)显示基板，或者可以是电泳显示(EPD)显示基板，或者可以是 液晶显示(LCD)基板。在一些示例中，显示面板可以包括OLED显示基板，OLED显示基板可以包括：衬底基板、设置在衬底基板上的驱动电路层、设置在驱动电路层上的发光元件层以及设置在发光元件层上的封装层。触控结构设置在显示基板的封装层上，形成触控结构在薄膜封装上(Touch on Thin Film Encapsulation，简称Touch on TFE)的结构，显示结构和触控结构集成在一起，具有轻薄、可折叠等优点，可以满足柔性折叠、窄边框等产品需求。
Touch on TFE结构主要包括柔性多层覆盖表面式(FMLOC，Flexible Multi-Layer On Cell)结构和柔性单层覆盖表面式(FSLOC，Flexible Single-Layer On Cell)结构。FMLOC结构是基于互容检测的工作原理，一般采用两层金属形成驱动(Tx)电极和感应(Rx)电极，集成电路(IC)通过检测驱动电极和感应电极间的互容来实现触控动作。FSLOC结构是基于自容(或电压)检测的工作原理，一般采用单层金属形成触控电极，集成电路通过检测触控电极自容(或电压)来实现触控动作。
图1A为显示面板的盖板表面摩擦产生的负电荷的传导示意图。图1B为盖板表面摩擦产生的负电荷在显示面板内形成负电场的示意图。图1A和图1B所示均为一种显示面板的剖面结构。
如图1A和图1B所示，显示面板可以包括：依次设置的散热膜层(SCF)11、承载膜层(U-film)12、显示触控基板13、偏光片(POL，Polarizer)14、光学胶(OCA，Optically Clear Adhesive)层15、盖板(CG)16。盖板16可以为玻璃盖板。散热膜层11可以包括依次叠设的导电散热层111和不导电散热层112。承载膜层12可以包括依次叠设的第一承载层121和第二承载层122。例如，第一承载层121的材料可以为聚对苯二甲酸乙二酯(PET)，第二承载层122的材料可以为压敏胶(PSA，Pressure Sensitive Adhesive)。显示触控基板13可以包括：依次设置的衬底基板131、显示结构层132和触控结构层133。显示结构层132可以包括：驱动电路层(例如，包括多个像素电路)和发光元件层(例如包括多个发光元件)。像素电路与发光元件电连接，配置为驱动发光元件发光。驱动电路层可以至少包括：半导体层134(例如包括晶体管的有源层)、电源走线135(例如，低压线VSS)、以及信号走线136。在显示面板的边框区域，盖板16和光学胶层15之间涂覆有油墨 17。
如图1A和图1B所示，当用户手指(相当于金属棒)在盖板16表面进行摩擦时，会产生大量负电荷。由于同极性电荷彼此互斥，导致负电荷会扩散运动。由于显示面板的膜层材料大部分为高电阻材料，静电上下传导(即沿垂直剖面方向传导)比横向传导(即沿水平面方向传导)更容易，因此，静电会在盖板16表面积累后向下层传导。由于显示触控基板13的显示结构层132的金属膜层(例如，电源走线135和信号走线136)和触控结构层133的金属膜层可以导走静电，因此，大部分静电更多地是从显示面板的边缘无金属层的位置向下层依次传递。如图1B所示，盖板16、光学胶层15、偏光片14、显示触控基板13和承载膜层12的第二承载层122针对负电荷均具有高传导性，油墨17和散热膜层11的不导电散热层112对负电荷具有中传导性，承载膜层12的第一承载层121对于负电荷的传导能力较低。因此，在盖板16表面产生的负电荷会从显示面板的边缘向下层传递，依次经过光学胶层15、偏光片14、显示触控基板13的绝缘层和衬底基板131，在显示触控基板13的衬底基板131远离盖板16一侧(即背面)聚集形成负电场。在显示触控基板13形成的负电场，会导致驱动电路层的晶体管的阈值电压(Vth)发生正偏，从而造成显示触控基板13发亮的情况。例如，由于绿色子像素启动敏感，显示面板常会表现出画面发绿的显示不良。
在一些实现方式中，显示面板需要与天线结构组装。显示面板与天线结构组装后，显示面板内与天线结构存在交叠的金属膜层会对天线结构产生影响，使得天线结构的全向接收灵敏度(TIS，Total Isotropic Sensitivity)和信号接收发射产生衰减，影响天线结构的性能。
本实施例提供一种显示面板，包括：有效区域、位于有效区域至少一侧的边缘区域，边缘区域包括天线投影区域和位于天线投影区域至少一侧的非天线投影区域。有效区域包括：衬底基板、以及依次设置在衬底基板上的显示结构层和触控结构层。边缘区域包括：设置在衬底基板上的隔离坝和边缘接地走线。边缘接地走线位于隔离坝远离有效区域的一侧。边缘接地走线与天线投影区域的交叠面积小于边缘接地走线与非天线投影区域的交叠面积。
在一些示例中，天线投影区域可以为天线结构在显示面板的投影区域。 天线投影区域和非天线投影区域可以均位于边缘区域内的隔离坝远离有效区域的一侧。天线投影区域和非天线投影区域可以没有交叠。例如，非天线投影区域可以围绕在天线投影区域的周边；或者，非天线投影区域与天线投影区域可以沿一个方向相邻。本实施例对此并不限定。
本实施例提供的显示面板，通过在显示面板的边缘区域设置边缘接地走线，可以将显示面板的盖板表面产生的负电荷导出，从而阻断静电传导路径，减少显示面板内部形成的负电场，改善由于负电场造成的显示结构层发亮情况。而且，通过减少边缘接地走线与天线投影区域的交叠面积，可以减小边缘接地走线对天线结构的全向接收灵敏度和信号接收发射造成的影响，减少边缘接地走线对天线信号的屏蔽干扰，从而保证天线结构的性能。
在一些示例性实施方式中，边缘接地走线与天线投影区域的交叠面积在天线投影区域的占比可以小于或等于7％。其中，边缘接地走线与天线投影区域的交叠面积在天线投影区域的占比可以等于边缘接地走线与天线投影区域的交叠面积与天线投影区域的总面积的比值。在一些示例中，边缘接地走线与天线投影区域可以没有交叠。换言之，边缘接地走线与天线投影区域的交叠面积可以为0。本示例通过设置边缘接地走线完全避让天线结构，可以将显示面板的盖板表面产生的负电荷导出并避免对天线信号的屏蔽干扰。在一些示例中，边缘接地走线与天线投影区域的交叠面积在天线投影区域的占比可以约为7％。本示例通过设置边缘接地走线部分避让天线结构，可以保证将显示面板的盖板表面产生的负电荷导出的效果，而且可以减少对天线信号的屏蔽干扰，使得显示面板的静电导出和天线结构的性能均达到较佳效果。
在一些示例性实施方式中，边缘接地走线可以包括：外圈走线、内圈走线、以及多个第一连接走线。多个第一连接走线连接内圈走线和外圈走线。例如，内圈走线、外圈走线和多个第一连接走线可以为一体结构。外圈走线可以位于内圈走线远离有效区域的一侧。多个第一连接走线可以位于非天线投影区域，换言之，多个第一连接走线与天线投影区域可以没有交叠。本示例可以利用内圈走线、第一连接走线和外圈走线将显示面板的盖板表面产生的负电荷导出，从而阻断静电传导路径，改善显示面板的显示效果。
在一些示例性实施方式中，第一连接走线在衬底基板的正投影可以为蛇 形走线。其中，蛇形走线是一种弯折曲线。例如，走线一端沿一个方向延伸一段距离后，弯折迂回并向与该方向的相反方向延伸一段距离，再次弯折迂回而向该方向延伸，如此反复弯折迂回若干次，形成蛇形走线。本示例通过设置第一连接走线为蛇形走线，可以增加边缘接地走线的电阻，从而防止产生静电击穿，起到保护作用。
在一些示例性实施方式中，内圈走线可以包括：至少两个内圈走线段以及连接相邻内圈走线段的内圈连接段。内圈连接段与衬底基板的边缘之间的距离可以大于内圈走线段与衬底基板的边缘之间的距离。在一些示例中，内圈走线与天线投影区域可以没有交叠，内圈走线的内圈连接段可以位于天线投影区域靠近有效区域的一侧。本示例通过设置内圈连接段向有效区域缩进来绕开天线投影区域，可以减少边缘接地走线与天线投影区域的交叠面积，从而改善边缘接地走线对天线信号的屏蔽干扰。而且，内圈走线在天线投影区域附近保持连续可以确保将显示面板的盖板表面产生的负电荷导出，从而阻断静电传导路径，改善显示面板的显示效果。
在本示例中，某一走线与衬底基板的边缘之间的距离可以指该走线与最邻近的衬底基板边缘之间的距离。在边缘区域，衬底基板的边缘与边缘接地走线的边缘可以平齐。
在一些示例性实施方式中，外圈走线与天线投影区域可以没有交叠。例如，外圈走线可以包括：位于非天线投影区域的两个外圈走线段。两个外圈走线段与天线投影区域没有交叠。换言之，天线投影区域可以不设置外圈走线。本示例通过将外圈走线在天线投影区域截断以避让天线投影区域，可以减少边缘接地走线与天线投影区域的交叠面积，从而改善边缘接地走线对天线信号的屏蔽干扰。
在一些示例性实施方式中，外圈走线可以包括：至少两个外圈走线段、以及连接相邻外圈走线段的外圈连接段。至少两个外圈走线段位于非天线投影区域。外圈连接段与衬底基板的边缘之间的距离可以大于外圈走线段与衬底基板的边缘之间的距离。在一些示例中，外圈走线的外圈连接段可以位于天线投影区域靠近内圈走线的一侧。例如，外圈连接段与天线投影区域可以没有交叠。本示例中通过设置外圈连接段向有效区域缩进来绕开天线投影区 域，从而减少边缘接地走线与天线投影区域的交叠面积，从而改善边缘接地走线对天线信号的屏蔽干扰。而且，外圈走线在天线投影区域附近保持连续可以确保将显示面板的盖板表面产生的负电荷导出，从而阻断静电传导路径，改善显示面板的显示效果。在另一些示例中，外圈走线的外圈连接段与天线投影区域可以存在交叠。例如，外圈连接段的宽度可以小于外圈走线段的宽度。本示例通过减小外圈走线与天线投影区域的交叠面积，可以改善边缘接地走线对天线信号的屏蔽干扰。
在一些示例性实施方式中，边缘接地走线位于天线投影区域靠近有效区域一侧的部分为第一走线，边缘接地走线位于非天线投影区域靠近有效区域一侧的部分为第二走线。第一走线靠近有效区域一侧的边缘与衬底基板的边缘之间的距离，可以大于第二走线靠近有效区域一侧的边缘与衬底基板的边缘之间的距离。在一些示例中，第一走线可以仅包括内圈走线，或者可以包括相互没有连接的内圈走线和外圈走线，或者可以包括相互连接的内圈走线和外圈走线。第二走线可以包括内圈走线、外圈走线以及连接内圈走线和外圈走线的第一连接走线。本实施例对此并不限定。在本示例中，设置边缘接地走线向有效区域一侧缩进来完全避让或部分避让天线投影区域，可以保证将显示面板的盖板表面产生的负电荷导出的效果，并减少对天线信号的屏蔽干扰。
在一些示例性实施方式中，触控结构层可以包括：至少一个触控导电层；边缘接地走线与触控导电层可以为同层结构。例如，触控结构层可以包括多个触控导电层，边缘接地走线可以与距离盖板最近的触控导电层为同层结构，盖板可以位于触控结构层远离衬底基板的一侧。本示例通过设置边缘接地走线与触控导电层同层，可以有效导出大部分静电，从而减小显示面板内部形成的负电场，改善由于负电场造成的发亮问题。
在一些示例性实施方式中，至少一个触控导电层可以包括触控走线，边缘接地走线可以位于触控走线远离有效区域的一侧。例如，触控走线可以包括：多条第二面板裂纹检测线。在边缘区域，多条触控引线、保护线、第一接地走线以及多条第二面板裂纹检测线可以沿着远离有效区域的方向依次设置。
下面通过一些示例对本实施例的显示面板进行举例说明。
在一些示例中，以柔性显示面板为例进行说明。在柔性显示面板的制备过程中，先制备显示母板，然后对显示母板进行切割，从而使显示母板被分割成多个显示触控基板，分开的显示触控基板均可以用于形成单个显示面板。图2为一种显示母板上包括多个显示触控基板的排布示意图。如图2所示，显示母板100上的多个基板区域200呈周期性规则排布，切割区域300位于基板区域200的外侧。基板区域200至少包括有效区域AA和位于有效区域AA至少一侧的绑定区域B1。例如，有效区域AA可以包括规则排布的多个子像素，绑定区域B1可以包括扇出区和绑定引脚。切割区域300内设置有第一切割道X1和第二切割道X2。在显示母板的所有膜层制备完成后，切割设备分别沿着第一切割道X1和第二切割道X2进行粗切割和精切割，形成显示触控基板。
图3为本公开至少一实施例的显示面板的示意图。本示例的显示面板以FMLOC结构为例进行示意。然而，本实施例对此并不限定。在另一些示例中，显示面板可以为FSLOC结构，具有单个触控导电层。
在一些示例中，如图3所示，在平行于显示面板的平面内，显示面板可以包括：有效区域AA、以及位于有效区域AA外围的周边区域。周边区域可以包括：位于有效区域AA一侧的绑定区域B1以及位于有效区域AA其它侧的边缘区域B2。对于叠设的显示基板和触控结构，有效区域AA既可以是触控区域，或者可以是显示区域，以下描述中的触控区域和显示区域均是指有效区域AA。
在一些示例中，如图3所示，触控区域至少可以包括规则排布的多个触控电极，边缘区域B2至少包括多条触控引线、以及边缘接地走线35，绑定区域B1至少包括将多条触控引线、边缘接地走线35连接至外部控制装置的引脚。通过在显示面板的周边区域设置边缘接地走线35，可以将盖板表面产生的负电荷导出，从而阻断静电传导路径，减少显示面板内部形成的负电场，改善由于负电场造成的显示结构层发亮情况。
在一些示例中，触控结构可以为互容式结构。如图3所示，触控区域可以包括多个第一触控单元310和多个第二触控单元320。第一触控单元310 可以具有沿第一方向D1延伸的线形状，多个第一触控单元310可以沿第二方向D2依次排列；第二触控单元320可以具有沿第二方向D2延伸的线形状，多个第二触控单元320可以沿第一方向D1依次排列。其中，第一方向D1与第二方向D2交叉，例如，第一方向D1可以垂直于第二方向D2。每个第一触控单元310可以包括沿第一方向D1依次排列的多个第一触控电极311和第一连接部312，第一触控电极311和第一连接部312交替设置且依次电连接。每个第二触控单元320可以包括沿第二方向D2依次排列的多个第二触控电极321，多个第二触控电极321间隔设置，相邻的第二触控电极321通过第二连接部322彼此电连接。在一些示例中，第二连接部322所在的膜层可以不同于第一触控电极311和第二触控电极321所在的膜层。第一触控电极311和第二触控电极321可以在第三方向D3上交替布置，第三方向D3可以与第一方向D1和第二方向D2均交叉。
在一些示例中，多个第一触控电极311、多个第二触控电极321和多个第一连接部312可以同层设置在触控层，并且可以通过同一次图案化工艺形成，第一触控电极311和第一连接部312可以为相互连接的一体结构。第二连接部322可以设置在桥接层，通过过孔使相邻的第二触控电极321相互电连接，触控层与桥接层之间设置有触控绝缘层。在一些可能的实现方式中，多个第一触控电极311、多个第二触控电极321和多个第二连接部322可以同层设置在触控层，第二触控电极321和第二连接部322可以为相互连接的一体结构，第一连接部312可以设置在桥接层，通过过孔使相邻的第一触控电极311相互电连接。在一些示例中，第一触控电极可以是驱动(Tx)电极，第二触控电极可以是感应(Rx)电极。或者，第一触控电极可以是感应(Rx)电极，第二触控电极可以是驱动(Tx)电极。然而，本实施例对此并不限定。
在一些示例中，第一触控电极311和第二触控电极321可以具有菱形状，例如可以是正菱形，或者是横长的菱形，或者是纵长的菱形。在一些可能的实现方式中，第一触控电极311和第二触控电极321可以具有三角形、正方形、梯形、平行四边形、五边形、六边形和其它多边形中的任意一种或多种，本公开在此不做限定。
在一些示例中，第一触控电极311和第二触控电极321可以是透明导电 电极形式。在另一些示例中，第一触控电极311和第二触控电极321可以是金属网格形式，金属网格由多条金属线交织形成，金属网格包括多个网格图案，网格图案是由多条金属线构成的多边形。金属网格式的第一触控电极311和第二触控电极321具有电阻小、厚度小和反应速度快等优点。
在一些示例中，如图3所示，绑定区域B1位于有效区域AA的一侧，沿着远离有效区域AA的方向(例如，第二方向D2)，绑定区域B1可以包括：依次设置的第一扇出区201、弯折区202、第二扇出区203、防静电区204、驱动芯片区205和绑定引脚区206。第一扇出区201可以设置显示基板的信号传输线和触控引线。显示基板的信号传输线至少可以包括高压线VDD、低压线VSS和多条数据传输线。多条数据传输线配置为以扇出(Fan-out)走线方式连接显示区域的数据线(Data Line)，高压线VDD和低压线VSS配置为分别连接显示基板的高电平电源线和低电平电源线。多条触控引线配置为与绑定引脚区206的多个引脚对应连接。弯折区202可以设置凹槽，凹槽配置为使第二扇出区203、防静电区204、驱动芯片区205和绑定引脚区206弯折到有效区域AA的背面。第二扇出区203可以设置多条触控引线和以扇出走线方式引出的多条数据传输线。防静电区204可以设置防静电电路，防静电电路配置为消除静电。驱动芯片区205可以设置源驱动电路(Driver IC)，源驱动电路配置为与第二扇出区203的多条数据传输线电连接。在一些可能的实现方式中，驱动芯片区205可以设置触控与显示驱动器集成电路(TDDI，Touch and Display Driver Integration)。绑定引脚区206可以设置多个引脚(PIN)，多个引脚与多条触控引线和源驱动电路的多条信号传输线对应电连接，并通过绑定的柔性电路板(FPC)连接外部控制装置。
在一些示例中，如图3所示，边缘区域B2位于有效区域AA远离绑定区域B1的多侧。例如，绑定区域B1可以位于有效区域AA的下侧，边缘区域B2可以位于有效区域AA的上侧、左侧和右侧。边缘区域B2至少设置有边缘接地走线35以及多条触控引线。边缘接地走线35可以从边缘区域B2延伸至绑定区域B1，并在绑定区域B1的绑定引脚区206与接地引脚电连接。
在一些示例中，多条触控引线可以包括多条驱动引线和多条感应引线。以第一触控电极为驱动电极，第二触控电极为感应电极为例，驱动引线的第 一端与第一触控电极的电连接，驱动引线的第二端沿着边缘区域B2延伸到绑定区域B1。感应引线的第一端与第二触控电极电连接，感应引线的第二端沿着边缘区域B2延伸到绑定区域B1。然而，本实施例对此并不限定。
在一些示例中，绑定区域B1和边缘区域B2的外侧设置有第一切割线和第二切割线，第二切割线为精切割线，位于绑定区域B1和边缘区域B2的外围，第二切割线的形状与绑定区域B1和边缘区域B2的外轮廓相同。第一切割线为粗切割线，位于第二切割线的外围，第一切割线的形状与第二切割线的轮廓可以大致相同。在本示例中，边缘接地走线35远离有效区域AA的边缘可以通过第二切割线得到。然而，本实施例对此并不限定。
图4为图3中沿P-P’方向的局部剖面示意图。在一些示例中，如图3和图4所示，在垂直于显示面板的方向上，有效区域AA的显示面板可以包括：衬底基板30、依次设置在衬底基板30上的显示结构层41和触控结构层31。显示结构层41可以包括：依次设置在衬底基板30上的驱动电路层42、发光结构层43和封装层44。触控结构层31以封装层44作为基底。在一些可能的实现方式中，显示结构层可以包括其它膜层，触控结构层与封装层之间可以设置其它膜层，本公开在此不做限定。
在一些示例中，衬底基板30可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高衬底基板的抗水氧能力，半导体层的材料可以采用非晶硅(a-Si)。然而，本实施例对此并不限定。
在一些示例中，有效区域AA的驱动电路层42可以包括构成像素电路的晶体管和存储电容。在图4中以有效区域AA的一个子像素的像素电路的一个晶体管(例如，第一晶体管421)为例进行示意。在一些示例中，如图4所示，有效区域AA的驱动电路层42可以包括：依次设置在衬底基板30上的半导体层、第一绝缘层411、第一栅金属层、第二绝缘层412、第二栅金属层、第三绝缘层413、第一源漏金属层、第四绝缘层414、第一平坦层415、 第二源漏金属层和第二平坦层416。在一些示例中，半导体层至少包括：第一晶体管421的有源层。第一栅金属层至少包括：第一晶体管421的栅电极、像素电路的电容的第一电容极板。第二栅金属层至少包括：像素电路的电容的第二电容极板。第一源漏金属层至少包括：第一晶体管421的第一极和第二极。第二源漏金属层至少包括：阳极连接电极428，阳极连接电极428被配置为连接发光元件的阳极和像素电路。
在一些示例中，第一绝缘层411、第二绝缘层412、第三绝缘层413和第四绝缘层414可以为无机绝缘层，第一平坦层415和第二平坦层416可以为有机绝缘层。例如，第一绝缘层411、第二绝缘层412、第三绝缘层413和第四绝缘层414可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。其中，第一绝缘层411和第二绝缘层412可称之为栅绝缘(GI)层，第三绝缘层413可称之为层间绝缘(ILD)层，第四绝缘层414可称之为钝化(PVX)层。第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
在一些示例中，如图4所示，有效区域AA的发光结构层43可以包括：阳极431、像素定义层434、有机发光层432和阴极433。阳极431设置在第二平坦层416上，通过第二平坦层416上开设的过孔与阳极连接电极428电连接。像素定义层434设置在阳极431和第二平坦层416上，其上设置有像素开口，像素开口暴露出阳极431的至少部分表面，有机发光层432设置在像素开口内，阴极433设置在有机发光层432上，有机发光层432在阳极431和阴极433施加电压的作用下出射相应颜色的光线。在一些示例中，像素定义层434可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等材料。
在一些示例中，如图4所示，有效区域AA的封装层44可以包括叠设的 第一封装层441、第二封装层4442和第三封装层443，第一封装层441和第三封装层443可采用无机材料，第二封装层442可采用有机材料，第二封装层442设置在第一封装层441和第三封装层443之间，可以保证外界水汽无法进入发光结构层43。
在一些示例中，如图4所示，有效区域AA的触控结构层31可以包括：依次叠设的缓冲层(图4中省略示意)、第一触控导电层(TMA)、第一触控绝缘层(TLD)301、第二触控导电层(TMB)和第二触控绝缘层(TOC)302。例如，第一触控导电层可以为前述的桥接层，第二触控导电层可以为前述的触控层。第一触控导电层可以包括第二连接部322，第二触控导电层可以包括第一触控电极311、第二触控电极321以及第一连接部312。在一些示例中，缓冲层和第一触控绝缘层301可以采用无机材料，第二触控绝缘层302可以采用有机材料。例如，缓冲层和第一触控绝缘层301可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第二触控绝缘层302可以采用聚酰亚胺(PI)等。然而，本实施例对此并不限定。
在一些示例中，如图4所示，边缘区域B2沿着远离有效区域AA的方向，可以包括：第一子边缘区域B21、第二子边缘区域B22和第三子边缘区域B23。第一子边缘区域B21至少包括：栅极驱动电路、多条触控引线313以及第一接地走线331。在一些示例中，触控引线313和第一接地走线331可以为双层走线结构。例如，一条触控引线313可以包括电连接的第一子引线313a和第二子引线313b。第一接地走线331可以包括电连接的第一子接地走线331a和第二子接地走线331b。第二子边缘区域B22位于第一子边缘区域B21远离有效区域AA的一侧，第二子边缘区域B22至少包括：第一隔离坝513、第二隔离坝514、以及至少一条(例如三条)第一面板裂纹检测(PCD，Panel Crack Detection)线516。第一面板裂纹检测线516可以配置为对显示结构层41进行检测。第三子边缘区域B23位于第二子边缘区域B12远离有效区域AA的一侧，第三子边缘区域B23可以至少包括：裂缝坝515以及边缘接地走线35。
在一些示例中，如图4所示，第一子边缘区域B21的显示面板可以包括： 衬底基板30以及依次设置在衬底基板30上的驱动电路层42、第一平坦层415、第二平坦层416、第一连接电极512、隔离柱511、阴极433、封装层44、设置在封装层44上的多条第一子引线313a和第一子接地走线331a、第一触控绝缘层301、设置在第一触控绝缘层301上的多条第二子引线313b和第二子接地走线331b、以及第二触控绝缘层302。第一子边缘区域B21的驱动电路层42可以包括构成栅驱动电路的晶体管和存储电容。在一些示例中，第一子边缘区域B21的栅驱动电路可以包括扫描驱动电路和发光控制驱动电路。在图4中边缘区域B2以扫描驱动电路的一个晶体管(例如，第二晶体管422)和一个电容(例如，第一电容424)、以及发光控制驱动电路的一个晶体管(例如，第三晶体管423)和一个电容(例如，第二电容425)为例进行示意。第一子边缘区域B21的驱动电路层的膜层结构可以与有效区域AA的驱动电路层的膜层结构类似，故于此不再赘述。
在一些示例中，如图4所示，第一子接地走线331a和多条第一子引线313a与第一触控导电层可以为同层结构，第二子接地走线331b和多条第二子引线313b与第二触控导电层可以为同层结构，多条第一子引线313a和多条第二子引线313b可以一一对应电连接，从而实现双层走线结构的触控引线313。第一子接地走线331a和第二子接地走线331b电连接，实现双层走线结构的第一接地走线331。在触控引线313和第一接地走线331之间可以设置有保护(Guard)线，保护线315可以包括电连接的第一保护子线315a和第二保护子线315b，第一保护子线315a与第一触控导电层可以为同层结构，第二保护子线315b与第二触控导电层可以为同层结构。换言之，在本示例中，保护线315可以为双层走线结构。第一接地走线331远离触控引线313和保护线315一侧还可以设置至少一条(例如两条)第二面板裂纹检测线314。第二面板裂纹检测线314可以配置为对触控结构层31进行检测。第二面板裂纹检测线314与第二触控导电层可以为同层结构。然而，本实施例对此并不限定。在另一些示例中，第一接地走线331、触控引线313和保护线315可以为单层走线结构，例如可以与第一触控导电层为同层结构或者可以与第二触控导电层为同层结构。
在一些示例中，如图4所示，第二子边缘区域B22的显示面板可以包括： 衬底基板30以及设置在衬底基板30上的复合绝缘层、第一面板裂纹检测线516、低压线426、第二连接电极427、隔离坝(例如，第一隔离坝513和第二隔离坝514)、第一封装层441、第三封装层443、第一触控绝缘层301和第二触控绝缘层302。复合绝缘层可以包括：叠设在衬底基板30上的第一绝缘层411至第三绝缘层413。第一面板裂纹检测线516可以设置在第二绝缘层412上，可以与第二栅金属层为同层结构。低压线426可以与驱动电路层42的第一源漏金属层为同层结构，第二连接电极427可以与驱动电路层42的第二源漏金属层为同层结构。阴极433可以通过第一连接电极512与第二连接电极427电连接，第一连接电极512可以通过第二连接电极427与低压线426电连接。第一隔离坝513位于第二隔离坝514靠近有效区域AA的一侧。第二隔离坝514可以由第一坝基、第二坝基、第三坝基和第四坝基叠设形成。第一隔离坝513可以由第二坝基、第三坝基和第四坝基叠设形成。其中，第一坝基可以与第一平坦层415为同层结构，第二坝基可以与第二平坦层416为同层结构，第三坝基可以与像素定义层434为同层结构，第四坝基可以与隔离柱511为同层结构。然而，本实施例对此并不限定。
在一些示例中，如图4所示，第三子边缘区域B23的显示面板可以包括设置在衬底基板30上的裂缝坝515以及边缘接地走线35。裂缝坝515形成在复合绝缘层上，裂缝坝515可以包括多个间隔设置的裂缝，裂缝可以暴露出衬底基板30。第一平坦层415可以覆盖裂缝坝515。边缘接地走线35可以设置在覆盖裂缝坝515的第一平坦层415上。第二触控绝缘层302可以暴露出边缘接地走线35的部分表面。在一些示例中，第一触控绝缘层301与边缘接地走线35在衬底基板30的正投影可以没有交叠。第一触控绝缘层301的边界可以位于边缘接地走线35靠近有效区域AA的一侧。边缘接地走线35在衬底基板30的正投影与裂缝坝515在衬底基板30的正投影可以部分交叠。然而，本实施例对此并不限定。例如，第一触控绝缘层301与边缘接地走线35在衬底基板30的正投影可以部分交叠。在本示例中，在边缘区域B2形成的凹凸状的裂缝坝515，是用于避免在显示母板切割过程中影响有效区域AA和第一子边缘区域B21的膜层结构，多个间隔设置的裂缝不仅能够减小有效区域AA和第一子边缘区域B21的受力，而且能够截断裂纹向有效区域AA和第一子边缘区域B21方向传递。
在一些示例中，如图4所示，边缘接地走线35与第二触控导电层可以为同层结构。然而，本实施例对此并不限定。在另一些示例中，边缘接地走线可以与触控结构层靠近衬底基板的任一导电层为同层结构。
本示例性实施例中，通过在周边区域的第三子边缘区域B23设置边缘接地走线35，可以将盖板表面摩擦产生的负电荷利用边缘接地走线35导出。而且，由于第二触控导电层相较于第一触控导电层具有较大的厚度和较小的电阻，且第二触控导电层相较于其他导电层更接近盖板，通过设置边缘接地走线35与第二触控导电层同层，可以有效导出大部分静电，从而减小显示面板内部形成的负电场，改善由于负电场造成的发亮问题。
在一些示例中，边缘接地走线35在衬底基板30的正投影与其他导电层在衬底基板30的正投影可以没有交叠。通过设置边缘接地走线35避开下方所有的金属膜层，可以防止对边缘接地走线35下方的金属膜层造成静电击伤。
图5为图3中区域S1的局部放大示意图。图5中简单示意了边缘区域B2内的栅极驱动电极420、以及多条走线(例如包括第一接地走线331、多条触控引线313、保护线315、多条第一面板裂纹检测线516、多条第二面板裂纹检测线314、以及边缘接地走线35)的位置，省略示意了其余结构。
在一些示例中，如图5所示，第一接地走线331可以位于多条触控引线313远离有效区域AA的一侧，保护线315可以位于第一接地走线331和多条触控引线313之间，第二面板裂纹检测线314可以位于第一接地走线331远离保护线315和多条触控引线313的一侧。第一接地走线331和第二面板裂纹检测线314在衬底基板的正投影与栅极驱动电路420在衬底基板的正投影可以存在交叠。第一面板裂纹检测线516在衬底基板的正投影可以位于边缘接地走线35在衬底基板的正投影和第二面板裂纹检测线314在衬底基板的正投影之间。边缘接地走线35在衬底基板的正投影靠近有效区域AA的一侧最接近的金属走线可以为第一面板裂纹检测线516。在一些示例中，边缘接地走线35和第一接地走线331可以在绑定区域与相同的接地引脚电连接，或者可以与不同的接地引脚电连接。本实施例对此并不限定。
在一些示例中，如图5所示，边缘接地走线35的宽度可以大于第一接地走线331的宽度。本示例中，走线的宽度是指经过切割设备切割后形成的显 示触控基板上的走线的宽度。在一些示例中，边缘接地走线35与最接近的第一面板裂纹检测线516之间的间距L1可以约为65微米至150微米，例如可以约为120微米。边缘接地走线35与最接近的第二面板裂纹检测线314之间的间距L2可以约为220微米至280微米，例如可以约为256微米。然而，本实施例对此并不限定。
图6为本公开至少一实施例的显示面板与天线结构的平面位置示意图。图7为本公开至少一实施例的显示面板与天线结构的剖面位置示意图。图7中仅示意了显示面板10的衬底基板30、显示结构层41、触控结构层31、偏光片14、光学胶层15和盖板16，省略示意了其他结构。
在一些示例中，如图6和图7所示，天线结构50可以位于显示面板10的衬底基板30远离触控结构层31的一侧。例如，天线结构50可以与显示面板10部分交叠。天线结构50在显示面板10的正投影可以位于周边区域的边缘区域B2。天线结构50与显示面板10的交叠区域可以为显示面板10的天线投影区域500。例如，天线投影区域500可以位于显示面板10的右侧的边缘区域B2。在一些示例中，天线投影区域500可以为矩形。例如，天线投影区域500的长度可以约为100毫米(mm)至140mm，比如可以约为122mm，天线投影区域500的宽度可以约为0.10mm至0.17mm，比如可以约为0.15mm。天线投影区域500可以包括上边缘、下边缘、左边缘和右边缘；其中，天线投影区域500的右边缘与显示面板10的右侧边缘可以齐平。例如，天线投影区域500的左边缘可以平行于右边缘，上边缘可以平行于下边缘。天线结构50的上边缘在显示面板10的正投影可以与天线投影区域500的上边缘重合，天线结构50的下边缘在显示面板10的正投影可以与天线投影区域500的下边缘重合，天线结构50的左边缘在显示面板10的正投影可以与天线投影区域500的左边缘重合，天线结构50的右边缘可以与显示面板10没有交叠，换言之，天线结构50的右侧部分可以凸出于显示面板10的右侧边缘。然而，本实施例对此并不限定。在另一些示例中，天线结构50的右边缘在显示面板10的正投影可以与天线投影区域500的右边缘重合。在另一些示例中，天线结构50在显示面板10的正投影可以位于显示面板10的左侧的边缘区域B2。在一些示例中，如图6所示，非天线投影区域501可以在第二方向D2的两 侧、以及在第一方向D1的一侧包围天线投影区域500。例如，边缘区域B2的第三子边缘区域内除了天线投影区域500以外的区域可以为非天线投影区域501。
在一些示例中，如图4和图7所示，显示结构层41在天线投影区域500没有金属膜层，天线投影区域500内的金属膜层仅包括边缘接地走线35。通过设置边缘接地走线35绕开天线投影区域500，或者减少边缘接地走线35与天线投影区域500的交叠面积，可以减少天线结构50上方的金属膜层，从而改善显示面板10对天线信号的屏蔽干扰。
下面通过多个示例对边缘接地走线的结构进行举例说明。下述示例中以边缘接地走线与第二触控导电层为同层结构为例。在本示例中，沿着有效区域AA朝向边缘区域B2的方向可以为第四方向D4，与第四方向D4在同一平面内且与第四方向D4交叉的方向为第五方向D5。例如，第五方向D5与第四方向D4位于同一平面内，且第五方向D5可以垂直于第四方向D5。在区域S2和区域S3中，第一方向D1可以平行于第四方向D4，第二方向D2可以平行于第五方向D5。
图8A为图6中区域S2的局部平面示意图。图8B为图8A中边缘接地走线的示意图。图9为图8A中沿Q-Q’方向的局部剖面示意图。图8A和图8B所示为非天线投影区域内的边缘接地走线的局部结构。图10为图6中区域S3的边缘接地走线的局部平面示意图。图11为图6中区域S3在未按照第二切割道X2进行精切割之前的局部平面示意图。图10所示为天线投影区域以及相邻的非天线投影区域内的边缘接地走线的结构。图10内的虚线标识区域为天线投影区域500，天线投影区域500以外所示的区域为非天线投影区域。图11内的区域500a可以为天线结构在显示母板所对应的投影区域。在一些示例中，天线结构可以在显示母板经过切割得到显示面板后与显示面板组装。本实施例对此并不限定。
在一些示例中，如图8A、图8B、图10和图11所示，边缘接地走线35可以包括：外圈走线351和内圈走线352。外圈走线351可以位于内圈走线352远离有效区域的一侧。外圈走线351远离内圈走线352的边缘可以按照第二切割线X2进行切割后得到。外圈走线351可以包括：位于非天线投影 区域的外圈走线段(例如外圈走线段3511和3512)、连接相邻外圈走线段的外圈连接段3513、以及至少部分位于天线投影区域500的外圈延伸段3514。内圈走线352可以包括：位于非天线投影区域的内圈走线段(例如内圈走线段3521和3522)、以及连接相邻内圈走线段的内圈连接段3523。
在一些示例中，如图8A和8B所示，外圈走线351的外圈走线段3512和内圈走线352的内圈走线段3522可以通过多个第一连接走线353电连接。多个第一连接走线353可以位于外圈走线351的外圈走线段3512和内圈走线352的内圈走线段3522之间。单个第一连接走线353的一端与外圈走线351的外圈走线段3512电连接，另一端与内圈走线352的内圈走线段3522电连接。外圈走线351的外圈走线段3512、内圈走线352的内圈走线段3522和多个第一连接走线353可以为一体结构。
在一些示例中，如图8A和图8B所示，内圈走线352的内圈走线段3522上可以开设有多个第一开孔3520。多个第一开孔3520可以沿第四方向D4排布为一列。多个第一开孔3520可以沿垂直于第四方向D4的第五方向D5依次排布。在一些示例中，第一开孔3520在衬底基板的正投影可以为矩形。例如，第一开孔3520的大小与有效区域的子像素的尺寸可以大致相同，相邻第一开孔3520的间隔与有效区域的相邻子像素的间隔可以大致相同。例如，第一开孔3520在衬底基板的正投影的尺寸可以约为5微米×5微米。然而，本实施例对此并不限定。例如，第一开孔在衬底基板的正投影可以为圆形或椭圆形等其他形状。又如，多个第一开孔可以沿第四方向排布为多列(例如，两列或三列)。本示例中，通过在内圈走线段设置第一开孔，可以减小边缘接地走线与第二触控绝缘层的直接接触面积，从而降低膜层剥落风险。
在一些示例中，如图8A和图8B所示，单个第一连接走线353的电阻可以约为10欧姆至20欧姆，例如可以约为10欧姆。第一连接走线353在衬底基板的正投影可以为蛇形走线。例如，单个第一连接走线353可以包括多个依次连接的第一延伸段353a和第二延伸段353b。第一延伸段353a可以沿第四方向D4延伸，第二延伸段353b可以沿第五方向D5延伸。依次连接的第二延伸段353b、第一延伸段353a和第二延伸段353b可以形成一个迂回。多个迂回可以沿第四方向D4依次排布。单个第一连接走线353可以包括多个 迂回。例如，单个第一连接走线353的迂回个数可以约为3至5个。如图8B所示，单个第一连接走线353可以包括3个迂回。在一些示例中，第一延伸段353a的长度(即沿第四方向D4的长度)可以小于第二延伸段353b的长度(即沿第五方向D5的长度)。第一延伸段353a的宽度(即沿第五方向D5的长度)与第二延伸段353b的宽度(即沿第四方向D4的长度)可以大致相同。例如，第一延伸段353a的宽度可以约为3微米至5微米，比如可以约为5微米。相邻第二延伸段353b之间的间距可以约为3微米至5微米，比如可以约为5微米。第二延伸段353b与相邻的外圈走线351的外圈走线段3512之间的间距、第二延伸段353b与相邻的内圈走线352的内圈走线段3522之间的间距可以与相邻第二延伸段353b之间的间距大致相同。然而，本实施例对此并不限定。例如，第一连接走线的第一延伸段的长度可以大于第二延伸段的长度，依次连接的第一延伸段、第二延伸段和第一延伸段可以形成一个迂回，多个迂回可以沿第五方向依次排布。本示例性实施方式中，利用第一连接走线电连接外圈走线的外圈走线段和内圈走线的内圈走线段，且通过多次折回的方式延长第一连接走线的长度，可以提高接地电阻，从而增加边缘接地走线的电阻，并提升静电防护效果。
在一些示例中，如图8A和图8B所示，外圈走线351的外圈走线段3512和内圈走线352的内圈走线段3522之间可以设置多个防静电电容354。防静电电容354可以排布在相邻第一连接走线353之间的间隔内。至少一个防静电电容354可以包括第一极板354a和第二极板354b。第一极板354a与外圈走线351的外圈走线段3512可以为一体结构。第二极板354b可以位于第一极板354a靠近内圈走线352的内圈走线段3522的一侧。第一极板354a可以接地，第二极板354b可以为虚设的导电结构。在本示例中，外圈走线351的外圈走线段3512、内圈走线352的内圈走线段3522、第一连接走线353和防静电电容354的第一极板354a可以为一体结构。第一极板354a可以具有面向第二极板354b的多个第一梳齿部，第二极板354b可以具有面向第一极板354a的多个第二梳齿部。多个第一梳齿部和第二梳齿部可以相互穿插。如此一来，可以在有限空间内增大两个极板的交叠面积，减小电容间距，从而增大电容量。然而，本实施例对此并不限定。在本示例中，通过在内圈走线的内圈走线段和外圈走线的外圈走线段之间设置防静电电容，可以在通过 瞬时高压静电时对防静电电容充电，起到分压作用，改善静电击穿风险。
在一些示例中，如图10所示，外圈走线段3511和3512可以沿第五方向D5位于天线投影区域500的相对两侧。关于外圈走线段3511与内圈走线段3521的结构可以参照外圈走线段3512与内圈走线段3522之间的结构，故于此不再赘述。
在一些示例中，如图10和图11所示，内圈走线352的内圈走线段3521(或3522)与第二切割道X2之间的距离可以小于内圈连接段3523与第二切割道X2之间的距离。在图11中，第二切割道X2所在位置可以形成显示面板的右侧边缘。
在一些示例中，如图10所示，显示面板的天线投影区域500可以为矩形，天线投影区域500可以包括上边缘、下边缘、左边缘和右边缘。天线投影区域500的上边缘与下边缘可以大致平行，例如可以沿第四方向D4延伸，左边缘与右边缘可以大致平行，例如可以沿第五方向D5延伸。天线投影区域500的左边缘可以位于右边缘靠近有效区域的一侧。天线投影区域500的右边缘与显示面板的衬底基板的右侧边缘可以齐平。
在一些示例中，如图10所示，内圈连接段3523连接在内圈走线段3521和3522之间。内圈连接段3523和内圈走线段3521和3522可以为一体结构。在区域S3内，内圈走线352的内圈走线段3521和3522可以沿第五方向D5延伸，内圈连接段3523可以沿第四方向D4的反方向内缩，即向靠近有效区域一侧收缩，以绕过天线投影区域500。
在一些示例中，如图10所示，内圈连接段3523可以包括依次连接的第一连接段3523a、第二连接段3523b和第三连接段3523c。第一连接段3523a可以与内圈走线段3521连接，第三连接段3523c可以与内圈走线段3522连接。第二连接段3523b连接在第一连接段3523a和第三连接段3523c之间。第一连接段3523a可以沿第六方向D6延伸，第二连接段3523b可以沿第五方向D5延伸，第三连接段3523c可以沿第七方向D7延伸。第一连接段3523a和第二连接段3523b之间的顺时针夹角可以大于90度且小于180度，第二连接段3523b与第三连接段3523c之间的顺时针夹角可以大于90度且小于180度。其中，第六方向D6可以与第五方向D5和第四方向D4交叉，第七方向 D7可以与第四方向D4、第五方向D5和第六方向D6均交叉，例如第六方向D6可以垂直于第七方向D7。然而，本实施例对此并不限定。在另一些示例中，第一连接段3523a和第三连接段3523c可以均沿第四方向D4延伸，使得第一连接段3523a和第二连接段3523b之间的顺时针夹角可以约为90度，第二连接段3523b与第三连接段3523c之间的顺时针夹角可以约为90度。
在一些示例中，如图10所示，内圈连接段3523的第一连接段3523a、第二连接段3523b和第三连接段3523c可以均为直线段。然而，本实施例对此并不限定。在另一些示例中，内圈连接段的第一连接段和第三连接段可以为折线段、或者弧线段。
在一些示例中，如图10所示，内圈连接段3523的宽度与内圈走线段3521(或3522)的宽度可以大致相同。内圈连接段3523上可以开设有多个第一开孔3520。多个第一开孔3520可以沿第四方向D4排布为一列。关于第一开孔在内圈连接段的排布方式可以与第一开孔在内圈走线段的排布方式相同，故于此不再赘述。然而，本实施例对此并不限定。在另一些示例中，内圈走线段上设置的第一开孔的列数可以大于内圈连接段上开设的第一开孔的列数。例如，内圈走线段的多个第一开孔可以排布为多列，内圈连接段的多个第一开孔可以排布为一列。
在一些示例中，如图10和图11所示，外圈走线351的外圈走线段3511(或3512)与第二切割道X2之间的距离可以小于外圈连接段3523与第二切割道X2之间的距离。外圈走线段3511和3512远离有效区域的边缘为按照第二切割道X2进行切割后得到的。
在一些示例中，如图10所示，外圈连接段3513连接在外圈走线段3511和3512之间。外圈连接段3513和外圈走线段3511和3512可以为一体结构。在区域S3内，外圈走线351的外圈走线段3511和3512可以沿第五方向D5延伸，外圈连接段3513可以沿第四方向D4的反方向内缩，即向靠近有效区域一侧收缩，以绕过天线投影区域500，使得外圈走线351的外圈连接段3523位于天线投影区域500靠近内圈走线352的一侧。
在一些示例中，如图10所示，外圈连接段3513可以包括：依次连接的第四连接段3513a、第五连接段3513b和第六连接段3513c。第四连接段3513a 可以与外圈走线段3511连接，第六连接段3513c可以与外圈走线段3512连接。第五连接段3513b连接在第四连接段3513a和第六连接段3513c之间。第四连接段3513a可以沿第六方向D6延伸，第五连接段3513b可以沿第五方向D5延伸，第六连接段3513c可以沿第七方向D7延伸。第四连接段3513a和第五连接段3513b之间的顺时针夹角可以大于90度且小于180度，第五连接段3513b与第六连接段3513c之间的顺时针夹角可以大于90度且小于180度。然而，本实施例对此并不限定。在另一些示例中，第四连接段3513a和第六连接段3513c可以均沿第四方向D4延伸，使得第四连接段3513a和第五连接段3513b之间的顺时针夹角可以约为90度，第五连接段3513b与第六连接段3513c之间的顺时针夹角可以约为90度。
在一些示例中，如图10所示，外圈连接段3513的第四连接段3513a、第五连接段3513b和第六连接段3513c可以均为直线段。然而，本实施例对此并不限定。在另一些示例中，外圈连接段的第四连接段和第六连接段可以为折线段、或者弧线段。在本示例中，外圈连接段3513的走线形态可以与内圈连接段3523的走线形态类似。然而，本实施例对此并不限定。
在一些示例中，如图10所示，外圈连接段3513的宽度可以小于外圈走线段3511(或3512)的宽度。外圈连接段3513的宽度可以与内圈连接段3523的宽度大致相同。例如，外圈连接段3513的宽度与内圈连接段3523的宽度可以约为15微米至25微米，比如可以约为20微米。本示例通过设置外圈连接段的宽度与内圈连接段的宽度大致相同，既可以保证相邻外圈走线段之间的电连接，也可以保证相邻内圈走线段之间的电连接，还可以避免空间占用。
在一些示例中，如图10所示，外圈连接段3513上可以开设有多个第二开孔3510。多个第二开孔3510可以沿第四方向D4排布为一列。关于第二开孔3510的结构可以参照第一开孔3520的结构，关于第二开孔3510在外圈连接段3513的排布方式可以与第一开孔在内圈连接段的排布方式相同，故于此不再赘述。然而，本实施例对此并不限定。在另一些示例中，内圈连接段上设置的第一开孔的列数可以不同于外圈连接段上设置的第二开孔的列数。
在一些示例中，如图10所示，外圈走线351的多个外圈延伸段3514的一端与外圈连接段3513连接，另一端可以沿第四方向D4延伸至衬底基板的 边缘。多个外圈延伸段3514与外圈连接段3513可以连接形成梳齿状结构。多个外圈延伸段3514可以沿第五方向D5依次排布在外圈走线段3511和3512之间。多个外圈延伸段3514的形状和尺寸可以大致相同。例如，单个外圈延伸段3514在衬底基板的正投影可以为矩形。然而，本实施例对此并不限定。在另一些示例中，多个外圈延伸段的形状或尺寸可以不同。
在一些示例中，如图10所示，外圈走线351的外圈走线段3511(或3512)的宽度F1可以约为50微米至70微米，例如可以约为60微米。外圈走线352的外圈连接段3513与显示面板边缘之间的距离F2可以约为130微米至170微米，例如可以约为150微米。相邻外圈延伸段3514之间的距离F3可以约为1500微米至2300微米，比如可以约为2000微米。外圈延伸段3514与相邻的外圈走线段3511(或3512)之间的距离与相邻外圈延伸段之间的距离可以大致相同。至少一个外圈延伸段3514沿第四方向D4的长度可以与外圈连接段3513与显示面板边缘之间的距离大致相同。至少一个外圈延伸段3514沿第五方向D5的长度F4可以约为130微米至170微米，例如可以约为150微米。外圈走线351的外圈连接段3513与内圈走线352的内圈连接段3523之间的距离F5可以约为30微米至40微米，比如可以约为35微米。然而，本实施例对此并不限定。
在一些示例中，如图11所示，外圈金属层361沿第二切割道X2切割掉部分可以得到外圈走线段，沿第二切割道X2切割掉部分可以得到外圈延伸段3514。其中，外圈金属层361形成外圈走线段所切割的部分的宽度F7可以约为60微米至80微米，比如可以约为70微米。外圈金属层361形成外圈延伸段所切割的部分的宽度F8可以约为50微米至70微米，比如可以约为60微米。
在一些示例中，如图10所示，外圈连接段3513的第五连接段3513b和内圈连接段3523的第二连接段3523b可以通过多个第二连接走线355电连接。图11A中仅示意了两个第二连接走线355。多个第二连接走线355可以位于外圈走线351的外圈连接段3513和内圈走线352的内圈连接段3523之间。单个第二连接走线355的一端与外圈走线351的外圈连接段3513电连接，另一端与内圈走线352的内圈连接段3513电连接。外圈走线351的外圈连接段 3513、内圈走线352的内圈连接段3523和多个第二连接走线355可以为一体结构。单个第二连接走线355的电阻与单个第一连接走线353的电阻可以大致相同，例如可以约为10欧姆。通过设置第二连接走线和第一连接走线的电阻大致相同，可以保证显示面板周边的静电导出效果的一致性。
在一些示例中，如图10所示，第二连接走线355在衬底基板的正投影可以为蛇形走线。第二连接走线355沿第五方向D5的长度F6可以约为120微米至150微米，比如可以约为135微米。本示例性实施方式中，利用第二连接走线电连接外圈走线的外圈连接段和内圈走线的内圈连接段，且通过多次折回的方式延长第二连接走线的长度，可以提高接地电阻，从而增加边缘接地走线的电阻，并提升静电防护效果。
在一些示例中，第一连接走线353和第二连接走线355的数量可以根据边缘接地走线的总电阻和电容的数量来匹配，以避免设置过多的连接走线导致因并联电阻过小而引入外部电荷，使静电释放(ESD，Electro-Static Discharge)测试失效，或者设置太少的连接走线导致因工艺风险而使线路被瞬间ESD浪涌电流烧断失效。在一些示例中，第一连接走线和第二连接走线的总数目可以小于或等于40个。例如，第一连接走线和第二连接走线的总数目可以约为20至40个，比如可以约为6个、19个或40个。
图12为本公开至少一实施例的连接走线的排布示意图。在一些示例中，如图12所示，边缘接地走线可以包括19个连接走线。19个连接走线可以分别排布在上侧、左侧和右侧的边缘区域，其中，上侧的边缘区域可以排布5个第一连接走线353，左侧边缘区域可以分别排布7个第一连接走线353，右侧边缘区域可以排布1个第一连接走线353和6个第二连接走线355。然而，本实施例对此并不限定。例如，上侧、左侧和右侧的边缘区域可以分别2个连接走线。又如，上侧的边缘区域可以排布10个连接走线，左侧和右侧的边缘区域可以分别排布15个连接走线。
在一些示例中，左侧和右侧边缘区域内的连接走线的排布位置可以相对于显示面板在第一方向D1的中心线对称，上侧边缘区域内的连接走线的排布位置可以关于显示面板在第一方向D1的中心线对称。然而，本实施例对此并不限定。本示例性实施方式中，通过控制连接走线的数量，可以实现增 加边缘接地走线的电阻，而且减小对相邻金属膜层的静电击穿风险。
在一些示例中，如图9所示，第二触控绝缘层302在衬底基板30上的正投影与边缘接地走线在衬底基板30的正投影可以部分交叠。例如，第二触控绝缘层302可以覆盖内圈走线352，不覆盖外圈走线351。第二触控绝缘层302的边缘可以与防静电电容354存在交叠。在本示例中，通过对内圈走线352和外圈走线351的外圈连接段3512采用开孔设计，可以避免边缘接地走线与第二触控绝缘层302大面积直接接触，可以避免膜层剥落情况。
在一些示例中，如图10所示，边缘接地走线与天线投影区域500的交叠面积可以小于或等于天线投影区域500的总面积的7％。在本示例中，外圈走线的多个外圈延伸段与天线投影区域的交叠面积在天线投影区域的占比可以小于7％。在一些示例中，边缘接地走线与天线投影区域的交叠面积在天线投影区域的占比，可以小于边缘接地走线与非天线投影区域的交叠面积在非天线投影区域的占比。通过控制边缘接地走线位于天线投影区域的面积，可以减少对天线结构的干涉影响，并保证静电导出效果。
图13为图6中区域S3的边缘接地走线的另一局部平面示意图。在一些示例中，如图13所示，外圈走线351的外圈延伸段3514在衬底基板的正投影可以为T字型。单个外圈延伸段3514可以包括：相互连接的第一外圈延伸部3514a和第二外圈延伸部3514b。第一外圈延伸部3514a可以位于第二外圈延伸部3514b靠近内圈走线352的一侧。第一外圈延伸部3514a可以与外圈连接段3513电连接。第二外圈延伸部3514b的一端与第一外圈延伸部3514a电连接，另一端延伸至显示面板的边缘。第一外圈延伸部3514a沿第五方向D5的长度可以小于第二外圈延伸部3514b沿第五方向D5的长度。在本示例中，通过设置T字型的外圈延伸段，可以沿显示面板的边缘保留更大长度的外圈延伸段，从而有利于导出显示面板的边缘电荷。
在一些示例中，如图13所示，第一外圈延伸部3514a沿第五方向D5的长度F14可以约为130微米至170微米，比如可以约为150微米。相邻第二外圈延伸部3514b之间的距离F13可以约为900微米至1100微米，比如可以为约1000微米。第二外圈延伸部3514b沿第四方向D4的长度与外圈走线段3511的宽度可以大致相同。例如，第二外圈延伸部3514b沿第四方向D4 的长度F12可以约为50微米至70微米，比如可以约为60微米，沿第五方向D5的长度F11可以约为1000微米至1300微米，比如可以约为1150微米。
关于本实施例的边缘接地走线的其余结构可以参照前述实施例的说明，故于此不再赘述。
图14为图6中区域S3的边缘接地走线的另一局部平面示意图。在一些示例中，如图14所示，外圈走线可以包括：位于非天线投影区域的外圈走线段(例如外圈走线段3511和3512)、至少部分位于天线投影区域500的外圈连接段3513、以及位于天线投影区域500的多个外圈延伸段3514。
在一些示例中，如图14所示，外圈连接段3513可以沿第五方向D5延伸。在区域S3中，外圈连接段3513可以为直线段。在另一些示例中，外圈连接段可以为折线段或曲线段。外圈连接段3513与内圈连接段3523之间的间距F15可以约为80微米至100微米，比如可以为90微米。外圈连接段3513的宽度与内圈连接段3523的宽度可以大致相同，例如可以约为20微米。外圈连接段3513远离显示面板边缘的侧面与显示面板边缘之间的距离与外圈走线段3511(或3512)远离显示面板边缘的侧面与显示面板边缘之间的距离可以大致相同。换言之，外圈连接段3513远离显示面板边缘的侧面与外圈走线段3511(或3512)远离显示面板边缘的侧面可以大致齐平。然而，本实施例对此并不限定。
在一些示例中，如图14所示，多个外圈延伸段3514的一端与外圈连接段3513连接，另一端可以延伸至显示面板的边缘。例如，多个外圈延伸段3514与外圈连接段3513可以连接形成梳齿状结构。例如，单个外圈延伸段3514沿第五方向D5的长度F17可以约为130微米至170微米，比如可以约为150微米；相邻外圈延伸段3514之间的间距F18可以约为1800微米至2200微米，比如可以约为2000微米。然而，本实施例对此并不限定。
在一些示例中，如图14所示，外圈连接段3513和内圈连接段3523可以通过多个第二连接走线355电连接。图14中仅示意了两个第二连接走线355。多个第二连接走线355可以位于外圈走线351的外圈连接段3513和内圈走线352的内圈连接段3523之间。单个第二连接走线355的一端与外圈走线351的外圈连接段3513电连接，另一端与内圈走线352的内圈连接段3513电连 接。外圈走线351的外圈连接段3513、内圈走线352的内圈连接段3523和多个第二连接走线355可以为一体结构。单个第二连接走线355的至少部分可以位于天线投影区域500内。单个第二连接走线355的电阻与单个第一连接走线353的电阻可以大致相同，例如可以约为10欧姆。第二连接走线355在衬底基板的正投影可以为蛇形走线。第二连接走线355沿第五方向D5的长度F16可以约为100微米至120微米，比如可以约为109微米。本示例性实施方式中，利用第二连接走线电连接外圈走线的外圈连接段和内圈走线的内圈连接段，且通过多次折回的方式延长第二连接走线的长度，可以提高接地电阻，从而增加边缘接地走线的电阻，并提升静电防护效果。
本示例的边缘接地走线的外圈连接段和外圈延伸段位于天线投影区域内，且位于天线投影区域的边缘接地走线的面积小于非天线投影区域内的边缘接地走线的面积，如此一来不会造成大面积金属屏蔽天线信号的情况，而且，通过第二连接走线电连接外圈连接段和内圈走线，可以更好地导出静电并且防止ESD测试中造成的静电击伤情况。
关于本实施例的边缘接地走线的其余结构可以参照前述实施例的说明，故于此不再赘述。
图15为图6中区域S3的边缘接地走线的另一局部平面示意图。在一些示例中，如图54所示，外圈走线351可以包括：位于非天线投影区域的外圈走线段3511和3512。本示例中，外圈走线351与天线投影区域500没有交叠，外圈走线351的外圈走线段3511和3512在天线投影区域500可以断开。内圈走线352的内圈连接段3523与显示面板边缘之间的距离F19可以约为40微米至50微米，比如可以约为45微米。通过内圈走线352向有效区域一侧内缩来避让天线投影区域。本示例中，通过对内圈走线进行内缩避让，将外圈走线断开避让，使得天线投影区域内没有金属膜层，边缘接地走线与天线投影区域没有交叠，从而减少边缘接地走线对天线信号的屏蔽干扰，从而保证天线结构的性能。在非天线投影区域，内圈走线352和外圈走线351可以通过第一连接走线电连接，从而确保可以将显示面板的盖板表面产生的负电荷导出，阻断静电传导路径，减少显示面板内部形成的负电场，改善由于负电场造成的显示结构层发亮情况。
关于本实施例的边缘接地走线的其余结构可以参照前述实施例的说明，故于此不再赘述。
图16为图6中区域S3的边缘接地走线的另一局部平面示意图。在一些示例中，如图16所示，外圈走线351可以包括：外圈走线段(例如外圈走线端3511和3512)、以及连接相邻外圈走线段的外圈连接段3513。外圈走线段3511和3512以及外圈连接段3513可以位于非天线投影区域。本示例中，外圈走线351与天线投影区域500没有交叠，外圈走线351的外圈走线段3511和3512在天线投影区域500可以断开，并通过非天线投影区域的外圈连接段3513进行连接。外圈连接段3513的宽度可以小于外圈走线段的宽度，并可以与内圈连接段3523的宽度大致相同。外圈连接段3513和内圈连接段3523可以通过多个第二连接走线355电连接。
本示例中，通过对内圈走线和外圈走线进行内缩避让，使得天线投影区域内没有金属膜层，边缘接地走线与天线投影区域没有交叠，从而减少边缘接地走线对天线信号的屏蔽干扰，从而保证天线结构的性能。在非天线投影区域，内圈走线和外圈走线可以通过第一连接走线和第二连接走线电连接，从而确保可以将显示面板的盖板表面产生的负电荷导出，阻断静电传导路径，减少显示面板内部形成的负电场，改善由于负电场造成的显示结构层发亮情况。
关于本实施例的边缘接地走线的其余结构可以参照前述实施例的说明，故于此不再赘述。
本实施例提供的显示面板通过设置边缘接地走线，并使得边缘接地走线部分或完全避让天线投影区域，可以在确保将显示面板的盖板表面产生的负电荷导出以保证显示面板的显示效果基础上，减少显示面板对天线信号的屏蔽干扰，从而保证天线结构的性能。
本实施例还提供一种显示面板，包括显示面板以及天线结构。显示面板包括有效区域、以及位于有效区域至少一侧的边缘区域，边缘区域包括天线投影区域和位于天线投影区域至少一侧的非天线投影区域。显示面板的有效区域包括：衬底基板、以及依次设置在衬底基板上的显示结构层和触控结构层。显示面板的边缘区域包括：设置在衬底基板上的触控引线和边缘接地走 线，边缘接地走线位于触控引线远离有效区域的一侧。触控引线与边缘接地走线至少部分同层设置。天线结构在显示面板的正投影与显示面板的天线投影区域存在交叠。边缘接地走线与天线投影区域的交叠面积小于边缘接地走线与非天线投影区域的交叠面积。
在一些示例性实施方式中，天线结构可以位于显示面板的衬底基板远离触控结构层的一侧。
在一些示例性实施方式中，边缘接地走线位于天线投影区域靠近有效区域一侧的部分为第一走线，边缘接地走线位于非天线投影区域靠近有效区域一侧的部分为第二走线。第一走线靠近有效区域一侧的边缘与衬底基板的边缘之间的距离，大于第二走线靠近有效区域一侧的边缘与衬底基板的边缘之间的距离。
关于本实施例提供的显示面板的结构可以参照前述实施例的说明，故于此不再赘述。
本实施例提供的显示面板通过在触控引线远离有效区域一侧设置边缘接地走线，并使得边缘接地走线部分或完全避让天线投影区域，可以在确保将显示面板的盖板表面产生的负电荷导出以保证显示面板的显示效果基础上，减少显示面板对天线信号的屏蔽干扰，从而保证天线结构的性能。
图17为本公开至少一实施例的显示装置的示意图。如图17所示，本实施例提供一种显示装置91，包括前述实施例的显示面板910和天线结构920。天线结构920在显示面板910的正投影可以与显示面板910的天线投影区域存在交叠。在一些示例中，显示面板910可以为集成触控结构的OLED显示面板。显示装置91可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示和触控功能的产品或部件。在一些示例性实施方式中，显示装置91可以为穿戴式显示装置，例如可以通过某些方式佩戴在人体上。比如，显示装置91可以为智能手表、智能手环等。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (30)

  1. 一种显示面板，包括：有效区域、以及位于所述有效区域至少一侧的边缘区域，所述边缘区域包括天线投影区域和位于所述天线投影区域至少一侧的非天线投影区域；
    所述有效区域包括：衬底基板、以及依次设置在所述衬底基板上的显示结构层和触控结构层；
    所述边缘区域包括：设置在所述衬底基板上的隔离坝和边缘接地走线；所述边缘接地走线位于所述隔离坝远离所述有效区域的一侧；
    所述边缘接地走线与所述天线投影区域的交叠面积小于所述边缘接地走线与所述非天线投影区域的交叠面积。
  2. 根据权利要求1所述的显示面板，其中，所述边缘接地走线与所述天线投影区域的交叠面积在所述天线投影区域的占比小于或等于7％。
  3. 根据权利要求1或2所述的显示面板，其中，所述边缘接地走线位于所述天线投影区域靠近所述有效区域一侧的部分为第一走线，所述边缘接地走线位于所述非天线投影区域靠近所述有效区域一侧的部分为第二走线；
    所述第一走线靠近所述有效区域一侧的边缘与所述衬底基板的边缘之间的距离，大于所述第二走线靠近所述有效区域一侧的边缘与所述衬底基板的边缘之间的距离。
  4. 根据权利要求1至3中任一项所述的显示面板，其中，所述边缘接地走线包括：外圈走线、内圈走线、以及多个第一连接走线；所述多个第一连接走线连接所述内圈走线和所述外圈走线；所述外圈走线位于所述内圈走线远离所述有效区域的一侧；所述多个第一连接走线位于所述非天线投影区域。
  5. 根据权利要求4所述的显示面板，其中，所述内圈走线包括：至少两个内圈走线段以及连接相邻内圈走线段的内圈连接段；所述内圈连接段与所述衬底基板的边缘之间的距离大于所述内圈走线段与所述衬底基板的边缘之间的距离。
  6. 根据权利要求5所述的显示面板，其中，所述内圈走线与所述天线投影区域没有交叠，所述内圈走线的内圈连接段位于所述天线投影区域靠近所 述有效区域的一侧。
  7. 根据权利要求4至6中任一项所述的显示面板，其中，所述内圈走线开设有多个第一开孔，所述多个第一开孔沿着所述有效区域朝向所述边缘区域的方向设置为至少一列。
  8. 根据权利要求5至7中任一项所述的显示面板，其中，所述外圈走线与所述天线投影区域没有交叠，所述外圈走线至少包括：位于所述非天线投影区域的两个外圈走线段。
  9. 根据权利要求5至7中任一项所述的显示面板，其中，所述外圈走线包括：至少两个外圈走线段以及连接相邻外圈走线段的外圈连接段；所述至少两个外圈走线段位于所述非天线投影区域；
    所述外圈连接段与所述衬底基板的边缘之间的距离大于所述外圈走线段与所述衬底基板的边缘之间的距离。
  10. 根据权利要求9所述的显示面板，其中，所述外圈走线的外圈连接段的宽度小于外圈走线段的宽度。
  11. 根据权利要求9所述的显示面板，其中，所述外圈走线的外圈连接段的宽度与所述内圈走线的内圈连接段的宽度大致相同。
  12. 根据权利要求9至11中任一项所述的显示面板，其中，所述外圈走线的外圈连接段位于所述天线投影区域靠近所述内圈走线的一侧。
  13. 根据权利要求12所述的显示面板，其中，所述外圈连接段开设有多个第二开孔，所述多个第二开孔沿着所述有效区域朝向所述边缘区域的方向设置为至少一列。
  14. 根据权利要求9至11中任一项所述的显示面板，其中，所述外圈走线的外圈连接段与所述天线投影区域至少部分交叠。
  15. 根据权利要求12至14中任一项所述的显示面板，其中，所述外圈走线还包括：多个外圈延伸段，所述多个外圈延伸段分别与所述外圈连接段靠近所述衬底基板的边缘的一侧连接，并延伸至所述衬底基板的边缘；所述多个外圈延伸段与所述天线投影区域至少部分交叠。
  16. 根据权利要求15所述的显示面板，其中，所述多个外圈延伸段中的 至少一个外圈延伸段在所述衬底基板的正投影为矩形或T字型。
  17. 根据权利要求9至16中任一项所述的显示面板，其中，所述外圈走线还包括：至少一个第二连接走线；所述外圈走线的外圈连接段通过所述至少一个第二连接走线与所述内圈走线的内圈连接段连接；所述第二连接走线的电阻与所述第一连接走线的电阻大致相同。
  18. 根据权利要求17所述的显示面板，其中，所述第一连接走线和第二连接走线在所述衬底基板的正投影为蛇形走线。
  19. 根据权利要求8至18中任一项所述的显示面板，其中，所述外圈走线的外圈走线段和相邻的所述内圈走线的内圈走线段之间设置多个防静电电容，至少一个防静电电容包括第一极板和第二极板，所述第一极板与所述外圈走线段为一体结构，所述第二极板位于所述第一极板靠近所述内圈走线段的一侧。
  20. 根据权利要求19所述的显示面板，其中，所述第一极板具有面向所述第二极板的多个第一梳齿部，所述第二极板具有面向所述第一极板的多个第二梳齿部，所述多个第一梳齿部和多个第二梳齿部相互穿插。
  21. 根据权利要求19或20所述的显示面板，其中，所述防静电电容的第一极板接地，所述第二极板为虚设的导电结构。
  22. 根据权利要求19至21中任一项所述的显示面板，其中，所述触控结构层包括：至少一个触控导电层以及位于所述至少一个触控导电层远离所述衬底基板一侧的第二触控绝缘层，所述第二触控绝缘层的边缘与所述防静电电容存在交叠。
  23. 根据权利要求1至21中任一项所述的显示面板，其中，所述触控结构层包括：至少一个触控导电层；所述边缘接地走线与所述触控导电层为同层结构。
  24. 根据权利要求23所述的显示面板，其中，所述至少一个触控导电层包括触控走线，所述边缘接地走线位于所述触控走线远离所述有效区域的一侧。
  25. 根据权利要求1至24中任一项所述的显示面板，其中，所述触控结 构层包括：第一触控导电层、第二触控导电层、以及位于所述第一触控导电层和所述第二触控导电层之间的第一触控绝缘层，所述第一触控绝缘层的边界位于所述边缘接地走线靠近所述有效区域的一侧。
  26. 根据权利要求1至25中任一项所述的显示面板，其中，在所述边缘区域，所述衬底基板的边缘与所述边缘接地走线的边缘平齐。
  27. 一种显示装置，包括如权利要求1至26中任一项所述的显示面板以及天线结构，所述天线结构位于所述显示面板的衬底基板远离触控结构层的一侧，所述显示面板的天线投影区域与所述天线结构在所述显示面板的正投影存在交叠。
  28. 一种显示装置，包括：显示面板以及天线结构，所述显示面板包括有效区域、以及位于所述有效区域至少一侧的边缘区域，所述边缘区域包括天线投影区域和位于所述天线投影区域至少一侧的非天线投影区域；所述显示面板的有效区域包括：衬底基板、以及依次设置在所述衬底基板上的显示结构层和触控结构层；所述边缘区域包括：设置在所述衬底基板上的触控引线和边缘接地走线；所述边缘接地走线位于所述触控引线远离所述有效区域的一侧；所述触控引线与所述边缘接地走线至少部分同层设置；
    所述天线结构在所述显示面板的正投影与所述显示面板的天线投影区域存在交叠；所述边缘接地走线与所述天线投影区域的交叠面积小于所述边缘接地走线与所述非天线投影区域的交叠面积。
  29. 根据权利要求28所述的显示装置，其中，所述天线结构位于所述显示面板的衬底基板远离所述触控结构层的一侧。
  30. 根据权利要求28或29所述的显示装置，其中，所述边缘接地走线位于所述天线投影区域靠近所述有效区域一侧的部分为第一走线，所述边缘接地走线位于所述非天线投影区域靠近所述有效区域一侧的部分为第二走线；所述第一走线靠近所述有效区域一侧的边缘与所述衬底基板的边缘之间的距离，大于所述第二走线靠近所述有效区域一侧的边缘与所述衬底基板的边缘之间的距离。
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CN112083826A (zh) * 2019-06-13 2020-12-15 三星显示有限公司 显示面板和包括该显示面板的显示装置
CN112612323A (zh) * 2020-12-28 2021-04-06 维沃移动通信有限公司 显示模组和电子设备
CN113311964A (zh) * 2021-06-10 2021-08-27 京东方科技集团股份有限公司 触控面板及显示装置
CN113972484A (zh) * 2020-07-22 2022-01-25 东友精细化工有限公司 天线插入式电极结构和图像显示装置
CN216979737U (zh) * 2022-01-29 2022-07-15 京东方科技集团股份有限公司 显示面板及显示触控装置
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CN112083826A (zh) * 2019-06-13 2020-12-15 三星显示有限公司 显示面板和包括该显示面板的显示装置
CN113972484A (zh) * 2020-07-22 2022-01-25 东友精细化工有限公司 天线插入式电极结构和图像显示装置
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