WO2024087079A1 - Mems器件及其制备方法、电子设备 - Google Patents

Mems器件及其制备方法、电子设备 Download PDF

Info

Publication number
WO2024087079A1
WO2024087079A1 PCT/CN2022/127808 CN2022127808W WO2024087079A1 WO 2024087079 A1 WO2024087079 A1 WO 2024087079A1 CN 2022127808 W CN2022127808 W CN 2022127808W WO 2024087079 A1 WO2024087079 A1 WO 2024087079A1
Authority
WO
WIPO (PCT)
Prior art keywords
dielectric layer
gap
sub
dielectric
filling structure
Prior art date
Application number
PCT/CN2022/127808
Other languages
English (en)
French (fr)
Inventor
刘建兴
郭景文
吴倩红
李春昕
曹子博
赵建昀
曲峰
李必奇
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/127808 priority Critical patent/WO2024087079A1/zh
Publication of WO2024087079A1 publication Critical patent/WO2024087079A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H49/00—Apparatus or processes specially adapted to the manufacture of relays or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H59/00—Electrostatic relays; Electro-adhesion relays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P1/00—Auxiliary devices
    • H01P1/18—Phase-shifters

Definitions

  • the present invention belongs to the technical field of micro-electromechanical systems, and in particular relates to a MEMS device and a preparation method thereof, and an electronic device.
  • MEMS Micro-Electro-Mechanical System
  • MEMS is a micro device or system that integrates micro sensors, micro actuators, micro mechanical structures, micro power sources, signal processing and control circuits, high-performance electronic integrated devices, interfaces, and communications.
  • MEMS is a revolutionary new technology that is widely used in high-tech industries and is a key technology related to the country's scientific and technological development, economic prosperity, and national defense security. With the rapid development of the information age, MEMS devices with high integration, miniaturization, multi-functions, and low cost will bring huge economic value.
  • the present invention aims to solve at least one of the technical problems existing in the prior art, and provides a MEMS device and a preparation method thereof, and an electronic device.
  • the present disclosure provides a MEMS device, which includes:
  • the driving electrode, the first reference electrode and the second reference electrode are arranged on the dielectric substrate, and the first reference electrode and the second reference electrode are respectively located on both sides of the extending direction of the driving electrode;
  • a first dielectric layer covering a side of the driving electrode away from the dielectric substrate
  • the membrane bridge is arranged on the side of the first dielectric layer away from the dielectric substrate, and the two ends of the orthographic projection of the membrane bridge on the dielectric substrate are respectively located on the orthographic projections of the first reference electrode and the second reference electrode on the dielectric substrate; the driving electrode is located in the space enclosed by the membrane bridge and the dielectric substrate;
  • first gap between the first reference electrode and the driving electrode; there is a second gap between the second reference electrode and the driving electrode;
  • the thickness of the first dielectric layer located in the first gap and the second gap is greater than the thickness of the driving electrode; and/or, a second dielectric layer is arranged on the side of the bridge deck of the membrane bridge close to the dielectric substrate, and the orthographic projection of the second dielectric layer on the dielectric substrate at least covers the orthographic projection of the driving electrode on the dielectric substrate.
  • the first dielectric layer when the thickness of the first dielectric layer located in the first gap and the second gap is greater than the thickness of the driving electrode, the first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer sequentially arranged in a direction away from the dielectric substrate;
  • the second sub-dielectric layer includes a first filling structure and a second filling structure; the first filling structure and the second filling structure are respectively located in the first gap and the second gap.
  • the first sub-dielectric layer covers the first gap and the second gap, and the first sub-dielectric layer forms a first groove in the first gap, and the second sub-dielectric layer forms a second groove in the second gap; the first filling structure fills the first groove, and the second filling structure fills the second groove.
  • the material of the second sub-medium layer includes resin glue.
  • the second dielectric layer when the second dielectric layer is arranged on a side of the bridge surface of the membrane bridge close to the dielectric substrate, the second dielectric layer has a first protruding portion protruding toward the first dielectric layer.
  • the bridge deck of the membrane bridge has a second protrusion protruding toward the first medium layer, and the second protrusion is arranged in a one-to-one correspondence with the first protrusion, and the second protrusion is embedded in the corresponding first protrusion.
  • the surface of the first dielectric layer facing the second dielectric layer has a first recessed portion; the first recessed portion is arranged in one-to-one correspondence with the first protruding portion.
  • the first dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer which are sequentially arranged in a direction away from the substrate;
  • the second sub-dielectric layer includes a first filling structure and a second filling structure; the first filling structure and the second filling structure are respectively located in the first gap and the second gap.
  • the first filling structure and the second filling structure both have a first surface in contact with the first sub-dielectric layer, a second surface arranged opposite to the dielectric substrate, and a first connecting surface connecting the first surface and the second surface; the first connecting surface and the first sub-dielectric layer define the first recessed portion.
  • the material of the second sub-medium layer includes resin glue.
  • the first dielectric layer when the thickness of the first dielectric layer located at the first gap and the second gap is greater than the thickness of the driving electrode, the first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer sequentially arranged in a direction close to the dielectric substrate;
  • the second sub-dielectric layer includes a first filling structure and a second filling structure; the first filling structure and the second filling structure are respectively located in the first gap and the second gap.
  • the material of the second sub-medium layer includes resin glue.
  • the present disclosure provides a method for preparing a MEMS device, which includes:
  • a driving electrode, a first reference electrode and a second reference electrode are formed on the dielectric substrate; the first reference electrode and the second reference electrode are respectively located on both sides of the extending direction of the driving electrode;
  • a membrane bridge is formed on the side of the first dielectric layer away from the dielectric substrate; the two ends of the orthographic projection of the membrane bridge on the dielectric substrate are respectively located on the orthographic projections of the first reference electrode and the second reference electrode on the dielectric substrate; the driving electrode is located in the space enclosed by the membrane bridge and the dielectric substrate;
  • a first gap is defined between the first reference electrode and the driving electrode; a second gap is defined between the second reference electrode and the driving electrode; a thickness of a portion of the first dielectric layer located in the first gap and the second gap is greater than a thickness of the driving electrode; and/or,
  • the preparation method further includes: providing a second dielectric layer on a side of the bridge surface of the membrane bridge close to the dielectric substrate, and the orthographic projection of the second dielectric layer on the dielectric substrate at least covers the orthographic projection of the driving electrode on the dielectric substrate.
  • the step of forming the first dielectric layer includes:
  • a first sub-dielectric layer and a second sub-dielectric layer are sequentially formed in a direction away from the dielectric substrate; the second sub-dielectric layer includes a first filling structure and a second filling structure; the first filling structure and the second filling structure are respectively located in the first gap and the second gap.
  • the preparation method when the preparation method includes providing the second dielectric layer on a side of the bridge surface of the membrane bridge close to the dielectric substrate, before forming the second dielectric layer, it also includes:
  • a sacrificial layer is formed on a surface of the first dielectric layer that is away from the dielectric substrate; wherein a second recessed portion is provided on a side of the sacrificial layer that is away from the dielectric substrate;
  • the second dielectric layer is formed on a side of the sacrificial layer away from the dielectric substrate, and the formed second dielectric layer has a first protruding portion protruding toward one side of the dielectric substrate; the first protruding portion and the second recessed portion are arranged in a one-to-one correspondence;
  • the method further includes removing the sacrificial layer.
  • the preparation method includes providing the second dielectric layer on the side of the bridge surface of the membrane bridge close to the dielectric substrate
  • the step of forming the first dielectric layer comprises:
  • a first sub-dielectric layer and a second sub-dielectric layer are sequentially formed in a direction away from the dielectric substrate;
  • the second sub-dielectric layer comprises a first filling structure and a second filling structure;
  • the first filling structure and the second filling structure are respectively located in the first gap and the second gap;
  • the step of forming the second sub-dielectric layer comprises:
  • Filling materials are formed in the first gap and the second gap, and annealed to form the first filling structure and the second filling structure; the first filling structure and the second filling structure each have a first surface in contact with the first sub-dielectric layer, a second surface arranged opposite to the dielectric substrate, and a first connecting surface connecting the first surface and the second surface; the first connecting surface and the first sub-dielectric layer define the first recessed portion;
  • the method further includes:
  • a sacrificial layer is formed on the surface of the first dielectric layer away from the dielectric substrate; wherein the sacrificial layer has a second recessed portion on a side away from the dielectric substrate; and the second recessed portion is arranged in one-to-one correspondence with the first recessed portion;
  • the second dielectric layer is formed on a side of the sacrificial layer away from the dielectric substrate, and the formed second dielectric layer has a first protruding portion protruding toward one side of the dielectric substrate; the first protruding portion and the second recessed portion are arranged in a one-to-one correspondence;
  • the method further includes removing the sacrificial layer.
  • the bridge surface of the formed membrane bridge has a second protruding portion protruding toward the first dielectric layer, and the second protruding portion is arranged in a one-to-one correspondence with the first protruding portion, and the second protruding portion is embedded in the corresponding first protruding portion.
  • the step of forming the first dielectric layer includes:
  • a second sub-dielectric layer and a first sub-dielectric layer are sequentially formed in a direction away from the dielectric substrate;
  • the second sub-dielectric layer comprises a first filling structure and a second filling structure;
  • the first filling structure and the second filling structure are respectively located in the first gap and the second gap;
  • the step of forming the second sub-dielectric layer comprises:
  • the second sub-dielectric material layer is heated to reshape the second sub-dielectric material layer to backfill the first gap and the second gap to form the first filling structure and the second filling structure.
  • the step of forming the first dielectric layer includes:
  • a second sub-dielectric layer and a first sub-dielectric layer are sequentially formed in a direction away from the dielectric substrate;
  • the second sub-dielectric layer comprises a first filling structure and a second filling structure;
  • the first filling structure and the second filling structure are respectively located in the first gap and the second gap;
  • the step of forming the second sub-dielectric layer comprises:
  • a chemical mechanical polishing and flattening process is adopted to remove the portion of the second sub-dielectric material layer protruding from the first gap and the second gap, so as to form the first filling structure and the second filling structure filling the first gap and the second gap respectively.
  • An embodiment of the present disclosure provides an electronic device, which includes any of the above-mentioned MEMS devices.
  • FIG. 1 is a schematic diagram of an exemplary MEMS device in an open state as a switching device.
  • FIG. 2 is a schematic diagram of an exemplary MEMS device in an off state as a switching device.
  • FIG. 3 is a schematic diagram of an exemplary MEMS device in an open state as another switching device.
  • FIG. 4 is a schematic diagram of an exemplary MEMS device in an off state as another switching device.
  • FIG. 5 is a schematic structural diagram of a MEMS device according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a first exemplary MEMS device according to an embodiment of the present disclosure.
  • FIG. 7 is a flow chart of the preparation of the MEMS device shown in FIG. 6 .
  • FIG. 8 is a schematic structural diagram of a second exemplary MEMS device according to an embodiment of the present disclosure.
  • FIG. 9 is a flow chart of the preparation of the MEMS device shown in FIG. 8 .
  • FIG. 10 is a schematic structural diagram of a third exemplary MEMS device according to an embodiment of the present disclosure.
  • FIG. 11 is a flow chart of the preparation of the MEMS device shown in FIG. 10 .
  • FIG. 12 is a schematic structural diagram of a fourth exemplary MEMS device according to an embodiment of the present disclosure.
  • FIG. 13 is a flow chart of the preparation of the MEMS device shown in FIG. 12 .
  • FIG. 14 is a schematic diagram of the structure of a fifth exemplary MEMS device according to an embodiment of the present disclosure.
  • FIG. 15 is a flow chart of manufacturing the MEMS device shown in FIG. 14 .
  • FIG. 16 is another preparation flow chart of the MEMS device shown in FIG. 14 .
  • Micro-Electro-Mechanical System also known as micro-electro-mechanical system, microsystem, micromachine, etc.
  • MEMS Micro-Electro-Mechanical System
  • the MEMS device in the disclosed embodiment can be any device based on MEMS, for example: it can be used for RF switches, probe detection, and resonant beams. It is also applicable to the design and application of other microstructures such as circular diaphragms and polygonal diaphragms, including but not limited to accelerometers, angular velocity meters, miniature microphones, micro-electromechanical interference displays, micro-electromechanical capacitive ultrasonic transducers, micromirrors and other structures.
  • FIG1 is a schematic diagram of an exemplary MEMS device in the open state as a switch device
  • FIG2 is a schematic diagram of an exemplary MEMS device in the closed state as a switch device
  • the MEMS device 100 includes a dielectric substrate, a drive electrode 30, a first reference electrode and a second reference electrode arranged on the dielectric substrate 10, a first dielectric layer 40 covering the drive electrode 30, and a membrane bridge 20 arranged above the first dielectric layer 40, wherein the membrane bridge 20 includes a bridge deck 21 and connecting arms 22 connected to both ends of the bridge deck structure 21.
  • the bridge deck 21 of the membrane bridge 20 spans the drive electrode and has a certain distance from the first dielectric layer 40 above the drive electrode 30.
  • the membrane bridge 20 and the dielectric substrate 10 enclose an active space.
  • the first reference electrode 51 and the second reference electrode 52 are respectively located on both sides of the extension direction of the drive electrode 30, and the three can constitute a CPW transmission line structure.
  • the first reference electrode 21 and the second reference electrode 52 can be used to write reference ground signals.
  • FIGS. 1 and 2 a MEMS switch with a dual-arm fixed beam structure is shown in FIGS. 1 and 2 .
  • the MEMS switch may also include only one connecting arm 22, that is, the MEMS switch is a cantilever beam structure.
  • FIG. 3 is a schematic diagram of an exemplary MEMS device in an open state as another switching device;
  • FIG. 4 is a schematic diagram of an exemplary MEMS device in an off state as another switching device.
  • the working principle of this switch is the same as that of the above-mentioned MEMS switch with a dual-arm fixed beam structure, so it will not be repeated here.
  • the inventors found that when the first dielectric layer covers the driving electrode, due to mechanical properties, the thickness of the first dielectric layer covering the surface of the driving electrode facing away from the dielectric substrate is greater than the thickness covering the side of the driving electrode, that is, the thickness of the first dielectric layer on the side of the driving electrode is thinner. As a result, when the membrane bridge is pulled down, the distance between the membrane bridge and the driving electrode below is too close, which will cause tip discharge and there is a risk of breaking down the first dielectric layer on the side of the driving electrode and causing damage to the device.
  • FIG5 is a schematic diagram of the structure of a MEMS device of the embodiment of the present disclosure; as shown in FIG5, the MEMS device in the embodiment of the present disclosure includes a dielectric substrate 10, a driving electrode 30, a first reference electrode 51, a second reference electrode 52, a first dielectric layer 40 and a membrane bridge arranged on the dielectric substrate 10.
  • the first reference electrode 51 and the second reference electrode 52 are respectively located on both sides of the extension direction of the driving electrode 30, and there is a first gap Q1 between the first reference electrode 51 and the driving electrode 30, and there is a second gap Q2 between the second reference electrode 52 and the driving electrode 30.
  • the first dielectric layer 40 at least covers the driving electrode 30.
  • the membrane bridge is arranged on the side of the first dielectric layer 40 away from the dielectric substrate 10, and the two ends of the orthographic projection of the membrane bridge on the dielectric substrate 10 are respectively located on the orthographic projection of the first reference electrode 51 and the second reference electrode 52 on the dielectric substrate 10; the driving electrode 30 is located in the space enclosed by the membrane bridge and the dielectric substrate 10.
  • the MEMS device of the present disclosure satisfies at least one of the following conditions.
  • the thickness of the first dielectric layer 40 covered by the side of the driving electrode 30 is relatively thick, which can effectively avoid the risk of tip discharge caused by the distance between the membrane bridge and the driving electrode 30 below being too close when the membrane bridge is pulled down, resulting in the breakdown of the first dielectric layer 40 on the side of the driving electrode 30 and causing damage to the device.
  • the MEMS device of the embodiment of the present disclosure is described in detail below in combination with specific examples and preparation methods.
  • FIG6 is a schematic diagram of the structure of a MEMS device of the second example of an embodiment of the present disclosure; as shown in FIG6, the MEMS device includes a dielectric substrate 10, a driving electrode 30, a first reference electrode 51, a second reference electrode 52, a first dielectric layer 40 and a membrane bridge arranged on the dielectric substrate 10.
  • the first reference electrode 51 and the second reference electrode 52 are respectively located on both sides of the extension direction of the driving electrode 30, and there is a first gap Q1 between the first reference electrode 51 and the driving electrode 30, and there is a second gap Q2 between the second reference electrode 52 and the driving electrode 30.
  • the first dielectric layer 40 includes a first sub-dielectric layer 41 and a second sub-dielectric layer 42 arranged in sequence along a direction away from the dielectric substrate 10.
  • the first sub-dielectric layer 41 covers the side of the driving electrode 30 away from the dielectric substrate 10;
  • the second sub-dielectric layer 42 includes a first filling structure and a second filling structure, and the first filling structure and the second filling structure fill the first gap Q1 and the second gap Q2 respectively.
  • the membrane bridge is arranged on the side of the first dielectric layer 40 away from the dielectric substrate 10, and the two ends of the orthographic projection of the membrane bridge on the dielectric substrate 10 are respectively located on the orthographic projections of the first reference electrode 51 and the second reference electrode 52 on the dielectric substrate 10; the driving electrode 30 is located in the space enclosed by the membrane bridge and the dielectric substrate 10.
  • the first sub-dielectric layer 41 covers the first gap Q1 and the second gap Q2, and forms a first groove and a second groove in the first gap Q1 and the second gap Q2, respectively, and the first filling structure fills the first groove, and the second filling structure fills the second groove.
  • the thickness of the first filling structure and the second filling structure is the same as the thickness of the driving electrode 30.
  • silicon oxide may be selected as the material of the first sub-dielectric layer 41.
  • Resin glue may be selected as the material of the second sub-dielectric layer 42, namely the first filling structure and the second filling structure.
  • the materials of the driving electrode 30, the first reference electrode 51 and the second reference electrode 52 include but are not limited to copper.
  • the membrane bridge 20 may have a three-layer structure, and the materials of the three-layer structure are molybdenum, aluminum, and molybdenum respectively.
  • FIG. 7 is a preparation flow chart of the MEMS device shown in FIG. 6 . As shown in FIG. 7 , the preparation method may specifically include the following steps.
  • the dielectric substrate 1010 may specifically be a glass substrate.
  • a 0.5T glass substrate may be selected, and then the glass substrate is cleaned by a standard cleaning process.
  • step S12 may include: using methods including but not limited to magnetron sputtering of a first conductive film, followed by coating, exposing, developing, and etching (e.g., wet etching) to form a drive electrode 30, a first reference electrode 51, and a second reference electrode 52, and finally, removing the remaining photoresist to complete the preparation of the drive electrode 30, the first reference electrode 51, and the second reference electrode 52.
  • magnetron sputtering of a first conductive film followed by coating, exposing, developing, and etching (e.g., wet etching) to form a drive electrode 30, a first reference electrode 51, and a second reference electrode 52, and finally, removing the remaining photoresist to complete the preparation of the drive electrode 30, the first reference electrode 51, and the second reference electrode 52.
  • first sub-dielectric layer 41 in the first dielectric layer 40 on the side of the layer where the driving electrode 30, the first reference electrode 51 and the second reference electrode 52 are located away from the dielectric substrate 10; wherein the first sub-dielectric layer 41 covers the driving electrode 30 and may also cover the first gap Q1 and the second gap Q2.
  • the first sub-dielectric layer 41 forms a first groove portion and a second groove portion located in the first gap Q1 and the second gap Q2, respectively.
  • the first sub-dielectric layer 41 may be made of silicon oxide.
  • step S13 may include forming the first sub-dielectric layer 41 in the first dielectric layer 40 on the side of the layer where the drive electrode 30, the first reference electrode 51 and the second reference electrode 52 are located away from the dielectric substrate 10 by using a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, an electron cyclotron resonance chemical vapor deposition method or a sputtering method.
  • first sub-dielectric layer 41 formed in FIG. 6 also covers part of the first sub-reference electrode and part of the second sub-reference electrode to ensure that the thickness of the second sub-dielectric layer 42 subsequently formed in the first groove portion and the second groove portion is uniform.
  • the material of the second sub-dielectric layer 42 includes, but is not limited to, resin glue.
  • the step S14 may include: firstly, forming filling materials in the first groove portion and the second groove portion respectively by a glue-splitting process, and the orthographic projection of the filling material on the dielectric substrate 10 covers the orthographic projection of the first gap Q1 and the second gap Q2 on the dielectric substrate 10, and then heating the filling material to reshape and backfill the filling material to form a first filling structure filling the first groove portion and a second filling structure filling the second groove portion.
  • the thickness of the first filling structure and the second filling structure is the same as the thickness of the driving electrode 30 , and the thickness of the first filling structure and the second filling structure can be controlled by controlling the glue spreading speed.
  • the material of the sacrificial layer 60 may be silicon nitride, and the reason for using silicon nitride is that when the sacrificial layer 60 is subsequently removed, the first sub-dielectric layer 41 made of silicon oxide will not be damaged.
  • step S15 may include forming the sacrificial layer 60 on the side of the first sub-dielectric layer 41 and the second sub-dielectric layer 42 away from the dielectric substrate 10 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition, or sputtering.
  • a membrane bridge is formed on the side of the sacrificial layer 60 facing away from the dielectric substrate 10.
  • the two ends of the orthographic projection of the membrane bridge on the dielectric substrate 10 are respectively located on the orthographic projections of the first reference electrode 51 and the second reference electrode 52 on the dielectric substrate 10; the driving electrode 30 is located in the space enclosed by the membrane bridge and the dielectric substrate 10.
  • Step S16 may specifically include, but is not limited to, magnetron sputtering of the second conductive film, followed by coating, exposure, development, and etching (e.g., wet etching) to form a pattern including the membrane bridge, and finally removing the photoresist to complete the preparation of the membrane bridge.
  • step S17 may include using reactive ion etching (RIE) to reasonably control the gas atmosphere (lateral etching strength), pressure, power (etching rate), etching time, etc., to precisely control the etching of the sacrificial layer 60 under the membrane bridge to remove the sacrificial layer 60 under the membrane bridge, so as to complete the preparation of the MEMS device.
  • RIE reactive ion etching
  • the gas atmosphere is SF6 gas.
  • FIG8 is a schematic diagram of the structure of a MEMS device of the second example of the embodiment of the present disclosure; as shown in FIG8, the MEMS device includes a dielectric substrate 10, a driving electrode 30, a first reference electrode 51, a second reference electrode 52, a first dielectric layer 40, a second dielectric layer 70 and a membrane bridge arranged on the dielectric substrate 10.
  • the first reference electrode 51 and the second reference electrode 52 are respectively located on both sides of the extension direction of the driving electrode 30, and there is a first gap Q1 between the first reference electrode 51 and the driving electrode 30, and there is a second gap Q2 between the second reference electrode 52 and the driving electrode 30.
  • the first dielectric layer 40 includes a first sub-dielectric layer 41 and a second sub-dielectric layer 42 arranged in sequence along a direction away from the dielectric substrate 10.
  • the first sub-dielectric layer 41 covers the side of the driving electrode 30 away from the dielectric substrate 10;
  • the second sub-dielectric layer 42 includes a first filling structure and a second filling structure, and the first filling structure and the second filling structure fill the first gap Q1 and the second gap Q2 respectively.
  • the membrane bridge is arranged on the side of the first dielectric layer 40 away from the dielectric substrate 10, and the two ends of the orthographic projection of the membrane bridge on the dielectric substrate 10 are respectively located on the orthographic projections of the first reference electrode 51 and the second reference electrode 52 on the dielectric substrate 10; the driving electrode 30 is located in the space surrounded by the membrane bridge and the dielectric substrate 10.
  • the second dielectric layer 70 is located on the surface of the bridge surface 21 of the membrane bridge close to the dielectric substrate 10, and the orthographic projection of the second dielectric layer 70 on the dielectric substrate 10 at least covers the orthographic projection of the first dielectric layer 40 on the dielectric substrate 10.
  • the first sub-dielectric layer 41 covers the first gap Q1 and the second gap Q2, and forms a first groove and a second groove in the first gap Q1 and the second gap Q2, respectively, and the first filling structure fills the first groove, and the second filling structure fills the second groove.
  • the thickness of the first filling structure and the second filling structure is the same as the thickness of the driving electrode 30.
  • silicon oxide may be selected as the material of the first dielectric sub-layer 41 and the second dielectric layer 70.
  • Resin glue may be selected as the material of the second dielectric sub-layer 42, namely the first filling structure and the second filling structure.
  • FIG. 9 is a preparation flow chart of the MEMS device shown in FIG. 8 . As shown in FIG. 9 , the preparation method may specifically include the following steps.
  • the dielectric substrate 10 may specifically be a glass substrate.
  • a 0.5T glass substrate may be selected, and then the glass substrate is cleaned by a standard cleaning process.
  • step S22 may include: using methods including but not limited to magnetron sputtering of a first conductive film, followed by coating, exposing, developing, and etching (e.g., wet etching) to form a drive electrode 30, a first reference electrode 51, and a second reference electrode 52, and finally, removing the remaining photoresist to complete the preparation of the drive electrode 30, the first reference electrode 51, and the second reference electrode 52.
  • methods including but not limited to magnetron sputtering of a first conductive film, followed by coating, exposing, developing, and etching (e.g., wet etching) to form a drive electrode 30, a first reference electrode 51, and a second reference electrode 52, and finally, removing the remaining photoresist to complete the preparation of the drive electrode 30, the first reference electrode 51, and the second reference electrode 52.
  • first sub-dielectric layer 41 in the first dielectric layer 40 on the side of the layer where the driving electrode 30, the first reference electrode 51 and the second reference electrode 52 are located away from the dielectric substrate 10; wherein the first sub-dielectric layer 41 covers the driving electrode 30 and may also cover the first gap Q1 and the second gap Q2.
  • the first sub-dielectric layer 41 forms a first groove portion and a second groove portion located in the first gap Q1 and the second gap Q2, respectively.
  • the first sub-dielectric layer 41 may be made of silicon oxide.
  • step S23 may include forming the first sub-dielectric layer 41 in the first dielectric layer 40 on the side of the layer where the drive electrode 30, the first reference electrode 51 and the second reference electrode 52 are located away from the dielectric substrate 10 by using a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, an electron cyclotron resonance chemical vapor deposition method or a sputtering method.
  • first sub-dielectric layer 41 formed in FIG. 8 also covers part of the first sub-reference electrode and part of the second sub-reference electrode to ensure that the thickness of the second sub-dielectric layer 42 subsequently formed in the first groove portion and the second groove portion is uniform.
  • the material of the second sub-dielectric layer 42 includes, but is not limited to, resin glue.
  • the step S24 may include: firstly, forming filling materials in the first groove portion and the second groove portion respectively by a glue-splitting process, and the orthographic projection of the filling material on the dielectric substrate 10 covers the orthographic projection of the first gap Q1 and the second gap Q2 on the dielectric substrate 10, and then heating the filling material to reshape and backfill the filling material to form a first filling structure filling the first groove portion and a second filling structure filling the second groove portion.
  • the thickness of the first filling structure and the second filling structure is the same as the thickness of the driving electrode 30 , and the thickness of the first filling structure and the second filling structure can be controlled by controlling the glue spreading speed.
  • the material of the sacrificial layer 60 may be silicon nitride, and the reason for using silicon nitride is that when the sacrificial layer 60 is subsequently removed, the first sub-dielectric layer 41 made of silicon oxide will not be damaged.
  • step S25 may include forming the sacrificial layer 60 on the side of the first sub-dielectric layer 41 and the second sub-dielectric layer 42 away from the dielectric substrate 10 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering.
  • the second dielectric layer 70 may be made of silicon oxide.
  • step S26 may include forming the second dielectric layer 70 on the side of the sacrificial layer 60 away from the dielectric substrate 10 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering.
  • a membrane bridge is formed on the side of the second dielectric layer 70 facing away from the dielectric substrate 10.
  • the two ends of the orthographic projection of the membrane bridge on the dielectric substrate 10 are respectively located on the orthographic projections of the first reference electrode 51 and the second reference electrode 52 on the dielectric substrate 10.
  • the driving electrode 30 is located in the space enclosed by the membrane bridge and the dielectric substrate 10.
  • Step S27 may specifically include, but is not limited to, magnetron sputtering of the second conductive film, followed by coating, exposure, development, and etching (e.g., wet etching) to form a pattern including the membrane bridge, and finally removing the photoresist to complete the preparation of the membrane bridge.
  • step S28 may include using reactive ion etching (RIE) to reasonably control the gas atmosphere (lateral etching strength), pressure, power (etching rate), etching time, etc., to precisely control the etching of the sacrificial layer 60 under the membrane bridge to remove the sacrificial layer 60 under the membrane bridge, so as to complete the preparation of the MEMS device.
  • RIE reactive ion etching
  • the gas atmosphere is SF6 gas.
  • FIG. 10 is a schematic diagram of the structure of the MEMS device of the second example of the embodiment of the present disclosure; as shown in FIG. 10, the MEMS device includes a dielectric substrate 10, a driving electrode 30, a first reference electrode 51, a second reference electrode 52, a first dielectric layer 40, a second dielectric layer 70 and a membrane bridge arranged on the dielectric substrate 10.
  • the first reference electrode 51 and the second reference electrode 52 are respectively located on both sides of the extension direction of the driving electrode 30, and there is a first gap Q1 between the first reference electrode 51 and the driving electrode 30, and there is a second gap Q2 between the second reference electrode 52 and the driving electrode 30.
  • the membrane bridge is arranged on the side of the first dielectric layer 40 away from the dielectric substrate 10, and the two ends of the orthographic projection of the membrane bridge on the dielectric substrate 10 are respectively located on the orthographic projections of the first reference electrode 51 and the second reference electrode 52 on the dielectric substrate 10; the driving electrode 30 is located in the space enclosed by the membrane bridge and the dielectric substrate 10.
  • the second dielectric layer 70 is located on the bridge deck 21 of the membrane bridge close to the surface of the dielectric substrate 10, and the orthographic projection of the second dielectric layer 70 on the dielectric substrate 10 at least covers the orthographic projection of the first dielectric layer 40 on the dielectric substrate 10.
  • the second dielectric layer 70 has a first protrusion 71 protruding toward the dielectric substrate 10.
  • the bridge deck 21 of the membrane bridge has a second protrusion 211 protruding toward the first dielectric layer 40, and the second protrusion 211 is arranged in a one-to-one correspondence with the first protrusion 71, and the second protrusion 211 is embedded in the corresponding first protrusion 71. In this case, it can be ensured that the bridge deck 21 of the membrane bridge can be stably attached to the second dielectric layer 70.
  • the material of the first dielectric layer 40 and the second dielectric layer 70 may be silicon oxide.
  • FIG. 11 is a preparation flow chart of the MEMS device shown in FIG. 10 . As shown in FIG. 11 , the preparation method may specifically include the following steps.
  • the dielectric substrate 10 may specifically be a glass substrate.
  • a 0.5T glass substrate may be selected, and then the glass substrate is cleaned by a standard cleaning process.
  • step S32 may include: using methods including but not limited to magnetron sputtering of a first conductive film, followed by coating, exposing, developing, and etching (e.g., wet etching) to form a drive electrode 30, a first reference electrode 51, and a second reference electrode 52, and finally, removing the remaining photoresist to complete the preparation of the drive electrode 30, the first reference electrode 51, and the second reference electrode 52.
  • methods including but not limited to magnetron sputtering of a first conductive film, followed by coating, exposing, developing, and etching (e.g., wet etching) to form a drive electrode 30, a first reference electrode 51, and a second reference electrode 52, and finally, removing the remaining photoresist to complete the preparation of the drive electrode 30, the first reference electrode 51, and the second reference electrode 52.
  • first dielectric layer 40 on the side of the layer where the driving electrode 30, the first reference electrode 51 and the second reference electrode 52 are located away from the dielectric substrate 10; wherein the first dielectric layer 40 covers the driving electrode 30, and may also cover the first gap Q1 and the second gap Q2. At this time, the first dielectric layer 40 forms a first groove portion and a second groove portion located in the first gap Q1 and the second gap Q2, respectively.
  • the first dielectric layer 40 may be made of silicon oxide.
  • step S33 may include forming the first dielectric layer 40 on the side of the layer where the drive electrode 30, the first reference electrode 51, and the second reference electrode 52 are located away from the dielectric substrate 10 by using a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, an electron cyclotron resonance chemical vapor deposition method, or a sputtering method.
  • first dielectric layer 40 formed in FIG. 10 also covers a portion of the first sub-reference electrode and a portion of the second sub-reference electrode.
  • the first dielectric layer 40 is formed with a first groove portion and a second groove portion, so a second recessed portion 61 is formed on the surface of the sacrificial layer 60 away from the dielectric substrate 10.
  • the material of the sacrificial layer 60 may be silicon nitride, and the reason for using silicon nitride is that when the sacrificial layer 60 is subsequently removed, the first dielectric layer 40 made of silicon oxide will not be damaged.
  • step S34 may include forming the sacrificial layer 60 on the side of the first dielectric layer 40 away from the dielectric substrate 10 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition, or sputtering.
  • a second dielectric layer 70 is formed on the side of the sacrificial layer 60 facing away from the dielectric substrate 10. Since the sacrificial layer 60 has a second recessed portion 61, the second dielectric layer 70 formed at this time has a first protruding portion 71 protruding toward the dielectric substrate 10. The first protruding portion 71 is corresponding to the second recessed portion 61, and one first protruding portion 71 is embedded in one second recessed portion 61.
  • the second dielectric layer 70 may be made of silicon oxide.
  • step S35 may include forming the second dielectric layer 70 on the side of the sacrificial layer 60 away from the dielectric substrate 10 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering.
  • a membrane bridge is formed on the side of the second dielectric layer 70 away from the dielectric substrate 10, and the two ends of the orthographic projection of the membrane bridge on the dielectric substrate 10 are respectively located on the orthographic projections of the first reference electrode 51 and the second reference electrode 52 on the dielectric substrate 10; the driving electrode 30 is located in the space surrounded by the membrane bridge and the dielectric substrate 10. Since the second dielectric layer 70 has the first protrusion 71, the bridge surface 21 of the membrane bridge has the second protrusion 211 protruding toward the first dielectric layer 40, and the second protrusion 211 is arranged in a one-to-one correspondence with the first protrusion 71, and the second protrusion 211 is embedded in the corresponding first protrusion 71.
  • Step S36 may specifically include, but is not limited to, magnetron sputtering of the second conductive film, followed by coating, exposure, development, and etching (e.g., wet etching) to form a pattern including the membrane bridge, and finally removing the photoresist to complete the preparation of the membrane bridge.
  • step S37 may include using reactive ion etching (RIE) to reasonably control the gas atmosphere (lateral etching strength), pressure, power (etching rate), etching time, etc., to precisely control the etching of the sacrificial layer 60 under the membrane bridge to remove the sacrificial layer 60 under the membrane bridge, so as to complete the preparation of the MEMS device.
  • RIE reactive ion etching
  • the gas atmosphere is SF6 gas.
  • FIG. 12 is a schematic diagram of the structure of the MEMS device of the second example of the embodiment of the present disclosure; as shown in FIG. 12, the MEMS device includes a dielectric substrate 10, a driving electrode 30, a first reference electrode 51, a second reference electrode 52, a first dielectric layer 40, a second dielectric layer 70 and a membrane bridge arranged on the dielectric substrate 10.
  • the first reference electrode 51 and the second reference electrode 52 are respectively located on both sides of the extension direction of the driving electrode 30, and there is a first gap Q1 between the first reference electrode 51 and the driving electrode 30, and there is a second gap Q2 between the second reference electrode 52 and the driving electrode 30.
  • the first sub-dielectric layer 41 covers the side of the driving electrode 30 away from the dielectric substrate 10;
  • the second sub-dielectric layer 42 includes a first filling structure and a second filling structure, and the first filling structure and the second filling structure fill the first gap Q1 and the second gap Q2 respectively.
  • the first filling structure and the second filling structure both have a first surface in contact with the first sub-dielectric layer 41, a second surface arranged opposite to the dielectric substrate 10, and a first connecting surface connecting the first surface and the second surface; the first connecting surface and the first sub-dielectric layer 41 define a first recessed portion 80.
  • the membrane bridge is arranged on the side of the first dielectric layer 40 away from the dielectric substrate 10, and the two ends of the orthographic projection of the membrane bridge on the dielectric substrate 10 are respectively located on the orthographic projections of the first reference electrode 51 and the second reference electrode 52 on the dielectric substrate 10; the driving electrode 30 is located in the space enclosed by the membrane bridge and the dielectric substrate 10.
  • the second dielectric layer 70 is located on the surface of the bridge surface 21 of the membrane bridge close to the dielectric substrate 10, and the orthographic projection of the second dielectric layer 70 on the dielectric substrate 10 at least covers the orthographic projection of the first dielectric layer 40 on the dielectric substrate 10.
  • the second dielectric layer 70 has a first protruding portion 71 protruding toward the dielectric substrate 10, and the first protruding portion 71 is arranged in a one-to-one correspondence with the first recessed portion 80.
  • the membrane bridge can be effectively prevented from failing to bounce up after being pulled down, thereby ensuring the reliability and reusability of the MEMS device and improving the device performance.
  • the bridge deck 21 of the membrane bridge has a second protrusion 211 protruding toward the first dielectric layer 40, and the second protrusion 211 is arranged one-to-one with the first protrusion 71, and the second protrusion 211 is embedded in the corresponding first protrusion 71. In this case, it can be ensured that the bridge deck 21 of the membrane bridge can be stably attached to the second dielectric layer 70.
  • silicon oxide may be selected as the material of the first dielectric sub-layer 41 and the second dielectric layer 70.
  • Resin glue may be selected as the material of the second dielectric sub-layer 42, namely the first filling structure and the second filling structure.
  • FIG13 is a preparation flow chart of the MEMS device shown in FIG12 . As shown in FIG13 , the preparation method may specifically include the following steps.
  • the dielectric substrate 10 may specifically be a glass substrate.
  • a 0.5T glass substrate may be selected, and then the glass substrate is cleaned by a standard cleaning process.
  • step S42 may include: using methods including but not limited to magnetron sputtering of a first conductive film, followed by coating, exposing, developing, and etching (e.g., wet etching) to form a drive electrode 30, a first reference electrode 51, and a second reference electrode 52, and finally, removing the remaining photoresist to complete the preparation of the drive electrode 30, the first reference electrode 51, and the second reference electrode 52.
  • methods including but not limited to magnetron sputtering of a first conductive film, followed by coating, exposing, developing, and etching (e.g., wet etching) to form a drive electrode 30, a first reference electrode 51, and a second reference electrode 52, and finally, removing the remaining photoresist to complete the preparation of the drive electrode 30, the first reference electrode 51, and the second reference electrode 52.
  • first sub-dielectric layer 41 on the side of the layer where the driving electrode 30, the first reference electrode 51 and the second reference electrode 52 are located away from the dielectric substrate 10; wherein the first sub-dielectric layer 41 covers the driving electrode 30, and may also cover the first gap Q1 and the second gap Q2.
  • the first sub-dielectric layer 41 forms a first groove portion and a second groove portion located in the first gap Q1 and the second gap Q2, respectively.
  • the first sub-dielectric layer 41 may be made of silicon oxide.
  • step S43 may include forming the first sub-dielectric layer 41 in the first dielectric layer 40 on the side of the layer where the drive electrode 30, the first reference electrode 51 and the second reference electrode 52 are located away from the dielectric substrate 10 by using a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, an electron cyclotron resonance chemical vapor deposition method or a sputtering method.
  • first sub-dielectric layer 41 formed in FIG. 12 also covers a portion of the first sub-reference electrode and a portion of the second sub-reference electrode.
  • a second sub-dielectric layer 42 on a side of the first sub-dielectric layer 41 away from the dielectric substrate 10, the second sub-dielectric layer 42 comprising a first filling structure filling the first groove portion and a second filling structure filling the second groove portion.
  • the first filling structure and the second filling structure formed both have a first surface in contact with the first sub-dielectric layer 41, a second surface arranged opposite to the dielectric substrate 10, and a first connecting surface connecting the first surface and the second surface; the first connecting surface and the first sub-dielectric layer 41 define a first recessed portion 80.
  • the material of the second sub-dielectric layer 42 includes, but is not limited to, resin glue.
  • the step S44 may include: firstly, forming filling materials in the first groove and the second groove respectively by a coating process, and the orthographic projection of the filling materials on the dielectric substrate 10 covers the orthographic projection of the first gap Q1 and the second gap Q2 on the dielectric substrate 10, and then reshaping and backfilling the filling materials by annealing to form a first filling structure filling the first groove and a second filling structure filling the second groove, and the first filling structure and the second filling structure formed at this time both have a first surface in contact with the first sub-dielectric layer 41, a second surface arranged opposite to the dielectric substrate 10, and a first connecting surface connecting the first surface and the second surface; the first connecting surface and the first sub-dielectric layer 41 define a first recessed portion 80.
  • the thickness of the first filling structure and the second filling structure is the same as the thickness of the driving electrode 30 , and the thickness of the first filling structure and the second filling structure can be controlled by controlling the glue spreading speed.
  • a second recessed portion 61 is formed on the surface of the sacrificial layer 60 away from the dielectric substrate 10.
  • the second recessed portion 61 is arranged in a one-to-one correspondence with the first recessed portion 80, and the second recessed portion 61 is embedded in the corresponding first recessed portion 80.
  • the material of the sacrificial layer 60 may be silicon nitride, and the reason for using silicon nitride is that when the sacrificial layer 60 is subsequently removed, the first dielectric layer 40 made of silicon oxide will not be damaged.
  • step S45 may include forming the sacrificial layer 60 on the side of the first dielectric layer 40 away from the dielectric substrate 10 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition, or sputtering.
  • a second dielectric layer 70 is formed on the side of the sacrificial layer 60 facing away from the dielectric substrate 10. Since the sacrificial layer 60 has the second recessed portion 61, the second dielectric layer 70 formed at this time has a first protruding portion 71 protruding toward the dielectric substrate 10. The first protruding portion 71 and the second recessed portion 61 are arranged correspondingly, and one first protruding portion 71 is embedded in one second recessed portion 61.
  • the second dielectric layer 70 may be made of silicon oxide.
  • step S46 may include forming the second dielectric layer 70 on the side of the sacrificial layer 60 away from the dielectric substrate 10 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering.
  • a membrane bridge is formed on the side of the second dielectric layer 70 away from the dielectric substrate 10, and the two ends of the orthographic projection of the membrane bridge on the dielectric substrate 10 are respectively located on the orthographic projections of the first reference electrode 51 and the second reference electrode 52 on the dielectric substrate 10; the driving electrode 30 is located in the space surrounded by the membrane bridge and the dielectric substrate 10. Since the second dielectric layer 70 has the first protrusion 71, the bridge surface 21 of the membrane bridge has the second protrusion 211 protruding toward the first dielectric layer 40, and the second protrusion 211 is arranged in a one-to-one correspondence with the first protrusion 71, and the second protrusion 211 is embedded in the corresponding first protrusion 71.
  • Step S47 may specifically include, but is not limited to, magnetron sputtering of the second conductive film, followed by coating, exposure, development, and etching (e.g., wet etching) to form a pattern including the membrane bridge, and finally removing the photoresist to complete the preparation of the membrane bridge.
  • step S48 may include using reactive ion etching (RIE) to reasonably control the gas atmosphere (lateral etching strength), pressure, power (etching rate), etching time, etc., to precisely control the etching of the sacrificial layer 60 under the membrane bridge to remove the sacrificial layer 60 under the membrane bridge, so as to complete the preparation of the MEMS device.
  • RIE reactive ion etching
  • the gas atmosphere is SF6 gas.
  • FIG. 14 is a schematic diagram of the structure of the MEMS device of the second example of the embodiment of the present disclosure; as shown in FIG. 14, the MEMS device includes a dielectric substrate 10, a driving electrode 30, a first reference electrode 51, a second reference electrode 52, a first dielectric layer 40 and a membrane bridge arranged on the dielectric substrate 10.
  • the first reference electrode 51 and the second reference electrode 52 are respectively located on both sides of the extension direction of the driving electrode 30, and there is a first gap Q1 between the first reference electrode 51 and the driving electrode 30, and there is a second gap Q2 between the second reference electrode 52 and the driving electrode 30.
  • the first dielectric layer 40 includes a second sub-dielectric layer 42 and a first sub-dielectric layer 41 which are sequentially arranged in a direction away from the dielectric substrate 10.
  • the first sub-dielectric layer 41 covers the side of the second dielectric layer 70 away from the dielectric substrate 10;
  • the second sub-dielectric layer 42 includes a first filling structure and a second filling structure, and the first filling structure and the second filling structure fill the first gap Q1 and the second gap Q2 respectively.
  • the membrane bridge is arranged on the side of the first dielectric layer 40 away from the dielectric substrate 10, and the two ends of the orthographic projection of the membrane bridge on the dielectric substrate 10 are respectively located on the orthographic projections of the first reference electrode 51 and the second reference electrode 52 on the dielectric substrate 10; the driving electrode 30 is located in the space enclosed by the membrane bridge and the dielectric substrate 10.
  • the thickness of the first filling structure and the second filling structure is the same as the thickness of the driving electrode 30 .
  • silicon oxide may be selected as the material of the first sub-dielectric layer 41.
  • Resin glue may be selected as the material of the second sub-dielectric layer 42, namely the first filling structure and the second filling structure.
  • FIG. 15 is a flow chart for preparing the MEMS device shown in FIG. 14 .
  • the preparation method may specifically include the following steps.
  • the dielectric substrate 10 may specifically be a glass substrate.
  • a 0.5T glass substrate may be selected, and then the glass substrate is cleaned by a standard cleaning process.
  • step S52 may include: using, including but not limited to, magnetron sputtering a first conductive film, followed by coating, exposing, developing, and etching (e.g., wet etching) to form a drive electrode 30, a first reference electrode 51, and a second reference electrode 52, and finally, removing the remaining photoresist to complete the preparation of the drive electrode 30, the first reference electrode 51, and the second reference electrode 52.
  • magnetron sputtering a first conductive film followed by coating, exposing, developing, and etching (e.g., wet etching) to form a drive electrode 30, a first reference electrode 51, and a second reference electrode 52, and finally, removing the remaining photoresist to complete the preparation of the drive electrode 30, the first reference electrode 51, and the second reference electrode 52.
  • the material of the second sub-dielectric layer 42 includes, but is not limited to, resin glue.
  • the step S53 may include: firstly, forming filling materials in the first gap Q1 and the second gap Q2 respectively by a glue-splitting process, and the orthographic projection of the filling material on the dielectric substrate 10 covers the orthographic projection of the first gap Q1 and the second gap Q2 on the dielectric substrate 10, and then heating the filling material to reshape and backfill the filling material to form a first filling structure filling the first gap Q1 and a second filling structure filling the second gap Q2.
  • the thickness of the first filling structure and the second filling structure is the same as the thickness of the driving electrode 30 , and the thickness of the first filling structure and the second filling structure can be controlled by controlling the glue spreading speed.
  • the first sub-dielectric layer 41 may be made of silicon oxide.
  • step S54 may include forming the first sub-dielectric layer 41 in the first dielectric layer 40 on the side of the second sub-dielectric layer 42 away from the dielectric substrate 10 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering.
  • first sub-dielectric layer 41 formed in FIG. 14 also covers part of the first sub-reference electrode and part of the second sub-reference electrode to ensure that the thickness of the second sub-dielectric layer 42 subsequently formed in the first groove portion and the second groove portion is uniform.
  • the material of the sacrificial layer 60 may be silicon nitride.
  • the reason for using silicon nitride is that when the sacrificial layer 60 is subsequently removed, the first sub-dielectric layer 41 made of silicon oxide will not be damaged.
  • step S55 may include forming the sacrificial layer 60 on the side of the first sub-dielectric layer 41 away from the dielectric substrate 10 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering.
  • a membrane bridge is formed on the side of the sacrificial layer 60 facing away from the dielectric substrate 10.
  • the two ends of the orthographic projection of the membrane bridge on the dielectric substrate 10 are respectively located on the orthographic projections of the first reference electrode 51 and the second reference electrode 52 on the dielectric substrate 10; the driving electrode 30 is located in the space enclosed by the membrane bridge and the dielectric substrate 10.
  • Step S56 may specifically include, but is not limited to, magnetron sputtering of the second conductive film, followed by coating, exposure, development, and etching (e.g., wet etching) to form a pattern including the membrane bridge, and finally removing the photoresist to complete the preparation of the membrane bridge.
  • step S57 may include using reactive ion etching (RIE) to reasonably control the gas atmosphere (lateral etching strength), pressure, power (etching rate), etching time, etc., to precisely control the etching of the sacrificial layer 60 under the membrane bridge to remove the sacrificial layer 60 under the membrane bridge, so as to complete the preparation of the MEMS device.
  • RIE reactive ion etching
  • the gas atmosphere is SF6 gas.
  • the sacrificial layer 60 is made of silicon nitride, and the material of the sacrificial layer 60 can also be photoresist.
  • the corresponding first dielectric layer 40 can be made of a silicon nitride/silicon oxide composite film layer.
  • FIG16 is a preparation flow chart of the MEMS device shown in FIG14 . As shown in FIG16 , the preparation method includes the following steps.
  • the dielectric substrate 10 may specifically be a glass substrate.
  • a 0.5T glass substrate may be selected, and then the glass substrate is cleaned by a standard cleaning process.
  • step S62 may include: using methods including but not limited to magnetron sputtering of a first conductive film, followed by coating, exposing, developing, and etching (e.g., wet etching) to form a drive electrode 30, a first reference electrode 51, and a second reference electrode 52, and finally, removing the remaining photoresist to complete the preparation of the drive electrode 30, the first reference electrode 51, and the second reference electrode 52.
  • methods including but not limited to magnetron sputtering of a first conductive film, followed by coating, exposing, developing, and etching (e.g., wet etching) to form a drive electrode 30, a first reference electrode 51, and a second reference electrode 52, and finally, removing the remaining photoresist to complete the preparation of the drive electrode 30, the first reference electrode 51, and the second reference electrode 52.
  • step S53 may include: firstly forming the filling material in the first gap Q1 and the second gap Q2 and on the driving electrode 30 by a coating process.
  • step S64 may include using CMP chemical mechanical polishing to grind down the filling material above the driving electrode 30, leaving only a first filling structure filling the first gap Q1 and a second filling structure filling the second gap Q2 to form a second sub-dielectric layer 42 of the first dielectric layer 40; the thickness of the first filling structure and the second filling structure is the same as the thickness of the driving electrode 30.
  • the first sub-dielectric layer 41 may be made of silicon oxide.
  • step S65 may include forming the first sub-dielectric layer 41 in the first dielectric layer 40 on the side of the second sub-dielectric layer 42 away from the dielectric substrate 10 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering.
  • first sub-dielectric layer 41 formed in FIG. 14 also covers part of the first sub-reference electrode and part of the second sub-reference electrode to ensure that the thickness of the second sub-dielectric layer 42 subsequently formed in the first groove portion and the second groove portion is uniform.
  • the material of the sacrificial layer 60 may be silicon nitride.
  • the reason for using silicon nitride is that when the sacrificial layer 60 is subsequently removed, the first sub-dielectric layer 41 made of silicon oxide will not be damaged.
  • step S66 may include forming the sacrificial layer 60 on the side of the first sub-dielectric layer 41 away from the dielectric substrate 10 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering.
  • a membrane bridge is formed on the side of the sacrificial layer 60 facing away from the dielectric substrate 10.
  • the two ends of the orthographic projection of the membrane bridge on the dielectric substrate 10 are respectively located on the orthographic projections of the first reference electrode 51 and the second reference electrode 52 on the dielectric substrate 10; the driving electrode 30 is located in the space enclosed by the membrane bridge and the dielectric substrate 10.
  • Step S67 may specifically include, but is not limited to, magnetron sputtering of the second conductive film, followed by coating, exposure, development, and etching (e.g., wet etching) to form a pattern including the membrane bridge, and finally removing the photoresist to complete the preparation of the membrane bridge.
  • step S68 may include using reactive ion etching (RIE) to reasonably control the gas atmosphere (lateral etching strength), pressure, power (etching rate), etching time, etc., to precisely control the etching of the sacrificial layer 60 under the membrane bridge to remove the sacrificial layer 60 under the membrane bridge, so as to complete the preparation of the MEMS device.
  • RIE reactive ion etching
  • the gas atmosphere is SF6 gas.
  • the embodiment of the present disclosure provides an electronic device, which includes any of the above-mentioned MEMS devices.
  • the electronic device includes but is not limited to a phase shifter.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Micromachines (AREA)

Abstract

本公开提供一种MEMS器件及其制备方法、电子设备，属于微机电系统技术领域。本公开的MEMS器件，其包括：介质基板；驱动电极、第一参考电极和第二参考电极，设置在介质基板上，且第一参考电极和第二参考电极分别位于驱动电极延伸方向两侧；第一介质层，覆盖在驱动电极背离介质基板的一侧；膜桥，设置在第一介质层背离介质基板的一侧，第一参考电极和驱动电极之间具有第一间隙；第二参考电极和驱动电极之间具有第二间隙；第一介质层位于第一间隙和第二间隙的部分的厚度大于驱动电极的厚度；和/或，在膜桥的桥面靠近介质基板的一侧设置有第二介质层，且第二介质层在介质基板上的正投影至少覆盖驱动电极在介质基板上的正投影。

Description

MEMS器件及其制备方法、电子设备 技术领域
本公开属于微机电系统技术领域，具体涉及一种MEMS器件及其制备方法、电子设备。
背景技术
微机电系统(MEMS，Micro-Electro-Mechanical System)是集微传感器、微执行器、微机械结构、微电源微能源、信号处理和控制电路、高性能电子集成器件、接口、通信等于一体的微型器件或系统。MEMS是一项革命性的新技术，广泛应用于高新技术产业，是一项关系到国家的科技发展、经济繁荣和国防安全的关键技术。随着信息时代迅速发展，具备高集成、小型化、多功能以及低成本的MEMS器件将会带来巨大的经济价值。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种MEMS器件及其制备方法、电子设备。
本公开实施例提供一种MEMS器件，其包括：
介质基板；
驱动电极、第一参考电极和第二参考电极，设置在所述介质基板上，且所述第一参考电极和所述第二参考电极分别位于所述驱动电极延伸方向两侧；
第一介质层，覆盖在所述驱动电极背离所述介质基板的一侧；
膜桥，设置在所述第一介质层背离所述介质基板的一侧，且所述膜桥在所述介质基板上的正投影的两端，分别位于所述第一参考电极和所述第二参考电极在所述介质基板上的正投影上；所述驱动电极位于所述膜桥和所述介质基板所围成的空间内；其中，
所述第一参考电极和所述驱动电极之间具有第一间隙；所述第二参考电极和所述驱动电极之间具有第二间隙；
所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度；和/或，在所述膜桥的桥面靠近所述介质基板的一侧设置有第二介质层，且所述第二介质层在所述介质基板上的正投影至少覆盖所述驱动电极在所述介质基板上的正投影。
其中，当所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度时，所述第一介质层包括沿背离所述介质基板方向依次设置的第一子介质层和第二子介质层；
所述第二子介质层包括第一填充结构和第二填充结构；所述第一填充结构和所述第二填充结构分别位于所述第一间隙和所述第二间隙。
其中，所述第一子介质层覆盖所述第一间隙和所述第二间隙，且所述第一子介质层在所述第一间隙形成第一槽部，所述第二子介质层在所述第二间隙形成第二槽部；所述第一填充结构填充所述第一槽部，所述第二填充结构填充所述第二槽部。
其中，所述第二子介质层的材料包括树脂胶。
其中，当在所述膜桥的桥面靠近所述介质基板的一侧设置有所述第二介质层时，所述第二介质层具有朝向所述第一介质层凸出的第一凸出部。
其中，所述膜桥的桥面具有朝向所述第一介质层凸出的第二凸出部，且所述第二凸出部与所述第一凸出部一一对应设置的，且所述第二凸出部嵌在与之对应的第一凸出部内。
其中，当所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度时，所述第一介质层朝向所述第二介质层的表面具有第一凹陷部；所述第一凹陷部与所述第一凸出部一一对应设置。
其中，所述第一介质层包括沿背离基板方向依次设置的第一子介质层和第二子介质层；
所述第二子介质层包括第一填充结构和第二填充结构；所述第一填充结构和所述第二填充结构分别位于所述第一间隙和所述第二间隙。
其中，所述第一填充结构和所述第二填充结构均具有与所述第一子介质 层接触的第一面，与所述介质基板相对设置的第二面，以及连接所述第一表面和所述第二面的第一连接面；所述第一连接面和所述第一子介质层限定出所述第一凹陷部。
其中，所述第二子介质层的材料包括树脂胶。
其中，当所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度时，所述第一介质层包括沿靠近所述介质基板方向依次设置的第一子介质层和第二子介质层；
所述第二子介质层包括第一填充结构和第二填充结构；所述第一填充结构和所述第二填充结构分别位于所述第一间隙和所述第二间隙。
其中，所述第二子介质层的材料包括树脂胶。
本公开实施例提供一种MEMS器件的制备方法，其包括：
提供一介质基板；
在所述介质基板上形成驱动电极、第一参考电极和第二参考电极；所述第一参考电极和所述第二参考电极分别位于所述驱动电极延伸方向两侧；
在驱动电极、所述第一参考电极和所述第二参考电极背离所述介质基板的一侧形成第一介质层；
在所述第一介质层背离所述介质基板的一侧形成膜桥；所述膜桥在所述介质基板上的正投影的两端，分别位于所述第一参考电极和所述第二参考电极在所述介质基板上的正投影上；所述驱动电极位于所述膜桥和所述介质基板所围成的空间内；其中，
所述第一参考电极和所述驱动电极之间限定出第一间隙；所述第二参考电极和所述驱动电极之间限定出第二间隙；所形成所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度；和/或，
所述制备方法还包括：在所述膜桥的桥面靠近所述介质基板的一侧设置有第二介质层，且所述第二介质层在所述介质基板上的正投影至少覆盖所述驱动电极在所述介质基板上的正投影。
其中，当所形成的所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度时，所述形成的第一介质层的步骤包括：
沿背离所述介质基板的方向依次形成第一子介质层和第二子介质层；所述第二子介质层包括第一填充结构和第二填充结构；所述第一填充结构和所述第二填充结构分别位于所述第一间隙和所述第二间隙。
其中，当所述制备方法包括在所述膜桥的桥面靠近所述介质基板的一侧设置有所述第二介质层时，在形成所述第二介质层之前还包括：
在所述第一介质层背离介质基板的表面形成牺牲层；其中，所述牺牲层背离介质基板的一侧具有第二凹陷部；
所述第二介质层形成在所述牺牲层背离介质基板的一侧，所形成的所述第二介质层具有朝向所述介质基板一侧凸出的第一凸出部；所述第一凸出部与所述第二凹陷部一一对应设置；
在形成所述膜桥之后还包括去除所述牺牲层的步骤。
其中，当所形成的所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度，以及在述制备方法包括在所述膜桥的桥面靠近所述介质基板的一侧设置有所述第二介质层时，
形成所述第一介质层的步骤包括：
沿背离所述介质基板的方向依次形成第一子介质层和第二子介质层；所述第二子介质层包括第一填充结构和第二填充结构；所述第一填充结构和所述第二填充结构分别位于所述第一间隙和所述第二间隙；
形成所述第二子介质层的步骤包括：
在所述第一间隙和第二间隙形成填充材料，退火形成所述第一填充结构和所述第二填充结构；所述第一填充结构和所述第二填充结构均具有与所述第一子介质层接触的第一面，与所述介质基板相对设置的第二面，以及连接所述第一表面和所述第二面的第一连接面；所述第一连接面和所述第一子介质层限定出所述第一凹陷部；
在形成所述第二子介质层之后还包括：
在所述第一介质层背离介质基板的表面形成牺牲层；其中，所述牺牲层背离介质基板的一侧具有第二凹陷部；所述第二凹陷部与所述第一凹陷部一一对应设置的；
所述第二介质层形成在所述牺牲层背离介质基板的一侧，所形成的所述第二介质层具有朝向所述介质基板一侧凸出的第一凸出部；所述第一凸出部与所述第二凹陷部一一对应设置；
在形成所述膜桥之后还包括去除所述牺牲层的步骤。
其中，所形成的所述膜桥的桥面具有朝向所述第一介质层凸出的第二凸出部，且所述第二凸出部与所述第一凸出部一一对应设置的，且所述第二凸出部嵌在与之对应的第一凸出部内。
其中，当所形成的所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度时，形成所述第一介质层的步骤包括：
沿背离所述介质基板的方向依次形成第二子介质层和第一子介质层；所述第二子介质层包括第一填充结构和第二填充结构；所述第一填充结构和所述第二填充结构分别位于所述第一间隙和所述第二间隙；
形成所述第二子介质层的步骤包括：
形成第二子介质材料层，且所述第二介质材料层突出于所述第一间隙和所述第二间隙；
对所述第二子介质材料层进行加热，以使第二子介质材料层重塑回填所述第一间隙和所述第二间隙，形成所述第一填充结构和所述第二填充结构。
其中，当所形成的所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度时，形成所述第一介质层的步骤包括：
沿背离所述介质基板的方向依次形成第二子介质层和第一子介质层；所述第二子介质层包括第一填充结构和第二填充结构；所述第一填充结构和所述第二填充结构分别位于所述第一间隙和所述第二间隙；
形成所述第二子介质层的步骤包括：
形成第二子介质材料层，且所述第二介质材料层突出于所述第一间隙和所述第二间隙；
采用化学机械抛光磨平工艺，去除突出于所述第一间隙和所述第二间隙的所述第二子介质材料层部分，形成分别填充所述第一间隙和所述第二间隙的所述第一填充结构和所述第二填充结构。
本公开实施例提供一种电子设备，其包括上述任一所述的MEMS器件。
附图说明
图1为一种示例性的MEMS器件作为一种开关器件的开态示意图。
图2为一种示例性的MEMS器件作为一种开关器件的关态示意图。
图3为一种示例性的MEMS器件作为另一种开关器件的开态示意图。
图4为一种示例性的MEMS器件作为另一种开关器件的关态示意图。
图5为本公开实施例的MEMS器件的结构示意图。
图6为本公开实施例的第一种示例的MEMS器件的结构示意图。
图7为图6所示的MEMS器件的制备流程图。
图8为本公开实施例的第二种示例的MEMS器件的结构示意图。
图9为图8所示的MEMS器件的制备流程图。
图10为本公开实施例的第三种示例的MEMS器件的结构示意图。
图11为图10所示的MEMS器件的制备流程图。
图12为本公开实施例的第四种示例的MEMS器件的结构示意图。
图13为图12所示的MEMS器件的制备流程图。
图14为本公开实施例的第五种示例的MEMS器件的结构示意图。
图15为图14所示的MEMS器件的一种制备流程图。
图16为图14所示的MEMS器件的另一种制备流程图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
微机电系统(MEMS，Micro-Electro-Mechanical System)，也叫做微电子机械系统、微系统、微机械等，指尺寸在几毫米乃至更小的高科技装置。本公开实施例中的MEMS器件可以为以MEMS为基础任何器件，例如：可以用于射频RF开关、探针探测、谐振梁。同样适用于圆形振膜、多边形振膜等其它微结构的设计与应用，包括但不限于加速计、角速度计、微型麦克风、微机电干涉显示、微机电电容式超声换能器、微镜等结构。
MEMS器件可用作开关器件，图1为一种示例性的MEMS器件作为一种开关器件的开态示意图；图2为一种示例性的MEMS器件作为一种开关器件的关态示意图；如图1和2所示，该MEMS器件100包括介质基板上，设置介质基板10上的驱动电极30、第一参考电极和第二参考电极，覆盖驱动电极30的第一介质层40，设置在第一介质层40上方的膜桥20，该膜桥20包括桥面21和连接在桥面结构21两端连接臂22。膜桥20的桥面21横跨驱动动电极，与驱动电极30上方的第一介质层40之间具有一定的距离。也即膜桥20和介质基板10围成一活动空间。其中，第一参考电极51、第二参考电极52分别位于驱动电极30延伸方向的两侧，三者可构成CPW传 输线结构。第一参考电极21和第二参考电极52可以为写入参考地信号。
参照图2，当给驱动电极30和膜桥20施加一定的电压时，膜桥20的桥面结构21将会在静电力作用下，向驱动电极30侧运动，从而实现开关的关态。惨参照图1，当将驱动电极30和膜桥20上的电压撤掉，膜桥20将恢复到初始位置，此时开关开态。
需要说明的是，图1和2中给出了一种双臂固定梁结构的MEMS开关，对于MEMS开关也可以仅包括一个连接臂22，也即MEMS开关为悬臂梁结构，图3为一种示例性的MEMS器件作为另一种开关器件的开态示意图；图4为一种示例性的MEMS器件作为另一种开关器件的关态示意图；如图3和4所示，该种开关的工作原理与上述双臂固定梁结构的MEMS开关相同，故在此不再重复描述。
发明人发现，当第一介质层覆盖驱动电极时，由于力学性能，导致第一电介质层覆盖在驱动电极背离介质基板的表面的厚度大于覆盖在驱动电极侧面的厚度，也就是说驱动电极侧面的第一介质层的厚度较薄，这样一来，在膜桥下拉时与下方的驱动电极之间的距离过近将会导致尖端放电，就会存在将驱动电极侧面的第一介质层击穿造成器件损坏的风险。
基于上述技术问题，本公开实施例提供如下MEMS器件及其制备方法。图5为本公开实施例的一种MEMS器件的结构示意图；如图5所示，本公开实施例中的MEMS器件，其包括介质基板10，设置在介质基板10上的驱动电极30、第一参考电极51、第二参考电极52、第一介质层40和膜桥。其中，第一参考电极51和第二参考电极52分别位于驱动电极30延伸方向的两侧，且第一参考电极51和驱动电极30之间具有第一间隙Q1，第二参考电极52和驱动电极30之间具有第二间隙Q2。第一介质层40至少覆盖驱动电极30。膜桥设置在第一介质层40背离介质基板10的一侧，且膜桥在介质基板10上的正投影的两端，分别位于第一参考电极51和第二参考电极52在介质基板10上的正投影上；驱动电极30位于膜桥和介质基板10所围成的空间内。
在本公开的MEMS器件满足以下情况中的至少一者。第一种情况：第一介质层40位于第一间隙Q1和第二间隙Q2的部分的厚度大于驱动电极30的厚度，例如：第一介质层40不仅覆盖驱动电极30而且填充第一间隙Q1和第二间隙Q2，此时驱动电极30的侧面所覆盖的第一介质层40的厚度较厚，可以有效的避免在膜桥下拉时与下方的驱动电极30之间的距离过近将会导致尖端放电，导致驱动电极30侧面的第一介质层40击穿造成器件损坏的风险。第二种情况：在膜桥的桥面21靠近介质基板10的表面设置第二介质层70，且第二介质层70在介质基板10上的正投影至少覆盖驱动电极30在介质基板10上的正投影，通过设置第二介质层70同样可以有效的避免在膜桥下拉时与下方的驱动电极30之间的距离过近将会导致尖端放电，导致驱动电极30侧面的第一介质层40击穿造成器件损坏的风险。
为了更清楚本公开实施例的MEMS器件的结构，以下结合具体示例及制备方法对本公开实施例的MEMS器件进行详细说明。
第一种示例：图6为本公开实施例的第二种示例的MEMS器件的结构示意图；如图6所示，MEMS器件包括介质基板10，设置在介质基板10上的驱动电极30、第一参考电极51、第二参考电极52、第一介质层40和膜桥。其中，第一参考电极51和第二参考电极52分别位于驱动电极30延伸方向的两侧，且第一参考电极51和驱动电极30之间具有第一间隙Q1，第二参考电极52和驱动电极30之间具有第二间隙Q2。第一介质层40包括沿背离介质基板10方向依次设置的第一子介质层41和第二子介质层42。第一子介质层41覆盖驱动电极30背离介质基板10的一侧；第二子介质层42包括第一填充结构和第二填充结构，且第一填充结构和第二填充结构分别填充第一间隙Q1和第二间隙Q2。膜桥设置在第一介质层40背离介质基板10的一侧，且膜桥在介质基板10上的正投影的两端，分别位于第一参考电极51和第二参考电极52在介质基板10上的正投影上；驱动电极30位于膜桥和介质基板10所围成的空间内。
在一些示例中，继续参照图6，第一子介质层41覆盖第一间隙Q1和第二间隙Q2，并分别在第一间隙Q1和第二间隙Q2中形成第一槽部和第二槽 部，第一填充结构填充第一槽部，第二填充结构填充第二槽部。为保证第一介质层40背离介质基板10的表面平坦，此时第一填充结构和第二填充结构的厚度与驱动电极30的厚度相同。
进一步的，第一子介质层41的材料可以选用氧化硅。第二子介质层42，也即第一填充结构和第二填充结构的材料可以选用树脂胶。
在一些示例中，驱动电极30、第一参考电极51和第二参考电极52的材料包括但不限于铜。膜桥20可以有叠层设置的三层结构组成，三层结构的材料分别选用为钼、铝、钼。
接下来对第一种示例的MEMS器件的制备方法进行说明，图7为图6所示的MEMS器件的制备流程图；如图7所示，该制备方法具体可以包括如下步骤。
S11、提供一介质基板10。
在一些示例中，介质基板1010具体可以为玻璃衬底，在步骤S11中可以选用0.5T的玻璃衬底，之后对该玻璃衬底经过标准清洗工艺进行清洗。
S12、在介质基板10上形成驱动电极30、第一参考电极51和第二参考电极52；其中，第一参考电极51和第二参考电极52分别位于驱动电极30延伸方向的两侧，且第一参考电极51和驱动电极30之间具有第一间隙Q1，第二参考电极52和驱动电极30之间具有第二间隙Q2。
在一些示例中，步骤S12可以包括：采用包括但不限于磁控溅射第一导电薄膜，之后，涂胶、曝光、显影、刻蚀(例如：湿法刻蚀)形成包括驱动电极30、第一参考电极51和第二参考电极52，最后，去除剩余光刻胶，完成驱动电极30、第一参考电极51和第二参考电极52制备。
S13、在驱动电极30、第一参考电极51和第二参考电极52所在层背离介质基板10的一侧形成第一介质层40中的第一子介质层41；其中，第一子介质层41覆盖驱动电极30，还可以覆盖第一间隙Q1和第二间隙Q2。此时，第一子介质层41形成分别位于第一间隙Q1和第二间隙Q2的第一凹槽部和第二凹槽部。
在一些示例中，第一子介质层41可以采用氧化硅。当第一子介质层41采用氧化硅时，步骤S13可以包括采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式，在驱动电极30、第一参考电极51和第二参考电极52所在层背离介质基板10的一侧形成第一介质层40中的第一子介质层41。
需要说明的是，图6中所形成的第一子介质层41还覆盖部分第一子参考电极和部分第二子参考电极，以保证后续在第一槽部和第二槽部内形成第二子介质层42的厚度均匀。
S14、在第一子介质层41背离介质基板10的一侧形成第二子介质层42，第二子介质层42包括填充第一凹槽部的第一填充结构和填充第二凹槽部的第二填充结构。
在一些示例中，第二子介质层42的材料包括但不限于树脂胶。以第二子介质层42采用树脂胶为例，步骤S14可以包括：首先通过匀胶工艺在第一槽部和第二槽部内分别形成填充材料，且填充材料在介质基板10上的正投影覆盖第一间隙Q1和第二间隙Q2在介质基板10上的正投影，之后加热对填充材料，以使填充材料重塑回填，以形成填充第一凹槽部的第一填充结构和填充第二凹槽部的第二填充结构。
需要说明的是，第一填充结构和第二填充结构的厚度与驱动电极30的厚度相同，对于第一填充结构和第二填充结构的厚度把控可以通过控匀胶转速来实现。
S15、在第一子介质层41和第二子介质层42背离介质基板10的一侧形成牺牲层60。
在一些示例中，牺牲层60的材料可以采用氮化硅，之所以采用氮化硅是因为在后续去除牺牲层60时，不会对氧化硅材质的第一子介质层41造成损伤。当牺牲层60的材料采用氮化硅时，步骤S15可以包括采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式，在第一子介质层41和第二 子介质层42背离介质基板10的一侧形成牺牲层60。
S16、在牺牲层60背离介质基板10的一侧形成膜桥，膜桥在介质基板10上的正投影的两端，分别位于第一参考电极51和第二参考电极52在所述介质基板10上的正投影上；所述驱动电极30位于膜桥和介质基板10所围成的空间内。
在一些示例中，膜桥的两个连接臂22分别与第一参考电极51和第二参考电极52接触且电连接。步骤S16具体可以包括采用包括但不限于磁控溅射第二导电薄膜，之后，涂胶、曝光、显影、刻蚀(例如：湿法刻蚀)形成包括膜桥的图形，最后去除光刻胶，完成膜桥的制备。
S17、去除牺牲层60。
在一些示例中，步骤S17可以包括通过采用反应离子刻蚀(RIE)，合理控制气体氛围(侧向刻蚀强度)、压强、功率(刻蚀速率)、刻蚀时间等，对膜桥下方的牺牲层60进行精确控制刻蚀，以去除位于膜桥下的牺牲层60，以完成MEMS器件的制备。其中，气体氛围为SF 6气体。
第二种示例：图8为本公开实施例的第二种示例的MEMS器件的结构示意图；如图8所示，MEMS器件包括介质基板10，设置在介质基板10上的驱动电极30、第一参考电极51、第二参考电极52、第一介质层40、第二介质层70和膜桥。其中，第一参考电极51和第二参考电极52分别位于驱动电极30延伸方向的两侧，且第一参考电极51和驱动电极30之间具有第一间隙Q1，第二参考电极52和驱动电极30之间具有第二间隙Q2。第一介质层40包括沿背离介质基板10方向依次设置的第一子介质层41和第二子介质层42。第一子介质层41覆盖驱动电极30背离介质基板10的一侧；第二子介质层42包括第一填充结构和第二填充结构，且第一填充结构和第二填充结构分别填充第一间隙Q1和第二间隙Q2。膜桥设置在第一介质层40背离介质基板10的一侧，且膜桥在介质基板10上的正投影的两端，分别位于第一参考电极51和第二参考电极52在介质基板10上的正投影上；驱动 电极30位于膜桥和介质基板10所围成的空间内。第二介质层70位于膜桥的桥面21靠近介质基板10的表面，且第二介质层70在所述介质基板10上的正投影至少覆盖第一介质层40在介质基板10上的正投影。
在一些示例中，继续参照图8，第一子介质层41覆盖第一间隙Q1和第二间隙Q2，并分别在第一间隙Q1和第二间隙Q2中形成第一槽部和第二槽部，第一填充结构填充第一槽部，第二填充结构填充第二槽部。为保证第一介质层40背离介质基板10的表面平坦，此时第一填充结构和第二填充结构的厚度与驱动电极30的厚度相同。
进一步的，第一子介质层41和第二介质层70的材料可以选用氧化硅。第二子介质层42，也即第一填充结构和第二填充结构的材料可以选用树脂胶。
接下来对第二种示例的MEMS器件的制备方法进行说明，图9为图8所示的MEMS器件的制备流程图；如图9所示，该制备方法具体可以包括如下步骤。
S21、提供一介质基板10。
在一些示例中，介质基板10具体可以为玻璃衬底，在步骤S21中可以选用0.5T的玻璃衬底，之后对该玻璃衬底经过标准清洗工艺进行清洗。
S22、在介质基板10上形成驱动电极30、第一参考电极51和第二参考电极52；其中，第一参考电极51和第二参考电极52分别位于驱动电极30延伸方向的两侧，且第一参考电极51和驱动电极30之间具有第一间隙Q1，第二参考电极52和驱动电极30之间具有第二间隙Q2。
在一些示例中，步骤S22可以包括：采用包括但不限于磁控溅射第一导电薄膜，之后，涂胶、曝光、显影、刻蚀(例如：湿法刻蚀)形成包括驱动电极30、第一参考电极51和第二参考电极52，最后，去除剩余光刻胶，完成驱动电极30、第一参考电极51和第二参考电极52制备。
S23、在驱动电极30、第一参考电极51和第二参考电极52所在层背离介质基板10的一侧形成第一介质层40中的第一子介质层41；其中，第一 子介质层41覆盖驱动电极30，还可以覆盖第一间隙Q1和第二间隙Q2。此时，第一子介质层41形成分别位于第一间隙Q1和第二间隙Q2的第一凹槽部和第二凹槽部。
在一些示例中，第一子介质层41可以采用氧化硅。当第一子介质层41采用氧化硅时，步骤S23可以包括采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式，在驱动电极30、第一参考电极51和第二参考电极52所在层背离介质基板10的一侧形成第一介质层40中的第一子介质层41。
需要说明的是，图8中所形成的第一子介质层41还覆盖部分第一子参考电极和部分第二子参考电极，以保证后续在第一槽部和第二槽部内形成第二子介质层42的厚度均匀。
S24、在第一子介质层41背离介质基板10的一侧形成第二子介质层42，第二子介质层42包括填充第一凹槽部的第一填充结构和填充第二凹槽部的第二填充结构。
在一些示例中，第二子介质层42的材料包括但不限于树脂胶。以第二子介质层42采用树脂胶为例，步骤S24可以包括：首先通过匀胶工艺在第一槽部和第二槽部内分别形成填充材料，且填充材料在介质基板10上的正投影覆盖第一间隙Q1和第二间隙Q2在介质基板10上的正投影，之后加热对填充材料，以使填充材料重塑回填，以形成填充第一凹槽部的第一填充结构和填充第二凹槽部的第二填充结构。
需要说明的是，第一填充结构和第二填充结构的厚度与驱动电极30的厚度相同，对于第一填充结构和第二填充结构的厚度把控可以通过控匀胶转速来实现。
S25、在第一子介质层41和第二子介质层42背离介质基板10的一侧形成牺牲层60。
在一些示例中，牺牲层60的材料可以采用氮化硅，之所以采用氮化硅是因为在后续去除牺牲层60时，不会对氧化硅材质的第一子介质层41造成 损伤。当牺牲层60的材料采用氮化硅时，步骤S25可以包括采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式，在第一子介质层41和第二子介质层42背离介质基板10的一侧形成牺牲层60。
S26、在牺牲层60背离介质基板10的一侧形成第二介质层70。
在一些示例中，第二介质层70可以采用氧化硅。当第一子介质层41采用氧化硅时，步骤S26可以包括采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式，在牺牲层60背离介质基板10的一侧形成第二介质层70。
S27、在第二介质层70背离介质基板10的一侧形成膜桥，膜桥在介质基板10上的正投影的两端，分别位于第一参考电极51和第二参考电极52在所述介质基板10上的正投影上；所述驱动电极30位于膜桥和介质基板10所围成的空间内。
在一些示例中，膜桥的两个连接臂22分别与第一参考电极51和第二参考电极52接触且电连接。步骤S27具体可以包括采用包括但不限于磁控溅射第二导电薄膜，之后，涂胶、曝光、显影、刻蚀(例如：湿法刻蚀)形成包括膜桥的图形，最后去除光刻胶，完成膜桥的制备。
S28、去除牺牲层60。
在一些示例中，步骤S28可以包括通过采用反应离子刻蚀(RIE)，合理控制气体氛围(侧向刻蚀强度)、压强、功率(刻蚀速率)、刻蚀时间等，对膜桥下方的牺牲层60进行精确控制刻蚀，以去除位于膜桥下的牺牲层60，以完成MEMS器件的制备。其中，气体氛围为SF 6气体。
第三种示例：图10为本公开实施例的第二种示例的MEMS器件的结构示意图；如图10所示，MEMS器件包括介质基板10，设置在介质基板10上的驱动电极30、第一参考电极51、第二参考电极52、第一介质层40、第二介质层70和膜桥。其中，第一参考电极51和第二参考电极52分别位于 驱动电极30延伸方向的两侧，且第一参考电极51和驱动电极30之间具有第一间隙Q1，第二参考电极52和驱动电极30之间具有第二间隙Q2。膜桥设置在第一介质层40背离介质基板10的一侧，且膜桥在介质基板10上的正投影的两端，分别位于第一参考电极51和第二参考电极52在介质基板10上的正投影上；驱动电极30位于膜桥和介质基板10所围成的空间内。第二介质层70位于膜桥的桥面21靠近介质基板10的表面，且第二介质层70在所述介质基板10上的正投影至少覆盖第一介质层40在介质基板10上的正投影。而且第二介质层70具有朝向介质基板10凸出的第一凸出部71第一凸出部71。通过设置第一凸出部71第一凸出部71可以有效的避免膜桥在下拉后无法弹起，保证了MEMS器件的可靠性和可重复使用性，提高了器件性能。
在一些示例中，继续参照图10，膜桥的桥面21具有朝向第一介质层40凸出的第二凸出部211，且第二凸出部211与第一凸出部71第一凸出部71一一对应设置的，且第二凸出部211嵌在与之对应的第一凸出部71第一凸出部71内。在该种情况下，可以保证膜桥的桥面21可以与第二介质层70稳定贴合。
进一步的，第一介质层40和第二介质层70的材料可以选用氧化硅。
接下来对第三种示例的MEMS器件的制备方法进行说明，图11为图10所示的MEMS器件的制备流程图；如图11所示，该制备方法具体可以包括如下步骤。
S31、提供一介质基板10。
在一些示例中，介质基板10具体可以为玻璃衬底，在步骤S31中可以选用0.5T的玻璃衬底，之后对该玻璃衬底经过标准清洗工艺进行清洗。
S32、在介质基板10上形成驱动电极30、第一参考电极51和第二参考电极52；其中，第一参考电极51和第二参考电极52分别位于驱动电极30延伸方向的两侧，且第一参考电极51和驱动电极30之间具有第一间隙Q1，第二参考电极52和驱动电极30之间具有第二间隙Q2。
在一些示例中，步骤S32可以包括：采用包括但不限于磁控溅射第一导电薄膜，之后，涂胶、曝光、显影、刻蚀(例如：湿法刻蚀)形成包括驱动电极30、第一参考电极51和第二参考电极52，最后，去除剩余光刻胶，完成驱动电极30、第一参考电极51和第二参考电极52制备。
S33、在驱动电极30、第一参考电极51和第二参考电极52所在层背离介质基板10的一侧形成第一介质层40；其中，第一介质层40覆盖驱动电极30，还可以覆盖第一间隙Q1和第二间隙Q2。此时，第一介质层40形成分别位于第一间隙Q1和第二间隙Q2的第一凹槽部和第二凹槽部。
在一些示例中，第一介质层40可以采用氧化硅。当第一介质层40采用氧化硅时，步骤S33可以包括采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式，在驱动电极30、第一参考电极51和第二参考电极52所在层背离介质基板10的一侧形成第一介质层40中的第一介质层40。
需要说明的是，图10中所形成的第一介质层40还覆盖部分第一子参考电极和部分第二子参考电极。
S34、在第一介质层40背离介质基板10的一侧形成牺牲层60。此时由于第一间隙Q1和第二间隙Q2的存在第一介质层40形成有第一凹槽部和第二凹槽部，故牺牲层60背离介质基板10的表面形成有第二凹陷部61。第二凹陷部61的数量为两个，分别对应第一凹槽部和第二凹槽部。
在一些示例中，牺牲层60的材料可以采用氮化硅，之所以采用氮化硅是因为在后续去除牺牲层60时，不会对氧化硅材质的第一介质层40造成损伤。当牺牲层60的材料采用氮化硅时，步骤S34可以包括采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式，在第一介质层40背离介质基板10的一侧形成牺牲层60。
S35、在牺牲层60背离介质基板10的一侧形成第二介质层70，由于牺牲层60上具有第二凹陷部61，此时所形成的第二介质层70具有朝向介质 基板10凸出的第一凸出部71第一凸出部71，第一凸出部71第一凸出部71与第二凹陷部61对应设置，且一个第一凸出部71第一凸出部71嵌在一个第二凹陷部61内。
在一些示例中，第二介质层70可以采用氧化硅。当第一子介质层41采用氧化硅时，步骤S35可以包括采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式，在牺牲层60背离介质基板10的一侧形成第二介质层70。
S36、在第二介质层70背离介质基板10的一侧形成膜桥，膜桥在介质基板10上的正投影的两端，分别位于第一参考电极51和第二参考电极52在所述介质基板10上的正投影上；所述驱动电极30位于膜桥和介质基板10所围成的空间内。由于第二介质层70具有第一凸出部71第一凸出部71，故膜桥的桥面21具有朝向第一介质层40凸出的第二凸出部211，且第二凸出部211与第一凸出部71第一凸出部71一一对应设置的，且第二凸出部211嵌在与之对应的第一凸出部71第一凸出部71内。
在一些示例中，膜桥的两个连接臂22分别与第一参考电极51和第二参考电极52接触且电连接。步骤S36具体可以包括采用包括但不限于磁控溅射第二导电薄膜，之后，涂胶、曝光、显影、刻蚀(例如：湿法刻蚀)形成包括膜桥的图形，最后去除光刻胶，完成膜桥的制备。
S37、去除牺牲层60。
在一些示例中，步骤S37可以包括通过采用反应离子刻蚀(RIE)，合理控制气体氛围(侧向刻蚀强度)、压强、功率(刻蚀速率)、刻蚀时间等，对膜桥下方的牺牲层60进行精确控制刻蚀，以去除位于膜桥下的牺牲层60，以完成MEMS器件的制备。其中，气体氛围为SF 6气体。
第四种示例：图12为本公开实施例的第二种示例的MEMS器件的结构示意图；如图12所示，MEMS器件包括介质基板10，设置在介质基板10上的驱动电极30、第一参考电极51、第二参考电极52、第一介质层40、第 二介质层70和膜桥。其中，第一参考电极51和第二参考电极52分别位于驱动电极30延伸方向的两侧，且第一参考电极51和驱动电极30之间具有第一间隙Q1，第二参考电极52和驱动电极30之间具有第二间隙Q2。第一子介质层41覆盖驱动电极30背离介质基板10的一侧；第二子介质层42包括第一填充结构和第二填充结构，且第一填充结构和第二填充结构分别填充第一间隙Q1和第二间隙Q2。而且第一填充结构和第二填充结构均具有与第一子介质层41接触的第一面，与介质基板10相对设置的第二面，以及连接第一表面和第二面的第一连接面；第一连接面和第一子介质层41限定出第一凹陷部80。膜桥设置在第一介质层40背离介质基板10的一侧，且膜桥在介质基板10上的正投影的两端，分别位于第一参考电极51和第二参考电极52在介质基板10上的正投影上；驱动电极30位于膜桥和介质基板10所围成的空间内。第二介质层70位于膜桥的桥面21靠近介质基板10的表面，且第二介质层70在所述介质基板10上的正投影至少覆盖第一介质层40在介质基板10上的正投影。而且第二介质层70具有朝向介质基板10凸出的第一凸出部71第一凸出部71，第一凸出部71第一凸出部71与第一凹陷部80一一对应设置。通过设置第一凸出部71第一凸出部71可以有效的避免膜桥在下拉后无法弹起，保证了MEMS器件的可靠性和可重复使用性，提高了器件性能。
在一些示例中，继续参照图12，膜桥的桥面21具有朝向第一介质层40凸出的第二凸出部211，且第二凸出部211与第一凸出部71第一凸出部71一一对应设置的，且第二凸出部211嵌在与之对应的第一凸出部71第一凸出部71内。在该种情况下，可以保证膜桥的桥面21可以与第二介质层70稳定贴合。
进一步的，第一子介质层41和第二介质层70的材料可以选用氧化硅。第二子介质层42，也即第一填充结构和第二填充结构的材料可以选用树脂胶。
接下来对第四种示例的MEMS器件的制备方法进行说明，图13为图12所示的MEMS器件的制备流程图；如图13所示，该制备方法具体可以包括 如下步骤。
S41、提供一介质基板10。
在一些示例中，介质基板10具体可以为玻璃衬底，在步骤S31中可以选用0.5T的玻璃衬底，之后对该玻璃衬底经过标准清洗工艺进行清洗。
S42、在介质基板10上形成驱动电极30、第一参考电极51和第二参考电极52；其中，第一参考电极51和第二参考电极52分别位于驱动电极30延伸方向的两侧，且第一参考电极51和驱动电极30之间具有第一间隙Q1，第二参考电极52和驱动电极30之间具有第二间隙Q2。
在一些示例中，步骤S42可以包括：采用包括但不限于磁控溅射第一导电薄膜，之后，涂胶、曝光、显影、刻蚀(例如：湿法刻蚀)形成包括驱动电极30、第一参考电极51和第二参考电极52，最后，去除剩余光刻胶，完成驱动电极30、第一参考电极51和第二参考电极52制备。
S43、在驱动电极30、第一参考电极51和第二参考电极52所在层背离介质基板10的一侧形成第一子介质层41；其中，第一子介质层41覆盖驱动电极30，还可以覆盖第一间隙Q1和第二间隙Q2。此时，第一子介质层41形成分别位于第一间隙Q1和第二间隙Q2的第一凹槽部和第二凹槽部。
在一些示例中，第一子介质层41可以采用氧化硅。当第一子介质层41采用氧化硅时，步骤S43可以包括采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式，在驱动电极30、第一参考电极51和第二参考电极52所在层背离介质基板10的一侧形成第一介质层40中的第一子介质层41。
需要说明的是，图12中所形成的第一子介质层41还覆盖部分第一子参考电极和部分第二子参考电极。
S44、在第一子介质层41背离介质基板10的一侧形成第二子介质层42，第二子介质层42包括填充第一凹槽部的第一填充结构和填充第二凹槽部的第二填充结构。其中，所形成的第一填充结构和第二填充结构均具有与第一子介质层41接触的第一面，与介质基板10相对设置的第二面，以及连接第 一表面和第二面的第一连接面；第一连接面和第一子介质层41限定出第一凹陷部80。
在一些示例中，第二子介质层42的材料包括但不限于树脂胶。以第二子介质层42采用树脂胶为例，步骤S44可以包括：首先通过匀胶工艺在第一槽部和第二槽部内分别形成填充材料，且填充材料在介质基板10上的正投影覆盖第一间隙Q1和第二间隙Q2在介质基板10上的正投影，之后通过退火填充材料重塑回填，以形成填充第一凹槽部的第一填充结构和填充第二凹槽部的第二填充结构，此时所形成的第一填充结构和第二填充结构均具有与第一子介质层41接触的第一面，与介质基板10相对设置的第二面，以及连接第一表面和第二面的第一连接面；第一连接面和第一子介质层41限定出第一凹陷部80。
需要说明的是，第一填充结构和第二填充结构的厚度与驱动电极30的厚度相同，对于第一填充结构和第二填充结构的厚度把控可以通过控匀胶转速来实现。
S45、在第一介质层40背离介质基板10的一侧形成牺牲层60。此时由于第二子介质层42和第一子介质层41形成第一凹陷部80，故牺牲层60背离介质基板10的表面形成有第二凹陷部61。第二凹陷部61与第一凹陷部80一一对应设置的，且第二凹陷部61嵌入与之对应的第一凹陷部80内。
在一些示例中，牺牲层60的材料可以采用氮化硅，之所以采用氮化硅是因为在后续去除牺牲层60时，不会对氧化硅材质的第一介质层40造成损伤。当牺牲层60的材料采用氮化硅时，步骤S45可以包括采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式，在第一介质层40背离介质基板10的一侧形成牺牲层60。
S46、在牺牲层60背离介质基板10的一侧形成第二介质层70，由于牺牲层60上具有第二凹陷部61，此时所形成的第二介质层70具有朝向介质基板10凸出的第一凸出部71第一凸出部71，第一凸出部71第一凸出部71 与第二凹陷部61对应设置，且一个第一凸出部71第一凸出部71嵌在一个第二凹陷部61内。
在一些示例中，第二介质层70可以采用氧化硅。当第一子介质层41采用氧化硅时，步骤S46可以包括采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式，在牺牲层60背离介质基板10的一侧形成第二介质层70。
S47、在第二介质层70背离介质基板10的一侧形成膜桥，膜桥在介质基板10上的正投影的两端，分别位于第一参考电极51和第二参考电极52在所述介质基板10上的正投影上；所述驱动电极30位于膜桥和介质基板10所围成的空间内。由于第二介质层70具有第一凸出部71第一凸出部71，故膜桥的桥面21具有朝向第一介质层40凸出的第二凸出部211，且第二凸出部211与第一凸出部71第一凸出部71一一对应设置的，且第二凸出部211嵌在与之对应的第一凸出部71第一凸出部71内。
在一些示例中，膜桥的两个连接臂22分别与第一参考电极51和第二参考电极52接触且电连接。步骤S47具体可以包括采用包括但不限于磁控溅射第二导电薄膜，之后，涂胶、曝光、显影、刻蚀(例如：湿法刻蚀)形成包括膜桥的图形，最后去除光刻胶，完成膜桥的制备。
S48、去除牺牲层60。
在一些示例中，步骤S48可以包括通过采用反应离子刻蚀(RIE)，合理控制气体氛围(侧向刻蚀强度)、压强、功率(刻蚀速率)、刻蚀时间等，对膜桥下方的牺牲层60进行精确控制刻蚀，以去除位于膜桥下的牺牲层60，以完成MEMS器件的制备。其中，气体氛围为SF 6气体。
第五种示例：图14为本公开实施例的第二种示例的MEMS器件的结构示意图；如图14所示，MEMS器件包括介质基板10，设置在介质基板10上的驱动电极30、第一参考电极51、第二参考电极52、第一介质层40和膜桥。其中，第一参考电极51和第二参考电极52分别位于驱动电极30延 伸方向的两侧，且第一参考电极51和驱动电极30之间具有第一间隙Q1，第二参考电极52和驱动电极30之间具有第二间隙Q2。第一介质层40包括沿背离介质基板10方向依次设置的第二子介质层42和第一子介质层41。第一子介质层41覆盖第二介质层70背离介质基板10的一侧；第二子介质层42包括第一填充结构和第二填充结构，且第一填充结构和第二填充结构分别填充第一间隙Q1和第二间隙Q2。膜桥设置在第一介质层40背离介质基板10的一侧，且膜桥在介质基板10上的正投影的两端，分别位于第一参考电极51和第二参考电极52在介质基板10上的正投影上；驱动电极30位于膜桥和介质基板10所围成的空间内。
在一些示例中，继续参照图14，为保证第一子介质层41背离介质基板10的表面平坦，此时第一填充结构和第二填充结构的厚度与驱动电极30的厚度相同。
进一步的，第一子介质层41的材料可以选用氧化硅。第二子介质层42，也即第一填充结构和第二填充结构的材料可以选用树脂胶。
接下来对第五种示例的MEMS器件的制备方法进行说明，图15为图14所示的MEMS器件的制备流程图；如图15所示，该制备方法具体可以包括如下步骤。
S51、提供一介质基板10。
在一些示例中，介质基板10具体可以为玻璃衬底，在步骤S51中可以选用0.5T的玻璃衬底，之后对该玻璃衬底经过标准清洗工艺进行清洗。
S52、在介质基板10上形成驱动电极30、第一参考电极51和第二参考电极52；其中，第一参考电极51和第二参考电极52分别位于驱动电极30延伸方向的两侧，且第一参考电极51和驱动电极30之间具有第一间隙Q1，第二参考电极52和驱动电极30之间具有第二间隙Q2。
在一些示例中，步骤S52可以包括：采用包括但不限于磁控溅射第一导电薄膜，之后，涂胶、曝光、显影、刻蚀(例如：湿法刻蚀)形成包括驱动电极30、第一参考电极51和第二参考电极52，最后，去除剩余光刻胶，完 成驱动电极30、第一参考电极51和第二参考电极52制备。
S53、在驱动电极30、第一参考电极51和第二参考电极52所在层背离介质基板10的一侧形成第一介质层40中的第二子介质层42，第二子介质层42包括填充第一间隙Q1的第一填充结构和填充第二间隙Q2的第二填充结构。
在一些示例中，第二子介质层42的材料包括但不限于树脂胶。以第二子介质层42采用树脂胶为例，步骤S53可以包括：首先通过匀胶工艺在第一间隙Q1和第二间隙Q2内分别形成填充材料，且填充材料在介质基板10上的正投影覆盖第一间隙Q1和第二间隙Q2在介质基板10上的正投影，之后加热对填充材料，以使填充材料重塑回填，以形成填充第一间隙Q1的第一填充结构和填充第二间隙Q2的第二填充结构。
需要说明的是，第一填充结构和第二填充结构的厚度与驱动电极30的厚度相同，对于第一填充结构和第二填充结构的厚度把控可以通过控匀胶转速来实现。
S54、在第一子介质层41背离介质基板10的一侧形成第一子介质层41；其中，第一子介质层41覆盖第二子介质层42，还可以覆盖驱动电极30。
在一些示例中，第一子介质层41可以采用氧化硅。当第一子介质层41采用氧化硅时，步骤S54可以包括采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式，在第二子介质层42背离介质基板10的一侧形成第一介质层40中的第一子介质层41。
需要说明的是，图14中所形成的第一子介质层41还覆盖部分第一子参考电极和部分第二子参考电极，以保证后续在第一槽部和第二槽部内形成第二子介质层42的厚度均匀。
S55、在第一子介质层41和第二子介质层42背离介质基板10的一侧形成牺牲层60。
在一些示例中，牺牲层60的材料可以采用氮化硅，之所以采用氮化硅 是因为在后续去除牺牲层60时，不会对氧化硅材质的第一子介质层41造成损伤。当牺牲层60的材料采用氮化硅时，步骤S55可以包括采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式，在第一子介质层41背离介质基板10的一侧形成牺牲层60。
S56、在牺牲层60背离介质基板10的一侧形成膜桥，膜桥在介质基板10上的正投影的两端，分别位于第一参考电极51和第二参考电极52在所述介质基板10上的正投影上；所述驱动电极30位于膜桥和介质基板10所围成的空间内。
在一些示例中，膜桥的两个连接臂22分别与第一参考电极51和第二参考电极52接触且电连接。步骤S56具体可以包括采用包括但不限于磁控溅射第二导电薄膜，之后，涂胶、曝光、显影、刻蚀(例如：湿法刻蚀)形成包括膜桥的图形，最后去除光刻胶，完成膜桥的制备。
S57、去除牺牲层60。
在一些示例中，步骤S57可以包括通过采用反应离子刻蚀(RIE)，合理控制气体氛围(侧向刻蚀强度)、压强、功率(刻蚀速率)、刻蚀时间等，对膜桥下方的牺牲层60进行精确控制刻蚀，以去除位于膜桥下的牺牲层60，以完成MEMS器件的制备。其中，气体氛围为SF 6气体。
在一些示例中，上述的牺牲层60以采用氮化硅为例，牺牲层60的材料还可以采用光刻胶，此时对应的第一介质层40可以采用氮化硅/氧化硅复合膜层。当牺牲层60采用光刻胶时，在后续可以采用湿法刻蚀去除牺牲层60。
针对第五种示例的MEMS器件，本公开实施例中还提供一种MEMS器件的制备方法，图16为图14所示的MEMS器件的制备流程图；如图16所示，该制备方法包括步骤如下步骤。
S61、提供一介质基板10。
在一些示例中，介质基板10具体可以为玻璃衬底，在步骤S61中可以选用0.5T的玻璃衬底，之后对该玻璃衬底经过标准清洗工艺进行清洗。
S62、在介质基板10上形成驱动电极30、第一参考电极51和第二参考电极52；其中，第一参考电极51和第二参考电极52分别位于驱动电极30延伸方向的两侧，且第一参考电极51和驱动电极30之间具有第一间隙Q1，第二参考电极52和驱动电极30之间具有第二间隙Q2。
在一些示例中，步骤S62可以包括：采用包括但不限于磁控溅射第一导电薄膜，之后，涂胶、曝光、显影、刻蚀(例如：湿法刻蚀)形成包括驱动电极30、第一参考电极51和第二参考电极52，最后，去除剩余光刻胶，完成驱动电极30、第一参考电极51和第二参考电极52制备。
S63、在驱动电极30、第一参考电极51和第二参考电极52所在层背离介质基板10的一侧形成填充材料，第二子介质层42包括覆盖第一间隙Q1、第二间隙Q2，以及驱动电极30。
在一些示例中，填充材料包括但不限于树脂胶。以第二子介质层42采用树脂胶为例，步骤S53可以包括：首先通过匀胶工艺在第一间隙Q1和第二间隙Q2内，以及驱动电极30上形成填充材料。
S64、去除驱动电极30上方的填充材料，仅剩余填充第一间隙Q1的第一填充结构和填充第二间隙Q2的第二填充结构，以形成第一介质层40的第二子介质层42；第一填充结构和第二填充结构的厚度与驱动电极30的厚度相同。
在一些示例中，步骤S64可以包括采用CMP化学机械抛光磨平驱动电极30上方的填充材料，仅剩余填充第一间隙Q1的第一填充结构和填充第二间隙Q2的第二填充结构，以形成第一介质层40的第二子介质层42；第一填充结构和第二填充结构的厚度与驱动电极30的厚度相同。
S65、在第一子介质层41背离介质基板10的一侧形成第一子介质层41；其中，第一子介质层41覆盖第二子介质层42，还可以覆盖驱动电极30。
在一些示例中，第一子介质层41可以采用氧化硅。当第一子介质层41采用氧化硅时，步骤S65可以包括采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉 积方式或溅射方式，在第二子介质层42背离介质基板10的一侧形成第一介质层40中的第一子介质层41。
需要说明的是，图14中所形成的第一子介质层41还覆盖部分第一子参考电极和部分第二子参考电极，以保证后续在第一槽部和第二槽部内形成第二子介质层42的厚度均匀。
S66、在第一子介质层41和第二子介质层42背离介质基板10的一侧形成牺牲层60。
在一些示例中，牺牲层60的材料可以采用氮化硅，之所以采用氮化硅是因为在后续去除牺牲层60时，不会对氧化硅材质的第一子介质层41造成损伤。当牺牲层60的材料采用氮化硅时，步骤S66可以包括采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式，在第一子介质层41背离介质基板10的一侧形成牺牲层60。
S67、在牺牲层60背离介质基板10的一侧形成膜桥，膜桥在介质基板10上的正投影的两端，分别位于第一参考电极51和第二参考电极52在所述介质基板10上的正投影上；所述驱动电极30位于膜桥和介质基板10所围成的空间内。
在一些示例中，膜桥的两个连接臂22分别与第一参考电极51和第二参考电极52接触且电连接。步骤S67具体可以包括采用包括但不限于磁控溅射第二导电薄膜，之后，涂胶、曝光、显影、刻蚀(例如：湿法刻蚀)形成包括膜桥的图形，最后去除光刻胶，完成膜桥的制备。
S68、去除牺牲层60。
在一些示例中，步骤S68可以包括通过采用反应离子刻蚀(RIE)，合理控制气体氛围(侧向刻蚀强度)、压强、功率(刻蚀速率)、刻蚀时间等，对膜桥下方的牺牲层60进行精确控制刻蚀，以去除位于膜桥下的牺牲层60，以完成MEMS器件的制备。其中，气体氛围为SF 6气体。
本公开实施例提供一种电子设备，其包括上述任一MEMS器件。该电 子设备包括但不限于移相器。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (20)

  1. 一种MEMS器件，其包括：
    介质基板；
    驱动电极、第一参考电极和第二参考电极，设置在所述介质基板上，且所述第一参考电极和所述第二参考电极分别位于所述驱动电极延伸方向两侧；
    第一介质层，覆盖在所述驱动电极背离所述介质基板的一侧；
    膜桥，设置在所述第一介质层背离所述介质基板的一侧，且所述膜桥在所述介质基板上的正投影的两端，分别位于所述第一参考电极和所述第二参考电极在所述介质基板上的正投影上；所述驱动电极位于所述膜桥和所述介质基板所围成的空间内；其中，
    所述第一参考电极和所述驱动电极之间具有第一间隙；所述第二参考电极和所述驱动电极之间具有第二间隙；
    所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度；和/或，在所述膜桥的桥面靠近所述介质基板的一侧设置有第二介质层，且所述第二介质层在所述介质基板上的正投影至少覆盖所述驱动电极在所述介质基板上的正投影。
  2. 根据权利要求1所述的MEMS器件，其中，当所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度时，所述第一介质层包括沿背离所述介质基板方向依次设置的第一子介质层和第二子介质层；
    所述第二子介质层包括第一填充结构和第二填充结构；所述第一填充结构和所述第二填充结构分别位于所述第一间隙和所述第二间隙。
  3. 根据权利要求2所述的MEMS器件，其中，所述第一子介质层覆盖所述第一间隙和所述第二间隙，且所述第一子介质层在所述第一间隙形成第一槽部，所述第二子介质层在所述第二间隙形成第二槽部；所述第一填充结构填充所述第一槽部，所述第二填充结构填充所述第二槽部。
  4. 根据权利要求2所述的MEMS器件，其中，所述第二子介质层的材料包括树脂胶。
  5. 根据权利要求1所述的MEMS器件，其中，当在所述膜桥的桥面靠近所述介质基板的一侧设置有所述第二介质层时，所述第二介质层具有朝向所述第一介质层凸出的第一凸出部。
  6. 根据权利要求5所述的MEMS器件，其中，所述膜桥的桥面具有朝向所述第一介质层凸出的第二凸出部，且所述第二凸出部与所述第一凸出部一一对应设置的，且所述第二凸出部嵌在与之对应的第一凸出部内。
  7. 根据权利要求5或6所述的MEMS器件，其中，当所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度时，所述第一介质层朝向所述第二介质层的表面具有第一凹陷部；所述第一凹陷部与所述第一凸出部一一对应设置。
  8. 根据权利要求7所述的MEMS器件，其中，所述第一介质层包括沿背离基板方向依次设置的第一子介质层和第二子介质层；
    所述第二子介质层包括第一填充结构和第二填充结构；所述第一填充结构和所述第二填充结构分别位于所述第一间隙和所述第二间隙。
  9. 根据权利要求8所述的MEMS器件，其中，所述第一填充结构和所述第二填充结构均具有与所述第一子介质层接触的第一面，与所述介质基板相对设置的第二面，以及连接所述第一表面和所述第二面的第一连接面；所述第一连接面和所述第一子介质层限定出所述第一凹陷部。
  10. 根据权利要求8所述的MEMS器件，其中，所述第二子介质层的材料包括树脂胶。
  11. 根据权利要求1所述的MEMS器件，其中，当所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度时，所述第一介质层包括沿靠近所述介质基板方向依次设置的第一子介质层和第二子介质层；
    所述第二子介质层包括第一填充结构和第二填充结构；所述第一填充结 构和所述第二填充结构分别位于所述第一间隙和所述第二间隙。
  12. 根据权利要求11所述的MEMS器件，其中，所述第二子介质层的材料包括树脂胶。
  13. 一种MEMS器件的制备方法，其包括：
    提供一介质基板；
    在所述介质基板上形成驱动电极、第一参考电极和第二参考电极；所述第一参考电极和所述第二参考电极分别位于所述驱动电极延伸方向两侧；
    在驱动电极、所述第一参考电极和所述第二参考电极背离所述介质基板的一侧形成第一介质层；
    在所述第一介质层背离所述介质基板的一侧形成膜桥；所述膜桥在所述介质基板上的正投影的两端，分别位于所述第一参考电极和所述第二参考电极在所述介质基板上的正投影上；所述驱动电极位于所述膜桥和所述介质基板所围成的空间内；其中，
    所述第一参考电极和所述驱动电极之间限定出第一间隙；所述第二参考电极和所述驱动电极之间限定出第二间隙；所形成所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度；和/或，
    所述制备方法还包括：在所述膜桥的桥面靠近所述介质基板的一侧设置有第二介质层，且所述第二介质层在所述介质基板上的正投影至少覆盖所述驱动电极在所述介质基板上的正投影。
  14. 根据权利要求13所述的MEMS器件的制备方法，其中，当所形成的所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度时，所述形成的第一介质层的步骤包括：
    沿背离所述介质基板的方向依次形成第一子介质层和第二子介质层；所述第二子介质层包括第一填充结构和第二填充结构；所述第一填充结构和所述第二填充结构分别位于所述第一间隙和所述第二间隙。
  15. 根据权利要求13所述的MEMS器件的制备方法，其中，当所述制 备方法包括在所述膜桥的桥面靠近所述介质基板的一侧设置有所述第二介质层时，在形成所述第二介质层之前还包括：
    在所述第一介质层背离介质基板的表面形成牺牲层；其中，所述牺牲层背离介质基板的一侧具有第二凹陷部；
    所述第二介质层形成在所述牺牲层背离介质基板的一侧，所形成的所述第二介质层具有朝向所述介质基板一侧凸出的第一凸出部；所述第一凸出部与所述第二凹陷部一一对应设置；
    在形成所述膜桥之后还包括去除所述牺牲层的步骤。
  16. 根据权利要求13所述的MEMS器件的制备方法，其中，当所形成的所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度，以及在述制备方法包括在所述膜桥的桥面靠近所述介质基板的一侧设置有所述第二介质层时，
    形成所述第一介质层的步骤包括：
    沿背离所述介质基板的方向依次形成第一子介质层和第二子介质层；所述第二子介质层包括第一填充结构和第二填充结构；所述第一填充结构和所述第二填充结构分别位于所述第一间隙和所述第二间隙；
    形成所述第二子介质层的步骤包括：
    在所述第一间隙和第二间隙形成填充材料，退火形成所述第一填充结构和所述第二填充结构；所述第一填充结构和所述第二填充结构均具有与所述第一子介质层接触的第一面，与所述介质基板相对设置的第二面，以及连接所述第一表面和所述第二面的第一连接面；所述第一连接面和所述第一子介质层限定出所述第一凹陷部；
    在形成所述第二子介质层之后还包括：
    在所述第一介质层背离介质基板的表面形成牺牲层；其中，所述牺牲层背离介质基板的一侧具有第二凹陷部；所述第二凹陷部与所述第一凹陷部一一对应设置的；
    所述第二介质层形成在所述牺牲层背离介质基板的一侧，所形成的所述第二介质层具有朝向所述介质基板一侧凸出的第一凸出部；所述第一凸出部与所述第二凹陷部一一对应设置；
    在形成所述膜桥之后还包括去除所述牺牲层的步骤。
  17. 根据权利要求16所述的MEMS器件的制备方法，其中，所形成的所述膜桥的桥面具有朝向所述第一介质层凸出的第二凸出部，且所述第二凸出部与所述第一凸出部一一对应设置的，且所述第二凸出部嵌在与之对应的第一凸出部内。
  18. 根据权利要求13所述的MEMS器件的制备方法，其中，当所形成的所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度时，形成所述第一介质层的步骤包括：
    沿背离所述介质基板的方向依次形成第二子介质层和第一子介质层；所述第二子介质层包括第一填充结构和第二填充结构；所述第一填充结构和所述第二填充结构分别位于所述第一间隙和所述第二间隙；
    形成所述第二子介质层的步骤包括：
    形成第二子介质材料层，且所述第二介质材料层突出于所述第一间隙和所述第二间隙；
    对所述第二子介质材料层进行加热，以使第二子介质材料层重塑回填所述第一间隙和所述第二间隙，形成所述第一填充结构和所述第二填充结构。
  19. 根据权利要求13所述的MEMS器件的制备方法，其中，当所形成的所述第一介质层位于所述第一间隙和所述第二间隙的部分的厚度大于所述驱动电极的厚度时，形成所述第一介质层的步骤包括：
    沿背离所述介质基板的方向依次形成第二子介质层和第一子介质层；所述第二子介质层包括第一填充结构和第二填充结构；所述第一填充结构和所述第二填充结构分别位于所述第一间隙和所述第二间隙；
    形成所述第二子介质层的步骤包括：
    形成第二子介质材料层，且所述第二介质材料层突出于所述第一间隙和所述第二间隙；
    采用化学机械抛光磨平工艺，去除突出于所述第一间隙和所述第二间隙的所述第二子介质材料层部分，形成分别填充所述第一间隙和所述第二间隙的所述第一填充结构和所述第二填充结构。
  20. 一种电子设备，其包括权利要求1-12中任一项所述的MEMS器件。
PCT/CN2022/127808 2022-10-27 2022-10-27 Mems器件及其制备方法、电子设备 WO2024087079A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/127808 WO2024087079A1 (zh) 2022-10-27 2022-10-27 Mems器件及其制备方法、电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/127808 WO2024087079A1 (zh) 2022-10-27 2022-10-27 Mems器件及其制备方法、电子设备

Publications (1)

Publication Number Publication Date
WO2024087079A1 true WO2024087079A1 (zh) 2024-05-02

Family

ID=90829677

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/127808 WO2024087079A1 (zh) 2022-10-27 2022-10-27 Mems器件及其制备方法、电子设备

Country Status (1)

Country Link
WO (1) WO2024087079A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2658933Y (zh) * 2003-11-07 2004-11-24 中国电子科技集团公司第五十五研究所 一种驱动电压通路与射频信号隔离的微机电系统开关
CN2729890Y (zh) * 2004-09-27 2005-09-28 东南大学 射频微电子机械单刀双掷膜开关
CN114551166A (zh) * 2022-02-22 2022-05-27 北京京东方光电科技有限公司 微机电系统开关及其制备方法
CN114824698A (zh) * 2021-01-19 2022-07-29 京东方科技集团股份有限公司 一种移相器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2658933Y (zh) * 2003-11-07 2004-11-24 中国电子科技集团公司第五十五研究所 一种驱动电压通路与射频信号隔离的微机电系统开关
CN2729890Y (zh) * 2004-09-27 2005-09-28 东南大学 射频微电子机械单刀双掷膜开关
CN114824698A (zh) * 2021-01-19 2022-07-29 京东方科技集团股份有限公司 一种移相器
CN114551166A (zh) * 2022-02-22 2022-05-27 北京京东方光电科技有限公司 微机电系统开关及其制备方法

Similar Documents

Publication Publication Date Title
US8564176B2 (en) Piezoelectric MEMS switch and method of manufacturing piezoelectric MEMS switch
EP2377154B1 (en) Via structure and method thereof
CN1950291B (zh) 在微机电装置的制造中减轻蚀刻电荷的破坏
JP4613165B2 (ja) 微小電気機械システムのスイッチ
US7209019B2 (en) Switch
KR20080004467A (ko) 가요성이고 자유로운 스위치 멤브레인의 무선 주파수 미세전자기계 시스템 스위치
EP2200063B1 (en) Micro-electromechanical system switch
JP4739173B2 (ja) マイクロスイッチング素子
US8207460B2 (en) Electrostatically actuated non-latching and latching RF-MEMS switch
WO2024087079A1 (zh) Mems器件及其制备方法、电子设备
US20120019886A1 (en) Via structure and method thereof
WO2023225978A1 (zh) Mems器件及其制备方法、电子设备
US20090146773A1 (en) Lateral snap acting mems micro switch
JP2005504415A (ja) マイクロメカニカル・スイッチ及び同スイッチを製造する方法
JP2003323840A (ja) リレー