WO2024083347A1

WO2024083347A1 - An automated dynamic high temperature operating life test acquisition system

Info

Publication number: WO2024083347A1
Application number: PCT/EP2022/079481
Authority: WO
Inventors: Gilberto Curatola; Marco Silvestri; Muhammad Tayyab
Original assignee: Huawei Digital Power Technologies Co., Ltd.
Priority date: 2022-10-21
Filing date: 2022-10-21
Publication date: 2024-04-25

Abstract

The present disclosure relates to dynamic high temperature operating lifetime (DHTOL) testing of a transistor device under test, DUT (210), for example, a GaN power device. The disclosure presents a test system (200) for performing the DHTOL test on the transistor DUT (210). The test system (200) uses a DHTOL switching cell (220) and a lock-in circuit (240), which are both controlled by a controller (230). The controller (230) is configured to measure an on-state source¬ drain voltage and an on-state source-drain current of the transistor DUT (210) during its operation according to a switching signal applied by the switching cell (220). The controller (230) is also configured to control thresholds of comparators of two comparator pairs (241,242) of the lock-in-circuit (240), in order to track changes of the on-state source-drain voltage and the on-state source-drain current of the transistor DUT (210) over one or more repetitions of the switching signal.

Description

AN AUTOMATED DYNAMIC HIGH TEMPERATURE OPERATING LIFE TEST ACQUISITION SYSTEM

TECHNICAL FIELD

The present disclosure relates to dynamic high temperature operating lifetime (DHTOL) testing of a device under test (DUT), for example, transistor device like a GaN power device. The disclosure presents a test system for performing the DHTOL test on the DUT. The test system uses a DHTOL switching cell and a lock-in circuit, both controlled by a controller.

BACKGROUND

The DHTOL test is a mandatory test for gallium nitride (GaN) devices as per JEP 180 Joint Electron Device Engineering Council (JEDEC) standards. The test guidelines provided in these standards are specific for test circuit or vehicle, but are open in terms of optimizing the test system. A standardized core switching cell or circuit needs to be consistently used for the evaluation of DUTs according to the standards, because the evaluated stress parameters or signals should represent specific application similar stress levels for different DUTs. Further, the test evaluation parameters or signals need to be tracked throughout the test runtime, in order to track reliability and degradation factors for the DUT.

In addition to conducting and publishing the DHTOL reliability results, at least for GaN devices there is an additional need for proving application level reliability test results after long term switching. Such long term testing is complicated compared to any other characterization test performed before, since it summarizes the DUT lifetime under hard- switching and soft- switching application stress for over 1000 hours, which concludes the switching power loss defects and effects.

DHTOL tests and related test systems and components are relatively new in the industry.

SUMMARY

In view of the above, an objective of this disclosure is to provide a test system for performing a DHTOL test of a transistor DUT, wherein the test system is of low complexity and is cost effective. Another objective is enable obtaining the point value of the dynamic on-state resistance of the transistor DUT during the test. As dynamic on-state resistance is a key parameter to represent device aging and failure under repetitive hard-switching application conditions. An automated extraction of relevant signals of the DUT is another objective.

In particular, it is another objective to provide a smart and auto-calibration data acquisition hardware as the test system. Complicated post-processing after tedious data-acqui sition should be efficiently simplified. Another objective is to avoid using many high bandwidth oscilloscopes and high bandwidth probes when conducting the DHOL test especially for GaN devices, which are conventionally needed for long term waveform acquisition, however, make such tests costly and industrially unrealistic. Moreover, a smart signal conditioning at a temperature steady state is needed.

These and other objectives are achieved by the solutions of this disclosure as described in the independent claims. Advantageous implementations are further defined in the dependent claims.

A first aspect of this disclosure provides a test system for performing a DHTOL test on a transistor DUT, the test system comprising: a controller; a DHTOL switching cell connectable to the transistor DUT and configured to operate the transistor DUT; wherein the controller is configured to control the switching cell to operate the transistor DUT according to a switching signal applied to a gate driver circuit of the transistor DUT; a lock-in circuit connected with an input of the lock-in circuit to the switching cell, the lock-in circuit comprising a first pair of comparators, wherein an input of the first pair of comparators is connected to a voltage tab from a voltage clamp of the switching cell for an on-state source-drain voltage of the transistor DUT, and a second pair of comparators, wherein an input of the second pair of comparators is connected to a current-dependent voltage signal tab of the switching cell for an on-state sourcedrain current of the transistor DUT, and wherein an output of the first and second pair of comparators is connected to digital inputs of the controller; wherein the controller is configured to measure the on-state source-drain voltage and on-state source-drain current of the transistor DUT during operating the transistor DUT according to the switching signal, and to control the thresholds of the comparators with analog outputs to track changes of the on-state source-drain voltage and the on-state source-drain current of the transistor DUT over one or more repetitions of the switching signal. The test system of the first aspect enables conducting the DHTOL test of the transistor DUT with a low-complex system and in a cost effective way. The test system of the first aspect can operate in an automated way, track the on-state source-drain voltage and the on-state sourcedrain current, and may calculate the dynamic on-state resistance of the transistor DUT during the test based on these tracked device signals. No complicated post-processing of these obtained signals and parameters is needed. The test system of the first aspect does also not require high bandwidth oscilloscopes and high bandwidth probes.

In an implementation form of the first aspect, the switching signal comprises on-periods and off-periods, and the controller is configured to measure the on-state source-drain voltage and the on-state source drain current during each on-period.

Each on-period and off-period may correspond to one repetition of the switching signal, and multiple on- and off-periods may be the one or more repetitions of the switching signal, over which the DHTOL test is performed.

In an implementation form of the first aspect, the controller is configured to control the thresholds of the comparators in real-time as a movable window.

This enables a reliable and automated DHTOL test of the transistor DUT.

In an implementation form of the first aspect, the controller is configured to use an analog lock- in method to track the changes of the on-state source-drain voltage and source-drain current of the transistor DUT.

Thus, these signals can be reliably extracted, even when they change during the DHTOL test.

In an implementation form of the first aspect, the controller is configured to start the analog lock-in method after a predetermined delay after the beginning of each on-period.

The predetermined delay may be in the order of 1 ps, for instance, in a range of 0.5-2 ps.

In an implementation form of the first aspect, the controller configured to use the analog lock- in method is further configured to calculate the on-state resistance of the transistor DUT based on the on-state source-drain voltage and the on-state source-drain current and to output the on- state resistance to a data logger.

As mentioned above, the on-state resistance is an important parameter for evaluating device reliability and failure at a thermal steady state, where device degradation and aging under switching stress condition is represented by an increase in its on-state resistance value, and can be automatically and dynamically obtained by the test system.

In an implementation form of the first aspect, the controller is further configured to calculate the on-resistance of the transistor DUT for each on-period of the switching signal, and to normalize the calculated resistance based on the resistance calculated in a one or more preceding on-periods of the switching signal.

Thus, a tracking of the dynamic resistance is enabled.

In an implementation form of the first aspect, each comparator of the first comparator pair comprises an inverting input and a non-inverting input; the inverting input of the first comparator of the first pair of comparators and the non-inverting input of the second comparator of the first pair of comparators are connected respectively and connected to the voltage tab from the voltage clamp of the switching cell; and the non-inverting input of the first comparator of the first pair of comparators and the inverting input of the second comparator of the first pair of comparators define first upper and lower thresholds respectively and are connected to two separate analog outputs of the controller.

In an implementation form of the first aspect, each comparator of the second pair of comparators comprises an inverting input and a non-inverting input; the inverting input of the first comparator of the second pair of comparators and the non-inverting input of the second comparator of the second pair of comparators are connected respectively and connected to the a current-dependent voltage signal tab of the switching cell; and the non-inverting input of the first comparator of the second pair of comparators and the inverting input of the second comparator of the second pair of comparators define second upper and lower thresholds respectively and are connected to two separate analog outputs of the controller. In an implementation form of the first aspect, the non-inverting input of the first comparator of the first pair of comparators, the inverting input of the second comparator of the first pair of comparators, the non-inverting input of the first comparator of the second pair of comparators, and the inverting input of the second comparator of the second pair of comparators are connected to the controller via respective threshold tuning resistors of said comparators.

A second aspect of this disclosure provides a method for performing a DHTOL test on a transistor DUT, the method comprising: controlling a DHTOL switching cell connected to the transistor DUT to operate the transistor DUT; wherein the switching cell is controlled to operate the transistor DUT according to a switching signal applied to a gate driver circuit of the transistor DUT; controlling a lock-in circuit connected with an input of the lock-in circuit to the switching cell, the lock-in circuit comprising a first pair of comparators wherein an input of the first pair of comparators is connected to a voltage tab from a voltage clamp of the switching cell for an on-state source-drain voltage of the transistor DUT, and a second pair of comparators wherein an input of the second pair of comparators is connected to a current-dependent voltage signal tab of the switching cell for an on-state source-drain current of the transistor DUT; wherein the controlling comprises measuring the on-state source-drain voltage and the on-state source-drain current of the transistor DUT during operating the transistor DUT according to the switching signal, and controlling the thresholds of the comparators to track changes of the on- state source-drain voltage and the on-state source-drain current of the transistor DUT over one or more repetitions of the switching signal.

The method of the second aspect provides the same advantages as described above for the test system of the first aspect. In implementation forms of the method, the method may perform the DHTOL test with the implementation forms of the test system of the first aspect, i.e., controlling the switching cell and the lock-in circuit as described in the implementation forms of the test system of the first aspect.

A third aspect of this disclosure provides a controller firmware program comprising instructions which, when the program is executed by a controller, cause the controller to perform the method according to the second aspect, and send one or more values to a data-logging computer over a communication port. A fourth aspect of this disclosure provides a non-transitory storage medium storing executable program code which, when executed by a processor, causes the method according to the second aspect to be performed.

In summary of the above aspects, this disclosure proposes the test system including the lock-in circuit, which is a newly designed circuit for DUT degradation factor acquisition. The test system and corresponding method are industrially relevant and show large benefits over the state-of-the art DHTOL tests. In particular, the proposed test system and method allow at least the following benefits:

■ The test system is for automated DHTOL testing.

■ The test system and method are not only usable for GaN devices, but can be applicable also for other transistor DUTs or to any switching device for performing automated degradation factor tracking while switching the DUT.

■ The test system includes an analog lock-in interfaced with the controller, e.g., a digital processor (e.g. microcontroller or microprocessor), in order to track the on-state sourcedrain voltage and the on-state source-drain current, and to carry out signal conditional and averaging in hardware. Normalization, signal parsing, and averaging can be done in the hardware as well.

■ An on-state resistance of the transistor DUT can be extracted at any desirable intervals in the processing hardware of the test system, and may be transmitted as encoded digital signal with, for example, a USB interface, so that EMI noise interactions do not have an effect on the measurements.

It has to be noted that all devices, elements, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. BRIEF DESCRIPTION OF DRAWINGS

The above described aspects and implementation forms will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which

FIG. 1 compares schematically a conventional DHTOL test (a), and a DHTOL test performed by a test system of this disclosure (b).

FIG. 2 shows a test system for performing a DHTOL test according to this disclosure.

FIG. 3 shows switching cell and lock-in circuit examples of a test system for performing a DHTOL test according to this disclosure.

FIG. 4 shows an exemplary schematic of operation of the test system.

FIG. 5 shows a flow diagram of operation of a single repetition of the DHTOL test performed by the test system of this disclosure.

FIG. 6 shows a processor or digital control state flow diagram for a single repetition of the DHTOL test performed by the test system of this disclosure.

FIG. 7 shows a parallel lot operation for multiple DHTOL tests and qualifications of multiple transistor DUTs.

FIG. 8 shows a WiFi shield based wireless transmission of values to a data logger machine, for reducing further USB cable complexities

FIG. 9 shows an exemplary complete system schematic of a test system according to this disclosure.

FIG. 10 shows a method for performing a DHTOL test according to this disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1 compares schematically a conventional DHTOL test in FIG. 1(a), and a DHTOL test performed by a test system of this disclosure in FIG 1(b).

In the JEDEC complaint test methodology, the dynamic on-state resistance of a transistor DUT, along with a junction temperature (TJ) dependent sensor temperature (TS), is extracted and tracked along the testing time. In order to carry out this test methodology for one core switching cell (also referred to as a switching test board), a supporting clamping circuitry, a current sensor, and high bandwidth probes and oscilloscope are needed. The data extracted in every switching instant of the DUT needs to be post-processed, in order to extract the meaningful information (device parameters) from it. Further, parsing and averaging functions are also applied to the waveforms of data, which can be very time consuming and can take up gigabytes of hard disk space, if many waveforms are saved.

In this disclosure, a test specific automated tracking and extraction data acquisition hardware (the test system 200, e.g., as shown in FIG. 2) is proposed instead. As shown schematically in FIG. 1(b), a switching cell (or switching board) and a new circuit (referred to as a lock-in circuit) may be used by the test system 200 of this disclosure. The test system 200 may also employ a current sensor and voltage clamping circuit, in order to access the on-state source-drain voltage and the on-state source-drain current of the transistor DUT. The test system 200 may further perform a firmware or software based data state machine algorithm, for example by a controller, to control the circuits. As shown, the test system 200 may provide directly already processed and meaningful degradation evaluation signals of the transistor DUT, so that no post-processing is needed.

FIG. 2 shows an example of the test system 200 according to this disclosure. The test system 200 is configured to perform a DHTOL test on a transistor DUT 210. The transistor DUT 210 may be a GaN device.

The test system 200 comprises a controller 230, for instance, a microcontroller or a microprocessor. Further, the test system 200 comprises a DHTOL switching cell 220, which is connectable to the transistor DUT 210, and is configured to operate the transistor DUT 210. The switching cell 220 may be a conventional switching cell, or a switching circuit, or a switching board, as it is used for performing conventional DHTOL tests (e.g. as shown in FIG. 1(a)). The controller 230 is configured to control the switching cell 220 to operate the transistor DUT 210 according to a switching signal 400 (see, e g., FIG. 4), which is applied to a gate driver circuit of the transistor DUT 210. That is, the switching signal 400 may operate a gate of the transistor DUT 210, and may be referred to as gate signal as well.

The test system 200 further comprises a lock-in circuit 240. An input of the lock-in circuit 240 is connected to the switching cell 220. The lock-in circuit 240 comprises a first pair of comparators 241 and a second pair of comparators 242 An input of the first pair of comparators 241 is connected to a voltage tab 221, from a voltage clamp of the switching cell 220, which is for (obtaining) the on-state source-drain voltage of the transistor DUT 210. An input of the second pair of comparators 242 is connected to a current-dependent voltage signal tab 222 of the switching cell 220, which is for (obtaining) the on-state source-drain current of the transistor DUT 210. An output of the first pair of comparators 241 and an output of the second pair of comparators 242 is, respectively, connected to a digital input of the controller 230.

The controller 230 is configured to measure the on-state source-drain voltage and the on-state source-drain current of the transistor DUT 210 during operating the transistor DUT 210 based on the switching signal 400.

The controller 230 is also configured to control the thresholds of the comparators of the comparator pairs 241 and 242 with analog outputs, in order to track changes of the on-state source-drain voltage and the on-state source-drain current of the transistor DUT 210 over one or more repetitions of the switching signal 400. Optionally, the controller 210 is configured to use an analog lock-in method, in order to track the changes of the on-state source-drain voltage and source-drain current of the transistor DUT 210. Optionally, the controller 230 is configured to control the thresholds of the comparators of the comparator pairs 241 and 242, respectively, in real-time as a movable window.

The controller 230 may, in addition to measuring the signals mentioned above, be configured to calculate the on-state resistance of the transistor DUT 210 based on the source-drain voltage and the source-drain current. The controller 230 may output the calculated on-state resistance. The controller 230 may track the on-state resistance over the one or more repetitions of the switching signal 400.

The controller 230 may comprise or be a processor or processing circuitry (not shown) configured to perform, conduct or initiate the various operations of the controller 230 described herein. The processing circuitry may comprise hardware and/or the processing circuitry may be controlled by software. The hardware may comprise analog circuitry or digital circuitry, or both analog and digital circuitry. The digital circuitry may comprise components such as applicationspecific integrated circuits (ASICs), field-programmable arrays (FPGAs), digital signal processors (DSPs), or multi-purpose processors. The controller 230 may further comprise memory circuitry, which stores one or more instruction(s) that can be executed by the processor or by the processing circuitry, in particular under control of the software. For instance, the memory circuitry may comprise a non-transitory storage medium storing executable software code which, when executed by the processor or the processing circuitry, causes the various operations of the controller 230 to be performed. In one embodiment, the processing circuitry comprises one or more processors and a non-transitory memory connected to the one or more processors. The non-transitory memory may carry executable program code which, when executed by the one or more processors, causes the controller 230 to perform, conduct or initiate the operations or methods described herein.

FIG. 3 shows an exemplary test system 200 according to this disclosure, which builds on the test system 200 shown in FIG. 2. Same elements are labelled with the same reference signs and may function likewise. In particular, FIG. 3 shows a schematic for the proposed circuits (switching cell 220 and lock-in circuit 240) of the tests system 200, and their components.

The DHTOL, as mentioned before, is an application level test, so that the transistor DUT 210 is operated under specified stress levels. This means a continuous operation at the gate driver circuit of a gate of the transistor DUT 210. The gate signal (switching signal 400) may be generated by the controller 230, e.g., a microcontroller. The same controller 230 may be used to perform the analog lock-in method. With the DHTOL test of this disclosure, the DUT’s degradation can be tracked or evaluated, for example, according to an increase of its on-state resistance (RDSON), which may be extracted as described above from the voltage drop during on-state (i.e., the on-state source-drain voltage (VDSON)), and the device current during on-state (i.e., the on-state source-drain current (IDSON). A current sensor may be used in the switching cell 220, and a voltage drop V(I)DSON over the sensor may be equated to as the total on-state current. In an example, the sensor comprises a current shunt, and the voltage drop V(I)DSON is over the current shunt. The two voltage drops, VDSON and V(I)DSON, may be in the millivolts range, so that they are easily measureable using the comparator pairs 241, 242 with high vertical resolution. The two voltages may become the input(s) for the lock-in circuit 240 as shown.

It can be seen in FIG. 3, that each comparator 241a and 241b of the first comparator pair 241 comprises an inverting input (-) and a non-inverting input (+). The inverting input of the first comparator 241a and the non-inverting input of the second comparator 241b are connected respectively and connected to the voltage tab 221 from the voltage clamp of the switching cell 220. Further, the non-inverting input of the first comparator 241a and the inverting input of the second comparator 241b define first upper and lower thresholds, respectively, and are connected to two separate analog outputs of the controller 230. These thresholds may be controlled by the controller 230 during the DHTOL test. It can also be seen in FIG. 3 that each comparator 242a and 242b of the second pair of comparators 242 comprises an inverting input (-) and a non-inverting input (+). The inverting input of the first comparator 242a and the non-inverting input of the second comparator 242b are connected respectively and connected to the current-dependent voltage signal tab 222 of the switching cell 220. Further, the non-inverting input of the first comparator 242a and the inverting input of the second comparator 242b define second upper and lower thresholds, respectively, and are connected to two separate analog outputs of the controller 230. These thresholds may be controlled by the controller 230 during the DHTOL test.

It can further be seen in FIG. 3 that the non-inverting input of the first comparator 241a, the inverting input of the second comparator 241b, the non-inverting input of the first comparator 242a, and the inverting input of the second comparator 242b are connected to the controller 230via respective threshold tuning resistors Rl, R2, R3, R4 of said comparators. By means of these connections, the controller 230 can control the thresholds of the comparators 241a, 241b, 242a, and 242b. For instance, change the thresholds (increase or decrease).

FIG. 3 shows further that the controller 230 is connected to a data logger 300. The controller 230 may output data to the data logger, e.g., the on-state source-drain voltage and/or the on state source-drain current. The controller 230 may also output the calculated on-state resistance to the data logger 300.

A schematic of an automated operation of the test system 200 with waveforms for the gate voltage (Vgs), which is the switching signal 400, the on-state source-drain voltage and the on- state source-drain current, can be seen from FIG. 4. The switching signal 400 comprises on- periods 401 and off-periods 402. The controller 230 may be configured to measure the on-state source-drain voltage and the on-state source drain current during each on-period 401. Accordingly, it may also calculated the on-state resistance for each on-period.

The controller 230 may be configured to use an analog lock-in method to track the changes of the on-state source-drain voltage and source-drain current of the transistor DUT 210 The proposed analog lock-in method, which may be performed by the controller 230, can control the thresholds of the comparators 241a, 241b, 242a and 242b in real-time, e.g., operating as a movable window. A first conditional applies on the gate signal applied to the DUT 210, to enter the on-state of the DUT 210. Then the VDSON and V(I)DSON signals may be located by the analog lock-in method, for instance, after a predetermined delay after the beginning of each on-period 401 of the switching signal 400, like after a delay of 1 ps.

FIG. 5 shows a flow diagram of operation of a single repetition of the DHTOL test (for one on- period 401, i.e., one repetition of the switching signal 400). The controller 230 may obtain the values of Vgs, VDSON, and IDSON. After the predetermined delay, e.g. the 1 ps delay, after switching on the transistor DUT 210 with the switching signal 400, the controller 230 may locate the waveforms by analog lock-in, and may calculate and extract the values of VDSON and IDSON. Then, the controller 230 may calculate RDSON. The calculated RDSON may be saved for a next repetition, and may be transmitted by the controller 230 via a COM port to a data logger 300. The RDSON of any repetition of the DHTOL test may also be normalized by one or more RDSON of previous repetitions.

If a degradation of the transistor DUT 210 leads to a change of the on-state source-drain voltage, an auto locating algorithm performed by the controller 230 may track the signal changes. According to the DHTOL degradation rule of industrial convention, a total of 20% increase in the on-state resistance is considered as a DUT failure. This parameter may thus be tracked by the controller 230, in order to extract the high resolution degradation factor without using oscilloscope and probes.

The controller 230 may be configured to work with a feedback loop from the comparators 241a, 241b, 242a, and 242b, in order to constantly track the device signals (on-state source-drain voltage and on-state source-drain current) and change the thresholds. The value of the locked thresholds, and the changes of the signals, may be calibrated as the tracked degradation factor of the DUT 210. The calculated and parsed signal values may be transmitted over a COM port or by USB in the form of digital encoded signal values. The signal locating with the comparator pairs 241, 242, and the digital control for a single repetition is broken down in FIG. 6.

In particular, FIG. 6 shows that after the start of the repetition, the controller 230 reads the gate voltage Vgs, and can set a frequency of the measurement extraction based thereon, i.e., a frequency of extracting VDSON and IDSON. The controller 230 may read these values after the predetermined delay of the positive edge of the gate signal. Then, the controller 230 may set the comparator thresholds, and perform an auto adjustment, as shown. This way of operation of the DHOL test by the controller 230, in collaboration with proposed circuits 220 and 240 of the test system 200, may eliminate the manual extraction of meaningful data by first scanning the whole waveforms and then post processing it. It also eliminates the use of probes and oscilloscope, which would otherwise be a problem in the parallelization of the test for many devices simultaneously.

In FIG. 7, an embodiment of this disclosure is shown. The test system 200 may have multiple switching cells 220 and multiple lock-in circuits 240 respectively connected to the switching cells 240, in order to test multiple transistor DUTs 210 in parallel. Thus, this disclosure allows an easy and cost effective parallel operation of the DHTOL test, without having to invest in the measurement setup and instrumentation (high bandwidth probe and oscilloscopes). To run a single switching cell conventionally, at least four channels on an oscilloscope may be needed. Therefore, parallel testing with oscilloscopes becomes very costly. The test system 200 of this disclosure, and its specific acquisition control by the controller 230, eliminates the need of such measurement instrumentation all together.

Additionally, the acquisition can also be made wirelessly by the test system 200, which further simplifies the hardware intervention, as shown in FIG. 8. The wireless acquisition can be achieved by configuring a WiFi shield with the acquisition (micro)-controller 230 connected to a Local Area Network (LAN) of the data logger 300.

FIG. 9 combines the schematic representation of a test vehicle printed circuit board with eight standardized parallelized switching cells 220 accompanied by respective lock-in circuits 240, and other components of the test system 200 according to this disclosure. The test system 200 is connected wirelessly to a data-logging computer 300.

FIG. 10 shows a method 1000 for performing a DHTOL test on a transistor DUT 210, according to this disclosure. The method 1000 may be performed by the test system 200.

The method 1000 comprises a step 1001 of controlling a DHTOL switching cell 220 connected to the transistor DUT 210 to operate the transistor DUT 210. The switching cell 220 is controlled to operate the transistor DUT 210 according to a switching signal 400 applied to a gate driver circuit of the transistor DUT 210. The method 1000 further comprises a step 1002 of controlling 1002 a lock-in circuit 240 connected with an input of the lock-in circuit 240 to the switching cell 220. The lock-in circuit 240 comprises a first pair of comparators 241. An input of the first pair of comparators 241 is connected to a voltage tab 221 from a voltage clamp of the switching cell 220 for an on-state source-drain voltage of the transistor DUT 210. The lock-in circuit 240 also comprises a second pair of comparators 242. An input of the second pair of comparators 242 is connected to a current-dependent voltage signal tab 222 of the switching cell 220 for an on-state source-drain current of the transistor DUT.

The step 1002 of controlling comprises measuring the on-state source-drain voltage and the on- state source-drain current of the transistor DUT 210 during operating the transistor DUT 210 according to the switching signal 400, and comprises controlling the thresholds of the comparators 241a, 241b, 242a, and 242b, to track changes of the on-state source-drain voltage and the on-state source-drain current of the transistor DUT 210 over one or more repetitions of the switching signal 400.

The present disclosure has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed matter, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

1. A test system (200) for performing a dynamic high temperature operating lifetime, DHTOL, test on a transistor device under test (210), transistor DUT, the test system (200) comprising: a controller (230); a DHTOL switching cell (220) connectable to the transistor DUT (210) and configured to operate the transistor DUT (210); wherein the controller (230) is configured to control the switching cell (220) to operate the transistor DUT (210) according to a switching signal (400) applied to a gate driver circuit of the transistor DUT (210); a lock-in circuit (240) connected with an input of the lock-in circuit (240) to the switching cell (220), the lock-in circuit (240) comprising a first pair of comparators (241), wherein an input of the first pair of comparators (241) is connected to a voltage tab (221) from a voltage clamp of the switching cell (220) for an on-state source-drain voltage of the transistor DUT (210), and a second pair of comparators (242), wherein an input of the second pair of comparators (242) is connected to a current-dependent voltage signal tab (222) of the switching cell (220) for an on-state source-drain current of the transistor DUT (210), and wherein an output of the first and second pair of comparators (241, 242) is connected to digital inputs of the controller (230); wherein the controller (230) is configured to measure the on-state source-drain voltage and on-state source-drain current of the transistor DUT (210) during operating the transistor DUT (210) according to the switching signal (400), and to control the thresholds of the comparators (241, 242) with analog outputs to track changes of the on-state source-drain voltage and the on-state source-drain current of the transistor DUT (210) over one or more repetitions of the switching signal (400).

2. The test system (200) according to claim 1, wherein: the switching signal (400) comprises on-periods (401) and off-periods (402), and the controller (230) is configured to measure the on-state source-drain voltage and the on-state source drain current during each on-period (401).

3. The tests system (200) according to claim 1 or 2, wherein the controller (230) is configured to control the thresholds of the comparators (241, 242) in real-time as a movable window.

4. The test system (200) according to one of the claims 1 to 3, wherein the controller (230) is configured to use an analog lock-in method to track the changes of the on-state source-drain voltage and source-drain current of the transistor DUT (210).

5. The test system (200) according to claim 4, wherein the controller (230) is configured to start the analog lock-in method after a predetermined delay after the beginning of each on- period (401).

6. The test system (200) according to claim 4 or 5, wherein the controller (230) configured to use the analog lock-in method is further configured to calculate the on-state resistance of the transistor DUT (210) based on the on-state source-drain voltage and the on-state source-drain current and to output the on-state resistance to a data logger (300).

7. The test system (200) according to claim 6, wherein the controller (230) is further configured to calculate the on-resistance of the transistor DUT (210) for each on-period (401) of the switching signal (400), and to normalize the calculated resistance based on the resistance calculated in one or more preceding on-periods (401) of the switching signal (400).

8. The tests system (200) according to one of the claims 1 to 7, wherein: each comparator (241a, 241b) of the first comparator pair (241) comprises an inverting input and a non-inverting input; the inverting input of the first comparator (241a) of the first pair of comparators (241) and the non-inverting input of the second comparator (241b) of the first pair of comparators (241) are connected respectively and connected to the voltage tab (221) from the voltage clamp of the switching cell (220); and the non-inverting input of the first comparator (241a) of the first pair of comparators (241) and the inverting input of the second comparator (241b) of the first pair of comparators (241) define first upper and lower thresholds respectively and are connected to two separate analog outputs of the controller (230).

9. The tests system (200) according to one of the claims 1 to 8, wherein: each comparator (242a, 242b) of the second pair of comparators (242) comprises an inverting input and a non-inverting input; the inverting input of the first comparator (242a) of the second pair of comparators (242) and the non-inverting input of the second comparator (242b) of the second pair of comparators (242) are connected respectively and connected to the current-dependent voltage signal tab (222) of the switching cell (220); and the non-inverting input of the first comparator (242a) of the second pair of comparators (242) and the inverting input of the second comparator (242b) of the second pair of comparators (242) define second upper and lower thresholds respectively and are connected to two separate analog outputs of the controller (230).

10. The test system (200) according to claim 8 or 9, wherein the non-inverting input of the first comparator (241a) of the first pair of comparators (241), the inverting input of the second comparator (241b) of the first pair of comparators (241), the non-inverting input of the first comparator (242a) of the second pair of comparators (242), and the inverting input of the second comparator (242b) of the second pair of comparators (242) are connected to the controller (230) via respective threshold tuning resistors (Rl, R2, R3, R4) of said comparators (241a, 241b, 242a, 242b).

11. A method (1000) for performing a dynamic high temperature operating lifetime, DHTOL, test on a transistor device under test (210), DUT, the method (1000) comprising: controlling (1001) a DHTOL switching cell (220) connected to the transistor DUT (210) to operate the transistor DUT (210); wherein the switching cell (220) is controlled to operate the transistor DUT (210) according to a switching signal (400) applied to a gate driver circuit of the transistor DUT (210); controlling (1002) a lock-in circuit (240) connected with an input of the lock-in circuit

(240) to the switching cell (220), the lock-in circuit (240) comprising a first pair of comparators

(241) wherein an input of the first pair of comparators (241) is connected to a voltage tab (221) from a voltage clamp of the switching cell (220) for an on-state source-drain voltage of the transistor DUT (210), and a second pair of comparators (242) wherein an input of the second pair of comparators (242) is connected to a current-dependent voltage signal tab (222) of the switching cell for an on-state source-drain current of the transistor DUT; wherein the controlling (1002) comprises measuring the on-state source-drain voltage and the on-state source-drain current of the transistor DUT (210) during operating the transistor DUT (210) according to the switching signal (400), and controlling the thresholds of the comparators (241, 242) to track changes of the on-state source-drain voltage and the on-state source-drain current of the transistor DUT (210) over one or more repetitions of the switching signal (400).

12. A controller firmware program comprising instructions which, when the program is executed by a controller (230), cause the controller (230) to perform the method (1000) according to claim 11 and send one or more values to a data-logging computer (300) over a communication port.