WO2024083266A1 - 半导体器件及电子设备 - Google Patents

半导体器件及电子设备 Download PDF

Info

Publication number
WO2024083266A1
WO2024083266A1 PCT/CN2023/136908 CN2023136908W WO2024083266A1 WO 2024083266 A1 WO2024083266 A1 WO 2024083266A1 CN 2023136908 W CN2023136908 W CN 2023136908W WO 2024083266 A1 WO2024083266 A1 WO 2024083266A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor device
temperature compensation
thin film
compensation layer
Prior art date
Application number
PCT/CN2023/136908
Other languages
English (en)
French (fr)
Inventor
庞慰
杨清瑞
Original Assignee
广州乐仪投资有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 广州乐仪投资有限公司 filed Critical 广州乐仪投资有限公司
Publication of WO2024083266A1 publication Critical patent/WO2024083266A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02244—Details of microelectro-mechanical resonators
    • H03H9/02433—Means for compensation or elimination of undesired effects
    • H03H9/02448—Means for compensation or elimination of undesired effects of temperature influence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02244—Details of microelectro-mechanical resonators
    • H03H2009/02283—Vibrating means

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and an electronic device.
  • Piezoelectric MEMS Micro-Electro-Mechanical System
  • silicon resonator is a MEMS resonator that uses silicon as the resonant body and utilizes the piezoelectric effect of piezoelectric film for mechanical drive and electrical signal detection.
  • a MEMS silicon resonator generally includes a silicon substrate with a cavity, a thin film silicon layer located above the silicon substrate, and a piezoelectric transducer structure located above the thin film silicon layer, wherein the piezoelectric transducer structure includes at least a piezoelectric layer and a top electrode located above the piezoelectric layer, a passivation layer located above the top electrode, a bottom electrode located below the piezoelectric layer, an isolation layer or a seed layer located below the bottom electrode, etc.
  • silicon with ordinary doping concentration doping concentration less than 10 19 cm -3
  • piezoelectric materials such as aluminum nitride, zinc oxide, PZT, lithium niobate, lithium tantalate, etc.
  • metal electrode materials such as Mo, W, Ru, Al, Cr, Cu, Ti, Pt, Au
  • the overall frequency temperature coefficient of the device is usually around -30ppm/°C, that is, the frequency of the resonator decreases as the temperature increases, resulting in the technical problem of poor frequency temperature stability of MEMS silicon resonators.
  • a silicon oxide layer (containing silicon dioxide or other silicon oxides with a high silicon-oxygen atomic ratio) is usually formed by thermal oxidation below and/or above a thin film silicon layer as a temperature compensation layer.
  • the silicon oxide layer grown by thermal oxidation has a dense film and low material loss, thereby ensuring that the Q value of the resonator will not decrease due to the introduction of a thicker temperature compensation layer.
  • the growth rate of the silicon oxide layer by thermal oxidation decreases as the thickness of the silicon oxide layer increases. Therefore, it is difficult for the grown silicon oxide layer to reach more than 2um, and the growth time is relatively long, which is not conducive to high-efficiency and low-cost production.
  • the present invention mainly solves at least one aspect of the above problems.
  • the embodiments of the present application provide a semiconductor device and an electronic device, which can significantly increase the negative frequency temperature coefficient, and its specific meaning is as follows: the first-order frequency temperature coefficient is changed from negative to zero, or from negative to positive, so that the second-order frequency temperature coefficient is dominant, and the overall frequency-temperature curve presents a parabolic shape; or the first-order and second-order frequency temperature coefficients are close to zero, so that the third-order frequency temperature coefficient is dominant.
  • the frequency-temperature stability of the semiconductor device can be improved.
  • the Q value of the resonator is basically unchanged compared with the case without a temperature compensation layer.
  • a first aspect of an embodiment of the present application provides a semiconductor device, comprising: a plurality of layer structures arranged in stacking, the plurality of layer structures comprising a substrate, a thin film silicon layer and a device layer arranged in sequence, the substrate having a cavity, the thin film silicon layer being arranged on the upper surface of the substrate, the device layer being arranged on the thin film silicon layer, and the device layer forming a transducer structure; at least one layer structure is provided with a temperature compensation layer, and in the stacking direction, the temperature compensation layer is located above the thin film silicon layer; wherein the temperature compensation layer is a doped silicon oxide layer, and the dopant of the temperature compensation layer comprises at least one of fluorine, hydrogen, methyl, methylene, chlorine, carbon, nitrogen, phosphorus and sulfur.
  • the dopant of the temperature compensating layer includes one of fluorine, hydrogen, methyl, methylene, chlorine, carbon, nitrogen, phosphorus, and sulfur.
  • the dopant of the temperature compensating layer is fluorine.
  • the molecular weight percentage of fluorine in the temperature compensating layer is greater than or equal to 3%.
  • the molecular weight percentage of fluorine in the temperature compensating layer is 6%.
  • the thickness of the temperature compensation layer is less than 2 ⁇ m.
  • the thickness of the temperature compensation layer is less than 1.5 ⁇ m.
  • the temperature compensating layer is disposed on the upper surface of at least one layer structure, or the temperature compensating layer constitutes at least a portion of the layer structure.
  • the device layer includes a piezoelectric layer and a top electrode stacked in sequence.
  • the temperature compensation layer is disposed in at least one of the following:
  • the device layer further includes a bottom electrode, and the bottom electrode is disposed between the piezoelectric layer and the thin film silicon layer.
  • the temperature compensation layer is disposed in at least one of the following:
  • the temperature compensation layer is disposed on the upper surface of the top electrode and covers at least a portion of the top electrode.
  • the transducer structure includes a beam structure, and the temperature compensation layer covers an upper surface of the beam structure.
  • the beam structure includes a coupling beam and at least two cantilever beams, wherein the first end of the cantilever beam is connected to the coupling beam and the second end is a free end, wherein at least one of the coupling beam and the cantilever beam is covered with the temperature compensation layer.
  • the temperature compensation layer covers at least a portion of the surface of the cantilever beam.
  • the temperature compensation layer covers the first end of the cantilever beam.
  • the temperature compensation layer is arranged in a first region on the upper surface of the beam structure, wherein there are multiple first regions and the multiple first regions are distributed in a matrix on the upper surface of the beam structure.
  • the temperature compensating layer is disposed in a second region on the upper surface of the beam structure, wherein there are multiple second regions and the multiple second regions are spaced apart and distributed along the extension direction of the beam structure.
  • the widths of the plurality of second regions in the extension direction of the beam structure gradually decrease from the first end of the cantilever beam to the second end of the cantilever beam.
  • the thin film silicon layer is an N-type doped silicon layer
  • the dopant of the thin film silicon layer includes one of phosphorus and arsenic
  • the doping concentration is 1 ⁇ 10 19 cm ⁇ 3 ⁇ 1 ⁇ 10 21 cm ⁇ 3 .
  • a thermal oxide silicon dioxide layer is disposed on a side of the thin film silicon layer close to and/or away from the substrate.
  • a second aspect of an embodiment of the present application provides an electronic device, comprising the above-mentioned semiconductor device.
  • the semiconductor device provided by the present application comprises a plurality of layer structures arranged in a stacked manner, wherein the plurality of layer structures comprises a substrate, a thin film silicon layer and a device layer arranged in sequence, wherein the thin film silicon layer is arranged on the upper surface of the substrate, the device layer is arranged on the thin film silicon layer, and the device layer forms a transducer structure, and at least one layer structure is provided with a temperature compensation layer, and in the stacking direction, the temperature compensation layer is located above the thin film silicon layer, wherein the temperature compensation layer is a doped silicon oxide layer, and the dopant of the temperature compensation layer comprises at least one of fluorine, hydrogen, methyl, methylene, chlorine, carbon, nitrogen, phosphorus and sulfur.
  • the temperature compensation layer as a doped silicon oxide layer
  • the overall negative frequency temperature coefficient of the semiconductor device can be significantly increased, thereby achieving a temperature compensation effect on the semiconductor device, and improving the frequency temperature stability of the semiconductor device
  • the temperature compensation layer as a doped silicon oxide layer
  • the thickness of the required temperature compensation layer can be reduced compared with the undoped silicon oxide layer, so that the quality factor Q of the semiconductor device remains basically unchanged
  • the doped silicon oxide layer is formed by sputtering, the time for growing the oxide layer can be reduced compared with the thermal oxygen growth method, thereby improving the production efficiency and reducing the production cost.
  • FIG. 1a is a schematic cross-sectional view of a structure of a semiconductor device provided in an embodiment of the present application
  • FIG1b is a schematic cross-sectional view of another structure of a semiconductor device provided in an embodiment of the present application.
  • FIG1c is a schematic cross-sectional view of another structure of a semiconductor device provided in an embodiment of the present application.
  • FIG. 2 is a schematic diagram showing the variation trend of the temperature coefficient of the elastic coefficient of the sputtered temperature compensation layer thin film in the semiconductor device provided by an embodiment of the present application with the doping concentration of the dopant F;
  • FIG3 is a schematic diagram of the thickness of the temperature compensation layer and the doping atomic ratio of the doping material F provided in an embodiment of the present application;
  • FIG4 is another schematic diagram of the thickness of the temperature compensation layer and the doping atomic ratio of the doping material F provided in an embodiment of the present application;
  • FIG5 is a schematic top view of a structure of a semiconductor device provided in an embodiment of the present application.
  • FIG6 is a schematic top view of another structure of a semiconductor device provided in an embodiment of the present application.
  • FIG7 is a schematic top view of another structure of a semiconductor device provided in an embodiment of the present application.
  • FIG8 is a schematic top view of another structure of a semiconductor device provided in an embodiment of the present application.
  • FIG9 is a schematic top view of another structure of a semiconductor device provided in an embodiment of the present application.
  • FIG. 10 is a cross-sectional schematic diagram of another structure of a semiconductor device provided in an embodiment of the present application.
  • 10-semiconductor device 100-substrate; 111-cavity; 201-silicon dioxide layer; 204-temperature compensation layer;
  • 300-thin film silicon layer 500-piezoelectric layer; 600-top electrode; 400-bottom electrode; 701-cantilever beam;
  • a semiconductor device such as a piezoelectric MEMS silicon resonator
  • a semiconductor device includes: a silicon substrate with a cavity, a thin film silicon layer located above the cavity, and a piezoelectric transducer structure located above the thin film silicon layer, wherein the piezoelectric transducer structure includes at least a piezoelectric layer and a top electrode located above the piezoelectric layer, a passivation layer may be provided above the top electrode, a bottom electrode may be provided below the piezoelectric layer, and an isolation layer or seed layer located below the bottom electrode, etc.
  • silicon, piezoelectric and electrode materials are usually negative temperature coefficient materials, the frequency of the semiconductor device will decrease as the temperature increases, resulting in a temperature drift phenomenon in the semiconductor device, and this temperature drift phenomenon will lead to poor frequency temperature stability of the semiconductor device.
  • the embodiments of the present application provide a semiconductor device and an electronic device.
  • the temperature compensating layer as a doped silicon oxide layer
  • the overall negative frequency temperature coefficient of the semiconductor device can be significantly increased, thereby achieving a temperature compensating effect on the semiconductor device and improving the frequency-temperature stability of the semiconductor device.
  • the temperature compensating layer as a doped silicon oxide layer
  • the thickness of the required temperature compensating layer can be reduced compared to the undoped silicon oxide layer, so that the quality factor Q of the semiconductor device remains basically unchanged.
  • the doped silicon oxide layer is formed by sputtering, the time for growing the oxide layer can be reduced compared to the thermal oxygen growth method, thereby improving the production efficiency and reducing the production cost.
  • the semiconductor device provided in the embodiments of the present application may be a resonator, a transducer, a driver, etc.
  • the semiconductor device is introduced as a MEMS resonator (eg, a piezoelectric MEMS silicon-based resonator) as an example.
  • the structure of the piezoelectric MEMS silicon-based resonator can be a cantilever beam, a simply supported beam, a tuning fork structure, or other forms of a combination of multiple beams, and its vibration mode can be in-plane flexural mode, out-of-plane flexural mode, torsional mode, etc. It can also be in the form of a diaphragm, and its vibration mode can be Lamé mode, Lamb mode, flexural mode, wine glass mode, etc.
  • an embodiment of the present application provides a semiconductor device 10, which includes a plurality of layer structures stacked together, wherein the plurality of layer structures include a substrate 100, a thin film silicon layer 300 and a device layer arranged in sequence, wherein the thin film silicon layer 300 is arranged on the upper surface of the substrate 100, the device layer is arranged on the thin film silicon layer 300, and the device layer forms a transducer structure; at least one layer structure is provided with a temperature compensating layer 204, and in the stacking direction, the temperature compensating layer 204 is located above the thin film silicon layer 300; wherein the temperature compensating layer 204 is a doped silicon oxide layer, and the dopant of the temperature compensating layer 204 includes at least one of fluorine (F), hydrogen (H), methyl (CH 3 ), methylene (CH 2 ), chlorine (Cl), carbon (C), nitrogen (N), phosphorus (P), and sulfur (S).
  • the substrate 100 may provide a support foundation for the structural layer on the substrate 100.
  • the substrate 100 may be made of a crystalline semiconductor material, the substrate 100 may be a silicon (Si) substrate, the substrate 100 may also be a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, etc.
  • the substrate 100 may be a single-layer structure or a multi-layer composite structure, and may be adaptively designed according to actual needs, and no specific limitation is made here. In the embodiment of the present application, the substrate 100 is taken as a single crystal silicon substrate as an example for introduction.
  • a cavity 111 is provided on the side of the substrate 100 facing the thin film silicon layer 300, wherein the cross-sectional shape of the cavity 111 may be any shape such as a rectangle or a trapezoid.
  • the cavity 111 may be provided in the substrate 100, that is, the cavity is formed by etching the substrate 100, as shown in FIGS. 1a and 1b, or may be provided on the substrate 100, that is, the cavity is formed by etching a bonding layer (which may also be a buried oxide layer in an SOI wafer), wherein the bonding layer may be a silicon dioxide layer 201, as shown in FIG. 1c.
  • the substrate 100 and the thin film silicon layer 300 can be bonded directly, as shown in FIG. 1b , or can be bonded through a bonding layer (generally a dielectric layer such as silicon dioxide, aluminum oxide, etc., or a metal layer, or an organic compound), as shown in FIGS. 1a and 1c .
  • a bonding layer generally a dielectric layer such as silicon dioxide, aluminum oxide, etc., or a metal layer, or an organic compound
  • the temperature compensation layer 204 is a doped silicon oxide layer, that is, the silicon oxide is doped while growing the silicon oxide.
  • the dopant may be at least one of the elements F, H, Cl, C, N, P, S, etc., or the dopant may be an organic substance, such as CH 3 , CH 2 , etc.
  • the temperature compensation layer 204 is located above the thin film silicon layer 300, and the temperature compensation layer 204 is set as a doped silicon oxide layer, and the dopant is at least one of fluorine (F), hydrogen (H), methyl (CH 3 ), methylene (CH 2 ), chlorine (Cl), carbon (C), nitrogen (N), phosphorus (P), and sulfur (S), the overall frequency temperature coefficient of the semiconductor device 10 can be significantly increased to achieve zero drift temperature.
  • the so-called zero temperature drift generally refers to that the first-order temperature coefficient is close to zero, and the second-order temperature coefficient is the dominant term, or the first-order and second-order temperature coefficients are close to zero, and the third-order temperature coefficient is the dominant term, thereby improving the temperature stability of the semiconductor device 10; in addition, compared with using an undoped silicon oxide layer as a temperature compensation layer, the present scheme can reduce the thickness of the temperature compensation layer 204, thereby ensuring that the quality factor Q of the semiconductor device 10 is almost not reduced; in addition, the doped silicon oxide layer can be deposited by plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the temperature compensation layer is grown on any structural layer above the thin film silicon layer 300 by sputtering processes such as chemical vapor deposition (PECVD) or chemical vapor deposition (CVD). Therefore, the position of the temperature compensation layer can be flexibly set according to the vibration mode of different resonators. At the same time, while meeting the temperature compensation effect of the semiconductor device 10, the sputtering method can improve production efficiency and thus reduce costs.
  • PECVD chemical vapor deposition
  • CVD chemical vapor deposition
  • the dopant of the temperature compensating layer 204 is one of fluorine (F), hydrogen (H), methyl (CH 3 ), methylene (CH 2 ), chlorine (Cl), carbon (C), nitrogen (N), phosphorus (P), and sulfur (S).
  • the dopant of the temperature compensating layer 204 is fluorine (F).
  • the molecular weight percentage of fluorine in the temperature compensation layer may be greater than or equal to 3%.
  • the molecular weight percentage of fluorine in the temperature compensation layer is 6%.
  • the temperature coefficient can be significantly increased while the thickness of the temperature compensation layer can be reduced.
  • the thickness of the temperature compensation layer doped with fluorine can be less than 2 ⁇ m.
  • the thickness of the temperature compensation layer doped with fluorine can be prepared to be less than 1.5 ⁇ m. In this way, the quality factor Q of the semiconductor device will not be substantially reduced while meeting the temperature compensation requirements.
  • a thermal oxide silicon dioxide layer formed by thermal oxygen growth is provided on a side of the thin film silicon layer close to the substrate; or, a thermal oxide silicon dioxide layer formed by thermal oxygen growth is provided on a side of the thin film silicon layer away from the substrate; or, a thermal oxide silicon dioxide layer formed by thermal oxygen growth is provided on both the side of the thin film silicon layer close to and away from the substrate; wherein the thermal oxide silicon dioxide layer can serve as a temperature compensation layer.
  • Figure 2 shows the temperature coefficient of the elastic coefficient (or Young's modulus) of the sputtered temperature compensation layer film as F Schematic diagram of the trend of doping concentration changes.
  • point A corresponds to the temperature coefficient value of the silicon dioxide film (SiO2 layer) grown by wet thermal oxygen (about 180ppm/°C)
  • point B corresponds to the temperature coefficient value of the SiO2 film grown by dry thermal oxygen (about 195ppm/°C). It can be seen that when the F doping concentration is 0, the temperature coefficient of the Young's modulus of the sputtered SiO2 is about 140ppm/°C, which is lower than that of the SiO2 layer grown by thermal oxygen.
  • the temperature coefficient of the Young's modulus of the doped SiO2 is greater than that of the SiO2 layer grown by thermal oxygen.
  • the temperature coefficient of the Young's modulus of the doped SiO2 is greater than twice that of the non-doped SiO2 layer.
  • the temperature coefficient of the Young's modulus of the SiO2 is greater than twice that of the SiO2 layer grown by thermal oxygen. It can be seen that by doping the temperature compensation layer 204 , the positive temperature coefficient of the temperature compensation layer 204 can be significantly improved, so that the temperature compensation of the semiconductor device can be achieved with a thinner thickness.
  • the piezoelectric driven cantilever beam 701 type MEMS resonator when its vibration mode is the surface vibration mode, when ordinary Si (such as boron doping 5 ⁇ 10 18 cm -3 ) is used, when the thickness of Mo (top electrode 600)-AlN (piezoelectric layer 500)-Mo (bottom electrode 400)-Si (substrate 100) from top to bottom is 1000A-1um-1000A-8um respectively, when the first-order temperature coefficient of the resonator is 0, the required thickness of the temperature compensation layer 204 with different doping concentrations is shown in Figure 3.
  • the required thickness of the temperature compensating layer 204 is approximately 3.25um; when the F doping concentration is 3%, the required thickness of the temperature compensating layer 204 is approximately 2.4um (approximately 74% of the non-doped thickness); when the F doping concentration is 6%, the required thickness of the temperature compensating layer 204 is approximately 2um (approximately 61.5% of the non-doped thickness); when the F doping concentration is 10%, the required thickness of the temperature compensating layer 204 is approximately 1.6um (approximately 49% of the non-doped concentration).
  • the use of a doped silicon oxide layer can achieve zero temperature compensation for the first-order temperature coefficient of the resonator with a thinner thickness, and reducing the proportion of the temperature compensating layer in the overall device thickness can keep the Q value of the device basically unchanged compared to when the temperature compensating layer is not added.
  • the thickness of Mo (top electrode 600)-AlN (piezoelectric layer 500)-Mo (bottom electrode 400)-Si (substrate 100) from top to bottom is: 1000A-1um-1000A-8um, respectively.
  • the first-order temperature coefficient of the resonator is 0, the required thickness of the temperature compensation layer 204 with different doping concentrations is shown in FIG4 .
  • the required thickness is about 1um; when the F doping concentration is 3%, the required thickness is about 0.76um (about 76% of the non-doped thickness); when the F doping concentration is 6%, the required thickness is about 0.64um (about 64% of the non-doped thickness); when the F doping concentration is 10%, the required thickness is about 0.5um (about 50% of the non-doped concentration).
  • the doping type is N-type
  • the dopant is a Group V element such as phosphorus and arsenic
  • the doping concentration is between 1x10 19 cm -3 and 1x10 21 cm -3 .
  • the thickness of the required doped silicon oxide layer can be further reduced. By further reducing the proportion of the temperature compensation layer in the overall device thickness, the Q value of the device can be kept basically unchanged compared with the case where the temperature compensation layer is not added.
  • the temperature compensating layer 204 is disposed on the upper surface of at least one layer structure. It is understandable that, since the temperature compensating layer 204 is disposed on different structural layers, the temperature compensating effect produced is different. Compared with the silicon dioxide layer 201 grown by the thermal oxidation method, which must be located on the upper surface of the substrate 100 or the lower surface of the substrate 100, the temperature compensating layer 204 in this embodiment can be disposed on the upper surface of at least one layer structure above the thin film silicon layer 300, so that the setting position of the temperature compensating layer 204 can be more flexible, thereby achieving an ideal temperature compensating effect.
  • the device layer includes a piezoelectric layer 500 and a top electrode 600 which are stacked in sequence.
  • the material of the piezoelectric layer 500 may include PZT, ZnO, AlN, and doped AlN.
  • the material of the top electrode 600 located above the piezoelectric layer 500 may be at least one of Mo, W, Ru, Al, Cr, Cu, Ti, Pt, Au, Ir, Ta, and Rh.
  • the temperature compensating layer 204 can be disposed at at least one of the following: for example, the temperature compensating layer 204 can be disposed between the piezoelectric layer 500 and the thin film silicon layer 300, the temperature compensating layer 204 can also be disposed between the piezoelectric layer 500 and the top electrode 600, the temperature compensating layer 204 is disposed on the upper surface of the top electrode 600, etc.
  • the temperature compensating layer 204 can be disposed at different positions, different temperature compensating effects can be achieved. Therefore, the setting position of the temperature compensating layer 204 can be adaptively adjusted according to actual needs, and no specific limitation is made here.
  • the temperature compensating layer 204 can also constitute at least a partial layer structure.
  • the temperature compensating layer 204 is arranged in the top electrode 600, that is, the temperature compensating layer 204 is a part of the top electrode 600; or, the temperature compensating layer 204 is arranged in the thin film silicon layer 300, that is, the temperature compensating layer 204 is a part of the thin film silicon layer 300; or, the temperature compensating layer 204 is arranged in the piezoelectric layer 500, etc.
  • the device layer also includes a bottom electrode 400, which is disposed between the piezoelectric layer 500 and the thin film silicon layer 300, wherein the material of the bottom electrode 400 may also be at least one of Mo, W, Ru, Al, Cr, Cu, Ti, Pt, Au, Ir, Ta, and Rh.
  • the temperature compensating layer 204 can be arranged at at least one of the following: for example, the temperature compensating layer 204 is located between the thin film silicon layer 300 and the bottom electrode 400, the temperature compensating layer 204 is located between the bottom electrode 400 and the piezoelectric layer 500, the temperature compensating layer 204 is located between the piezoelectric layer 500 and the top electrode 600, or the temperature compensating layer 204 is located on the upper surface of the top electrode 600, etc.
  • the setting position of the temperature compensating layer 204 has the advantages of being able to be based on the temperature compensating layer 204. Adaptive adjustment is performed according to actual needs, so as to achieve different temperature compensation effects by setting the temperature compensation layer 204 at different positions, thereby improving the stability of the semiconductor device 10 .
  • the temperature compensation layer 204 is disposed on the upper surface of the top electrode 600 and covers at least a portion of the top electrode 600.
  • the temperature compensation layer 204 can completely cover the top electrode 600 or partially cover the top electrode 600, which can be adjusted according to the required temperature compensation effect.
  • the transducer structure includes a beam structure, and the temperature compensation layer 204 covers the upper surface of the beam structure.
  • the beam structure includes a coupling beam 702 and at least two cantilever beams 701, the first end of the cantilever beam 701 is connected to the coupling beam 702, and the second end is a free end, wherein at least one of the coupling beam 702 and the cantilever beam 701 is covered with the temperature compensation layer 204, so as to meet the temperature compensation effect through the temperature compensation layer 204, thereby improving the stability of the semiconductor device 10.
  • FIG5 is a top view of a tuning fork type MEMS resonator based on a cantilever beam 701; the cross-sectional schematic diagram at A-A in FIG5 can refer to FIG1a; it should be noted that the structure of the MEMS resonator provided in the embodiment of the present application is not limited to FIG5, but the cross-sectional laminated structure thereof can refer to FIG1a.
  • the beam structure includes two cantilever beams 701, a coupling beam 702 connecting the two cantilever beams 701, and a support structure 703 is provided at one end of the coupling beam 702.
  • the temperature compensation layer 204 covers the upper surface of the entire device to meet the temperature compensation requirements and achieve the purpose of zero drift temperature, thereby improving the stability of the semiconductor device 10.
  • the substrate 100 is a single crystal silicon substrate with a cavity 111.
  • a bonding layer for bonding is provided on one side of the substrate 100 having the cavity 111, wherein the bonding layer can be grown on one side of the substrate 100 by a thermal oxidation method, wherein the material of the bonding layer can be silicon dioxide, that is, a silicon dioxide layer 201 is provided on the bottom wall of the cavity 111 of the substrate 100, and a thermal oxygen temperature compensation layer 204 is no longer grown under the thin film silicon layer 300 used as a device layer.
  • an impurity-doped silicon oxide layer can be grown above the top electrode 600 by processes such as PECVD or CVD to form a temperature compensation layer 204, thereby meeting the temperature compensation requirements and improving the frequency temperature stability of the semiconductor device 10.
  • a passivation layer or other functional layer may be provided above the temperature compensating layer 204 or between the temperature compensating layer 204 and the top electrode 600.
  • a passivation layer may be provided between the temperature compensating layer 204 and the top electrode 600, and the temperature compensating layer 204 and the top electrode 600 may be electrically isolated through the passivation layer.
  • the temperature compensation layer 204 covers at least a portion of the surface of the cantilever beam 701, for example, the temperature compensation layer 204 only covers the first end of the cantilever beam 701; or Layer 204 only covers part of the cantilever beam 701 and part of the coupling beam 702; alternatively, the temperature compensation layer 204 covers the cantilever beam 701, the coupling beam 702 and the supporting structure 703, etc.
  • the temperature compensation layer 204 covers different areas, different temperature compensation effects can be obtained, which can be specifically set according to actual temperature compensation requirements.
  • the temperature compensation layer 204 is disposed in a first region on the upper surface of the beam structure, wherein there are multiple first regions, and the multiple first regions are distributed in a matrix on the upper surface of the beam structure.
  • the first region may only cover the cantilever beam 701 or a portion of the cantilever beam 701, or the first region may cover part or all of the cantilever beam 701 and part (or all) of the coupling beam 702, etc.
  • the temperature compensating layer 204 By patterning the temperature compensating layer 204, there are multiple patterned temperature compensating layers 204, and the multiple temperature compensating layers 204 can be arranged in a regular pattern array on the upper surface of the beam structure, for example, in a matrix distribution, and the temperature compensating layer 204 covers the corresponding first area. In this way, the overall temperature coefficient of the semiconductor device 10 can be adjusted by the arrangement density of the temperature compensating layer 204 to meet the temperature compensation demand of the semiconductor device 10 and improve the stability of the semiconductor device 10.
  • the temperature compensation layer 204 may match the shape and size of the first region.
  • the temperature compensating layer 204 is disposed in the second region on the upper surface of the beam structure, wherein there are multiple second regions, and the multiple second regions are spaced apart along the extension direction of the beam structure (e.g., cantilever beam 701) (e.g., the length direction of the cantilever beam 701).
  • the multiple patterned temperature compensating layers 204 are disposed on the upper surface of the beam structure, and are spaced apart along the extension direction of the beam structure (e.g., cantilever beam 701), and the temperature compensating layer 204 covers the second region corresponding thereto, so that the overall temperature coefficient of the semiconductor device 10 can be adjusted by the arrangement density of the temperature compensating layer 204 in the extension direction of the beam structure, so as to meet the temperature compensation requirements of the semiconductor device 10 and improve the stability of the semiconductor device 10.
  • the temperature compensation layer 204 can be patterned according to the stress distribution of the resonator so that it mainly covers the area with greater stress.
  • the area with the maximum stress is the fixed end of the first end, or the end with the minimum amplitude, and the stress gradually decreases along the extension direction of the cantilever beam 701.
  • the minimum stress point is the second end (i.e., the free end) or the end with the maximum amplitude. Therefore, the patterned temperature compensation layer 204 partially covers a part of the cantilever beam 701 from the first end to the second end.
  • the temperature compensation layer 204 covers 50% of the total length from the first end to the second end of the cantilever beam 701, so as to regulate the overall temperature coefficient of the semiconductor device 10.
  • the cantilever beam 701 its stress gradually decreases from the first end to the second end. Therefore, the width of the multiple second regions in the extension direction of the beam structure (such as the cantilever beam 701) can also gradually decrease from the first end of the cantilever beam 701 to the second end of the cantilever beam 701. Therefore, the width of the temperature compensation layer 204 arranged on the upper surface of the beam structure also gradually decreases from the first end to the second end of the cantilever beam 701. That is to say, the area ratio of the temperature compensation layer 204 covering the stress is large in the area with large stress, and the area ratio of the temperature compensation layer 204 covering the stress is small in the area with small stress, as shown in Figure 9.
  • the distribution density of multiple second regions in the extension direction of the beam structure can gradually decrease from the first end of the cantilever beam 701 to the second end of the cantilever beam 701.
  • the distribution density of the temperature compensation layer 204 covering the second region also gradually decreases from the first end to the second end of the cantilever beam 701. That is to say, the temperature compensation layer 204 is densely distributed in the area with high stress and sparsely distributed in the area with low stress, thereby realizing flexible regulation of the overall temperature coefficient of the semiconductor device 10 to meet the temperature compensation requirements and improve the stability of the semiconductor device 10.
  • the temperature compensation layer 204 is located on the upper surface of the transducer structure.
  • a silicon dioxide layer 201 can be formed on the lower surface of the thin film silicon layer 300 by a thermal oxygen growth method.
  • the silicon dioxide layer 201 formed by the thermal oxygen growth method can also serve as a bonding layer between the substrate 100 and the thin film silicon layer 300, so that the substrate 100 and the thin film silicon layer 300 are bonded through the bonding layer.
  • the overall temperature coefficient of the semiconductor device 10 can be jointly adjusted to meet the temperature compensation requirements of the semiconductor device 10 and improve the stability of the semiconductor device 10.
  • the temperature compensation layer 204 of the doped silicon oxide layer and the silicon dioxide layer 201 obtained by thermal oxygen growth can be arbitrarily combined and arranged in different positions, as long as they can significantly increase the overall temperature coefficient of the semiconductor device 10, meet the temperature compensation effect, and improve the stability of the semiconductor device 10. No specific restrictions are made here.
  • An embodiment of the present application also provides an electronic device, comprising the semiconductor device provided in the above embodiment.
  • the semiconductor device provided in the embodiment of the present application comprises a plurality of layer structures arranged in a stacked manner, wherein the plurality of layer structures comprise a substrate, a thin film silicon layer and a device layer arranged in sequence, wherein the thin film silicon layer is arranged on the upper surface of the substrate, the device layer is arranged on the thin film silicon layer, and the device layer forms a transducer structure, at least one layer structure is provided with a temperature compensation layer, and in the stacking direction, the temperature compensation layer is located above the thin film silicon layer, wherein the temperature compensation layer is a doped silicon oxide layer, and the dopant of the temperature compensation layer comprises at least one of F, H, CH 3 , CH 2 , Cl, C, N, P, and S.
  • the temperature compensation layer as a doped silicon oxide layer, it is possible to Significantly increasing the temperature coefficient can satisfy the temperature compensation effect and improve the stability of the semiconductor device; in addition, the thickness of the temperature compensation layer can be reduced, the production cost can be reduced, the production efficiency can be improved, and the quality factor Q of the semiconductor device can not be reduced.

Landscapes

  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

本申请实施例提供一种半导体器件及电子设备，该半导体器件包括层叠设置的多个层结构，多个层结构包括依次设置的衬底、薄膜硅层和器件层，衬底具有空腔，薄膜硅层设置于衬底的上表面，器件层设置于薄膜硅层上，且器件层形成换能器结构，至少一个层结构设置有温补层，且在层叠方向上，温补层位于薄膜硅层的上方，其中，温补层为掺杂氧化硅层，温补层的掺杂物包括氟、氢、甲基、亚甲基、氯、碳、氮、磷、硫中的至少一种。本申请实施例可以显著的增大温度系数，即可以满足温补效果，提高半导体器件的稳定性。

Description

半导体器件及电子设备
本申请要求于2022年10月21日提交中国专利局、申请号为202211296632.8、申请名称为“半导体器件及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体器件及电子设备。
背景技术
压电MEMS(Micro-Electro-Mechanical System，微机电系统)硅谐振器是一种以硅为谐振主体利用压电薄膜的压电效应进行机械驱动及电信号检测的MEMS谐振器。
相关技术中，MEMS硅谐振器通常包括带空腔的硅衬底，位于硅衬底上方的薄膜硅层以及位于薄膜硅层上方的压电换能器结构，其中，压电换能器结构至少包括压电层和位于压电层上方的顶电极，还包括位于顶电极上方的钝化层，包括位于压电层下方的底电极，包括位于底电极下方的隔离层或种子层等。
然而，普通掺杂浓度的硅(掺杂浓度小于1019cm-3)以及常用的压电材料(如氮化铝、氧化锌、PZT、铌酸锂、钽酸锂等)、金属电极材料(如：Mo、W、Ru、Al、Cr、Cu、Ti、Pt、Au)通常为负温度系数材料，使得器件整体的频率温度系数通常在-30ppm/℃左右，即谐振器的频率随着温度升高而降低，导致MEMS硅谐振器的频率温度稳定性差的技术问题。
在现有技术中通常是采用在薄膜硅层下方和/或上方热氧形成氧化硅层(包含二氧化硅或其他硅氧原子比的硅氧化物)作为温补层，主要是因为热氧生长的氧化硅层成膜致密，材料的损耗较低，从而可以保证谐振器Q值不会因引入较厚的温补层而下降，但是采用热氧法生长的氧化硅层会随着氧化硅层厚度增大而速率降低，因此生长的氧化硅层很难达到2um以上，且生长时间较长，不利于高效率低成本生产。而如果采用CVD或者其他溅射法生长氧化硅层，虽然可以容易的实现较厚的氧化硅层，但相比热氧形成的氧化硅 层，其成膜质量较疏松，损耗较大，从而导致器件整体Q值会显著下降。因此，本发明主要解决上述问题的至少一个方面。
发明内容
鉴于上述问题，本申请实施例提供一种半导体器件及电子设备，能够显著的增大负频率温度系数，其具体含义如下：使其一阶频率温度系数由负趋近于零，或由负变为正，从而使得其二阶频率温度系数为主导，整体频率温度曲线呈现抛物线形状；或者使其一阶和二阶频率温度系数趋近于零，从而使其三阶频率温度系数为主导。从而能够提高半导体器件的频率温度稳定性。同时保证谐振器的Q值相比无温补层的情况基本不变。
为了实现上述目的，本申请实施例提供如下技术方案：
本申请实施例第一方面提供一种半导体器件，包括：层叠设置的多个层结构，多个所述层结构包括依次设置的衬底、薄膜硅层和器件层，所述衬底具有空腔，所述薄膜硅层设置于所述衬底的上表面，所述器件层设置于所述薄膜硅层上，且所述器件层形成换能器结构；至少一个层结构设置有温补层，且在层叠方向上，所述温补层位于所述薄膜硅层的上方；其中，所述温补层为掺杂氧化硅层，所述温补层的掺杂物包括氟、氢、甲基、亚甲基、氯、碳、氮、磷、硫中的至少一种。
在一些可选的实施方式中，所述温补层的掺杂物包括氟、氢、甲基、亚甲基、氯、碳、氮、磷、硫中的一种。
在一些可选的实施方式中，所述温补层的掺杂物为氟。
在一些可选的实施方式中，所述温补层中的氟的分子量百分比为大于或等于3％。
在一些可选的实施方式中，所述温补层中的氟的分子量百分比为6％。
在一些可选的实施方式中，所述温补层的厚度小于2μm。
在一些可选的实施方式中，所述温补层的厚度小于1.5μm。
在一些可选的实施方式中，所述温补层设置在至少一个层结构的上表面，或者，所述温补层构成至少部分所述层结构。
在一些可选的实施方式中，所述器件层包括依次层叠设置的压电层和顶电极。
在一些可选的实施方式中，所述温补层设置于以下至少一者：
所述压电层和所述薄膜硅层之间、所述压电层和所述顶电极之间、所述顶电极的上表面。
在一些可选的实施方式中，所述器件层还包括底电极，所述底电极设置于所述压电层和所述薄膜硅层之间。
在一些可选的实施方式中，所述温补层设置于以下至少一者：
所述薄膜硅层和所述底电极之间、所述底电极和所述压电层之间、所述压电层和所述顶电极之间、所述顶电极的上表面。
在一些可选的实施方式中，所述温补层设置于所述顶电极的上表面，并覆盖至少部分所述顶电极。
在一些可选的实施方式中，所述换能器结构包括梁结构，所述温补层覆盖于所述梁结构的上表面。
在一些可选的实施方式中，所述梁结构包括耦合梁和至少两个悬臂梁，所述悬臂梁的第一端连接于所述耦合梁，第二端为自由端，其中，所述耦合梁和所述悬臂梁的至少一者覆盖有所述温补层。
在一些可选的实施方式中，所述温补层覆盖所述悬臂梁的至少部分表面。
在一些可选的实施方式中，所述温补层覆盖所述悬臂梁的第一端。
在一些可选的实施方式中，所述温补层设置于所述梁结构的上表面的第一区域内，其中，所述第一区域为多个，且多个所述第一区域在所述梁结构的上表面呈矩阵分布。
在一些可选的实施方式中，所述温补层设置于所述梁结构的上表面的第二区域内，其中，所述第二区域为多个，且多个所述第二区域沿所述梁结构的延伸方向间隔分布。
在一些可选的实施方式中，多个所述第二区域在所述梁结构的延伸方向的宽度沿所述悬臂梁的第一端至所述悬臂梁的第二端逐渐减小。
在一些可选的实施方式中，所述薄膜硅层为N型掺杂硅层，所述薄膜硅层的掺杂物包括磷、砷中的一种，且掺杂浓度为1x1019cm-3～1x1021cm-3。
在一些可选的实施方式中，所述薄膜硅层靠近和/或远离所述衬底的一侧设置有热氧二氧化硅层。
本申请实施例第二方面提供一种电子设备，包括上述半导体器件。
本申请实施提供的半导体器件，包括层叠设置的多个层结构，多个层结构包括依次设置的衬底、薄膜硅层和器件层，薄膜硅层设置于衬底的上表面，器件层设置于薄膜硅层上，且器件层形成换能器结构，至少一个层结构设置有温补层，且在层叠方向上，温补层位于薄膜硅层的上方，其中，温补层为掺杂氧化硅层，温补层的掺杂物包括氟、氢、甲基、亚甲基、氯、碳、氮、磷、硫中的至少一种。上述方案中，通过将温补层设置为掺杂氧化硅层，这样，可以显著的增大半导体器件整体的负频率温度系数，从而实现对半导体器件的温补效果，能够提高半导体器件的频率温度稳定性；另外，通过将温补层设置为掺杂氧化硅层，相比不掺杂的氧化硅层，可以减小所需温补层的厚度，使得半导体器件的品质因数Q基本保持不变；同时，由于采用溅射的方式形成掺杂氧化硅层，因此相比热氧生长法，可以减小生长氧化层的时间，提高生产效率，进而降低生产成本。
本申请的构造以及它的其他发明目的及有益效果将会通过结合附图而对优选实施例的描述而更加明显易懂。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a为本申请实施例提供的半导体器件的一种结构剖面示意图；
图1b为本申请实施例提供的半导体器件的另一种结构剖面示意图；
图1c为本申请实施例提供的半导体器件的又一种结构剖面示意图；
图2为本申请实施例提供的半导体器件中溅射生长的温补层薄膜弹性系数的温度系数随掺杂物F掺杂浓度的变化趋势示意图；
图3为本申请实施例提供的温补层的厚度与掺杂物质F的掺杂原子比的示意图；
图4为本申请实施例提供的温补层的厚度与掺杂物质F的掺杂原子比的另一示意图；
图5为本申请实施例提供的半导体器件的一种结构的俯视示意图；
图6为本申请实施例提供的半导体器件的另一种结构的俯视示意图；
图7为本申请实施例提供的半导体器件的另一种结构的俯视示意图；
图8为本申请实施例提供的半导体器件的另一种结构的俯视示意图；
图9为本申请实施例提供的半导体器件的另一种结构的俯视示意图；
图10为本申请实施例提供的半导体器件的另一种结构的剖面示意图。
附图标记：
10-半导体器件；100-衬底；111-空腔；201-二氧化硅层；204-温补层；
300-薄膜硅层；500-压电层；600-顶电极；400-底电极；701-悬臂梁；
702-耦合梁；703-支撑结构。
具体实施方式
相关技术中，半导体器件(例如压电MEMS硅谐振器)包括：带空腔的硅衬底，位于空腔上方的薄膜硅层，以及位于薄膜硅层上方的压电换能器结构，其中，压电换能器结构至少包括压电层和位于压电层上方的顶电极，顶电极的上方还可以设置有钝化层，压电层下方还可以设置有底电极，以及位于底电极下方的隔离层或种子层等。然而，由于硅、压电以及电极材料通常为负温度系数材料，因此半导体器件的频率会随着温度升高而降低，使得半导体器件存在温漂现象，而这种温漂现象会导致半导体器件的频率温度稳定性差。
为了解决上述问题，本申请实施例提供一种半导体器件及电子设备，通过将温补层设置为掺杂氧化硅层，这样，可以显著的增大半导体器件整体的负频率温度系数，从而实现对半导体器件的温补效果，能够提高半导体器件的频率温度稳定性；另外，通过将温补层设置为掺杂氧化硅层，相比不掺杂的氧化硅层，可以减小所需温补层的厚度，使得半导体器件的品质因数Q基本保持不变；同时，由于采用溅射的方式形成掺杂氧化硅层，因此相比热氧生长法，可以减小生长氧化层的时间，提高生产效率，进而降低生产成本。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造 性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
本申请实施例提供的半导体器件可以是谐振器、换能器、驱动器等，在本申请中，以半导体器件为MEMS谐振器(例如压电MEMS硅基谐振器)为例进行介绍。
压电MEMS硅基谐振器的结构可以为悬臂梁、简支梁、音叉结构等具有多个梁组合结构的形式，其振动模式可以为in-plane flexural mode(面内弯曲振动模式)、out-of-plane flexural mode(面外弯曲振动模式)、torsional mode(扭转模式)等，也可以为振膜形式，其振动模式可以为Lamé(拉梅)模式、Lamb(兰姆波)模式、flexural(弯曲)模式、wine glass(酒杯模式)等。
请参照图1a，本申请实施例提供一种半导体器件10，其包括层叠设置的多个层结构，多个层结构包括依次设置的衬底100、薄膜硅层300和器件层，薄膜硅层300设置于衬底100的上表面，器件层设置于薄膜硅层300上，且器件层形成换能器结构；至少一个层结构设置有温补层204，且在层叠方向上，温补层204位于薄膜硅层300的上方；其中，温补层204为掺杂氧化硅层，温补层204的掺杂物包括氟(F)、氢(H)、甲基(CH3)、亚甲基(CH2)、氯(Cl)、碳(C)、氮(N)、磷(P)、硫(S)中的至少一种。
其中，衬底100可以为衬底100上的结构层提供支撑基础。该衬底100可以为晶体半导体材料制成，衬底100可以为硅(Si)衬底，衬底100还可以为锗化硅(SiGe)衬底、碳化硅(SiC)衬底、绝缘体上硅(silicon-on-insulator，简称SOI)衬底等，其中，衬底100可以为单层结构，也可以为多层复合结构，具体根据实际需求进行适应性设计，在此不做具体限制，在本申请实施例中，以衬底100为单晶硅衬底为例进行介绍。
在一些实施例中，衬底100面向薄膜硅层300的一侧设置有空腔111，其中，空腔111的截面形状可以为矩形、梯形等任意形状，空腔111可以设置在衬底100内，即通过刻蚀衬底100形成空腔，如图1a和1b所示，也可以设置在衬底100上，即通过刻蚀键合层(也可以是SOI晶圆中的埋氧层)形成空腔，其中，键合层可以是二氧化硅层201，如图1c所示。
衬底100与薄膜硅层300可以直接键合，如图1b所示，也可以通过键合层(一般为介质层，如二氧化硅、氧化铝等，也可以为金属层，或有机化合物)进行键合，如图1a和1c所示。
温补层204为掺杂氧化硅层，即在生长氧化硅的同时对氧化硅做掺 杂，其掺杂物可以为F、H、Cl、C、N、P、S等元素中的至少一者，或者掺杂物也可以为有机物，例如CH3、CH2等。
上述方案中，通过在至少一个层结构上设置温补层204，且温补层204位于薄膜硅层300的上方，并将温补层204设置为掺杂氧化硅层，其掺杂物为氟(F)、氢(H)、甲基(CH3)、亚甲基(CH2)、氯(Cl)、碳(C)、氮(N)、磷(P)、硫(S)中的至少一种，可以显著的增大半导体器件10的整体频率温度系数，实现零漂温，所谓零温漂一般是指一阶温度系数接近于零，而二阶温度系数为主导项，或者一阶和二阶温度系数接近于零，三阶温度系数为主导项，从而能够提高半导体器件10的温度稳定性；另外，相比采用不掺杂氧化硅层做温补层，本方案可以减小温补层204的厚度，从而能够保证几乎不会降低半导体器件10的品质因数Q；此外，掺杂氧化硅层可以采用等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)或者化学气相沉积(Chemical Vapor Deposition，简称CVD)等溅射工艺在薄膜硅层300以上的任意一结构层上生长，因此，可以根据不同谐振器的振动模式灵活设置温补层的位置；同时，在满足半导体器件10的温补效果的同时，溅射方法可以提高生产效率，从而降低成本。
在一些实施例中，温补层204的掺杂物为氟(F)、氢(H)、甲基(CH3)、亚甲基(CH2)、氯(Cl)、碳(C)、氮(N)、磷(P)、硫(S)中的一种，示例性的，温补层204的掺杂物为氟(F)。
在一些实施例中，温补层中的氟的分子量百分比可以大于或等于3％，优选的，温补中的氟的分子量百分比为6％。
通过上述方案，可以显著增大温度系数的同时，可以减小温补层的厚度，示例性的，掺杂物为氟的温补层的厚度可以小于2μm，优选的，掺杂为氟的温补层的厚度可以制备为小于1.5μm，这样，可以在满足温补要求的同时，基本不会降低半导体器件的品质因数Q。
在一些实施例中，薄膜硅层靠近衬底的一侧设置有通过热氧生长的方式形成的热氧二氧化硅层；或者，薄膜硅层背离衬底的一侧设置有通过热氧生长的方式形成的热氧二氧化硅层；或者，薄膜硅层靠近和背离衬底的一侧均设置有通过热氧生长的方式形成的热氧二氧化硅层；其中，热氧二氧化硅层可以作为温补层。
图2为溅射生长的温补层薄膜弹性系数(或杨氏模量)的温度系数随F 掺杂浓度变化趋势示意图。在图2中，A点对应湿法热氧生长的二氧化硅薄膜(SiO2层)对应的温度系数值(大约为180ppm/℃)，B点对应干法热氧生长的SiO2薄膜对应的温度系数值(大约为195ppm/℃)。可以看到，F掺杂浓度为0时，溅射生长的SiO2杨氏模量的温度系数大约为140ppm/℃，低于热氧法生长的SiO2层，而当F掺杂浓度大于3％时，掺杂SiO2杨氏模量的温度系数大于热氧法生长的SiO2层，当F掺杂浓度大于6％时，掺杂SiO2杨氏模量的温度系数大于非掺杂SiO2层的2倍，当F掺杂浓度大于10％时，SiO2杨氏模量的温度系数大于热氧生长的SiO2层的2倍。由此可见，通过对温补层204进行掺杂，可以显著的提高温补层204的正温度系数，从而能够以更薄的厚度来实现对半导体器件的温度补偿。
以压电驱动的悬臂梁701式MEMS谐振器为例，其振动模式为面振动模式时，当采用普通Si(如硼掺杂5×1018cm-3)时，从上到下Mo(顶电极600)-AlN(压电层500)-Mo(底电极400)-Si(衬底100)厚度分别为1000A-1um-1000A-8um时，谐振器一阶温度系数为0时，所需不同掺杂浓度温补层204的厚度如图3所示。可以看到，当F掺杂浓度为0时，温补层204所需厚度大约为3.25um；当F掺杂浓度为3％时，温补层204所需厚度大约为2.4um(约为非掺杂厚度的74％)；当F掺杂浓度为6％时，温补层204所需厚度大约为2um(约为非掺杂厚度的61.5％)；当F掺杂浓度为10％时，温补层204所需厚度大约为1.6um(约为非掺杂浓度的49％)，由此可见，采用掺杂氧化硅层可以以更薄的厚度来实现对谐振器一阶温度系数的零温度补偿，而减小温补层在整体器件厚度中的占比，可以保持器件的Q值与未增加温补层时基本不变。
而当温补层204采用高掺杂的n-type Si(如磷或砷掺杂浓度为8×1019cm-3)时，从上到下Mo(顶电极600)-AlN(压电层500)-Mo(底电极400)-Si(衬底100)厚度分别为：1000A-1um-1000A-8um时，谐振器一阶温度系数为0时，所需不同掺杂浓度温补层204的厚度如图4中所示。可以看到，当F掺杂浓度为0时，所需厚度大约为1um；当F掺杂浓度为3％时，所需厚度大约为0.76um(约为非掺杂厚度的76％)；当F掺杂浓度为6％时，所需厚度大约为0.64um(约为非掺杂厚度的64％)；当F掺杂浓度为10％时，所需厚度大约为0.5um(约为非掺杂浓度的50％)。由此可 见，当采用高掺杂薄膜硅层时，掺杂类型为N型，掺杂剂为磷、砷等五族元素，掺杂浓度在1x1019cm-3到1x1021cm-3之间，此时，可以进一步减小所需掺杂氧化硅层厚度。通过进一步减小温补层在整体器件厚度中的占比，可以保持器件的Q值与未增加温补层时基本不变。
在一些实施例中，温补层204设置在至少一个层结构的上表面。可以理解的是，由于温补层204设置在不同结构层上所产生的温补效果不同，与采用热氧法生长的二氧化硅层201必须位于衬底100上表面或者衬底100的下表面相比，本实施例中的温补层204可以设置在薄膜硅层300的上方的至少一个层结构的上表面，这样温补层204的设置位置可以更灵活，从而能够达到理想的温补效果。
请继续参照图1a，在一些实施例中，器件层包括依次层叠设置的压电层500和顶电极600。其中，压电层500可以的材料可以包括PZT、ZnO、AlN以及掺杂AlN等。位于压电层500上方的顶电极600的材料可以为Mo、W、Ru、Al、Cr、Cu、Ti、Pt、Au、Ir、Ta、Rh中的至少一种。
可选的，温补层204可以设置于以下至少一者：例如，温补层204可以设置在压电层500和薄膜硅层300之间、温补层204还可以设置于压电层500和顶电极600之间、温补层204设置于顶电极600的上表面等。通过将温补层204设置在不同的位置，以达到不同的温补效果，因此，温补层204的设置位置具体可根据实际需要进行适应性调整，在此不做具体限制。
在另一些实施例中，温补层204还可以构成至少部分层结构，例如，温补层204设置在顶电极600中，即温补层204作为顶电极600的一部分；或者，温补层204设置于薄膜硅层300中，即温补层204作为薄膜硅层300的一部分；又或者，温补层204设置于压电层500中等。
在一些实施例中，器件层还包括底电极400，底电极400设置于压电层500和薄膜硅层300之间，其中，底电极400的材料也可以为Mo、W、Ru、Al、Cr、Cu、Ti、Pt、Au、Ir、Ta、Rh中的至少一种。
当器件层包括底电极400时，温补层204可以设置于以下至少一者：例如：温补层204位于薄膜硅层300和底电极400之间、温补层204位于底电极400和压电层500之间、温补层204位于压电层500和顶电极600之间或者温补层204位于顶电极600的上表面等，温补层204的设置位置具有可根 据实际需要进行适应性调整，以通过将温补层204设置在不同的位置，达到不同的温补效果，从而提高半导体器件10的稳定性。
在一些实施例中，温补层204设置于顶电极600的上表面，并覆盖至少部分顶电极600，例如，温补层204可以完全覆盖顶电极600，也可以覆盖部分顶电极600，具体可根据需求的温补效果进行调整。
在一些实施例中，换能器结构包括梁结构，温补层204覆盖于梁结构的上表面。示例性的，梁结构包括耦合梁702和至少两个悬臂梁701，悬臂梁701的第一端连接于耦合梁702，第二端为自由端，其中，耦合梁702和悬臂梁701的至少一者覆盖有温补层204，以通过温补层204满足温补效果，提高半导体器件10的稳定性。
图5为一种以悬臂梁701为基础结构的音叉型MEMS谐振器的俯视图；图5中A-A处的剖面示意图可参照图1a；需要说明的是，本申请实施例提供的MEMS谐振器的结构不局限于图5，但其剖面的叠层结构可参照图1a。在图5中，梁结构包括两个悬臂梁701、连接两个悬臂梁701的耦合梁702，耦合梁702的一端设置有支撑结构703，在图5中，温补层204覆盖整个器件的上表面，以满足温补需求，实现零漂温的目的，从而提高半导体器件10的稳定性。
请返回参照图1a，衬底100为带空腔111的单晶硅衬底，衬底100上具有空腔111的一侧设置有用于键合的键合层，其中，键合层可通过热氧法生长在衬底100一侧，其中，键合层的材料可以为二氧化硅，即衬底100的空腔111底壁上具有二氧化硅层201，而在用作器件层的薄膜硅层300的下方不再生长热氧的温补层204，在本申请实施例中，为了实现温补效果，可以在顶电极600上方通过PECVD或CVD等工艺生长掺杂氧化硅层，以形成温补层204，从而满足温补需求，提高半导体器件10的频率温度稳定性。
在一些实施例中，温补层204的上方或者温补层204与顶电极600之间，还可以设置有钝化层或者其它功能层，例如，在温补层204和顶电极600之间设置钝化层，可以通过钝化层使得温补层204与顶电极600之间实现电隔离。
在另一些实施例中，请参照图6至图9，温补层204覆盖悬臂梁701的至少部分表面，例如，温补层204只覆盖悬臂梁701的第一端；或者，温补 层204只覆盖悬臂梁701的部分以及部分耦合梁702；又或者，温补层204覆盖悬臂梁701、耦合梁702以及支撑结构703等，通过使得温补层204覆盖不同的区域，则获得的不同的温补效果，具体可根据实际温补需求进行设置。
在一些实施例中，温补层204设置于梁结构的上表面的第一区域内，其中，第一区域为多个，且多个第一区域在梁结构的上表面呈矩阵分布。示例性的，第一区域可以只覆盖悬臂梁701或者悬臂梁701的部分，或者，第一区域可以覆盖部分或全部悬臂梁701以及部分(或全部)耦合梁702等。
而通过将温补层204进行图形化处理，这样，图形化后的温补层204为多个，且多个温补层204可以在梁结构的上表面呈规则图形阵列排布，例如，呈矩阵分布，并使得温补层204覆盖对应的第一区域，这样，可通过温补层204的排布密度调节半导体器件10的整体温度系数，以满足半导体器件10的温补需求，提高半导体器件10的稳定性。
其中，温补层204可以与第一区域的形状、大小相匹配。
在一些实施例中，请参照图7，温补层204设置于梁结构的上表面的第二区域内，其中，第二区域为多个，且多个第二区域沿梁结构(例如悬臂梁701)的延伸方向(例如悬臂梁701的长度方向)间隔分布。也就是说，图形化后的多个温补层204设置于梁结构的上表面，并沿梁结构(例如悬臂梁701)的延伸方向间隔排布，且温补层204覆盖与其对应的第二区域，这样，可通过温补层204在梁结构的延伸方向上的排布密度调节半导体器件10的整体温度系数，以满足半导体器件10的温补需求，提高半导体器件10的稳定性。
在一些实施例中，可以根据谐振器的应力分布情况图形化温补层204，使其主要覆盖应力较大的区域。例如，对于悬臂梁701式的结构而言，其应力最大区域为第一端的固定端，或者是振幅最小端，其应力沿悬臂梁701的延伸方向逐渐减小，应力最小点为第二端(即自由端)或者振幅最大端，因此，图形化的温补层204使其部分的覆盖悬臂梁701的第一端到第二端的一部分，优选的，如图8所示，温补层204覆盖悬臂梁701的第一端到第二端的总长度的50％，以对半导体器件10的整体温度系数进行调控。
示例性的，由于对于悬臂梁701而言，其应力沿第一端向第二端逐渐减 小，因此，多个第二区域在梁结构(如悬臂梁701)的延伸方向的宽度也可以沿悬臂梁701的第一端至悬臂梁701的第二端逐渐减小，因此，设置在梁结构的上表面的温补层204宽度也从悬臂梁701的第一端至第二端逐渐减小，也就是说，在应力大的区域覆盖温补层204的面积比例大，在应力小的区域覆盖温补层204的面积比例小，如图9中所示。
或者，多个第二区域在梁结构(如悬臂梁701)的延伸方向的分布密度可以沿悬臂梁701的第一端至悬臂梁701的第二端逐渐减小，这样，覆盖在第二区域上的温补层204的分布密度也从悬臂梁701的第一端至第二端逐渐减小，也就是说，在应力大的区域温补层204分布密集，在应力小的区域分布稀疏，从而实现对半导体器件10的整体温度系数的灵活调控，以满足温补需求，提高半导体器件10的稳定性。
请参照图10，在一些实施例中，温补层204位于换能器结构的上表面，同时还可以在薄膜硅层300的下表面通过热氧生长方式形成二氧化硅层201，通过热氧生长方式形成的二氧化硅层201还可以作为衬底100与薄膜硅层300的键合层，以使得衬底100与薄膜硅层300通过键合层进行键合，这样，通过在半导体器件10中设置掺杂的温补层204和通过热氧生长方式形成的二氧化硅层201，可以共同调节半导体器件10的整体温度系数，以满足半导体器件10的温补需求，提高半导体器件10的稳定性。
当然，掺杂氧化硅层的温补层204和通过热氧生长方式获得二氧化硅层201可以任意组合设置在不同位置，只要能够显著的增大半导体器件10的整体温度系数，满足温补效果，提高半导体器件10的稳定性即可，在此不做具体限制。
本申请实施例还提供一种电子设备，包括上述实施例中提供的半导体器件。
本申请实施例提供的半导体器件，包括层叠设置的多个层结构，多个层结构包括依次设置的衬底、薄膜硅层和器件层，薄膜硅层设置于衬底的上表面，器件层设置于薄膜硅层上，且器件层形成换能器结构，至少一个层结构设置有温补层，且在层叠方向上，温补层位于薄膜硅层的上方，其中，温补层为掺杂氧化硅层，温补层的掺杂物包括F、H、CH3、CH2、Cl、C、N、P、S中的至少一种。上述方案中，通过将温补层设置为掺杂氧化硅层，这样，可以 显著的增大温度系数，即可以满足温补效果，提高半导体器件的稳定性；另外，还可以减小温补层的厚度，降低生产成本、提高生产效率，且能使得半导体器件的品质因数Q不降低。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (23)

  1. 一种半导体器件，其特征在于，包括层叠设置的多个层结构，多个所述层结构包括依次设置的衬底、薄膜硅层和器件层，所述衬底具有空腔，所述薄膜硅层设置于所述衬底的上表面，所述器件层设置于所述薄膜硅层上，且所述器件层形成换能器结构；至少一个层结构设置有温补层，且在层叠方向上，所述温补层位于所述薄膜硅层的上方；
    其中，所述温补层为掺杂氧化硅层，所述温补层的掺杂物包括氟、氢、甲基、亚甲基、氯、碳、氮、磷、硫中的至少一种。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述温补层的掺杂物包括氟、氢、甲基、亚甲基、氯、碳、氮、磷、硫中的一种。
  3. 根据权利要求2所述的半导体器件，其特征在于，所述温补层的掺杂物为氟。
  4. 根据权利要求3所述的半导体器件，其特征在于，所述温补层中的氟的分子量百分比为大于或等于3％。
  5. 根据权利要求4所述的半导体器件，其特征在于，所述温补层中的氟的分子量百分比为6％。
  6. 根据权利要求3所述的半导体器件，其特征在于，所述温补层的厚度小于2μm。
  7. 根据权利要求6所述的半导体器件，其特征在于，所述温补层的厚度小于1.5μm。
  8. 根据权利要求1-7中任一项所述的半导体器件，其特征在于，所述温补层设置在至少一个层结构的上表面，或者，所述温补层构成至少部分所述层结构。
  9. 根据权利要求8所述的半导体器件，其特征在于，所述器件层包括依次层叠设置的压电层和顶电极。
  10. 根据权利要求9所述的半导体器件，其特征在于，所述温补层设置于以下至少一者：
    所述压电层和所述薄膜硅层之间、所述压电层和所述顶电极之间、所述顶电极的上表面。
  11. 根据权利要求9所述的半导体器件，其特征在于，所述器件层还包 括底电极，所述底电极设置于所述压电层和所述薄膜硅层之间。
  12. 根据权利要求11所述的半导体器件，其特征在于，所述温补层设置于以下至少一者：
    所述薄膜硅层和所述底电极之间、所述底电极和所述压电层之间、所述压电层和所述顶电极之间、所述顶电极的上表面。
  13. 根据权利要求12所述的半导体器件，其特征在于，所述温补层设置于所述顶电极的上表面，并覆盖至少部分所述顶电极。
  14. 根据权利要求13所述的半导体器件，其特征在于，所述换能器结构包括梁结构，所述温补层覆盖于所述梁结构的上表面。
  15. 根据权利要求14所述的半导体器件，其特征在于，所述梁结构包括耦合梁和至少两个悬臂梁，所述悬臂梁的第一端连接于所述耦合梁，第二端为自由端，其中，所述耦合梁和所述悬臂梁的至少一者覆盖有所述温补层。
  16. 根据权利要求15所述的半导体器件，其特征在于，所述温补层覆盖所述悬臂梁的至少部分表面。
  17. 根据权利要求16所述的半导体器件，其特征在于，所述温补层覆盖所述悬臂梁的第一端。
  18. 根据权利要求16所述的半导体器件，其特征在于，所述温补层设置于所述梁结构的上表面的第一区域内，其中，所述第一区域为多个，且多个所述第一区域在所述梁结构的上表面呈矩阵分布。
  19. 根据权利要求16所述的半导体器件，其特征在于，所述温补层设置于所述梁结构的上表面的第二区域内，其中，所述第二区域为多个，且多个所述第二区域沿所述梁结构的延伸方向间隔分布。
  20. 根据权利要求19所述的半导体器件，其特征在于，多个所述第二区域在所述梁结构的延伸方向的宽度沿所述悬臂梁的第一端至所述悬臂梁的第二端逐渐减小。
  21. 根据权利要求1-7中任一项所述的半导体器件，其特征在于，所述薄膜硅层为N型掺杂硅层，所述薄膜硅层的掺杂物包括磷、砷中的一种，且掺杂浓度为1x1019cm-3～1x1021cm-3。
  22. 根据权利要求1-7中任一项所述的半导体器件，其特征在于，所述薄膜硅层靠近和/或远离所述衬底的一侧设置有热氧二氧化硅层。
  23. 一种电子设备，其特征在于，包括权利要求1-22中任一项所述的半导体器件。
PCT/CN2023/136908 2022-10-21 2023-12-06 半导体器件及电子设备 WO2024083266A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211296632.8 2022-10-21
CN202211296632.8A CN117955450A (zh) 2022-10-21 2022-10-21 半导体器件及电子设备

Publications (1)

Publication Number Publication Date
WO2024083266A1 true WO2024083266A1 (zh) 2024-04-25

Family

ID=90737030

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/136908 WO2024083266A1 (zh) 2022-10-21 2023-12-06 半导体器件及电子设备

Country Status (2)

Country Link
CN (1) CN117955450A (zh)
WO (1) WO2024083266A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6770504B2 (en) * 2003-01-06 2004-08-03 Honeywell International Inc. Methods and structure for improving wafer bow control
CN109831175A (zh) * 2018-12-26 2019-05-31 天津大学 一种薄膜体声波谐振器
CN111010130A (zh) * 2019-12-19 2020-04-14 诺思(天津)微系统有限责任公司 带温补层和电学层的体声波谐振器、滤波器及电子设备
CN114070231A (zh) * 2020-08-03 2022-02-18 诺思(天津)微系统有限责任公司 带温补层的体声波谐振器、滤波器及电子设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6770504B2 (en) * 2003-01-06 2004-08-03 Honeywell International Inc. Methods and structure for improving wafer bow control
CN109831175A (zh) * 2018-12-26 2019-05-31 天津大学 一种薄膜体声波谐振器
CN111010130A (zh) * 2019-12-19 2020-04-14 诺思(天津)微系统有限责任公司 带温补层和电学层的体声波谐振器、滤波器及电子设备
CN114070231A (zh) * 2020-08-03 2022-02-18 诺思(天津)微系统有限责任公司 带温补层的体声波谐振器、滤波器及电子设备

Also Published As

Publication number Publication date
CN117955450A (zh) 2024-04-30

Similar Documents

Publication Publication Date Title
JP4624005B2 (ja) 薄膜バルク音響共鳴器における圧電結合係数を制御して製造される装置
JP7432518B2 (ja) マルチプルレイヤシステム、製造方法およびマルチプルレイヤシステム上に形成されるｓａｗデバイス
CN107317560B (zh) 一种温度补偿表面声波器件及其制备方法
JP6300123B2 (ja) 音響共振器及びその製造方法
US20170288121A1 (en) Acoustic resonator including composite polarity piezoelectric layer having opposite polarities
Pan et al. Thin-film piezoelectric-on-substrate resonators with Q enhancement and TCF reduction
US7586239B1 (en) MEMS vibrating structure using a single-crystal piezoelectric thin film layer
CN105556840A (zh) 振动装置及其制造方法
CN111262543A (zh) 一种钪掺杂氮化铝兰姆波谐振器与制备方法
CN112134540B (zh) 一种复合电极的体声波谐振器及其制备方法
US20070284971A1 (en) Electronic device
CN106233626B (zh) 具有高耦合系数的温度补偿体声波谐振器
US20150180449A1 (en) Vibrating device and manufacturing method therfor
JP2002094356A (ja) 表面弾性波フィルター及びその製造方法
WO2013185737A2 (zh) 一种温度补偿能力可调节的压电声波谐振器
WO2022143286A1 (zh) 单晶体声波谐振器、滤波器及电子设备
WO2024169075A1 (zh) 声表面波器件及其制造方法
CN114726334B (zh) 一种声波谐振器及其制造方法
JPH10270978A (ja) 表面弾性波素子及びその製造方法
WO2024083266A1 (zh) 半导体器件及电子设备
US4501987A (en) Surface acoustic wave transducer using a split-finger electrode on a multi-layered substrate
CN212163290U (zh) 一种钪掺杂氮化铝兰姆波谐振器
JP3838359B2 (ja) 音響信号または熱信号と電圧変化とを互いに変換するための層配列を備えた半導体素子、および、その製造方法
CN113301484A (zh) 一种mems结构及其制造方法
WO2024061051A1 (zh) 带有声子晶体的横向激励体声波谐振器及制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23879249

Country of ref document: EP

Kind code of ref document: A1