WO2024082820A1 - Low-noise amplifier and radio-frequency chip - Google Patents

Low-noise amplifier and radio-frequency chip Download PDF

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Publication number
WO2024082820A1
WO2024082820A1 PCT/CN2023/115042 CN2023115042W WO2024082820A1 WO 2024082820 A1 WO2024082820 A1 WO 2024082820A1 CN 2023115042 W CN2023115042 W CN 2023115042W WO 2024082820 A1 WO2024082820 A1 WO 2024082820A1
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Prior art keywords
transistor
switch
gate
source
drain
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PCT/CN2023/115042
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French (fr)
Chinese (zh)
Inventor
胡杨君
郭嘉帅
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深圳飞骧科技股份有限公司
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Publication of WO2024082820A1 publication Critical patent/WO2024082820A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present invention relates to the field of amplifier circuits, and in particular to a low noise amplifier and a radio frequency chip.
  • the RF low noise amplifier is one of the important components.
  • the low noise amplifier amplifies the signal.
  • the performance of the low noise amplifier directly affects the overall performance of the receiver, such as gain, power consumption, noise figure, linearity and area, etc.
  • the gain of the low noise amplifier is an important performance indicator.
  • the low-noise amplifier of the related technology includes an input matching network circuit, a first capacitor, a first transistor, a second transistor and an output matching network circuit, wherein the input end of the input matching network circuit serves as the input end of the low-noise amplifier; the output end of the input matching network circuit is connected in series with the first capacitor and then connected to the gate of the first transistor; the source of the first transistor is grounded; the drain of the first transistor is connected to the source of the second transistor; the drain of the second transistor is connected to the input end of the output matching network circuit, and the output end of the output matching network circuit serves as the output end of the low-noise amplifier.
  • the first crystal and the second transistor of the low noise amplifier of the related art generally use MOS tubes.
  • the low noise amplifier is often required to have the function of gain adjustment. How to generate an accurate gain gear difference is also very important.
  • the gate length of MOS tubes is getting smaller and smaller, and its various performances are more and more sensitive to the bias voltage. How to adjust the bias voltage of the low noise amplifier and provide a stable and adjustable bias structure to meet the needs of different scenarios is a technical problem that needs to be solved.
  • the present invention proposes a low-noise amplifier and a radio frequency chip that can adjust the bias of the amplifier and have little effect of process deviation.
  • an embodiment of the present invention provides a low-noise amplifier, which includes an input matching network circuit, a first capacitor, a first transistor, a second transistor and an output matching network circuit, wherein the input end of the input matching network circuit serves as the input end of the low-noise amplifier; the output end of the input matching network circuit is connected in series with the first capacitor and then connected to the gate of the first transistor; the source of the first transistor is grounded; the drain of the first transistor is connected to the source of the second transistor; the drain of the second transistor is connected to the input end of the output matching network circuit, and the output end of the output matching network circuit serves as the output end of the low-noise amplifier; wherein the input matching network circuit is used for impedance matching of the input end of the low-noise amplifier, and the output matching network circuit is used for impedance matching of the output end of the low-noise amplifier;
  • the low noise amplifier further comprises an adjustable common source bias circuit disposed between the gate of the first transistor and the first capacitor and an adjustable common gate bias circuit connected to the gate of the second transistor;
  • the adjustable common source bias circuit is used to control the magnitude of the output current according to a preset ratio of the received external current source current through the received first control signal, and generate a corresponding first output voltage from the output current;
  • the adjustable common-gate bias circuit is used to pass the received current source current through a plurality of resistors connected in series, and then control the number of the resistors through which the current source current passes through by a received second control signal to generate a corresponding second output voltage.
  • both the first transistor and the second transistor are MOS transistors.
  • the adjustable common source bias circuit includes a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch and a second capacitor;
  • the drain of the fifth transistor serves as the input terminal of the adjustable common-source bias circuit. and the drain of the fifth transistor is connected to the gate of the fifth transistor and the gate of the sixth transistor respectively; the input end of the adjustable common source bias circuit is used to receive the current of the current source;
  • the source of the fifth transistor and the source of the sixth transistor are both grounded;
  • the drain of the sixth transistor is respectively connected to the drain of the seventh transistor, the gate of the seventh transistor, the gate of the eighth transistor, the first end of the first switch, the first end of the third switch and the first end of the fifth switch;
  • a source of the seventh transistor, a source of the eighth transistor, a source of the ninth transistor, a source of the tenth transistor, a source of the eleventh transistor, a first end of the second switch, a first end of the fourth switch, and a first end of the sixth switch are all connected to a power supply voltage;
  • the second end of the first switch is connected to the second end of the second switch and the gate of the ninth transistor respectively;
  • the second end of the third switch is connected to the second end of the fourth switch and the gate of the tenth transistor respectively;
  • the second end of the fifth switch is connected to the second end of the sixth switch and the gate of the eleventh transistor respectively;
  • the control end of the first switch, the control end of the second switch, the control end of the third switch, the control end of the fourth switch, the control end of the fifth switch and the control end of the sixth switch are all used to connect the first control signal;
  • the drain of the eighth transistor serves as the output end of the adjustable common-source bias circuit, and the drain of the eighth transistor is respectively connected to the drain of the ninth transistor, the drain of the tenth transistor, the drain of the eleventh transistor, the drain of the third transistor, the gate of the third transistor and the first end of the second capacitor;
  • a source of the third transistor and a second end of the second capacitor are both grounded.
  • the third transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor and the eleventh transistor are all MOS transistors.
  • the width-to-length ratio of the third transistor is the same as the width-to-length ratio of the first transistor.
  • the adjustable common source bias circuit further includes an mth transistor, an hth switch and an h+1th switch, wherein m is a positive integer greater than 16, and h is a positive integer greater than 7;
  • the first end of the hth switch is connected to the first end of the first switch
  • the source of the mth transistor is connected to the first terminal of the h+1th switch and the power supply voltage respectively;
  • the gate of the mth transistor is connected to the second end of the hth switch and the second end of the h+1th switch respectively;
  • a drain of the mth transistor is connected to a drain of the third transistor.
  • the adjustable common-gate bias circuit includes a fourth transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a first resistor, an nth resistor, an n+1th resistor, an n+2th resistor, a first transmission gate, an nth transmission gate, an n+1th transmission gate, and an n+2th transmission gate; wherein n is a positive integer greater than 2;
  • the drain of the twelfth transistor serves as an input terminal of the adjustable common-gate bias circuit, and the drain of the twelfth transistor is respectively connected to the gate of the twelfth transistor and the gate of the thirteenth transistor; the input terminal of the adjustable common-gate bias circuit is used to receive the current of the current source;
  • the source of the twelfth transistor and the source of the thirteenth transistor are both grounded;
  • the drain of the thirteenth transistor is connected to the drain of the fourteenth transistor, the gate of the fourteenth transistor and the gate of the fifteenth transistor respectively;
  • the source of the fourteenth transistor and the source of the fifteenth transistor are both connected to a power supply voltage
  • the drain of the fifteenth transistor is connected to the drain of the fourth transistor and the gate of the fourth transistor respectively by sequentially connecting the first resistor, the nth resistor, the n+1th resistor and the n+2th resistor in series;
  • the source of the fourth transistor is grounded
  • the first end of the first transmission gate is connected to the second end of the first resistor, and the control end of the first transmission gate is used to connect to the second control signal;
  • the first end of the nth transmission gate is connected to the second end of the nth resistor, and the control end of the nth transmission gate is used to connect to the second control signal;
  • the first end of the n+1th transmission gate is connected to the second end of the n+1th resistor, and the control end of the n+1th transmission gate is used to connect the second control signal;
  • the first end of the n+2 th transmission gate is connected to the second end of the n+2 th resistor, and the control end of the n+2 th transmission gate is used to connect to the second control signal;
  • the second end of the first transmission gate serves as the output end of the adjustable common-gate bias circuit, and the second end of the first transmission gate is respectively connected to the second end of the nth transmission gate, the second end of the n+1th transmission gate and the second end of the n+2th transmission gate.
  • the fourth transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are all MOS transistors.
  • the width-to-length ratio of the fourth transistor is the same as the width-to-length ratio of the second transistor.
  • an embodiment of the present invention further provides a radio frequency chip, wherein the radio frequency chip includes the above-mentioned low noise amplifier provided by the embodiment of the present invention.
  • the low noise amplifier and the radio frequency chip of the present invention are used to control the size of the output current according to a preset ratio of the received external current source current through the adjustable common source bias circuit through the received first control signal, and generate the corresponding first output voltage from the output current.
  • the low noise amplifier and the radio frequency chip of the present invention are also used to pass the received current source current through a plurality of resistors connected in series through the adjustable common gate bias circuit, and then control the number of the current source current passing through the resistors through the received second control signal to generate the corresponding second output voltage.
  • the circuit structure adjusts the bias of the amplifier through the first output voltage and the second output voltage.
  • the first output voltage and the second output voltage can be appropriately increased; when the gain gear difference designed in the circuit of the low noise amplifier and the radio frequency chip of the present invention can avoid uncontrollable factors such as process manufacturing, and cause the actual current to be inaccurate with the design requirements, the performance of reducing the influence of process deviation can also be achieved by adjusting the first output voltage and the second output voltage of different sizes. Therefore, the bias of the amplifier can be adjusted by using the low noise amplifier and the radio frequency chip of the present invention, and the influence of process deviation is small.
  • FIG1 is a circuit diagram of a low noise amplifier of the related art
  • FIG2 is a circuit diagram of an adjustable common-source bias circuit of a low-noise amplifier in the related art
  • FIG3 is a circuit diagram of an adjustable common-gate bias circuit of a low noise amplifier according to an embodiment of the present invention.
  • the present invention provides a low noise amplifier 100.
  • Fig. 1 is a circuit structure diagram of the low noise amplifier 100 according to an embodiment of the present invention.
  • the low noise amplifier 100 includes an input matching network circuit 1 , a first capacitor C1 , a first transistor M1 , a second transistor M2 , an output matching network circuit 2 , an adjustable common source bias circuit 3 , and an adjustable common gate bias circuit 4 .
  • both the first transistor M1 and the second transistor M2 are MOS transistors.
  • the internal connection relationship of the low noise amplifier 100 is:
  • the input end of the input matching network circuit 1 serves as the input end of the low noise amplifier 100 .
  • the output end of the input matching network circuit 1 is connected in series with the first capacitor C1 and then connected to the gate of the first transistor M1 .
  • the source of the first transistor is connected to the ground GND.
  • the drain of the first transistor M1 is connected to the source of the second transistor M2.
  • a drain of the second transistor M2 is connected to an input end of the output matching network circuit 2 .
  • the output end of the output matching network circuit 2 serves as the output end of the low noise amplifier 100 .
  • the adjustable common-source bias circuit 3 is disposed between the gate of the first transistor M1 and the first capacitor C1 .
  • the adjustable common-gate bias circuit 4 is connected to the gate of the second transistor M2.
  • the input matching network circuit 1 is used for impedance matching of the input end of the low noise amplifier 100.
  • the input matching network circuit 1 is a commonly used circuit in the art. Of course, it is not limited thereto, and the input matching network circuit 1 may be removed if the design requires it.
  • the output matching network circuit 2 is used for impedance matching of the output end of the low noise amplifier 100.
  • the output matching network circuit 2 is a commonly used circuit in the art. Of course, it is not limited thereto, and the output matching network circuit 2 may be removed if the design requires it.
  • the adjustable common source bias circuit 3 is used to control the size of the output current according to a preset ratio of the received external current source current IPTAT through the received first control signal S1, and generate a corresponding first output voltage VCS from the output current.
  • the output current is the current output from the output end of the adjustable common source bias circuit 3.
  • FIG. 2 is a circuit diagram of an adjustable common source bias circuit 3 of a low noise amplifier 100 in the related art.
  • the adjustable common source bias circuit 3 includes a third transistor M3, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6 and a second capacitor C2.
  • the internal circuit connection relationship of the adjustable common source bias circuit 3 is:
  • the drain of the fifth transistor M5 serves as the input terminal of the adjustable common source bias circuit 3, and the drain of the fifth transistor M5 is respectively connected to the gate of the fifth transistor M5 and the gate of the sixth transistor M6.
  • the input terminal of the adjustable common source bias circuit 3 is used to receive the current source current IPTAT.
  • a source of the fifth transistor M5 and a source of the sixth transistor M6 are both connected to the ground GND.
  • the drain of the sixth transistor M6 is respectively connected to the drain of the seventh transistor M7, the gate of the seventh transistor M7, the gate of the eighth transistor M8, the first end of the first switch K1, the first end of the third switch K3 and the first end of the fifth switch K5.
  • a source of the seventh transistor M7, a source of the eighth transistor M8, a source of the ninth transistor M9, a source of the tenth transistor M10, a source of the eleventh transistor M11, a first end of the second switch K2, a first end of the fourth switch K4, and a first end of the sixth switch K6 are all connected to a power supply voltage VCC.
  • the second end of the first switch K1 is connected to the second end of the second switch K2 and the gate of the ninth transistor M9 respectively.
  • the second end of the third switch K3 is connected to the second end of the fourth switch K4 and the gate of the tenth transistor M10 respectively.
  • the second end of the fifth switch K5 is connected to the second end of the sixth switch K6 and the gate of the eleventh transistor M11 , respectively.
  • the control ends of the first switch K1 , the second switch K2 , the third switch K3 , the fourth switch K4 , the fifth switch K5 and the sixth switch K6 are all used to connect to the first control signal S1 .
  • the drain of the eighth transistor M8 serves as the input of the adjustable common source bias circuit 3.
  • the output terminal is connected to the drain of the ninth transistor M9, the drain of the tenth transistor M10, the drain of the eleventh transistor M11, the drain of the third transistor M3, the gate of the third transistor M3 and the first terminal of the second capacitor C2.
  • a source of the third transistor M3 and a second end of the second capacitor C2 are both grounded GND.
  • the adjustable common source bias circuit 3 also includes an mth transistor Mm, an hth switch Kh and an h+1th switch Kh+1, wherein m is a positive integer greater than 16, and h is a positive integer greater than 7.
  • the first end of the hth switch Kh is connected to the first end of the first switch K1.
  • the source of the mth transistor Mm is respectively connected to the first end of the h+1th switch Kh+1 and the power supply voltage VCC.
  • the gate of the mth transistor Mm is respectively connected to the second end of the hth switch Kh and the second end of the h+1th switch Kh+1.
  • the drain of the mth transistor Mm is connected to the drain of the third transistor M3.
  • the working principle of the adjustable common source bias circuit 3 is:
  • the current source current IPTAT flows into the current mirror composed of the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11.
  • the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 are all MOS transistors, and the subsequent m-th transistor Mm replicates the current source current IPTAT in different proportions, that is, each transistor forms a branch.
  • the gate of the MOS transistor of each branch is connected to a series switch and a parallel switch, and the control signals are opposite to determine the on and off of the branch.
  • the first control signal S1 is a bus, and the first control signal S1 includes multiple control signals.
  • the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 are all MOS transistors.
  • the width-to-length ratio of the third transistor M3 and the The first transistors M1 have the same width-to-length ratio. This configuration can maximize the avoidance of the impact of process manufacturing deviations, thereby minimizing the process impact of the low noise amplifier 100.
  • the adjustable common-gate bias circuit 4 is used to pass the received current source current IPTAT through a plurality of resistors connected in series, and then control the number of resistors through which the current source current IPTAT passes through to generate a corresponding second output voltage VCG through the received second control signal S2.
  • the second output voltage VCG can be appropriately increased; when the gain gear difference designed in the circuit of the low-noise amplifier 100 of the present invention can avoid uncontrollable factors such as process manufacturing, and cause the actual current to be inaccurate with the design requirements, the performance of reducing the influence of process deviation can also be achieved by adjusting the second output voltage VCG of different sizes.
  • FIG. 3 is a circuit diagram of an adjustable common-gate bias circuit 4 of a low-noise amplifier 100 according to an embodiment of the present invention.
  • the adjustable common-gate bias circuit 4 includes a fourth transistor M4, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a first resistor R1, an nth resistor Rn, an n+1th resistor Rn+1, an n+2th resistor Rn+2, a first transmission gate TG1, an nth transmission gate TGn, an n+1th transmission gate TGn+1, and an n+2th transmission gate TGn+2.
  • n is a positive integer greater than 2.
  • the internal circuit connection relationship of the adjustable common-gate bias circuit 4 is:
  • the drain of the twelfth transistor M12 serves as the input terminal of the adjustable common-gate bias circuit 4, and the drain of the twelfth transistor M12 is respectively connected to the gate of the twelfth transistor M12 and the gate of the thirteenth transistor M13.
  • the input terminal of the adjustable common-gate bias circuit 4 is used to receive the current source current IPTAT.
  • a source of the twelfth transistor M12 and a source of the thirteenth transistor M13 are both connected to the ground GND.
  • the drain of the thirteenth transistor M13 is connected to the drain of the fourteenth transistor M14, the gate of the fourteenth transistor M14 and the gate of the fifteenth transistor M15, respectively.
  • a source of the fourteenth transistor M14 and a source of the fifteenth transistor M15 are both connected to a power supply voltage VCC.
  • the drain of the fifteenth transistor M15 is connected to the drain of the fourth transistor M4 and the gate of the fourth transistor M4 respectively by sequentially connecting the first resistor R1, the nth resistor Rn, the n+1th resistor Rn+1 and the n+2th resistor Rn+2 in series.
  • a source of the fourth transistor M4 is connected to the ground GND.
  • a first end of the first transmission gate TG1 is connected to a second end of the first resistor R1 , and a control end of the first transmission gate TG1 is used to connect to the second control signal S2 .
  • a first end of the nth transmission gate TGn is connected to a second end of the nth resistor Rn, and a control end of the nth transmission gate TGn is used to connect to the second control signal S2.
  • a first end of the n+1th transmission gate TGn+1 is connected to a second end of the n+1th resistor Rn+1, and a control end of the n+1th transmission gate TGn+1 is used to connect to the second control signal S2.
  • a first end of the n+2 th transmission gate TGn+2 is connected to a second end of the n+2 th resistor Rn+2, and a control end of the n+2 th transmission gate TGn+2 is used to connect to the second control signal S2.
  • the second end of the first transmission gate TG1 serves as the output end of the adjustable common-gate bias circuit 4, and the second end of the first transmission gate TG1 is respectively connected to the second end of the nth transmission gate TGn, the second end of the n+1th transmission gate TGn+1, and the second end of the n+2th transmission gate TGn+2.
  • the working principle of the adjustable common-gate bias circuit 4 is:
  • the current source current IPTAT flows into the current mirror composed of the fourth transistor M4, the fourth transistor M4, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15.
  • N resistors of equal size are inserted between the fifteenth transistor M15 and the fourth transistor M4, so that N voltage levels can be determined.
  • Each voltage level is followed by a transmission gate, and the second control signal S2 is used to select the final second output voltage VCG by turning the transmission gate on and off. That is, a voltage is drawn out under each resistor, and each voltage is followed by a transmission gate.
  • the second control signal S2 that controls the transmission gate determines which voltage provides bias for the second transistor M2.
  • the fourth transistor M4, the twelfth transistor M12, The thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 are all MOS transistors.
  • the width-to-length ratio of the fourth transistor M4 is the same as the width-to-length ratio of the second transistor M2. This setting can maximize the avoidance of the influence of process manufacturing deviation, thereby minimizing the process influence of the low noise amplifier 100.
  • An embodiment of the present invention further provides a radio frequency chip, wherein the radio frequency chip includes the low noise amplifier 100 .
  • the low noise amplifier and the radio frequency chip of the present invention are used to control the size of the output current according to a preset ratio of the received external current source current through the adjustable common source bias circuit through the received first control signal, and generate the corresponding first output voltage from the output current.
  • the low noise amplifier and the radio frequency chip of the present invention are also used to pass the received current source current through a plurality of resistors connected in series through the adjustable common gate bias circuit, and then control the number of the current source current passing through the resistors through the received second control signal to generate the corresponding second output voltage.
  • the circuit structure adjusts the bias of the amplifier through the first output voltage and the second output voltage.
  • the first output voltage and the second output voltage can be appropriately increased; when the gain gear difference designed in the circuit of the low noise amplifier and the radio frequency chip of the present invention can avoid uncontrollable factors such as process manufacturing, and cause the actual current to be inaccurate with the design requirements, the performance of reducing the influence of process deviation can also be achieved by adjusting the first output voltage and the second output voltage of different sizes. Therefore, the bias of the amplifier can be adjusted by using the low noise amplifier and the radio frequency chip of the present invention, and the influence of process deviation is small.

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Abstract

The present invention provides a low-noise amplifier and a radio-frequency chip. The low-noise amplifier comprises an input matching network circuit, a first capacitor, a first transistor, a second transistor, an output matching network circuit, an adjustable common-source bias circuit arranged between a gate of the first transistor and the first capacitor, and an adjustable common-gate bias circuit connected to a gate of the second transistor. The adjustable common-source bias circuit is used for controlling the magnitude of an output current according to a preset proportion by using the received current of an external current source by means of a received first control signal, and generating a corresponding first output voltage from the output current. The adjustable common-gate bias circuit is used for enabling the received current of the current source to pass through a plurality of resistors which are connected in series, and then by means of a received second control signal, controlling the number of resistors that the current of the current source passes through, so as to generate a corresponding second output voltage. According to the technical solution of the present invention, the bias of the amplifier can be adjusted, and the process deviation influence is small.

Description

低噪声放大器和射频芯片Low noise amplifier and RF chip 技术领域Technical Field
本发明涉及放大器电路领域，尤其涉及一种低噪声放大器和射频芯片。The present invention relates to the field of amplifier circuits, and in particular to a low noise amplifier and a radio frequency chip.
背景技术Background technique
目前，在无线收发系统中，射频的低噪声放大器是重要的组成部分之一，低噪声放大器将信号进行放大，低噪声放大器作为接收机中关键的一环，其性能直接影响接收机整体的性能，例如增益、功耗、噪声系数、线性度以及面积等。其中，低噪声放大器的增益为重要的性能指标。At present, in wireless transceiver systems, the RF low noise amplifier is one of the important components. The low noise amplifier amplifies the signal. As a key part of the receiver, the performance of the low noise amplifier directly affects the overall performance of the receiver, such as gain, power consumption, noise figure, linearity and area, etc. Among them, the gain of the low noise amplifier is an important performance indicator.
相关技术的低噪声放大器包括输入匹配网络电路、第一电容、第一晶体管、第二晶体管以及输出匹配网络电路，所述输入匹配网络电路的输入端作为所述低噪声放大器的输入端；所述输入匹配网络电路的输出端串联所述第一电容后连接至所述第一晶体管的栅极；所述第一晶体的源极接地；所述第一晶体管的漏极连接至所述第二晶体管的源极；所述第二晶体管的漏极连接至所述输出匹配网络电路的输入端，所述输出匹配网络电路的输出端作为所述低噪声放大器的输出端。The low-noise amplifier of the related technology includes an input matching network circuit, a first capacitor, a first transistor, a second transistor and an output matching network circuit, wherein the input end of the input matching network circuit serves as the input end of the low-noise amplifier; the output end of the input matching network circuit is connected in series with the first capacitor and then connected to the gate of the first transistor; the source of the first transistor is grounded; the drain of the first transistor is connected to the source of the second transistor; the drain of the second transistor is connected to the input end of the output matching network circuit, and the output end of the output matching network circuit serves as the output end of the low-noise amplifier.
然而，相关技术的低噪声放大器的所述第一晶体和所述第二晶体管一般采用MOS管，在智能终端应用中，为应对来自天线的不同强度的信号，常常要求低噪声放大器具有增益调节的功能，如何生成一个精确的增益档位差也很重要。且随着工艺的进步，MOS管栅长越来越小，其各种性能对偏置电压的反应越来越敏感。如何对低噪声放大器的对偏置电压进行调节，并提供一种稳定的、可调节的偏置结构来应对不同情景的需求是一个需要解决的技术问题。However, the first crystal and the second transistor of the low noise amplifier of the related art generally use MOS tubes. In the application of smart terminals, in order to cope with signals of different strengths from the antenna, the low noise amplifier is often required to have the function of gain adjustment. How to generate an accurate gain gear difference is also very important. And with the advancement of technology, the gate length of MOS tubes is getting smaller and smaller, and its various performances are more and more sensitive to the bias voltage. How to adjust the bias voltage of the low noise amplifier and provide a stable and adjustable bias structure to meet the needs of different scenarios is a technical problem that needs to be solved.
因此，实有必要提供一种新的低噪声放大器和芯片解决上述问题。 Therefore, it is necessary to provide a new low noise amplifier and chip to solve the above problems.
发明内容Summary of the invention
针对以上现有技术的不足，本发明提出一种可调节放大器的偏置且工艺偏差影响小的低噪声放大器和射频芯片。In view of the above deficiencies in the prior art, the present invention proposes a low-noise amplifier and a radio frequency chip that can adjust the bias of the amplifier and have little effect of process deviation.
为了解决上述技术问题，第一方面，本发明的实施例提供了一种低噪声放大器，其包括输入匹配网络电路、第一电容、第一晶体管、第二晶体管以及输出匹配网络电路，所述输入匹配网络电路的输入端作为所述低噪声放大器的输入端；所述输入匹配网络电路的输出端串联所述第一电容后连接至所述第一晶体管的栅极；所述第一晶体的源极接地；所述第一晶体管的漏极连接至所述第二晶体管的源极；所述第二晶体管的漏极连接至所述输出匹配网络电路的输入端，所述输出匹配网络电路的输出端作为所述低噪声放大器的输出端；其中，所述输入匹配网络电路用于所述低噪声放大器的输入端的阻抗匹配，所述输出匹配网络电路用于所述低噪声放大器的输出端的阻抗匹配；In order to solve the above technical problems, in the first aspect, an embodiment of the present invention provides a low-noise amplifier, which includes an input matching network circuit, a first capacitor, a first transistor, a second transistor and an output matching network circuit, wherein the input end of the input matching network circuit serves as the input end of the low-noise amplifier; the output end of the input matching network circuit is connected in series with the first capacitor and then connected to the gate of the first transistor; the source of the first transistor is grounded; the drain of the first transistor is connected to the source of the second transistor; the drain of the second transistor is connected to the input end of the output matching network circuit, and the output end of the output matching network circuit serves as the output end of the low-noise amplifier; wherein the input matching network circuit is used for impedance matching of the input end of the low-noise amplifier, and the output matching network circuit is used for impedance matching of the output end of the low-noise amplifier;
所述低噪声放大器还包括设置于所述第一晶体管的栅极与所述第一电容之间的可调共源偏置电路和与所述第二晶体管的栅极连接的可调共栅偏置电路；The low noise amplifier further comprises an adjustable common source bias circuit disposed between the gate of the first transistor and the first capacitor and an adjustable common gate bias circuit connected to the gate of the second transistor;
所述可调共源偏置电路用于通过接收的第一控制信号将接收的外部的电流源电流根据预设的比例控制输出电流的大小，并将所述输出电流生成相应的第一输出电压；The adjustable common source bias circuit is used to control the magnitude of the output current according to a preset ratio of the received external current source current through the received first control signal, and generate a corresponding first output voltage from the output current;
所述可调共栅偏置电路用于将接收的所述电流源电流通过多个串联的电阻，再通过接收的第二控制信号控制所述电流源电流通过所述电阻的个数以生成相应的第二输出电压。The adjustable common-gate bias circuit is used to pass the received current source current through a plurality of resistors connected in series, and then control the number of the resistors through which the current source current passes through by a received second control signal to generate a corresponding second output voltage.
优选的，所述第一晶体管和所述第二晶体管均为MOS管。Preferably, both the first transistor and the second transistor are MOS transistors.
优选的，所述可调共源偏置电路包括第三晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第一开关、第二开关、第三开关、第四开关、第五开关、第六开关以及第二电容；Preferably, the adjustable common source bias circuit includes a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch and a second capacitor;
所述第五晶体管的漏极作为所述可调共源偏置电路的输入端， 且所述第五晶体管的漏极分别连接至所述第五晶体管的栅极和所述第六晶体管的栅极；所述可调共源偏置电路的输入端用于接收的所述电流源电流；The drain of the fifth transistor serves as the input terminal of the adjustable common-source bias circuit. and the drain of the fifth transistor is connected to the gate of the fifth transistor and the gate of the sixth transistor respectively; the input end of the adjustable common source bias circuit is used to receive the current of the current source;
所述第五晶体管的源极和所述第六晶体管的源极均接地；The source of the fifth transistor and the source of the sixth transistor are both grounded;
所述第六晶体管的漏极分别连接至所述第七晶体管的漏极、所述第七晶体管的栅极、所述第八晶体管的栅极、所述第一开关的第一端、所述第三开关的第一端以及所述第五开关的第一端；The drain of the sixth transistor is respectively connected to the drain of the seventh transistor, the gate of the seventh transistor, the gate of the eighth transistor, the first end of the first switch, the first end of the third switch and the first end of the fifth switch;
所述第七晶体管的源极、所述第八晶体管的源极、所述第九晶体管的源极、所述第十晶体管的源极、所述第十一晶体管的源极、所述第二开关的第一端、所述第四开关的第一端以及所述第六开关的第一端均连接至电源电压；A source of the seventh transistor, a source of the eighth transistor, a source of the ninth transistor, a source of the tenth transistor, a source of the eleventh transistor, a first end of the second switch, a first end of the fourth switch, and a first end of the sixth switch are all connected to a power supply voltage;
所述第一开关的第二端分别连接至所述第二开关的第二端和所述第九晶体管的栅极；The second end of the first switch is connected to the second end of the second switch and the gate of the ninth transistor respectively;
所述第三开关的第二端分别连接至所述第四开关的第二端和所述第十晶体管的栅极；The second end of the third switch is connected to the second end of the fourth switch and the gate of the tenth transistor respectively;
所述第五开关的第二端分别连接至所述第六开关的第二端和所述第十一晶体管的栅极；The second end of the fifth switch is connected to the second end of the sixth switch and the gate of the eleventh transistor respectively;
所述第一开关的控制端、所述第二开关的控制端、所述第三开关的控制端、所述第四开关的控制端、所述第五开关的控制端以及所述第六开关的控制端均用于连接所述第一控制信号；The control end of the first switch, the control end of the second switch, the control end of the third switch, the control end of the fourth switch, the control end of the fifth switch and the control end of the sixth switch are all used to connect the first control signal;
所述第八晶体管的漏极作为所述可调共源偏置电路的输出端，且所述第八晶体管的漏极分别连接至所述第九晶体管的漏极、所述第十晶体管的漏极、所述第十一晶体管的漏极、所述第三晶体管的漏极、所述第三晶体管的栅极以及所述第二电容的第一端；The drain of the eighth transistor serves as the output end of the adjustable common-source bias circuit, and the drain of the eighth transistor is respectively connected to the drain of the ninth transistor, the drain of the tenth transistor, the drain of the eleventh transistor, the drain of the third transistor, the gate of the third transistor and the first end of the second capacitor;
所述第三晶体管的源极和所述第二电容的第二端均接地。A source of the third transistor and a second end of the second capacitor are both grounded.
优选的，所述第三晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管、所述第九晶体管、所述第十晶体管以及所述第十一晶体管均为MOS管。Preferably, the third transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor and the eleventh transistor are all MOS transistors.
优选的，所述第三晶体管的宽长比和所述第一晶体管的宽长比相同。 Preferably, the width-to-length ratio of the third transistor is the same as the width-to-length ratio of the first transistor.
优选的，所述可调共源偏置电路还包括第m晶体管、第h开关和第h+1开关，其中，m为大于16的正整数，h为大于7的正整数；Preferably, the adjustable common source bias circuit further includes an mth transistor, an hth switch and an h+1th switch, wherein m is a positive integer greater than 16, and h is a positive integer greater than 7;
所述第h开关的第一端连接至所述第一开关的第一端；The first end of the hth switch is connected to the first end of the first switch;
所述第m晶体管的源极分别连接至所述第h+1开关的第一端和电源电压；The source of the mth transistor is connected to the first terminal of the h+1th switch and the power supply voltage respectively;
所述第m晶体管的栅极分别连接至所述第h开关的第二端和所述第h+1开关的第二端；The gate of the mth transistor is connected to the second end of the hth switch and the second end of the h+1th switch respectively;
所述第m晶体管的漏极连接至所述第三晶体管的漏极。A drain of the mth transistor is connected to a drain of the third transistor.
优选的，所述可调共栅偏置电路包括第四晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第一电阻、第n电阻、第n+1电阻、第n+2电阻、第一传输门、第n传输门、第n+1传输门以及第n+2传输门；其中，n为大于2的正整数；Preferably, the adjustable common-gate bias circuit includes a fourth transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a first resistor, an nth resistor, an n+1th resistor, an n+2th resistor, a first transmission gate, an nth transmission gate, an n+1th transmission gate, and an n+2th transmission gate; wherein n is a positive integer greater than 2;
所述第十二晶体管的漏极作为所述可调共栅偏置电路的输入端，且所述第十二晶体管的漏极分别连接至所述第十二晶体管的栅极和所述第十三晶体管的栅极；所述可调共栅偏置电路的输入端用于接收的所述电流源电流；The drain of the twelfth transistor serves as an input terminal of the adjustable common-gate bias circuit, and the drain of the twelfth transistor is respectively connected to the gate of the twelfth transistor and the gate of the thirteenth transistor; the input terminal of the adjustable common-gate bias circuit is used to receive the current of the current source;
所述第十二晶体管的源极和所述第十三晶体管的源极均接地；The source of the twelfth transistor and the source of the thirteenth transistor are both grounded;
所述第十三晶体管的漏极分别连接至所述第十四晶体管的漏极、所述第十四晶体管的栅极以及所述第十五晶体管的栅极；The drain of the thirteenth transistor is connected to the drain of the fourteenth transistor, the gate of the fourteenth transistor and the gate of the fifteenth transistor respectively;
所述第十四晶体管的源极和所述第十五晶体管的源极均连接至电源电压；The source of the fourteenth transistor and the source of the fifteenth transistor are both connected to a power supply voltage;
所述第十五晶体管的漏极通过依次串联所述第一电阻、所述第n电阻、所述第n+1电阻和所述第n+2电阻后分别连接至所述第四晶体管的漏极和所述第四晶体管的栅极；The drain of the fifteenth transistor is connected to the drain of the fourth transistor and the gate of the fourth transistor respectively by sequentially connecting the first resistor, the nth resistor, the n+1th resistor and the n+2th resistor in series;
所述第四晶体管的源极接地；The source of the fourth transistor is grounded;
所述第一传输门的第一端连接至所述第一电阻的第二端，所述第一传输门的控制端用于连接所述第二控制信号；The first end of the first transmission gate is connected to the second end of the first resistor, and the control end of the first transmission gate is used to connect to the second control signal;
所述第n传输门的第一端连接至所述第n电阻的第二端，所述第n传输门的控制端用于连接所述第二控制信号； The first end of the nth transmission gate is connected to the second end of the nth resistor, and the control end of the nth transmission gate is used to connect to the second control signal;
所述第n+1传输门的第一端连接至所述第n+1电阻的第二端，所述第n+1传输门的控制端用于连接所述第二控制信号；The first end of the n+1th transmission gate is connected to the second end of the n+1th resistor, and the control end of the n+1th transmission gate is used to connect the second control signal;
所述第n+2传输门的第一端连接至所述第n+2电阻的第二端，所述第n+2传输门的控制端用于连接所述第二控制信号；The first end of the n+2 th transmission gate is connected to the second end of the n+2 th resistor, and the control end of the n+2 th transmission gate is used to connect to the second control signal;
所述第一传输门的第二端作为所述可调共栅偏置电路的输出端，且所述第一传输门的第二端分别连接至所述第n传输门的第二端、所述第n+1传输门的第二端以及所述第n+2传输门的第二端。The second end of the first transmission gate serves as the output end of the adjustable common-gate bias circuit, and the second end of the first transmission gate is respectively connected to the second end of the nth transmission gate, the second end of the n+1th transmission gate and the second end of the n+2th transmission gate.
优选的，所述第四晶体管、所述第十二晶体管、所述第十三晶体管、所述第十四晶体管、所述第十五晶体管均为MOS管。Preferably, the fourth transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are all MOS transistors.
优选的，所述第四晶体管的宽长比和所述第二晶体管的宽长比相同。Preferably, the width-to-length ratio of the fourth transistor is the same as the width-to-length ratio of the second transistor.
第二方面，本发明的实施例还提供了一种射频芯片，所述射频芯片包括如本发明的实施例提供的上述的低噪声放大器。In a second aspect, an embodiment of the present invention further provides a radio frequency chip, wherein the radio frequency chip includes the above-mentioned low noise amplifier provided by the embodiment of the present invention.
与相关技术相比，本发明的低噪声放大器和射频芯片通过所述可调共源偏置电路用于通过接收的第一控制信号将接收的外部的电流源电流根据预设的比例控制输出电流的大小，并将所述输出电流生成相应的第一输出电压。本发明的低噪声放大器和射频芯片还通过所述可调共栅偏置电路用于将接收的所述电流源电流通过多个串联的电阻，再通过接收的第二控制信号控制所述电流源电流通过所述电阻的个数以生成相应的第二输出电压。该电路结构通过第一输出电压和第二输出电压实现调节放大器的偏置，当本发明的低噪声放大器和射频芯片的应用场景需要更好的噪声系数、增益、或大信号摆幅时，可以适当提高第一输出电压和第二输出电压；当本发明的低噪声放大器和射频芯片的电路中所设计的增益档位差可以避免工艺制造等不可控因素，而造成实际电流与设计要求不精确时，也可通过调节不同大小的第一输出电压和第二输出电压来实现减少工艺偏差影响的性能。因此，采用本发明的低噪声放大器和射频芯片可调节放大器的偏置且工艺偏差影响小。Compared with the related art, the low noise amplifier and the radio frequency chip of the present invention are used to control the size of the output current according to a preset ratio of the received external current source current through the adjustable common source bias circuit through the received first control signal, and generate the corresponding first output voltage from the output current. The low noise amplifier and the radio frequency chip of the present invention are also used to pass the received current source current through a plurality of resistors connected in series through the adjustable common gate bias circuit, and then control the number of the current source current passing through the resistors through the received second control signal to generate the corresponding second output voltage. The circuit structure adjusts the bias of the amplifier through the first output voltage and the second output voltage. When the application scenario of the low noise amplifier and the radio frequency chip of the present invention requires a better noise coefficient, gain, or large signal swing, the first output voltage and the second output voltage can be appropriately increased; when the gain gear difference designed in the circuit of the low noise amplifier and the radio frequency chip of the present invention can avoid uncontrollable factors such as process manufacturing, and cause the actual current to be inaccurate with the design requirements, the performance of reducing the influence of process deviation can also be achieved by adjusting the first output voltage and the second output voltage of different sizes. Therefore, the bias of the amplifier can be adjusted by using the low noise amplifier and the radio frequency chip of the present invention, and the influence of process deviation is small.
附图说明 BRIEF DESCRIPTION OF THE DRAWINGS
下面结合附图详细说明本发明。通过结合以下附图所作的详细描述，本发明的上述或其他方面的内容将变得更清楚和更容易理解。附图中,The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings.
图1为相关技术的低噪声放大器的电路结构图；FIG1 is a circuit diagram of a low noise amplifier of the related art;
图2为相关技术的低噪声放大器的可调共源偏置电路的电路图；FIG2 is a circuit diagram of an adjustable common-source bias circuit of a low-noise amplifier in the related art;
图3为本发明实施例的低噪声放大器的可调共栅偏置电路的电路图。FIG3 is a circuit diagram of an adjustable common-gate bias circuit of a low noise amplifier according to an embodiment of the present invention.
具体实施方式Detailed ways
下面结合附图详细说明本发明的具体实施方式。The specific implementation of the present invention will be described in detail below with reference to the accompanying drawings.
在此记载的具体实施方式/实施例为本发明的特定的具体实施方式，用于说明本发明的构思，均是解释性和示例性的，不应解释为对本发明实施方式及本发明范围的限制。除在此记载的实施例外，本领域技术人员还能够基于本申请权利要求书和说明书所公开的内容采用显而易见的其它技术方案，这些技术方案包括采用对在此记载的实施例的做出任何显而易见的替换和修改的技术方案，都在本发明的保护范围之内。The specific implementation modes/embodiments recorded herein are specific implementation modes of the present invention, which are used to illustrate the concept of the present invention, are explanatory and exemplary, and should not be interpreted as limiting the implementation modes of the present invention and the scope of the present invention. In addition to the embodiments recorded herein, those skilled in the art can also adopt other obvious technical solutions based on the contents disclosed in the claims and the specification of this application, and these technical solutions include any obvious replacement and modification of the embodiments recorded herein, which are within the protection scope of the present invention.
本发明提供一种低噪声放大器100。请参考图1所示，图1为本发明实施例的低噪声放大器100的电路结构图。The present invention provides a low noise amplifier 100. Please refer to Fig. 1, which is a circuit structure diagram of the low noise amplifier 100 according to an embodiment of the present invention.
所述低噪声放大器100包括输入匹配网络电路1、第一电容C1、第一晶体管M1、第二晶体管M2、输出匹配网络电路2、可调共源偏置电路3以及可调共栅偏置电路4。The low noise amplifier 100 includes an input matching network circuit 1 , a first capacitor C1 , a first transistor M1 , a second transistor M2 , an output matching network circuit 2 , an adjustable common source bias circuit 3 , and an adjustable common gate bias circuit 4 .
本实施例中，所述第一晶体管M1和所述第二晶体管M2均为MOS管。In this embodiment, both the first transistor M1 and the second transistor M2 are MOS transistors.
所述低噪声放大器100的内部连接关系为：The internal connection relationship of the low noise amplifier 100 is:
所述输入匹配网络电路1的输入端作为所述低噪声放大器100的输入端。The input end of the input matching network circuit 1 serves as the input end of the low noise amplifier 100 .
所述输入匹配网络电路1的输出端串联所述第一电容C1后连接至所述第一晶体管M1的栅极。 The output end of the input matching network circuit 1 is connected in series with the first capacitor C1 and then connected to the gate of the first transistor M1 .
所述第一晶体的源极接地GND。所述第一晶体管M1的漏极连接至所述第二晶体管M2的源极。The source of the first transistor is connected to the ground GND. The drain of the first transistor M1 is connected to the source of the second transistor M2.
所述第二晶体管M2的漏极连接至所述输出匹配网络电路2的输入端。A drain of the second transistor M2 is connected to an input end of the output matching network circuit 2 .
所述输出匹配网络电路2的输出端作为所述低噪声放大器100的输出端。The output end of the output matching network circuit 2 serves as the output end of the low noise amplifier 100 .
所述可调共源偏置电路3设置于所述第一晶体管M1的栅极与所述第一电容C1之间。The adjustable common-source bias circuit 3 is disposed between the gate of the first transistor M1 and the first capacitor C1 .
所述可调共栅偏置电路4与所述第二晶体管M2的栅极连接的。The adjustable common-gate bias circuit 4 is connected to the gate of the second transistor M2.
所述输入匹配网络电路1用于所述低噪声放大器100的输入端的阻抗匹配。所述输入匹配网络电路1为本领域常用的电路。当然，不限于此，在设计需要允许情况，可以去除所述输入匹配网络电路1也是可以的。The input matching network circuit 1 is used for impedance matching of the input end of the low noise amplifier 100. The input matching network circuit 1 is a commonly used circuit in the art. Of course, it is not limited thereto, and the input matching network circuit 1 may be removed if the design requires it.
所述输出匹配网络电路2用于所述低噪声放大器100的输出端的阻抗匹配。所述输出匹配网络电路2为本领域常用的电路。当然，不限于此，在设计需要允许情况，可以去除所述输出匹配网络电路2也是可以的。The output matching network circuit 2 is used for impedance matching of the output end of the low noise amplifier 100. The output matching network circuit 2 is a commonly used circuit in the art. Of course, it is not limited thereto, and the output matching network circuit 2 may be removed if the design requires it.
所述可调共源偏置电路3用于通过接收的第一控制信号S1将接收的外部的电流源电流IPTAT根据预设的比例控制输出电流的大小，并将所述输出电流生成相应的第一输出电压VCS。其中，所述输出电流为所述可调共源偏置电路3的输出端输出的电流。当本发明的低噪声放大器100的应用场景需要更好的噪声系数、增益、或大信号摆幅时，可以适当提高第一输出电压VCS；当本发明的低噪声放大器100的电路中所设计的增益档位差可以避免工艺制造等不可控因素，而造成实际电流与设计要求不精确时，也可通过调节不同大小的第一输出电压VCS来实现减少工艺偏差影响的性能。The adjustable common source bias circuit 3 is used to control the size of the output current according to a preset ratio of the received external current source current IPTAT through the received first control signal S1, and generate a corresponding first output voltage VCS from the output current. The output current is the current output from the output end of the adjustable common source bias circuit 3. When the application scenario of the low noise amplifier 100 of the present invention requires a better noise factor, gain, or large signal swing, the first output voltage VCS can be appropriately increased; when the gain gear difference designed in the circuit of the low noise amplifier 100 of the present invention can avoid uncontrollable factors such as process manufacturing, and cause the actual current to be inaccurate with the design requirements, the performance of reducing the influence of process deviation can also be achieved by adjusting the first output voltage VCS of different sizes.
请参考图2所示，图2为相关技术的低噪声放大器100的可调共源偏置电路3的电路图。具体的，所述可调共源偏置电路3包括第三晶体管M3、第五晶体管M5、第六晶体管M6、第七晶体管 M7、第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11、第一开关K1、第二开关K2、第三开关K3、第四开关K4、第五开关K5、第六开关K6以及第二电容C2。Please refer to FIG. 2, which is a circuit diagram of an adjustable common source bias circuit 3 of a low noise amplifier 100 in the related art. Specifically, the adjustable common source bias circuit 3 includes a third transistor M3, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6 and a second capacitor C2.
所述可调共源偏置电路3的内部电路连接关系为：The internal circuit connection relationship of the adjustable common source bias circuit 3 is:
所述第五晶体管M5的漏极作为所述可调共源偏置电路3的输入端，且所述第五晶体管M5的漏极分别连接至所述第五晶体管M5的栅极和所述第六晶体管M6的栅极。所述可调共源偏置电路3的输入端用于接收的所述电流源电流IPTAT。The drain of the fifth transistor M5 serves as the input terminal of the adjustable common source bias circuit 3, and the drain of the fifth transistor M5 is respectively connected to the gate of the fifth transistor M5 and the gate of the sixth transistor M6. The input terminal of the adjustable common source bias circuit 3 is used to receive the current source current IPTAT.
所述第五晶体管M5的源极和所述第六晶体管M6的源极均接地GND。A source of the fifth transistor M5 and a source of the sixth transistor M6 are both connected to the ground GND.
所述第六晶体管M6的漏极分别连接至所述第七晶体管M7的漏极、所述第七晶体管M7的栅极、所述第八晶体管M8的栅极、所述第一开关K1的第一端、所述第三开关K3的第一端以及所述第五开关K5的第一端。The drain of the sixth transistor M6 is respectively connected to the drain of the seventh transistor M7, the gate of the seventh transistor M7, the gate of the eighth transistor M8, the first end of the first switch K1, the first end of the third switch K3 and the first end of the fifth switch K5.
所述第七晶体管M7的源极、所述第八晶体管M8的源极、所述第九晶体管M9的源极、所述第十晶体管M10的源极、所述第十一晶体管M11的源极、所述第二开关K2的第一端、所述第四开关K4的第一端以及所述第六开关K6的第一端均连接至电源电压VCC。A source of the seventh transistor M7, a source of the eighth transistor M8, a source of the ninth transistor M9, a source of the tenth transistor M10, a source of the eleventh transistor M11, a first end of the second switch K2, a first end of the fourth switch K4, and a first end of the sixth switch K6 are all connected to a power supply voltage VCC.
所述第一开关K1的第二端分别连接至所述第二开关K2的第二端和所述第九晶体管M9的栅极。The second end of the first switch K1 is connected to the second end of the second switch K2 and the gate of the ninth transistor M9 respectively.
所述第三开关K3的第二端分别连接至所述第四开关K4的第二端和所述第十晶体管M10的栅极。The second end of the third switch K3 is connected to the second end of the fourth switch K4 and the gate of the tenth transistor M10 respectively.
所述第五开关K5的第二端分别连接至所述第六开关K6的第二端和所述第十一晶体管M11的栅极。The second end of the fifth switch K5 is connected to the second end of the sixth switch K6 and the gate of the eleventh transistor M11 , respectively.
所述第一开关K1的控制端、所述第二开关K2的控制端、所述第三开关K3的控制端、所述第四开关K4的控制端、所述第五开关K5的控制端以及所述第六开关K6的控制端均用于连接所述第一控制信号S1。The control ends of the first switch K1 , the second switch K2 , the third switch K3 , the fourth switch K4 , the fifth switch K5 and the sixth switch K6 are all used to connect to the first control signal S1 .
所述第八晶体管M8的漏极作为所述可调共源偏置电路3的输 出端，且所述第八晶体管M8的漏极分别连接至所述第九晶体管M9的漏极、所述第十晶体管M10的漏极、所述第十一晶体管M11的漏极、所述第三晶体管M3的漏极、所述第三晶体管M3的栅极以及所述第二电容C2的第一端。The drain of the eighth transistor M8 serves as the input of the adjustable common source bias circuit 3. The output terminal is connected to the drain of the ninth transistor M9, the drain of the tenth transistor M10, the drain of the eleventh transistor M11, the drain of the third transistor M3, the gate of the third transistor M3 and the first terminal of the second capacitor C2.
所述第三晶体管M3的源极和所述第二电容C2的第二端均接地GND。A source of the third transistor M3 and a second end of the second capacitor C2 are both grounded GND.
为了实现更多的调节放大器的偏置功能，本实施例中，所述可调共源偏置电路3还包括第m晶体管Mm、第h开关Kh和第h+1开关Kh+1，其中，m为大于16的正整数，h为大于7的正整数。其中，所述第h开关Kh的第一端连接至所述第一开关K1的第一端。所述第m晶体管Mm的源极分别连接至所述第h+1开关Kh+1的第一端和电源电压VCC。所述第m晶体管Mm的栅极分别连接至所述第h开关Kh的第二端和所述第h+1开关Kh+1的第二端。所述第m晶体管Mm的漏极连接至所述第三晶体管M3的漏极。In order to achieve more bias functions of adjusting the amplifier, in this embodiment, the adjustable common source bias circuit 3 also includes an mth transistor Mm, an hth switch Kh and an h+1th switch Kh+1, wherein m is a positive integer greater than 16, and h is a positive integer greater than 7. The first end of the hth switch Kh is connected to the first end of the first switch K1. The source of the mth transistor Mm is respectively connected to the first end of the h+1th switch Kh+1 and the power supply voltage VCC. The gate of the mth transistor Mm is respectively connected to the second end of the hth switch Kh and the second end of the h+1th switch Kh+1. The drain of the mth transistor Mm is connected to the drain of the third transistor M3.
所述可调共源偏置电路3的工作原理为：The working principle of the adjustable common source bias circuit 3 is:
所述电流源电流IPTAT流入所述第三晶体管M3、所述第五晶体管M5、所述第六晶体管M6、所述第七晶体管M7、所述第八晶体管M8、所述第九晶体管M9、所述第十晶体管M10以及所述第十一晶体管M11组成的电流镜。所述第八晶体管M8、所述第九晶体管M9、所述第十晶体管M10以及所述第十一晶体管M11均为MOS管及其后的所述第m晶体管Mm按不同比例复制所述电流源电流IPTAT，即每个晶体管形成一个支路。每一支路的MOS管栅极接一个串联开关和一个并联开关，令其控制信号相反，以决定该支路的通断。所述第一控制信号S1为总线，所述第一控制信号S1包括多个控制信号。通过选定不同的开关组合，可以决定流入所述第三晶体管M3的电流大小，从而决定第一输出电压VCS的大小。The current source current IPTAT flows into the current mirror composed of the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11. The eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 are all MOS transistors, and the subsequent m-th transistor Mm replicates the current source current IPTAT in different proportions, that is, each transistor forms a branch. The gate of the MOS transistor of each branch is connected to a series switch and a parallel switch, and the control signals are opposite to determine the on and off of the branch. The first control signal S1 is a bus, and the first control signal S1 includes multiple control signals. By selecting different switch combinations, the size of the current flowing into the third transistor M3 can be determined, thereby determining the size of the first output voltage VCS.
本实施例中，所述第三晶体管M3、所述第五晶体管M5、所述第六晶体管M6、所述第七晶体管M7、所述第八晶体管M8、所述第九晶体管M9、所述第十晶体管M10以及所述第十一晶体管M11均为MOS管。更优的，所述第三晶体管M3的宽长比和所述 第一晶体管M1的宽长比相同，该设置可以最大化避免工艺制造偏差带来的影响，从而使得所述低噪声放大器100的工艺影响小。In this embodiment, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 are all MOS transistors. Preferably, the width-to-length ratio of the third transistor M3 and the The first transistors M1 have the same width-to-length ratio. This configuration can maximize the avoidance of the impact of process manufacturing deviations, thereby minimizing the process impact of the low noise amplifier 100.
所述可调共栅偏置电路4用于将接收的所述电流源电流IPTAT通过多个串联的电阻，再通过接收的第二控制信号S2控制所述电流源电流IPTAT通过所述电阻的个数以生成相应的第二输出电压VCG。当本发明的低噪声放大器100的应用场景需要更好的噪声系数、增益、或大信号摆幅时，可以适当提高第二输出电压VCG；当本发明的低噪声放大器100的电路中所设计的增益档位差可以避免工艺制造等不可控因素，而造成实际电流与设计要求不精确时，也可通过调节不同大小的第二输出电压VCG来实现减少工艺偏差影响的性能。The adjustable common-gate bias circuit 4 is used to pass the received current source current IPTAT through a plurality of resistors connected in series, and then control the number of resistors through which the current source current IPTAT passes through to generate a corresponding second output voltage VCG through the received second control signal S2. When the application scenario of the low-noise amplifier 100 of the present invention requires a better noise factor, gain, or large signal swing, the second output voltage VCG can be appropriately increased; when the gain gear difference designed in the circuit of the low-noise amplifier 100 of the present invention can avoid uncontrollable factors such as process manufacturing, and cause the actual current to be inaccurate with the design requirements, the performance of reducing the influence of process deviation can also be achieved by adjusting the second output voltage VCG of different sizes.
请参考图3所示，图3为本发明实施例的低噪声放大器100的可调共栅偏置电路4的电路图。具体的，所述可调共栅偏置电路4包括第四晶体管M4、第十二晶体管M12、第十三晶体管M13、第十四晶体管M14、第十五晶体管M15、第一电阻R1、第n电阻Rn、第n+1电阻Rn+1、第n+2电阻Rn+2、第一传输门TG1、第n传输门TGn、第n+1传输门TGn+1以及第n+2传输门TGn+2。其中，n为大于2的正整数。Please refer to FIG. 3, which is a circuit diagram of an adjustable common-gate bias circuit 4 of a low-noise amplifier 100 according to an embodiment of the present invention. Specifically, the adjustable common-gate bias circuit 4 includes a fourth transistor M4, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a first resistor R1, an nth resistor Rn, an n+1th resistor Rn+1, an n+2th resistor Rn+2, a first transmission gate TG1, an nth transmission gate TGn, an n+1th transmission gate TGn+1, and an n+2th transmission gate TGn+2. Wherein, n is a positive integer greater than 2.
所述可调共栅偏置电路4的内部电路连接关系为：The internal circuit connection relationship of the adjustable common-gate bias circuit 4 is:
所述第十二晶体管M12的漏极作为所述可调共栅偏置电路4的输入端，且所述第十二晶体管M12的漏极分别连接至所述第十二晶体管M12的栅极和所述第十三晶体管M13的栅极。所述可调共栅偏置电路4的输入端用于接收的所述电流源电流IPTAT。The drain of the twelfth transistor M12 serves as the input terminal of the adjustable common-gate bias circuit 4, and the drain of the twelfth transistor M12 is respectively connected to the gate of the twelfth transistor M12 and the gate of the thirteenth transistor M13. The input terminal of the adjustable common-gate bias circuit 4 is used to receive the current source current IPTAT.
所述第十二晶体管M12的源极和所述第十三晶体管M13的源极均接地GND。A source of the twelfth transistor M12 and a source of the thirteenth transistor M13 are both connected to the ground GND.
所述第十三晶体管M13的漏极分别连接至所述第十四晶体管M14的漏极、所述第十四晶体管M14的栅极以及所述第十五晶体管M15的栅极。The drain of the thirteenth transistor M13 is connected to the drain of the fourteenth transistor M14, the gate of the fourteenth transistor M14 and the gate of the fifteenth transistor M15, respectively.
所述第十四晶体管M14的源极和所述第十五晶体管M15的源极均连接至电源电压VCC。 A source of the fourteenth transistor M14 and a source of the fifteenth transistor M15 are both connected to a power supply voltage VCC.
所述第十五晶体管M15的漏极通过依次串联所述第一电阻R1、所述第n电阻Rn、所述第n+1电阻Rn+1和所述第n+2电阻Rn+2后分别连接至所述第四晶体管M4的漏极和所述第四晶体管M4的栅极。The drain of the fifteenth transistor M15 is connected to the drain of the fourth transistor M4 and the gate of the fourth transistor M4 respectively by sequentially connecting the first resistor R1, the nth resistor Rn, the n+1th resistor Rn+1 and the n+2th resistor Rn+2 in series.
所述第四晶体管M4的源极接地GND。A source of the fourth transistor M4 is connected to the ground GND.
所述第一传输门TG1的第一端连接至所述第一电阻R1的第二端，所述第一传输门TG1的控制端用于连接所述第二控制信号S2。A first end of the first transmission gate TG1 is connected to a second end of the first resistor R1 , and a control end of the first transmission gate TG1 is used to connect to the second control signal S2 .
所述第n传输门TGn的第一端连接至所述第n电阻Rn的第二端，所述第n传输门TGn的控制端用于连接所述第二控制信号S2。A first end of the nth transmission gate TGn is connected to a second end of the nth resistor Rn, and a control end of the nth transmission gate TGn is used to connect to the second control signal S2.
所述第n+1传输门TGn+1的第一端连接至所述第n+1电阻Rn+1的第二端，所述第n+1传输门TGn+1的控制端用于连接所述第二控制信号S2。A first end of the n+1th transmission gate TGn+1 is connected to a second end of the n+1th resistor Rn+1, and a control end of the n+1th transmission gate TGn+1 is used to connect to the second control signal S2.
所述第n+2传输门TGn+2的第一端连接至所述第n+2电阻Rn+2的第二端，所述第n+2传输门TGn+2的控制端用于连接所述第二控制信号S2。A first end of the n+2 th transmission gate TGn+2 is connected to a second end of the n+2 th resistor Rn+2, and a control end of the n+2 th transmission gate TGn+2 is used to connect to the second control signal S2.
所述第一传输门TG1的第二端作为所述可调共栅偏置电路4的输出端，且所述第一传输门TG1的第二端分别连接至所述第n传输门TGn的第二端、所述第n+1传输门TGn+1的第二端以及所述第n+2传输门TGn+2的第二端。The second end of the first transmission gate TG1 serves as the output end of the adjustable common-gate bias circuit 4, and the second end of the first transmission gate TG1 is respectively connected to the second end of the nth transmission gate TGn, the second end of the n+1th transmission gate TGn+1, and the second end of the n+2th transmission gate TGn+2.
所述可调共栅偏置电路4的工作原理为：The working principle of the adjustable common-gate bias circuit 4 is:
所述电流源电流IPTAT流入第四晶体管M4、所述第四晶体管M4、所述第十二晶体管M12、所述第十三晶体管M13、所述第十四晶体管M14、所述第十五晶体管M15组成的电流镜。在所述第十五晶体管M15和所述第四晶体管M4之间插入N个大小相等的电阻，从而可以决定N档电压。每一档电压后接一个传输门，通过所述第二控制信号S2将传输门的通断选择最终的第二输出电压VCG。即在每个电阻下面引出一个电压，每个电压后面都接一个传输门，由控制传输门的所述第二控制信号S2信号决定哪一个电压给所述第二晶体管M2提供偏置。The current source current IPTAT flows into the current mirror composed of the fourth transistor M4, the fourth transistor M4, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15. N resistors of equal size are inserted between the fifteenth transistor M15 and the fourth transistor M4, so that N voltage levels can be determined. Each voltage level is followed by a transmission gate, and the second control signal S2 is used to select the final second output voltage VCG by turning the transmission gate on and off. That is, a voltage is drawn out under each resistor, and each voltage is followed by a transmission gate. The second control signal S2 that controls the transmission gate determines which voltage provides bias for the second transistor M2.
本实施例中，所述第四晶体管M4、所述第十二晶体管M12、 所述第十三晶体管M13、所述第十四晶体管M14、所述第十五晶体管M15均为MOS管。更优的，所述第四晶体管M4的宽长比和所述第二晶体管M2的宽长比相同，该设置可以最大化避免工艺制造偏差带来的影响，从而使得所述低噪声放大器100的工艺影响小。In this embodiment, the fourth transistor M4, the twelfth transistor M12, The thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 are all MOS transistors. Preferably, the width-to-length ratio of the fourth transistor M4 is the same as the width-to-length ratio of the second transistor M2. This setting can maximize the avoidance of the influence of process manufacturing deviation, thereby minimizing the process influence of the low noise amplifier 100.
本发明的实施例还提供一种射频芯片，所述射频芯片包括所述低噪声放大器100。An embodiment of the present invention further provides a radio frequency chip, wherein the radio frequency chip includes the low noise amplifier 100 .
需要指出的是，本发明采用的相关电路、电阻、电容、开关、传输门及晶体管均为本领域常用的电路、元器件，对应的具体的指标和参数根据实际应用进行调整，在此，不作详细赘述。It should be pointed out that the relevant circuits, resistors, capacitors, switches, transmission gates and transistors used in the present invention are all commonly used circuits and components in the field. The corresponding specific indicators and parameters are adjusted according to actual applications and are not described in detail here.
与相关技术相比，本发明的低噪声放大器和射频芯片通过所述可调共源偏置电路用于通过接收的第一控制信号将接收的外部的电流源电流根据预设的比例控制输出电流的大小，并将所述输出电流生成相应的第一输出电压。本发明的低噪声放大器和射频芯片还通过所述可调共栅偏置电路用于将接收的所述电流源电流通过多个串联的电阻，再通过接收的第二控制信号控制所述电流源电流通过所述电阻的个数以生成相应的第二输出电压。该电路结构通过第一输出电压和第二输出电压实现调节放大器的偏置，当本发明的低噪声放大器和射频芯片的应用场景需要更好的噪声系数、增益、或大信号摆幅时，可以适当提高第一输出电压和第二输出电压；当本发明的低噪声放大器和射频芯片的电路中所设计的增益档位差可以避免工艺制造等不可控因素，而造成实际电流与设计要求不精确时，也可通过调节不同大小的第一输出电压和第二输出电压来实现减少工艺偏差影响的性能。因此，采用本发明的低噪声放大器和射频芯片可调节放大器的偏置且工艺偏差影响小。Compared with the related art, the low noise amplifier and the radio frequency chip of the present invention are used to control the size of the output current according to a preset ratio of the received external current source current through the adjustable common source bias circuit through the received first control signal, and generate the corresponding first output voltage from the output current. The low noise amplifier and the radio frequency chip of the present invention are also used to pass the received current source current through a plurality of resistors connected in series through the adjustable common gate bias circuit, and then control the number of the current source current passing through the resistors through the received second control signal to generate the corresponding second output voltage. The circuit structure adjusts the bias of the amplifier through the first output voltage and the second output voltage. When the application scenario of the low noise amplifier and the radio frequency chip of the present invention requires a better noise coefficient, gain, or large signal swing, the first output voltage and the second output voltage can be appropriately increased; when the gain gear difference designed in the circuit of the low noise amplifier and the radio frequency chip of the present invention can avoid uncontrollable factors such as process manufacturing, and cause the actual current to be inaccurate with the design requirements, the performance of reducing the influence of process deviation can also be achieved by adjusting the first output voltage and the second output voltage of different sizes. Therefore, the bias of the amplifier can be adjusted by using the low noise amplifier and the radio frequency chip of the present invention, and the influence of process deviation is small.
需要说明的是，以上参照附图所描述的各个实施例仅用以说明本发明而非限制本发明的范围，本领域的普通技术人员应当理解，在不脱离本发明的精神和范围的前提下对本发明进行的修改或者等同替换，均应涵盖在本发明的范围之内。此外，除上下文另有所指外，以单数形式出现的词包括复数形式，反之亦然。另外，除非 特别说明，那么任何实施例的全部或一部分可结合任何其它实施例的全部或一部分来使用。 It should be noted that the various embodiments described above with reference to the accompanying drawings are only used to illustrate the present invention rather than to limit the scope of the present invention. Those skilled in the art should understand that any modification or equivalent substitution of the present invention without departing from the spirit and scope of the present invention should be included in the scope of the present invention. In addition, unless the context otherwise requires, words appearing in the singular include the plural form, and vice versa. In addition, unless otherwise specified in the context, In particular, all or part of any embodiment may be used in combination with all or part of any other embodiment.

Claims (10)

  1. 一种低噪声放大器，其包括输入匹配网络电路、第一电容、第一晶体管、第二晶体管以及输出匹配网络电路，所述输入匹配网络电路的输入端作为所述低噪声放大器的输入端；所述输入匹配网络电路的输出端串联所述第一电容后连接至所述第一晶体管的栅极；所述第一晶体的源极接地；所述第一晶体管的漏极连接至所述第二晶体管的源极；所述第二晶体管的漏极连接至所述输出匹配网络电路的输入端，所述输出匹配网络电路的输出端作为所述低噪声放大器的输出端；其中，所述输入匹配网络电路用于所述低噪声放大器的输入端的阻抗匹配，所述输出匹配网络电路用于所述低噪声放大器的输出端的阻抗匹配；其特征在于，A low-noise amplifier comprises an input matching network circuit, a first capacitor, a first transistor, a second transistor and an output matching network circuit, wherein the input end of the input matching network circuit serves as the input end of the low-noise amplifier; the output end of the input matching network circuit is connected in series with the first capacitor and then connected to the gate of the first transistor; the source of the first transistor is grounded; the drain of the first transistor is connected to the source of the second transistor; the drain of the second transistor is connected to the input end of the output matching network circuit, and the output end of the output matching network circuit serves as the output end of the low-noise amplifier; wherein the input matching network circuit is used for impedance matching of the input end of the low-noise amplifier, and the output matching network circuit is used for impedance matching of the output end of the low-noise amplifier; and characterized in that,
    所述低噪声放大器还包括设置于所述第一晶体管的栅极与所述第一电容之间的可调共源偏置电路和与所述第二晶体管的栅极连接的可调共栅偏置电路；The low noise amplifier further comprises an adjustable common source bias circuit disposed between the gate of the first transistor and the first capacitor and an adjustable common gate bias circuit connected to the gate of the second transistor;
    所述可调共源偏置电路用于通过接收的第一控制信号将接收的外部的电流源电流根据预设的比例控制输出电流的大小，并将所述输出电流生成相应的第一输出电压；The adjustable common source bias circuit is used to control the magnitude of the output current according to a preset ratio of the received external current source current through the received first control signal, and generate a corresponding first output voltage from the output current;
    所述可调共栅偏置电路用于将接收的所述电流源电流通过多个串联的电阻，再通过接收的第二控制信号控制所述电流源电流通过所述电阻的个数以生成相应的第二输出电压。The adjustable common-gate bias circuit is used to pass the received current source current through a plurality of resistors connected in series, and then control the number of the resistors through which the current source current passes through by a received second control signal to generate a corresponding second output voltage.
  2. 根据权利要求1所述的低噪声放大器，其特征在于，所述第一晶体管和所述第二晶体管均为MOS管。The low noise amplifier according to claim 1, characterized in that both the first transistor and the second transistor are MOS transistors.
  3. 根据权利要求2所述的低噪声放大器，其特征在于，所述可调共源偏置电路包括第三晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第一开关、第二开关、第三开关、第四开关、第五开关、第六开关以及第二电容；The low noise amplifier according to claim 2, characterized in that the adjustable common source bias circuit comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch and a second capacitor;
    所述第五晶体管的漏极作为所述可调共源偏置电路的输入端，且所述第五晶体管的漏极分别连接至所述第五晶体管的栅极和所述第六晶体管的栅极；所述可调共源偏置电路的输入端用于接收的 所述电流源电流；The drain of the fifth transistor serves as the input terminal of the adjustable common source bias circuit, and the drain of the fifth transistor is connected to the gate of the fifth transistor and the gate of the sixth transistor respectively; the input terminal of the adjustable common source bias circuit is used to receive the current source current;
    所述第五晶体管的源极和所述第六晶体管的源极均接地；The source of the fifth transistor and the source of the sixth transistor are both grounded;
    所述第六晶体管的漏极分别连接至所述第七晶体管的漏极、所述第七晶体管的栅极、所述第八晶体管的栅极、所述第一开关的第一端、所述第三开关的第一端以及所述第五开关的第一端；The drain of the sixth transistor is respectively connected to the drain of the seventh transistor, the gate of the seventh transistor, the gate of the eighth transistor, the first end of the first switch, the first end of the third switch and the first end of the fifth switch;
    所述第七晶体管的源极、所述第八晶体管的源极、所述第九晶体管的源极、所述第十晶体管的源极、所述第十一晶体管的源极、所述第二开关的第一端、所述第四开关的第一端以及所述第六开关的第一端均连接至电源电压；A source of the seventh transistor, a source of the eighth transistor, a source of the ninth transistor, a source of the tenth transistor, a source of the eleventh transistor, a first end of the second switch, a first end of the fourth switch, and a first end of the sixth switch are all connected to a power supply voltage;
    所述第一开关的第二端分别连接至所述第二开关的第二端和所述第九晶体管的栅极；The second end of the first switch is connected to the second end of the second switch and the gate of the ninth transistor respectively;
    所述第三开关的第二端分别连接至所述第四开关的第二端和所述第十晶体管的栅极；The second end of the third switch is connected to the second end of the fourth switch and the gate of the tenth transistor respectively;
    所述第五开关的第二端分别连接至所述第六开关的第二端和所述第十一晶体管的栅极；The second end of the fifth switch is connected to the second end of the sixth switch and the gate of the eleventh transistor respectively;
    所述第一开关的控制端、所述第二开关的控制端、所述第三开关的控制端、所述第四开关的控制端、所述第五开关的控制端以及所述第六开关的控制端均用于连接所述第一控制信号；The control end of the first switch, the control end of the second switch, the control end of the third switch, the control end of the fourth switch, the control end of the fifth switch and the control end of the sixth switch are all used to connect the first control signal;
    所述第八晶体管的漏极作为所述可调共源偏置电路的输出端，且所述第八晶体管的漏极分别连接至所述第九晶体管的漏极、所述第十晶体管的漏极、所述第十一晶体管的漏极、所述第三晶体管的漏极、所述第三晶体管的栅极以及所述第二电容的第一端；The drain of the eighth transistor serves as the output end of the adjustable common-source bias circuit, and the drain of the eighth transistor is respectively connected to the drain of the ninth transistor, the drain of the tenth transistor, the drain of the eleventh transistor, the drain of the third transistor, the gate of the third transistor and the first end of the second capacitor;
    所述第三晶体管的源极和所述第二电容的第二端均接地。A source of the third transistor and a second end of the second capacitor are both grounded.
  4. 根据权利要求3所述的低噪声放大器，其特征在于，所述第三晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管、所述第九晶体管、所述第十晶体管以及所述第十一晶体管均为MOS管。The low-noise amplifier according to claim 3 is characterized in that the third transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor and the eleventh transistor are all MOS transistors.
  5. 根据权利要求4所述的低噪声放大器，其特征在于，所述第三晶体管的宽长比和所述第一晶体管的宽长比相同。The low noise amplifier according to claim 4, characterized in that the width-to-length ratio of the third transistor is the same as the width-to-length ratio of the first transistor.
  6. 根据权利要求3所述的低噪声放大器，其特征在于，所述 可调共源偏置电路还包括第m晶体管、第h开关和第h+1开关，其中，m为大于16的正整数，h为大于7的正整数；The low noise amplifier according to claim 3, characterized in that The adjustable common source bias circuit further includes an mth transistor, an hth switch and an h+1th switch, wherein m is a positive integer greater than 16, and h is a positive integer greater than 7;
    所述第h开关的第一端连接至所述第一开关的第一端；The first end of the hth switch is connected to the first end of the first switch;
    所述第m晶体管的源极分别连接至所述第h+1开关的第一端和电源电压；The source of the mth transistor is connected to the first terminal of the h+1th switch and the power supply voltage respectively;
    所述第m晶体管的栅极分别连接至所述第h开关的第二端和所述第h+1开关的第二端；The gate of the mth transistor is connected to the second end of the hth switch and the second end of the h+1th switch respectively;
    所述第m晶体管的漏极连接至所述第三晶体管的漏极。A drain of the mth transistor is connected to a drain of the third transistor.
  7. 根据权利要求2所述的低噪声放大器，其特征在于，所述可调共栅偏置电路包括第四晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第一电阻、第n电阻、第n+1电阻、第n+2电阻、第一传输门、第n传输门、第n+1传输门以及第n+2传输门；其中，n为大于2的正整数；The low noise amplifier according to claim 2, characterized in that the adjustable common gate bias circuit comprises a fourth transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a first resistor, an nth resistor, an n+1th resistor, an n+2th resistor, a first transmission gate, an nth transmission gate, an n+1th transmission gate and an n+2th transmission gate; wherein n is a positive integer greater than 2;
    所述第十二晶体管的漏极作为所述可调共栅偏置电路的输入端，且所述第十二晶体管的漏极分别连接至所述第十二晶体管的栅极和所述第十三晶体管的栅极；所述可调共栅偏置电路的输入端用于接收的所述电流源电流；The drain of the twelfth transistor serves as an input terminal of the adjustable common-gate bias circuit, and the drain of the twelfth transistor is respectively connected to the gate of the twelfth transistor and the gate of the thirteenth transistor; the input terminal of the adjustable common-gate bias circuit is used to receive the current of the current source;
    所述第十二晶体管的源极和所述第十三晶体管的源极均接地；The source of the twelfth transistor and the source of the thirteenth transistor are both grounded;
    所述第十三晶体管的漏极分别连接至所述第十四晶体管的漏极、所述第十四晶体管的栅极以及所述第十五晶体管的栅极；The drain of the thirteenth transistor is connected to the drain of the fourteenth transistor, the gate of the fourteenth transistor and the gate of the fifteenth transistor respectively;
    所述第十四晶体管的源极和所述第十五晶体管的源极均连接至电源电压；A source of the fourteenth transistor and a source of the fifteenth transistor are both connected to a power supply voltage;
    所述第十五晶体管的漏极通过依次串联所述第一电阻、所述第n电阻、所述第n+1电阻和所述第n+2电阻后分别连接至所述第四晶体管的漏极和所述第四晶体管的栅极；The drain of the fifteenth transistor is connected to the drain of the fourth transistor and the gate of the fourth transistor respectively by sequentially connecting the first resistor, the nth resistor, the n+1th resistor and the n+2th resistor in series;
    所述第四晶体管的源极接地；The source of the fourth transistor is grounded;
    所述第一传输门的第一端连接至所述第一电阻的第二端，所述第一传输门的控制端用于连接所述第二控制信号；The first end of the first transmission gate is connected to the second end of the first resistor, and the control end of the first transmission gate is used to connect to the second control signal;
    所述第n传输门的第一端连接至所述第n电阻的第二端，所述第n传输门的控制端用于连接所述第二控制信号； The first end of the nth transmission gate is connected to the second end of the nth resistor, and the control end of the nth transmission gate is used to connect to the second control signal;
    所述第n+1传输门的第一端连接至所述第n+1电阻的第二端，所述第n+1传输门的控制端用于连接所述第二控制信号；The first end of the n+1th transmission gate is connected to the second end of the n+1th resistor, and the control end of the n+1th transmission gate is used to connect the second control signal;
    所述第n+2传输门的第一端连接至所述第n+2电阻的第二端，所述第n+2传输门的控制端用于连接所述第二控制信号；The first end of the n+2 th transmission gate is connected to the second end of the n+2 th resistor, and the control end of the n+2 th transmission gate is used to connect to the second control signal;
    所述第一传输门的第二端作为所述可调共栅偏置电路的输出端，且所述第一传输门的第二端分别连接至所述第n传输门的第二端、所述第n+1传输门的第二端以及所述第n+2传输门的第二端。The second end of the first transmission gate serves as the output end of the adjustable common-gate bias circuit, and the second end of the first transmission gate is respectively connected to the second end of the nth transmission gate, the second end of the n+1th transmission gate and the second end of the n+2th transmission gate.
  8. 根据权利要求7所述的低噪声放大器，其特征在于，所述第四晶体管、所述第十二晶体管、所述第十三晶体管、所述第十四晶体管、所述第十五晶体管均为MOS管。The low-noise amplifier according to claim 7, characterized in that the fourth transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are all MOS transistors.
  9. 根据权利要求8所述的低噪声放大器，其特征在于，所述第四晶体管的宽长比和所述第二晶体管的宽长比相同。The low noise amplifier according to claim 8, characterized in that the width-to-length ratio of the fourth transistor is the same as the width-to-length ratio of the second transistor.
  10. 一种射频芯片，其特征在于，所述射频芯片包括如权利要求1-9中任意一项所述的低噪声放大器。 A radio frequency chip, characterized in that the radio frequency chip comprises the low noise amplifier as described in any one of claims 1-9.
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CN115567006A (en) * 2022-10-21 2023-01-03 深圳飞骧科技股份有限公司 Low noise amplifier and radio frequency chip
CN116054802A (en) * 2023-01-09 2023-05-02 深圳飞骧科技股份有限公司 Radio frequency switch circuit
CN116248052A (en) * 2023-02-27 2023-06-09 深圳飞骧科技股份有限公司 Low noise amplifier and radio frequency chip
CN116131777B (en) * 2023-04-04 2023-08-04 安徽矽磊电子科技有限公司 High dynamic range variable gain amplifier circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070040609A1 (en) * 2005-08-16 2007-02-22 Intel Corporation Low noise amplifier
CN201039094Y (en) * 2007-05-21 2008-03-19 杭州中科微电子有限公司 A high-gain RF low-noise amplifier
CN105897201A (en) * 2016-03-31 2016-08-24 宜确半导体（苏州）有限公司 GSM (Global System for Mobile Communication) radio frequency power amplifier
CN113890491A (en) * 2021-12-03 2022-01-04 南京燧锐科技有限公司 Low-leakage amplifier bias circuit
CN115567006A (en) * 2022-10-21 2023-01-03 深圳飞骧科技股份有限公司 Low noise amplifier and radio frequency chip

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070040609A1 (en) * 2005-08-16 2007-02-22 Intel Corporation Low noise amplifier
CN201039094Y (en) * 2007-05-21 2008-03-19 杭州中科微电子有限公司 A high-gain RF low-noise amplifier
CN105897201A (en) * 2016-03-31 2016-08-24 宜确半导体（苏州）有限公司 GSM (Global System for Mobile Communication) radio frequency power amplifier
CN113890491A (en) * 2021-12-03 2022-01-04 南京燧锐科技有限公司 Low-leakage amplifier bias circuit
CN115567006A (en) * 2022-10-21 2023-01-03 深圳飞骧科技股份有限公司 Low noise amplifier and radio frequency chip

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