WO2024082568A1 - Semiconductor structure and manufacturing method therefor - Google Patents

Abstract

Disclosed are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: transistors and bit lines arranged in a first direction, each transistor comprising a gate structure extending in a second direction and a semiconductor channel having opposite first end and second end in the second direction, and the bit lines being in contact with and connected to first ends and extending in a third direction; and a lower electrode layer in contact with and connected to second ends, the lower electrode layer comprising a first region extending in the second direction, and a second region and a third region which extend in the first direction, the first region being connected to the second region and the third region, the third region being in contact with and connected to the second ends, the second region being directly opposite to the bit lines in the first direction, and a gap being formed between the bit lines and the lower electrode layer.

Description

Semiconductor structure and method for manufacturing the same

cross reference

This application claims priority to the Chinese patent application entitled “Semiconductor Structure and Method for Manufacturing the Same” filed on October 20, 2022 and application number 202211287767.8, which is incorporated herein by reference in its entirety.

Technical Field

The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same.

Background technique

With the continuous development of semiconductor structure, its critical dimensions are constantly decreasing. However, due to the limitations of lithography machines, there is a limit to the reduction of its critical dimensions. Therefore, how to make chips with higher storage density on a wafer is the research direction of many scientific researchers and semiconductor practitioners.

However, as the demand for capacitor structures with large capacitance increases, it is difficult to control the size of the capacitor structure while increasing the integration density of the semiconductor structure, as well as to control the positional relationship between the capacitor structure and other conductive structures in the semiconductor structure, thereby making it difficult to further improve the overall electrical performance of the semiconductor structure.

Summary of the invention

The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial for improving the integration density of the semiconductor structure while providing a novel lower electrode layer to improve the overall electrical performance of the semiconductor structure.

According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, comprising: transistors and bit lines arranged along a first direction; the transistor comprising: a gate structure extending along a second direction, and a semiconductor channel having a first end and a second end relative to each other along the second direction; the bit line is in contact with the first end, and the bit line extends along a third direction, and the first direction, the second direction and the third direction intersect each other; a lower electrode layer is in contact with the second end, the lower electrode layer comprising: a first region extending along the second direction, and a second region and a third region both extending along the first direction, the first region connecting the second region and the third region, the third region in contact with the second end, the second region facing the bit line along the first direction, and there is a gap between the bit line and the lower electrode layer.

In some embodiments, the length of the second region in the first direction is a first length, the length of the third region in the first direction is a second length, and the second length is greater than or equal to the first length.

In some embodiments, the lower electrode layer includes a first sub-lower electrode layer and a second sub-lower electrode layer, the first sub-lower electrode layer, the first end and the second end together constitute a semiconductor layer, and the semiconductor layer is an integrated structure; the semiconductor structure also includes: a first isolation layer, located in the interval between the bit line and the lower electrode layer along the first direction, the semiconductor layer, the bit line and the first isolation layer form a U-shaped structure; wherein the first sub-lower electrode layer is in contact with the second end, and the second sub-lower electrode layer covers the surface of the first sub-lower electrode layer that is not in contact with the second end.

In some embodiments, the semiconductor structure also includes: a second isolation layer, the second isolation layer is located in the gap between the bit line and the lower electrode layer along the second direction, and is located in the gap adjacent to the second end along the second direction, and the first isolation layer and the second isolation layer are an integrally formed structure.

In some embodiments, along a plane perpendicular to the third direction, the cross-sectional shape of the semiconductor channel is U-shaped, the semiconductor channel includes a channel region connecting the first end and the second end, the channel region extends along the second direction, and the first end and the second end are located on the same side of the channel region along the first direction.

In some embodiments, the channel region has a first side and a second side relative to each other in the first direction, the first end and the second end are located on the first side, the gate structure is located on the second side, and the gate structure corresponds to a plurality of the channel regions arranged at intervals along the second direction.

In some embodiments, the gate structure includes a gate dielectric layer and a gate, both of which extend along the second direction, the gate dielectric layer in different regions has the same width in the first direction, and the gate dielectric layer corresponds to the channel region one by one.

In some embodiments, the gate structure includes a gate dielectric layer and a gate, wherein the gate extends along the second direction; a region of the gate dielectric layer facing the first end is embedded in the gate, and/or a region of the gate dielectric layer facing the second end is embedded in the gate, and along a plane perpendicular to the third direction, the cross-sectional shape of the gate dielectric layer is L-shaped or U-shaped.

In some embodiments, the gate structure has a third side and a fourth side relative to each other in the first direction, one of the channel regions is located on the third side, and the other of the channel regions is located on the fourth side; the first end, the second end, the bit line and the lower electrode layer constitute a combined structure, the combined structure and the channel region correspond one-to-one, and two adjacent combined structures along the first direction are axially symmetrical or centrally symmetrical.

In some embodiments, the first end, the second end, the bit line and the lower electrode layer form a combined structure, the combined structure corresponds to the channel region one by one, and two adjacent combined structures along the second direction are axially symmetrical.

In some embodiments, the material of the channel region includes silicon or silicon germanium.

In some embodiments, at least a portion of the area where the first end contacts the bit line includes a metal semiconductor compound, and at least a portion of the area where the second end contacts the lower electrode layer includes the metal semiconductor compound; or, at least a portion of the area where the first end contacts the bit line includes the metal semiconductor compound, and a portion of the area where the lower electrode layer contacts the second end includes the metal semiconductor compound.

According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, comprising: forming a semiconductor channel and a bit line arranged along a first direction, wherein along the second direction, the semiconductor channel has a first end and a second end opposite to each other, and the bit line extends along a third direction and is in contact with the first end; forming a gate structure extending along the second direction, wherein the gate structure is directly opposite to a portion of a side wall of the semiconductor channel extending along the second direction, the first direction, the second direction and the third direction intersect each other, and the semiconductor channel and the gate structure constitute a transistor; forming a lower electrode layer in contact with the second end, the lower electrode layer comprising: a first region extending along the second direction, and a second region and a third region both extending along the first direction, the first region connecting the second region and the third region, the third region being in contact with the second end, the second region directly opposite to the bit line along the first direction, and a gap between the bit line and the lower electrode layer.

In some embodiments, the step of forming the lower electrode layer includes: providing a substrate; forming a multilayer stacking structure stacked along the third direction on the substrate, wherein the stacking structure includes a first semiconductor layer and a second semiconductor layer stacked in sequence along the third direction; performing a graphical processing on the stacking structure to form a first opening and a second opening alternately arranged along the second direction, wherein the first opening penetrates the stacking structure along the third direction, and the cross-sectional shape of the second opening is U-shaped along a plane perpendicular to the third direction; forming a third isolation layer extending along the second direction, wherein the third isolation layer is located in the first opening and the second opening, and the third isolation layer divides the first opening into a third opening and a fourth opening arranged along the first direction; removing the first semiconductor layer surrounding the third opening, and removing part of the second semiconductor layer surrounding the fourth opening to form a first groove, and the remaining second semiconductor layer serves as a first sub-lower electrode layer; forming a second sub-lower electrode layer, wherein the second sub-lower electrode layer covers the surface of the first sub-lower electrode layer that is not in contact with the third isolation layer, and the first sub-lower electrode layer and the second sub-lower electrode layer constitute the lower electrode layer.

In some embodiments, after forming the first sub-lower electrode layer and before forming the second sub-lower electrode layer, it also includes: removing the third isolation layer and the first semiconductor layer opposite to the third isolation layer along the third direction to expose a portion of the second semiconductor layer, and forming a first gap, the first groove and the first gap are connected to form a first hole; forming a fourth isolation layer, the fourth isolation layer fills the first hole.

In some embodiments, the step of forming the semiconductor channel includes: removing a portion of the first semiconductor layer on a side of the fourth isolation layer away from the first sub-lower electrode layer to form a second hole, the second hole being spaced apart from the first opening; forming a fifth isolation layer filling the second hole; etching the remaining second semiconductor layer to form a second space, the remaining second semiconductor layer exposed by the second space serving as a channel region of the semiconductor channel.

In some embodiments, the step of forming the semiconductor channel further includes: forming a third semiconductor layer on the surface of the remaining second semiconductor layer exposed by the second spacing; removing the second semiconductor layer located on the side of the third opening away from the fourth isolation layer; The third semiconductor layer serves as a channel region of the semiconductor channel.

In some embodiments, the step of forming the gate structure includes: forming the gate structure to fill up the remaining second space.

In some embodiments, after forming the first cavity and before forming the fourth isolation layer, the method further includes: performing metallization treatment on the second semiconductor layer exposed by the first cavity to form the second end including a metal semiconductor compound.

In some embodiments, the step of forming the bit line includes: etching the fourth isolation layer to form a second groove extending along the third direction, the second groove is at least located between the first opening and the second opening, and the remaining fourth isolation layer is at least located between the second groove and the first sub-lower electrode layer; forming the bit line that fills the second groove.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a partial three-dimensional schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

FIG2 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure;

FIG3 is a schematic cross-sectional view of the structure shown in FIG2 along a first cross-sectional direction AA1;

FIG4 is a schematic cross-sectional view of the structure shown in FIG2 along a second cross-sectional direction BB1;

FIG5 is a schematic cross-sectional view of the structure shown in FIG2 along a third cross-sectional direction CC1;

FIG6 is a schematic top view of the semiconductor layer, the bit line and the first isolation layer in the structure shown in FIG2;

FIG. 7 is a schematic diagram of two partial top views of a semiconductor structure provided by an embodiment of the present disclosure;

FIG8 is another partial top view schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

FIG9 is a schematic diagram of two other partial top views of the semiconductor structure provided by an embodiment of the present disclosure;

10 to 34 are partial schematic diagrams corresponding to the steps of a method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure.

Detailed ways

As can be seen from the background art, the electrical performance and integration density of semiconductor structures need to be improved.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the semiconductor structure, the bit line and the lower electrode layer can be located on the same side of the gate structure, and the bit line is directly opposite to the local lower electrode layer to provide a new type of lower electrode layer. In this way, while reducing the space occupied by the bit line and the lower electrode layer as a whole in the semiconductor structure, it is beneficial to increase the surface area of the lower electrode layer. When the capacitor structure is subsequently designed based on the lower electrode layer, the increase in the surface area of the lower electrode layer is beneficial to increase the capacitance of the capacitor structure composed of the lower electrode layer, the capacitor dielectric layer and the upper electrode layer. Moreover, the capacitor dielectric layer and the upper electrode layer can be located in the space surrounded by the bit line and the lower electrode layer, which is beneficial to reduce the size of the storage structure composed of the capacitor structure, the bit line and the transistor, thereby ensuring a high integration density of the semiconductor structure while improving the electrical performance of the semiconductor structure as a whole.

The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings. FIG. 1 is a partial three-dimensional schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure; FIG. 2 is a top view schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure; FIG. 3 is a cross-sectional view of the structure shown in FIG. 2 along the first cross-sectional direction AA1. FIG4 is a schematic cross-sectional view of the structure shown in FIG2 along the second cross-sectional direction BB1; FIG5 is a schematic cross-sectional view of the structure shown in FIG2 along the third cross-sectional direction CC1; FIG6 is a schematic top view of the semiconductor layer, bit line and first isolation layer as a whole in the structure shown in FIG2; FIG7 is a schematic diagram of two partial top-view structures of a semiconductor structure provided in an embodiment of the present disclosure; FIG8 is a schematic diagram of another partial top-view structure of a semiconductor structure provided in an embodiment of the present disclosure; and FIG9 is a schematic diagram of two other partial top-view structures of a semiconductor structure provided in an embodiment of the present disclosure.

1 to 9 , the semiconductor structure includes: a transistor 100 and a bit line 101 arranged along a first direction X; the transistor 100 includes: a gate structure 102 extending along a second direction Y, and a semiconductor channel 103 having a first end 113 and a second end 123 opposite to each other along the second direction Y; the bit line 101 is in contact with the first end 113 and connected, and the bit line 101 extends along a third direction Z, and the first direction X, the second direction Y and the third direction Z intersect each other; a lower electrode layer 104 is in contact with the second end 123 and connected, and the lower electrode layer 104 includes: a first region 114 extending along the second direction Y, and a second region 124 and a third region 134 both extending along the first direction X, the first region 114 connecting the second region 124 and the third region 134, the third region 134 is in contact with the second end 123, the second region 124 is directly opposite to the bit line 101 along the first direction X, and there is a gap between the bit line 101 and the lower electrode layer 104.

It can be understood that, referring to FIG. 1 , a plurality of semiconductor channels 103 can be arranged in an array along the second direction Y and the third direction Z, the semiconductor channels 103 correspond to the lower electrode layer 104 one by one, the bit line 101 can correspond to the plurality of semiconductor channels 103 arranged at intervals along the third direction Z, and the gate structure 102 can correspond to the plurality of semiconductor channels 103 arranged at intervals along the second direction Y, so that the semiconductor channels 103, the bit line 101, the gate structure 102 and the lower electrode layer 104 present a 3D stacked layout morphology, which is conducive to improving the overall integration density of the semiconductor structure. In addition, the second region 124 is directly opposite to the bit line 101 along the first direction X, which means that the plane perpendicular to the first direction X is used as a reference plane, and the orthographic projection of the second region 124 on the reference plane is located in the orthographic projection of the bit line 101 on the reference plane.

It should be noted that in Figure 1, the two semiconductor channels 103 arranged at intervals along the third direction Z correspond to the same bit line 101, and the two semiconductor channels 103 arranged at intervals along the second direction Y correspond to the same gate structure 102. In actual applications, there is no restriction on the number of semiconductor channels 103 corresponding to the same bit line 101 along the third direction Z, and there is no restriction on the number of semiconductor channels 103 corresponding to the same gate structure 102 along the second direction Y.

The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

In some embodiments, referring to FIG. 2 to FIG. 5 , the semiconductor structure may further include: a capacitor dielectric layer 164, covering the surface of the lower electrode layer 104 that is not in contact with the second end 123; and an upper electrode layer 174, covering the side of the capacitor dielectric layer 164 away from the lower electrode layer 104. In this way, the lower electrode layer 104, the capacitor dielectric layer 164 and the upper electrode layer 174 may constitute a capacitor structure, and the capacitor dielectric layer 164 and the upper electrode layer 174 sequentially cover the surface of the lower electrode layer 104 that is not in contact with the second end 123, and the size of the facing area between the lower electrode layer 104 and the upper electrode layer 174 mainly depends on the surface of the lower electrode layer 104 that is not in contact with the second end 123. It can be understood that the new lower electrode layer 104 provided in an embodiment of the present disclosure has a second area 124 and a third area 134 relative to each other along the second direction Y and a first area 114 connecting the second area 124 and the third area 134, that is, the lower electrode layer 104 as a whole presents a U-shaped morphology, which is beneficial for reducing the layout space of the lower electrode layer 104 in the semiconductor structure while increasing the surface area of the lower electrode layer 104, thereby facilitating increasing the facing area of the lower electrode layer 104 and the upper electrode layer 174 to increase the capacitance of the capacitor structure.

In some embodiments, referring to FIGS. 2 to 5 , the semiconductor structure may further include a substrate 110 , wherein the transistor 100 , the bit line 101 , the semiconductor channel 103 , the lower electrode layer 104 , the capacitor dielectric layer 164 and the upper electrode layer 174 are all located on one side of the substrate 110 .

In some embodiments, referring to FIGS. 1 to 9 , the length of the second region 124 in the first direction X is a first length, the length of the third region 134 in the first direction X is a second length, and the second length is greater than or equal to the first length.

It can be understood that, in the second direction Y, the bit line 101 and a part of the third region 134 are directly opposite, and the bit line 101 and the second region 124 are spaced apart in the first direction X, so the first length is smaller than the second length. In this way, it is beneficial to design the second length of the third region 134 to be as long as possible, so as to increase the overall surface area of the lower electrode layer 104.

1 , the lower electrode layer 104 may be a single-layer structure, and the side surfaces of the lower electrode layer 104 close to the semiconductor channel 103 are in contact with the second end 123. In one example, the material of the lower electrode layer 104 is different from that of the semiconductor channel 103.

In other embodiments, referring to FIG. 2 to FIG. 6 , the lower electrode layer 104 may be a double-layer structure, and the lower electrode layer 104 may include a first sub-lower electrode layer 144 and a second sub-lower electrode layer 154. The first sub-lower electrode layer 144, the first end 113 and the second end 123 together constitute a semiconductor layer 143, and the semiconductor layer 143 is an integrally formed structure. The semiconductor structure may also include: a first isolation layer 105, located between the bit line 101 and In the interval of the lower electrode layer 104 along the first direction X, the semiconductor layer 143, the bit line 101 and the first isolation layer 105 form a U-shaped structure; wherein the first sub-lower electrode layer 144 is in contact with the second end 123, and the second sub-lower electrode layer 154 covers the surface of the first sub-lower electrode layer 144 that is not in contact with the second end 123.

It can be understood that the first sub-lower electrode layer 144, the first end 113 and the second end 123 are an integrally formed structure, which is beneficial to reducing the interface state defects between the first sub-lower electrode layer 144 and the second end 123, so as to reduce the contact resistance between the first sub-lower electrode layer 144 and the second end 123. In addition, the lower electrode layer 104 also includes a second sub-lower electrode layer 154 covering the surface of the first sub-lower electrode layer 144 that is not in contact with the second end 123, which is beneficial to improve the overall conductivity of the lower electrode layer 104 without reducing the surface area of the surface of the lower electrode layer 104 that is not in contact with the second end 123.

In one example, the material of the semiconductor layer 143 may be at least one of semiconductor materials such as silicon, carbon, germanium, arsenic, gallium, and indium, and the material of the second lower sub-electrode layer 154 may be a conductive material such as titanium nitride.

In some embodiments, referring to Figures 2 to 5, the semiconductor structure also includes: a second isolation layer 115, the second isolation layer 115 is located in the interval between the bit line 101 and the lower electrode layer 104 along the second direction Y, and is located in the interval between the adjacent second ends 123 along the second direction Y, and the first isolation layer 105 and the second isolation layer 115 are an integrally formed structure.

It can be understood that the first isolation layer 105 and the second isolation layer 115 together constitute the sixth isolation layer 155, so that while achieving insulation between the bit line 101 and the lower electrode layer 104, that is, insulation between the bit line 101 and the capacitor structure, the insulation between the bit line 101 and the second end 123 is also achieved. In addition, the sixth isolation layer 155 also extends along the third direction Z to achieve insulation between adjacent second ends 123 along the third direction Z.

In some embodiments, referring to Figures 7 to 9, along a plane perpendicular to the third direction Z, the cross-sectional shape of the semiconductor channel 103 is U-shaped, and the semiconductor channel 103 includes a channel region 133 connecting the first end 113 and the second end 123, the channel region 133 extends along the second direction Y, and the first end 113 and the second end 123 are located on the same side of the channel region 133 along the first direction X.

In some embodiments, the material of the first end 113, the material of the second end 123, and the material of the channel region 133 may be the same, and the first end 113, the second end 123, and the channel region 133 may be an integrally formed structure. In one example, the material of the first end 113, the material of the second end 123, and the material of the channel region 133 may all be silicon.

In other embodiments, the material of the channel region 133 may be silicon germanium, which is advantageous for improving the carrier mobility of the channel region 133 by using silicon germanium to improve the on/off ratio of the transistor 100 (see FIG. 1 ), thereby facilitating improving the electrical performance of the semiconductor structure.

In some embodiments, in combination with reference Figures 1 and 7, the channel region 133 has a first side a and a second side b relative to each other in the first direction X, the first end 113 and the second end 123 are located on the first side a, the gate structure 102 is located on the second side b, and the gate structure 102 corresponds to a plurality of channel regions 133 arranged at intervals along the second direction Y.

It should be noted that FIGS. 1 to 6 all take the gate structure 102 and the two channel regions 133 arranged at intervals along the second direction Y as examples. In actual applications, there is no limitation on the number of the gate structure 102 and the channel regions 133 arranged at intervals along the second direction Y.

The gate structure 102 includes at least the following four embodiments:

In some embodiments, referring to FIGS. 1 to 8 , the gate structure 102 includes a gate dielectric layer 112 and a gate 122 , both of which extend along the second direction Y, the gate dielectric layer 112 in different regions have the same width in the first direction X, and the gate dielectric layer 112 corresponds one-to-one to the channel region 133 .

In some other embodiments, referring to 9a in Figure 9, the gate structure 102 includes a gate dielectric layer 112 and a gate 122, wherein the gate 122 extends along the second direction Y; a region of the gate dielectric layer 112 facing the first end 113 is embedded in the gate 122, and a region of the gate dielectric layer 112 facing the second end 123 is embedded in the gate 122, and along a plane perpendicular to the third direction Z, the cross-sectional shape of the gate dielectric layer 112 is U-shaped.

It can be understood that the gate dielectric layer 112 opposite the first end 113 and the second end 123 are both embedded in the gate 122, so that different regions of the gate dielectric layer 112 along the second direction Y have different widths in the first direction X, which is beneficial to increase the width of the gate dielectric layer 112 opposite the first end 113 and the second end 123 in the first direction X, thereby helping to reduce the leakage current of the transistor 100 (refer to Figure 1) to improve the electrical performance of the semiconductor structure.

In some other embodiments, referring to 9b in FIG. 9 , the gate structure 102 includes a gate dielectric layer 112 and a gate 122, wherein the gate 122 extends along the second direction Y; a region of the gate dielectric layer 112 directly opposite to the second end 123 is embedded in the gate 122, and a cross-sectional shape of the gate dielectric layer 112 is L-shaped along a plane perpendicular to the third direction Z. In this way, it is beneficial to increase the width of the gate dielectric layer 112 directly opposite to the second end 123 in the first direction X, thereby facilitating the reduction of the leakage current of the transistor 100 (refer to FIG. 1 ).

In some further embodiments, the region of the gate dielectric layer 112 facing the first end 113 is embedded in the gate 122, and the cross-sectional shape of the gate dielectric layer 112 is also L-shaped along a plane perpendicular to the third direction Z. In this way, the width of the gate dielectric layer 112 facing the first end 113 in the first direction X is increased, thereby facilitating the reduction of the leakage current of the transistor 100 (see FIG. 1 ).

In the above embodiment, the gate 122 can be in contact with a plurality of gate dielectric layers 112 arranged at intervals along the second direction Y, that is, a plurality of transistors 100 can share the same gate 122. An embodiment of the present disclosure does not limit the number of gate dielectric layers 112 arranged at intervals along the second direction Y to which the gate 122 is in contact.

The arrangement of the bit line 101 , the lower electrode layer 104 and the transistor 100 is described in detail below.

In some embodiments, referring to 7a in Figure 7, the gate structure 102 has a third side c and a fourth side d relative to each other in the first direction X, a channel region 133 is located on the third side c, and the other channel region 133 is located on the fourth side d; the first end 113, the second end 123, the bit line 101 and the lower electrode layer 104 constitute a combined structure, the combined structure and the channel region 133 correspond one to one, and two adjacent combined structures along the first direction X are centrally symmetrical.

In some other embodiments, referring to 7b in Figure 7, the gate structure 102 has a third side c and a fourth side d relative to each other in the first direction X, a channel region 133 is located on the third side c, and the other channel region 133 is located on the fourth side d; the first end 113, the second end 123, the bit line 101 and the lower electrode layer 104 constitute a combined structure, the combined structure and the channel region 133 correspond one to one, and two adjacent combined structures along the first direction X are axially symmetrical.

In the above two embodiments, in the gate structure 102, the gate 122 has a gate dielectric layer 112 on both opposite sides along the first direction X, that is, two adjacent transistors 100 along the first direction X (refer to Figure 1) can share the same gate 122, which is beneficial to further improve the integration density of the semiconductor structure.

In some other embodiments, referring to FIG8 , the first end 113, the second end 123, the bit line 101 and the lower electrode layer 104 form a combined structure, the combined structure corresponds to the channel region 133 one by one, and two adjacent combined structures along the second direction Y are axially symmetrical. It can be understood that the first ends 113 in adjacent combined structures are adjacent, that is, the second regions 124 in adjacent combined structures are adjacent.

In some further embodiments, referring to FIG1 , a plurality of combined structures may be sequentially spaced and arranged along the second direction Y. It is understood that the second end 123 of one of the adjacent combined structures is adjacent to the first end 113 of the other, that is, the third region 134 of one of the adjacent combined structures is adjacent to the bit line 101 and the second region 124 of the other.

It should be noted that the L-shaped or U-shaped gate dielectric layer 112 illustrated in FIG. 9 may also be applicable to the semiconductor structures shown in FIG. 1 to FIG. 8 .

In some embodiments, referring to FIGS. 7 to 9 , at least a portion of the area where the first end 113 contacts the bit line 101 may include a metal semiconductor compound 153, and at least a portion of the area where the second end 123 contacts the lower electrode layer 104 may include a metal semiconductor compound 153. It is understood that the sidewalls of the metal semiconductor compound 153 in the second end 123 extending along the first direction X are wrapped by the second isolation layer 115 (refer to FIG. 3 ).

It should be noted that, in actual applications, only at least a portion of the area where the first end 113 contacts the bit line 101 may include the metal semiconductor compound 153; or, only at least a portion of the area where the second end 123 contacts the lower electrode layer 104 may include the metal semiconductor compound 153; or, referring to Figures 1 to 6, neither the first end 113 nor the second end 123 contains the metal semiconductor compound 153.

In other embodiments, with continued reference to FIGS. 7 to 9 , at least a portion of the area where the first end 113 contacts the bit line 101 may include the metal semiconductor compound 153, and a portion of the area where the lower electrode layer 104 contacts the second end 123 may include the metal semiconductor compound 153. It is understood that the sidewalls of the metal semiconductor compound 153 in the lower electrode layer 104 extending along the first direction X are wrapped by the capacitor dielectric layer 164.

It should be noted that, in practical applications, only at least a portion of the area where the first end 113 contacts the bit line 101 may include the metal semiconductor compound 153; or only at least a portion of the area where the lower electrode layer 104 contacts the second end 123 may include the metal semiconductor compound 153. compound 153; or, referring to FIGS. 1 to 6 , neither the first end 113 nor the lower electrode layer 104 includes the metal semiconductor compound 153.

In addition, in the above embodiment, at least a portion of the area where the first end 113 contacts the bit line 101 includes a metal semiconductor compound 153. The metal semiconductor compound 153 has a relatively small resistivity compared to unmetallized semiconductor materials. Therefore, compared to the first end 113 that has not been metallized, the resistivity of the first end 113 is smaller, which is beneficial to reducing the resistance of the first end 113 and reducing the contact resistance between the first end 113 and the bit line 101, so as to further improve the electrical performance of the semiconductor structure. Similarly, at least a portion of the area where the second end 123 contacts the lower electrode layer 104 includes the metal semiconductor compound 153. Compared with the second end 123 that has not been metallized, the resistivity of the second end 123 is smaller, which is beneficial to reducing the resistance of the second end 123; or, at least a portion of the area where the lower electrode layer 104 contacts the second end 123 includes the metal semiconductor compound 153. Compared with the lower electrode layer 104 that has not been metallized, the resistivity of the lower electrode layer 104 is smaller, which is beneficial to reducing the resistance of the lower electrode layer 104. In this way, it is beneficial to reduce the contact resistance between the second end 123 and the lower electrode layer 104, so as to further improve the electrical performance of the semiconductor structure.

In some embodiments, a portion of the area where the first end 113 contacts the bit line 101 includes a metal semiconductor compound 153; in other embodiments, according to actual needs, the entire area where the first end 113 contacts the bit line 101 may include a metal semiconductor compound 153. In some embodiments, a portion of the area where the second end 123 contacts the lower electrode layer 104 includes a metal semiconductor compound 153; in other embodiments, according to actual needs, the entire area where the second end 123 contacts the lower electrode layer 104 may include a metal semiconductor compound 153.

It should be noted that, in order to schematically illustrate the metal semiconductor compound 153, FIG. 7 to FIG. 9 use different filling methods to draw the first end 113 that does not contain the metal semiconductor compound 153, and the actual metal semiconductor compound 153 is a part of the first end 113. Similarly, the metal semiconductor compound 153 located in the second end 123 is a part of the second end 123, or the metal semiconductor compound 153 located in the first sub-lower electrode layer 144 is a part of the first sub-lower electrode layer 144.

In some embodiments, the semiconductor structure may further include: a fifth isolation layer 145, located between adjacent gates 122 along the third direction Z to achieve insulation between adjacent gates 122, and the fifth isolation layer 145 also surrounds the sidewalls of the gate dielectric layer 112 extending along the first direction X and surrounds the sidewalls of the channel region 133 extending along the first direction X to achieve insulation between adjacent channel regions 133; a first dielectric layer 116, surrounds at least a portion of the sidewalls of the first end 113 extending along the first direction X and surrounds at least a portion of the sidewalls of the second end 123 extending along the first direction X to achieve insulation between the first end 113 and the second end 123.

It should be noted that, in order to illustrate the positional relationship between the first end 11 and the second end 123 and the first dielectric layer 116 , the first dielectric layer 116 is drawn in a perspective manner in FIG. 2 .

In summary, the bit line 101 and the lower electrode layer 104 can be located on the same side of the gate structure 102, and the bit line 101 is directly opposite to the local lower electrode layer 104, so as to provide a new type of lower electrode layer 104, so as to reduce the space occupied by the bit line 101 and the lower electrode layer 104 as a whole in the semiconductor structure, while increasing the surface area of the lower electrode layer 104. When the capacitor structure is subsequently designed based on the lower electrode layer 104, the increase in the surface area of the lower electrode layer 104 is conducive to increasing the capacitance of the capacitor structure composed of the lower electrode layer 104, the capacitor dielectric layer 164 and the upper electrode layer 174. Moreover, the capacitor dielectric layer 164 and the upper electrode layer 174 can be located in the space surrounded by the bit line 101 and the lower electrode layer 104, which is conducive to reducing the size of the storage structure composed of the capacitor structure, the bit line 101 and the transistor 100, thereby ensuring a high integration density of the semiconductor structure while improving the electrical performance of the semiconductor structure as a whole.

Another embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which is used to prepare the semiconductor structure provided by the above-mentioned embodiment. The method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described in detail below in conjunction with Figures 1 to 34. Figures 10 to 34 are partial schematic diagrams corresponding to each step of the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.

It should be noted that the parts that are the same or corresponding to the above-mentioned embodiments are not described in detail here. In addition, some of the drawings in Figures 10 to 34 are partial top view schematic diagrams corresponding to each step of the manufacturing method of the semiconductor structure; the remaining drawings in Figures 10 to 34 are partial cross-sectional schematic diagrams of the partial top view schematic diagram along the first cross-sectional direction AA1 and/or the second cross-sectional direction BB1 and/or the third cross-sectional direction CC1.

Referring to FIGS. 1 to 31 , a method for manufacturing a semiconductor structure includes: forming a semiconductor channel 103 and a bit line 101 arranged along a first direction X, wherein the semiconductor channel 103 has a first end 113 and a second end 123 opposite to each other along a second direction Y, and the bit line 101 extends along a third direction Z and is in contact with and connected to the first end 113; forming a gate structure 102 extending along the second direction Y, wherein the gate structure 102 is directly opposite to a portion of a sidewall of the semiconductor channel 103 extending along the second direction Y, wherein the first direction X, the second direction Y, and the third direction Z intersect in pairs, and the semiconductor channel 103 and the gate structure 102 constitute a transistor 100; forming a lower electrode layer 104 in contact with and connected to the second end 123, wherein the lower electrode layer 104 includes: a first region 114 extending along the second direction Y, and a second region 124 and a third region 134 both extending along the first direction X, wherein the first region 114 is connected to the second region 124 and the third region 134 both extending along the first direction X, wherein the first region 114 is connected to the second region 124 and the third region 134 The region 124 and the third region 134 are in contact with the second end 123 . The second region 124 is directly opposite to the bit line 101 along the first direction X, and there is a gap between the bit line 101 and the lower electrode layer 104 .

The steps of forming the semiconductor structure are described in detail below. It should be noted that, for the convenience of description, the semiconductor structure shown in FIG. 2 to FIG. 5 is mainly used as an example for explanation.

In some embodiments, forming the lower electrode layer 104 includes the following steps:

Referring to Figures 10 and 11, a substrate 110 is provided; a multilayer stacking structure 120 stacked along a third direction Z is formed on the substrate 110, and along the third direction Z, the stacking structure 120 includes a first semiconductor layer 130 and a second semiconductor layer 140 stacked in sequence; the stacking structure 120 is patterned to form a first opening 107 and a second opening 117 alternately arranged along the second direction Y, the first opening 107 penetrates the stacking structure 120 along the third direction Z, and along a plane perpendicular to the third direction Z, the cross-sectional shape of the second opening 117 is U-shaped.

It should be noted that the first opening 107 and the second opening 117 penetrate the thickness of the stack structure 120 in the third direction Z.

In one example, the material of the first semiconductor layer 130 may be silicon germanium, and the material of the second semiconductor layer 140 may be silicon.

12 to 15 , a third isolation layer 125 extending along the second direction Y is formed. The third isolation layer 125 is located in the first opening 107 and the second opening 117 . The third isolation layer 125 divides the first opening 107 into a third opening 127 and a fourth opening 137 arranged along the first direction X.

12 to 17 , the first semiconductor layer 130 surrounding the third opening 127 is removed, and a portion of the second semiconductor layer 140 surrounding the fourth opening 137 is removed to form a first groove 147 , and the remaining second semiconductor layer 140 serves as a first lower sub-electrode layer 144 (see FIG. 6 ).

The formation of the third isolation layer 125 and the first groove 147 will be described in detail below.

14 and 15 , the third isolation layer 125 located in the first opening 107 and the second opening 117 extends along the third direction Z and penetrates the thickness of the stack structure 120 (see FIG. 10 ) in the third direction Z. As shown in FIG.

In some embodiments, after forming the first opening 107 and the second opening 117 and before forming the lower electrode layer 104, the manufacturing method may include the following steps:

12 and 13 , a second dielectric layer 126 is formed. The second dielectric layer 126 fills the third opening 127 and the fourth opening 137 , and the second dielectric layer 126 also covers the top surface of the stack structure 120 away from the substrate 110 .

Referring to FIG. 10 , the remaining stacked structure 120 includes a first portion 160 and a second portion 170 sequentially arranged along the first direction X, a portion of the first opening 107 and a portion of the second opening 117 are located in the first portion 160, the remaining first opening 107 and the remaining second opening 117 are located in the second portion 170, and the second opening 117 is a U-shaped opening, and the notch of the U-shaped opening is located in the second portion 170. The space occupied by the second semiconductor layer 140 in the first portion 160 is subsequently used to form a gate structure 102 and a semiconductor channel 103, and the semiconductor channels 103 along the second direction Y are spaced apart, so that the gate structure 102 corresponds to a plurality of semiconductor channels 103 spaced apart along the second direction Y. In addition, the space occupied by the second semiconductor layer 140 in the second portion 170 is subsequently used to form a bit line 101 and a lower electrode layer 104.

10 to 13 , after forming the second dielectric layer 126 , the first semiconductor layer 130 in the first portion 160 is removed to form a first gap (not shown), that is, the first semiconductor layer 130 surrounding the third opening 127 is removed to form a third dielectric layer 136 filling the first gap.

12 to 15 , a portion of the second dielectric layer 126 that is in contact with the third dielectric layer 136 is etched to form a second gap (not shown in the figures). The second gap located in the first opening 107 and the second opening 117 penetrates the thickness of the stacked structure 120 (refer to FIG. 10 ) in the third direction Z, and the remaining second gap exposes the top surface of the second semiconductor layer 140 that is farthest from the substrate 110; a third isolation layer 125 that fills the second gap is formed.

Referring to Figures 14 to 17, the first semiconductor layer 130 that is not directly opposite to the third isolation layer 125 along the third direction Z is removed to form a third gap (not shown in the figure): a fourth dielectric layer 146 that fills the third gap is formed; in the second portion 170, the second semiconductor layer 140 that is in contact with the third isolation layer 125 has a first end and a second end in the second direction Y, and removing part of the second semiconductor layer 140 that surrounds the fourth opening 137 includes: removing any one of the first end and the second end, and removing the fourth dielectric layer 146 that is directly opposite to the removed second semiconductor layer 140 to form a first groove 147, and the remaining second semiconductor layer 140 serves as the first sub-lower electrode layer 144 (refer to Figure 6). Needed It should be noted that the above example takes the formation of the fourth dielectric layer 146 first and then the formation of the first groove 147 as an example. In practical applications, the order of forming the fourth dielectric layer 146 and the first groove 147 can be adjusted according to actual needs. In addition, the remaining second semiconductor layer 140 refers to the remaining second semiconductor layer 140 in the second portion 170.

In one example, the material of the second dielectric layer 126 , the material of the third dielectric layer 136 , and the material of the fourth dielectric layer 146 may all be silicon oxide.

In some embodiments, after forming the first sub-lower electrode layer 144 and before forming the second sub-lower electrode layer 154, the manufacturing method may further include: referring to Figures 18 and 19, removing the third isolation layer 125 and the first semiconductor layer 130 opposite to the third isolation layer 125 along the third direction Z to expose a portion of the second semiconductor layer 140, and forming a first spacer 157, the first groove 147 and the first spacer 157 are connected to form a first hole 167.

It can be understood that the first semiconductor layer 130 directly opposite to the third isolation layer 125 along the third direction Z refers to: taking a plane perpendicular to the third direction Z as a reference plane, the first semiconductor layer 130 whose orthographic projection on the reference plane is located in the orthographic projection of the third isolation layer 125 on the reference plane. Referring to FIGS. 18 to 21 , the fourth isolation layer 135 is formed, and the fourth isolation layer 135 fills the first cavity 167.

In some embodiments, after forming the fourth isolation layer 135 and before forming the second lower sub-electrode layer 154 , the step of forming the semiconductor channel 103 may include:

Referring to Fig. 22, a portion of the first semiconductor layer 130 on a side of the fourth isolation layer 135 away from the first sub-lower electrode layer 144 is removed to form a second cavity 177, and the second cavity 177 is spaced apart from the first opening 107 (see Fig. 16). In some embodiments, in the step of removing a portion of the first semiconductor layer 130 on a side of the fourth isolation layer 135 away from the first sub-lower electrode layer 144, the second dielectric layer 126 and the third dielectric layer 136 that are opposite to the removed first semiconductor layer 130 along the third direction Z are also removed.

It can be understood that the second dielectric layer 126 directly opposite to the removed first semiconductor layer 130 along the third direction Z refers to: taking the plane perpendicular to the third direction Z as the reference plane, the second dielectric layer 126 whose orthographic projection on the reference plane is located in the orthographic projection of the removed first semiconductor layer 130 on the reference plane. The third dielectric layer 136 directly opposite to the removed first semiconductor layer 130 along the third direction Z refers to: taking the plane perpendicular to the third direction Z as the reference plane, the orthographic projection on the reference plane is located in the orthographic projection of the removed first semiconductor layer 130 on the reference plane.

23 and 24 , a fifth isolation layer 145 filling the second holes 177 is formed.

How to form the channel region 133 is described in detail below.

In some embodiments, referring to FIG. 24 and FIG. 25 , the remaining second semiconductor layer 140 is etched to form a second spacer 187, and the remaining second semiconductor layer 140 exposed by the second spacer 187 serves as the channel region 133 of the semiconductor channel 103. In this way, the first end 113, the second end 123, and the channel region 133 can be an integrally formed structure. In one example, the material of the channel region 133 is silicon.

In some other embodiments, after forming the second spacer 187 , the step of forming the semiconductor channel 103 may further include: with reference to FIGS. 25 and 26 , forming a third semiconductor layer 150 on the surface of the remaining second semiconductor layer 140 exposed by the second spacer 187 .

In some implementations, the method for forming the third semiconductor layer 150 includes: forming the third semiconductor layer 150 by an epitaxial growth process based on the remaining second semiconductor layer 140. In this way, it is beneficial to improve the density of the formed third semiconductor layer 150 and reduce the defect state density of the third semiconductor layer 150 itself. When the third semiconductor layer 150 is subsequently used as the channel region 133, it is beneficial to improve the electrical performance of the channel region 133, so as to improve the on/off ratio of the transistor 100 (refer to FIG. 1). In one example, the material of the third semiconductor layer 150, that is, the material of the channel region 133 is silicon germanium.

In the above two embodiments of forming the channel region 133 , the step of forming the gate structure 102 may include: forming the gate structure 102 to fill the remaining second space 187 .

In some embodiments, continuing to refer to Figures 25 and 26, after forming the third semiconductor layer 150 and before removing the remaining second semiconductor layer 140, the step of forming the gate structure 102 may include: forming a gate dielectric layer 112 on a side of the third semiconductor layer 150 away from the second semiconductor layer 140, the gate dielectric layer 112 corresponding one-to-one to the third semiconductor layer 150; forming a gate 122, the gate 122 and the gate dielectric layer 112 together fill the remaining second gap 187.

27 , the second semiconductor layer 140 located on the side of the third opening 127 (see FIG. 16 ) away from the fourth isolation layer 135 is removed. The third semiconductor layer 150 serves as the channel region 133 of the semiconductor channel 103 .

It should be noted that the removed second semiconductor layer 140 is directly opposite to the third semiconductor layer 150 along the first direction X, and the remaining second semiconductor layer 140 located on the side of the fourth isolation layer 135 close to the third opening 127 serves as the initial first end and the initial second end 123 (refer to FIG. 5). In conjunction with FIG. 26 and FIG. 27, in the step of removing the second semiconductor layer 140 located on the side of the third opening 127 (refer to FIG. 16) away from the fourth isolation layer 135, a portion of the second dielectric layer 126 and a portion of the third dielectric layer 136 are also removed to form a through hole 108, and the through hole 108 corresponds to the third semiconductor layer 150 one by one.

It can be understood that the removed second semiconductor layer 140 and the third semiconductor layer 150 are opposite to each other along the first direction X, which means that: taking the plane perpendicular to the first direction X as the reference plane, the orthographic projection of the third semiconductor layer 150 on the reference plane is located in the orthographic projection of the removed second semiconductor layer 140 on the reference plane.

27 and 28, a fifth dielectric layer 156 is formed, and the fifth dielectric layer 156 fills the through hole 108. It can be understood that the fifth dielectric layer 156 and the remaining second dielectric layer 126 and third dielectric layer 136 together constitute the first dielectric layer 116 in the structure shown in FIGS.

The steps of forming the metal semiconductor compound 153 and the second lower sub-electrode layer are described in detail below.

In some embodiments, referring to Figures 18 and 19, after forming the first hole 167 and before forming the fourth isolation layer 135, the manufacturing method further includes: metallizing the second semiconductor layer 140 exposed by the first hole 167 to form a second end 123 (refer to Figure 7) containing a metal semiconductor compound 153 (refer to Figure 7).

It can be understood that the second semiconductor layer 140 exposed by the first hole 167 includes the second end 123 and the first end 113 formed by subsequently etching the initial first end, and in the step of metallizing the second semiconductor layer 140 exposed by the first hole 167, not only the first end 113 but also the second end 123 includes the metal semiconductor compound 153. After the metal semiconductor compound is formed, the second lower sub-electrode layer is formed.

In some other embodiments, forming the metal semiconductor compound 153 and the second lower sub-electrode layer comprises the following steps:

27 and 28 , the fourth dielectric layer 146 and the second dielectric layer 126 located on the side of the fourth isolation layer 135 away from the fifth dielectric layer 156 are removed to expose the surface of the first lower sub-electrode layer 144 that is not in contact with the fourth isolation layer 135 .

It is understandable that the second semiconductor layer 140 located on the side of the fourth isolation layer 135 close to the fifth dielectric layer 156 can be used as the initial first end 163 and the second end 123, and the first end 113 is subsequently formed by etching the initial first end 163 (see FIG. 4).

Referring to Figures 29 and 30, an initial second sub-lower electrode layer 184 is formed, and the initial second sub-lower electrode layer 184 conformally covers the surface of the first sub-lower electrode layer 144 that is not in contact with the fourth isolation layer 135; a sixth dielectric layer 166 is formed, and the sixth dielectric layer 166 is located on the surface of the initial second sub-lower electrode layer 184 away from the first sub-lower electrode layer 144, and the top surface of the sixth dielectric layer 166 away from the substrate 110 is flush with the top surface of the fourth isolation layer 135 away from the substrate 110.

29 to 32 , the fourth isolation layer 135 is removed to form a third cavity 118 , and the second semiconductor layer 140 exposed by the third cavity 118 is metallized to form a first end 113 (see FIG. 7 ) including a metal semiconductor compound 153 (see FIG. 7 ).

It can be understood that the second semiconductor layer 140 exposed by the third hole 118 includes a first end 113 and a first end 113 formed by subsequent etching of the initial first end 163, and in the step of metallizing the second semiconductor layer 140 exposed by the third hole 118, not only the first end 113 contains the metal semiconductor compound 153, but also the second end 123 contains the metal semiconductor compound 153.

In the step of removing the fourth isolation layer 135, the initial second sub-lower electrode layer 184 located on the side wall of the fourth isolation layer 135 extending along the third direction Z is also removed to form a second sub-lower electrode layer 154, so that adjacent lower electrode layers 104 in the third direction Z are spaced apart from each other, and adjacent lower electrode layers 104 in the second direction Y are spaced apart from each other.

With reference to FIGS. 31 to 34 , a sixth isolation layer 155 is formed, and the sixth isolation layer 155 fills the third cavity 118; the sixth dielectric layer 166 is removed to expose the second sub-lower electrode layer 154; a capacitor dielectric layer 164 is formed, and the capacitor dielectric layer 164 covers the surface of the second sub-lower electrode layer 154 away from the first sub-lower electrode layer 144, and the sidewall of the sixth isolation layer 155 extending in the third direction Z; and an upper electrode layer 174 is formed, and the upper electrode layer 174 covers a side of the capacitor dielectric layer 164 away from the lower electrode layer 104. In one example, the top surface of the upper electrode layer 174 away from the substrate 110 is not lower than the top surface of the sixth isolation layer 155 away from the substrate 110.

In actual applications, referring to Figure 17, after the first sub-lower electrode layer 144 is formed, the fourth dielectric layer 146 and the second dielectric layer 126 located on the side of the third isolation layer 125 away from the third dielectric layer 136 can be removed to expose the first sub-lower electrode layer 144; then, the second sub-lower electrode layer 154 is formed, and the second sub-lower electrode layer 154 covers the surface of the first sub-lower electrode layer 144 that is not in contact with the third isolation layer 125. The first sub-lower electrode layer 144 and the second sub-lower electrode layer 154 constitute the lower electrode layer 104.

In some embodiments, in combination with reference figures 33, 34, and 2 to 5, the step of forming the bit line 101 may include: etching the sixth isolation layer 155 to form a third groove (not shown in the figure) extending along the third direction Z, the third groove is at least located between the first opening 107 (refer to Figure 12) and the second opening 117 (refer to Figure 12), and the remaining sixth isolation layer 155 is at least located between the third groove and the first sub-lower electrode layer 144; forming the bit line 101 that fills the third groove.

It can be understood that in the step of etching the sixth isolation layer 155 , the initial first end 163 is also etched to form the first end 113 .

In some other embodiments, referring to FIG. 21 , after forming the fourth isolation layer 135 and before forming the gate structure 102, the bit line 101 can be formed. The step of forming the bit line 101 may include: etching the fourth isolation layer 135 to form a second groove (not shown in the figure) extending along the third direction Z, the second groove being at least located between the first opening 107 (refer to FIG. 12 ) and the second opening 117 (refer to FIG. 12 ), and the remaining fourth isolation layer 135 being at least located between the second groove and the first sub-lower electrode layer 144; forming the bit line 101 that fills the second groove. It is understandable that in the step of etching the fourth isolation layer 135, the initial first end 163 is also etched to form the first end 113.

It should be noted that in the manufacturing method provided in another embodiment of the present disclosure, after forming the first sub-lower electrode layer 144, there is no restriction on the order of forming the second sub-lower electrode layer 154, forming the gate structure 102, and forming the semiconductor channel 103 and the bit line 101. The above embodiment is only a specific embodiment of forming the second sub-lower electrode layer 154, the gate structure 102, the semiconductor channel 103 and the bit line 101.

In summary, in the semiconductor structure formed by the manufacturing method provided by another embodiment of the present disclosure, a new type of lower electrode layer 104 is formed, and the bit line 101 and the lower electrode layer 104 can be located on the same side of the gate structure 102, and the bit line 101 is directly opposite to the local lower electrode layer 104, so that while reducing the space occupied by the bit line 101 and the lower electrode layer 104 as a whole in the semiconductor structure, it is beneficial to increase the surface area of the lower electrode layer 104. When the capacitor structure is subsequently designed based on the lower electrode layer 104, the increase in the surface area of the lower electrode layer 104 is beneficial to increase the capacitance of the capacitor structure composed of the lower electrode layer 104, the capacitor dielectric layer 164 and the upper electrode layer 174. Moreover, the capacitor dielectric layer 164 and the upper electrode layer 174 can be located in the space surrounded by the bit line 101 and the lower electrode layer 104, which is beneficial to reduce the size of the storage structure composed of the capacitor structure, the bit line 101 and the transistor 100, thereby ensuring a high integration density of the semiconductor structure while improving the electrical performance of the semiconductor structure as a whole.

Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims (20)

1. A semiconductor structure comprising:

   Transistors (100) and bit lines (101) arranged along a first direction (X);

   The transistor (100) comprises: a gate structure (102) extending along a second direction (Y), and a semiconductor channel (103) having a first end (113) and a second end (123) opposite to each other along the second direction (Y);

   The bit line (101) is in contact with and connected to the first end (113), and the bit line (101) extends along a third direction (Z), and the first direction (X), the second direction (Y), and the third direction (Z) intersect in pairs;

   A lower electrode layer (104) is in contact with and connected to the second end (123), and the lower electrode layer (104) comprises: a first region (114) extending along the second direction (Y), and a second region (124) and a third region (134) both extending along the first direction, the first region (114) connecting the second region (124) and the third region (134), the third region (134) in contact with and connected to the second end (123), the second region (124) facing the bit line (101) along the first direction (X), and a gap is provided between the bit line (101) and the lower electrode layer (104).
2. The semiconductor structure as claimed in claim 1, wherein the length of the second region (124) in the first direction (X) is a first length, the length of the third region (134) in the first direction (X) is a second length, and the second length is greater than or equal to the first length.
3. The semiconductor structure according to claim 1 or 2, wherein the lower electrode layer (104) comprises a first sub-lower electrode layer (144) and a second sub-lower electrode layer (154), the first sub-lower electrode layer (144), the first end (113) and the second end (123) together constitute a semiconductor layer (143), and the semiconductor layer (143) is an integrally formed structure; the semiconductor structure further comprises:

   A first isolation layer (105) is located in the interval between the bit line (101) and the lower electrode layer (104) along the first direction (X), and the semiconductor layer (143), the bit line (101) and the first isolation layer (105) form a U-shaped structure;

   The first sub-lower electrode layer (144) is in contact with the second end (120), and the second sub-lower electrode layer (154) covers the surface of the first sub-lower electrode layer (144) that is not in contact with the second end (123).
4. The semiconductor structure as described in claim 3 further includes: a second isolation layer (115), the second isolation layer (115) is located in the interval between the bit line (101) and the lower electrode layer (104) along the second direction (Y), and is located in the interval adjacent to the second end (123) along the second direction (Y), and the first isolation layer (105) and the second isolation layer (115) are an integrally formed structure.
5. A semiconductor structure as claimed in claim 1 or 2, wherein along a plane perpendicular to the third direction (Z), the cross-sectional shape of the semiconductor channel (103) is U-shaped, the semiconductor channel (103) includes a channel region (133) connecting the first end (113) and the second end (123), the channel region (133) extends along the second direction (Y), and the first end (113) and the second end (123) are located on the same side of the channel region (133) along the first direction (X).
6. The semiconductor structure as claimed in claim 5, wherein the channel region (133) has a first side (a) and a second side (b) relative to each other in the first direction (X), the first end (113) and the second end (123) are located on the first side (a), the gate structure (102) is located on the second side (b), and the gate structure (102) corresponds to a plurality of the channel regions (133) arranged at intervals along the second direction (Y).
7. The semiconductor structure according to claim 6, wherein the gate structure (102) comprises a gate dielectric layer (112) and a gate (122), the gate dielectric layer (112) and the gate (122) both extend along the second direction (Y), the gate dielectric layer (112) in different regions has the same width in the first direction (X), and the gate dielectric layer (112) corresponds to the channel region (133) one by one.
8. The semiconductor structure according to claim 6, wherein the gate structure (102) comprises a gate dielectric layer (112) and a gate (122), wherein the gate (122) extends along the second direction (Y); a region of the gate dielectric layer (112) directly facing the first end (113) is embedded in the gate (122), and/or a region of the gate dielectric layer (112) directly facing the second end (123) is embedded in the gate (122), and along a plane perpendicular to the third direction (Z), the cross-sectional shape of the gate dielectric layer (112) is L Shape or U-shape.
9. A semiconductor structure as claimed in claim 7 or 8, wherein the gate structure (102) has a third side (c) and a fourth side (d) relative to each other in the first direction (X), one of the channel regions (133) is located on the third side (c), and the other of the channel regions (133) is located on the fourth side (d); the first end (113), the second end (123), the bit line (101) and the lower electrode layer (104) constitute a combined structure, the combined structure and the channel region (133) correspond one to one, and two adjacent combined structures along the first direction (X) are axially symmetrical or centrally symmetrical.
10. The semiconductor structure according to claim 7 or 8, wherein the first end (113), the second end (123), the bit line (101) and the lower electrode layer (104) constitute a combined structure, the combined structure and the channel region (133) correspond one to one, and two adjacent combined structures along the second direction (Y) are axially symmetrical.
11. The semiconductor structure according to claim 5, wherein the material of the channel region (133) comprises silicon or silicon germanium.
12. A semiconductor structure as claimed in claim 1, wherein at least a portion of the area where the first end (113) contacts the bit line (101) includes a metal semiconductor compound (153), and at least a portion of the area where the second end (123) contacts the lower electrode layer (104) includes the metal semiconductor compound (153); or, at least a portion of the area where the first end (113) contacts the bit line (101) includes the metal semiconductor compound (153), and a portion of the area where the lower electrode layer (104) contacts the second end (123) includes the metal semiconductor compound (153).
13. A method for manufacturing a semiconductor structure, comprising:

    A semiconductor channel (103) and a bit line (101) arranged along a first direction (X) are formed, wherein along a second direction (Y), the semiconductor channel (103) has an opposite first end (113) and a second end (123), and the bit line (101) extends along a third direction (Z) and is in contact with and connected to the first end (113);

    forming a gate structure (102) extending along a second direction (Y), the gate structure (102) being directly opposite to a portion of a side wall of the semiconductor channel (103) extending along the second direction (Y), the first direction (X), the second direction (Y) and the third direction (Z) intersecting in pairs, and the semiconductor channel (103) and the gate structure (102) forming a transistor (100);

    A lower electrode layer (104) is formed that is in contact with and connected to the second end (123), and the lower electrode layer (104) comprises: a first region (114) extending along the second direction (Y), and a second region (124) and a third region (134) both extending along the first direction (X), the first region (114) connecting the second region (124) and the third region (134), the third region (134) in contact with and connected to the second end (123), the second region (124) facing the bit line (101) along the first direction (X), and a gap is provided between the bit line (101) and the lower electrode layer (104).
14. The manufacturing method according to claim 13, wherein the step of forming the lower electrode layer (104) comprises:

    Providing a substrate (110);

    A multilayer stacked structure (120) stacked along the third direction (Z) is formed on the substrate (110), wherein along the third direction (Z), the stacked structure (120) comprises a first semiconductor layer (130) and a second semiconductor layer (140) stacked in sequence;

    The stacked structure (120) is patterned to form a first opening (107) and a second opening (117) alternately arranged along the second direction (Y), the first opening (107) penetrates the stacked structure (120) along the third direction (Z), and the cross-sectional shape of the second opening (117) along a plane perpendicular to the third direction (Z) is U-shaped;

    forming a third isolation layer (125) extending along the second direction (Y), wherein the third isolation layer (125) is located in the first opening (107) and the second opening (117), and the third isolation layer (125) divides the first opening (107) into a third opening (127) and a fourth opening (137) arranged along the first direction (X);

    removing the first semiconductor layer (130) surrounding the third opening (127), and removing a portion of the second semiconductor layer (140) surrounding the fourth opening (137) to form a first groove (147), with the remaining second semiconductor layer (140) serving as a first sub-lower electrode layer (144);

    A second lower sub-electrode layer (154) is formed, wherein the second lower sub-electrode layer (154) covers the first lower sub-electrode layer (144) not in contact with the The first sub-lower electrode layer (144) and the second sub-lower electrode layer (154) constitute the lower electrode layer (104).
15. The manufacturing method according to claim 14, after forming the first lower sub-electrode layer (144) and before forming the second lower sub-electrode layer (154), further comprising:

    The third isolation layer (125) and the first semiconductor layer (130) directly opposite to the third isolation layer (125) along the third direction (Z) are removed to expose a portion of the second semiconductor layer (140) and form a first spacer (157), wherein the first groove (147) and the first spacer (157) are connected to form a first cavity (167);

    A fourth isolation layer (135) is formed, and the fourth isolation layer (135) completely fills the first cavity (167).
16. The manufacturing method according to claim 15, wherein the step of forming the semiconductor channel (103) comprises:

    removing a portion of the first semiconductor layer (130) on a side of the fourth isolation layer (135) away from the first lower sub-electrode layer (144) to form a second cavity (177), wherein the second cavity (177) is spaced from the first opening (107);

    forming a fifth isolation layer (145) that completely fills the second cavity (177);

    The remaining second semiconductor layer (140) is etched to form a second spacer (187), and the remaining second semiconductor layer (140) exposed by the second spacer (187) serves as a channel region (133) of the semiconductor channel (103).
17. The manufacturing method according to claim 16, wherein the step of forming the semiconductor channel (103) further comprises: forming a third semiconductor layer (150) on the surface of the remaining second semiconductor layer (140) exposed by the second gap (187);

    The second semiconductor layer (140) located on a side of the third opening (127) away from the fourth isolation layer (135) is removed, and the third semiconductor layer (150) serves as a channel region (133) of the semiconductor channel (103).
18. The manufacturing method according to claim 16 or 17, wherein the step of forming the gate structure (102) comprises: forming the gate structure (102) to fill up the remaining second space (187).
19. The manufacturing method according to claim 15, after forming the first cavity (167) and before forming the fourth isolation layer (135), further comprising:

    The second semiconductor layer (140) exposed by the first hole (167) is subjected to a metallization process to form the second end (123) containing a metal semiconductor compound (153).
20. The manufacturing method according to claim 15 or 19, wherein the step of forming the bit line (101) comprises:

    Etching the fourth isolation layer (135) to form a second groove extending along the third direction (Z), the second groove being at least located between the first opening (107) and the second opening (117), and the remaining fourth isolation layer (135) being at least located between the second groove and the first sub-lower electrode layer (144);

    The bit line (101) is formed to fill the second groove.