WO2024079586A1 - Semiconductor device and storage device - Google Patents

Semiconductor device and storage device Download PDF

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Publication number
WO2024079586A1
WO2024079586A1 PCT/IB2023/060031 IB2023060031W WO2024079586A1 WO 2024079586 A1 WO2024079586 A1 WO 2024079586A1 IB 2023060031 W IB2023060031 W IB 2023060031W WO 2024079586 A1 WO2024079586 A1 WO 2024079586A1
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Prior art keywords
insulator
conductor
oxide
transistor
film
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PCT/IB2023/060031
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French (fr)
Japanese (ja)
Inventor
國武寛司
太田将志
齋藤暁
山崎舜平
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株式会社半導体エネルギー研究所
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Publication of WO2024079586A1 publication Critical patent/WO2024079586A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device that use an oxide semiconductor layer. Another aspect of the present invention relates to a method for manufacturing the semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, or manufacturing methods thereof.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices, are one embodiment of semiconductor devices.
  • Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be said to have semiconductor devices.
  • a CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) that are chipped by processing a semiconductor wafer and have electrodes that serve as connection terminals.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.
  • transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices).
  • ICs integrated circuits
  • image display devices also simply referred to as display devices.
  • Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.
  • Patent Document 1 discloses a low-power consumption CPU that utilizes the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by utilizing the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple overlapping memory cells.
  • Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.
  • An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with high on-current. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.
  • an object of one embodiment of the present invention is to provide a new semiconductor device.
  • an object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity.
  • an object of one embodiment of the present invention is to provide a method for manufacturing a new semiconductor device.
  • one object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated. Alternatively, one object of one embodiment of the present invention is to provide a memory device with a large storage capacity. Alternatively, one object of one embodiment of the present invention is to provide a memory device with a high operating speed. Alternatively, one object of one embodiment of the present invention is to provide a memory device with low power consumption. Alternatively, one object of one embodiment of the present invention is to provide a novel memory device.
  • One aspect of the present invention is a semiconductor device having a first insulator on a substrate, an oxide semiconductor covering the first insulator, a first conductor and a second conductor on the oxide semiconductor, a second insulator disposed on the first conductor and the second conductor and having an opening overlapping a region between the first conductor and the second conductor, a third insulator disposed in the opening and on the oxide semiconductor, and a third conductor disposed in the opening and on the third insulator, and in a cross-sectional view in the channel width direction, the height of the first insulator is greater than the width of the first insulator.
  • the side of the opening of the second insulator coincides or roughly coincides with the side of the first conductor and the side of the second conductor.
  • the height of the first insulator is at least 2 times and at most 20 times the width of the first insulator when viewed in a cross section in the channel width direction.
  • the first conductor functions as one of the source electrode and drain electrode of the transistor
  • the second conductor functions as the other of the source electrode and drain electrode of the transistor
  • the third conductor functions as the gate electrode of the transistor
  • the oxide semiconductor and the third conductor face each other on one side of the first insulator, sandwiching the third insulator therebetween, and that the oxide semiconductor and the third conductor face each other on the other side of the first insulator, sandwiching the third insulator therebetween.
  • the first conductor contacts the oxide semiconductor on one side and the other side of the first insulator, and the second conductor contacts the oxide semiconductor on one side and the other side of the first insulator.
  • the oxide semiconductor contains one or more elements selected from the group consisting of In, Ga, and Zn.
  • Another aspect of the present invention is a memory device that includes the above-described semiconductor device and a capacitor, in which one electrode of the capacitor is electrically connected to a first conductor of the semiconductor device.
  • the capacitive element is disposed on the third conductor, and at least a portion of the capacitive element overlaps with the oxide semiconductor and the third conductor.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a semiconductor device with high operating speed can be provided.
  • a semiconductor device with good electrical characteristics can be provided.
  • a semiconductor device with less variation in electrical characteristics of transistors can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with large on-state current can be provided.
  • a semiconductor device with low power consumption can be provided.
  • a novel semiconductor device can be provided.
  • a method for manufacturing a semiconductor device with high productivity can be provided.
  • a method for manufacturing a novel semiconductor device can be provided.
  • a memory device that can be miniaturized or highly integrated can be provided.
  • a memory device with a large storage capacity can be provided.
  • a memory device with a high operating speed can be provided.
  • a memory device with low power consumption can be provided.
  • a novel memory device can be provided.
  • Fig. 1A is a plan view showing an example of a semiconductor device
  • Figs. 1B to 1D are cross-sectional views showing the example of the semiconductor device.
  • 2A and 2B are cross-sectional views showing an example of a semiconductor device.
  • 3A to 3C are cross-sectional views showing an example of a semiconductor device.
  • 4A to 4C are cross-sectional views showing an example of a semiconductor device.
  • Fig. 5A is a plan view showing an example of a semiconductor device
  • Figs. 5B to 5D are cross-sectional views showing an example of the semiconductor device.
  • Fig. 6A is a plan view showing an example of a semiconductor device
  • Figs. 6B to 6D are cross-sectional views showing an example of the semiconductor device.
  • FIG. 7A is a plan view showing an example of a semiconductor device
  • Figs. 7B to 7D are cross-sectional views showing an example of the semiconductor device.
  • FIG. 8 is a cross-sectional view showing an example of a semiconductor device.
  • 9A is a plan view showing an example of a semiconductor device
  • FIGS. 9B to 9D are cross-sectional views showing an example of the semiconductor device.
  • 10A and 10B are cross-sectional views showing an example of a semiconductor device.
  • 11A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 12A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS.
  • FIGS. 12B to 12D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 13A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 13B to 13D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 14A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 14B to 14D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 15A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 15B to 15D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • FIGS. 16A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 16B to 16D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 17A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 17B to 17D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 18A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 18B to 18D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 19A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS.
  • 19B to 19D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 20A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 20B to 20D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 21A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 21B to 21D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • FIG. 22 is a block diagram illustrating an example of a storage device.
  • 23A and 23B are a schematic diagram and a circuit diagram showing an example of a memory device.
  • 24A and 24B are schematic diagrams showing an example of a storage device.
  • FIG. 25 is a circuit diagram showing an example of a memory device.
  • 26A and 26B are cross-sectional views showing an example of a memory device.
  • 27A and 27B are cross-sectional views showing an example of a memory device.
  • FIG. 28 is a cross-sectional view showing an example of a storage device.
  • 29A and 29B are diagrams showing an example of a semiconductor device.
  • 30A and 30B are diagrams illustrating an example of an electronic component.
  • 31A and 31B are diagrams showing an example of electronic equipment, and
  • FIGS. 31C to 31E are diagrams showing an example of a mainframe computer.
  • FIG. 32 is a diagram showing an example of space equipment.
  • FIG. 33 is a diagram illustrating an example of a storage system applicable to a data center.
  • top views also called “top views”
  • perspective views some components may be omitted from the illustration. Also, some hidden lines may be omitted from the illustration.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking). Furthermore, an ordinal number attached to a component in one place in this specification may not match an ordinal number attached to the same component in another place in this specification or in the claims.
  • film and “layer” may be interchangeable depending on the circumstances.
  • conductive layer may be interchangeable with the term “conductive film”.
  • insulating film may be interchangeable with the term “insulating layer”.
  • conductor may be interchangeable with the term “conductive layer” or the term “conductive film” depending on the circumstances.
  • insulating material may be interchangeable with the term “insulating layer” or the term “insulating film” depending on the circumstances.
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less.
  • approximately parallel refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • Perfect refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less.
  • approximately perpendicular refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • Openings include, for example, grooves and slits. Also, the area in which an opening is formed may be referred to as an opening.
  • the side walls of the opening in the insulator are shown as being perpendicular or approximately perpendicular to the substrate surface or the surface on which the film is formed, but they may also be tapered.
  • a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface or the surface on which the structure is to be formed.
  • it refers to a shape having an area in which the angle between the inclined side and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°.
  • the side of the structure and the substrate surface do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.
  • the same or approximately the same height refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are equal in cross-sectional view.
  • a planarization process typically a CMP process
  • the surfaces treated in the CMP process are configured to have the same height from the reference surface.
  • the heights of multiple layers may differ depending on the processing device, processing method, or material of the processed surface during the CMP process. In this specification, this case is also treated as "the same or approximately the same height".
  • the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, this is also referred to as "the same or approximately the same height".
  • side edges that coincide or roughly coincide means that, in a plan view, at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "side edges that coincide or roughly coincide" is also used.
  • FIG. 1A to FIG. 1D are a top view and a cross-sectional view of a semiconductor device having a transistor 200a and a transistor 200b over a substrate (not shown).
  • the transistor 200b has a similar structure to the transistor 200a, and therefore the components are given the same hatching pattern as the transistor 200a, and are not particularly marked with reference symbols.
  • the transistors 200a and 200b may be collectively referred to as the transistor 200.
  • the semiconductor device described in this embodiment can function as two 1T (transistor) 1C (capacitor) type memory cells by providing a capacitor electrically connected to the transistor 200a and a capacitor electrically connected to the transistor 200b, and can also be used for a memory device.
  • FIG. 1A is a top view of the semiconductor device.
  • FIGS. 1B to 1D are cross-sectional views of the semiconductor device.
  • FIG. 1B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 1A, and is also a cross-sectional view in the channel length direction of the transistor 200a.
  • FIG. 1C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 1A, and is also a cross-sectional view in the channel width direction of the transistors 200a and 200b.
  • FIG. 1D is a cross-sectional view of the portion indicated by the dashed line A5-A6 in FIG.
  • FIG. 1A shows an enlarged view of the vicinity of the conductor 260 in FIG. 1B.
  • FIG. 2B shows an enlarged view of the vicinity of the insulator 225 in FIG. 1C.
  • FIG. 4A shows an enlarged view of the vicinity of the conductor 242a in FIG. 1B.
  • FIG. 4B shows an enlarged view of the vicinity of the insulator 225 in FIG. 1D.
  • the semiconductor device has a conductor 205 (conductor 205a and conductor 205b) embedded in an insulator 216 on a substrate (not shown), an insulator 221 on the insulator 216 and the conductor 205, an insulator 222 on the insulator 221, an insulator 225 on the insulator 222, an oxide 230 (oxide 230a and oxide 230b) on the insulator 225 and the insulator 222, a conductor 242a and a conductor 242b on the oxide 230, an insulator 250 on the oxide 230, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250.
  • the conductor 242a and the conductor 242b may be collectively referred to as the conductor 242.
  • An insulator 275 is provided on the conductor 242, and an insulator 280 is provided on the insulator 275.
  • the insulator 250 and the conductor 260 are disposed inside openings provided in the insulator 280 and the insulator 275.
  • An insulator 282 is provided on the insulator 280 and the conductor 260.
  • An insulator 283 is provided on the insulator 282.
  • An insulator 215 is provided below the insulator 216 and the conductor 205.
  • Insulator 241a is provided in contact with the inner wall of the opening of insulator 280, etc., and conductor 240a is provided in contact with the side surface of insulator 241a. The bottom surface of conductor 240a is in contact with the top surface of conductor 242a.
  • Insulator 241b is provided in contact with the inner wall of the opening of insulator 280, etc., and conductor 240b is provided in contact with the side surface of insulator 241b. The bottom surface of conductor 240b is in contact with the top surface of conductor 242b.
  • conductors 240a and 240b may be collectively referred to as conductor 240.
  • Insulators 241a and 241b may be collectively referred to as insulator 241.
  • Oxide 230 has a region that functions as a channel formation region of transistor 200.
  • Conductor 260 has a region that functions as a first gate electrode (upper gate electrode) of transistor 200.
  • Insulator 250 has a region that functions as a first gate insulator of transistor 200.
  • Conductor 205 has a region that functions as a second gate electrode (lower gate electrode) of transistor 200.
  • Insulator 222 and insulator 221 each have a region that functions as a second gate insulator of transistor 200.
  • the conductor 242a has a region that functions as one of the source electrode or drain electrode of the transistor 200.
  • the conductor 240a functions as a plug that connects to the conductor 242a.
  • the conductor 242b has a region that functions as the other of the source electrode or drain electrode of the transistor 200.
  • the conductor 240b functions as a plug that connects to the conductor 242b.
  • the oxide 230 preferably has an oxide 230a covering the insulator 225 and an oxide 230b on the oxide 230a.
  • the oxide 230a contacts the top and side surfaces of the insulator 225 and the top surface of the insulator 222.
  • the oxide 230a and the oxide 230b are provided so as to cover the insulator 225, which has a high aspect ratio. Therefore, it is preferable to form the oxide 230a and the oxide 230b using a film formation method with good coverage, such as the ALD method.
  • the oxide 230a and the oxide 230b are formed so as to be folded in half through the insulator 225. With this configuration, the channel formation region of the transistor 200 can be formed on the top, the side surface on the A3 side, and the side surface on the A4 side of the insulator 225, so that the channel width per unit area can be increased.
  • oxide 230a below oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below oxide 230a into oxide 230b.
  • oxide 230 has a two-layer structure of oxide 230a and oxide 230b, but this is not limiting.
  • Oxide 230 may have, for example, a single-layer structure of oxide 230b, or a laminated structure of three or more layers.
  • a channel formation region and a source region and a drain region are formed, sandwiching the channel formation region, in the transistor 200. At least a portion of the channel formation region overlaps with the conductor 260.
  • the source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.
  • the channel formation region is a high-resistance region with a low carrier concentration because it has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.
  • the source and drain regions are low-resistance regions with high carrier concentrations due to a large amount of oxygen vacancies or a high concentration of impurities such as hydrogen, nitrogen, and metal elements.
  • the source and drain regions are n-type regions (low-resistance regions) with a high carrier concentration compared to the channel formation region.
  • the carrier concentration of the channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, less than 1 ⁇ 10 17 cm ⁇ 3 , less than 1 ⁇ 10 16 cm ⁇ 3 , less than 1 ⁇ 10 15 cm ⁇ 3 , less than 1 ⁇ 10 14 cm ⁇ 3 , less than 1 ⁇ 10 13 cm ⁇ 3 , less than 1 ⁇ 10 12 cm ⁇ 3 , less than 1 ⁇ 10 11 cm ⁇ 3 , or less than 1 ⁇ 10 10 cm ⁇ 3 .
  • the lower limit of the carrier concentration of the channel formation region is not particularly limited, but may be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • oxide 230b when the carrier concentration of oxide 230b is reduced, the impurity concentration in oxide 230b is reduced to reduce the defect state density.
  • a low impurity concentration and a low defect state density are referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc.
  • impurities in the oxide 230b refer to, for example, anything other than the main component that constitutes the oxide 230b.
  • an element with a concentration of less than 0.1 atomic % can be considered an impurity.
  • the channel formation region, source region, and drain region may each be formed with oxide 230a as well as oxide 230b.
  • the concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not only vary stepwise from region to region, but may also vary continuously within each region. In other words, the closer a region is to the channel formation region, the lower the concentrations of metal elements and impurity elements such as hydrogen and nitrogen.
  • oxide 230 oxide 230a and oxide 230b.
  • the band gap of a metal oxide that functions as a semiconductor is preferably 2 eV or more, and more preferably 2.5 eV or more.
  • a metal oxide with a large band gap By using a metal oxide with a large band gap, the off-current of a transistor can be reduced.
  • a transistor having a metal oxide in a channel formation region in this way is called an OS transistor. Since the off-current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, since the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.
  • the oxide 230 preferably has a metal oxide (oxide semiconductor).
  • metal oxides that can be used for the oxide 230 include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably has two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or semi-metal element that has a high bond energy with oxygen, for example, a metal element or semi-metal element that has a higher bond energy with oxygen than indium.
  • the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification may include metalloid elements.
  • the oxide 230 may be, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (Al-Zn oxide, also written as AZO), indium aluminum oxide (Al-Zn oxide, also written as AZO), Indium zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZO),
  • the field effect mobility of the transistor can be increased.
  • the metal oxide may contain one or more metal elements with a high periodic number instead of or in addition to indium.
  • metal elements with a high periodic number include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the field effect mobility of the transistor may be increased.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. This suppresses fluctuations in the electrical characteristics of the transistor, and increases its reliability.
  • the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, and a transistor with a small off-current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for oxide 230. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that combines excellent electrical characteristics and high reliability can be obtained.
  • the oxide 230 preferably has a laminated structure of multiple oxide layers with different chemical compositions.
  • the atomic ratio of element M to the main metal element is preferably greater than the atomic ratio of element M to the main metal element in the metal oxide used for the oxide 230b.
  • the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a to the oxide 230b.
  • the atomic ratio of In to element M is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.
  • oxide 230a and oxide 230b have a common element other than oxygen as a main component, the defect state density at the interface between oxide 230a and oxide 230b can be reduced. The defect state density at the interface between oxide 230a and oxide 230b can be reduced. As a result, the effect of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.
  • the nearby composition includes a range of ⁇ 30% of the desired atomic ratio.
  • Gallium is preferably used as the element M.
  • the metal oxide that can be used for the oxide 230a may be applied as the oxide 230b.
  • the composition of the metal oxide that can be used for the oxide 230a and the oxide 230b is not limited to the above.
  • the composition of the metal oxide that can be used for the oxide 230a may be applied to the oxide 230b.
  • the composition of the metal oxide that can be used for the oxide 230b may be applied to the oxide 230a.
  • the metal oxide of the above composition may be stacked in either or both of the oxide 230a and the oxide 230b.
  • the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of the sputtering target used to form the metal oxide film.
  • the oxide 230b is preferably crystalline.
  • CAAC-OS c-axis aligned crystalline oxide semiconductor
  • CAAC-OS is a metal oxide that has a highly crystalline and dense structure and has few impurities and defects (e.g., oxygen vacancies).
  • a temperature e.g. 400°C or higher and 600°C or lower
  • the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.
  • the oxide 230b Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide 230b, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or drain electrode. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.
  • a crystalline oxide such as CAAC-OS
  • the electrical characteristics of a transistor using an oxide semiconductor may fluctuate, and the reliability may be reduced.
  • hydrogen near the oxygen vacancies may form a defect in which hydrogen is inserted into the oxygen vacancies (hereinafter, may be referred to as VOH ), and may generate electrons that serve as carriers.
  • VOH hydrogen near the oxygen vacancies
  • the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and a current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, impurities, oxygen vacancies, and VOH are preferably reduced as much as possible in the channel formation region in the oxide semiconductor.
  • the carrier concentration of the channel formation region in the oxide semiconductor is reduced and the channel formation region in the oxide semiconductor is i-type (intrinsic) or substantially i-type.
  • excess oxygen oxygen that is desorbed by heating
  • excess oxygen oxygen can be supplied from the insulator to the oxide semiconductor, thereby reducing oxygen vacancies and VOH .
  • excess oxygen oxygen supplied to the source region or drain region
  • the on-current of the transistor 200 may be reduced or the field-effect mobility may be reduced.
  • the amount of oxygen supplied to the source region or drain region varies within the substrate surface, the characteristics of a semiconductor device including a transistor may vary.
  • the conductor When oxygen supplied from the insulator to the oxide semiconductor diffuses to a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized and its conductivity may be impaired, which may adversely affect the electrical characteristics and reliability of the transistor.
  • the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the source and drain regions preferably have a high carrier concentration and are n-type. That is, it is preferable to reduce oxygen vacancies and VOH in the channel formation region of the oxide semiconductor. It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions and to prevent the amount of VOH in the source and drain regions from being excessively reduced. It is also preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like.
  • the conductor 260 it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like.
  • hydrogen in the oxide semiconductor can form VOH , and therefore the hydrogen concentration needs to be reduced in order to reduce the amount of VOH .
  • a semiconductor device is configured to reduce the hydrogen concentration in the channel formation region, suppress oxidation of conductor 242a, conductor 242b, and conductor 260, and suppress reduction in the hydrogen concentration in the source region and drain region.
  • the insulator 250 in contact with the channel formation region in the oxide 230b preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide 230b. As a result, VOH in the channel formation region can be reduced, and the channel formation region can be made i-type or substantially i-type.
  • the insulator 250 has a layered structure of an insulator 250a in contact with the oxide 230, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c.
  • the insulators 250a and 250c have the function of capturing hydrogen or fixing hydrogen.
  • An example of an insulator that has the function of capturing or fixing hydrogen is a metal oxide having an amorphous structure.
  • a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium as insulator 250a and insulator 250c.
  • oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen.
  • metal oxides having an amorphous structure have a high ability to capture or fix hydrogen.
  • a high dielectric constant (high-k) material for the insulator 250a and the insulator 250c.
  • An example of a high-k material is an oxide containing one or both of aluminum and hafnium.
  • the insulators 250a and 250c it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.
  • an aluminum oxide film is used as the insulator 250a.
  • the aluminum oxide preferably has an amorphous structure.
  • hafnium oxide is used as the insulator 250c.
  • the hydrogen contained in the insulators 250b and 250d can be captured and fixed more effectively.
  • a thermally stable insulator such as silicon oxide or silicon oxynitride for the insulator 250b.
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • a nitride oxide refers to a material whose composition contains more nitrogen than oxygen.
  • silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.
  • the insulators are, for example, insulator 250a, insulator 250d, insulator 250c, and insulator 275.
  • a barrier insulator refers to an insulator that has barrier properties.
  • having barrier properties refers to having the property of preventing the penetration of the corresponding substance (also called low permeability).
  • an insulator with barrier properties has the property that the corresponding substance is unlikely to diffuse into the insulator.
  • an insulator with barrier properties has the function of capturing or fixing the corresponding substance inside the insulator (also called gettering).
  • the barrier insulator against oxygen examples include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).
  • the insulators 250a, 250c, 250d, and 275 each have a single-layer structure or a multilayer structure of the above-mentioned barrier insulator against oxygen.
  • the insulator 250a preferably has a barrier property against oxygen.
  • the insulator 250a is preferably at least less permeable to oxygen than the insulator 280.
  • the insulator 250a has an area in contact with the side surface of the conductor 242a and the side surface of the conductor 242b.
  • the insulator 250a having a barrier property against oxygen can suppress the side surfaces of the conductor 242a and the conductor 242b from being oxidized and forming an oxide film on the side surfaces. This can suppress a decrease in the on-current or a decrease in the field effect mobility of the transistor 200.
  • the insulator 250a is provided in contact with the upper surface and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, and the upper surface of the insulator 222. Since the insulator 250a has a barrier property against oxygen, it is possible to suppress the desorption of oxygen from the channel formation region of the oxide 230b when a heat treatment or the like is performed. Therefore, it is possible to reduce the formation of oxygen vacancies in the oxide 230a and the oxide 230b.
  • the insulator 250a it is possible to prevent an excessive amount of oxygen from being supplied from the insulator 280 to the oxide 230a and the oxide 230b, and to supply an appropriate amount of oxygen to the oxide 230a and the oxide 230b. This prevents the source region and the drain region from being excessively oxidized, and suppresses a decrease in the on-current or a decrease in the field effect mobility of the transistor 200.
  • Oxides containing either or both of aluminum and hafnium have barrier properties against oxygen, and are therefore suitable for use as the insulator 250a.
  • the insulator 250d also preferably has a barrier property against oxygen.
  • the insulator 250d is provided between the channel formation region of the oxide 230 and the conductor 260, and between the insulator 280 and the conductor 260. This configuration can suppress the oxygen contained in the channel formation region of the oxide 230 from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the oxide 230. In addition, it can suppress the oxygen contained in the oxide 230 and the oxygen contained in the insulator 280 from diffusing to the conductor 260 and oxidizing the conductor 260.
  • the insulator 250d is preferably at least less permeable to oxygen than the insulator 280. For example, it is preferable to use a silicon nitride film as the insulator 250d. In this case, the insulator 250d is an insulator having at least nitrogen and silicon.
  • the insulator 250d has a barrier property against hydrogen. This can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide 230b.
  • the insulator 275 also preferably has a barrier property against oxygen.
  • the insulator 275 is provided between the insulator 280 and the conductor 242a, and between the insulator 280 and the conductor 242b.
  • the insulator 275 is provided in contact with the side of the conductor 242, the side of the oxide 230, and the upper surface of the insulator 222.
  • This configuration can suppress the oxygen contained in the insulator 280 from diffusing into the conductor 242. Therefore, it is possible to suppress the conductor 242 from being oxidized by the oxygen contained in the insulator 280, which would increase the resistivity.
  • the insulator 275 is preferably at least less permeable to oxygen than the insulator 280.
  • the insulator 275 is an insulator having at least nitrogen and silicon.
  • the barrier insulator against hydrogen is, for example, insulator 275.
  • barrier insulators against hydrogen examples include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride.
  • the insulator 275 is preferably a single-layer structure or a multilayer structure of the above-mentioned barrier insulators against hydrogen.
  • the source and drain regions can be made n-type.
  • the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, and a semiconductor device with good electrical characteristics can be provided. Furthermore, by using the above configuration, the semiconductor device can have good electrical characteristics even when miniaturized or highly integrated. Furthermore, by miniaturizing the transistor 200, the frequency characteristics can be improved. Specifically, the cutoff frequency can be improved.
  • the insulators 250a to 250d function as part of the gate insulator.
  • the insulators 250a to 250d are provided in an opening formed in the insulator 280 together with the conductor 260.
  • the thicknesses of the insulators 250a to 250d are each thin.
  • the thicknesses of the insulators 250a to 250d are each preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that it is sufficient that the insulators 250a to 250d each have a region with the above-mentioned thickness at least in a portion thereof.
  • the film thickness of the insulators 250a to 250d as described above thin it is preferable to form the film using the atomic layer deposition (ALD) method.
  • ALD atomic layer deposition
  • the ALD method includes a thermal ALD method in which the reaction between the precursor and the reactant is carried out using only thermal energy, and a plasma enhanced ALD method in which a plasma excited reactant is used.
  • the use of plasma allows film formation at a lower temperature, which may be preferable.
  • the ALD method allows atoms to be deposited one layer at a time, which has the advantages of enabling extremely thin films to be formed, films to be formed on structures with high aspect ratios, films to be formed with fewer defects such as pinholes, films to be formed with excellent coverage, and films to be formed at low temperatures. Therefore, the insulator 250 can be formed with good coverage on the side surfaces of the opening formed in the insulator 280 and the side ends of the conductors 242a and 242b, and with a thin film thickness as described above.
  • films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods.
  • Quantitative determination of impurities can be performed using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).
  • the insulator 250 has been described above as having a four-layer structure of insulators 250a to 250d, the present invention is not limited to this.
  • the insulator 250 can have a structure including at least one of insulators 250a to 250d. By configuring the insulator 250 with one, two, or three layers of insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.
  • the insulator 250 may have a two-layer structure.
  • the insulator 250 has a laminated structure of an insulator 250a and an insulator 250d on the insulator 250a.
  • a high-k material can be used for at least one of the insulators 250a and 250d. This makes it possible to reduce the equivalent oxide thickness (EOT) while maintaining the thickness of the insulators 250a and 250d at a level that suppresses leakage current.
  • EOT equivalent oxide thickness
  • the insulator 250 may be configured to have a three-layer structure.
  • the insulator 250 has a layered structure of insulator 250a, insulator 250b on insulator 250a, and insulator 250d on insulator 250b.
  • the configuration shown in FIG. 3A is configured with an additional insulator 250b.
  • the semiconductor device is preferably configured to suppress hydrogen from being mixed into the transistor 200 and the like.
  • an insulator having a function of suppressing hydrogen diffusion so as to cover one or both of the top and bottom of the transistor 200 and the like.
  • the insulator is, for example, the insulator 283, the insulator 282, the insulator 222, the insulator 221, and the like.
  • the insulator 215 provided under the transistor 200 may have a structure similar to either one or both of the insulators 282 and 283.
  • the insulator 215 may have a stacked structure of the insulators 282 and 283, and may be configured to have the insulator 282 on the bottom and the insulator 283 on the top, or may be configured to have the insulator 282 on the top and the insulator 283 on the bottom.
  • one or more of the insulators 283, 282, 222, and 221 function as a barrier insulator that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 to the transistor 200. Therefore, it is preferable that one or more of the insulators 283, 282, 222, and 221 have an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 , etc.), and copper atoms (through which the above impurities are difficult to permeate). Alternatively, it is preferable that the insulators have an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.) (through which the above oxygen is difficult to permeate).
  • oxygen for example, at least one of oxygen atoms and oxygen molecules, etc.
  • the insulators 283, 282, 222, and 221 each preferably have an insulator that has a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen, and may be, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxide containing aluminum and hafnium (hafnium aluminate), oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide.
  • the insulators 283 and 221 are preferably made of silicon nitride, which has a higher hydrogen barrier property.
  • the insulator 282 is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen.
  • the insulator 222 is preferably made of hafnium oxide, which has a high ability to capture or fix hydrogen and is a high dielectric constant (high-k) material.
  • impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged above the insulator 283 to the transistor 200. Also, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged below the insulator 221 to the transistor 200. Also, hydrogen contained in the insulator 280 and the insulator 250 can be captured and fixed to the insulator 282 or the insulator 222. Furthermore, by providing the insulators 282 and 283, oxygen contained in the insulator 280 can be prevented from diffusing above the transistor 200. Also, by providing the insulators 222 and 221, oxygen contained in the oxide 230 can be prevented from diffusing below the transistor 200.
  • silicon nitride which has a higher hydrogen barrier property, for insulator 275 and insulator 250d. It is also preferable to use aluminum oxide, which has a higher ability to capture hydrogen or fix hydrogen, for insulator 250a. It is also preferable to use hafnium oxide, which has a higher ability to capture hydrogen or fix hydrogen, for insulator 250c.
  • the insulator 225 is formed on and in contact with the insulator 222. As shown in FIG. 2B and FIG. 4B, the insulator 225 has a shape with a high aspect ratio in a cross-sectional view in the channel width direction.
  • the aspect ratio of the insulator 225 in a cross-sectional view in the channel width direction refers to the ratio of the length L of the insulator 225 in the A3-A4 direction (which can also be called the width L of the insulator 225) to the length H in a direction perpendicular to the surface on which the insulator 225 is formed (for example, the insulator 222) (which can also be called the height H of the insulator 225).
  • the height H of the insulator 225 is at least longer than the width L of the insulator 225.
  • the height H of the insulator 225 is greater than 1 time the width L of the insulator 225, preferably 2 times or more, more preferably 5 times or more, and even more preferably 10 times or more.
  • the height H of the insulator 225 is preferably 20 times or less the width L of the insulator 225.
  • the oxide 230a, the oxide 230b, and the conductor 242 are provided to cover the insulator 225 having such a high aspect ratio.
  • the oxide 230a and the oxide 230b are provided so as to sandwich the insulator 225 in a folded state, and the insulator 250 and the conductor 260 are further provided to cover the oxide 230b.
  • the oxide 230 and the conductor 260 are provided facing each other with the insulator 250 sandwiched between them on the upper part, the side surface on the A3 side, and the side surface on the A4 side of the insulator 225.
  • the upper part, the side surface on the A3 side, and the side surface on the A4 side of the insulator 225 each function as a channel formation region. Therefore, compared to the case where the insulator 225 is not provided, the channel width of the transistor 200 is larger by the side surface on the A3 side and the side surface on the A4 side of the insulator 225.
  • the channel width as described above By increasing the channel width as described above, the on-state current, field effect mobility, frequency characteristics, and the like of the transistor 200 can be improved. This makes it possible to provide a semiconductor device with high operating speed. In addition, the operating speed of a memory device using the semiconductor device can be increased. In addition, in the above structure, by providing the insulator 225, the channel width can be increased without increasing the area occupied by the transistor 200. This makes it possible to miniaturize or highly integrate the semiconductor device. In addition, the memory capacity of a memory device using the semiconductor device can be increased.
  • the insulator 225 may be made of an insulating material that can be used for the insulators 222, 280, and 250.
  • the insulator 225 since the insulator 225 has a shape with a high aspect ratio, it is preferable to form it in a sidewall shape on the side of the sacrificial layer (insulator 223 described later). Therefore, it is preferable to form the insulator 225 using the ALD method, which has good coverage.
  • the insulator 225 may be made of hafnium oxide formed by the thermal ALD method.
  • the insulator 225 of the transistor 200a and the insulator 225 of the transistor 200b can be formed simultaneously.
  • the distance between the two insulators 225 can be set according to the size of the sacrificial layer. Therefore, the distance between the insulators 225 can be reduced, the area occupied by the transistors 200a and 200b can be reduced, and the semiconductor device can be highly integrated.
  • the insulator 225 is not limited to insulating materials in the strict sense.
  • metal oxides with relatively high insulating properties may be used.
  • metal oxides that can be used for the oxide 230a may be used.
  • the upper part of the insulator 225 may have a curved shape.
  • a curved shape can prevent defects such as voids from forming in the oxide 230a, the oxide 230b, and the conductor 242 near the upper part of the insulator 225.
  • a symmetrical structure is shown in which a curved shape is provided on both the A3 side (A5 side) and the A4 side (A6 side) of the upper part of the insulator 225, but the present invention is not limited to this.
  • an asymmetrical structure may be used in which a curved shape is provided only on the A3 side (A5 side) of the upper part of the insulator 225.
  • FIG. 5A is a top view of the semiconductor device.
  • FIG. 5B to FIG. 5D are cross-sectional views of the semiconductor device.
  • FIG. 5B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 5A.
  • FIG. 5C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 5A.
  • FIG. 5D is a cross-sectional view of the portion indicated by the dashed line A7-A8 in FIG. 5A. Note that some elements are omitted from the top view of FIG. 5A for clarity.
  • the insulator 225 is integrated between the transistors 200a and 200b. Therefore, the insulator 275 contacts the top surface of the insulator 225 between the transistors 200a and 200b. As described above, the insulator 225 is preferably formed in a sidewall shape in contact with the side surface of the sacrificial layer. In the semiconductor device shown in FIG. 5A to FIG. 5D, the insulator 225 is formed by providing a sacrificial layer in the area surrounded by the insulator 225.
  • the conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260.
  • the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216.
  • the conductor 205 is preferably provided extending in the channel width direction as shown in Figures 1A and 1C. With this configuration, the conductor 205 functions as wiring when multiple transistors are provided.
  • the conductor 205 has conductor 205a and conductor 205b.
  • Conductor 205a is provided in contact with the bottom surface and side wall of the opening.
  • Conductor 205b is provided so as to fill the recess of conductor 205a formed along the opening.
  • the height of the upper surface of conductor 205 coincides or approximately coincides with the height of the upper surface of insulator 216.
  • the conductor 205a preferably has a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules ( N2O , NO, NO2 , etc.), copper atoms, etc.
  • impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules ( N2O , NO, NO2 , etc.), copper atoms, etc.
  • it preferably has a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).
  • a conductive material having the function of reducing hydrogen diffusion for the conductor 205a By using a conductive material having the function of reducing hydrogen diffusion for the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 216, etc. Also, by using a conductive material having the function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials having the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.
  • the conductor 205a can have a single layer structure or a multilayer structure of the above conductive materials.
  • the conductor 205a preferably has titanium nitride.
  • the conductor 205b is made of a conductive material mainly composed of tungsten, copper, or aluminum.
  • the conductor 205b contains tungsten.
  • the conductor 205 can function as a second gate electrode.
  • the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260.
  • applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.
  • the electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity.
  • the film thickness of the insulator 216 is approximately the same as that of the conductor 205.
  • conductor 205 may have a single layer structure or a laminated structure of three or more layers.
  • the laminated structure of conductor 205a and conductor 205b may further include a conductor having the same material as conductor 205a on conductor 205b.
  • the conductor may be formed so that the top surface of conductor 205b is lower than the top of conductor 205a, and the recess formed by conductor 205a and conductor 205b is filled.
  • the semiconductor device of this embodiment may be configured without providing the conductor 205, as shown in Figures 6A to 6D.
  • the oxide 230 has a folded structure with the insulator 225 interposed therebetween. Therefore, the conductor 260 located opposite the oxide 230 across the insulator 225 may function similarly to the conductor 205. Therefore, as shown in Figures 6A to 6D, even if the conductor 205 is not provided, a part of the conductor 260 may function as a second gate electrode.
  • conductor 242a, conductor 242b, and conductor 260 are conductors that contain at least metal and nitrogen.
  • the conductors 242a and 242b are disposed at a distance from each other and are provided on the oxide 230b in contact with each other. As shown in Figures 4A and 4B, the conductor 242 is provided so as to cover the insulator 225, which has a high aspect ratio. Therefore, it is preferable to form the conductor 242 using a film formation method with good coverage, such as the ALD method or the CVD method.
  • the oxide 230a, the oxide 230b, and the conductor 242a are provided so as to be folded in half with the insulator 225 sandwiched therebetween.
  • the conductor 242a contacts the oxide 230b at the top, the side surface on the A5 side, and the side surface on the A6 side of the insulator 225. Therefore, compared to the case where the insulator 225 is not provided, the contact area between the conductor 242a and the oxide 230b is larger by the amount of the side surface on the A5 side and the side surface on the A6 side of the insulator 225.
  • FIG. 4B shows the vicinity of the conductor 242a, the same is true for the conductor 242b.
  • the contact area between the conductor 242b and the oxide 230b is larger, similar to the above-mentioned conductor 242a and the oxide 230b.
  • the on-current, frequency characteristics, and the like of the transistor 200 can be improved without increasing the area occupied by the transistor 200.
  • This makes it possible to provide a semiconductor device with a high operating speed.
  • the operating speed of a memory device using the semiconductor device can be increased.
  • This also makes it possible to miniaturize or highly integrate the semiconductor device.
  • the memory capacity of a memory device using the semiconductor device can be increased.
  • conductors 242a and 242b are in contact with oxide 230b, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen. This can suppress a decrease in the conductivity of conductors 242a and 242b. It can also suppress the extraction of oxygen from oxide 230b, which would result in the formation of an excessive amount of oxygen vacancy. It is also preferable to use a material that easily absorbs (extracts) hydrogen as conductors 242a and 242b, as this can reduce the hydrogen concentration in oxide 230.
  • a metal nitride for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum.
  • a nitride containing tantalum is particularly preferable.
  • ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.
  • hydrogen contained in oxide 230b etc. may diffuse into conductor 242a or conductor 242b.
  • hydrogen contained in oxide 230b etc. is more likely to diffuse into conductor 242a or conductor 242b, and the diffused hydrogen may combine with nitrogen contained in conductor 242a or conductor 242b.
  • hydrogen contained in oxide 230b etc. may be absorbed by conductor 242a or conductor 242b.
  • a crystalline oxide such as CAAC-OS as the oxide 230b.
  • a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin By using CAAC-OS, it is possible to suppress the extraction of oxygen from the oxide 230b by the conductor 242a or the conductor 242b. It is also possible to suppress a decrease in the conductivity of the conductor 242a and the conductor 242b.
  • the conductors 242a and 242b may have a two-layer structure.
  • the conductor 242a may be a laminated film of the conductor 242a1 and the conductor 242a2 on the conductor 242a1
  • the conductor 242b may be a laminated film of the conductor 242b1 and the conductor 242b2 on the conductor 242b1.
  • This can suppress the decrease in the conductivity of the conductors 242a and 242b. In addition, it can suppress the extraction of oxygen from the oxide 230b, which can suppress the formation of an excessive amount of oxygen vacancy. In addition, it is preferable to use a material that easily absorbs (removes) hydrogen as the layer in contact with the oxide 230b (conductor 242a1 and conductor 242b1), as this can reduce the hydrogen concentration in the oxide 230.
  • conductor 242a2 and conductor 242b2 have higher conductivity than conductor 242a1 and conductor 242b1.
  • the film thickness of conductor 242a2 and conductor 242b2 is larger than the film thickness of conductor 242a1 and conductor 242b1.
  • Conductors that can be used for conductor 205b may be used as conductor 242a2 and conductor 242b2.
  • tantalum nitride or titanium nitride can be used as the conductor 242a1 and the conductor 242b1, and tungsten can be used as the conductor 242a2 and the conductor 242b2.
  • the insulator 255 is disposed in an opening formed in the insulator 280, etc., and contacts the side of the insulator 280, the side of the insulator 275, the side of the conductor 242a2, the side of the conductor 242b2, the top surface of the conductor 242a1, and the top surface of the conductor 242b1.
  • the insulator 255 is formed in contact with the side wall of the opening formed in the insulator 280, etc. That is, the insulator 255 can also be called a sidewall insulating film.
  • the insulator 255 is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, and is an inorganic insulator that protects the conductor 242a2 and the conductor 242b2. Since the insulator 255 is exposed to an oxidizing atmosphere, it is preferable that the insulator 255 is an inorganic insulator that is not easily oxidized. Furthermore, since the insulator 255 is in contact with the conductor 242a2 and the conductor 242b2, it is preferable that the insulator 255 is an inorganic insulator that is not easily oxidized. Therefore, it is preferable that the insulator 255 is made of an insulating material that can be used for the insulator 250d that has a barrier property against oxygen. For example, silicon nitride can be used as the insulator 255.
  • 3C shows a structure in which the upper end of insulator 255 roughly coincides with the upper surface of insulator 280, the upper end of insulator 250, and the upper end of conductor 260, but this embodiment is not limited to this.
  • Insulator 255 may be structured to cover the side surface of conductor 242a2 and the side surface of conductor 242b2.
  • the upper end of insulator 255 may be structured to be lower than the upper surface of insulator 280 and higher than the upper surface of insulator 275.
  • the distance between the conductor 242a1 and the conductor 242b1 is smaller than the distance between the conductor 242a2 and the conductor 242b2.
  • the difference in distance is equal to or approximately equal to twice the film thickness of the insulator 255.
  • the film thickness of the insulator 255 refers to the film thickness in the A1-A2 direction of at least a portion of the insulator 255.
  • conductor 260 is disposed in an opening formed in insulator 280, insulator 275, conductor 242a, and conductor 242b.
  • Conductor 260 is disposed in the opening so as to cover the upper surface of insulator 222, the side of oxide 230a, the side of oxide 230b, and the upper surface of oxide 230b via insulator 250.
  • the upper surface of conductor 260 is disposed so as to be flush or approximately flush with the top of insulator 250 and the upper surface of insulator 280.
  • the sidewall of the opening may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may be tapered.
  • the sidewall tapered By making the sidewall tapered, the coverage of the insulator 250 and the like provided in the opening of the insulator 280 is improved, and defects such as voids can be reduced.
  • the conductor 260 functions as a first gate electrode of the transistor 200.
  • the conductor 260 is preferably provided extending in the channel width direction, as shown in Figures 1A and 1C. With this configuration, the conductor 260 functions as wiring when multiple transistors are provided.
  • the transistor structure in which the electric field of at least the first gate electrode electrically surrounds the channel formation region is called a surrounded channel (S-channel) structure.
  • the S-channel structure disclosed in this specification has a structure different from the Fin type structure and the planar type structure.
  • the S-channel structure disclosed in this specification can also be considered as a type of Fin type structure.
  • the Fin type structure refers to a structure in which the gate electrode is arranged to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.).
  • the channel formation region can be electrically surrounded. Since the S-channel structure electrically surrounds the channel formation region, it can be said that it is substantially the same structure as a GAA (Gate All Around) structure or a LGAA (Lateral Gate All Around) structure.
  • the transistor 200 By making the transistor 200 have an S-channel structure, a GAA structure, or a LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be the entire bulk of the oxide 230. Therefore, it is possible to improve the current density flowing through the transistor, and it is expected that the on-current of the transistor or the field effect mobility of the transistor can be improved.
  • conductor 260 is shown as having a two-layer structure.
  • conductor 260 preferably has conductor 260a and conductor 260b arranged on conductor 260a.
  • conductor 260a is preferably arranged so as to wrap around the bottom and side surfaces of conductor 260b.
  • the conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms.
  • impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms.
  • a conductive material that has the function of suppressing the diffusion of oxygen e.g., at least one of oxygen atoms and oxygen molecules).
  • the conductor 260a since the conductor 260a has the function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 260b due to the oxygen contained in the insulator 280, etc., which would otherwise cause a decrease in conductivity.
  • a conductive material having the function of suppressing the diffusion of oxygen it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.
  • the conductor 260b is a conductor having high conductivity.
  • the conductor 260b may be a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 260b may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.
  • the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like.
  • the side of the insulator 280 in the opening coincides or roughly coincides with the side of the conductor 242a and the side of the conductor 242b. Therefore, the conductor 260 can be positioned so as to overlap the region between the conductor 242a and the conductor 242b without alignment.
  • the insulators 216 and 280 each have a lower dielectric constant than the insulator 222.
  • the parasitic capacitance that occurs between the wirings can be reduced.
  • the insulators 216 and 280 each have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.
  • Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions that contain oxygen that is released by heating.
  • the upper surfaces of the insulators 216 and 280 may each be flattened.
  • the concentration of impurities such as water and hydrogen in the insulator 280 is reduced.
  • the insulator 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.
  • Conductor 240a and conductor 240b are formed in the openings of insulators 275, 280, 282, and 283, respectively.
  • the lower surface of conductor 240a contacts the upper surface of conductor 242a
  • the lower surface of conductor 240b contacts the upper surface of conductor 242b.
  • the height of the upper surface of conductor 240 and the height of the upper surface of insulator 283 are approximately the same.
  • the conductor 240 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 240 may also have a layered structure in which a first conductor is provided in contact with the side surface of the insulator 241, and a second conductor is provided further inside. In this case, the above-mentioned conductive material can be used as the second conductor.
  • the conductor 240 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the first conductor arranged near the insulators 283, 282, and 280, and the insulator 275.
  • a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the first conductor arranged near the insulators 283, 282, and 280, and the insulator 275.
  • the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a laminated layer. With such a configuration, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from being mixed into the oxide 230 through the conductors 240a and 240b.
  • Insulators 241a and 241b are formed in contact with the inner walls of the openings of insulators 275, 280, 282, and 283, respectively.
  • the inner side of insulator 241a contacts conductor 240a, and the inner side of insulator 241b contacts conductor 240b.
  • the insulator 241 may be a barrier insulating film that can be used for the insulator 275, etc.
  • the insulator 241 may be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide.
  • impurities such as water and hydrogen contained in the insulator 280, etc., can be prevented from mixing into the oxide 230 through the conductors 240a and 240b.
  • Silicon nitride is particularly suitable because it has high blocking properties against hydrogen.
  • the oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.
  • the first insulator in contact with the inner wall of the opening, such as the insulator 280, and the second insulator on the inside thereof are made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.
  • the first insulator may be aluminum oxide formed by thermal ALD, and the second insulator may be silicon nitride formed by PEALD. This configuration can suppress oxidation of the conductor 240 and also reduce hydrogen contamination of the conductor 240.
  • the insulator 241 has a two-layer laminated structure
  • the present invention is not limited to this.
  • the insulator 241 may be configured as a single layer or a laminated structure of three or more layers.
  • the conductor 240 may be configured as a single layer or a laminated structure of three or more layers.
  • FIG. 4B and other figures a structure in which the conductor 240a contacts the conductor 242a only above the upper end of the insulator 225 is shown, but the present invention is not limited to this.
  • FIG. 4C a structure in which the conductor 240a covers the insulator 225 and the oxide 230a, oxide 230b, and conductor 242a that are folded in half with the insulator 225 in between may be used.
  • the conductor 240a contacts the conductor 242a at the top of the insulator 225, the side surface on the A5 side, and the side surface on the A6 side.
  • the contact area between the conductor 240a and the conductor 242a is larger by the side surface on the A5 side and the side surface on the A6 side of the insulator 225.
  • FIG. 4C the vicinity of the conductor 240a and the conductor 242a is shown, but the same applies to the conductor 240b and the conductor 242b.
  • the contact area between conductor 240b and conductor 242b is large.
  • transistor 200 By increasing the contact area between conductor 240 and conductor 242 as described above, the on-current, frequency characteristics, and the like of transistor 200 can be improved without significantly increasing the area occupied by transistor 200. This makes it possible to provide a semiconductor device with a high operating speed. In addition, the operating speed of a storage device using the semiconductor device can be increased. This also makes it possible to miniaturize or highly integrate the semiconductor device. In addition, the storage capacity of a storage device using the semiconductor device can be increased.
  • the oxide 230a and the oxide 230b cover the insulator 225 near the channel of the transistor 200, but the present invention is not limited to this.
  • the upper surface of the insulator 225 may be exposed from the oxide 230a and the oxide 230b near the channel of the transistor 200.
  • FIG. 7A is a top view of the semiconductor device.
  • FIG. 7B to FIG. 7D, and FIG. 8 are cross-sectional views of the semiconductor device.
  • FIG. 7B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 7A.
  • FIG. 7C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 7A.
  • FIG. 7D is a cross-sectional view of the portion indicated by the dashed line A5-A6 in FIG. 7A.
  • FIG. 8 is a cross-sectional view of the portion indicated by the dashed line B1-B2 in FIG. 7A. Also, in the top view of Figure 7A, some elements have been omitted for clarity.
  • the oxide 230a contacts the side of the insulator 225
  • the oxide 230b contacts the side of the oxide 230a
  • the oxide 230a and the oxide 230b do not contact at least a part of the upper surface of the insulator 225.
  • the oxide 230a contacts the side of the insulator 225, the side and lower surface of the oxide 230b, and the upper surface of the insulator 222.
  • the upper surface of the insulator 225 contacts the lower surface of the insulator 250.
  • the oxide 230a and the oxide 230b cover the insulator 225 in the region that overlaps with the conductor 242, etc., similar to the structure shown in Figure 1D.
  • the oxide 230a and the oxide 230b are not formed between the conductor 242a and the conductor 242b, but as shown in FIG. 8, the oxide 230a and the oxide 230b are formed near the side of the insulator 225. That is, in the region where the oxide 230a and the oxide 230b overlap the conductor 242, the A5 side portion and the A6 side portion are folded in half and integrated with the insulator 225 in between, but in the region between the conductor 242a and the conductor 242b, the A3 side portion and the A4 side portion are separated by the insulator 225.
  • the insulator 225 is mostly covered by the oxide 230, but in the region between the conductor 242a and the conductor 242b, an opening is formed in the oxide 230, and the insulator 225 is exposed from the oxide 230 in that region.
  • the oxide 230a and the oxide 230b are provided in the form of sidewalls on the side of the insulator 225, which has a high aspect ratio.
  • the channel formation region of the transistor 200 can be formed on the side of the insulator 225 on the A3 side and the A4 side, so that the channel width per unit area can be increased.
  • the increased channel width can improve the on-current, field effect mobility, and frequency characteristics of the transistor 200. Therefore, by using the semiconductor device of this embodiment as a memory device, the operating speed can be improved.
  • the oxide 230a, the oxide 230b, the conductor 242a, and the conductor 242b are folded in two with the insulator 225 sandwiched between them near the source or drain of the transistor 200, but the present invention is not limited to this.
  • the oxide 230a, the oxide 230b, the conductor 242a, and the conductor 242b can be divided into a portion on the A3 side and a portion on the A4 side with the dashed line A1-A2 as the boundary.
  • FIG. 9A is a top view of the semiconductor device. Also, FIGS.
  • FIG. 9B to 9D, 10A, and 10B are cross-sectional views of the semiconductor device.
  • FIG. 9B is a cross-sectional view of the portion indicated by the dashed line D1-D2 in FIG. 9A.
  • FIG. 9C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 9A.
  • FIG. 9D is a cross-sectional view of the area indicated by the dashed line A5-A6 in FIG. 9A.
  • FIG. 10A is a cross-sectional view of the area indicated by the dashed line E1-E2 in FIG. 9A.
  • FIG. 10B is a cross-sectional view of the area indicated by the dashed line A1-A2 in FIG. 9A.
  • FIG. 9A In the top view of FIG. 9A, some elements have been omitted for clarity.
  • the semiconductor device shown in Figures 9A to 9D, 10A, and 10B has transistor 200aD on the A3 side and transistor 200aE on the A4 side, with the dashed line A1-A2 (insulator 225) as the boundary.
  • the transistor 200a is divided into transistor 200aD and transistor 200aE without significantly increasing the occupied area.
  • the semiconductor device shown in Figures 9A to 9D, 10A, and 10B does not show components corresponding to transistor 200b of the semiconductor device shown in Figures 7A to 7D, and 8, but components corresponding to transistor 200b can also be provided, as in the semiconductor device shown in Figures 7A to 7D, and 8.
  • the components of the semiconductor device shown in Figures 9A to 9D, 10A, and 10B are the components of the semiconductor device shown in Figures 7A to 7D, and 8, with D or E added. That is, the components of the transistor 200aD on the A3 side are the oxide 230D (oxide 230aD and oxide 230bD), conductor 242aD, conductor 242bD, conductor 240aD, conductor 240bD, insulator 241aD, and insulator 241bD.
  • the components of the transistor 200aE on the A4 side are the oxide 230E (oxide 230aE and oxide 230bE), conductor 242aE, conductor 242bE, conductor 240aE, conductor 240bE, insulator 241aE, and insulator 241bE.
  • oxide 230E oxide 230aE and oxide 230bE
  • conductor 242aE conductor 242bE
  • conductor 240aE conductor 240aE
  • conductor 240bE insulator 241aE
  • insulator 241bE insulator 241bE
  • oxide 230aD, oxide 230bD, and conductor 242aD are provided separately from oxide 230aE, oxide 230bE, and conductor 242aE (conductor 242bE) on insulator 225. Therefore, as shown in FIG. 10B, oxide 230aD, oxide 230bD, conductor 242aD, conductor 242bD, oxide 230aE, oxide 230bE, conductor 242aE, and conductor 242bE are not formed above at least a portion of insulator 225.
  • oxide 230D oxide 230aD and oxide 230bD
  • oxide 230bD oxide 230bD
  • oxide 230E oxide 230aE and oxide 230bE
  • Each layer constituting the semiconductor device may have a single layer structure or a multilayer structure.
  • insulating substrate for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate can be mentioned.
  • semiconductor substrate for example, a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be mentioned.
  • a semiconductor substrate having an insulator region inside the semiconductor substrate for example, an SOI (Silicon On Insulator) substrate
  • the conductive substrate for example, a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate
  • the substrate for example, a substrate having a metal nitride, a substrate having a metal oxide, a substrate having a conductor or semiconductor provided on an insulator substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate can be mentioned.
  • one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.
  • insulator examples include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.
  • Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxide nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxide nitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.
  • Examples of insulators with low dielectric constants include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with voids, and resin.
  • the electrical characteristics of a transistor using a metal oxide can be stabilized by surrounding it with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen.
  • an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen for example, an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer.
  • an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen
  • metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide
  • metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • the insulator that functions as the gate insulator is an insulator having a region containing oxygen that is released by heating.
  • the oxygen vacancies in oxide 230 can be compensated for.
  • a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc.
  • tantalum nitride titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel can be mentioned.
  • tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed.
  • a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • a layered structure combining the material containing the metal element described above with a conductive material containing oxygen for example, a layered structure combining the material containing the metal element described above with a conductive material containing oxygen, a layered structure combining the material containing the metal element described above with a conductive material containing nitrogen, or a layered structure combining the material containing the metal element described above with a conductive material containing oxygen and a conductive material containing nitrogen may be applied.
  • an oxide is used for the channel formation region of a transistor, it is preferable to use a layered structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductor that functions as the gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.
  • a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor that functions as a gate electrode may also be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride, may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may also be used.
  • Indium gallium zinc oxide containing nitrogen may also be used.
  • a metal oxide that functions as a semiconductor is preferably used as the oxide 230.
  • Metal oxides that can be used as the oxide 230 of one embodiment of the present invention are described below.
  • the metal oxide preferably contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition to these, it is preferable that it contains aluminum, gallium, yttrium, tin, antimony, etc. Furthermore, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.
  • the metal oxide is an In-M-Zn oxide having indium, element M, and zinc.
  • the element M is aluminum, gallium, yttrium, tin, or antimony.
  • Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.
  • the element M may be a combination of multiple of the above elements.
  • metal oxides containing nitrogen may also be collectively referred to as metal oxides.
  • Metal oxides containing nitrogen may also be referred to as metal oxide nitrides.
  • Crystal structures of oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystalline.
  • oxide semiconductors may be classified differently from the above when focusing on their structure. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductors), amorphous oxide semiconductors, and the like.
  • CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis oriented in a specific direction.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film.
  • the c-axis is preferably oriented in the normal direction of the surface of the insulator 225.
  • the crystalline region is a region having periodic atomic arrangement.
  • the crystalline region is also a region in which the lattice arrangement is uniform.
  • the CAAC-OS has a region in which a plurality of crystalline regions are connected in the a-b plane direction, and the region may have distortion.
  • the distortion refers to a portion in which the direction of the lattice arrangement is changed between a region in which the lattice arrangement is uniform and another region in which the lattice arrangement is uniform in a region in which the plurality of crystalline regions are connected. That is, the CAAC-OS is an oxide semiconductor that is c-axis aligned and does not clearly have an alignment in the a-b plane direction.
  • Each of the multiple crystal regions is composed of one or more tiny crystals (crystals with a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the maximum diameter of the crystal region may be several tens of nm.
  • CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries.
  • CAAC-OS since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor having CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having CAAC-OS is resistant to heat and highly reliable.
  • CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.
  • the nc-OS has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • the nc-OS has microcrystals.
  • the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals.
  • the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.
  • the a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.
  • CAC-OS relates to the material composition.
  • CAC-OS is a material in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that in the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and a region containing the metal elements is mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch shape.
  • CAC-OS is a structure in which the material is separated into a first region and a second region, forming a mosaic shape, and the first region is distributed throughout the film (hereinafter also referred to as a cloud shape).
  • CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
  • CAC-OS in In-Ga-Zn oxide refers to a material composition containing In, Ga, Zn, and O, in which some regions (first regions) mainly composed of In and some regions (second regions) mainly composed of Ga are arranged in a mosaic pattern, and these regions exist randomly. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed non-uniformly.
  • CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not heated.
  • any one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas can be used as the film-forming gas.
  • the flow rate ratio of oxygen gas to the total flow rate of film-forming gas during film formation is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.
  • the first region is a region with higher conductivity than the second region.
  • the first region exhibits conductivity as a metal oxide when carriers flow through it. Therefore, the first region is distributed in a cloud-like shape in the metal oxide, achieving high field-effect mobility ( ⁇ ).
  • the second region has higher insulating properties than the first region.
  • the second region being distributed in the metal oxide can suppress leakage current.
  • the CAC-OS when used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, so that the CAC-OS can be given a switching function (on/off function).
  • the CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and the whole material has a function as a semiconductor. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using the CAC-OS in a transistor, a high on-current (I on ), a high field-effect mobility ( ⁇ ), and a good switching operation can be realized.
  • CAC-OS is ideal for a variety of semiconductor devices including display devices.
  • Oxide semiconductors have a variety of structures, each with different characteristics.
  • An oxide semiconductor according to one embodiment of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.
  • the semiconductor layer of the transistor may be made of a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor), such as a semiconductor of an element such as silicon or a compound semiconductor such as gallium arsenide.
  • a semiconductor material having a band gap such as a semiconductor of an element such as silicon or a compound semiconductor such as gallium arsenide.
  • transition metal chalcogenide that functions as a semiconductor in the semiconductor layer of the transistor.
  • transition metal chalcogenides that can be applied to the semiconductor layer of the transistor include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), molybdenum tellurium (typically MoTe 2 ), tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten tellurium (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically HfSe 2 ), zirconium sulfide (typically ZrS 2 ), and zirconium selenide (typically ZrSe 2 ).
  • a in each figure shows a top view.
  • B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in A of each figure, and is also a cross-sectional view in the channel length direction of transistor 200.
  • C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in A of each figure, and is also a cross-sectional view in the channel width direction of transistor 200.
  • D in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in A of each figure, and is also a cross-sectional view in the channel width direction of transistor 200. Note that some elements are omitted from the top view in A of each figure to clarify the figure.
  • insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like, as appropriate.
  • CVD chemical vapor deposition
  • MBE molecular beam epitaxy
  • PLD pulsed laser deposition
  • ALD ALD method
  • Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner.
  • RF sputtering is mainly used when depositing insulating films
  • DC sputtering is mainly used when depositing metal conductive films.
  • Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using the reactive sputtering method.
  • CVD methods can be classified into plasma CVD (PECVD) methods, which use plasma, thermal CVD (TCVD: Thermal CVD) methods, which use heat, and photo CVD (Photo CVD) methods, which use light. They can also be further divided into metal CVD (MCVD: Metal CVD) methods and metal organic CVD (MOCVD: Metal CVD) methods, depending on the source gas used.
  • PECVD plasma CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal CVD
  • the plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can reduce plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, with the thermal CVD method, which does not use plasma, such plasma damage does not occur, and the yield of semiconductor devices can be increased. Furthermore, with the thermal CVD method, no plasma damage occurs during film formation, so films with fewer defects can be obtained.
  • the ALD method can be a thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy, or a PEALD method in which a plasma-excited reactant is used.
  • the CVD and ALD methods are different from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios.
  • the ALD method since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.
  • a film of any composition can be formed by changing the flow rate ratio of the source gases.
  • a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film.
  • a film of any composition can be formed by simultaneously introducing multiple different types of precursors.
  • a film of any composition can be formed by controlling the number of cycles of each precursor.
  • the insulator 215 can be an insulator similar to one or more stacked films of the insulators 282 and 283.
  • the method for forming the insulator 215 can be, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the sputtering method which does not require the use of molecules containing hydrogen in the film formation gas, is preferable because it can reduce the hydrogen concentration in the insulator 215.
  • the insulator 216 is formed on the insulator 215.
  • the insulator 216 is preferably formed by a sputtering method.
  • a sputtering method that does not require the use of molecules containing hydrogen in the film formation gas, the hydrogen concentration in the insulator 216 can be reduced.
  • the formation of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate.
  • a silicon oxide film is formed as the insulator 216 by a sputtering method.
  • insulators 215 and 216 it is preferable to deposit the insulators 215 and 216 in succession without exposing them to the atmosphere.
  • a multi-chamber deposition apparatus can be used. This allows the insulators 215 and 216 to be deposited with reduced hydrogen in the films, and further reduces the incorporation of hydrogen into the films between each deposition process.
  • an opening is formed in the insulator 216, reaching the insulator 215.
  • the opening may be formed by wet etching, but dry etching is preferable for fine processing.
  • the insulator 215 may be silicon nitride, aluminum oxide, hafnium oxide, or the like.
  • the conductive film that will become the conductor 205a desirably contains a conductor that has a function of suppressing oxygen transmission.
  • a conductor that has a function of suppressing oxygen transmission For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, it can be a laminated film of a conductor that has a function of suppressing oxygen transmission and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy.
  • the conductive film that will become the conductor 205a can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc.
  • titanium nitride is deposited as the conductive film that becomes conductor 205a.
  • a metal nitride as the lower layer of conductor 205b, it is possible to prevent conductor 205b from being oxidized by insulator 216 and the like.
  • conductor 205b even if a metal that easily diffuses, such as copper, is used as conductor 205b, it is possible to prevent the metal from diffusing out of conductor 205a.
  • a conductive film that will become the conductor 205b is formed. Tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy, or the like can be used as the conductive film that will become the conductor 205b.
  • the conductive film can be formed by plating, sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, tungsten is formed as the conductive film that will become the conductor 205b.
  • a CMP process is performed to remove a portion of the conductive film that will become conductor 205a and a portion of the conductive film that will become conductor 205b, exposing insulator 216 (see Figures 11A to 11D). As a result, conductor 205a and conductor 205b remain only in the openings. Note that the CMP process may remove a portion of insulator 216.
  • a film of insulator 221 is formed on insulator 216 and conductor 205 (see Figures 12A to 12D).
  • the insulator 221 may be an insulator having barrier properties against oxygen, hydrogen, and water.
  • the insulator 221 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • a silicon nitride film is formed as the insulator 221 by a PEALD method.
  • a film of insulator 222 is formed on insulator 221 (see Figures 12A to 12D).
  • the insulator 222 it is preferable to form a film of an insulator containing one or both of aluminum and hafnium oxides.
  • the insulator containing one or both of aluminum and hafnium oxides it is preferable to use, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Alternatively, it is preferable to use hafnium zirconium oxide.
  • An insulator containing one or both of aluminum and hafnium oxides has a barrier property against oxygen, hydrogen, and water.
  • the insulator 222 has a barrier property against hydrogen and water, the hydrogen and water contained in the structure provided around the transistor are prevented from diffusing into the inside of the transistor through the insulator 222, and the generation of oxygen vacancies in the oxide 230 can be suppressed.
  • the insulator 222 can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD.
  • a hafnium oxide film is formed as the insulator 222 by ALD.
  • an insulating film is formed on the insulator 222, and the insulating film is etched to form the insulator 223 (see Figures 12A to 12D).
  • the insulator 223 functions as a sacrificial layer for forming the insulator 225.
  • an insulator that can be used for the insulator 216 may be used.
  • the insulator 223 can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD.
  • a silicon oxide film is formed as the insulator 223 by sputtering.
  • the insulator 223 can be processed into an island shape using lithography. This can be done using dry etching or wet etching. Dry etching is suitable for fine processing.
  • the side of the insulator 223 may be configured to be perpendicular or approximately perpendicular to the top surface of the insulator 222. This configuration allows for a smaller area and higher density when providing multiple transistors.
  • a heat treatment may be performed before the formation of the insulator 223.
  • the heat treatment may be performed under reduced pressure, and the insulator 223 may be continuously formed without exposure to the atmosphere.
  • moisture and hydrogen adsorbed on the surface of the insulator 222 can be removed, and the moisture concentration and hydrogen concentration in the insulator 222 can be further reduced.
  • the heat treatment can prevent impurities such as moisture or hydrogen from entering from below the insulator 221.
  • the temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is 250°C.
  • Insulating film 225f which will become insulator 225, is formed to cover insulator 223 (see Figures 13A to 13D).
  • Insulating film 225f is an insulating film that will become insulator 225 in a later process, and the insulators described above can be used.
  • Insulating film 225f can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulating film 225f is formed along the insulator 223, it is preferable that the insulating film 225f has good coverage. Therefore, it is preferable that the insulating film 225f is formed using an ALD method or the like that has good coverage. Also, since it is preferable that the insulator 225 has a high aspect ratio, it is preferable that the insulating film 225f has a thin film thickness. Therefore, it is preferable to form the insulating film 225f using an ALD method that allows the film thickness to be adjusted to a thin film thickness. For example, it is preferable to form a film of hafnium oxide as the insulating film 225f using a thermal ALD method. By forming the insulating film 225f in this manner, the insulating film 225f is formed in contact with the upper surface and side surfaces of the insulator 223.
  • the insulator 225 is removed by anisotropic etching, and then the insulator 223 is removed (see Figures 14A to 14D).
  • the channel width of the transistor 200 can be increased without increasing the occupation area, and therefore the on-current, field effect mobility, and frequency characteristics of the transistor 200 can be improved.
  • the contact area between the oxide 230b and the conductors 242a and 242b can be increased without increasing the occupation area, and therefore the on-current, field effect mobility, and frequency characteristics of the transistor 200 can be improved.
  • the distance between the two insulators 225 can be set to match the size of the insulator 223. Therefore, the distance between the insulators 225 can be reduced, the area occupied by the transistors 200a and 200b can be reduced, and the semiconductor device and memory device can be highly integrated. This can increase the memory capacity of the memory device.
  • an etching gas containing halogen can be used, specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used.
  • an etching gas containing one or more of fluorine, chlorine, and bromine can be used.
  • C4F6 gas , C5F6 gas , C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, CH2F2 gas, Cl2 gas, BCl3 gas, SiCl4 gas, or BBr3 gas can be used alone or in a mixture of two or more gases.
  • oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be appropriately added to the above etching gas.
  • a gas containing no halogen gas but a hydrocarbon gas or hydrogen gas can be used as the etching gas.
  • the hydrocarbon used in the etching gas may be one or more of methane ( CH4 ), ethane ( C2H6 ) , propane ( C3H8 ), butane ( C4H10 ), ethylene (C2H4), propylene (C3H6), acetylene (C2H2), and propyne (C3H4 ) .
  • the etching conditions may be appropriately set according to the object to be etched.
  • a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used as the dry etching device.
  • the capacitively coupled plasma etching device having parallel plate electrodes can be configured to apply a high frequency voltage to one of the parallel plate electrodes. Alternatively, it can be configured to apply a plurality of different high frequency voltages to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply high frequency voltages of different frequencies to each of the parallel plate electrodes.
  • a dry etching device having a high density plasma source can be used.
  • an inductively coupled plasma (ICP) etching device can be used as the dry etching device having a high density plasma source.
  • ICP inductively coupled plasma
  • a mixed gas of C 4 F 8 , H 2 , and Ar may be used as an etching gas in a CCP etching apparatus.
  • the removal of the insulator 223 can be performed by dry etching or wet etching.
  • the insulator 223 can be removed by wet etching.
  • Insulator 225 when formed by anisotropic etching, is formed in a sidewall shape in contact with the side surface of insulator 223. In other words, insulator 225 is formed in a circumferential shape surrounding insulator 223. When a semiconductor device is manufactured while maintaining insulator 225 in a circumferential shape, insulator 225 becomes an integral part of transistors 200a and 200b, as shown in Figures 5A to 5D.
  • the insulator 225 is formed by removing the portion of the sidewall-shaped insulator that is not necessary for the configuration of the semiconductor device.
  • the unnecessary portion of the insulator 225 may be etched first before anisotropic etching of the insulating film 225f is performed.
  • an oxide film 230af is formed on the insulator 222 and the insulator 225, and an oxide film 230bf is formed on the oxide film 230af (see FIGS. 15A to 15D).
  • a metal oxide corresponding to the oxide 230a may be used as the oxide film 230af, and a metal oxide corresponding to the oxide 230b may be used as the oxide film 230bf. It is preferable that the oxide films 230af and 230bf are successively formed without being exposed to the air environment.
  • the films By forming the films without exposing them to the air, it is possible to prevent impurities or moisture from the air environment from adhering to the oxide films 230af and 230bf, and it is possible to keep the interface or the vicinity of the interface between the oxide films 230af and 230bf clean.
  • Oxide film 230af and oxide film 230bf can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the oxide film 230af and the oxide film 230bf are preferably formed by the ALD method, which has good coverage.
  • the oxide film 230af and the oxide film 230bf can be formed with good coverage on the side surface of the insulator 225. This allows channel formation regions to be provided on the side surface of the insulator 225 on the A3 side and the A4 side in the transistor 200, so that the channel width of the transistor 200 can be increased. This allows the field effect mobility, on-current, and frequency characteristics of the transistor 200 to be improved.
  • the ALD method can control the composition of the film obtained by adjusting the amount of raw material gas introduced.
  • the ALD method can form oxide film 230af and oxide film 230bf of any composition by adjusting the amount of raw material gas introduced, the number of introductions (also called the number of pulses), the time required for one pulse (also called the pulse time), etc.
  • the ALD method can form oxide film 230af and oxide film 230bf whose composition changes continuously by changing the raw material gas while forming the film.
  • the time required for film formation can be shortened compared to forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.
  • the oxide film 230af and the oxide film 230bf may be formed as a laminated structure of the above metal oxide layers.
  • the oxide film 230af and the oxide film 230bf may be formed by sputtering.
  • oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas.
  • the sputtering gas By increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the oxide film to be formed can be increased.
  • an In-M-Zn oxide target or the like can be used.
  • an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and not more than 100%, preferably 70% to 100%.
  • a transistor using an oxygen-excessive oxide semiconductor in a channel formation region can have relatively high reliability.
  • one embodiment of the present invention is not limited to this.
  • an oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%,.
  • a transistor using an oxygen-deficient oxide semiconductor in a channel formation region can have relatively high field effect mobility.
  • the crystallinity of the oxide film can be improved by forming the film while heating the substrate.
  • Each oxide film can be formed according to the desired characteristics of oxide 230a and oxide 230b by appropriately selecting the film formation conditions and atomic ratio.
  • the oxide film 230af may be formed by a sputtering method, and the oxide film 230bf may be formed by an ALD method.
  • the oxide film 230af and the oxide film 230bf may have a laminated structure.
  • the oxide film 230bf may be the above-mentioned metal oxide layer formed using the ALD method.
  • the crystallinity of the oxide film 230af can be increased by forming the oxide film 230af by sputtering. For example, by increasing the crystallinity of the oxide film 230af and then forming the oxide film 230bf on the oxide film 230af, a part or all of the oxide film 230bf can be crystallized. In other words, by increasing the crystallinity of the oxide film 230af, it is possible to increase the crystallinity of the oxide film 230bf as well. For example, if the oxide film 230af is an oxide semiconductor film with a CAAC structure, the oxide film 230bf formed on the oxide film 230af can also be an oxide semiconductor with a CAAC structure.
  • oxide film 230bf By forming the oxide film 230bf using the ALD method, a thin film can be formed with good controllability. This allows the oxide film 230bf to have a thin film thickness as designed. By using such oxide film 230af and oxide film 230bf, it is possible to improve the electrical characteristics and reliability of the transistor 200.
  • the oxide film 230af and the oxide film 230bf without exposing them to the atmosphere.
  • the heat treatment may be performed within a temperature range in which the oxide film 230af and the oxide film 230bf do not become polycrystallized.
  • the temperature of the heat treatment is preferably 100°C or higher, 250°C or higher, or 350°C or higher, and 650°C or lower, 600°C or lower, or 550°C or lower.
  • the heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • an atmosphere of nitrogen gas or an inert gas or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment may be carried out in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to set the oxygen gas concentration at about 20%.
  • the heat treatment may be carried out under reduced pressure.
  • the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the oxygen that has been released.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less.
  • the heat treatment is performed at a temperature of 450° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas of 4:1.
  • This heat treatment including oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 230af and the oxide film 230bf.
  • impurities such as carbon, water, and hydrogen in the oxide film 230af and the oxide film 230bf.
  • the crystallinity of the oxide film 230af and the oxide film 230bf can be improved, resulting in a denser and more compact structure.
  • This increases the crystalline region in the oxide film 230af and the oxide film 230bf, and reduces the in-plane variation of the crystalline region in the oxide film 230af and the oxide film 230bf. This reduces the in-plane variation of the electrical characteristics of the transistor.
  • oxide film 230af and oxide film 230bf (later oxide 230a and oxide 230b) function as a channel formation region of transistor 200.
  • Transistor 200 formed using oxide film 230af and oxide film 230bf in which the hydrogen concentration is reduced is preferable because it has good reliability.
  • a conductive film 242f is formed on the oxide film 230bf (see Figures 15A to 15D). Conductors corresponding to the above-mentioned conductors 242a and 242b may be used as the conductive film 242f.
  • the conductive film 242f is formed on and in contact with the oxide film 230bf without an etching process or the like, so that the upper surface of the oxide film 230bf can be protected by the conductive film 242f. This can reduce the diffusion of impurities into the oxide 230 that constitutes the transistor, thereby improving the electrical characteristics and reliability of the semiconductor device.
  • the conductive film 242f can be formed, for example, by sputtering, CVD, MBE, PLD, or ALD. By using the ALD method, the conductive film 242f can be formed with good coverage on the side surface of the insulator 225. For example, tantalum nitride can be formed as the conductive film 242f by the ALD method. By forming the conductive film 242f with good coverage in this way, the contact area between the oxide 230b and the conductors 242a and 242b can be increased without increasing the occupied area. This can improve the on-current and frequency characteristics of the transistor 200.
  • the oxide film 230af, the oxide film 230bf, and the conductive film 242f are processed into an island shape using lithography to form the oxide 230a, the oxide 230b, and the conductor 242A (see Figures 16A to 16D).
  • the oxide 230a, oxide 230b, and conductor 242A that form the transistor 200a are separated from the oxide 230a, oxide 230b, and conductor 242A that form the transistor 200b.
  • the oxide 230a, oxide 230b, and conductor 242A are formed so as to cover the insulator 225 that forms the transistor 200a and the insulator 225 that forms the transistor 200b, respectively.
  • the above processing can be performed using a dry etching method or a wet etching method. Processing using the dry etching method is suitable for fine processing. Note that the above description can be referred to for the conditions of the dry etching method and the dry etching apparatus. In addition, the processing of the oxide film 230af, the oxide film 230bf, and the conductive film 242f may be performed under different conditions.
  • oxide 230a, oxide 230b, and conductor 242A into an island shape collectively.
  • two or more side ends of oxide 230a, oxide 230b, and conductor 242A coincide or approximately coincide with each other.
  • oxide 230a, oxide 230b, and conductor 242A are formed so that at least a portion of them overlaps with conductor 205. Furthermore, insulator 222 is exposed in the region where insulator 222 does not overlap with oxide 230a, oxide 230b, and conductor 242A.
  • the side surfaces of oxide 230a, oxide 230b, and conductor 242A may be configured to be perpendicular or approximately perpendicular to the top surface of insulator 222. By using such a configuration, it is possible to reduce the area and increase the density when providing multiple transistors.
  • the side surfaces of oxide 230a, oxide 230b, and conductor 242A may be tapered.
  • the taper angle of the side surfaces of oxide 230a, oxide 230b, and conductor 242A may be, for example, 60° or more and less than 90°.
  • the resist is first exposed through a mask.
  • the exposed area is removed or left using a developer to form a resist mask.
  • a conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask.
  • a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light.
  • a liquid immersion technique can be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed.
  • an electron beam or an ion beam can be used instead of the light described above.
  • a mask may not be used.
  • the resist mask that is no longer needed after processing can be removed by performing a dry etching process such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.
  • a dry etching process such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.
  • a hard mask made of an insulator or conductor may be used under the resist mask.
  • an insulating film or conductive film that will be the hard mask material is formed on the conductive film 242f, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of the desired shape.
  • Etching of the conductive film 242f etc. may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching.
  • the hard mask may be removed by etching after etching the oxide film 230bf etc.
  • the material of the hard mask does not affect the later process or can be used in the later process, it is not necessarily necessary to remove the hard mask.
  • a configuration may be adopted in which an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film are formed between the workpiece and the resist mask.
  • SOC Spin On Carbon
  • SOG Spin On Glass
  • a SOC film, an SOG film, and a resist mask can be formed in this order on the workpiece, and then lithography can be performed.
  • the conductive film 242f may be divided into the conductor 242a and the conductor 242b, and the oxide film 230af and the oxide film 230bf may be anisotropically etched using the mask used to divide the conductor 242a and the conductor 242b.
  • the oxide 230a and the oxide 230b can be formed in a sidewall shape with respect to the insulator 225 in the regions that do not overlap with the conductor 242a and the conductor 242b, as shown in FIGS. 7A to 7D and 8.
  • a film of insulator 275 is formed to cover oxide 230a, oxide 230b, and conductor 242A, and then a film of insulator 280 is formed on insulator 275 (see Figures 17A to 17D).
  • the insulators described above may be used as insulator 275 and insulator 280.
  • the insulator 275 contacts the upper surface of the insulator 222.
  • the insulator 280 it is preferable to form an insulating film that will become the insulator 280, and then perform CMP processing on the insulating film to form an insulator with a flat upper surface. Note that it is also possible to form a film of silicon nitride on the insulator 280, for example, by a sputtering method, and then perform CMP processing on the silicon nitride until it reaches the insulator 280.
  • Insulator 275 and insulator 280 can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulator 275 it is preferable to use an insulator that has a function of suppressing oxygen transmission.
  • an insulator that has a function of suppressing oxygen transmission.
  • the oxide 230a, the oxide 230b, and the conductor 242A can be covered with the insulator 275, which has the function of suppressing the diffusion of oxygen. This makes it possible to reduce the direct diffusion of oxygen from the insulator 280, etc., to the oxide 230a, the oxide 230b, and the conductor 242A in a later process.
  • a film of silicon oxide as the insulator 280 by a sputtering method.
  • the insulator 280 containing excess oxygen can be formed.
  • the hydrogen concentration in the insulator 280 can be reduced.
  • a heat treatment may be performed before the formation of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be continuously formed without exposure to the atmosphere.
  • moisture and hydrogen adsorbed on the surface of the insulator 275, etc. can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced.
  • the heat treatment conditions described above can be used for the heat treatment.
  • lithography is used to process the conductor 242A, the insulator 275, and the insulator 280 to form an opening that reaches the oxide 230b and the insulator 222 (see Figures 18A to 18D).
  • the conductor 242A is divided to form the conductor 242a and the conductor 242b.
  • the opening is formed in the region where the oxide 230b and the conductor 205 overlap.
  • lithography methods can be used as appropriate.
  • a lithography method using short-wavelength light such as EUV light or an electron beam.
  • the above processing is preferably carried out using a dry etching method.
  • Dry etching is suitable for forming openings with high aspect ratios because it allows for anisotropic etching. Please refer to the above description for the conditions for the dry etching method and the dry etching apparatus.
  • an ashing process using oxygen plasma may be performed.
  • impurities that are generated in the above etching process and diffused into the oxide 230, etc. can be removed.
  • the impurities include those that originate from components contained in the workpiece of the above etching process and components contained in the gas used in the etching process. Examples of the impurities include chlorine, fluorine, tantalum, silicon, and hafnium.
  • chlorine gas is used in processing the conductor 242A, the oxide 230 is exposed to an atmosphere containing chlorine gas, so it is preferable to remove the chlorine attached to the oxide 230. By removing the impurities attached to the oxide 230 in this way, the electrical characteristics and reliability of the transistor can be improved.
  • a cleaning process may be performed to remove impurities that have adhered to the surface of oxide 230b during the etching process.
  • Cleaning methods include wet cleaning using a cleaning solution (which may also be called wet etching), plasma processing using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.
  • wet cleaning may be performed using an aqueous solution of one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid diluted with carbonated water or pure water, pure water, carbonated water, etc.
  • ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water.
  • these cleaning methods may be combined as appropriate.
  • an aqueous solution in which hydrofluoric acid is diluted with pure water may be referred to as diluted hydrofluoric acid
  • an aqueous solution in which ammonia water is diluted with pure water may be referred to as diluted ammonia water.
  • the concentration and temperature of the aqueous solution are adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned.
  • the ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less.
  • the hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.
  • a frequency of 200 kHz or more for ultrasonic cleaning and more preferably a frequency of 900 kHz or more. By using such a frequency, damage to the oxide 230b, etc. can be reduced.
  • the above cleaning process may be performed multiple times, and the cleaning solution may be changed for each cleaning process.
  • a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water
  • a second cleaning process may be performed using pure water or carbonated water.
  • wet cleaning is performed using diluted ammonia water.
  • impurities attached to the surfaces of oxide 230a, oxide 230b, etc. or diffused inside can be removed. Furthermore, the crystallinity of oxide 230a, oxide 230b, etc. can be improved.
  • the temperature of the heat treatment is preferably 100° C. or more, 250° C. or more, or 350° C. or more, and 650° C. or less, 600° C. or less, 550° C. or less, or 400° C. or less.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment is preferably performed in an atmosphere containing oxygen, and is preferably performed, for example, at a temperature of 350° C. for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1.
  • the heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.
  • the sheet resistance may decrease in the region of the oxide 230b that overlaps with the conductor 242a and the region that overlaps with the conductor 242b.
  • the carrier concentration may also increase. Therefore, the resistance of the region of the oxide 230b that overlaps with the conductor 242a and the region that overlaps with the conductor 242b can be reduced in a self-aligned manner.
  • an insulating film 250A that will become the insulator 250 is formed so as to fill the openings formed in the insulator 280 and the like (see Figures 19A to 19D).
  • the insulating film 250A contacts the insulator 280, the insulator 275, the conductor 242a, the conductor 242b, the insulator 222, the oxide 230a, and the oxide 230b.
  • the insulating film 250A can be formed by sputtering, CVD, MBE, PLD, or ALD.
  • the insulating film 250A is preferably formed by ALD.
  • the insulating film 250A is preferably formed to a thin thickness, and it is necessary to reduce the variation in thickness.
  • the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizing agent) are alternately introduced, and the thickness can be adjusted by the number of times this cycle is repeated, allowing for precise thickness adjustment.
  • the insulating film 250A needs to be formed with good coverage on the bottom and side surfaces of the opening. By using the ALD method, layers of atoms can be deposited one by one on the bottom and side surfaces of the opening, so that the insulating film 250A can be formed with good coverage on the opening.
  • ozone ( O3 ), oxygen ( O2 ), water ( H2O ), etc. can be used as an oxidizing agent.
  • Ozone ( O3 ), oxygen ( O2 ), etc. that do not contain hydrogen can be used as an oxidizing agent.
  • the insulator 250 can have a layered structure as shown in FIG. 2 and the like.
  • the insulator 250 can have a layered structure of insulators 250a to 250d.
  • aluminum oxide can be deposited by thermal ALD as the insulator 250a
  • silicon oxide can be deposited by PEALD as the insulator 250b
  • hafnium oxide can be deposited by thermal ALD as the insulator 250c
  • silicon nitride can be deposited by PEALD as the insulator 250d.
  • microwave treatment refers to treatment using, for example, an apparatus having a power source that generates high-density plasma using microwaves.
  • microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.
  • the microwave processing it is preferable to use a microwave processing device having a power source that generates high-density plasma using microwaves.
  • the frequency of the microwave processing device is preferably 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, and can be set to, for example, 2.45 GHz.
  • the power of the power source that applies microwaves in the microwave processing device is preferably 1000 W or more and 10,000 W or less, more preferably 2000 W or more and 5000 W or less.
  • the microwave processing device may have a power source that applies RF to the substrate side. In addition, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the oxide 230b.
  • the microwave treatment is preferably carried out under reduced pressure, with the pressure being preferably 10 Pa to 1000 Pa, and more preferably 300 Pa to 700 Pa.
  • the treatment temperature is preferably 750°C or less, and more preferably 500°C or less, and can be, for example, about 250°C.
  • a heat treatment may be carried out continuously without exposure to the outside air.
  • the heat treatment temperature is, for example, preferably 100°C to 750°C, and more preferably 300°C to 500°C.
  • the microwave treatment can be performed using oxygen gas and argon gas.
  • the oxygen flow ratio (O 2 /(O 2 +Ar)) is greater than 0% and less than 100%.
  • the oxygen flow ratio (O 2 /(O 2 +Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio (O 2 /(O 2 +Ar)) is greater than 10% and less than 40%. More preferably, the oxygen flow ratio (O 2 /(O 2 +Ar)) is greater than 10% and less than 30%.
  • oxygen gas By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region between the conductor 242a and the conductor 242b of the oxide 230b.
  • VOH in the region By the action of plasma, microwaves, or the like, VOH in the region can be separated into oxygen vacancies and hydrogen, and hydrogen can be removed from the region.
  • an insulating film e.g., aluminum oxide
  • hydrogen generated by the microwave treatment can be captured or fixed to the insulator 250a.
  • VOH contained in the channel formation region can be reduced.
  • oxygen vacancies and VOH in the channel formation region can be reduced, and the carrier concentration can be reduced.
  • the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be reduced.
  • the oxygen injected into the channel formation region can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also called O radicals, which are atoms, molecules, or ions with an unpaired electron).
  • the oxygen injected into the channel formation region can be in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.
  • the film quality of the insulator 250 can be improved, thereby improving the reliability of the transistor.
  • impurities such as carbon in the oxide 230b can also be removed.
  • carbon which is an impurity in the oxide 230b
  • the crystallinity of the oxide 230b can be improved. This allows the oxide 230b to become CAAC-OS.
  • carbon contained in the precursor may be incorporated into the oxide 230b, so it is preferable to remove the carbon by microwave treatment.
  • conductors 242a and 242b preferably function as a shielding film against the action of microwaves, high frequency waves such as RF, oxygen plasma, etc., when microwave processing is performed in an atmosphere containing oxygen.
  • conductors 242a and 242b preferably have the function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.
  • the conductors 242a and 242b shield against the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc., and therefore these effects do not extend to the regions of the oxide 230b that overlap with either of the conductors 242a and 242b.
  • the microwave treatment does not reduce VOH in the source and drain regions, and does not supply an excessive amount of oxygen, thereby preventing a decrease in carrier concentration.
  • oxygen vacancies and VOH can be selectively removed from the channel formation region of the oxide semiconductor to make the channel formation region i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions functioning as source and drain regions can be suppressed, and the conductivity (the state of being a low-resistance region) before the microwave treatment can be maintained. This can suppress fluctuations in the electrical characteristics of the transistor, and can suppress variations in the electrical characteristics of the transistor within the substrate surface.
  • thermal energy may be directly transferred to the oxide 230b due to electromagnetic interaction between the microwaves and the molecules in the oxide 230b.
  • This thermal energy may heat the oxide 230b.
  • This type of heating process may be called microwave annealing.
  • microwave annealing By performing microwave processing in an atmosphere containing oxygen, it may be possible to obtain an effect equivalent to that of oxygen annealing.
  • the oxide 230b contains hydrogen, it is thought that this thermal energy is transferred to the hydrogen in the oxide 230b, which activates the hydrogen and causes it to be released from the oxide 230b.
  • the diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, by performing a post-process such as forming a conductive film that becomes the conductor 260, or a post-process such as heat treatment, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. through the insulator 250 into the oxide 230b, the oxide 230a, etc. In this way, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.
  • a heat treatment may be performed while maintaining the reduced pressure state after the microwave treatment.
  • hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be efficiently removed.
  • some of the hydrogen may be gettered to the conductors 242a and 242b.
  • a step of performing a heat treatment may be repeated multiple times while maintaining the reduced pressure state after the microwave treatment.
  • the heat treatment temperature is preferably 300°C or higher and 500°C or lower.
  • the microwave treatment i.e., microwave annealing, may also serve as the heat treatment. If the oxide 230b, etc. is sufficiently heated by the microwave annealing, the heat treatment may not be performed.
  • microwave treatment When the insulator 250 has a layered structure of insulators 250a to 250d, it is preferable to perform microwave treatment after the formation of insulator 250b. Furthermore, microwave treatment may be performed again after the formation of insulator 250c. In this way, microwave treatment in an oxygen-containing atmosphere may be performed multiple times (at least two or more times).
  • Conductive film 260A and conductive film 260B that will become conductor 260b are formed in this order (see Figures 20A to 20D).
  • Conductive film 260A and conductive film 260B can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method.
  • titanium nitride is formed as conductive film 260A using the ALD method
  • tungsten is formed as conductive film 260B using the CVD method.
  • the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed.
  • the portions of the insulating film 250A, the conductive film 260A, and the conductive film 260B exposed from the openings are removed. This forms the insulator 250 and the conductor 260 (conductor 260a and conductor 260b) in the openings that overlap the conductor 205 (see Figures 21A to 21D).
  • insulator 250 is provided in the opening in contact with insulator 280, insulator 275, conductor 242a, conductor 242b, oxide 230b, oxide 230a, and insulator 222.
  • Conductor 260 is also arranged to fill the opening via insulator 250. In this manner, transistor 200 is formed.
  • the insulator 282 is formed on the insulator 250, the conductor 260, and the insulator 280.
  • the insulator 282 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulator 282 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the film formation gas, the hydrogen concentration in the insulator 282 can be reduced.
  • the insulator 282 in an oxygen-containing atmosphere using a sputtering method, oxygen can be added to the insulator 280 while the film is being formed. This allows the insulator 280 to contain excess oxygen. At this time, it is preferable to form the insulator 282 while heating the substrate.
  • oxygen can be diffused from the insulator 280 through the insulator 250 to the oxide 230b, and a suitable amount of oxygen can be supplied to the oxide 230b.
  • an excess amount of oxygen can be supplied into the insulator 250, which can prevent the conductors 242a and 242b near the insulator 250 from being excessively oxidized.
  • an aluminum oxide film is formed as the insulator 282 by sputtering using an aluminum target in an atmosphere containing oxygen gas.
  • the amount of oxygen injected into the layer below the insulator 282 can be controlled by the magnitude of the RF power applied to the substrate by the sputtering method. For example, the smaller the RF power, the less the amount of oxygen injected into the layer below the insulator 282, and the amount of oxygen is likely to be saturated even if the insulator 282 is thin. Also, the larger the RF power, the more the amount of oxygen injected into the layer below the insulator 282. By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed.
  • the insulator 282 may also be formed in a two-layer laminate structure. At this time, for example, the lower layer of the insulator 282 is formed without applying RF power to the substrate, and the upper layer of the insulator 282 is formed by applying RF power to the substrate.
  • the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage it can cause to the substrate.
  • a heat treatment may be performed before the formation of the insulator 282.
  • the heat treatment may be performed under reduced pressure, and the insulator 282 may be continuously formed without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 can be removed, and the moisture concentration and hydrogen concentration in the insulator 280 can be further reduced.
  • the temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is 250°C.
  • the insulator 283 is formed on the insulator 282.
  • the insulator 283 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulator 283 is preferably formed by a sputtering method.
  • a silicon nitride film is formed as the insulator 283 by a sputtering method.
  • the insulators 282 and 283 in succession without exposing them to the atmospheric environment. Depositing them without exposing them to the atmosphere can prevent impurities or moisture from the atmospheric environment from adhering to the insulators 282 and 283, and can keep the interface or the vicinity of the interface between the insulators 282 and 283 clean.
  • a heat treatment may be performed.
  • the temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.
  • an opening reaching conductor 242a and an opening reaching conductor 242b are formed in insulators 275, 280, 282, and 283 (see Figures 1A to 1D).
  • the openings may be formed using a lithography method. Note that, although the shape of the opening is circular in top view in Figure 1A, this is not limited to this. For example, the opening may be approximately circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in top view.
  • an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241a in the opening that reaches the conductor 242a, and the insulator 241b in the opening that reaches the conductor 242b (see Figures 1A to 1D).
  • the insulating film that will become the insulator 241 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to use an insulating film that has a function of suppressing oxygen permeation as the insulating film that will become the insulator 241. For example, it is preferable to form a film of aluminum oxide using the ALD method, and then form a film of silicon nitride thereon using the PEALD method. Silicon nitride is preferable because it has high blocking properties against hydrogen.
  • the anisotropic etching of the insulating film that will become the insulator 241 can be performed, for example, by dry etching.
  • By providing the insulator 241 on the sidewall of the opening it is possible to suppress the transmission of oxygen from the outside and prevent the oxidation of the conductors 240a and 240b that will be formed next. It is also possible to prevent impurities such as water and hydrogen contained in the insulator 280 from diffusing into the conductors 240a and 240b.
  • the conductive film that will become conductor 240a and conductor 240b is desirably a laminated structure that includes a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen.
  • a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen.
  • it can be a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc.
  • the conductive film that will become conductor 240a and conductor 240b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc.
  • a CMP process is performed to remove a portion of the conductive film that will become conductor 240a and conductor 240b, exposing the upper surface of insulator 283.
  • the conductive film remains only in the openings, forming conductors 240a and 240b with flat upper surfaces (see Figures 1A to 1D). Note that the CMP process may remove a portion of the upper surface of insulator 283.
  • conductor 240a in contact with conductor 242a, conductor 240a, which functions as one of the source and drain of transistor 200, can be electrically connected to wiring.
  • conductor 240b in contact with conductor 242b, conductor 240b, which functions as the other of the source and drain of transistor 200, can be electrically connected to wiring.
  • a conductive film that functions as wiring or a conductive film that functions as a plug can be formed on the conductor 240a and the conductor 240b.
  • the semiconductor device shown in Figure 1 can be manufactured.
  • the carrier concentration of a channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably less than 1 ⁇ 10 17 cm ⁇ 3 , more preferably less than 1 ⁇ 10 16 cm ⁇ 3 , further preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and further preferably less than 1 ⁇ 10 10 cm ⁇ 3 and 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more.
  • the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states.
  • a semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor an oxide semiconductor with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Furthermore, charges captured in the trap states of the oxide semiconductor may take a long time to disappear and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.
  • impurities in an oxide semiconductor refer to, for example, anything other than the main component that constitutes the oxide semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be considered an impurity.
  • an OS transistor may form a defect in which hydrogen enters an oxygen vacancy in an oxide semiconductor (hereinafter, this may be referred to as VOH ), and generate electrons that serve as carriers.
  • VOH hydrogen enters an oxygen vacancy in an oxide semiconductor
  • the donor concentration in the channel formation region may increase.
  • the threshold voltage may vary.
  • the transistor when an oxygen vacancy is present in a channel formation region in an oxide semiconductor, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and a current flows through the transistor even when no voltage is applied to a gate electrode). Therefore, it is preferable that impurities, oxygen vacancies, and VOH be reduced as much as possible in the channel formation region in an oxide semiconductor.
  • the band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more.
  • the off-current (also referred to as Ioff) of the transistor can be reduced.
  • OS transistors use oxide semiconductors, which are semiconductor materials with a wide band gap, and therefore the short channel effect can be suppressed. In other words, OS transistors are transistors that do not have the short channel effect or have an extremely small short channel effect.
  • the short channel effect is a degradation of electrical characteristics that becomes evident as transistors are miniaturized (reduced channel length).
  • Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes written as S value), and an increase in leakage current.
  • the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.
  • Characteristic length is widely used as an index of resistance to short channel effects.
  • Characteristic length is an index of how easily the potential of the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to short channel effects.
  • OS transistors are accumulation-type transistors, while Si transistors are inversion-type transistors. Therefore, compared to Si transistors, OS transistors have smaller characteristic lengths between the source region and the channel-forming region, and between the drain region and the channel-forming region. Therefore, OS transistors are more resistant to the short-channel effect than Si transistors. In other words, when it is desired to manufacture a transistor with a short channel length, OS transistors are more suitable than Si transistors.
  • the OS transistor can also be regarded as having an n + / n ⁇ /n + accumulation-type junction-less transistor structure or an n + /n ⁇ /n + accumulation-type non-junction transistor structure in which the channel formation region is an n ⁇ type region and the source region and drain region are n + type regions.
  • the OS transistor can have good electrical characteristics even when the semiconductor device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and 1 nm or more, 3 nm or more, or 5 nm or more.
  • the OS transistor can be suitably used as a transistor having a shorter channel length than that of a Si transistor.
  • the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region when the transistor is operating, and refers to the width of the bottom surface of the gate electrode in a plan view of the transistor.
  • the cutoff frequency of the transistor can be improved.
  • the cutoff frequency of the transistor can be set to, for example, 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more in a room temperature environment.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the excellent advantages of having a smaller off-state current and being able to fabricate transistors with a short channel length.
  • a configuration example of a memory device using a memory cell having a transistor described in the above embodiment is described.
  • a configuration example of a memory device is described in which a layer having stacked memory cells and a layer having a functional circuit having a function of amplifying and outputting a data potential held in the memory cell are provided.
  • FIG. 22 illustrates a block diagram of a storage device of one embodiment of the present invention.
  • the memory device 300 shown in FIG. 22 has a drive circuit 21 and a memory array 20.
  • the memory array 20 has a plurality of memory cells 10 and a functional layer 50 having a plurality of functional circuits 51.
  • FIG. 22 shows an example in which the memory array 20 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more).
  • FIG. 22 also shows an example in which a functional circuit 51 is provided for each wiring BL that functions as a bit line, and an example in which the functional layer 50 has n functional circuits 51 provided corresponding to the n wirings BL.
  • the memory cell 10 in the first row and first column is indicated as memory cell 10[1,1] and the memory cell 10 in the mth row and nth column is indicated as memory cell 10[m,n].
  • an arbitrary row may be indicated as row i.
  • An arbitrary column may be indicated as column j.
  • i is an integer between 1 and m
  • j is an integer between 1 and n.
  • the memory cell 10 in the ith row and jth column is indicated as memory cell 10[i,j].
  • i+ ⁇ ⁇ is a positive or negative integer
  • the memory array 20 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction.
  • the first wiring WL (first row) is indicated as wiring WL[1]
  • the mth wiring WL (mth row) is indicated as wiring WL[m].
  • the first wiring PL (first row) is indicated as wiring PL[1]
  • the mth wiring PL (mth row) is indicated as wiring PL[m].
  • the first wiring BL (first column) is indicated as wiring BL[1]
  • the nth wiring BL (nth column) is indicated as wiring BL[n].
  • the multiple memory cells 10 in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]).
  • the multiple memory cells 10 in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).
  • the memory array 20 can be a DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory).
  • DOSRAM is a RAM having 1T (transistor) 1C (capacitor) type memory cells, and the access transistor is an OS transistor.
  • the current flowing between the source and drain of an OS transistor in the off state, that is, the leakage current, is extremely small.
  • DOSRAM can hold a charge corresponding to the data held in the capacitance element (capacitor) for a long time. Therefore, DOSRAM can reduce the frequency of refresh operations compared to DRAM composed of transistors (Si transistors) having silicon in the channel formation region. As a result, it is possible to reduce power consumption.
  • the frequency characteristics of OS transistors are high, reading and writing of the storage device can be performed at high speed. This makes it possible to provide a storage device with high operating speed.
  • multiple memory arrays 20[1] to 20[m] can be stacked.
  • the memory arrays 20[1] to 20[m] of the memory array 20 can be arranged in the vertical direction of the substrate surface on which the drive circuit 21 is provided, thereby improving the memory density of the memory cells 10.
  • the wiring BL functions as a bit line for writing and reading data.
  • the wiring WL functions as a word line for controlling the on or off (conductive or non-conductive state) of an access transistor that functions as a switch.
  • the wiring PL functions as a constant potential line connected to a capacitance element. Note that a wiring CL (not shown) can be separately provided as a wiring having a function of transmitting a backgate potential to the backgate of the OS transistor that is the access transistor.
  • the wiring PL may also be configured to have a function of transmitting a backgate potential.
  • the memory cells 10 in each of the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 via wiring BL.
  • the wiring BL can be arranged in a vertical direction to the substrate surface on which the driver circuit 21 is provided.
  • the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened.
  • the signal propagation distance between the two circuits connected to the bit line can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thereby reducing power consumption and signal delay.
  • the memory device can be operated even if the capacitance of the capacitive element in the memory cell 10 is reduced.
  • the functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 of the driver circuit 21 via the wiring GBL (not shown) described later.
  • This configuration makes it possible to amplify the slight potential difference of the wiring BL when reading data.
  • the wiring GBL can be arranged in the vertical direction of the substrate surface on which the driver circuit 21 is provided, just like the wiring BL.
  • the wiring BL is provided in contact with the semiconductor layer of the transistor included in the memory cell 10.
  • the wiring BL is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the memory cell 10.
  • the wiring BL is provided in contact with a conductor that is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the memory cell 10.
  • the wiring BL can be said to be a wiring for electrically connecting one of the source or drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51 in the vertical direction.
  • the memory array 20 can be stacked on the drive circuit 21. By stacking the drive circuit 21 and the memory array 20, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. This reduces the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20, and reduces power consumption and signal delay. In addition, the storage device 300 can be made smaller.
  • the functional circuit 51 uses OS transistors similar to the transistors in the memory cells 10 of the DOSRAM, and can be freely arranged on circuits using Si transistors similar to the memory arrays 20[1] to 20[m], making integration easy. By configuring the functional circuit 51 to amplify signals, the circuits in the subsequent stage, such as the sense amplifier 46, can be made smaller, and the memory device 300 can be made smaller.
  • the drive circuit 21 has a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31.
  • the peripheral circuit 31 has a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.
  • each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or other signals may be added.
  • Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signals PON1 and PON2 are signals for power gating control. Signals PON1 and PON2 may be generated by control circuit 32.
  • the control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300.
  • the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the voltage generation circuit 33 has the function of generating a negative voltage.
  • the signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.
  • the peripheral circuit 41 is a circuit for writing and reading data to the memory cells 10.
  • the peripheral circuit 41 is also a circuit for outputting various signals for controlling the functional circuit 51.
  • the peripheral circuit 41 has a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.
  • the row decoder 42 and column decoder 44 have the function of decoding the signal ADDR.
  • the row decoder 42 is a circuit for specifying the row to be accessed
  • the column decoder 44 is a circuit for specifying the column to be accessed.
  • the row driver 43 has the function of selecting the wiring WL specified by the row decoder 42.
  • the column driver 45 has the function of writing data to the memory cell 10, reading data from the memory cell 10, and retaining the read data.
  • the input circuit 47 has a function of holding a signal WDA.
  • the data held by the input circuit 47 is output to the column driver 45.
  • the output data of the input circuit 47 is the data (Din) to be written to the memory cell 10.
  • the data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48.
  • the output circuit 48 has a function of holding Dout.
  • the output circuit 48 has a function of outputting Dout to the outside of the memory device 300.
  • the data output from the output circuit 48 is the signal RDA.
  • PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31.
  • PSW23 has a function of controlling the supply of VHM to the row driver 43.
  • the high power supply voltage of the memory device 300 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD.
  • the on/off of PSW22 is controlled by signal PON1, and the on/off of PSW23 is controlled by signal PON2.
  • the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it is also possible to have multiple power domains. In this case, a power switch can be provided for each power supply domain.
  • the memory array 20 having memory arrays 20[1] to 20[m] (m is an integer of 2 or more) and a functional layer 50 can be provided by stacking multiple layers of memory arrays 20 on a driving circuit 21. By stacking multiple layers of memory arrays 20, the memory density of the memory cells 10 can be increased.
  • the memory array 20 provided in the first layer is shown as memory array 20[1]
  • the memory array 20 provided in the second layer is shown as memory array 20[2]
  • the memory array 20 provided in the fifth layer is shown as memory array 20[5].
  • Also shown in FIG. 23A are wiring WL, wiring PL, and wiring CL extending in the X direction, and wiring BL extending in the Z direction (the direction perpendicular to the substrate surface on which the drive circuit is provided). Note that to make the drawing easier to understand, some of the wiring WL and wiring PL of each memory array 20 have been omitted.
  • FIG. 23B is a schematic diagram illustrating an example of the configuration of the functional circuit 51 connected to the wiring BL shown in FIG. 23A, and the memory cells 10 in the memory arrays 20[1] to 20[5] connected to the wiring BL.
  • FIG. 23B also illustrates the wiring GBL provided between the functional circuit 51 and the driver circuit 21. Note that a configuration in which multiple memory cells (memory cells 10) are electrically connected to one wiring BL is also referred to as a "memory string.” Note that in the drawings, the wiring GBL may be illustrated with a thick line to improve visibility.
  • FIG. 23B illustrates an example of a circuit configuration of a memory cell 10 connected to wiring BL.
  • the memory cell 10 has a transistor 11 and a capacitor 12.
  • the transistor 11, the capacitor 12, and each wiring may also be referred to as wiring BL[1] and wiring WL[1], for example.
  • the transistor 11 corresponds to the transistor 200 described in embodiment 1.
  • one of the source and drain of transistor 11 is connected to wiring BL.
  • the other of the source and drain of transistor 11 is connected to one electrode of capacitance element 12.
  • the other electrode of capacitance element 12 is connected to wiring PL.
  • the gate of transistor 11 is connected to wiring WL.
  • the backgate of transistor 11 is connected to wiring CL.
  • the wiring PL is a wiring that provides a constant potential to maintain the potential of the capacitance element 12.
  • the wiring CL is a wiring that provides a constant potential to control the threshold voltage of the transistor 11.
  • the wiring PL and the wiring CL may be at the same potential. In this case, by connecting the two wirings, the number of wirings connected to the memory cell 10 can be reduced.
  • FIG. 24A shows a schematic diagram of a memory device 300 in which a functional circuit 51 and memory arrays 20[1] to 20[m] are repeated as a unit 70. Note that while FIG. 24A shows one wiring GBL, the wiring GBL may be provided as appropriate according to the number of functional circuits 51 provided in the functional layer 50.
  • the wiring GBL is provided in contact with the semiconductor layer of the transistor in the functional circuit 51.
  • the wiring GBL is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor in the functional circuit 51.
  • the wiring GBL is provided in contact with a conductor that is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor in the functional circuit 51.
  • the wiring GBL can be said to be a wiring for electrically connecting one of the source or drain of the transistor in the functional circuit 51 in the functional layer 50 to the driver circuit 21 in the vertical direction.
  • the repeating unit 70 including the functional circuit 51 and the memory arrays 20[1] to 20[m] may be further stacked.
  • the memory device 300A of one embodiment of the present invention can have repeating units 70[1] to 70[p] (p is an integer of 2 or more) as illustrated in FIG. 24B.
  • the wiring GBL is connected to the functional layer 50 included in the repeating unit 70.
  • the wiring GBL may be provided as appropriate depending on the number of functional circuits 51.
  • OS transistors are stacked, and wiring that functions as bit lines is arranged in a vertical direction to the substrate surface on which the driver circuit 21 is provided.
  • the wiring that functions as bit lines extending from the memory array 20 in a vertical direction to the substrate surface, the length of the wiring between the memory array 20 and the driver circuit 21 can be shortened. This allows the parasitic capacitance of the bit lines to be significantly reduced.
  • the layer in which the memory array 20 is provided includes a functional layer 50 having a functional circuit 51 that has a function of amplifying and outputting the data potential held in the memory cell 10.
  • the slight potential difference of the wiring BL that functions as a bit line when reading data can be amplified to drive the sense amplifier 46 of the drive circuit 21. Since the circuits such as the sense amplifier can be miniaturized, the memory device 300 can be miniaturized. In addition, the memory device 300 can be operated even if the capacitance of the capacitive element 12 in the memory cell 10 is reduced.
  • the semiconductor device according to the present invention can also be used for a single-layer memory device having only memory array 20[1].
  • FIG. 25 a configuration example of the functional circuit 51 described in FIG. 22 to FIG. 24 and a configuration example of the sense amplifier 46 included in the memory array 20 and the driver circuit 21 will be described.
  • the driver circuit 21 connected to wirings GBL (wirings GBL_A, GBL_B) connected to functional circuits 51 (functional circuits 51_A, 51_B) connected to memory cells 10 (memory cells 10_A, 10_B) connected to different wirings BL (wirings BL_A, BL_B) is illustrated.
  • a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write/read circuit 73 are illustrated.
  • Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are illustrated as functional circuits 51_A and 51_B.
  • the transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b illustrated in FIG. 25 are OS transistors, similar to the transistor 11 included in the memory cell 10.
  • the functional layer 50 including the functional circuit 51 can be stacked on the driver circuit 21, similar to the memory arrays 20[1] to 20[m].
  • Wiring BL_A is connected to the gate of transistor 52_a, and wiring BL_B is connected to the gate of transistor 52_b.
  • One of the sources or drains of transistors 53_a and 54_a is connected to wiring GBL_A.
  • One of the sources or drains of transistors 53_b and 54_b is connected to wiring GBL_B.
  • Wirings GBL_A and GBL_B are provided vertically like wirings BL_A and BL_B, and are connected to transistors in driver circuit 21. As shown in FIG. 25, a selection signal MUX, a control signal WE, or a control signal RE is applied to the gates of transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b, respectively.
  • the transistors 81_1 to 81_6 and 82_1 to 82_4 constituting the sense amplifier 46, precharge circuit 71_A, and precharge circuit 71_B shown in FIG. 25 are composed of Si transistors.
  • the switches 83_A to 83_D constituting the switch circuit 72_A and switch circuit 72_B can also be composed of Si transistors.
  • One of the sources or drains of the transistors 53_a, 53_b, 54_a, and 54_b is connected to the transistors or switches constituting the precharge circuit 71_A, precharge circuit 71_B, sense amplifier 46, and switch circuit 72_A.
  • the precharge circuit 71_A has n-channel transistors 81_1 to 81_3.
  • the precharge circuit 71_A is a circuit for precharging the wiring BL_A and the wiring BL_B to an intermediate potential VPC that corresponds to a potential VDD/2 between a high power supply potential (VDD) and a low power supply potential (VSS) in response to a precharge signal provided to a precharge line PCL1.
  • VDD high power supply potential
  • VSS low power supply potential
  • the precharge circuit 71_B has n-channel transistors 81_4 to 81_6.
  • the precharge circuit 71_B is a circuit for precharging the wiring GBL_A and the wiring GBL_B to an intermediate potential VPC that corresponds to a potential VDD/2 between VDD and VSS in response to a precharge signal provided to the precharge line PCL2.
  • the sense amplifier 46 has p-channel transistors 82_1 and 82_2 and n-channel transistors 82_3 and 82_4 connected to the wiring VHH or wiring VLL.
  • the wiring VHH or wiring VLL is a wiring that has a function of providing VDD or VSS.
  • the transistors 82_1 to 82_4 are transistors that form an inverter loop.
  • the potentials of the precharged wirings BL_A and BL_B change by selecting memory cells 10_A and 10_B, and the potentials of the wirings GBL_A and GBL_B are set to VDD or VSS in response to the change.
  • the potentials of the wirings GBL_A and GBL_B can be output to the outside via the switches 83_C and 83_D, and the write/read circuit 73.
  • the wirings BL_A and BL_B, and the wirings GBL_A and GBL_B correspond to bit line pairs.
  • the write/read circuit 73 controls the writing of data signals according to the signal EN_data.
  • the switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wiring GBL_A and wiring GBL_B.
  • the switch circuit 72_A is switched on or off under the control of the switching signal CSEL1.
  • the switches 83_A and 83_B are n-channel transistors, the switching signal CSEL1 is on at a high level and off at a low level.
  • the switch circuit 72_B is a circuit for controlling the conduction state between the write/read circuit 73 and the bit line pair connected to the sense amplifier 46.
  • the switch circuit 72_B is switched on or off under the control of the switching signal CSEL2.
  • the switches 83_C and 83_D may operate in the same manner as the switches 83_A and 83_B.
  • the memory device 300 can be configured to connect the memory cell 10, the functional circuit 51, and the sense amplifier 46 via wiring BL and wiring GBL that are provided in the vertical direction, which is the shortest distance.
  • the number of functional layers 50 having transistors that constitute the functional circuit 51 increases, the load on the wiring BL is reduced, which shortens the write time and makes it easier to read data.
  • each transistor in the functional circuits 51_A and 51_B is controlled in response to control signals WE, RE, and a selection signal MUX.
  • Each transistor can output the potential of the wiring BL to the driver circuit 21 via the wiring GBL in response to the control signal and selection signal.
  • the functional circuits 51_A and 51_B can function as sense amplifiers made up of OS transistors. With this configuration, a slight potential difference in the wiring BL can be amplified during reading to drive the sense amplifier 46 using Si transistors.
  • Example of memory cell configuration An example of the configuration of a memory cell 10 used in the memory device will be described with reference to FIG. 26A.
  • the X direction is parallel to the channel length direction of the illustrated transistor
  • the Y direction is perpendicular to the X direction
  • the Z direction is perpendicular to the X and Y directions.
  • the memory cell 10 includes a transistor 11 and a capacitor 12.
  • An insulator 285 is provided on the transistor 11, and an insulator 284 is provided on the insulator 285.
  • the insulators 285 and 284 may be made of an insulator that can be used for the insulator 216.
  • the transistor 11 has a similar structure to the transistor 200 described in the previous embodiment, and the same components are denoted by the same reference numerals. For details of the transistor 200, the previous embodiment can be referred to.
  • a conductor 240b is provided in contact with one of the source and drain (conductor 242b) of the transistor 11.
  • the conductor 240b is provided extending in the Z direction and functions as a wiring BL.
  • the capacitance element 12 has a conductor 153 on the conductor 242a, an insulator 154 on the conductor 153, and a conductor 160 (conductor 160a and conductor 160b) on the insulator 154.
  • At least a portion of conductor 153, insulator 154, and conductor 160 are disposed inside openings provided in insulators 275, 280, 282, 283, and 285, respectively.
  • the ends of conductors 153, 154, and 160 are located at least on insulator 282, and preferably on insulator 285.
  • Insulator 154 is disposed so as to cover the end of conductor 153. This allows electrical insulation between conductor 153 and conductor 160.
  • insulators 275, 280, 282, 283, and 285 are (i.e., the thicker one or more of insulators 275, 280, 282, 283, and 285 are), the larger the capacitance of capacitive element 12 can be. Increasing the capacitance per unit area of capacitive element 12 allows for miniaturization or high integration of the memory device.
  • the conductor 153 has a region that functions as one electrode (lower electrode) of the capacitance element 12.
  • the insulator 154 has a region that functions as a dielectric of the capacitance element 12.
  • the conductor 160 has a region that functions as the other electrode (upper electrode) of the capacitance element 12.
  • the upper part of the conductor 260 can be extended to function as the wiring PL shown in Figures 23A and 23B.
  • the capacitance element 12 constitutes a MIM (Metal-Insulator-Metal) capacitance.
  • the conductor 242a overlapping the oxide 230 functions as an electrode electrically connected to the conductor 153 of the capacitor 12.
  • the conductor 153 and the conductor 160 of the capacitor 12 can be formed using various conductors that can be used for the conductor 205 or the conductor 260, respectively.
  • the conductor 153 and the conductor 160 are preferably formed using a film formation method with good coating properties, such as the ALD method or the CVD method.
  • the conductor 153 can be made of titanium nitride or tantalum nitride formed using the ALD method or the CVD method.
  • the upper surface of conductor 242a contacts the lower surface of conductor 153.
  • the contact resistance between conductor 153 and conductor 242a can be reduced.
  • the conductor 160a may be made of titanium nitride formed using the ALD method or the CVD method, and the conductor 160b may be made of tungsten formed using the CVD method. If the adhesion of tungsten to the insulator 154 is sufficiently high, the conductor 160 may be a single layer structure of tungsten formed using the CVD method.
  • the insulator 154 of the capacitance element 12 is preferably made of a high-k material (a material with a high relative dielectric constant).
  • the insulator 154 is preferably formed using a film formation method with good coating properties, such as the ALD method or the CVD method.
  • high-dielectric constant (high-k) insulators examples include oxides, oxynitrides, oxynitrides, and nitrides that contain one or more metal elements selected from aluminum, hafnium, zirconium, and gallium. Silicon may also be contained in the oxides, oxynitrides, oxynitrides, or nitrides. Insulators made of the above materials may also be stacked.
  • examples of insulators made of high dielectric constant (high-k) materials include aluminum oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, oxides having silicon and zirconium, oxynitrides having silicon and zirconium, oxides having hafnium and zirconium, and oxynitrides having hafnium and zirconium.
  • high-k materials include aluminum oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, oxides having silicon and zirconium, oxynitrides having hafnium and zirconium.
  • insulators made of the above materials in a laminated structure, and it is preferable to use a laminated structure of a high dielectric constant (high-k) material and a material having a higher dielectric strength than the high dielectric constant (high-k) material.
  • a laminated structure of a high dielectric constant (high-k) material and a material having a higher dielectric strength than the high dielectric constant (high-k) material for example, an insulator laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used as the insulator 154.
  • an insulator laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used.
  • an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used.
  • an insulator with a relatively high dielectric strength such as aluminum oxide in a laminated structure the dielectric strength is improved and electrostatic breakdown of the capacitance element 12 can be suppressed.
  • a material that can have ferroelectricity may be used as the insulator 154.
  • materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (X is a real number greater than 0).
  • materials that can have ferroelectricity include a material in which an element J1 (here, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide.
  • the ratio of the number of atoms of hafnium atoms to the number of atoms of the element J1 can be set appropriately, and for example, the ratio of the number of atoms of hafnium atoms to the number of atoms of the element J1 may be set to 1:1 or close to 1:1.
  • materials that can have ferroelectricity include a material in which an element J2 (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide.
  • the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 may be set to 1: 1 or close to 1.
  • piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiO x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may be used.
  • examples of materials that can have ferroelectricity include metal nitrides having element M1, element M2, and nitrogen.
  • element M1 is one or more selected from aluminum, gallium, indium, etc.
  • element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. It should be noted that the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Also, metal oxides having element M1 and nitrogen may have ferroelectricity even if they do not contain element M2.
  • examples of materials that can have ferroelectricity include materials in which element M3 is added to the above metal nitride.
  • element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.
  • the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.
  • examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO 2 N and BaTaO 2 N, and GaFeO 3 with a ⁇ -alumina structure.
  • metal oxides and metal nitrides are given as examples, but the present invention is not limited to these.
  • metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, etc. may also be used.
  • a material that can have ferroelectricity for example, a mixture or compound made of multiple materials selected from the materials listed above can be used.
  • the insulator 154 can have a layered structure made of multiple materials selected from the materials listed above.
  • the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials that can have ferroelectricity.
  • a ferroelectric is an insulator that is polarized when an electric field is applied from the outside, and has the property that the polarization remains even when the electric field is made zero. For this reason, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric.
  • a nonvolatile memory element that uses a ferroelectric capacitor is sometimes called a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, etc.
  • a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance element 12, the memory device shown in this embodiment functions as a ferroelectric memory.
  • the insulators 275, 280, 282, 283, and 285 function as barrier insulators, it is preferable to set the film thickness according to the barrier properties required for the semiconductor device.
  • the film thickness of the conductor 260 that functions as a gate electrode is determined according to the film thickness of the insulator 280, it is preferable to set the film thickness of the insulator 280 according to the film thickness of the conductor 260 required for the semiconductor device.
  • the film thickness of the insulator 285 may be set in the range of 50 nm to 250 nm, and the depth of the opening may be set to approximately 150 nm to 350 nm.
  • the capacitance element 12 By forming the capacitance element 12 in such a range, it is possible to provide the capacitance element 12 with sufficient capacitance, and to prevent the height of one layer from becoming excessively high in a semiconductor device in which multiple memory cell layers are stacked.
  • a configuration may be adopted in which the capacitance of the capacitance element provided in each memory cell is different in each of the multiple memory cell layers. In this configuration, for example, the film thickness of the insulator 285 provided in each memory cell layer may be different.
  • the sidewall of the opening may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may be tapered.
  • the sidewall tapered By making the sidewall tapered, the coverage of the conductor 153 or the like provided in the opening of the insulator 285 or the like is improved, and defects such as voids can be reduced.
  • the conductor 242b provided on the oxide 230 functions as wiring that electrically connects to the conductor 240b.
  • the upper surface and side end of the conductor 242b are electrically connected to the conductor 240b extending in the Z direction.
  • the upper surface and side end of the conductor 242b are in contact with the conductor 240b.
  • the conductor 240b By directly contacting the conductor 240b with at least one of the upper surface and side end of the conductor 242b, there is no need to provide a separate electrode for connection, and the area occupied by the memory array can be reduced. In addition, the integration density of memory cells is improved, and the memory capacity of the storage device can be increased. Note that it is preferable that the conductor 240b contacts a part of the upper surface and the side end of the conductor 242b. By contacting multiple surfaces of the conductor 242b with the conductor 240b, the contact resistance between the conductor 240b and the conductor 242b can be reduced.
  • Conductor 240b is provided in openings formed in insulators 216, 221, 222, 275, 280, 282, 283, 285, and 284.
  • the insulator 241b is provided in contact with the side surface of the conductor 240b. Specifically, the insulator 241b is provided in contact with the inner walls of the openings of the insulators 216, 221, 222, 275, 280, 282, 283, 285, and 284. The insulator 241 is also formed on the side surface of the oxide 230 that is formed to protrude into the opening. Here, at least a portion of the conductor 242b is exposed from the insulator 241b and is in contact with the conductor 240b. In other words, the conductor 240b is provided so as to fill the inside of the opening via the insulator 241b.
  • the top of the insulator 241b formed below the conductor 242b is preferably located below the top surface of the conductor 242b.
  • This configuration allows the conductor 240b to contact at least a portion of the side end of the conductor 242b.
  • the insulator 241b formed below the conductor 242b preferably has an area that contacts the side of the oxide 230. This configuration can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide 230 through the conductor 240b.
  • the sidewall of the opening may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may be tapered. By making the sidewall tapered, the coverage of the insulator 241b and the like provided in the opening is improved.
  • the conductor 153 of the capacitance element 12 is in contact with the conductor 242a of the transistor 11, but the present invention is not limited to this.
  • a configuration may be used in which a conductor 240a is provided in the transistor 11 and the capacitance element 12 is provided on top of that.
  • an insulator 286 can be provided on the insulator 283, an insulator 287 can be provided on the insulator 286, and an insulator 288 can be provided on the insulator 287.
  • the insulators 286, 287, and 288 may be made of an insulator that can be used for the insulator 284.
  • Conductors 246a and 246b are provided so as to be embedded in the insulator 286.
  • Conductors 246a and 246b function as wirings or electrodes, and may be made of a conductor that can be used for the conductor 205.
  • a capacitor 12 is provided so as to be embedded in the insulator 287 and the insulator 288. The capacitor 12 shown in FIG.
  • FIG. 26B has a structure similar to that of FIG. 26A. Also, the transistor 11 shown in FIG. 26B has a conductor 240a, a conductor 240b, an insulator 241a, and an insulator 241b embedded in an insulator 280, similar to the transistor 200 shown in FIG. 1B, etc.
  • conductor 240a contacts conductor 242a
  • conductor 246a contacts conductor 240a
  • conductor 153 contacts conductor 246a. Therefore, conductor 153, which is the lower electrode of capacitance element 12, is electrically connected to conductor 242a, which is one of the source and drain of transistor 11, via conductor 246a and conductor 240a.
  • conductor 240b contacts conductor 242b
  • conductor 246b contacts conductor 240b
  • conductor 246b can be routed in the same layer to function as wiring BL.
  • the memory cells 10 shown in FIG. 26B are arranged in a matrix in the same layer to form a memory array. Furthermore, without being limited to this, they may be configured to extend in the Z direction, similar to conductor 240b shown in FIG. 26A.
  • the conductor 246a and the conductor 246b are configured to be formed in the same layer, but the present invention is not limited to this.
  • the conductor 246a may be configured to be provided in a layer above the conductor 246b.
  • an insulator 289 can be provided on the insulator 286, and an insulator 290 can be provided on the insulator 289.
  • the insulator 289 can be an insulator that can be used for the insulator 283, and the insulator 290 can be an insulator that can be used for the insulator 284.
  • a conductor 246a is provided so as to be embedded in the insulator 290.
  • the conductor 246a can be arranged overlapping the transistor 11 without interfering with the conductor 246b. Therefore, the capacitor 12 provided on the conductor 246a can be arranged overlapping the transistor 11.
  • the insulator 289 functions as an etching stopper when forming the conductor 246a. With this configuration, even if a part of the conductor 246a overlaps with the conductor 246b, the part of the conductor 246a can be prevented from contacting the conductor 246b.
  • the capacitance element 12 is configured to be provided on the transistor 11, but the present invention is not limited to this.
  • the capacitance element 12 may be configured to be provided below the transistor 11.
  • an insulator 215 can be provided under the insulator 216 as in FIG. 1B
  • an insulator 291 can be provided under the insulator 215, an insulator 292 can be provided under the insulator 291, and an insulator 293 can be provided under the insulator 292.
  • the insulators 291, 292, and 293 may be made of an insulator that can be used for the insulator 284.
  • a conductor 294 is provided so as to be embedded in the insulator 293.
  • the conductor 294 may be made of a conductor that functions as a wiring or an electrode and can be used for the conductor 205.
  • a capacitor 12 is provided so as to be embedded in the insulators 291 and 292.
  • the capacitor 12 shown in FIG. 27B has a structure similar to that of FIG. 26A.
  • a conductor 206 is provided so as to be embedded in the insulators 215 and 216.
  • the conductor 206 can be formed in the same process as the conductor 205 by using a dual damascene method.
  • Conductor 240c and insulator 241c are provided so as to be embedded in insulator 221, insulator 222, insulator 275, insulator 280, insulator 282, and insulator 283.
  • Conductor 240c can be formed in the same process as conductor 240a and conductor 240b, and insulator 241c can be formed in the same process as insulator 241a and insulator 241b.
  • conductor 240a contacts conductor 242a
  • conductor 246a contacts conductor 240a
  • conductor 240c contacts conductor 246a
  • conductor 206 contacts conductor 240c
  • conductor 160 contacts conductor 206.
  • conductor 160 which is the upper electrode of capacitance element 12
  • conductor 242a which is one of the source and drain of transistor 11, via conductor 206, conductor 240c, conductor 246a, and conductor 240a.
  • the conductor 294 contacts the conductor 153.
  • the conductor 153 can function as the wiring PL.
  • the capacitor 12 can be arranged overlapping under the transistor 11.
  • the memory device 300 has a driver circuit 21, which is a layer having transistors 310 and the like, a functional layer 50 on the driver circuit 21, which is a layer having transistors 52, 53, 54, 55 and the like, and memory arrays 20[1] to 20[m] on the functional layer 50.
  • the transistor 52 corresponds to the transistors 52_a and 52_b described above
  • the transistor 53 corresponds to the transistors 53_a and 53_b described above
  • the transistor 54 corresponds to the transistors 54_a and 54_b described above
  • the transistor 55 corresponds to the transistors 55_a and 55_b described above.
  • a transistor 310 included in the driver circuit 21 is illustrated.
  • the transistor 310 is provided on a substrate 311, and has a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 including a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region.
  • the transistor 310 may be either a p-channel transistor or an n-channel transistor.
  • a single crystal silicon substrate can be used as the substrate 311.
  • the semiconductor region 313 (part of the substrate 311) in which the channel is formed has a convex shape.
  • the side and top surface of the semiconductor region 313 are covered with a conductor 316 via an insulator 315.
  • the conductor 316 may be made of a material that adjusts the work function.
  • Such a transistor 310 is also called a Fin-type transistor because it uses the convex portion of the semiconductor substrate.
  • an insulator that contacts the top of the convex portion and functions as a mask for forming the convex portion may be provided.
  • a convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may be formed by processing an SOI (Silicon on Insulator) substrate.
  • transistor 310 shown in FIG. 28 is just an example, and the structure is not limited to this, and an appropriate transistor can be used depending on the circuit configuration or driving method.
  • a wiring layer having an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers may be provided depending on the design. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film.
  • Conductors 328 and the like are embedded in the insulators 320 and 322.
  • Conductors 330 and the like are embedded in the insulators 324 and 326.
  • Conductors 328 and 330 function as contact plugs or wiring.
  • the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath.
  • the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.
  • CMP chemical mechanical polishing
  • FIG. 28 also illustrates transistors 52, 53, and 55 in the functional layer 50.
  • the transistors 52, 53, and 55 have the same configuration as the transistor 11 in the memory cell 10.
  • the sources and drains of the transistors 52, 53, and 55 are connected in series.
  • An insulator 208 is provided on the transistors 52, 53, and 55, and a conductor 207 is provided in an opening formed in the insulator 208. Furthermore, an insulator 210 is provided on the insulator 208, and a conductor 209 is provided in an opening formed in the insulator 210. Furthermore, an insulator 212 is provided on the insulator 210, and an insulator 214 is provided on the insulator 212. A part of the conductor 240b provided in the memory array 20[1] is embedded in the openings formed in the insulators 212 and 214.
  • the insulators 208 and 210 can be made of an insulator that can be used for the insulator 216. Furthermore, the insulator 212 can be made of an insulator that can be used for the insulator 283. Furthermore, the insulator 214 can be made of an insulator that can be used for the insulator 282.
  • the bottom surface of conductor 207 is in contact with the top surface of conductor 260 of transistor 52.
  • the top surface of conductor 207 is in contact with the bottom surface of conductor 209.
  • the top surface of conductor 209 is in contact with the bottom surface of conductor 240b provided in memory array 20[1]. With this configuration, conductor 240b, which corresponds to wiring BL, can be electrically connected to the gate of transistor 52.
  • Memory arrays 20[1] to 20[m] each include a plurality of memory cells 10.
  • the conductor 240b of each memory cell 10 is electrically connected to the conductor 240b in the upper layer and the conductor 240b in the lower layer.
  • the conductor 240b is shared between adjacent memory cells 10.
  • the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductor 240b.
  • the conductor 160 functioning as the upper electrode of the capacitance element 12 in the lower layer (e.g., the layer of the memory array 20[1]) and the conductor 205 functioning as the second gate electrode of the transistor 11 in the upper layer (e.g., the layer of the memory array 20[2]) can be formed in the same layer.
  • the conductor 160 of the capacitance element 12 in the lower layer and the conductor 205 of the transistor 11 in the upper layer can be formed so as to be embedded in an opening formed in the same insulator 216.
  • the conductor 205 of the transistor 11 in the upper layer can also be formed by processing the conductive film used for the conductor 160 of the capacitance element 12 in the lower layer. In this case, the conductor 205 of the transistor 11 in the upper layer has the same material as the conductor 160 of the capacitance element 12 in the lower layer.
  • multiple memory arrays 20[1] to 20[m] can be stacked.
  • the memory arrays 20[1] to 20[m] of the memory array 20 can be arranged in the vertical direction of the substrate surface on which the drive circuit 21 is provided, thereby improving the memory density of the memory cells 10.
  • the memory array 20 can also be manufactured using the same manufacturing process repeatedly in the vertical direction.
  • the storage device 300 can reduce the manufacturing cost of the memory array 20.
  • the chip 1200 shown in Figures 29A and 29B has multiple circuits (systems) implemented on it. This technology of integrating multiple circuits (systems) on a single chip is sometimes called a system on chip (SoC).
  • SoC system on chip
  • the chip 1200 has a CPU 1211, a GPU 1212, one or more analog computing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.
  • Bumps (not shown) are provided on the chip 1200, and as shown in FIG. 29B, they are connected to the first surface of the package substrate 1201.
  • a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201, and they are connected to the motherboard 1203.
  • the motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222.
  • a storage device such as a DRAM 1221 or a flash memory 1222.
  • the DOSRAM described in the previous embodiment may be used for the DRAM 1221. This allows the DRAM 1221 to consume less power, operate at a higher speed, and have a larger capacity.
  • the CPU 1211 preferably has multiple CPU cores.
  • the GPU 1212 preferably has multiple GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200.
  • the memory may be the DOSRAM described above.
  • the GPU 1212 is suitable for parallel calculation of a large amount of data, and may be used for image processing or multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the OS transistor described in the previous embodiment, it becomes possible to perform image processing or multiply-and-accumulate operations with low power consumption.
  • the wiring between the CPU 1211 and GPU 1212 can be shortened, and data can be transferred from the CPU 1211 to the GPU 1212, data can be transferred between the memories of the CPU 1211 and GPU 1212, and the results of calculations performed by the GPU 1212 can be transferred from the GPU 1212 to the CPU 1211 at high speed.
  • the analog calculation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit.
  • the analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.
  • the memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.
  • the interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include mice, keyboards, and game controllers. Examples of such interfaces that can be used include USB (Universal Serial Bus) and HDMI (registered trademark) (High-Definition Multimedia Interface).
  • USB Universal Serial Bus
  • HDMI registered trademark
  • the network circuit 1216 has a circuit for connecting to a network such as a LAN (Local Area Network). It may also have a circuit for network security.
  • a network such as a LAN (Local Area Network). It may also have a circuit for network security.
  • circuits can be formed in chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, there is no need to increase the manufacturing process, and chip 1200 can be manufactured at low cost.
  • the package substrate 1201 on which the chip 1200 having the GPU 1212 is provided, the motherboard 1203 on which the DRAM 1221 and the flash memory 1222 are provided, can be called a GPU module 1204.
  • the GPU module 1204 has the chip 1200 using SoC technology, so its size can be reduced. In addition, because it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles.
  • the product-sum calculation circuit using the GPU 1212 can execute techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), so the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.
  • DNN deep neural networks
  • CNN convolutional neural networks
  • RNN recurrent neural networks
  • DBM deep Boltzmann machines
  • DBN deep belief networks
  • Embodiment 5 electronic components, electronic devices, large scale computers, space equipment, and data centers (also referred to as data centers (DCs)) in which the semiconductor device described in the above embodiment can be used will be described.
  • the electronic components, electronic devices, large scale computers, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.
  • FIG. 30A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 700 is mounted.
  • the electronic component 700 shown in FIG. 30A has a semiconductor device 710 in a mold 711. In FIG. 30A, some parts are omitted in order to show the inside of the electronic component 700.
  • the electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714.
  • the electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
  • the semiconductor device 710 also has a drive circuit layer 715 and a memory layer 716.
  • the memory layer 716 is configured by stacking a plurality of memory cell arrays.
  • the stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) and bonding technology such as Cu-Cu direct bonding.
  • TSV Through Silicon Via
  • bonding technology such as Cu-Cu direct bonding.
  • the memory as an on-chip memory, it is possible to reduce the size of the connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).
  • the multiple memory cell arrays in the memory layer 716 are formed using OS transistors and the multiple memory cell arrays are monolithically stacked.
  • OS transistors By configuring the multiple memory cell arrays as monolithic stacks, it is possible to improve either or both of the memory bandwidth and the memory access latency.
  • the bandwidth is the amount of data transferred per unit time
  • the access latency is the time from access to the start of data exchange.
  • Si transistors when Si transistors are used for the memory layer 716, it is difficult to configure the memory layer 716 as a monolithic stack compared to OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in the monolithic stack configuration.
  • the semiconductor device 710 may also be referred to as a die.
  • a die refers to a chip piece obtained during the manufacturing process of a semiconductor chip by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into cubes.
  • Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also called a silicon wafer
  • a silicon die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.
  • Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module).
  • Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.
  • semiconductor device 710 is used as a high bandwidth memory (HBM).
  • semiconductor device 735 can be used in integrated circuits such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).
  • CPU central processing unit
  • GPU graphics processing unit
  • FPGA field programmable gate array
  • the package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.
  • the interposer 731 may be, for example, a silicon interposer or a resin interposer.
  • the interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732.
  • the interposer is sometimes called a "rewiring substrate” or "intermediate substrate.”
  • a through electrode is provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrode.
  • a TSV can also be used as the through electrode.
  • the interposer that implements the HBM requires fine, high-density wiring. For this reason, it is preferable to use a silicon interposer for the interposer that implements the HBM.
  • silicon interposers Furthermore, in SiP and MCM using silicon interposers, deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.
  • a composite structure may be used that combines a memory cell array stacked using TSVs and a monolithic stacking memory cell array.
  • a heat sink may be provided overlapping the electronic component 730.
  • electrodes 733 may be provided on the bottom of the package substrate 732.
  • FIG. 30B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved.
  • the electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.
  • the electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA.
  • mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).
  • FIG. 31A a perspective view of an electronic device 6500 is shown in FIG. 31A.
  • the electronic device 6500 shown in FIG. 31A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like.
  • the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.
  • the electronic device 6600 shown in FIG. 31B is an information terminal that can be used as a notebook personal computer.
  • the electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like.
  • the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention for the above-described control device 6509 and control device 6616 is preferable because power consumption can be reduced.
  • Fig. 31C shows a perspective view of the large scale computer 5600.
  • the large scale computer 5600 shown in Fig. 31C has a rack 5610 housing a plurality of rack-mounted computers 5620.
  • the large scale computer 5600 may also be called a supercomputer.
  • Computer 5620 can be configured, for example, as shown in the perspective view of FIG. 31D.
  • computer 5620 has motherboard 5630, which has multiple slots 5631 and multiple connection terminals.
  • PC card 5621 is inserted into slot 5631.
  • PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to motherboard 5630.
  • PC card 5621 shown in FIG. 31E is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like.
  • PC card 5621 has board 5622.
  • Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629.
  • FIG. 31E illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for those semiconductor devices, please refer to the explanation of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 described below.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • An example of the standard for the connection terminal 5629 is PCIe.
  • Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
  • the semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • the electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • An example of the semiconductor device 5628 is a memory device.
  • the electronic component 700 can be used as the semiconductor device 5628.
  • the mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment, such as equipment for processing and storing data.
  • the semiconductor device of one embodiment of the present invention can include an OS transistor.
  • the OS transistor has small changes in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and can be preferably used in an environment where radiation may be incident.
  • the OS transistor can be preferably used in outer space.
  • an artificial satellite 6800 is shown as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807.
  • a planet 6804 is shown as an example of outer space.
  • outer space refers to an altitude of 100 km or more, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.
  • the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit.
  • BMS battery management system
  • the use of OS transistors in the above-mentioned battery management system or battery control circuit is preferable because it has low power consumption and high reliability even in outer space.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • the power required for the operation of the satellite 6800 is generated.
  • the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated.
  • the solar panel may be called a solar cell module.
  • Satellite 6800 can generate a signal.
  • the signal is transmitted via antenna 6803, and can be received, for example, by a receiver installed on the ground or by another satellite.
  • the position of the receiver that received the signal can be measured.
  • satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device.
  • a semiconductor device according to one embodiment of the present invention is preferably used for the control device 6807.
  • an OS transistor Compared to a Si transistor, an OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure. In other words, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can also be configured to have a sensor. For example, by configuring it to have a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground. Or, by configuring it to have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is given as an example of space equipment, but the present invention is not limited to this.
  • a semiconductor device according to one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.
  • the semiconductor device can be suitably used in a storage system applied to a data center or the like.
  • the data center is required to perform long-term management of data, such as by ensuring the immutability of the data.
  • it is necessary to increase the size of the building for example, by installing storage and servers for storing a huge amount of data, by securing a stable power source for holding the data, or by securing cooling equipment required for holding the data.
  • a semiconductor device By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores the data. This makes it possible to miniaturize the storage system, miniaturize the power source for storing data, and reduce the scale of cooling equipment. This makes it possible to save space in the data center.
  • the semiconductor device of one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. This reduces adverse effects of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. This improves the reliability of the data center.
  • Figure 33 shows a storage system applicable to a data center.
  • the storage system 7000 shown in Figure 33 has multiple servers 7001sb as hosts 7001 (illustrated as Host Computer). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage).
  • the host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).
  • SAN Storage Area Network
  • the host 7001 corresponds to a computer that accesses data stored in the storage 7003.
  • the hosts 7001 may be connected to each other via a network.
  • Storage 7003 uses flash memory to reduce data access speed, that is, the time required to store and output data, but this time is significantly longer than the time required by DRAM that can be used as cache memory in storage 7003.
  • cache memory is usually provided in storage 7003 to reduce the time required to store and output data.
  • the above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.
  • OS transistors as transistors for storing data in the above-mentioned cache memory and configuring them to hold a potential according to the data, it is possible to reduce the frequency of refreshes and lower power consumption.
  • memory cell arrays in a stacked structure, it is possible to miniaturize the storage.
  • the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO 2 ). In addition, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming because of its low power consumption.
  • CO 2 greenhouse gases
  • ADDR signal, BL[1]: wiring, BL[j]: wiring, BL[n]: wiring, BL_A: wiring, BL_B: wiring, BL: wiring, BW: signal, CE: signal, CLK: signal, EN_data: signal, GBL_A: wiring, GBL_B: wiring, GBL: wiring, GW: signal, MUX: selection signal, PL[1]: wiring, PL[i]: wiring, PL[m]: wiring, PL: wiring, RDA : signal, RE: control signal, VHH: wiring, VLL: wiring, VPC: intermediate potential, WAKE: signal, WDA: signal, WE: control signal, WL[1]: wiring, WL[i]: wiring, WL[m]: wiring, WL: wiring, 10[1,1]: memory cell, 10[i,j]: memory cell, 10[m,n]: memory cell, 10_A: memory cell, 10_B: memory cell, 10: memory cell, 1 1: transistor, 12: capac

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Abstract

The present invention provides a semiconductor device which achieves miniaturization or high integration. This semiconductor device comprises a first insulator on a substrate, an oxide semiconductor that covers the first insulator, a first conductor and a second conductor on the oxide semiconductor, a second insulator disposed on the first conductor and the second conductor and having an opening overlapping a region between the first conductor and the second conductor, a third insulator disposed inside the opening and disposed on the oxide semiconductor, and a third conductor disposed inside the opening and disposed on the third insulator. The height of the first insulator is longer than the width of the first insulator.

Description

半導体装置、及び記憶装置Semiconductor device and storage device
　本発明の一態様は、酸化物半導体層を用いた半導体装置、記憶装置、及び電子機器に関する。また、本発明の一態様は、上記半導体装置の作製方法に関する。 One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device that use an oxide semiconductor layer. Another aspect of the present invention relates to a method for manufacturing the semiconductor device.
　なお、本発明の一態様は、上記の技術分野に限定されない。本発明の一態様の技術分野としては、半導体装置、表示装置、発光装置、蓄電装置、記憶装置、電子機器、照明装置、入力装置（例えば、タッチセンサ）、入出力装置（例えば、タッチパネル）、それらの駆動方法、またはそれらの製造方法を一例として挙げることができる。 Note that one embodiment of the present invention is not limited to the above technical field. Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, or manufacturing methods thereof.
　なお、本明細書等において半導体装置とは、半導体特性を利用することで機能し得る装置全般を指す。トランジスタなどの半導体素子をはじめ、半導体回路、演算装置、記憶装置は、半導体装置の一態様である。表示装置（液晶表示装置、発光表示装置など）、投影装置、照明装置、電気光学装置、蓄電装置、記憶装置、半導体回路、撮像装置、電子機器などは、半導体装置を有するといえる場合がある。 In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices, are one embodiment of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be said to have semiconductor devices.
　近年、半導体装置の開発が進められ、ＬＳＩ、ＣＰＵ、メモリなどが主に半導体装置に用いられている。ＣＰＵは、半導体ウエハを加工し、チップ化された半導体集積回路（少なくともトランジスタ及びメモリ）を有し、接続端子である電極が形成された半導体素子の集合体である。 In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, memories, etc. are mainly used in semiconductor devices. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) that are chipped by processing a semiconductor wafer and have electrodes that serve as connection terminals.
　ＬＳＩ、ＣＰＵ、メモリなどの半導体回路（ＩＣチップ）は、回路基板、例えばプリント配線基板に実装され、様々な電子機器の部品の一つとして用いられる。 Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.
　また、絶縁表面を有する基板上に形成された半導体薄膜を用いてトランジスタを構成する技術が注目されている。該トランジスタは集積回路（ＩＣ）、画像表示装置（単に表示装置とも表記する）のような電子デバイスに広く応用されている。トランジスタに適用可能な半導体薄膜としてシリコン系半導体材料が広く知られているが、その他の材料として酸化物半導体が注目されている。 In addition, technology that constructs transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.
　また、酸化物半導体を用いたトランジスタは、非導通状態において極めてリーク電流が小さいことが知られている。例えば、特許文献１には、酸化物半導体を用いたトランジスタのリーク電流が小さいという特性を応用した低消費電力のＣＰＵなどが開示されている。また、例えば、特許文献２には、酸化物半導体を用いたトランジスタのリーク電流が小さいという特性を応用して、長期にわたり記憶内容を保持することができる記憶装置などが、開示されている。 In addition, it is known that transistors using oxide semiconductors have extremely low leakage current when in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of low leakage current of transistors using oxide semiconductors. In addition, for example, Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by utilizing the property of low leakage current of transistors using oxide semiconductors.
　また、近年では電子機器の小型化、軽量化に伴い、集積回路のさらなる高密度化への要求が高まっている。また、集積回路を含む半導体装置の生産性の向上が求められている。例えば、特許文献３及び非特許文献１では、酸化物半導体膜を用いる第１のトランジスタと、酸化物半導体膜を用いる第２のトランジスタとを積層させることで、メモリセルを複数重畳して設けることにより、集積回路の高密度化を図る技術が開示されている。また、例えば、特許文献４のように、酸化物半導体膜を用いるトランジスタのチャネルを縦方向に配置し、集積回路の高密度化を図る技術も開示されている。 Furthermore, in recent years, with the miniaturization and weight reduction of electronic devices, there is an increasing demand for further increasing the density of integrated circuits. There is also a demand for improving the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple overlapping memory cells. In addition, for example, Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.
特開２０１２−２５７１８７号公報JP 2012-257187 A 特開２０１１−１５１３８３号公報JP 2011-151383 A 国際公開第２０２１／０５３４７３号International Publication No. 2021/053473 特開２０１３−２１１５３７号公報JP 2013-211537 A
　本発明の一態様は、微細化または高集積化が可能な半導体装置を提供することを課題の一とする。または、本発明の一態様は、動作速度が速い半導体装置を提供することを課題の一とする。または、本発明の一態様は、良好な電気特性を有する半導体装置を提供することを課題の一とする。または、本発明の一態様は、トランジスタの電気特性のばらつきが少ない半導体装置を提供することを課題の一とする。または、本発明の一態様は、信頼性が高い半導体装置を提供することを課題の一とする。または、本発明の一態様は、オン電流が大きい半導体装置を提供することを課題の一とする。または、本発明の一態様は、消費電力が少ない半導体装置を提供することを課題の一とする。または、本発明の一態様は、新規の半導体装置を提供することを課題の一とする。または、本発明の一態様は、生産性の高い半導体装置の作製方法を提供することを課題の一とする。または、本発明の一態様は、新規の半導体装置の作製方法を提供することを課題の一とする。 An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with high on-current. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Alternatively, an object of one embodiment of the present invention is to provide a new semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Alternatively, an object of one embodiment of the present invention is to provide a method for manufacturing a new semiconductor device.
　または、本発明の一態様は、微細化または高集積化が可能な記憶装置を提供することを課題の一とする。または、本発明の一態様は、記憶容量が大きい記憶装置を提供することを課題の一とする。または、本発明の一態様は、動作速度が速い記憶装置を提供することを課題の一とする。または、本発明の一態様は、消費電力が少ない記憶装置を提供することを課題の一とする。または、本発明の一態様は、新規な記憶装置を提供することを課題の一とする。 Alternatively, one object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated. Alternatively, one object of one embodiment of the present invention is to provide a memory device with a large storage capacity. Alternatively, one object of one embodiment of the present invention is to provide a memory device with a high operating speed. Alternatively, one object of one embodiment of the present invention is to provide a memory device with low power consumption. Alternatively, one object of one embodiment of the present invention is to provide a novel memory device.
　なお、これらの課題の記載は、他の課題の存在を妨げるものではない。本発明の一態様は、必ずしも、これらの課題の全てを解決する必要はないものとする。明細書、図面、請求項の記載から、これら以外の課題を抽出することが可能である。 Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.
　本発明の一態様は、基板上の第１の絶縁体と、第１の絶縁体を覆う酸化物半導体と、酸化物半導体上の第１の導電体及び第２の導電体と、第１の導電体、及び第２の導電体上に配置され、第１の導電体と第２の導電体の間の領域と重畳する開口を有する、第２の絶縁体と、開口内に配置され、酸化物半導体上に配置される第３の絶縁体と、開口内に配置され、第３の絶縁体上に配置される、第３の導電体と、を有し、チャネル幅方向の断面視において、第１の絶縁体の高さは、第１の絶縁体の幅より長い、半導体装置である。 One aspect of the present invention is a semiconductor device having a first insulator on a substrate, an oxide semiconductor covering the first insulator, a first conductor and a second conductor on the oxide semiconductor, a second insulator disposed on the first conductor and the second conductor and having an opening overlapping a region between the first conductor and the second conductor, a third insulator disposed in the opening and on the oxide semiconductor, and a third conductor disposed in the opening and on the third insulator, and in a cross-sectional view in the channel width direction, the height of the first insulator is greater than the width of the first insulator.
　上記において、平面視において、第２の絶縁体の開口の側面は、第１の導電体の側面、及び第２の導電体の側面と一致または概略一致する、ことが好ましい。 In the above, it is preferable that, in a plan view, the side of the opening of the second insulator coincides or roughly coincides with the side of the first conductor and the side of the second conductor.
　また、上記において、チャネル幅方向の断面視において、第１の絶縁体の高さは、第１の絶縁体の幅の２倍以上２０倍以下である、ことが好ましい。 Furthermore, in the above, it is preferable that the height of the first insulator is at least 2 times and at most 20 times the width of the first insulator when viewed in a cross section in the channel width direction.
　また、上記において、第１の導電体は、トランジスタのソース電極及びドレイン電極の一方として機能し、第２の導電体は、トランジスタのソース電極及びドレイン電極の他方として機能し、第３の導電体は、トランジスタのゲート電極として機能する、ことが好ましい。 Furthermore, in the above, it is preferable that the first conductor functions as one of the source electrode and drain electrode of the transistor, the second conductor functions as the other of the source electrode and drain electrode of the transistor, and the third conductor functions as the gate electrode of the transistor.
　また、上記の半導体装置は、チャネル幅方向の断面視において、第１の絶縁体の一方の側面で、酸化物半導体と第３の導電体が第３の絶縁体を挟んで対向し、第１の絶縁体の他方の側面で、酸化物半導体と第３の導電体が第３の絶縁体を挟んで対向する、ことが好ましい。 Furthermore, in the above-mentioned semiconductor device, it is preferable that, in a cross-sectional view in the channel width direction, the oxide semiconductor and the third conductor face each other on one side of the first insulator, sandwiching the third insulator therebetween, and that the oxide semiconductor and the third conductor face each other on the other side of the first insulator, sandwiching the third insulator therebetween.
　また、上記の半導体装置は、チャネル幅方向の断面視において、第１の導電体は、第１の絶縁体の一方の側面側、及び他方の側面側において、酸化物半導体と接し、第２の導電体は、第１の絶縁体の一方の側面側、及び他方の側面側において、酸化物半導体と接する、ことが好ましい。 Furthermore, in the above-mentioned semiconductor device, it is preferable that, in a cross-sectional view in the channel width direction, the first conductor contacts the oxide semiconductor on one side and the other side of the first insulator, and the second conductor contacts the oxide semiconductor on one side and the other side of the first insulator.
　また、上記において、酸化物半導体は、Ｉｎ、Ｇａ、及びＺｎの中から選ばれるいずれか一または複数を有する、ことが好ましい。 In the above, it is preferable that the oxide semiconductor contains one or more elements selected from the group consisting of In, Ga, and Zn.
　また、本発明の他の一態様は、上記の半導体装置と、容量素子と、を有し、容量素子の一方の電極が、半導体装置の第１の導電体と電気的に接続される、記憶装置である。 Another aspect of the present invention is a memory device that includes the above-described semiconductor device and a capacitor, in which one electrode of the capacitor is electrically connected to a first conductor of the semiconductor device.
　また、上記において、容量素子は、第３の導電体上に配置され、容量素子の少なくとも一部は、酸化物半導体、及び第３の導電体と重畳する、ことが好ましい。 Furthermore, in the above, it is preferable that the capacitive element is disposed on the third conductor, and at least a portion of the capacitive element overlaps with the oxide semiconductor and the third conductor.
　本発明の一態様により、微細化または高集積化が可能な半導体装置を提供できる。または、本発明の一態様により、動作速度が速い半導体装置を提供できる。または、本発明の一態様により、良好な電気特性を有する半導体装置を提供できる。または、本発明の一態様により、トランジスタの電気特性のばらつきが少ない半導体装置を提供できる。または、本発明の一態様により、信頼性が高い半導体装置を提供できる。または、本発明の一態様により、オン電流が大きい半導体装置を提供できる。または、本発明の一態様により、消費電力が少ない半導体装置を提供できる。または、本発明の一態様により、新規の半導体装置を提供できる。または、本発明の一態様により、生産性の高い半導体装置の作製方法を提供できる。または、本発明の一態様により、新規の半導体装置の作製方法を提供できる。 According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with less variation in electrical characteristics of transistors can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.
　または、本発明の一態様により、微細化または高集積化が可能な記憶装置を提供できる。または、本発明の一態様により、記憶容量が大きい記憶装置を提供できる。または、本発明の一態様により、動作速度が速い記憶装置を提供できる。または、本発明の一態様により、消費電力が少ない記憶装置を提供できる。または、本発明の一態様により、新規な記憶装置を提供できる。 Alternatively, according to one embodiment of the present invention, a memory device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a memory device with a large storage capacity can be provided. Alternatively, according to one embodiment of the present invention, a memory device with a high operating speed can be provided. Alternatively, according to one embodiment of the present invention, a memory device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a novel memory device can be provided.
　なお、これらの効果の記載は、他の効果の存在を妨げるものではない。本発明の一態様は、必ずしも、これらの効果の全てを有する必要はない。明細書、図面、請求項の記載から、これら以外の効果を抽出することが可能である。 Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have to have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.
図１Ａは、半導体装置の一例を示す平面図である。図１Ｂ乃至図１Ｄは、半導体装置の一例を示す断面図である。
図２Ａ及び図２Ｂは、半導体装置の一例を示す断面図である。
図３Ａ乃至図３Ｃは、半導体装置の一例を示す断面図である。
図４Ａ乃至図４Ｃは、半導体装置の一例を示す断面図である。
図５Ａは、半導体装置の一例を示す平面図である。図５Ｂ乃至図５Ｄは、半導体装置の一例を示す断面図である。
図６Ａは、半導体装置の一例を示す平面図である。図６Ｂ乃至図６Ｄは、半導体装置の一例を示す断面図である。
図７Ａは、半導体装置の一例を示す平面図である。図７Ｂ乃至図７Ｄは、半導体装置の一例を示す断面図である。
図８は、半導体装置の一例を示す断面図である。
図９Ａは、半導体装置の一例を示す平面図である。図９Ｂ乃至図９Ｄは、半導体装置の一例を示す断面図である。
図１０Ａ及び図１０Ｂは、半導体装置の一例を示す断面図である。
図１１Ａは、半導体装置の作製方法の一例を示す平面図である。図１１Ｂ乃至図１１Ｄは、半導体装置の作製方法の一例を示す断面図である。
図１２Ａは、半導体装置の作製方法の一例を示す平面図である。図１２Ｂ乃至図１２Ｄは、半導体装置の作製方法の一例を示す断面図である。
図１３Ａは、半導体装置の作製方法の一例を示す平面図である。図１３Ｂ乃至図１３Ｄは、半導体装置の作製方法の一例を示す断面図である。
図１４Ａは、半導体装置の作製方法の一例を示す平面図である。図１４Ｂ乃至図１４Ｄは、半導体装置の作製方法の一例を示す断面図である。
図１５Ａは、半導体装置の作製方法の一例を示す平面図である。図１５Ｂ乃至図１５Ｄは、半導体装置の作製方法の一例を示す断面図である。
図１６Ａは、半導体装置の作製方法の一例を示す平面図である。図１６Ｂ乃至図１６Ｄは、半導体装置の作製方法の一例を示す断面図である。
図１７Ａは、半導体装置の作製方法の一例を示す平面図である。図１７Ｂ乃至図１７Ｄは、半導体装置の作製方法の一例を示す断面図である。
図１８Ａは、半導体装置の作製方法の一例を示す平面図である。図１８Ｂ乃至図１８Ｄは、半導体装置の作製方法の一例を示す断面図である。
図１９Ａは、半導体装置の作製方法の一例を示す平面図である。図１９Ｂ乃至図１９Ｄは、半導体装置の作製方法の一例を示す断面図である。
図２０Ａは、半導体装置の作製方法の一例を示す平面図である。図２０Ｂ乃至図２０Ｄは、半導体装置の作製方法の一例を示す断面図である。
図２１Ａは、半導体装置の作製方法の一例を示す平面図である。図２１Ｂ乃至図２１Ｄは、半導体装置の作製方法の一例を示す断面図である。
図２２は、記憶装置の一例を示すブロック図である。
図２３Ａ及び図２３Ｂは、記憶装置の一例を示す模式図及び回路図である。
図２４Ａ及び図２４Ｂは、記憶装置の一例を示す模式図である。
図２５は、記憶装置の一例を示す回路図である。
図２６Ａ及び図２６Ｂは、記憶装置の一例を示す断面図である。
図２７Ａ及び図２７Ｂは、記憶装置の一例を示す断面図である。
図２８は、記憶装置の一例を示す断面図である。
図２９Ａ及び図２９Ｂは半導体装置の一例を示す図である。
図３０Ａ及び図３０Ｂは、電子部品の一例を示す図である。
図３１Ａ及び図３１Ｂは、電子機器の一例を示す図であり、図３１Ｃ乃至図３１Ｅは、大型計算機の一例を示す図である。
図３２は、宇宙用機器の一例を示す図である。
図３３は、データセンターに適用可能なストレージシステムの一例を示す図である。 Fig. 1A is a plan view showing an example of a semiconductor device, and Figs. 1B to 1D are cross-sectional views showing the example of the semiconductor device.
2A and 2B are cross-sectional views showing an example of a semiconductor device.
3A to 3C are cross-sectional views showing an example of a semiconductor device.
4A to 4C are cross-sectional views showing an example of a semiconductor device.
Fig. 5A is a plan view showing an example of a semiconductor device, and Figs. 5B to 5D are cross-sectional views showing an example of the semiconductor device.
Fig. 6A is a plan view showing an example of a semiconductor device, and Figs. 6B to 6D are cross-sectional views showing an example of the semiconductor device.
Fig. 7A is a plan view showing an example of a semiconductor device, and Figs. 7B to 7D are cross-sectional views showing an example of the semiconductor device.
FIG. 8 is a cross-sectional view showing an example of a semiconductor device.
9A is a plan view showing an example of a semiconductor device, and FIGS. 9B to 9D are cross-sectional views showing an example of the semiconductor device.
10A and 10B are cross-sectional views showing an example of a semiconductor device.
11A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS.
12A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 12B to 12D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
13A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 13B to 13D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
14A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 14B to 14D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
15A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 15B to 15D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
16A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 16B to 16D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
17A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 17B to 17D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
18A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 18B to 18D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
19A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 19B to 19D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
20A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 20B to 20D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
21A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 21B to 21D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
FIG. 22 is a block diagram illustrating an example of a storage device.
23A and 23B are a schematic diagram and a circuit diagram showing an example of a memory device.
24A and 24B are schematic diagrams showing an example of a storage device.
FIG. 25 is a circuit diagram showing an example of a memory device.
26A and 26B are cross-sectional views showing an example of a memory device.
27A and 27B are cross-sectional views showing an example of a memory device.
FIG. 28 is a cross-sectional view showing an example of a storage device.
29A and 29B are diagrams showing an example of a semiconductor device.
30A and 30B are diagrams illustrating an example of an electronic component.
31A and 31B are diagrams showing an example of electronic equipment, and FIGS. 31C to 31E are diagrams showing an example of a mainframe computer.
FIG. 32 is a diagram showing an example of space equipment.
FIG. 33 is a diagram illustrating an example of a storage system applicable to a data center.
　実施の形態について、図面を用いて詳細に説明する。但し、本発明は以下の説明に限定されず、本発明の趣旨及びその範囲から逸脱することなくその形態及び詳細を様々に変更し得ることは当業者であれば容易に理解される。従って、本発明は以下に示す実施の形態の記載内容に限定して解釈されるものではない。 The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will easily understand that the form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.
　なお、以下に説明する発明の構成において、同一部分又は同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、その繰り返しの説明は省略する。また、同様の機能を指す場合には、ハッチングパターンを同じくし、特に符号を付さない場合がある。 In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.
　また、図面において示す各構成の、位置、大きさ、及び、範囲などは、理解の簡単のため、実際の位置、大きさ、及び、範囲などを表していない場合がある。このため、開示する発明は、必ずしも、図面に開示された位置、大きさ、及び、範囲などに限定されない。 Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. For this reason, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.
　また、特に平面図（「上面図」ともいう）、または斜視図などにおいて、発明の理解を容易とするため、一部の構成要素の記載を省略する場合がある。また、一部の隠れ線の記載を省略する場合がある。 In order to make the invention easier to understand, particularly in plan views (also called "top views") or perspective views, some components may be omitted from the illustration. Also, some hidden lines may be omitted from the illustration.
　なお、本明細書等において、「第１」、「第２」という序数詞は、便宜上用いるものであり、構成要素の数、または、構成要素の順序（例えば、工程順、または積層順）を限定するものではない。また、本明細書のある箇所において構成要素に付す序数詞と、本明細書の他の箇所、または特許請求の範囲において、当該構成要素に付す序数詞と、が一致しない場合がある。 In this specification and the like, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking). Furthermore, an ordinal number attached to a component in one place in this specification may not match an ordinal number attached to the same component in another place in this specification or in the claims.
　なお、「膜」という言葉と、「層」という言葉とは、場合によっては、または、状況に応じて、互いに入れ替えることが可能である。例えば、「導電層」という用語を、「導電膜」という用語に変更することが可能である。または、例えば、「絶縁膜」という用語を、「絶縁層」という用語に変更することが可能である。また、「導電体」という用語は、場合によっては、または、状況に応じて、「導電層」という用語、または「導電膜」という用語に、互いに入れ替えることが可能である。また、「絶縁体」という用語は、場合によっては、または、状況に応じて、「絶縁層」という用語、または「絶縁膜」という用語に、互いに入れ替えることが可能である。 The terms "film" and "layer" may be interchangeable depending on the circumstances. For example, the term "conductive layer" may be interchangeable with the term "conductive film". Or, for example, the term "insulating film" may be interchangeable with the term "insulating layer". Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or the term "conductive film" depending on the circumstances. Furthermore, the term "insulating material" may be interchangeable with the term "insulating layer" or the term "insulating film" depending on the circumstances.
　また、本明細書等において、「平行」とは、二つの直線が−１０度以上１０度以下の角度で配置されている状態をいう。したがって、−５度以上５度以下の場合も含まれる。また、「概略平行」とは、二つの直線が−３０度以上３０度以下の角度で配置されている状態をいう。また、「垂直」とは、二つの直線が８０度以上１００度以下の角度で配置されている状態をいう。したがって、８５度以上９５度以下の場合も含まれる。また、「概略垂直」とは、二つの直線が６０度以上１２０度以下の角度で配置されている状態をいう。 In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
　開口とは、例えば、溝、スリットなども含まれる。また、開口が形成された領域を開口部と記す場合がある。 Openings include, for example, grooves and slits. Also, the area in which an opening is formed may be referred to as an opening.
　また、本明細書における実施の形態で用いる図面において、絶縁体の開口部における、側壁が、基板面または被形成面に対して垂直、または概略垂直である場合を示すが、テーパー形状であってもよい。 In addition, in the drawings used in the embodiments of this specification, the side walls of the opening in the insulator are shown as being perpendicular or approximately perpendicular to the substrate surface or the surface on which the film is formed, but they may also be tapered.
　なお、本明細書等において、テーパー形状とは、構造の側面の少なくとも一部が、基板面または被形成面に対して傾斜して設けられている形状のことを指す。例えば、傾斜した側面と基板面または被形成面とがなす角（以下、テーパー角と呼ぶ場合がある）が９０°未満である領域を有する形状のことを指す。なお、構造の側面及び基板面は、必ずしも完全に平坦である必要はなく、微細な曲率を有する略平面状、または微細な凹凸を有する略平面状であってもよい。 In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface or the surface on which the structure is to be formed. For example, it refers to a shape having an area in which the angle between the inclined side and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. Note that the side of the structure and the substrate surface do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.
　なお、本明細書等において、「高さが一致または概略一致」とは、断面視において、基準となる面（例えば、基板表面などの平坦な面）からの高さが等しい構成を示す。例えば、記憶装置の製造プロセスにおいて、平坦化処理（代表的にはＣＭＰ処理）を行うことで、単層または複数の層の表面を露出する場合がある。この場合、ＣＭＰ処理の被処理面は、基準となる面からの高さが等しい構成となる。ただし、ＣＭＰ処理の際の処理装置、処理方法、または被処理面の材料によって、複数の層の高さが異なる場合がある。本明細書等においては、この場合も「高さが一致または概略一致」として扱う。例えば、基準面に対して、２つの高さを有する層（ここでは第１の層と、第２の層とする）を有する場合、第１の層の上面の高さと、第２の層の上面の高さとの差が、２０ｎｍ以下である場合も、「高さが一致または概略一致」という。 In this specification, "the same or approximately the same height" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in the manufacturing process of a memory device, a planarization process (typically a CMP process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces treated in the CMP process are configured to have the same height from the reference surface. However, the heights of multiple layers may differ depending on the processing device, processing method, or material of the processed surface during the CMP process. In this specification, this case is also treated as "the same or approximately the same height". For example, in the case of a layer having two heights (here, a first layer and a second layer) with respect to the reference surface, if the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, this is also referred to as "the same or approximately the same height".
　なお、本明細書等において、「側端部が一致または概略一致」とは、平面視において、積層した層と層との間で少なくとも輪郭の一部が重なることをいう。例えば、上層と下層とが、同一のマスクパターン、または一部が同一のマスクパターンにより加工された場合を含む。ただし、厳密には輪郭が重ならず、上層の輪郭が下層の輪郭より内側に位置すること、または、上層の輪郭が下層の輪郭より外側に位置することもあり、この場合も「側端部が一致または概略一致」という。 In this specification, "side edges that coincide or roughly coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "side edges that coincide or roughly coincide" is also used.
（実施の形態１）
　本実施の形態では、酸化物半導体層を有する半導体装置、及び当該半導体装置の作製方法について、図１乃至図２１を用いて説明する。 (Embodiment 1)
In this embodiment, a semiconductor device including an oxide semiconductor layer and a method for manufacturing the semiconductor device will be described with reference to FIGS.
＜半導体装置の構成例＞
　図１乃至図１０を用いて、半導体装置の構成例について説明する。図１Ａ乃至図１Ｄは、基板（図示せず）上にトランジスタ２００ａ、及びトランジスタ２００ｂを有する、半導体装置の上面図および断面図である。なお、トランジスタ２００ｂは、トランジスタ２００ａと同様の構造を有するため、構成要素にトランジスタ２００ａと同じハッチングパターンを付し、特に符号を付さない。また、以下において、トランジスタ２００ａとトランジスタ２００ｂをまとめてトランジスタ２００と記載する場合がある。なお、本実施の形態に示す半導体装置は、トランジスタ２００ａと電気的に接続する容量素子、及びトランジスタ２００ｂと電気的に接続する容量素子を設けることで、２個の１Ｔ（トランジスタ）１Ｃ（容量）型のメモリセルとして機能させることができ、記憶装置に用いることもできる。 <Configuration Example of Semiconductor Device>
A configuration example of a semiconductor device will be described with reference to FIG. 1 to FIG. 10. FIG. 1A to FIG. 1D are a top view and a cross-sectional view of a semiconductor device having a transistor 200a and a transistor 200b over a substrate (not shown). Note that the transistor 200b has a similar structure to the transistor 200a, and therefore the components are given the same hatching pattern as the transistor 200a, and are not particularly marked with reference symbols. In addition, in the following, the transistors 200a and 200b may be collectively referred to as the transistor 200. Note that the semiconductor device described in this embodiment can function as two 1T (transistor) 1C (capacitor) type memory cells by providing a capacitor electrically connected to the transistor 200a and a capacitor electrically connected to the transistor 200b, and can also be used for a memory device.
　図１Ａは、上記半導体装置の上面図である。また、図１Ｂ乃至図１Ｄは、当該半導体装置の断面図である。ここで、図１Ｂは、図１ＡにＡ１−Ａ２の一点鎖線で示す部位の断面図であり、トランジスタ２００ａのチャネル長方向の断面図でもある。また、図１Ｃは、図１ＡにＡ３−Ａ４の一点鎖線で示す部位の断面図であり、トランジスタ２００ａ及びトランジスタ２００ｂのチャネル幅方向の断面図でもある。また、図１Ｄは、図１ＡにＡ５−Ａ６の一点鎖線で示す部位の断面図であり、トランジスタ２００ａ及びトランジスタ２００ｂのチャネル幅方向の断面図でもある。ここで、Ａ１−Ａ２の一点鎖線は、Ａ３−Ａ４の一点鎖線及びＡ５−Ａ６の一点鎖線と直交しており、Ａ３−Ａ４の一点鎖線とＡ５−Ａ６の一点鎖線は互いに平行である。なお、図１Ａの上面図では、図の明瞭化のために一部の要素を省いている。また、図２Ａに、図１Ｂの導電体２６０近傍の拡大図を示す。また、図２Ｂに、図１Ｃの絶縁体２２５近傍の拡大図を示す。また、図４Ａに、図１Ｂの導電体２４２ａ近傍の拡大図を示す。また、図４Ｂに、図１Ｄの絶縁体２２５近傍の拡大図を示す。 1A is a top view of the semiconductor device. Also, FIGS. 1B to 1D are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 1A, and is also a cross-sectional view in the channel length direction of the transistor 200a. Also, FIG. 1C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 1A, and is also a cross-sectional view in the channel width direction of the transistors 200a and 200b. Also, FIG. 1D is a cross-sectional view of the portion indicated by the dashed line A5-A6 in FIG. 1A, and is also a cross-sectional view in the channel width direction of the transistors 200a and 200b. Here, the dashed line A1-A2 is perpendicular to the dashed line A3-A4 and the dashed line A5-A6, and the dashed line A3-A4 and the dashed line A5-A6 are parallel to each other. Note that some elements are omitted in the top view of FIG. 1A to clarify the figure. FIG. 2A shows an enlarged view of the vicinity of the conductor 260 in FIG. 1B. FIG. 2B shows an enlarged view of the vicinity of the insulator 225 in FIG. 1C. FIG. 4A shows an enlarged view of the vicinity of the conductor 242a in FIG. 1B. FIG. 4B shows an enlarged view of the vicinity of the insulator 225 in FIG. 1D.
　本実施の形態に係る半導体装置は、基板（図示せず）上の絶縁体２１６に埋め込まれるように設けられた導電体２０５（導電体２０５ａ及び導電体２０５ｂ）と、絶縁体２１６及び導電体２０５上の絶縁体２２１と、絶縁体２２１上の絶縁体２２２と、絶縁体２２２上の絶縁体２２５と、絶縁体２２５及び絶縁体２２２上の酸化物２３０（酸化物２３０ａ及び酸化物２３０ｂ）と、酸化物２３０上の導電体２４２ａ及び導電体２４２ｂと、酸化物２３０上の絶縁体２５０と、絶縁体２５０上の導電体２６０（導電体２６０ａ及び導電体２６０ｂ）と、を有する。なお、以下において、導電体２４２ａと導電体２４２ｂをまとめて導電体２４２と記載する場合がある。 The semiconductor device according to this embodiment has a conductor 205 (conductor 205a and conductor 205b) embedded in an insulator 216 on a substrate (not shown), an insulator 221 on the insulator 216 and the conductor 205, an insulator 222 on the insulator 221, an insulator 225 on the insulator 222, an oxide 230 (oxide 230a and oxide 230b) on the insulator 225 and the insulator 222, a conductor 242a and a conductor 242b on the oxide 230, an insulator 250 on the oxide 230, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250. Note that hereinafter, the conductor 242a and the conductor 242b may be collectively referred to as the conductor 242.
　導電体２４２上には、絶縁体２７５が設けられ、絶縁体２７５上には絶縁体２８０が設けられている。絶縁体２５０、及び導電体２６０は、絶縁体２８０及び絶縁体２７５に設けられた開口の内部に配置されている。また、絶縁体２８０上及び導電体２６０上に絶縁体２８２が設けられている。また、絶縁体２８２上に絶縁体２８３が設けられている。また、絶縁体２１６及び導電体２０５の下に絶縁体２１５が設けられている。 An insulator 275 is provided on the conductor 242, and an insulator 280 is provided on the insulator 275. The insulator 250 and the conductor 260 are disposed inside openings provided in the insulator 280 and the insulator 275. An insulator 282 is provided on the insulator 280 and the conductor 260. An insulator 283 is provided on the insulator 282. An insulator 215 is provided below the insulator 216 and the conductor 205.
　絶縁体２８０などの開口の内壁に接して絶縁体２４１ａが設けられ、絶縁体２４１ａの側面に接して導電体２４０ａが設けられている。導電体２４０ａの下面は、導電体２４２ａの上面に接している。また、絶縁体２８０などの開口の内壁に接して絶縁体２４１ｂが設けられ、絶縁体２４１ｂの側面に接して導電体２４０ｂが設けられている。導電体２４０ｂの下面は、導電体２４２ｂの上面に接している。なお、以下において、導電体２４０ａと導電体２４０ｂをまとめて導電体２４０と記載する場合がある。また、絶縁体２４１ａと絶縁体２４１ｂをまとめて絶縁体２４１と記載する場合がある。 Insulator 241a is provided in contact with the inner wall of the opening of insulator 280, etc., and conductor 240a is provided in contact with the side surface of insulator 241a. The bottom surface of conductor 240a is in contact with the top surface of conductor 242a. Insulator 241b is provided in contact with the inner wall of the opening of insulator 280, etc., and conductor 240b is provided in contact with the side surface of insulator 241b. The bottom surface of conductor 240b is in contact with the top surface of conductor 242b. Note that hereinafter, conductors 240a and 240b may be collectively referred to as conductor 240. Insulators 241a and 241b may be collectively referred to as insulator 241.
　酸化物２３０は、トランジスタ２００のチャネル形成領域として機能する領域を有する。また、導電体２６０は、トランジスタ２００の第１のゲート電極（上側のゲート電極）として機能する領域を有する。絶縁体２５０は、トランジスタ２００の第１のゲート絶縁体として機能する領域を有する。また、導電体２０５は、トランジスタ２００の第２のゲート電極（下側のゲート電極）として機能する領域を有する。絶縁体２２２、及び絶縁体２２１は、それぞれ、トランジスタ２００の第２のゲート絶縁体として機能する領域を有する。 Oxide 230 has a region that functions as a channel formation region of transistor 200. Conductor 260 has a region that functions as a first gate electrode (upper gate electrode) of transistor 200. Insulator 250 has a region that functions as a first gate insulator of transistor 200. Conductor 205 has a region that functions as a second gate electrode (lower gate electrode) of transistor 200. Insulator 222 and insulator 221 each have a region that functions as a second gate insulator of transistor 200.
　導電体２４２ａは、トランジスタ２００のソース電極またはドレイン電極の一方として機能する領域を有する。導電体２４０ａは、導電体２４２ａに接続するプラグとして機能する。導電体２４２ｂは、トランジスタ２００のソース電極またはドレイン電極の他方として機能する領域を有する。導電体２４０ｂは、導電体２４２ｂに接続するプラグとして機能する。 The conductor 242a has a region that functions as one of the source electrode or drain electrode of the transistor 200. The conductor 240a functions as a plug that connects to the conductor 242a. The conductor 242b has a region that functions as the other of the source electrode or drain electrode of the transistor 200. The conductor 240b functions as a plug that connects to the conductor 242b.
　酸化物２３０は、絶縁体２２５を覆う酸化物２３０ａと、酸化物２３０ａ上の酸化物２３０ｂと、を有することが好ましい。ここで、酸化物２３０ａは、絶縁体２２５の上面及び側面、ならびに絶縁体２２２の上面に接する。酸化物２３０ａ及び酸化物２３０ｂは、図２Ｂなどに示すように、アスペクト比が高い絶縁体２２５を覆うように設けられる。よって、酸化物２３０ａ及び酸化物２３０ｂは、ＡＬＤ法などの被覆性の良好な成膜法を用いて成膜することが好ましい。ここで、図２Ｂに示すように、チャネル幅方向の断面では、絶縁体２２５を介して、二つ折りの状態になるように、酸化物２３０ａ及び酸化物２３０ｂが形成される。このような構成にすることで、絶縁体２２５の、上部、Ａ３側の側面、及びＡ４側の側面にトランジスタ２００のチャネル形成領域を形成することができるため、単位面積当たりのチャネル幅を大きくすることができる。 The oxide 230 preferably has an oxide 230a covering the insulator 225 and an oxide 230b on the oxide 230a. Here, the oxide 230a contacts the top and side surfaces of the insulator 225 and the top surface of the insulator 222. As shown in FIG. 2B and other figures, the oxide 230a and the oxide 230b are provided so as to cover the insulator 225, which has a high aspect ratio. Therefore, it is preferable to form the oxide 230a and the oxide 230b using a film formation method with good coverage, such as the ALD method. Here, as shown in FIG. 2B, in the cross section in the channel width direction, the oxide 230a and the oxide 230b are formed so as to be folded in half through the insulator 225. With this configuration, the channel formation region of the transistor 200 can be formed on the top, the side surface on the A3 side, and the side surface on the A4 side of the insulator 225, so that the channel width per unit area can be increased.
　酸化物２３０ｂの下に酸化物２３０ａを有することで、酸化物２３０ａよりも下方に形成された構造物から、酸化物２３０ｂへの不純物の拡散を抑制することができる。 By having oxide 230a below oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below oxide 230a into oxide 230b.
　なお、本実施の形態では、酸化物２３０が、酸化物２３０ａ及び酸化物２３０ｂの２層構造である例を示すが、これに限定されない。酸化物２３０は、例えば、酸化物２３０ｂの単層構造であってもよく、３層以上の積層構造としてもよい。 In the present embodiment, an example is shown in which oxide 230 has a two-layer structure of oxide 230a and oxide 230b, but this is not limiting. Oxide 230 may have, for example, a single-layer structure of oxide 230b, or a laminated structure of three or more layers.
　酸化物２３０ｂには、トランジスタ２００における、チャネル形成領域と、チャネル形成領域を挟むように設けられるソース領域及びドレイン領域と、が形成される。チャネル形成領域の少なくとも一部は、導電体２６０と重なる。ソース領域は導電体２４２ａと重なり、ドレイン領域は導電体２４２ｂと重なる。なお、ソース領域とドレイン領域は互いに入れ替えることができる。 In the oxide 230b, a channel formation region and a source region and a drain region are formed, sandwiching the channel formation region, in the transistor 200. At least a portion of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.
　チャネル形成領域は、ソース領域及びドレイン領域よりも、酸素欠損が少ない、または不純物濃度が低いため、キャリア濃度が低い高抵抗領域である。よって、チャネル形成領域は、ｉ型（真性）または実質的にｉ型であるということができる。 The channel formation region is a high-resistance region with a low carrier concentration because it has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.
　また、ソース領域及びドレイン領域は、酸素欠損が多い、または水素、窒素、金属元素などの不純物濃度が高いため、キャリア濃度が高い低抵抗領域である。すなわち、ソース領域及びドレイン領域は、チャネル形成領域と比較してキャリア濃度が高い、ｎ型の領域（低抵抗領域）である。 The source and drain regions are low-resistance regions with high carrier concentrations due to a large amount of oxygen vacancies or a high concentration of impurities such as hydrogen, nitrogen, and metal elements. In other words, the source and drain regions are n-type regions (low-resistance regions) with a high carrier concentration compared to the channel formation region.
　なお、チャネル形成領域のキャリア濃度は、１×１０１８ｃｍ−３以下、１×１０１７ｃｍ−３未満、１×１０１６ｃｍ−３未満、１×１０１５ｃｍ−３未満、１×１０１４ｃｍ−３未満、１×１０１３ｃｍ−３未満、１×１０１２ｃｍ−３未満、１×１０１１ｃｍ−３未満、または、１×１０１０ｃｍ−３未満であることが好ましい。また、チャネル形成領域のキャリア濃度の下限値については、特に限定は無いが、例えば、１×１０−９ｃｍ−３とすることができる。 The carrier concentration of the channel formation region is preferably 1×10 18 cm −3 or less, less than 1×10 17 cm −3 , less than 1×10 16 cm −3 , less than 1×10 15 cm −3 , less than 1×10 14 cm −3 , less than 1×10 13 cm −3 , less than 1×10 12 cm −3 , less than 1×10 11 cm −3 , or less than 1×10 10 cm −3 . The lower limit of the carrier concentration of the channel formation region is not particularly limited, but may be, for example, 1×10 −9 cm −3 .
　なお、酸化物２３０ｂのキャリア濃度を低くする場合においては、酸化物２３０ｂ中の不純物濃度を低くし、欠陥準位密度を低くする。本明細書等において、不純物濃度が低く、欠陥準位密度の低いことを高純度真性または実質的に高純度真性という。なお、キャリア濃度の低い酸化物半導体（または金属酸化物）を、高純度真性または実質的に高純度真性な酸化物半導体（または金属酸化物）と呼ぶ場合がある。 Note that when the carrier concentration of oxide 230b is reduced, the impurity concentration in oxide 230b is reduced to reduce the defect state density. In this specification and the like, a low impurity concentration and a low defect state density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).
　トランジスタ２００の電気特性を安定にするためには、酸化物２３０ｂ中の不純物濃度を低減することが有効である。また、酸化物２３０ｂの不純物濃度を低減するためには、近接する膜中の不純物濃度も低減することが好ましい。不純物としては、水素、窒素、アルカリ金属、アルカリ土類金属、鉄、ニッケル、シリコン等がある。なお、酸化物２３０ｂ中の不純物とは、例えば、酸化物２３０ｂを構成する主成分以外をいう。例えば、濃度が０．１原子％未満の元素は不純物といえる。 In order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the oxide 230b. In addition, in order to reduce the impurity concentration in the oxide 230b, it is preferable to also reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. Note that impurities in the oxide 230b refer to, for example, anything other than the main component that constitutes the oxide 230b. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.
　なお、チャネル形成領域、ソース領域、及び、ドレイン領域は、それぞれ、酸化物２３０ｂだけでなく、酸化物２３０ａまで形成されていてもよい。 The channel formation region, source region, and drain region may each be formed with oxide 230a as well as oxide 230b.
　また、酸化物２３０において、各領域の境界を明確に検出することが困難な場合がある。各領域内で検出される金属元素、並びに、水素、及び窒素などの不純物元素の濃度は、領域ごとの段階的な変化に限らず、各領域内でも連続的に変化していてもよい。つまり、チャネル形成領域に近い領域であるほど、金属元素、並びに、水素、及び窒素などの不純物元素の濃度が減少していてもよい。 Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not only vary stepwise from region to region, but may also vary continuously within each region. In other words, the closer a region is to the channel formation region, the lower the concentrations of metal elements and impurity elements such as hydrogen and nitrogen.
　酸化物２３０（酸化物２３０ａ及び酸化物２３０ｂ）には、半導体として機能する金属酸化物（以下、酸化物半導体ともいう）を用いることが好ましい。 It is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for oxide 230 (oxide 230a and oxide 230b).
　半導体として機能する金属酸化物のバンドギャップは、２ｅＶ以上が好ましく、２．５ｅＶ以上がより好ましい。バンドギャップの大きい金属酸化物を用いることで、トランジスタのオフ電流を低減できる。このように、チャネル形成領域に金属酸化物を有するトランジスタをＯＳトランジスタと呼ぶ。ＯＳトランジスタは、オフ電流が小さいため、半導体装置の消費電力を十分に低減できる。また、ＯＳトランジスタの周波数特性が高いため、半導体装置を高速に動作させることができる。 The band gap of a metal oxide that functions as a semiconductor is preferably 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a large band gap, the off-current of a transistor can be reduced. A transistor having a metal oxide in a channel formation region in this way is called an OS transistor. Since the off-current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, since the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.
　酸化物２３０は、金属酸化物（酸化物半導体）を有することが好ましい。酸化物２３０に用いることができる金属酸化物として、例えば、インジウム酸化物、ガリウム酸化物、及び亜鉛酸化物が挙げられる。金属酸化物は、少なくともインジウム（Ｉｎ）または亜鉛（Ｚｎ）を含むことが好ましい。また、金属酸化物は、インジウムと、元素Ｍと、亜鉛と、の中から選ばれる二または三を有することが好ましい。なお、元素Ｍは、酸素との結合エネルギーが高い金属元素又は半金属元素であり、例えば、酸素との結合エネルギーがインジウムよりも高い金属元素又は半金属元素である。元素Ｍとして、具体的には、アルミニウム、ガリウム、スズ、イットリウム、チタン、バナジウム、クロム、マンガン、鉄、コバルト、ニッケル、ジルコニウム、モリブデン、ハフニウム、タンタル、タングステン、ランタン、セリウム、ネオジム、マグネシウム、カルシウム、ストロンチウム、バリウム、ホウ素、シリコン、ゲルマニウム、及びアンチモンなどが挙げられる。金属酸化物が有する元素Ｍは、上記元素のいずれか一種または複数種であることが好ましく、アルミニウム、ガリウム、スズ、及びイットリウムから選ばれた一種または複数種であることがより好ましく、ガリウムがさらに好ましい。なお、本明細書等において、金属元素と半金属元素をまとめて「金属元素」と呼ぶことがあり、本明細書等に記載の「金属元素」には半金属元素が含まれることがある。 The oxide 230 preferably has a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the oxide 230 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably has two or three elements selected from indium, element M, and zinc. The element M is a metal element or semi-metal element that has a high bond energy with oxygen, for example, a metal element or semi-metal element that has a higher bond energy with oxygen than indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification may include metalloid elements.
　酸化物２３０は、例えば、インジウム亜鉛酸化物（Ｉｎ−Ｚｎ酸化物）、インジウムスズ酸化物（Ｉｎ−Ｓｎ酸化物）、インジウムチタン酸化物（Ｉｎ−Ｔｉ酸化物）、インジウムガリウム酸化物（Ｉｎ−Ｇａ酸化物）、インジウムガリウムアルミニウム酸化物（Ｉｎ−Ｇａ−Ａｌ酸化物）、インジウムガリウムスズ酸化物（Ｉｎ−Ｇａ−Ｓｎ酸化物）、ガリウム亜鉛酸化物（Ｇａ−Ｚｎ酸化物、ＧＺＯとも記す）、アルミニウム亜鉛酸化物（Ａｌ−Ｚｎ酸化物、ＡＺＯとも記す）、インジウムアルミニウム亜鉛酸化物（Ｉｎ−Ａｌ−Ｚｎ酸化物、ＩＡＺＯとも記す）、インジウムスズ亜鉛酸化物（Ｉｎ−Ｓｎ−Ｚｎ酸化物）、インジウムチタン亜鉛酸化物（Ｉｎ−Ｔｉ−Ｚｎ酸化物）、インジウムガリウム亜鉛酸化物（Ｉｎ−Ｇａ−Ｚｎ酸化物、ＩＧＺＯとも記す）、インジウムガリウムスズ亜鉛酸化物（Ｉｎ−Ｇａ−Ｓｎ−Ｚｎ酸化物、ＩＧＺＴＯとも記す）、インジウムガリウムアルミニウム亜鉛酸化物（Ｉｎ−Ｇａ−Ａｌ−Ｚｎ酸化物、ＩＧＡＺＯまたはＩＡＧＺＯとも記す）などを用いることができる。または、シリコンを含むインジウムスズ酸化物、ガリウムスズ酸化物（Ｇａ−Ｓｎ酸化物）、アルミニウムスズ酸化物（Ａｌ−Ｓｎ酸化物）などを用いることができる。 The oxide 230 may be, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (Al-Zn oxide, also written as AZO), indium aluminum oxide (Al-Zn oxide, also written as AZO), Indium zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.
　金属酸化物に含まれる全ての金属元素の原子数の和に対するインジウムの原子数の割合を高くすることにより、トランジスタの電界効果移動度を高めることができる。 By increasing the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements contained in the metal oxide, the field effect mobility of the transistor can be increased.
　なお、金属酸化物は、インジウムに代えて、又は、インジウムに加えて、周期番号が大きい金属元素の一種または複数種を有してもよい。金属元素の軌道の重なりが大きいほど、金属酸化物におけるキャリア伝導は大きくなる傾向がある。よって、周期番号が大きい金属元素を含むことで、トランジスタの電界効果移動度を高めることができる場合がある。周期番号が大きい金属元素として、第５周期に属する金属元素、及び第６周期に属する金属元素などが挙げられる。当該金属元素として、具体的には、イットリウム、ジルコニウム、銀、カドミウム、スズ、アンチモン、バリウム、鉛、ビスマス、ランタン、セリウム、プラセオジム、ネオジム、プロメチウム、サマリウム、及びユウロピウムなどが挙げられる。なお、ランタン、セリウム、プラセオジム、ネオジム、プロメチウム、サマリウム、及びユウロピウムは、軽希土類元素と呼ばれる。 Note that the metal oxide may contain one or more metal elements with a high periodic number instead of or in addition to indium. The greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element with a high periodic number, the field effect mobility of the transistor may be increased. Examples of metal elements with a high periodic number include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
　また、金属酸化物は、非金属元素の一種または複数種を有してもよい。金属酸化物が非金属元素を有することで、トランジスタの電界効果移動度を高めることができる場合がある。非金属元素として、例えば、炭素、窒素、リン、硫黄、セレン、フッ素、塩素、臭素、及び水素などが挙げられる。 The metal oxide may also contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the field effect mobility of the transistor may be increased. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
　また、金属酸化物に含まれる全ての金属元素の原子数の和に対する亜鉛の原子数の割合を高くすることにより、結晶性の高い金属酸化物となり、金属酸化物中の不純物の拡散を抑制できる。したがって、トランジスタの電気特性の変動が抑制され、信頼性を高めることができる。 In addition, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. This suppresses fluctuations in the electrical characteristics of the transistor, and increases its reliability.
　また、金属酸化物に含まれる全ての金属元素の原子数の和に対する元素Ｍの原子数の割合を高くすることにより、金属酸化物に酸素欠損が形成されるのを抑制できる。したがって、酸素欠損に起因するキャリア生成が抑制され、オフ電流の小さいトランジスタとすることができる。また、トランジスタの電気特性の変動が抑制され、信頼性を高めることができる。 In addition, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, and a transistor with a small off-current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
　前述したように、酸化物２３０に適用する金属酸化物の組成により、トランジスタの電気特性、及び信頼性が異なる。したがって、トランジスタに求められる電気特性、及び信頼性に応じて金属酸化物の組成を異ならせることにより、優れた電気特性と高い信頼性を両立した半導体装置とすることができる。 As mentioned above, the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for oxide 230. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that combines excellent electrical characteristics and high reliability can be obtained.
　酸化物２３０は、化学組成が異なる複数の酸化物層の積層構造を有することが好ましい。例えば、酸化物２３０ａに用いる金属酸化物において、主成分である金属元素に対する元素Ｍの原子数比が、酸化物２３０ｂに用いる金属酸化物における、主成分である金属元素に対する元素Ｍの原子数比より、大きいことが好ましい。また、酸化物２３０ａに用いる金属酸化物において、Ｉｎに対する元素Ｍの原子数比が、酸化物２３０ｂに用いる金属酸化物における、Ｉｎに対する元素Ｍの原子数比より大きいことが好ましい。当該構成にすることで、酸化物２３０ａよりも下方に形成された構造物からの、酸化物２３０ｂに対する、不純物及び酸素の拡散を抑制できる。 The oxide 230 preferably has a laminated structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used for the oxide 230a, the atomic ratio of element M to the main metal element is preferably greater than the atomic ratio of element M to the main metal element in the metal oxide used for the oxide 230b. Also, in the metal oxide used for the oxide 230a, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a to the oxide 230b.
　また、酸化物２３０ｂに用いる金属酸化物において、元素Ｍに対するＩｎの原子数比が、酸化物２３０ａに用いる金属酸化物における、元素Ｍに対するＩｎの原子数比より大きいことが好ましい。当該構成することで、トランジスタ２００は大きいオン電流、及び高い周波数特性を得ることができる。 Furthermore, in the metal oxide used for oxide 230b, it is preferable that the atomic ratio of In to element M is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a. With this configuration, the transistor 200 can obtain a large on-current and high frequency characteristics.
　また、酸化物２３０ａ及び酸化物２３０ｂが、酸素以外に共通の元素を主成分として有することで、酸化物２３０ａ及び酸化物２３０ｂの界面における欠陥準位密度を低減できる。酸化物２３０ａ及び酸化物２３０ｂの界面における欠陥準位密度を低減できる。そのため、界面散乱によるキャリア伝導への影響が小さくなり、トランジスタ２００は大きいオン電流、及び高い周波数特性を得ることができる。 Furthermore, since oxide 230a and oxide 230b have a common element other than oxygen as a main component, the defect state density at the interface between oxide 230a and oxide 230b can be reduced. The defect state density at the interface between oxide 230a and oxide 230b can be reduced. As a result, the effect of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.
　具体的には、酸化物２３０ａとして、Ｉｎ：Ｍ：Ｚｎ＝１：３：２［原子数比］もしくはその近傍の組成、Ｉｎ：Ｍ：Ｚｎ＝１：３：４［原子数比］もしくはその近傍の組成、Ｉｎ：Ｍ：Ｚｎ＝１：１：１［原子数比］もしくはその近傍の組成、またはＩｎ：Ｍ：Ｚｎ＝１：１：０．５［原子数比］もしくはその近傍の組成の金属酸化物を用いることができる。また、酸化物２３０ｂとして、Ｉｎ：Ｍ：Ｚｎ＝１：１：１［原子数比］もしくはその近傍の組成、Ｉｎ：Ｍ：Ｚｎ＝１：１：１．２［原子数比］もしくはその近傍の組成、Ｉｎ：Ｍ：Ｚｎ＝１：１：２［原子数比］もしくはその近傍の組成、Ｉｎ：Ｍ：Ｚｎ＝４：２：３［原子数比］もしくはその近傍の組成、または、元素Ｍを含まず、Ｉｎ：Ｚｎ＝４：１［原子数比］もしくはその近傍の組成の金属酸化物を用いることができる。なお、近傍の組成とは、所望の原子数比の±３０％の範囲を含む。また、元素Ｍとして、ガリウムを用いることが好ましい。また、酸化物２３０として酸化物２３０ｂの単層を設ける場合、酸化物２３０ｂとして、酸化物２３０ａに用いることができる金属酸化物を適用してもよい。また、酸化物２３０ａ、及び酸化物２３０ｂに用いることのできる金属酸化物の組成については、上記に限定されない。例えば、酸化物２３０ａに用いることのできる金属酸化物の組成は、酸化物２３０ｂに適用してもよい。同様に、酸化物２３０ｂに用いることのできる金属酸化物の組成は、酸化物２３０ａに適用してもよい。また、酸化物２３０ａ、および酸化物２３０ｂのいずれか一方または両方において、上記組成の金属酸化物を積層してもよい。 Specifically, the oxide 230a may be a metal oxide having a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, or In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto. The oxide 230b may be a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, or a metal oxide not including element M and having a composition of In:Zn=4:1 [atomic ratio] or a composition close thereto. The nearby composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M. When a single layer of the oxide 230b is provided as the oxide 230, the metal oxide that can be used for the oxide 230a may be applied as the oxide 230b. The composition of the metal oxide that can be used for the oxide 230a and the oxide 230b is not limited to the above. For example, the composition of the metal oxide that can be used for the oxide 230a may be applied to the oxide 230b. Similarly, the composition of the metal oxide that can be used for the oxide 230b may be applied to the oxide 230a. The metal oxide of the above composition may be stacked in either or both of the oxide 230a and the oxide 230b.
　なお、金属酸化物をスパッタリング法により成膜する場合、上記の原子数比は、成膜された金属酸化物の原子数比に限られず、金属酸化物の成膜に用いるスパッタリングターゲットの原子数比であってもよい。 When a metal oxide film is formed by sputtering, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of the sputtering target used to form the metal oxide film.
　酸化物２３０ｂは、結晶性を有することが好ましい。特に、酸化物２３０ｂとして、ＣＡＡＣ−ＯＳ（ｃ−ａｘｉｓ　ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）を用いることが好ましい。 The oxide 230b is preferably crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide 230b.
　ＣＡＡＣ−ＯＳは、結晶性の高い、緻密な構造を有しており、不純物及び欠陥（例えば、酸素欠損）が少ない金属酸化物である。特に、金属酸化物の形成後に、金属酸化物が多結晶化しない程度の温度（例えば、４００℃以上６００℃以下）で加熱処理することで、ＣＡＡＣ−ＯＳをより結晶性の高い、緻密な構造にすることができる。このようにして、ＣＡＡＣ−ＯＳの密度をより高めることで、当該ＣＡＡＣ−ＯＳ中の不純物または酸素の拡散をより低減することができる。 CAAC-OS is a metal oxide that has a highly crystalline and dense structure and has few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400°C or higher and 600°C or lower) at which the metal oxide does not become polycrystallized after the formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.
　また、ＣＡＡＣ−ＯＳは、明確な結晶粒界を確認することが難しいため、結晶粒界に起因する電子移動度の低下が起こりにくいといえる。したがって、ＣＡＡＣ−ＯＳを有する金属酸化物は、物理的性質が安定する。そのため、ＣＡＡＣ−ＯＳを有する金属酸化物は熱に強く、信頼性が高い。 In addition, since it is difficult to identify clear crystal boundaries in CAAC-OS, it can be said that the decrease in electron mobility caused by crystal boundaries is unlikely to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are resistant to heat and highly reliable.
　また、酸化物２３０ｂとしてＣＡＡＣ−ＯＳなどの結晶性を有する酸化物を用いることで、ソース電極またはドレイン電極による、酸化物２３０ｂからの酸素の引き抜きを抑制することができる。これにより、熱処理を行っても、酸化物２３０ｂから酸素が引き抜かれることを低減できるため、トランジスタ２００は、製造工程における高い温度（所謂サーマルバジェット）に対して安定である。 Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide 230b, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or drain electrode. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.
　酸化物半導体を用いたトランジスタは、酸化物半導体中のチャネルが形成される領域に不純物及び酸素欠損が存在すると、電気特性が変動しやすく、信頼性が悪くなる場合がある。また、酸素欠損近傍の水素が、酸素欠損に水素が入った欠陥（以下、ＶＯＨと呼ぶ場合がある）を形成し、キャリアとなる電子を生成する場合がある。このため、酸化物半導体中のチャネル形成領域に酸素欠損が含まれていると、トランジスタはノーマリーオン特性（ゲート電極に電圧を印加しなくてもチャネルが存在し、トランジスタに電流が流れる特性）となりやすい。したがって、酸化物半導体中のチャネル形成領域では、不純物、酸素欠損、及びＶＯＨはできる限り低減されていることが好ましい。言い換えると、酸化物半導体中のチャネル形成領域は、キャリア濃度が低減され、ｉ型（真性化）または実質的にｉ型であることが好ましい。 When impurities and oxygen vacancies are present in a region in which a channel is formed in the oxide semiconductor, the electrical characteristics of a transistor using an oxide semiconductor may fluctuate, and the reliability may be reduced. In addition, hydrogen near the oxygen vacancies may form a defect in which hydrogen is inserted into the oxygen vacancies (hereinafter, may be referred to as VOH ), and may generate electrons that serve as carriers. For this reason, when oxygen vacancies are present in the channel formation region in the oxide semiconductor, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and a current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, impurities, oxygen vacancies, and VOH are preferably reduced as much as possible in the channel formation region in the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor is reduced and the channel formation region in the oxide semiconductor is i-type (intrinsic) or substantially i-type.
　これに対して、酸化物半導体の近傍に、加熱により脱離する酸素（以下、過剰酸素と呼ぶ場合がある）を含む絶縁体を設け、熱処理を行うことで、当該絶縁体から酸化物半導体に酸素を供給し、酸素欠損、及びＶＯＨを低減することができる。ただし、ソース領域またはドレイン領域に過剰な量の酸素が供給されると、トランジスタ２００のオン電流の低下、または電界効果移動度の低下を引き起こすおそれがある。さらに、ソース領域またはドレイン領域に供給される酸素の量が基板面内でばらつくことで、トランジスタを有する半導体装置の特性にばらつきが出ることになる。また、当該絶縁体から酸化物半導体に供給する酸素が、ゲート電極、ソース電極、及びドレイン電極などの導電体に拡散すると、当該導電体が酸化してしまい、導電性が損なわれることなどにより、トランジスタの電気特性及び信頼性に悪影響を及ぼす場合がある。 In response to this, by providing an insulator containing oxygen that is desorbed by heating (hereinafter may be referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen can be supplied from the insulator to the oxide semiconductor, thereby reducing oxygen vacancies and VOH . However, when an excessive amount of oxygen is supplied to the source region or drain region, the on-current of the transistor 200 may be reduced or the field-effect mobility may be reduced. Furthermore, when the amount of oxygen supplied to the source region or drain region varies within the substrate surface, the characteristics of a semiconductor device including a transistor may vary. When oxygen supplied from the insulator to the oxide semiconductor diffuses to a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized and its conductivity may be impaired, which may adversely affect the electrical characteristics and reliability of the transistor.
　よって、酸化物半導体中において、チャネル形成領域は、キャリア濃度が低減され、ｉ型または実質的にｉ型であることが好ましいが、ソース領域及びドレイン領域は、キャリア濃度が高く、ｎ型であることが好ましい。つまり、酸化物半導体のチャネル形成領域の酸素欠損、及びＶＯＨを低減することが好ましい。また、ソース領域及びドレイン領域には過剰な量の酸素が供給されないようにすること、及びソース領域及びドレイン領域のＶＯＨの量が過剰に低減しないようにすることが好ましい。また、導電体２６０、導電体２４２ａ、及び導電体２４２ｂなどの導電率が低下することを抑制する構成にすることが好ましい。例えば、導電体２６０、導電体２４２ａ、及び導電体２４２ｂなどの酸化を抑制する構成にすることが好ましい。なお、酸化物半導体中の水素はＶＯＨを形成しうるため、ＶＯＨの量を低減するには、水素濃度を低減する必要がある。 Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the source and drain regions preferably have a high carrier concentration and are n-type. That is, it is preferable to reduce oxygen vacancies and VOH in the channel formation region of the oxide semiconductor. It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions and to prevent the amount of VOH in the source and drain regions from being excessively reduced. It is also preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor can form VOH , and therefore the hydrogen concentration needs to be reduced in order to reduce the amount of VOH .
　そこで、本実施の形態では、半導体装置において、チャネル形成領域の水素濃度を低減し、かつ、導電体２４２ａ、導電体２４２ｂ、及び導電体２６０の酸化を抑制し、かつ、ソース領域及びドレイン領域中の水素濃度が低減することを抑制する構成とする。 Therefore, in this embodiment, a semiconductor device is configured to reduce the hydrogen concentration in the channel formation region, suppress oxidation of conductor 242a, conductor 242b, and conductor 260, and suppress reduction in the hydrogen concentration in the source region and drain region.
　酸化物２３０ｂにおけるチャネル形成領域と接する絶縁体２５０は、水素を捕獲または水素を固着する機能を有することが好ましい。これにより、酸化物２３０ｂのチャネル形成領域中の水素濃度を低減できる。よって、チャネル形成領域中のＶＯＨを低減し、チャネル形成領域をｉ型または実質的にｉ型とすることができる。 The insulator 250 in contact with the channel formation region in the oxide 230b preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide 230b. As a result, VOH in the channel formation region can be reduced, and the channel formation region can be made i-type or substantially i-type.
　ここで、図２Ａに示すように、絶縁体２５０は、酸化物２３０に接する絶縁体２５０ａと、絶縁体２５０ａ上の絶縁体２５０ｂと、絶縁体２５０ｂ上の絶縁体２５０ｃと、絶縁体２５０ｃ上の絶縁体２５０ｄの積層構造とすることが好ましい。この場合、絶縁体２５０ａ及び絶縁体２５０ｃが水素を捕獲または水素を固着する機能を有することが好ましい。 Here, as shown in FIG. 2A, it is preferable that the insulator 250 has a layered structure of an insulator 250a in contact with the oxide 230, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c. In this case, it is preferable that the insulators 250a and 250c have the function of capturing hydrogen or fixing hydrogen.
　水素を捕獲または水素を固着する機能を有する絶縁体として、アモルファス構造を有する金属酸化物が挙げられる。絶縁体２５０ａ及び絶縁体２５０ｃとして、例えば、酸化マグネシウム、またはアルミニウム及びハフニウムの一方または双方を含む酸化物などの金属酸化物を用いることが好ましい。このようなアモルファス構造を有する金属酸化物では、酸素原子がダングリングボンドを有しており、当該ダングリングボンドで水素を捕獲または固着する性質を有する場合がある。つまり、アモルファス構造を有する金属酸化物は、水素を捕獲または固着する能力が高いといえる。 An example of an insulator that has the function of capturing or fixing hydrogen is a metal oxide having an amorphous structure. For example, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium as insulator 250a and insulator 250c. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. In other words, it can be said that metal oxides having an amorphous structure have a high ability to capture or fix hydrogen.
　また、絶縁体２５０ａ及び絶縁体２５０ｃに、高誘電率（ｈｉｇｈ−ｋ）材料を用いることが好ましい。なお、ｈｉｇｈ−ｋ材料の一例として、アルミニウム及びハフニウムの一方または双方を含む酸化物がある。絶縁体２５０ａ及び絶縁体２５０ｃとしてｈｉｇｈ−ｋ材料を用いることで、ゲート絶縁体の物理膜厚を保持したまま、トランジスタ動作時に印加するゲート電位の低減化が可能となる。また、ゲート絶縁体として機能する絶縁体の等価酸化膜厚（ＥＯＴ）の薄膜化が可能となる。 Furthermore, it is preferable to use a high dielectric constant (high-k) material for the insulator 250a and the insulator 250c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. By using a high-k material for the insulator 250a and the insulator 250c, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It is also possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.
　絶縁体２５０ａ及び絶縁体２５０ｃとして、アルミニウム及びハフニウムの一方または双方を含む酸化物を用いることが好ましく、アモルファス構造を有し、アルミニウム及びハフニウムの一方または双方を含む酸化物を用いることがより好ましい。 As the insulators 250a and 250c, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.
　本実施の形態では、絶縁体２５０ａとして、酸化アルミニウム膜を用いる。また、当該酸化アルミニウムは、アモルファス構造を有することが好ましい。ここで、酸化物２３０ｂに接して、絶縁体２５０ａを設けることにより、酸化物２３０ｂなどに含まれる水素を、より効果的に捕獲及び固着させることができる。 In this embodiment, an aluminum oxide film is used as the insulator 250a. The aluminum oxide preferably has an amorphous structure. By providing the insulator 250a in contact with the oxide 230b, the hydrogen contained in the oxide 230b can be captured and fixed more effectively.
　本実施の形態では、絶縁体２５０ｃとして、酸化ハフニウムを用いる。ここで、絶縁体２５０ｂと絶縁体２５０ｄの間に、絶縁体２５０ｃを設けることにより、絶縁体２５０ｂなどに含まれる水素を、より効果的に捕獲及び固着させることができる。 In this embodiment, hafnium oxide is used as the insulator 250c. Here, by providing the insulator 250c between the insulators 250b and 250d, the hydrogen contained in the insulators 250b and 250d can be captured and fixed more effectively.
　次に、絶縁体２５０ｂは、酸化シリコンまたは酸化窒化シリコンなどの、熱に対し安定な絶縁体を用いることが好ましい。なお、本明細書等において、酸化窒化物とは、その組成として、窒素よりも酸素の含有量が多い材料を指し、窒化酸化物とは、その組成として、酸素よりも窒素の含有量が多い材料を指す。例えば、酸化窒化シリコンと記載した場合は、その組成として窒素よりも酸素の含有量が多い材料を指し、窒化酸化シリコンと記載した場合は、その組成として、酸素よりも窒素の含有量が多い材料を示す。 Next, it is preferable to use a thermally stable insulator such as silicon oxide or silicon oxynitride for the insulator 250b. In this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.
　導電体２４２ａ、導電体２４２ｂ、及び導電体２６０の酸化を抑制するために、導電体２４２ａ、導電体２４２ｂ、及び導電体２６０それぞれの近傍に酸素に対するバリア絶縁体を設けることが好ましい。本実施の形態で説明する半導体装置において、当該絶縁体は、例えば、絶縁体２５０ａ、絶縁体２５０ｄ、絶縁体２５０ｃ、及び絶縁体２７５である。 In order to suppress oxidation of conductor 242a, conductor 242b, and conductor 260, it is preferable to provide a barrier insulator against oxygen near each of conductor 242a, conductor 242b, and conductor 260. In the semiconductor device described in this embodiment, the insulators are, for example, insulator 250a, insulator 250d, insulator 250c, and insulator 275.
　なお、本明細書等において、バリア絶縁体とは、バリア性を有する絶縁体のことを指す。本明細書等において、バリア性を有するとは、対応する物質の透過を妨げる性質（透過性が低いともいう）を有することを指す。例えば、バリア性を有する絶縁体は、対応する物質が当該絶縁体内部に拡散しにくい性質を有する。また例えば、バリア性を有する絶縁体は、対応する物質を、当該絶縁体内部で捕獲、または固着する（ゲッタリングともいう）機能を有する。 In this specification, a barrier insulator refers to an insulator that has barrier properties. In this specification, having barrier properties refers to having the property of preventing the penetration of the corresponding substance (also called low permeability). For example, an insulator with barrier properties has the property that the corresponding substance is unlikely to diffuse into the insulator. Also, for example, an insulator with barrier properties has the function of capturing or fixing the corresponding substance inside the insulator (also called gettering).
　酸素に対するバリア絶縁体としては、例えば、アルミニウム及びハフニウムの一方または双方を含む酸化物、酸化マグネシウム、酸化ガリウム、インジウムガリウム亜鉛酸化物、窒化シリコン、及び窒化酸化シリコンが挙げられる。また、アルミニウム及びハフニウムの一方または双方を含む酸化物として、例えば、酸化アルミニウム、酸化ハフニウム、アルミニウム及びハフニウムを含む酸化物（ハフニウムアルミネート）、並びに、ハフニウム及びシリコンを含む酸化物（ハフニウムシリケート）が挙げられる。例えば、絶縁体２５０ａ、絶縁体２５０ｃ、絶縁体２５０ｄ、及び絶縁体２７５はそれぞれ、上記酸素に対するバリア絶縁体の単層構造または積層構造であると好ましい。 Examples of the barrier insulator against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, it is preferable that the insulators 250a, 250c, 250d, and 275 each have a single-layer structure or a multilayer structure of the above-mentioned barrier insulator against oxygen.
　絶縁体２５０ａは、酸素に対するバリア性を有することが好ましい。絶縁体２５０ａは、少なくとも絶縁体２８０よりも酸素を透過しにくいことが好ましい。絶縁体２５０ａは、導電体２４２ａの側面、及び導電体２４２ｂの側面と接する領域を有する。絶縁体２５０ａが酸素に対するバリア性を有することで、導電体２４２ａ及び導電体２４２ｂの側面が酸化され、当該側面に酸化膜が形成されることを抑制できる。これにより、トランジスタ２００のオン電流の低下、または電界効果移動度の低下を抑制できる。 The insulator 250a preferably has a barrier property against oxygen. The insulator 250a is preferably at least less permeable to oxygen than the insulator 280. The insulator 250a has an area in contact with the side surface of the conductor 242a and the side surface of the conductor 242b. The insulator 250a having a barrier property against oxygen can suppress the side surfaces of the conductor 242a and the conductor 242b from being oxidized and forming an oxide film on the side surfaces. This can suppress a decrease in the on-current or a decrease in the field effect mobility of the transistor 200.
　また、絶縁体２５０ａは、酸化物２３０ｂの上面及び側面、酸化物２３０ａの側面、及び絶縁体２２２の上面に接して設けられる。絶縁体２５０ａが酸素に対するバリア性を有することで、熱処理などを行った際に、酸化物２３０ｂのチャネル形成領域から酸素が脱離することを抑制できる。よって、酸化物２３０ａ及び酸化物２３０ｂに酸素欠損が形成されることを低減できる。 Furthermore, the insulator 250a is provided in contact with the upper surface and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, and the upper surface of the insulator 222. Since the insulator 250a has a barrier property against oxygen, it is possible to suppress the desorption of oxygen from the channel formation region of the oxide 230b when a heat treatment or the like is performed. Therefore, it is possible to reduce the formation of oxygen vacancies in the oxide 230a and the oxide 230b.
　また、絶縁体２５０ａを設けることにより、絶縁体２８０から、酸化物２３０ａ及び酸化物２３０ｂに過剰な量の酸素が供給されることを抑制し、適量の酸素を酸化物２３０ａ及び酸化物２３０ｂに供給することができる。よって、ソース領域及びドレイン領域が過剰に酸化されることを防ぎ、トランジスタ２００のオン電流の低下、または電界効果移動度の低下を抑制できる。 Furthermore, by providing the insulator 250a, it is possible to prevent an excessive amount of oxygen from being supplied from the insulator 280 to the oxide 230a and the oxide 230b, and to supply an appropriate amount of oxygen to the oxide 230a and the oxide 230b. This prevents the source region and the drain region from being excessively oxidized, and suppresses a decrease in the on-current or a decrease in the field effect mobility of the transistor 200.
　アルミニウム及びハフニウムの一方または双方を含む酸化物は酸素に対するバリア性を有するため、絶縁体２５０ａとして好適に用いることができる。 Oxides containing either or both of aluminum and hafnium have barrier properties against oxygen, and are therefore suitable for use as the insulator 250a.
　絶縁体２５０ｄも、酸素に対するバリア性を有することが好ましい。絶縁体２５０ｄは酸化物２３０のチャネル形成領域と導電体２６０との間、及び絶縁体２８０と導電体２６０との間に設けられている。当該構成にすることで、酸化物２３０のチャネル形成領域に含まれる酸素が導電体２６０へ拡散し、酸化物２３０のチャネル形成領域に酸素欠損が形成されることを抑制できる。また、酸化物２３０に含まれる酸素及び絶縁体２８０に含まれる酸素が導電体２６０へ拡散し、導電体２６０が酸化することを抑制できる。絶縁体２５０ｄは、少なくとも絶縁体２８０よりも酸素を透過しにくいことが好ましい。例えば、絶縁体２５０ｄとして、窒化シリコン膜を用いることが好ましい。この場合、絶縁体２５０ｄは、少なくとも窒素と、シリコンと、を有する絶縁体となる。 The insulator 250d also preferably has a barrier property against oxygen. The insulator 250d is provided between the channel formation region of the oxide 230 and the conductor 260, and between the insulator 280 and the conductor 260. This configuration can suppress the oxygen contained in the channel formation region of the oxide 230 from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the oxide 230. In addition, it can suppress the oxygen contained in the oxide 230 and the oxygen contained in the insulator 280 from diffusing to the conductor 260 and oxidizing the conductor 260. The insulator 250d is preferably at least less permeable to oxygen than the insulator 280. For example, it is preferable to use a silicon nitride film as the insulator 250d. In this case, the insulator 250d is an insulator having at least nitrogen and silicon.
　また、絶縁体２５０ｄは、水素に対するバリア性を有することが好ましい。これにより、導電体２６０に含まれる水素などの不純物が、酸化物２３０ｂに拡散することを防ぐことができる。 In addition, it is preferable that the insulator 250d has a barrier property against hydrogen. This can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide 230b.
　絶縁体２７５も、酸素に対するバリア性を有することが好ましい。絶縁体２７５は、絶縁体２８０と導電体２４２ａとの間、及び、絶縁体２８０と導電体２４２ｂとの間に設けられている。絶縁体２７５は、導電体２４２の側面、酸化物２３０の側面、及び絶縁体２２２の上面に接して設けられる。当該構成にすることで、絶縁体２８０に含まれる酸素が、導電体２４２に拡散することを抑制できる。したがって、絶縁体２８０に含まれる酸素によって、導電体２４２が酸化されて抵抗率が増大することを抑制できる。絶縁体２７５は、少なくとも絶縁体２８０よりも酸素を透過しにくいことが好ましい。例えば、絶縁体２７５として、窒化シリコンを用いることが好ましい。この場合、絶縁体２７５は、少なくとも窒素と、シリコンと、を有する絶縁体となる。 The insulator 275 also preferably has a barrier property against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242a, and between the insulator 280 and the conductor 242b. The insulator 275 is provided in contact with the side of the conductor 242, the side of the oxide 230, and the upper surface of the insulator 222. This configuration can suppress the oxygen contained in the insulator 280 from diffusing into the conductor 242. Therefore, it is possible to suppress the conductor 242 from being oxidized by the oxygen contained in the insulator 280, which would increase the resistivity. The insulator 275 is preferably at least less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 275. In this case, the insulator 275 is an insulator having at least nitrogen and silicon.
　酸化物２３０におけるソース領域及びドレイン領域の水素濃度が低減することを抑制するために、ソース領域及びドレイン領域それぞれの近傍に水素に対するバリア絶縁体を設けることが好ましい。本実施の形態で説明する半導体装置において、当該水素に対するバリア絶縁体は、例えば、絶縁体２７５である。 In order to prevent the hydrogen concentration in the source and drain regions in the oxide 230 from decreasing, it is preferable to provide a barrier insulator against hydrogen near each of the source and drain regions. In the semiconductor device described in this embodiment, the barrier insulator against hydrogen is, for example, insulator 275.
　水素に対するバリア絶縁体として、酸化アルミニウム、酸化ハフニウム、酸化タンタルなどの酸化物、及び窒化シリコンなどの窒化物が挙げられる。例えば、絶縁体２７５は、上記水素に対するバリア絶縁体の単層構造または積層構造であると好ましい。 Examples of barrier insulators against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 is preferably a single-layer structure or a multilayer structure of the above-mentioned barrier insulators against hydrogen.
　上記のような絶縁体２７５を設けることで、ソース領域及びドレイン領域の水素が外部に拡散するのを低減することができるので、ソース領域及びドレイン領域の水素濃度が低減するのを抑制することができる。したがって、ソース領域及びドレイン領域をｎ型とすることができる。 By providing the insulator 275 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, and therefore to suppress the reduction in the hydrogen concentration in the source and drain regions. Therefore, the source and drain regions can be made n-type.
　上記構成にすることで、チャネル形成領域をｉ型または実質的にｉ型とし、ソース領域及びドレイン領域をｎ型とすることができ、良好な電気特性を有する半導体装置を提供できる。また、上記構成にすることで、半導体装置を微細化または高集積化しても良好な電気特性を有することができる。また、トランジスタ２００を微細化することで周波数特性を向上することができる。具体的には、遮断周波数を向上することができる。 By using the above configuration, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, and a semiconductor device with good electrical characteristics can be provided. Furthermore, by using the above configuration, the semiconductor device can have good electrical characteristics even when miniaturized or highly integrated. Furthermore, by miniaturizing the transistor 200, the frequency characteristics can be improved. Specifically, the cutoff frequency can be improved.
　絶縁体２５０ａ乃至絶縁体２５０ｄは、ゲート絶縁体の一部として機能する。絶縁体２５０ａ乃至絶縁体２５０ｄは、導電体２６０とともに、絶縁体２８０に形成された開口に設ける。トランジスタ２００の微細化を図るにあたって、絶縁体２５０ａ乃至絶縁体２５０ｄの膜厚はそれぞれ薄いことが好ましい。絶縁体２５０ａ乃至絶縁体２５０ｄの膜厚は、それぞれ、０．１ｎｍ以上１０ｎｍ以下が好ましく、０．１ｎｍ以上５．０ｎｍ以下がより好ましく、０．５ｎｍ以上５．０ｎｍ以下がより好ましく、１．０ｎｍ以上５．０ｎｍ未満がより好ましく、１．０ｎｍ以上３．０ｎｍ以下がさらに好ましい。なお、絶縁体２５０ａ乃至絶縁体２５０ｄは、それぞれ、少なくとも一部において、上記のような膜厚の領域を有していればよい。 The insulators 250a to 250d function as part of the gate insulator. The insulators 250a to 250d are provided in an opening formed in the insulator 280 together with the conductor 260. In order to miniaturize the transistor 200, it is preferable that the thicknesses of the insulators 250a to 250d are each thin. The thicknesses of the insulators 250a to 250d are each preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that it is sufficient that the insulators 250a to 250d each have a region with the above-mentioned thickness at least in a portion thereof.
　絶縁体２５０ａ乃至絶縁体２５０ｄの膜厚を上記のように薄くするためには、原子層堆積（ＡＬＤ：Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法を用いて成膜することが好ましい。また、絶縁体２８０等の開口内に、絶縁体２５０ａ乃至絶縁体２５０ｄを設けるには、ＡＬＤ法を用いて成膜することが好ましい。ＡＬＤ法は、プリカーサ及びリアクタントの反応を熱エネルギーのみで行う熱ＡＬＤ（Ｔｈｅｒｍａｌ　ＡＬＤ）法、プラズマ励起されたリアクタントを用いるＰＥＡＬＤ（Ｐｌａｓｍａ　Ｅｎｈａｎｃｅｄ　ＡＬＤ）法などがある。ＰＥＡＬＤ法では、プラズマを利用することで、より低温での成膜が可能となり好ましい場合がある。 In order to make the film thickness of the insulators 250a to 250d as described above thin, it is preferable to form the film using the atomic layer deposition (ALD) method. Also, to provide the insulators 250a to 250d in openings such as the insulator 280, it is preferable to form the film using the ALD method. The ALD method includes a thermal ALD method in which the reaction between the precursor and the reactant is carried out using only thermal energy, and a plasma enhanced ALD method in which a plasma excited reactant is used. In the PEALD method, the use of plasma allows film formation at a lower temperature, which may be preferable.
　ＡＬＤ法は、一層ずつ原子を堆積することができるため、極薄の成膜が可能、アスペクト比の高い構造への成膜が可能、ピンホールなどの欠陥の少ない成膜が可能、被覆性に優れた成膜が可能、低温での成膜が可能、などの効果がある。よって、絶縁体２５０を、絶縁体２８０に形成された開口部の側面、及び導電体２４２ａ、２４２ｂの側端部などに被覆性良く、上記のような薄い膜厚で成膜することができる。 The ALD method allows atoms to be deposited one layer at a time, which has the advantages of enabling extremely thin films to be formed, films to be formed on structures with high aspect ratios, films to be formed with fewer defects such as pinholes, films to be formed with excellent coverage, and films to be formed at low temperatures. Therefore, the insulator 250 can be formed with good coverage on the side surfaces of the opening formed in the insulator 280 and the side ends of the conductors 242a and 242b, and with a thin film thickness as described above.
　なお、ＡＬＤ法で用いるプリカーサには炭素などを含むものがある。このため、ＡＬＤ法により設けられた膜は、他の成膜法により設けられた膜と比較して、炭素などの不純物を多く含む場合がある。なお、不純物の定量は、二次イオン質量分析法（ＳＩＭＳ：Ｓｅｃｏｎｄａｒｙ　Ｉｏｎ　Ｍａｓｓ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）、Ｘ線光電子分光法（ＸＰＳ：Ｘ−ｒａｙ　Ｐｈｏｔｏｅｌｅｃｔｒｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ）、またはオージェ電子分光法（ＡＥＳ：Ａｕｇｅｒ　Ｅｌｅｃｔｒｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ）を用いて行うことができる。 Some of the precursors used in the ALD method contain carbon and other impurities. For this reason, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).
　なお、上記において、絶縁体２５０が、絶縁体２５０ａ乃至絶縁体２５０ｄの４層構造となる構成について説明したが、本発明はこれに限られるものではない。絶縁体２５０は、絶縁体２５０ａ乃至絶縁体２５０ｄのうち、少なくとも一つを有する構成にすることができる。絶縁体２５０を、絶縁体２５０ａ乃至絶縁体２５０ｄのうち、１層、２層または３層で構成することで、半導体装置の作製工程を簡略化し、生産性の向上を図ることができる。 Note that, although the insulator 250 has been described above as having a four-layer structure of insulators 250a to 250d, the present invention is not limited to this. The insulator 250 can have a structure including at least one of insulators 250a to 250d. By configuring the insulator 250 with one, two, or three layers of insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.
　例えば、図３Ａに示すように、絶縁体２５０を２層構造にする構成にしてもよい。この場合、絶縁体２５０を、絶縁体２５０ａと、絶縁体２５０ａ上の絶縁体２５０ｄの積層構造にすることが好ましい。絶縁体２５０ａ及び絶縁体２５０ｄの少なくとも一方にｈｉｇｈ−ｋ材料を用いることができる。これにより、絶縁体２５０ａ及び絶縁体２５０ｄをリーク電流が抑制される程度の膜厚に維持しながら、等価酸化膜厚（ＥＯＴ）の薄膜化が可能となる。 For example, as shown in FIG. 3A, the insulator 250 may have a two-layer structure. In this case, it is preferable that the insulator 250 has a laminated structure of an insulator 250a and an insulator 250d on the insulator 250a. A high-k material can be used for at least one of the insulators 250a and 250d. This makes it possible to reduce the equivalent oxide thickness (EOT) while maintaining the thickness of the insulators 250a and 250d at a level that suppresses leakage current.
　また、例えば、図３Ｂに示すように、絶縁体２５０を３層構造にする構成にしてもよい。この場合、絶縁体２５０を、絶縁体２５０ａと、絶縁体２５０ａ上の絶縁体２５０ｂと、絶縁体２５０ｂ上の絶縁体２５０ｄの積層構造にすることが好ましい。つまり、図３Ａに示す構成に、さらに絶縁体２５０ｂを設けた構成になる。 Also, for example, as shown in FIG. 3B, the insulator 250 may be configured to have a three-layer structure. In this case, it is preferable that the insulator 250 has a layered structure of insulator 250a, insulator 250b on insulator 250a, and insulator 250d on insulator 250b. In other words, the configuration shown in FIG. 3A is configured with an additional insulator 250b.
　また、本実施の形態では、半導体装置を、上記構成に加えて、水素がトランジスタ２００等に混入することを抑制する構成とすることが好ましい。例えば、水素の拡散を抑制する機能を有する絶縁体を、トランジスタ２００等の上下の一方または双方を覆うように設けることが好ましい。本実施の形態で説明する半導体装置において、当該絶縁体は、例えば、絶縁体２８３、絶縁体２８２、絶縁体２２２、及び絶縁体２２１などである。また、トランジスタ２００の下に設ける絶縁体２１５を、絶縁体２８２、及び絶縁体２８３のいずれか一方、または両方と同様の構成にしてもよい。この場合、絶縁体２１５を、絶縁体２８２と絶縁体２８３の積層構造にしてもよく、絶縁体２８２を下にし、絶縁体２８３を上にする構成にしてもよいし、絶縁体２８２を上にし、絶縁体２８３を下にする構成にしてもよい。 In addition to the above-mentioned structure, in this embodiment, the semiconductor device is preferably configured to suppress hydrogen from being mixed into the transistor 200 and the like. For example, it is preferable to provide an insulator having a function of suppressing hydrogen diffusion so as to cover one or both of the top and bottom of the transistor 200 and the like. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 283, the insulator 282, the insulator 222, the insulator 221, and the like. In addition, the insulator 215 provided under the transistor 200 may have a structure similar to either one or both of the insulators 282 and 283. In this case, the insulator 215 may have a stacked structure of the insulators 282 and 283, and may be configured to have the insulator 282 on the bottom and the insulator 283 on the top, or may be configured to have the insulator 282 on the top and the insulator 283 on the bottom.
　絶縁体２８３、絶縁体２８２、絶縁体２２２、及び絶縁体２２１のうち一つまたは複数は、水、水素などの不純物が、基板側から、または、トランジスタ２００等の上方からトランジスタ２００等に拡散することを抑制するバリア絶縁体として機能することが好ましい。したがって、絶縁体２８３、絶縁体２８２、絶縁体２２２、及び絶縁体２２１のうち一つまたは複数は、水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）、銅原子などの不純物の拡散を抑制する機能を有する（上記不純物が透過しにくい）絶縁性材料を有することが好ましい。または、酸素（例えば、酸素原子、及び酸素分子などの少なくとも一）の拡散を抑制する機能を有する（上記酸素が透過しにくい）絶縁性材料を有することが好ましい。 It is preferable that one or more of the insulators 283, 282, 222, and 221 function as a barrier insulator that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 to the transistor 200. Therefore, it is preferable that one or more of the insulators 283, 282, 222, and 221 have an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 , etc.), and copper atoms (through which the above impurities are difficult to permeate). Alternatively, it is preferable that the insulators have an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.) (through which the above oxygen is difficult to permeate).
　絶縁体２８３、絶縁体２８２、絶縁体２２２、及び絶縁体２２１は、それぞれ、水、水素などの不純物、及び酸素の拡散を抑制する機能を有する絶縁体を有することが好ましく、例えば、酸化アルミニウム、酸化マグネシウム、酸化ハフニウム、酸化ジルコニウム、アルミニウム及びハフニウムを含む酸化物（ハフニウムアルミネート）、ハフニウム及びジルコニウムを含む酸化物（ハフニウムジルコニウム酸化物）、酸化ガリウム、インジウムガリウム亜鉛酸化物、窒化シリコン、または窒化酸化シリコンなどを用いることができる。例えば、絶縁体２８３及び絶縁体２２１は、より水素バリア性が高い、窒化シリコンなどを用いることが好ましい。また、例えば、絶縁体２８２は、水素を捕獲または水素を固着する能力が高い、酸化アルミニウムなどを用いることが好ましい。また、例えば、絶縁体２２２は、水素を捕獲または水素を固着する能力が高く、高誘電率（ｈｉｇｈ−ｋ）材料である、酸化ハフニウムなどを用いることが好ましい。 The insulators 283, 282, 222, and 221 each preferably have an insulator that has a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen, and may be, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxide containing aluminum and hafnium (hafnium aluminate), oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide. For example, the insulators 283 and 221 are preferably made of silicon nitride, which has a higher hydrogen barrier property. For example, the insulator 282 is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen. For example, the insulator 222 is preferably made of hafnium oxide, which has a high ability to capture or fix hydrogen and is a high dielectric constant (high-k) material.
　このような構成にすることで、絶縁体２８３よりも上側に配置されている層間絶縁膜などから、水、水素などの不純物が、トランジスタ２００等に拡散することを抑制できる。また、絶縁体２２１よりも下側に配置されている層間絶縁膜などから、水、水素などの不純物が、トランジスタ２００等に拡散することを抑制できる。また、絶縁体２８０、及び絶縁体２５０等に含まれる水素を、絶縁体２８２または絶縁体２２２に、捕獲及び固着することができる。また、絶縁体２８２及び絶縁体２８３を設けることで、絶縁体２８０などに含まれる酸素が、トランジスタ２００等より上方に拡散することを抑制できる。また、絶縁体２２２及び絶縁体２２１を設けることで、酸化物２３０などに含まれる酸素が、トランジスタ２００等より下方に拡散することを抑制できる。このように、トランジスタ２００の上下を、水、水素などの不純物、及び酸素の拡散を抑制する機能を有する絶縁体で取り囲む構造にすることで、酸化物半導体に過剰な酸素及び水素が拡散するのを低減することができる。これにより、半導体装置の電気特性、及び信頼性の向上を図ることができる。 With this structure, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged above the insulator 283 to the transistor 200. Also, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged below the insulator 221 to the transistor 200. Also, hydrogen contained in the insulator 280 and the insulator 250 can be captured and fixed to the insulator 282 or the insulator 222. Furthermore, by providing the insulators 282 and 283, oxygen contained in the insulator 280 can be prevented from diffusing above the transistor 200. Also, by providing the insulators 222 and 221, oxygen contained in the oxide 230 can be prevented from diffusing below the transistor 200. In this way, by surrounding the top and bottom of the transistor 200 with insulators that have the function of preventing the diffusion of impurities such as water and hydrogen, and oxygen, the diffusion of excess oxygen and hydrogen to the oxide semiconductor can be reduced. This improves the electrical characteristics and reliability of the semiconductor device.
　さらに、絶縁体２７５及び絶縁体２５０ｄに、より水素バリア性が高い、窒化シリコンなどを用いることが好ましい。また、絶縁体２５０ａに、水素を捕獲または水素を固着する能力が高い、酸化アルミニウムなどを用いることが好ましい。また、絶縁体２５０ｃに、水素を捕獲または水素を固着する能力が高い、酸化ハフニウムなどを用いることが好ましい。 Furthermore, it is preferable to use silicon nitride, which has a higher hydrogen barrier property, for insulator 275 and insulator 250d. It is also preferable to use aluminum oxide, which has a higher ability to capture hydrogen or fix hydrogen, for insulator 250a. It is also preferable to use hafnium oxide, which has a higher ability to capture hydrogen or fix hydrogen, for insulator 250c.
　絶縁体２２５は、絶縁体２２２の上に接して形成される。絶縁体２２５は、図２Ｂ及び図４Ｂに示すように、チャネル幅方向の断面視において、高いアスペクト比の形状を有する。ここで、チャネル幅方向の断面視における、絶縁体２２５のアスペクト比は、絶縁体２２５のＡ３−Ａ４方向の長さＬ（絶縁体２２５の幅Ｌということもできる。）と、絶縁体２２５の被形成面（例えば絶縁体２２２）に垂直な方向の長さＨ（絶縁体２２５の高さＨということもできる。）の比のことを指す。絶縁体２２５において、絶縁体２２５の高さＨは、少なくとも絶縁体２２５の幅Ｌより長くなる。絶縁体２２５の高さＨは、絶縁体２２５の幅Ｌの１倍より大きく、好ましくは２倍以上、より好ましくは５倍以上、さらに好ましくは１０倍以上にすればよい。また、絶縁体２２５の高さＨは、絶縁体２２５の幅Ｌの２０倍以下が好ましい。 The insulator 225 is formed on and in contact with the insulator 222. As shown in FIG. 2B and FIG. 4B, the insulator 225 has a shape with a high aspect ratio in a cross-sectional view in the channel width direction. Here, the aspect ratio of the insulator 225 in a cross-sectional view in the channel width direction refers to the ratio of the length L of the insulator 225 in the A3-A4 direction (which can also be called the width L of the insulator 225) to the length H in a direction perpendicular to the surface on which the insulator 225 is formed (for example, the insulator 222) (which can also be called the height H of the insulator 225). In the insulator 225, the height H of the insulator 225 is at least longer than the width L of the insulator 225. The height H of the insulator 225 is greater than 1 time the width L of the insulator 225, preferably 2 times or more, more preferably 5 times or more, and even more preferably 10 times or more. In addition, the height H of the insulator 225 is preferably 20 times or less the width L of the insulator 225.
　このような高アスペクト比の絶縁体２２５を覆って、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２が設けられる。トランジスタ２００においては、図２Ｂに示すように、絶縁体２２５を挟んで二つ折りの状態になるように酸化物２３０ａ及び酸化物２３０ｂが設けられ、さらに酸化物２３０ｂを覆って絶縁体２５０、及び導電体２６０が設けられる。これにより、チャネル幅方向の断面視において、絶縁体２２５の上部、Ａ３側の側面、及びＡ４側の側面それぞれにおいて、酸化物２３０と導電体２６０が、絶縁体２５０を挟んで対向して設けられる。つまり、絶縁体２２５の上部、Ａ３側の側面、及びＡ４側の側面それぞれがチャネル形成領域として機能する。よって、絶縁体２２５を設けない場合と比較して、絶縁体２２５のＡ３側の側面、及びＡ４側の側面の分だけ、トランジスタ２００のチャネル幅が大きくなっている。 The oxide 230a, the oxide 230b, and the conductor 242 are provided to cover the insulator 225 having such a high aspect ratio. In the transistor 200, as shown in FIG. 2B, the oxide 230a and the oxide 230b are provided so as to sandwich the insulator 225 in a folded state, and the insulator 250 and the conductor 260 are further provided to cover the oxide 230b. As a result, in a cross-sectional view in the channel width direction, the oxide 230 and the conductor 260 are provided facing each other with the insulator 250 sandwiched between them on the upper part, the side surface on the A3 side, and the side surface on the A4 side of the insulator 225. In other words, the upper part, the side surface on the A3 side, and the side surface on the A4 side of the insulator 225 each function as a channel formation region. Therefore, compared to the case where the insulator 225 is not provided, the channel width of the transistor 200 is larger by the side surface on the A3 side and the side surface on the A4 side of the insulator 225.
　上記のようにチャネル幅が大きくなることで、トランジスタ２００のオン電流、電界効果移動度、周波数特性などを良好にすることができる。これにより、動作速度が速い半導体装置を提供することができる。また、当該半導体装置を用いた記憶装置の動作速度を速くすることができる。また、上記の構造では、絶縁体２２５を設けることにより、トランジスタ２００の占有面積を広げることなく、チャネル幅を大きくすることができる。これにより、半導体装置の微細化または高集積化を図ることができる。また、当該半導体装置を用いた記憶装置の記憶容量を大きくすることができる。 By increasing the channel width as described above, the on-state current, field effect mobility, frequency characteristics, and the like of the transistor 200 can be improved. This makes it possible to provide a semiconductor device with high operating speed. In addition, the operating speed of a memory device using the semiconductor device can be increased. In addition, in the above structure, by providing the insulator 225, the channel width can be increased without increasing the area occupied by the transistor 200. This makes it possible to miniaturize or highly integrate the semiconductor device. In addition, the memory capacity of a memory device using the semiconductor device can be increased.
　絶縁体２２５は、絶縁体２２２、絶縁体２８０、絶縁体２５０などに用いることができる絶縁性材料を用いればよい。また、絶縁体２２５は、高アスペクト比の形状を有するので、犠牲層（後述する絶縁体２２３）の側面にサイドウォール状に形成することが好ましい。よって、絶縁体２２５は被覆性の良好なＡＬＤ法を用いて形成することが好ましい。例えば、絶縁体２２５は、熱ＡＬＤ法で成膜した酸化ハフニウムを用いることができる。 The insulator 225 may be made of an insulating material that can be used for the insulators 222, 280, and 250. In addition, since the insulator 225 has a shape with a high aspect ratio, it is preferable to form it in a sidewall shape on the side of the sacrificial layer (insulator 223 described later). Therefore, it is preferable to form the insulator 225 using the ALD method, which has good coverage. For example, the insulator 225 may be made of hafnium oxide formed by the thermal ALD method.
　このように、犠牲層の側面に接してサイドウォール状に絶縁体２２５を形成することで、図１Ａなどに示すように、トランジスタ２００ａの絶縁体２２５と、トランジスタ２００ｂの絶縁体２２５と、を同時に形成することができる。このように、２個の絶縁体２２５を形成することで、犠牲層の大きさに合わせて、２個の絶縁体２２５の距離を設定することができる。よって、絶縁体２２５の距離を小さくし、トランジスタ２００ａ、及びトランジスタ２００ｂの占有面積を低減し、半導体装置の高集積化を図ることができる。 In this way, by forming the insulator 225 in a sidewall shape in contact with the side surface of the sacrificial layer, as shown in FIG. 1A, the insulator 225 of the transistor 200a and the insulator 225 of the transistor 200b can be formed simultaneously. By forming two insulators 225 in this way, the distance between the two insulators 225 can be set according to the size of the sacrificial layer. Therefore, the distance between the insulators 225 can be reduced, the area occupied by the transistors 200a and 200b can be reduced, and the semiconductor device can be highly integrated.
　ただし、絶縁体２２５は、厳密な意味で絶縁性材料のみに限定されるものではない。例えば、比較的絶縁性が高い金属酸化物などを用いることもできる。例えば、上記酸化物２３０ａに用いることが可能な金属酸化物などを用いてもよい。 However, the insulator 225 is not limited to insulating materials in the strict sense. For example, metal oxides with relatively high insulating properties may be used. For example, metal oxides that can be used for the oxide 230a may be used.
　また、絶縁体２２５の上部は、湾曲形状を有していてもよい。このような湾曲形状を有することで、絶縁体２２５の上部近傍において、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２に鬆などの欠陥が形成されるのを防ぐことができる。なお、図２Ｂ及び図４Ｂなどにおいては、絶縁体２２５上部のＡ３側（Ａ５側）と、Ａ４側（Ａ６側）の両方に、湾曲形状が設けられる、対称の構造にしているが、本発明はこれに限られるものではない。例えば、絶縁体２２５上部のＡ３側（Ａ５側）だけに、湾曲形状が設けられた、非対称の構造になる場合もある。 The upper part of the insulator 225 may have a curved shape. Such a curved shape can prevent defects such as voids from forming in the oxide 230a, the oxide 230b, and the conductor 242 near the upper part of the insulator 225. Note that in Figures 2B and 4B, a symmetrical structure is shown in which a curved shape is provided on both the A3 side (A5 side) and the A4 side (A6 side) of the upper part of the insulator 225, but the present invention is not limited to this. For example, an asymmetrical structure may be used in which a curved shape is provided only on the A3 side (A5 side) of the upper part of the insulator 225.
　また、図１Ａなどに示すように、絶縁体２２５をＡ１−Ａ２方向に延伸させる構造にしたが、本発明はこれに限られるものではない。例えば、図５Ａ乃至図５Ｄに示すように、絶縁体２２５を周状（枠状、または閉曲線状ということもできる。）に設ける構造にしてもよい。図５Ａは、上記半導体装置の上面図である。また、図５Ｂ乃至図５Ｄは、当該半導体装置の断面図である。ここで、図５Ｂは、図５ＡにＡ１−Ａ２の一点鎖線で示す部位の断面図である。また、図５Ｃは、図５ＡにＡ３−Ａ４の一点鎖線で示す部位の断面図である。また、図５Ｄは、図５ＡにＡ７−Ａ８の一点鎖線で示す部位の断面図である。なお、図５Ａの上面図では、図の明瞭化のために一部の要素を省いている。 As shown in FIG. 1A, the insulator 225 extends in the A1-A2 direction, but the present invention is not limited to this. For example, as shown in FIG. 5A to FIG. 5D, the insulator 225 may be provided in a circumferential shape (which may also be called a frame shape or a closed curve shape). FIG. 5A is a top view of the semiconductor device. Also, FIG. 5B to FIG. 5D are cross-sectional views of the semiconductor device. Here, FIG. 5B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 5A. Also, FIG. 5C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 5A. Also, FIG. 5D is a cross-sectional view of the portion indicated by the dashed line A7-A8 in FIG. 5A. Note that some elements are omitted from the top view of FIG. 5A for clarity.
　図５ＤのＡ７−Ａ８断面に示すように、トランジスタ２００ａとトランジスタ２００ｂで絶縁体２２５が一体物になっている。このため、トランジスタ２００ａとトランジスタ２００ｂの間で、絶縁体２７５が絶縁体２２５の上面に接する。上述の通り、絶縁体２２５は、犠牲層の側面に接してサイドウォール状に形成することが好ましい。図５Ａ乃至図５Ｄに示す半導体装置では、絶縁体２２５に囲まれた領域の中に犠牲層を設けることで、絶縁体２２５が形成される。 As shown in the A7-A8 cross section of FIG. 5D, the insulator 225 is integrated between the transistors 200a and 200b. Therefore, the insulator 275 contacts the top surface of the insulator 225 between the transistors 200a and 200b. As described above, the insulator 225 is preferably formed in a sidewall shape in contact with the side surface of the sacrificial layer. In the semiconductor device shown in FIG. 5A to FIG. 5D, the insulator 225 is formed by providing a sacrificial layer in the area surrounded by the insulator 225.
　トランジスタ２００において、導電体２０５は、酸化物２３０及び導電体２６０と重なるように配置する。ここで、導電体２０５は、絶縁体２１６に形成された開口部に埋め込まれて設けることが好ましい。また、導電体２０５は、図１Ａ及び図１Ｃに示すように、チャネル幅方向に延在して設けられることが好ましい。このような構成にすることで、複数のトランジスタを設ける場合に、導電体２０５は配線として機能する。 In the transistor 200, the conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. Also, the conductor 205 is preferably provided extending in the channel width direction as shown in Figures 1A and 1C. With this configuration, the conductor 205 functions as wiring when multiple transistors are provided.
　図１Ｂ及び図１Ｃに示すように、導電体２０５は、導電体２０５ａ及び導電体２０５ｂを有する事が好ましい。導電体２０５ａは、上記開口部の底面及び側壁に接して設けられる。導電体２０５ｂは、上記開口部に沿って形成された導電体２０５ａの凹部を埋め込むように設けられる。ここで、導電体２０５の上面の高さは、絶縁体２１６の上面の高さと一致または概略一致する。 As shown in Figures 1B and 1C, it is preferable that the conductor 205 has conductor 205a and conductor 205b. Conductor 205a is provided in contact with the bottom surface and side wall of the opening. Conductor 205b is provided so as to fill the recess of conductor 205a formed along the opening. Here, the height of the upper surface of conductor 205 coincides or approximately coincides with the height of the upper surface of insulator 216.
　ここで、導電体２０５ａは、水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）、銅原子などの不純物の拡散を抑制する機能を有する導電性材料を有することが好ましい。または、酸素（例えば、酸素原子、及び酸素分子などの少なくとも一）の拡散を抑制する機能を有する導電性材料を有することが好ましい。 Here, the conductor 205a preferably has a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules ( N2O , NO, NO2 , etc.), copper atoms, etc. Alternatively, it preferably has a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).
　導電体２０５ａに、水素の拡散を低減する機能を有する導電性材料を用いることにより、導電体２０５ｂに含まれる水素などの不純物が、絶縁体２１６等を介して、酸化物２３０に拡散することを防ぐことができる。また、導電体２０５ａに、酸素の拡散を抑制する機能を有する導電性材料を用いることにより、導電体２０５ｂが酸化して導電率が低下することを抑制できる。酸素の拡散を抑制する機能を有する導電性材料としては、例えば、チタン、窒化チタン、タンタル、窒化タンタル、ルテニウム、及び、酸化ルテニウムが挙げられる。導電体２０５ａは、上記導電性材料の単層構造または積層構造とすることができる。例えば、導電体２０５ａは、窒化チタンを有することが好ましい。 By using a conductive material having the function of reducing hydrogen diffusion for the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 216, etc. Also, by using a conductive material having the function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials having the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can have a single layer structure or a multilayer structure of the above conductive materials. For example, the conductor 205a preferably has titanium nitride.
　また、導電体２０５ｂは、タングステン、銅、またはアルミニウムを主成分とする導電性材料を用いることが好ましい。例えば、導電体２０５ｂは、タングステンを有することが好ましい。 Furthermore, it is preferable that the conductor 205b is made of a conductive material mainly composed of tungsten, copper, or aluminum. For example, it is preferable that the conductor 205b contains tungsten.
　導電体２０５は、第２のゲート電極として機能することができる。その場合、導電体２０５に印加する電位を、導電体２６０に印加する電位と連動させず、独立して変化させることで、トランジスタ２００のしきい値電圧（Ｖｔｈ）を制御することができる。特に、導電体２０５に負の電位を印加することにより、トランジスタ２００のＶｔｈをより大きくし、オフ電流を低減することが可能となる。したがって、導電体２０５に負の電位を印加したほうが、印加しない場合よりも、導電体２６０に印加する電位が０Ｖのときのドレイン電流を小さくすることができる。 The conductor 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.
　また、導電体２０５の電気抵抗率は、上記の導電体２０５に印加する電位を考慮して設計され、導電体２０５の膜厚は当該電気抵抗率に合わせて設定される。また、絶縁体２１６の膜厚は、導電体２０５とほぼ同じになる。ここで、導電体２０５の設計が許す範囲で導電体２０５及び絶縁体２１６の膜厚を薄くすることが好ましい。絶縁体２１６の膜厚を薄くすることで、絶縁体２１６中に含まれる水素などの不純物の絶対量を低減することができるため、当該不純物が酸化物２３０に拡散することを低減することができる。 The electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 as thin as possible within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, and therefore the diffusion of the impurities into the oxide 230 can be reduced.
　なお、上記において、導電体２０５ａと導電体２０５ｂの積層構造について示したが、本発明はこれに限られるものではなく、導電体２０５は、単層構造であってもよく、３層以上の積層構造であってもよい。例えば、導電体２０５を３層の積層構造にする場合、上記導電体２０５ａと導電体２０５ｂの積層構造でさらに、導電体２０５ｂの上に、導電体２０５ａと同様の材料を有する導電体を設ける構成にすることができる。このとき、導電体２０５ｂの上面が導電体２０５ａの最上部より低くなるようにして、導電体２０５ａと導電体２０５ｂで形成された凹部を埋め込むように、上記導電体を形成する構成にしてもよい。 Although the above describes a laminated structure of conductor 205a and conductor 205b, the present invention is not limited to this, and conductor 205 may have a single layer structure or a laminated structure of three or more layers. For example, when conductor 205 has a three-layer laminated structure, the laminated structure of conductor 205a and conductor 205b may further include a conductor having the same material as conductor 205a on conductor 205b. In this case, the conductor may be formed so that the top surface of conductor 205b is lower than the top of conductor 205a, and the recess formed by conductor 205a and conductor 205b is filled.
　また、本実施の形態の半導体装置は、図６Ａ乃至図６Ｄに示すように、導電体２０５を設けない構成にしてもよい。ここで、図２Ｂに示すように、トランジスタ２００において、酸化物２３０は、絶縁体２２５を介して二つ折りの構造になっている。よって、酸化物２３０に対して、絶縁体２２５を挟んで対向する位置の導電体２６０が、上記導電体２０５と同様の機能を奏する場合がある。このため、図６Ａ乃至図６Ｄに示すように、導電体２０５を設けなくても、導電体２６０の一部が第２のゲート電極として機能する場合がある。 The semiconductor device of this embodiment may be configured without providing the conductor 205, as shown in Figures 6A to 6D. Here, as shown in Figure 2B, in the transistor 200, the oxide 230 has a folded structure with the insulator 225 interposed therebetween. Therefore, the conductor 260 located opposite the oxide 230 across the insulator 225 may function similarly to the conductor 205. Therefore, as shown in Figures 6A to 6D, even if the conductor 205 is not provided, a part of the conductor 260 may function as a second gate electrode.
　導電体２４２ａ、導電体２４２ｂ、及び導電体２６０として、それぞれ、酸化しにくい導電性材料、または、酸素の拡散を抑制する機能を有する導電性材料を用いることが好ましい。当該導電性材料として、例えば、窒素を含む導電性材料、及び酸素を含む導電性材料が挙げられる。これにより、導電体２４２ａ、導電体２４２ｂ、及び導電体２６０の導電率が低下することを抑制できる。導電体２４２ａ、導電体２４２ｂ、及び導電体２６０として、金属及び窒素を含む導電性材料を用いる場合、導電体２４２ａ、導電体２４２ｂ、及び導電体２６０は、少なくとも金属と、窒素と、を有する導電体となる。 It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen as conductor 242a, conductor 242b, and conductor 260, respectively. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress a decrease in the conductivity of conductor 242a, conductor 242b, and conductor 260. When a conductive material containing metal and nitrogen is used as conductor 242a, conductor 242b, and conductor 260, conductor 242a, conductor 242b, and conductor 260 are conductors that contain at least metal and nitrogen.
　導電体２４２ａと導電体２４２ｂは互いに離隔して配置され、酸化物２３０ｂ上に接して設けられる。導電体２４２は、図４Ａ及び図４Ｂなどに示すように、アスペクト比が高い絶縁体２２５を覆うように設けられる。よって、導電体２４２は、ＡＬＤ法またはＣＶＤ法などの被覆性の良好な成膜法を用いて成膜することが好ましい。 The conductors 242a and 242b are disposed at a distance from each other and are provided on the oxide 230b in contact with each other. As shown in Figures 4A and 4B, the conductor 242 is provided so as to cover the insulator 225, which has a high aspect ratio. Therefore, it is preferable to form the conductor 242 using a film formation method with good coverage, such as the ALD method or the CVD method.
　ここで、トランジスタ２００ａのソースまたはドレイン近傍においては、図４Ｂに示すように、絶縁体２２５を挟んで二つ折りの状態になるように、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２ａが設けられる。これにより、チャネル幅方向の断面視において、絶縁体２２５の上部、Ａ５側の側面、及びＡ６側の側面それぞれにおいて、導電体２４２ａが、酸化物２３０ｂに接する。よって、絶縁体２２５を設けない場合と比較して、絶縁体２２５のＡ５側の側面、及びＡ６側の側面の分だけ、導電体２４２ａと酸化物２３０ｂの接触面積が大きくなっている。なお、図４Ｂにおいては、導電体２４２ａの近傍を示したが、導電体２４２ｂについても同様である。つまり、上述の導電体２４２ａと酸化物２３０ｂと同様に、導電体２４２ｂと酸化物２３０ｂの接触面積が大きくなっている。 Here, in the vicinity of the source or drain of the transistor 200a, as shown in FIG. 4B, the oxide 230a, the oxide 230b, and the conductor 242a are provided so as to be folded in half with the insulator 225 sandwiched therebetween. As a result, in a cross-sectional view in the channel width direction, the conductor 242a contacts the oxide 230b at the top, the side surface on the A5 side, and the side surface on the A6 side of the insulator 225. Therefore, compared to the case where the insulator 225 is not provided, the contact area between the conductor 242a and the oxide 230b is larger by the amount of the side surface on the A5 side and the side surface on the A6 side of the insulator 225. Note that while FIG. 4B shows the vicinity of the conductor 242a, the same is true for the conductor 242b. In other words, the contact area between the conductor 242b and the oxide 230b is larger, similar to the above-mentioned conductor 242a and the oxide 230b.
　上記のように導電体２４２と酸化物２３０ｂの接触面積が大きくなることで、トランジスタ２００の占有面積を広げることなく、トランジスタ２００のオン電流、周波数特性などを良好にすることができる。これにより、動作速度が速い半導体装置を提供することができる。また、当該半導体装置を用いた記憶装置の動作速度を速くすることができる。また、これにより、半導体装置の微細化または高集積化を図ることができる。また、当該半導体装置を用いた記憶装置の記憶容量を大きくすることができる。 By increasing the contact area between the conductor 242 and the oxide 230b as described above, the on-current, frequency characteristics, and the like of the transistor 200 can be improved without increasing the area occupied by the transistor 200. This makes it possible to provide a semiconductor device with a high operating speed. In addition, the operating speed of a memory device using the semiconductor device can be increased. This also makes it possible to miniaturize or highly integrate the semiconductor device. In addition, the memory capacity of a memory device using the semiconductor device can be increased.
　導電体２４２ａと導電体２４２ｂは、酸化物２３０ｂに接するので、酸化しにくい導電性材料、または、酸素の拡散を抑制する機能を有する導電性材料を用いることが好ましい。これにより、導電体２４２ａ、２４２ｂの導電率が低下することを抑制できる。また、酸化物２３０ｂから酸素が引き抜かれ、過剰な量の酸素欠損が形成されるのを抑制できる。また、導電体２４２ａ、２４２ｂとして、水素を吸い取りやすい（抜き取りやすい）材料を用いると、酸化物２３０の水素濃度を低減でき、好ましい。 Because conductors 242a and 242b are in contact with oxide 230b, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen. This can suppress a decrease in the conductivity of conductors 242a and 242b. It can also suppress the extraction of oxygen from oxide 230b, which would result in the formation of an excessive amount of oxygen vacancy. It is also preferable to use a material that easily absorbs (extracts) hydrogen as conductors 242a and 242b, as this can reduce the hydrogen concentration in oxide 230.
　導電体２４２としては、金属窒化物を用いることが好ましく、例えば、タンタルを含む窒化物、チタンを含む窒化物、モリブデンを含む窒化物、タングステンを含む窒化物、タンタル及びアルミニウムを含む窒化物、チタン及びアルミニウムを含む窒化物などを用いることが好ましい。本発明の一態様においては、タンタルを含む窒化物が特に好ましい。また、例えば、ルテニウム、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物などを用いてもよい。これらの材料は、酸化しにくい導電性材料、または、酸素を吸収しても導電性を維持する材料であるため、好ましい。 As the conductor 242, it is preferable to use a metal nitride, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one aspect of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.
　なお、酸化物２３０ｂなどに含まれる水素が、導電体２４２ａまたは導電体２４２ｂに拡散する場合がある。特に、導電体２４２ａ及び導電体２４２ｂに、タンタルを含む窒化物を用いることで、酸化物２３０ｂなどに含まれる水素は、導電体２４２ａまたは導電体２４２ｂに拡散しやすく、拡散した水素は、導電体２４２ａまたは導電体２４２ｂが有する窒素と結合することがある。つまり、酸化物２３０ｂなどに含まれる水素は、導電体２４２ａまたは導電体２４２ｂに吸い取られる場合がある。 Note that hydrogen contained in oxide 230b etc. may diffuse into conductor 242a or conductor 242b. In particular, by using a nitride containing tantalum for conductor 242a and conductor 242b, hydrogen contained in oxide 230b etc. is more likely to diffuse into conductor 242a or conductor 242b, and the diffused hydrogen may combine with nitrogen contained in conductor 242a or conductor 242b. In other words, hydrogen contained in oxide 230b etc. may be absorbed by conductor 242a or conductor 242b.
　また、導電体２４２ａ及び導電体２４２ｂの導電率が低下することを抑制するために、酸化物２３０ｂとして、ＣＡＡＣ−ＯＳなどの結晶性を有する酸化物を用いることが好ましい。特に、インジウムと、亜鉛と、ガリウム、アルミニウム、及び錫から選ばれる一または複数と、を有する金属酸化物を用いることが好ましい。ＣＡＡＣ−ＯＳを用いることで、導電体２４２ａまたは導電体２４２ｂによる、酸化物２３０ｂからの酸素の引き抜きを抑制できる。また、導電体２４２ａ及び導電体２４２ｂの導電率が低下することを抑制できる。 Furthermore, in order to suppress a decrease in the conductivity of the conductor 242a and the conductor 242b, it is preferable to use a crystalline oxide such as CAAC-OS as the oxide 230b. In particular, it is preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. By using CAAC-OS, it is possible to suppress the extraction of oxygen from the oxide 230b by the conductor 242a or the conductor 242b. It is also possible to suppress a decrease in the conductivity of the conductor 242a and the conductor 242b.
　また、図３Ｃに示すように、導電体２４２ａ、２４２ｂを２層構造にしてもよい。導電体２４２ａを、導電体２４２ａ１と導電体２４２ａ１上の導電体２４２ａ２の積層膜とし、導電体２４２ｂを、導電体２４２ｂ１と導電体２４２ｂ１上の導電体２４２ｂ２の積層膜とすることができる。このとき、酸化物２３０ｂに接する層（導電体２４２ａ１及び導電体２４２ｂ１）として、上述の酸化しにくい導電性材料、または、酸素の拡散を抑制する機能を有する導電性材料を用いることが好ましい。これにより、導電体２４２ａ、２４２ｂの導電率が低下することを抑制できる。また、酸化物２３０ｂから酸素が引き抜かれ、過剰な量の酸素欠損が形成されるのを抑制できる。また、酸化物２３０ｂに接する層（導電体２４２ａ１及び導電体２４２ｂ１）として、水素を吸い取りやすい（抜き取りやすい）材料を用いると、酸化物２３０の水素濃度を低減でき、好ましい。 Also, as shown in FIG. 3C, the conductors 242a and 242b may have a two-layer structure. The conductor 242a may be a laminated film of the conductor 242a1 and the conductor 242a2 on the conductor 242a1, and the conductor 242b may be a laminated film of the conductor 242b1 and the conductor 242b2 on the conductor 242b1. In this case, it is preferable to use the above-mentioned conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen as the layer in contact with the oxide 230b (the conductor 242a1 and the conductor 242b1). This can suppress the decrease in the conductivity of the conductors 242a and 242b. In addition, it can suppress the extraction of oxygen from the oxide 230b, which can suppress the formation of an excessive amount of oxygen vacancy. In addition, it is preferable to use a material that easily absorbs (removes) hydrogen as the layer in contact with the oxide 230b (conductor 242a1 and conductor 242b1), as this can reduce the hydrogen concentration in the oxide 230.
　また、導電体２４２ａ２及び導電体２４２ｂ２は、導電体２４２ａ１及び導電体２４２ｂ１よりも、導電性が高いことが好ましい。例えば、導電体２４２ａ２及び導電体２４２ｂ２の膜厚を、導電体２４２ａ１及び導電体２４２ｂ１の膜厚より大きくすることが好ましい。導電体２４２ａ２及び導電体２４２ｂ２としては、上記導電体２０５ｂに用いることが可能な導電体を用いればよい。上記のような構造にすることで、導電体２４２ａ２及び導電体２４２ｂ２の抵抗を低減することができる。これにより、トランジスタ２００のオン電流を大きくし、本実施の形態に係る半導体装置の動作速度の向上を図ることができる。 Furthermore, it is preferable that conductor 242a2 and conductor 242b2 have higher conductivity than conductor 242a1 and conductor 242b1. For example, it is preferable that the film thickness of conductor 242a2 and conductor 242b2 is larger than the film thickness of conductor 242a1 and conductor 242b1. Conductors that can be used for conductor 205b may be used as conductor 242a2 and conductor 242b2. By using the above structure, it is possible to reduce the resistance of conductor 242a2 and conductor 242b2. This increases the on-current of transistor 200, and improves the operating speed of the semiconductor device according to this embodiment.
　例えば、導電体２４２ａ１及び導電体２４２ｂ１として、窒化タンタルまたは窒化チタンを用い、導電体２４２ａ２及び導電体２４２ｂ２として、タングステンを用いることができる。 For example, tantalum nitride or titanium nitride can be used as the conductor 242a1 and the conductor 242b1, and tungsten can be used as the conductor 242a2 and the conductor 242b2.
　さらに、図３Ｃに示すように、導電体２４２ａ２、導電体２４２ｂ２、絶縁体２７５、及び絶縁体２８０と、絶縁体２５０の間に、絶縁体２５５を設けることが好ましい。絶縁体２５５は、絶縁体２８０等に形成された開口の中に配置され、絶縁体２８０の側面、絶縁体２７５の側面、導電体２４２ａ２の側面、導電体２４２ｂ２の側面、導電体２４２ａ１の上面、及び導電体２４２ｂ１の上面に接する。言い換えると、絶縁体２５５は、絶縁体２８０等に形成された開口の側壁に接して形成されている。すなわち、絶縁体２５５は、サイドウォール絶縁膜ということもできる。 Furthermore, as shown in FIG. 3C, it is preferable to provide an insulator 255 between the conductor 242a2, the conductor 242b2, the insulator 275, and the insulator 280 and the insulator 250. The insulator 255 is disposed in an opening formed in the insulator 280, etc., and contacts the side of the insulator 280, the side of the insulator 275, the side of the conductor 242a2, the side of the conductor 242b2, the top surface of the conductor 242a1, and the top surface of the conductor 242b1. In other words, the insulator 255 is formed in contact with the side wall of the opening formed in the insulator 280, etc. That is, the insulator 255 can also be called a sidewall insulating film.
　絶縁体２５５は、導電体２４２ａ２の側面、及び導電体２４２ｂ２の側面に接して形成されており、導電体２４２ａ２、及び導電体２４２ｂ２を保護する無機絶縁体である。絶縁体２５５は、酸化雰囲気に曝されるので、酸化されにくい無機絶縁体が好ましい。また、絶縁体２５５は、導電体２４２ａ２及び導電体２４２ｂ２に接するので、導電体２４２ａ２、２４２ｂ２を酸化させにくい、無機絶縁体であることが好ましい。よって、絶縁体２５５は、酸素に対するバリア性を有する絶縁体２５０ｄに用いることが可能な絶縁性材料を用いることが好ましい。例えば、絶縁体２５５として、窒化シリコンを用いることができる。 The insulator 255 is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, and is an inorganic insulator that protects the conductor 242a2 and the conductor 242b2. Since the insulator 255 is exposed to an oxidizing atmosphere, it is preferable that the insulator 255 is an inorganic insulator that is not easily oxidized. Furthermore, since the insulator 255 is in contact with the conductor 242a2 and the conductor 242b2, it is preferable that the insulator 255 is an inorganic insulator that is not easily oxidized. Therefore, it is preferable that the insulator 255 is made of an insulating material that can be used for the insulator 250d that has a barrier property against oxygen. For example, silicon nitride can be used as the insulator 255.
　このような絶縁体２５５を用いることで、導電体２４２ａ１と導電体２４２ｂ１を分断した後で、絶縁体２５０を成膜する前に酸素を含む雰囲気で熱処理を行っても、導電体２４２ａ２及び導電体２４２ｂ２が過剰に酸化されるのを防ぐことができる。 By using such an insulator 255, even if a heat treatment is performed in an oxygen-containing atmosphere after separating the conductor 242a1 and the conductor 242b1 and before forming the insulator 250, excessive oxidation of the conductor 242a2 and the conductor 242b2 can be prevented.
　なお、図３Ｃにおいて、絶縁体２５５の上端と絶縁体２８０の上面、絶縁体２５０の上端、及び導電体２６０の上端が概略一致する構造を示したが、本実施の形態はこれに限られるものではない。絶縁体２５５は、導電体２４２ａ２の側面、及び導電体２４２ｂ２の側面を覆う構造になっていればよい。例えば、絶縁体２５５の上端が、絶縁体２８０の上面より低く、絶縁体２７５の上面より高い構造にしてもよい。 3C shows a structure in which the upper end of insulator 255 roughly coincides with the upper surface of insulator 280, the upper end of insulator 250, and the upper end of conductor 260, but this embodiment is not limited to this. Insulator 255 may be structured to cover the side surface of conductor 242a2 and the side surface of conductor 242b2. For example, the upper end of insulator 255 may be structured to be lower than the upper surface of insulator 280 and higher than the upper surface of insulator 275.
　また、図３Ｃに示すように、トランジスタ２００のチャネル長方向の断面視において、導電体２４２ａ１と導電体２４２ｂ１の間の距離は、導電体２４２ａ２と導電体２４２ｂ２の間の距離より小さい。具体的には、上記の距離の差は、絶縁体２５５の膜厚の２倍と一致または概略一致する。ここで、絶縁体２５５の膜厚とは、絶縁体２５５の少なくとも一部における、Ａ１−Ａ２方向の膜厚を指す。このような構成にすることで、ソースとドレインの間の距離をより短くし、それに応じてチャネル長を短くすることが可能になる。よって、トランジスタ２００の周波数特性を向上させることができる。このように、半導体装置の微細化を図ることで、動作速度の向上した半導体装置を提供することができる。 Also, as shown in FIG. 3C, in a cross-sectional view of the transistor 200 in the channel length direction, the distance between the conductor 242a1 and the conductor 242b1 is smaller than the distance between the conductor 242a2 and the conductor 242b2. Specifically, the difference in distance is equal to or approximately equal to twice the film thickness of the insulator 255. Here, the film thickness of the insulator 255 refers to the film thickness in the A1-A2 direction of at least a portion of the insulator 255. With this configuration, it is possible to further shorten the distance between the source and the drain, and accordingly shorten the channel length. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.
　導電体２６０は、図１Ｂ及び図１Ｃに示すように、絶縁体２８０、絶縁体２７５、導電体２４２ａ、及び導電体２４２ｂに形成された開口内に配置される。導電体２６０は、当該開口内において、絶縁体２５０を介して、絶縁体２２２の上面、酸化物２３０ａの側面、酸化物２３０ｂの側面、及び酸化物２３０ｂの上面を覆うように設けられる。また、導電体２６０の上面は、絶縁体２５０の最上部、及び絶縁体２８０の上面と高さが一致または概略一致するように配置される。 As shown in Figures 1B and 1C, conductor 260 is disposed in an opening formed in insulator 280, insulator 275, conductor 242a, and conductor 242b. Conductor 260 is disposed in the opening so as to cover the upper surface of insulator 222, the side of oxide 230a, the side of oxide 230b, and the upper surface of oxide 230b via insulator 250. In addition, the upper surface of conductor 260 is disposed so as to be flush or approximately flush with the top of insulator 250 and the upper surface of insulator 280.
　なお、導電体２６０及び絶縁体２５０が配置された、上記開口において、当該開口の側壁は、絶縁体２２２の上面に対して垂直または概略垂直であってもよく、テーパー形状であってもよい。側壁をテーパー形状にすることで、絶縁体２８０の開口に設けられる、絶縁体２５０などの被覆性が向上し、鬆などの欠陥を低減できる。 In addition, in the above opening in which the conductor 260 and the insulator 250 are disposed, the sidewall of the opening may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may be tapered. By making the sidewall tapered, the coverage of the insulator 250 and the like provided in the opening of the insulator 280 is improved, and defects such as voids can be reduced.
　導電体２６０は、トランジスタ２００の第１のゲート電極として機能する。ここで、導電体２６０は、図１Ａ、及び図１Ｃに示すように、チャネル幅方向に延在して設けられることが好ましい。このような構成にすることで、複数のトランジスタを設ける場合に、導電体２６０は配線として機能する。 The conductor 260 functions as a first gate electrode of the transistor 200. Here, the conductor 260 is preferably provided extending in the channel width direction, as shown in Figures 1A and 1C. With this configuration, the conductor 260 functions as wiring when multiple transistors are provided.
　なお、本明細書等において、少なくとも第１のゲート電極の電界によって、チャネル形成領域を電気的に取り囲むトランジスタの構造を、ｓｕｒｒｏｕｎｄｅｄ　ｃｈａｎｎｅｌ（Ｓ−ｃｈａｎｎｅｌ）構造とよぶ。また、本明細書等で開示するＳ−ｃｈａｎｎｅｌ構造は、Ｆｉｎ型構造およびプレーナ型構造とは異なる構造を有する。一方で、本明細書等で開示するＳ−ｃｈａｎｎｅｌ構造は、Ｆｉｎ型構造の一種として捉えることも可能である。なお、本明細書等において、Ｆｉｎ型構造とは、ゲート電極が少なくともチャネルの２面以上（具体的には、２面、３面、または４面等）を包むように配置される構造を示す。Ｆｉｎ型構造、およびＳ−ｃｈａｎｎｅｌ構造を採用することで、短チャネル効果に対する耐性を高める、別言すると短チャネル効果が発生し難いトランジスタとすることができる。 In this specification, the transistor structure in which the electric field of at least the first gate electrode electrically surrounds the channel formation region is called a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification has a structure different from the Fin type structure and the planar type structure. On the other hand, the S-channel structure disclosed in this specification can also be considered as a type of Fin type structure. In this specification, the Fin type structure refers to a structure in which the gate electrode is arranged to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By adopting the Fin type structure and the S-channel structure, it is possible to increase the resistance to the short channel effect, in other words to make a transistor in which the short channel effect is less likely to occur.
　トランジスタ２００を、上記のＳ−ｃｈａｎｎｅｌ構造とすることで、チャネル形成領域を電気的に取り囲むことができる。なお、Ｓ−ｃｈａｎｎｅｌ構造は、チャネル形成領域を電気的に取り囲んでいる構造であるため、実質的にＧＡＡ（Ｇａｔｅ　Ａｌｌ　Ａｒｏｕｎｄ）構造、またはＬＧＡＡ（Ｌａｔｅｒａｌ　Ｇａｔｅ　Ａｌｌ　Ａｒｏｕｎｄ）構造と、同等の構造であるともいえる。トランジスタ２００をＳ−ｃｈａｎｎｅｌ構造、ＧＡＡ構造、又はＬＧＡＡ構造とすることで、酸化物２３０とゲート絶縁体との界面又は界面近傍に形成されるチャネル形成領域を、酸化物２３０のバルク全体とすることができる。したがって、トランジスタに流れる電流密度を向上させることが可能となるため、トランジスタのオン電流の向上、またはトランジスタの電界効果移動度を高めることが期待できる。 By making the transistor 200 have the above-mentioned S-channel structure, the channel formation region can be electrically surrounded. Since the S-channel structure electrically surrounds the channel formation region, it can be said that it is substantially the same structure as a GAA (Gate All Around) structure or a LGAA (Lateral Gate All Around) structure. By making the transistor 200 have an S-channel structure, a GAA structure, or a LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be the entire bulk of the oxide 230. Therefore, it is possible to improve the current density flowing through the transistor, and it is expected that the on-current of the transistor or the field effect mobility of the transistor can be improved.
　図１Ｂなどでは、導電体２６０を２層構造で示す。ここで、導電体２６０は、導電体２６０ａと、導電体２６０ａの上に配置された導電体２６０ｂと、を有することが好ましい。例えば、導電体２６０ａは、導電体２６０ｂの底面及び側面を包むように配置されることが好ましい。このとき、導電体２６０ａとして、酸化しにくい導電性材料、または、酸素の拡散を抑制する機能を有する導電性材料を用いることが好ましい。 In FIG. 1B and other figures, conductor 260 is shown as having a two-layer structure. Here, conductor 260 preferably has conductor 260a and conductor 260b arranged on conductor 260a. For example, conductor 260a is preferably arranged so as to wrap around the bottom and side surfaces of conductor 260b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen as conductor 260a.
　導電体２６０ａは、水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子、銅原子などの不純物の拡散を抑制する機能を有する導電性材料を用いることが好ましい。または、酸素（例えば、酸素原子、及び酸素分子などの少なくとも一）の拡散を抑制する機能を有する導電性材料を用いることが好ましい。 The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).
　また、導電体２６０ａが酸素の拡散を抑制する機能を有することにより、絶縁体２８０などに含まれる酸素により、導電体２６０ｂが酸化して導電率が低下することを抑制できる。酸素の拡散を抑制する機能を有する導電性材料としては、例えば、チタン、窒化チタン、タンタル、窒化タンタル、ルテニウム、酸化ルテニウムなどを用いることが好ましい。 In addition, since the conductor 260a has the function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 260b due to the oxygen contained in the insulator 280, etc., which would otherwise cause a decrease in conductivity. As a conductive material having the function of suppressing the diffusion of oxygen, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.
　また、導電体２６０ｂは、導電性が高い導電体を用いることが好ましい。例えば、導電体２６０ｂは、タングステン、銅、またはアルミニウムを主成分とする導電性材料を用いることができる。また、導電体２６０ｂは積層構造としてもよく、例えば、チタン、または窒化チタンと上記導電性材料との積層構造としてもよい。 Furthermore, it is preferable that the conductor 260b is a conductor having high conductivity. For example, the conductor 260b may be a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.
　また、トランジスタ２００では、導電体２６０は、絶縁体２８０などに形成されている開口を埋めるように自己整合的に形成される。ここで、上記開口における絶縁体２８０の側面は、導電体２４２ａの側面、及び導電体２４２ｂの側面と一致、または概略一致する。よって、位置合わせをしなくても、導電体２４２ａと導電体２４２ｂとの間の領域に重畳して、導電体２６０を配置することができる。 In addition, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. Here, the side of the insulator 280 in the opening coincides or roughly coincides with the side of the conductor 242a and the side of the conductor 242b. Therefore, the conductor 260 can be positioned so as to overlap the region between the conductor 242a and the conductor 242b without alignment.
　絶縁体２１６、及び絶縁体２８０は、それぞれ、絶縁体２２２よりも誘電率が低いことが好ましい。誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減できる。 It is preferable that the insulators 216 and 280 each have a lower dielectric constant than the insulator 222. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between the wirings can be reduced.
　例えば、絶縁体２１６、及び絶縁体２８０は、それぞれ、酸化シリコン、酸化窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素及び窒素を添加した酸化シリコン、及び、空孔を有する酸化シリコンのうち一つまたは複数を有することが好ましい。 For example, it is preferable that the insulators 216 and 280 each have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.
　特に、酸化シリコン及び酸化窒化シリコンは、熱的に安定であるため好ましい。特に、酸化シリコン、酸化窒化シリコン、空孔を有する酸化シリコンなどの材料は、加熱により脱離する酸素を含む領域を容易に形成することができるため好ましい。 Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions that contain oxygen that is released by heating.
　また、絶縁体２１６、及び絶縁体２８０の上面は、それぞれ、平坦化されていてもよい。 Furthermore, the upper surfaces of the insulators 216 and 280 may each be flattened.
　絶縁体２８０中の水、水素などの不純物濃度は低減されていることが好ましい。例えば、絶縁体２８０は、酸化シリコン、酸化窒化シリコンなどのシリコンを含む酸化物を有することが好ましい。 It is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. For example, it is preferable that the insulator 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.
　導電体２４０ａ、及び導電体２４０ｂは、それぞれ絶縁体２７５、絶縁体２８０、絶縁体２８２、及び絶縁体２８３の開口内に形成されている。導電体２４０ａの下面は、導電体２４２ａの上面に接し、導電体２４０ｂの下面は、導電体２４２ｂの上面に接している。ここで、導電体２４０の上面の高さと、絶縁体２８３の上面の高さは、同程度になる。 Conductor 240a and conductor 240b are formed in the openings of insulators 275, 280, 282, and 283, respectively. The lower surface of conductor 240a contacts the upper surface of conductor 242a, and the lower surface of conductor 240b contacts the upper surface of conductor 242b. Here, the height of the upper surface of conductor 240 and the height of the upper surface of insulator 283 are approximately the same.
　導電体２４０は、タングステン、銅、またはアルミニウムを主成分とする導電性材料を用いることが好ましい。また、導電体２４０は、導電体２４０は、第１の導電体が絶縁体２４１の側面に接して設けられ、さらに内側に第２の導電体が設けられる、積層構造としてもよい。この場合、第２の導電体として、上記の導電性材料を用いることができる。 The conductor 240 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240 may also have a layered structure in which a first conductor is provided in contact with the side surface of the insulator 241, and a second conductor is provided further inside. In this case, the above-mentioned conductive material can be used as the second conductor.
　また、導電体２４０を積層構造とする場合、絶縁体２８３、絶縁体２８２、絶縁体２８０、及び、絶縁体２７５の近傍に配置される第１の導電体には、水、水素などの不純物の透過を抑制する機能を有する導電性材料を用いることが好ましい。例えば、タンタル、窒化タンタル、チタン、窒化チタン、ルテニウム、酸化ルテニウムなどを用いることが好ましい。また、水、水素などの不純物の透過を抑制する機能を有する導電性材料は、単層または積層で用いてもよい。このような構成にすることで、絶縁体２８３より上層に含まれる水、水素などの不純物が、導電体２４０ａおよび導電体２４０ｂを通じて酸化物２３０に混入するのを抑制することができる。 Furthermore, when the conductor 240 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the first conductor arranged near the insulators 283, 282, and 280, and the insulator 275. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Furthermore, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a laminated layer. With such a configuration, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from being mixed into the oxide 230 through the conductors 240a and 240b.
　絶縁体２４１ａ、及び絶縁体２４１ｂは、それぞれ絶縁体２７５、絶縁体２８０、絶縁体２８２、及び絶縁体２８３の開口の内壁に接して形成されている。絶縁体２４１ａの内側の側面は、導電体２４０ａに接し、絶縁体２４１ｂの内側の側面は、導電体２４０ｂに接する。 Insulators 241a and 241b are formed in contact with the inner walls of the openings of insulators 275, 280, 282, and 283, respectively. The inner side of insulator 241a contacts conductor 240a, and the inner side of insulator 241b contacts conductor 240b.
　絶縁体２４１としては、絶縁体２７５などに用いることができるバリア絶縁膜を用いればよい。例えば、絶縁体２４１として、窒化シリコン、酸化アルミニウム、窒化酸化シリコンなどの絶縁体を用いればよい。絶縁体２４１を設けることで、絶縁体２８０などに含まれる水、水素などの不純物が、導電体２４０ａおよび導電体２４０ｂを通じて酸化物２３０に混入するのを抑制することができる。特に、窒化シリコンは水素に対するブロッキング性が高いので好適である。また、絶縁体２８０に含まれる酸素が導電体２４０ａおよび導電体２４０ｂに吸収されるのを防ぐことができる。 The insulator 241 may be a barrier insulating film that can be used for the insulator 275, etc. For example, the insulator 241 may be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. By providing the insulator 241, impurities such as water and hydrogen contained in the insulator 280, etc., can be prevented from mixing into the oxide 230 through the conductors 240a and 240b. Silicon nitride is particularly suitable because it has high blocking properties against hydrogen. In addition, the oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.
　絶縁体２４１を、図１Ｂに示すように積層構造にする場合、絶縁体２８０などの開口の内壁に接する第１の絶縁体と、その内側の第２の絶縁体は、酸素に対するバリア絶縁膜と、水素に対するバリア絶縁膜を組み合わせて用いることが好ましい。 When the insulator 241 has a layered structure as shown in FIG. 1B, it is preferable that the first insulator in contact with the inner wall of the opening, such as the insulator 280, and the second insulator on the inside thereof are made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.
　例えば、第１の絶縁体として、熱ＡＬＤ法で成膜された酸化アルミニウムを用い、第２の絶縁体として、ＰＥＡＬＤ法で成膜された窒化シリコンを用いればよい。このような構成にすることで、導電体２４０の酸化を抑制し、さらに、導電体２４０に水素が混入するのを低減することができる。 For example, the first insulator may be aluminum oxide formed by thermal ALD, and the second insulator may be silicon nitride formed by PEALD. This configuration can suppress oxidation of the conductor 240 and also reduce hydrogen contamination of the conductor 240.
　なお、上記において、絶縁体２４１が２層の積層構造である構成について示しているが、本発明はこれに限られるものではない。例えば、絶縁体２４１を単層、または３層以上の積層構造として設ける構成にしてもよい。また、上記において、導電体２４０が２層の積層構造である構成について示しているが、本発明はこれに限られるものではない。例えば、導電体２４０を単層、または３層以上の積層構造として設ける構成にしてもよい。 Note that, although the above describes a configuration in which the insulator 241 has a two-layer laminated structure, the present invention is not limited to this. For example, the insulator 241 may be configured as a single layer or a laminated structure of three or more layers. Also, although the above describes a configuration in which the conductor 240 has a two-layer laminated structure, the present invention is not limited to this. For example, the conductor 240 may be configured as a single layer or a laminated structure of three or more layers.
　また、図４Ｂなどにおいて、導電体２４０ａが、絶縁体２２５の上端部より上だけで、導電体２４２ａと接する構造について示したが、本発明はこれに限られるものではない。例えば、図４Ｃに示すように、導電体２４０ａが、絶縁体２２５と、絶縁体２２５を挟んで二つ折りの状態になっている酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２ａと、を覆う構造にしてもよい。これにより、チャネル幅方向の断面視において、絶縁体２２５の上部、Ａ５側の側面、及びＡ６側の側面それぞれにおいて、導電体２４０ａが、導電体２４２ａに接する。よって、絶縁体２２５を設けない場合と比較して、絶縁体２２５のＡ５側の側面、及びＡ６側の側面の分だけ、導電体２４０ａと導電体２４２ａの接触面積が大きくなっている。なお、図４Ｃにおいては、導電体２４０ａ及び導電体２４２ａの近傍を示したが、導電体２４０ｂ及び導電体２４２ｂについても同様である。つまり、上述の導電体２４０ａと導電体２４２ａと同様に、導電体２４０ｂと導電体２４２ｂの接触面積が大きくなっている。 In addition, in FIG. 4B and other figures, a structure in which the conductor 240a contacts the conductor 242a only above the upper end of the insulator 225 is shown, but the present invention is not limited to this. For example, as shown in FIG. 4C, a structure in which the conductor 240a covers the insulator 225 and the oxide 230a, oxide 230b, and conductor 242a that are folded in half with the insulator 225 in between may be used. As a result, in a cross-sectional view in the channel width direction, the conductor 240a contacts the conductor 242a at the top of the insulator 225, the side surface on the A5 side, and the side surface on the A6 side. Therefore, compared to a case in which the insulator 225 is not provided, the contact area between the conductor 240a and the conductor 242a is larger by the side surface on the A5 side and the side surface on the A6 side of the insulator 225. Note that in FIG. 4C, the vicinity of the conductor 240a and the conductor 242a is shown, but the same applies to the conductor 240b and the conductor 242b. In other words, similar to the above-mentioned conductor 240a and conductor 242a, the contact area between conductor 240b and conductor 242b is large.
　上記のように導電体２４０と導電体２４２の接触面積が大きくなることで、トランジスタ２００の占有面積を大きく広げることなく、トランジスタ２００のオン電流、周波数特性などを良好にすることができる。これにより、動作速度が速い半導体装置を提供することができる。また、当該半導体装置を用いた記憶装置の動作速度を速くすることができる。また、これにより、半導体装置の微細化または高集積化を図ることができる。また、当該半導体装置を用いた記憶装置の記憶容量を大きくすることができる。 By increasing the contact area between conductor 240 and conductor 242 as described above, the on-current, frequency characteristics, and the like of transistor 200 can be improved without significantly increasing the area occupied by transistor 200. This makes it possible to provide a semiconductor device with a high operating speed. In addition, the operating speed of a storage device using the semiconductor device can be increased. This also makes it possible to miniaturize or highly integrate the semiconductor device. In addition, the storage capacity of a storage device using the semiconductor device can be increased.
　また、上記においては、図１Ｃなどに示すように、トランジスタ２００のチャネル近傍において、酸化物２３０ａ及び酸化物２３０ｂが絶縁体２２５を覆う構造にしたが、本発明はこれに限られるものではない。例えば、図７Ａ乃至図７Ｄ、及び図８に示すように、トランジスタ２００のチャネル近傍において、酸化物２３０ａ及び酸化物２３０ｂから絶縁体２２５の上面が露出している構造にしてもよい。図７Ａは、上記半導体装置の上面図である。また、図７Ｂ乃至図７Ｄ、及び図８は、当該半導体装置の断面図である。ここで、図７Ｂは、図７ＡにＡ１−Ａ２の一点鎖線で示す部位の断面図である。また、図７Ｃは、図７ＡにＡ３−Ａ４の一点鎖線で示す部位の断面図である。また、図７Ｄは、図７ＡにＡ５−Ａ６の一点鎖線で示す部位の断面図である。また、図８は、図７ＡにＢ１−Ｂ２の一点鎖線で示す部位の断面図である。また、図７Ａの上面図では、図の明瞭化のために一部の要素を省いている。 In the above, as shown in FIG. 1C and the like, the oxide 230a and the oxide 230b cover the insulator 225 near the channel of the transistor 200, but the present invention is not limited to this. For example, as shown in FIG. 7A to FIG. 7D, and FIG. 8, the upper surface of the insulator 225 may be exposed from the oxide 230a and the oxide 230b near the channel of the transistor 200. FIG. 7A is a top view of the semiconductor device. Also, FIG. 7B to FIG. 7D, and FIG. 8 are cross-sectional views of the semiconductor device. Here, FIG. 7B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 7A. Also, FIG. 7C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 7A. Also, FIG. 7D is a cross-sectional view of the portion indicated by the dashed line A5-A6 in FIG. 7A. Also, FIG. 8 is a cross-sectional view of the portion indicated by the dashed line B1-B2 in FIG. 7A. Also, in the top view of Figure 7A, some elements have been omitted for clarity.
　図７Ａ、図７Ｂ、図７Ｃ、図８に示すように、導電体２４２等と重ならない領域（導電体２４２ａと導電体２４２ｂに挟まれた領域ということもできる。）において、酸化物２３０ａが絶縁体２２５の側面に接し、酸化物２３０ｂが酸化物２３０ａの側面に接し、且つ酸化物２３０ａ及び酸化物２３０ｂが絶縁体２２５の上面の少なくとも一部に接しない、構造にすることができる。ここで、酸化物２３０ａは、絶縁体２２５の側面、酸化物２３０ｂの側面及び下面、ならびに絶縁体２２２の上面に接する。さらに、図７Ｂ、図７Ｃなどに示すように、絶縁体２２５の上面は絶縁体２５０の下面に接する。なお、図７Ａ、図７Ｄなどに示すように、酸化物２３０ａ及び酸化物２３０ｂは、導電体２４２等と重なる領域においては、図１Ｄに示す構造と同様に、絶縁体２２５を覆う構造になる。 As shown in Figures 7A, 7B, 7C, and 8, in the region that does not overlap with the conductor 242, etc. (which can also be called the region sandwiched between the conductor 242a and the conductor 242b), the oxide 230a contacts the side of the insulator 225, the oxide 230b contacts the side of the oxide 230a, and the oxide 230a and the oxide 230b do not contact at least a part of the upper surface of the insulator 225. Here, the oxide 230a contacts the side of the insulator 225, the side and lower surface of the oxide 230b, and the upper surface of the insulator 222. Furthermore, as shown in Figures 7B, 7C, etc., the upper surface of the insulator 225 contacts the lower surface of the insulator 250. Note that, as shown in Figures 7A, 7D, etc., the oxide 230a and the oxide 230b cover the insulator 225 in the region that overlaps with the conductor 242, etc., similar to the structure shown in Figure 1D.
　図７Ｂでは、導電体２４２ａと導電体２４２ｂの間に、酸化物２３０ａ及び酸化物２３０ｂが形成されていないように見えるが、図８に示すように、絶縁体２２５の側面近傍に酸化物２３０ａ及び酸化物２３０ｂが形成されている。つまり、酸化物２３０ａ及び酸化物２３０ｂは、それぞれ、導電体２４２と重なる領域では、絶縁体２２５を挟んでＡ５側の部位とＡ６側の部位が二つ折り状に一体になっているが、導電体２４２ａと導電体２４２ｂの間の領域では、Ａ３側の部位とＡ４側の部位が絶縁体２２５によって分断された形状である。言い換えると、絶縁体２２５は、酸化物２３０によって概略覆われているが、導電体２４２ａと導電体２４２ｂの間の領域では、酸化物２３０に開口が形成されており、当該領域において絶縁体２２５は、酸化物２３０から露出している。 In FIG. 7B, it appears that the oxide 230a and the oxide 230b are not formed between the conductor 242a and the conductor 242b, but as shown in FIG. 8, the oxide 230a and the oxide 230b are formed near the side of the insulator 225. That is, in the region where the oxide 230a and the oxide 230b overlap the conductor 242, the A5 side portion and the A6 side portion are folded in half and integrated with the insulator 225 in between, but in the region between the conductor 242a and the conductor 242b, the A3 side portion and the A4 side portion are separated by the insulator 225. In other words, the insulator 225 is mostly covered by the oxide 230, but in the region between the conductor 242a and the conductor 242b, an opening is formed in the oxide 230, and the insulator 225 is exposed from the oxide 230 in that region.
　上記のように、導電体２４２ａと導電体２４２ｂの間の領域では、酸化物２３０ａ及び酸化物２３０ｂは、アスペクト比が高い絶縁体２２５の側面にサイドウォール状に設けられる。このような構成にすることで、絶縁体２２５の、Ａ３側の側面、及びＡ４側の側面にトランジスタ２００のチャネル形成領域を形成することができるので、単位面積当たりのチャネル幅を大きくすることができる。チャネル幅が大きくなることで、トランジスタ２００のオン電流、電界効果移動度、周波数特性を良好にすることができる。よって、本実施の形態の半導体装置を記憶装置として用いることで、動作速度の向上を図ることができる。 As described above, in the region between the conductor 242a and the conductor 242b, the oxide 230a and the oxide 230b are provided in the form of sidewalls on the side of the insulator 225, which has a high aspect ratio. With this configuration, the channel formation region of the transistor 200 can be formed on the side of the insulator 225 on the A3 side and the A4 side, so that the channel width per unit area can be increased. The increased channel width can improve the on-current, field effect mobility, and frequency characteristics of the transistor 200. Therefore, by using the semiconductor device of this embodiment as a memory device, the operating speed can be improved.
　また、上記においては、図７Ｄなどに示すように、トランジスタ２００のソースまたはドレイン近傍において、酸化物２３０ａ、酸化物２３０ｂ、導電体２４２ａ、及び導電体２４２ｂが、絶縁体２２５を挟んで二つ折り状になる構造にしたが、本発明はこれに限られるものではない。例えば、図９Ａ乃至図９Ｄ、図１０Ａ及び図１０Ｂに示すように、酸化物２３０ａ、酸化物２３０ｂ、導電体２４２ａ、及び導電体２４２ｂが、Ａ１−Ａ２の一点鎖線を境にＡ３側の部位と、Ａ４側の部位に分断された構造にすることもできる。図９Ａは、上記半導体装置の上面図である。また、図９Ｂ乃至図９Ｄ、図１０Ａ及び図１０Ｂは、当該半導体装置の断面図である。ここで、図９Ｂは、図９ＡにＤ１−Ｄ２の一点鎖線で示す部位の断面図である。また、図９Ｃは、図９ＡにＡ３−Ａ４の一点鎖線で示す部位の断面図である。また、図９Ｄは、図９ＡにＡ５−Ａ６の一点鎖線で示す部位の断面図である。また、図１０Ａは、図９ＡにＥ１−Ｅ２の一点鎖線で示す部位の断面図である。また、図１０Ｂは、図９ＡにＡ１−Ａ２の一点鎖線で示す部位の断面図である。また、図９Ａの上面図では、図の明瞭化のために一部の要素を省いている。 In the above, as shown in FIG. 7D and other figures, the oxide 230a, the oxide 230b, the conductor 242a, and the conductor 242b are folded in two with the insulator 225 sandwiched between them near the source or drain of the transistor 200, but the present invention is not limited to this. For example, as shown in FIGS. 9A to 9D, 10A, and 10B, the oxide 230a, the oxide 230b, the conductor 242a, and the conductor 242b can be divided into a portion on the A3 side and a portion on the A4 side with the dashed line A1-A2 as the boundary. FIG. 9A is a top view of the semiconductor device. Also, FIGS. 9B to 9D, 10A, and 10B are cross-sectional views of the semiconductor device. Here, FIG. 9B is a cross-sectional view of the portion indicated by the dashed line D1-D2 in FIG. 9A. Also, FIG. 9C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 9A. FIG. 9D is a cross-sectional view of the area indicated by the dashed line A5-A6 in FIG. 9A. FIG. 10A is a cross-sectional view of the area indicated by the dashed line E1-E2 in FIG. 9A. FIG. 10B is a cross-sectional view of the area indicated by the dashed line A1-A2 in FIG. 9A. In the top view of FIG. 9A, some elements have been omitted for clarity.
　図９Ａ乃至図９Ｄ、図１０Ａ及び図１０Ｂに示す半導体装置は、Ａ１−Ａ２の一点鎖線（絶縁体２２５）を境に、Ａ３側にトランジスタ２００ａＤを有し、Ａ４側にトランジスタ２００ａＥを有する。つまり、図７Ａ乃至図７Ｄ、及び図８に示す半導体装置において、大きく占有面積を増やすことなく、トランジスタ２００ａをトランジスタ２００ａＤとトランジスタ２００ａＥに分割した構造になる。なお、図９Ａ乃至図９Ｄ、図１０Ａ及び図１０Ｂに示す半導体装置では、図７Ａ乃至図７Ｄ、及び図８に示す半導体装置のトランジスタ２００ｂに対応する構成要素を示していないが、図７Ａ乃至図７Ｄ、及び図８に示す半導体装置と同様に、トランジスタ２００ｂに対応する構成要素も設けることができる。 The semiconductor device shown in Figures 9A to 9D, 10A, and 10B has transistor 200aD on the A3 side and transistor 200aE on the A4 side, with the dashed line A1-A2 (insulator 225) as the boundary. In other words, in the semiconductor device shown in Figures 7A to 7D, and 8, the transistor 200a is divided into transistor 200aD and transistor 200aE without significantly increasing the occupied area. Note that the semiconductor device shown in Figures 9A to 9D, 10A, and 10B does not show components corresponding to transistor 200b of the semiconductor device shown in Figures 7A to 7D, and 8, but components corresponding to transistor 200b can also be provided, as in the semiconductor device shown in Figures 7A to 7D, and 8.
　よって、図９Ａ乃至図９Ｄ、図１０Ａ及び図１０Ｂに示す半導体装置の構成要素は、図７Ａ乃至図７Ｄ、及び図８に示す半導体装置の構成要素に、ＤまたはＥを付して記す。つまり、Ａ３側のトランジスタ２００ａＤが有する構成要素は、酸化物２３０Ｄ（酸化物２３０ａＤ及び酸化物２３０ｂＤ）、導電体２４２ａＤ、導電体２４２ｂＤ、導電体２４０ａＤ、導電体２４０ｂＤ、絶縁体２４１ａＤ、絶縁体２４１ｂＤとなる。また、Ａ４側のトランジスタ２００ａＥが有する構成要素は、酸化物２３０Ｅ（酸化物２３０ａＥ及び酸化物２３０ｂＥ）、導電体２４２ａＥ、導電体２４２ｂＥ、導電体２４０ａＥ、導電体２４０ｂＥ、絶縁体２４１ａＥ、絶縁体２４１ｂＥとなる。これらの構成要素の詳細は、上述の記載を参照することができる。 Therefore, the components of the semiconductor device shown in Figures 9A to 9D, 10A, and 10B are the components of the semiconductor device shown in Figures 7A to 7D, and 8, with D or E added. That is, the components of the transistor 200aD on the A3 side are the oxide 230D (oxide 230aD and oxide 230bD), conductor 242aD, conductor 242bD, conductor 240aD, conductor 240bD, insulator 241aD, and insulator 241bD. The components of the transistor 200aE on the A4 side are the oxide 230E (oxide 230aE and oxide 230bE), conductor 242aE, conductor 242bE, conductor 240aE, conductor 240bE, insulator 241aE, and insulator 241bE. For details of these components, refer to the above description.
　図９Ｂ及び図９Ｃに示すように、絶縁体２２５上で、酸化物２３０ａＤ、酸化物２３０ｂＤ、及び導電体２４２ａＤ（導電体２４２ｂＤ）は、酸化物２３０ａＥ、酸化物２３０ｂＥ、及び導電体２４２ａＥ（導電体２４２ｂＥ）と、離隔して設けられている。よって、図１０Ｂに示すように、絶縁体２２５の少なくとも一部の上方には、酸化物２３０ａＤ、酸化物２３０ｂＤ、導電体２４２ａＤ、導電体２４２ｂＤ、酸化物２３０ａＥ、酸化物２３０ｂＥ、導電体２４２ａＥ、及び導電体２４２ｂＥが形成されない。 9B and 9C, oxide 230aD, oxide 230bD, and conductor 242aD (conductor 242bD) are provided separately from oxide 230aE, oxide 230bE, and conductor 242aE (conductor 242bE) on insulator 225. Therefore, as shown in FIG. 10B, oxide 230aD, oxide 230bD, conductor 242aD, conductor 242bD, oxide 230aE, oxide 230bE, conductor 242aE, and conductor 242bE are not formed above at least a portion of insulator 225.
　また、図９Ｂに示すように、絶縁体２２５のＡ３側の側面に接して、酸化物２３０Ｄ（酸化物２３０ａＤ及び酸化物２３０ｂＤ）が形成されており、酸化物２３０ｂＤにチャネル形成領域が設けられている。また、同様に、図１０Ａに示すように、絶縁体２２５のＡ４側の側面に接して、酸化物２３０Ｅ（酸化物２３０ａＥ及び酸化物２３０ｂＥ）が形成されており、酸化物２３０ｂＥにチャネル形成領域が設けられている。 Furthermore, as shown in FIG. 9B, oxide 230D (oxide 230aD and oxide 230bD) is formed in contact with the side surface of insulator 225 on the A3 side, and a channel formation region is provided in oxide 230bD. Similarly, as shown in FIG. 10A, oxide 230E (oxide 230aE and oxide 230bE) is formed in contact with the side surface of insulator 225 on the A4 side, and a channel formation region is provided in oxide 230bE.
　図９Ａ乃至図９Ｄ、図１０Ａ及び図１０Ｂに示す構造にすることで、大きく占有面積を広げることなく、２倍のメモリセルを形成することができる。よって、半導体装置の微細化または高集積化を図ることができる。また、当該半導体装置を用いた記憶装置の記憶容量を大きくすることができる。 By using the structures shown in Figures 9A to 9D, 10A, and 10B, it is possible to form twice as many memory cells without significantly increasing the occupied area. This makes it possible to miniaturize or highly integrate the semiconductor device. In addition, it is possible to increase the storage capacity of a storage device using the semiconductor device.
＜半導体装置の構成材料＞
　以下では、半導体装置に用いることができる構成材料について説明する。なお、半導体装置を構成する各層は、単層構造であってもよく、積層構造であってもよい。 <Materials Constituting Semiconductor Device>
Constituent materials that can be used in the semiconductor device will be described below. Each layer constituting the semiconductor device may have a single layer structure or a multilayer structure.
＜＜基板＞＞
　トランジスタを形成する基板としては、例えば、絶縁体基板、半導体基板、または導電体基板を用いることができる。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板（イットリア安定化ジルコニア基板など）、及び、樹脂基板が挙げられる。また、半導体基板としては、例えば、シリコンまたはゲルマニウムを材料とした半導体基板、及び、炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、もしくは酸化ガリウムからなる化合物半導体基板が挙げられる。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えば、ＳＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板などが挙げられる。導電体基板としては、例えば、黒鉛基板、金属基板、合金基板、及び導電性樹脂基板が挙げられる。また、基板としては、例えば、金属の窒化物を有する基板、金属の酸化物を有する基板、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、及び、導電体基板に半導体または絶縁体が設けられた基板が挙げられる。または、これらの基板に１種または複数種の素子が設けられたものを用いてもよい。基板に設けられる素子としては、例えば、容量素子、抵抗素子、スイッチ素子、発光素子、及び記憶素子が挙げられる。 <<Substrate>>
As the substrate on which the transistor is formed, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As the insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate can be mentioned. As the semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be mentioned. Furthermore, as the semiconductor substrate, a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate, can be mentioned. As the conductive substrate, for example, a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate can be mentioned. As the substrate, for example, a substrate having a metal nitride, a substrate having a metal oxide, a substrate having a conductor or semiconductor provided on an insulator substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate can be mentioned. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.
＜＜絶縁体＞＞
　絶縁体としては、例えば、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、及び、金属窒化酸化物が挙げられる。 <<Insulators>>
Examples of the insulator include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.
　例えば、トランジスタの微細化、及び高集積化が進むと、ゲート絶縁体の薄膜化により、リーク電流などの問題が生じる場合がある。ゲート絶縁体として機能する絶縁体に、ｈｉｇｈ−ｋ材料を用いることで物理膜厚を保ちながら、トランジスタ動作時の低電圧化が可能となる。一方、層間膜として機能する絶縁体には、比誘電率が低い材料を用いることで、配線間に生じる寄生容量を低減することができる。したがって、絶縁体の機能に応じて、材料を選択するとよい。 For example, as transistors become more miniaturized and highly integrated, problems such as leakage currents can occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulator.
　比誘電率の高い絶縁体としては、例えば、酸化ガリウム、酸化ハフニウム、酸化ジルコニウム、アルミニウム及びハフニウムを有する酸化物、アルミニウム及びハフニウムを有する酸化窒化物、シリコン及びハフニウムを有する酸化物、シリコン及びハフニウムを有する酸化窒化物、並びに、シリコン及びハフニウムを有する窒化物が挙げられる。 Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxide nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxide nitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.
　比誘電率が低い絶縁体としては、例えば、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素及び窒素を添加した酸化シリコン、空孔を有する酸化シリコン、及び、樹脂が挙げられる。 Examples of insulators with low dielectric constants include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with voids, and resin.
　また、金属酸化物を用いたトランジスタは、水素などの不純物及び酸素の透過を抑制する機能を有する絶縁体で囲うことによって、トランジスタの電気特性を安定にすることができる。水素などの不純物及び酸素の透過を抑制する機能を有する絶縁体としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウム、及びタンタルのうち一つまたは複数を含む絶縁体を、単層で、または積層で用いることができる。具体的には、水素などの不純物及び酸素の透過を抑制する機能を有する絶縁体として、例えば、酸化アルミニウム、酸化マグネシウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウム、酸化タンタルなどの金属酸化物、及び、窒化アルミニウム、窒化酸化シリコン、窒化シリコンなどの金属窒化物が挙げられる。 In addition, the electrical characteristics of a transistor using a metal oxide can be stabilized by surrounding it with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer. Specifically, as an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
　また、ゲート絶縁体として機能する絶縁体は、加熱により脱離する酸素を含む領域を有する絶縁体であることが好ましい。例えば、加熱により脱離する酸素を含む領域を有する酸化シリコンまたは酸化窒化シリコンを酸化物２３０と接する構造とすることで、酸化物２３０が有する酸素欠損を補償することができる。 Furthermore, it is preferable that the insulator that functions as the gate insulator is an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with oxide 230, the oxygen vacancies in oxide 230 can be compensated for.
＜＜導電体＞＞
　導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウム、イリジウム、ストロンチウム、ランタンなどから選ばれた金属元素、または上述した金属元素を成分とする合金か、上述した金属元素を組み合わせた合金等を用いることが好ましい。導電体としては、例えば、窒化タンタル、窒化チタン、タングステン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、及び、ランタンとニッケルを含む酸化物が挙げられる。また、窒化タンタル、窒化チタン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、及び、ランタンとニッケルを含む酸化物は、それぞれ、酸化しにくい導電性材料、または、酸素を吸収しても導電性を維持する材料であるため、好ましい。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、導電率が高い半導体、または、ニッケルシリサイドなどのシリサイドを用いてもよい。 <<Conductors>>
As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. As the conductor, for example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel can be mentioned. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed. Alternatively, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
　積層構造の導電体を用いる場合、例えば、前述した金属元素を含む材料と、酸素を含む導電性材料と、を組み合わせた積層構造、前述した金属元素を含む材料と、窒素を含む導電性材料と、を組み合わせた積層構造、または、前述した金属元素を含む材料と、酸素を含む導電性材料と、窒素を含む導電性材料と、を組み合わせた積層構造を適用してもよい。 When using a conductor with a layered structure, for example, a layered structure combining the material containing the metal element described above with a conductive material containing oxygen, a layered structure combining the material containing the metal element described above with a conductive material containing nitrogen, or a layered structure combining the material containing the metal element described above with a conductive material containing oxygen and a conductive material containing nitrogen may be applied.
　なお、トランジスタのチャネル形成領域に酸化物を用いる場合において、ゲート電極として機能する導電体には、前述した金属元素を含む材料と、酸素を含む導電性材料と、を組み合わせた積層構造を用いることが好ましい。この場合は、酸素を含む導電性材料をチャネル形成領域側に設けるとよい。酸素を含む導電性材料をチャネル形成領域側に設けることで、当該導電性材料から離脱した酸素がチャネル形成領域に供給されやすくなる。 When an oxide is used for the channel formation region of a transistor, it is preferable to use a layered structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductor that functions as the gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.
　特に、ゲート電極として機能する導電体として、チャネルが形成される金属酸化物に含まれる金属元素及び酸素を含む導電性材料を用いることが好ましい。また、前述した金属元素及び窒素を含む導電性材料を用いてもよい。例えば、窒化チタン、窒化タンタルなどの窒素を含む導電性材料を用いてもよい。また、インジウム錫酸化物、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、酸化チタンを含むインジウム錫酸化物、インジウム亜鉛酸化物、及び、シリコンを添加したインジウム錫酸化物のうち一つまたは複数を用いてもよい。また、窒素を含むインジウムガリウム亜鉛酸化物を用いてもよい。このような材料を用いることで、チャネルが形成される金属酸化物に含まれる水素を捕獲することができる場合がある。または、外方の絶縁体などから混入する水素を捕獲することができる場合がある。 In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor that functions as a gate electrode. The conductive material containing the metal element and nitrogen described above may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. One or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Or, it may be possible to capture hydrogen mixed in from an external insulator or the like.
＜＜金属酸化物＞＞
　酸化物２３０として、半導体として機能する金属酸化物（酸化物半導体）を用いることが好ましい。以下では、本発明の一態様に係る酸化物２３０に適用可能な金属酸化物について説明する。 <<Metal oxides>>
A metal oxide that functions as a semiconductor (oxide semiconductor) is preferably used as the oxide 230. Metal oxides that can be used as the oxide 230 of one embodiment of the present invention are described below.
　金属酸化物は、少なくともインジウムまたは亜鉛を含むことが好ましい。特に、インジウム及び亜鉛を含むことが好ましい。また、それらに加えて、アルミニウム、ガリウム、イットリウム、錫、アンチモンなどが含まれていることが好ましい。また、ホウ素、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、マグネシウム、コバルトなどから選ばれた一種、または複数種が含まれていてもよい。 The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition to these, it is preferable that it contains aluminum, gallium, yttrium, tin, antimony, etc. Furthermore, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.
　ここでは、金属酸化物が、インジウム、元素Ｍ及び亜鉛を有するＩｎ−Ｍ−Ｚｎ酸化物である場合を考える。なお、元素Ｍは、アルミニウム、ガリウム、イットリウム、錫、またはアンチモンとする。その他、元素Ｍに適用可能な元素としては、ホウ素、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、マグネシウム、コバルトなどがある。ただし、元素Ｍとして、前述の元素を複数組み合わせても構わない場合がある。特に、元素Ｍは、ガリウム、アルミニウム、イットリウム、及びスズから選ばれた一種または複数種であることが好ましい。 Here, we consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. The element M is aluminum, gallium, yttrium, tin, or antimony. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where the element M may be a combination of multiple of the above elements. In particular, it is preferable that element M is one or more types selected from gallium, aluminum, yttrium, and tin.
　なお、本明細書等において、窒素を有する金属酸化物も金属酸化物（ｍｅｔａｌ　ｏｘｉｄｅ）と総称する場合がある。また、窒素を有する金属酸化物を、金属酸化窒化物（ｍｅｔａｌ　ｏｘｙｎｉｔｒｉｄｅ）と呼称してもよい。 In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Metal oxides containing nitrogen may also be referred to as metal oxide nitrides.
　以降では、金属酸化物の一例として、Ｉｎ−Ｇａ−Ｚｎ酸化物について説明する。 Below, we will explain In-Ga-Zn oxide as an example of a metal oxide.
　酸化物半導体の結晶構造としては、アモルファス（ｃｏｍｐｌｅｔｅｌｙ　ａｍｏｒｐｈｏｕｓを含む）、ＣＡＡＣ（ｃ−ａｘｉｓ−ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌｌｉｎｅ）、ｎｃ（ｎａｎｏｃｒｙｓｔａｌｌｉｎｅ）、ＣＡＣ（ｃｌｏｕｄ−ａｌｉｇｎｅｄ　ｃｏｍｐｏｓｉｔｅ）、単結晶（ｓｉｎｇｌｅ　ｃｒｙｓｔａｌ）、及び多結晶（ｐｏｌｙｃｒｙｓｔａｌ）等が挙げられる。 Crystal structures of oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystalline.
　なお、酸化物半導体は、構造に着目した場合、上記とは異なる分類となる場合がある。例えば、酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、上述のＣＡＡＣ−ＯＳ、及びｎｃ−ＯＳがある。また、非単結晶酸化物半導体には、多結晶酸化物半導体、擬似非晶質酸化物半導体（ａ−ｌｉｋｅ　ＯＳ：ａｍｏｒｐｈｏｕｓ−ｌｉｋｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、非晶質酸化物半導体などが含まれる。 Note that oxide semiconductors may be classified differently from the above when focusing on their structure. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductors), amorphous oxide semiconductors, and the like.
　ここで、上述のＣＡＡＣ−ＯＳ、ｎｃ−ＯＳ、及びａ−ｌｉｋｅ　ＯＳの詳細について、説明を行う。 Here, we will explain the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS.
［ＣＡＡＣ−ＯＳ］
　ＣＡＡＣ−ＯＳは、複数の結晶領域を有し、当該複数の結晶領域はｃ軸が特定の方向に配向している酸化物半導体である。なお、特定の方向とは、ＣＡＡＣ−ＯＳ膜の厚さ方向、ＣＡＡＣ−ＯＳ膜の被形成面の法線方向、またはＣＡＡＣ−ＯＳ膜の表面の法線方向である。なお、図２Ｂなどに示すように、酸化物２３０が絶縁体２２５に接している領域では、ｃ軸が絶縁体２２５の膜の表面の法線方向に配向していることが好ましい。また、結晶領域とは、原子配列に周期性を有する領域である。なお、原子配列を格子配列とみなすと、結晶領域とは、格子配列の揃った領域でもある。さらに、ＣＡＡＣ−ＯＳは、ａ−ｂ面方向において複数の結晶領域が連結する領域を有し、当該領域は歪みを有する場合がある。なお、歪みとは、複数の結晶領域が連結する領域において、格子配列の揃った領域と、別の格子配列の揃った領域と、の間で格子配列の向きが変化している箇所を指す。つまり、ＣＡＡＣ−ＯＳは、ｃ軸配向し、ａ−ｂ面方向には明らかな配向をしていない酸化物半導体である。 [CAAC-OS]
CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis oriented in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film. As shown in FIG. 2B and other figures, in a region where the oxide 230 is in contact with the insulator 225, the c-axis is preferably oriented in the normal direction of the surface of the insulator 225. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region in which the lattice arrangement is uniform. Furthermore, the CAAC-OS has a region in which a plurality of crystalline regions are connected in the a-b plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement is changed between a region in which the lattice arrangement is uniform and another region in which the lattice arrangement is uniform in a region in which the plurality of crystalline regions are connected. That is, the CAAC-OS is an oxide semiconductor that is c-axis aligned and does not clearly have an alignment in the a-b plane direction.
　なお、上記複数の結晶領域のそれぞれは、１つまたは複数の微小な結晶（最大径が１０ｎｍ未満である結晶）で構成される。結晶領域が１つの微小な結晶で構成されている場合、当該結晶領域の最大径は１０ｎｍ未満となる。また、結晶領域が多数の微小な結晶で構成されている場合、当該結晶領域の最大径は、数十ｎｍ程度となる場合がある。 Each of the multiple crystal regions is composed of one or more tiny crystals (crystals with a maximum diameter of less than 10 nm). When a crystal region is composed of one tiny crystal, the maximum diameter of the crystal region is less than 10 nm. When a crystal region is composed of many tiny crystals, the maximum diameter of the crystal region may be several tens of nm.
　ＣＡＡＣ−ＯＳは、結晶性が高く、明確な結晶粒界が確認されない酸化物半導体である。よって、ＣＡＡＣ−ＯＳは、結晶粒界に起因する電子移動度の低下が起こりにくいといえる。また、酸化物半導体の結晶性は不純物の混入、欠陥の生成などによって低下する場合があるため、ＣＡＡＣ−ＯＳは不純物及び欠陥（酸素欠損など）の少ない酸化物半導体ともいえる。従って、ＣＡＡＣ−ＯＳを有する酸化物半導体は、物理的性質が安定する。そのため、ＣＡＡＣ−ＯＳを有する酸化物半導体は熱に強く、信頼性が高い。また、ＣＡＡＣ−ＯＳは、製造工程における高い温度（所謂サーマルバジェット）に対しても安定である。したがって、ＯＳトランジスタにＣＡＡＣ−ＯＳを用いると、製造工程の自由度を広げることが可能となる。 CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor having CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having CAAC-OS is resistant to heat and highly reliable. In addition, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.
［ｎｃ−ＯＳ］
　ｎｃ−ＯＳは、微小な領域（例えば、１ｎｍ以上１０ｎｍ以下の領域、特に１ｎｍ以上３ｎｍ以下の領域）において原子配列に周期性を有する。別言すると、ｎｃ−ＯＳは、微小な結晶を有する。なお、当該微小な結晶の大きさは、例えば、１ｎｍ以上１０ｎｍ以下、特に１ｎｍ以上３ｎｍ以下であることから、当該微小な結晶をナノ結晶ともいう。また、ｎｃ−ＯＳは、異なるナノ結晶間で結晶方位に規則性が見られない。そのため、膜全体で配向性が見られない。したがって、ｎｃ−ＯＳは、分析方法によっては、ａ−ｌｉｋｅ　ＯＳまたは非晶質酸化物半導体と区別が付かない場合がある。 [nc-OS]
The nc-OS has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.
［ａ−ｌｉｋｅ　ＯＳ］
　ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳと非晶質酸化物半導体との間の構造を有する酸化物半導体である。ａ−ｌｉｋｅ　ＯＳは、鬆または低密度領域を有する。即ち、ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳ及びＣＡＡＣ−ＯＳと比べて、結晶性が低い。また、ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳ及びＣＡＡＣ−ＯＳと比べて、膜中の水素濃度が高い。 [a-like OS]
The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.
　次に、上述のＣＡＣ−ＯＳの詳細について、説明を行う。なお、ＣＡＣ−ＯＳは材料構成に関する。 Next, we will explain the details of the above-mentioned CAC-OS. Note that CAC-OS relates to the material composition.
［ＣＡＣ−ＯＳ］
　ＣＡＣ−ＯＳとは、例えば、金属酸化物を構成する元素が、０．５ｎｍ以上１０ｎｍ以下、好ましくは、１ｎｍ以上３ｎｍ以下、またはその近傍のサイズで偏在した材料の一構成である。なお、以下では、金属酸化物において、一つまたは複数の金属元素が偏在し、該金属元素を有する領域が、０．５ｎｍ以上１０ｎｍ以下、好ましくは、１ｎｍ以上３ｎｍ以下、またはその近傍のサイズで混合した状態をモザイク状、またはパッチ状ともいう。 [CAC-OS]
CAC-OS is a material in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that in the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and a region containing the metal elements is mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch shape.
　さらに、ＣＡＣ−ＯＳとは、第１の領域と、第２の領域と、に材料が分離することでモザイク状となり、当該第１の領域が、膜中に分布した構成（以下、クラウド状ともいう）である。つまり、ＣＡＣ−ＯＳは、当該第１の領域と、当該第２の領域とが、混合している構成を有する複合金属酸化物である。 Furthermore, CAC-OS is a structure in which the material is separated into a first region and a second region, forming a mosaic shape, and the first region is distributed throughout the film (hereinafter also referred to as a cloud shape). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
　また、Ｉｎ−Ｇａ−Ｚｎ酸化物におけるＣＡＣ−ＯＳとは、Ｉｎ、Ｇａ、Ｚｎ、及びＯを含む材料構成において、一部にＩｎを主成分とする領域（第１の領域）と、一部にＧａを主成分とする領域（第２の領域）とが、それぞれモザイク状であり、これらの領域がランダムに存在している構成をいう。よって、ＣＡＣ−ＯＳは、金属元素が不均一に分布した構造を有していると推測される。 CAC-OS in In-Ga-Zn oxide refers to a material composition containing In, Ga, Zn, and O, in which some regions (first regions) mainly composed of In and some regions (second regions) mainly composed of Ga are arranged in a mosaic pattern, and these regions exist randomly. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed non-uniformly.
　ＣＡＣ−ＯＳは、例えば基板を加熱しない条件で、スパッタリング法により形成することができる。また、ＣＡＣ−ＯＳをスパッタリング法で形成する場合、成膜ガスとして、不活性ガス（代表的にはアルゴン）、酸素ガス、及び窒素ガスの中から選ばれたいずれか一つまたは複数を用いることができる。また、成膜時の成膜ガスの総流量に対する酸素ガスの流量比は低いほど好ましい。例えば、成膜時の成膜ガスの総流量に対する酸素ガスの流量比を０％以上３０％未満、好ましくは０％以上１０％以下とする。 CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not heated. When CAC-OS is formed by a sputtering method, any one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas can be used as the film-forming gas. The lower the flow rate ratio of oxygen gas to the total flow rate of film-forming gas during film formation, the more preferable it is. For example, the flow rate ratio of oxygen gas to the total flow rate of film-forming gas during film formation is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.
　ここで、第１の領域は、第２の領域と比較して、導電性が高い領域である。つまり、第１の領域を、キャリアが流れることにより、金属酸化物としての導電性が発現する。従って、第１の領域が、金属酸化物中にクラウド状に分布することで、高い電界効果移動度（μ）が実現できる。 Here, the first region is a region with higher conductivity than the second region. In other words, the first region exhibits conductivity as a metal oxide when carriers flow through it. Therefore, the first region is distributed in a cloud-like shape in the metal oxide, achieving high field-effect mobility (μ).
　一方、第２の領域は、第１の領域と比較して、絶縁性が高い領域である。つまり、第２の領域が、金属酸化物中に分布することで、リーク電流を抑制することができる。 On the other hand, the second region has higher insulating properties than the first region. In other words, the second region being distributed in the metal oxide can suppress leakage current.
　したがって、ＣＡＣ−ＯＳをトランジスタに用いる場合、第１の領域に起因する導電性と、第２の領域に起因する絶縁性とが、相補的に作用することにより、スイッチングさせる機能（Ｏｎ／Ｏｆｆさせる機能）をＣＡＣ−ＯＳに付与することができる。つまり、ＣＡＣ−ＯＳとは、材料の一部では導電性の機能と、材料の一部では絶縁性の機能とを有し、材料の全体では半導体としての機能を有する。導電性の機能と絶縁性の機能とを分離させることで、双方の機能を最大限に高めることができる。よって、ＣＡＣ−ＯＳをトランジスタに用いることで、高いオン電流（Ｉｏｎ）、高い電界効果移動度（μ）、及び良好なスイッチング動作を実現することができる。 Therefore, when the CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, so that the CAC-OS can be given a switching function (on/off function). In other words, the CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and the whole material has a function as a semiconductor. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using the CAC-OS in a transistor, a high on-current (I on ), a high field-effect mobility (μ), and a good switching operation can be realized.
　また、ＣＡＣ−ＯＳを用いたトランジスタは、信頼性が高い。従って、ＣＡＣ−ＯＳは、表示装置をはじめとするさまざまな半導体装置に最適である。 In addition, transistors using CAC-OS are highly reliable. Therefore, CAC-OS is ideal for a variety of semiconductor devices including display devices.
　酸化物半導体は、多様な構造をとり、それぞれが異なる特性を有する。本発明の一態様の酸化物半導体は、非晶質酸化物半導体、多結晶酸化物半導体、ａ−ｌｉｋｅ　ＯＳ、ＣＡＣ−ＯＳ、ｎｃ−ＯＳ、ＣＡＡＣ−ＯＳのうち、二種以上を有していてもよい。 Oxide semiconductors have a variety of structures, each with different characteristics. An oxide semiconductor according to one embodiment of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.
＜＜その他の半導体材料＞＞
　トランジスタの半導体層には、バンドギャップを有する半導体材料（ゼロギャップ半導体ではない半導体材料）を用いてもよい。例えば、シリコンなどの単体元素の半導体、ヒ化ガリウムなどの化合物半導体を用いてもよい。 <<Other semiconductor materials>>
The semiconductor layer of the transistor may be made of a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor), such as a semiconductor of an element such as silicon or a compound semiconductor such as gallium arsenide.
　また、トランジスタの半導体層に、例えば、半導体として機能する遷移金属カルコゲナイドを用いることが好ましい。トランジスタの半導体層に適用可能な遷移金属カルコゲナイドとして、具体的には、硫化モリブデン（代表的にはＭｏＳ２）、セレン化モリブデン（代表的にはＭｏＳｅ２）、モリブデンテルル（代表的にはＭｏＴｅ２）、硫化タングステン（代表的にはＷＳ２）、セレン化タングステン（代表的にはＷＳｅ２）、タングステンテルル（代表的にはＷＴｅ２）、硫化ハフニウム（代表的にはＨｆＳ２）、セレン化ハフニウム（代表的にはＨｆＳｅ２）、硫化ジルコニウム（代表的にはＺｒＳ２）、セレン化ジルコニウム（代表的にはＺｒＳｅ２）などが挙げられる。上述の遷移金属カルコゲナイドを、トランジスタの半導体層に適用することで、オン電流が大きい半導体装置を提供することができる。 In addition, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor in the semiconductor layer of the transistor. Specific examples of transition metal chalcogenides that can be applied to the semiconductor layer of the transistor include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), molybdenum tellurium (typically MoTe 2 ), tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten tellurium (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically HfSe 2 ), zirconium sulfide (typically ZrS 2 ), and zirconium selenide (typically ZrSe 2 ). By applying the above-mentioned transition metal chalcogenide to the semiconductor layer of the transistor, a semiconductor device with a large on-current can be provided.
＜半導体装置の作製方法例＞
　図１１Ａ乃至図２１Ｄを用いて、本発明の一態様の半導体装置の作製方法例について説明する。ここでは、図１Ａ乃至図１Ｄに示す半導体装置を作製する場合を例に挙げて説明する。 <Example of Manufacturing Method of Semiconductor Device>
An example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to Fig. 11A to Fig. 21D. Here, the case of manufacturing the semiconductor device illustrated in Fig. 1A to Fig. 1D will be described as an example.
　各図のＡは、上面図を示す。また、各図のＢはそれぞれ、各図のＡにＡ１−Ａ２の一点鎖線で示す部位に対応する断面図であり、トランジスタ２００のチャネル長方向の断面図でもある。また、各図のＣはそれぞれ、各図のＡにＡ３−Ａ４の一点鎖線で示す部位に対応する断面図であり、トランジスタ２００のチャネル幅方向の断面図でもある。また、各図のＤはそれぞれ、各図のＡにＡ５−Ａ６の一点鎖線で示す部位の断面図であり、トランジスタ２００のチャネル幅方向の断面図でもある。なお、各図のＡの上面図では、図の明瞭化のために一部の要素を省いている。 A in each figure shows a top view. B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in A of each figure, and is also a cross-sectional view in the channel length direction of transistor 200. C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in A of each figure, and is also a cross-sectional view in the channel width direction of transistor 200. D in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in A of each figure, and is also a cross-sectional view in the channel width direction of transistor 200. Note that some elements are omitted from the top view in A of each figure to clarify the figure.
　以下において、絶縁体を形成するための絶縁性材料、導電体を形成するための導電性材料、または半導体を形成するための半導体材料は、スパッタリング法、化学気相成長（ＣＶＤ：Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、分子線エピタキシー（ＭＢＥ：Ｍｏｌｅｃｕｌａｒ　Ｂｅａｍ　Ｅｐｉｔａｘｙ）法、パルスレーザ堆積（ＰＬＤ：Ｐｕｌｓｅｄ　Ｌａｓｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、ＡＬＤ法などを適宜用いて成膜することができる。 In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like, as appropriate.
　なお、スパッタリング法にはスパッタリング用電源に高周波電源を用いるＲＦスパッタリング法、直流電源を用いるＤＣスパッタリング法、さらにパルス的に電極に印加する電圧を変化させるパルスＤＣスパッタリング法がある。ＲＦスパッタリング法は主に絶縁膜を成膜する場合に用いられ、ＤＣスパッタリング法は主に金属導電膜を成膜する場合に用いられる。また、パルスＤＣスパッタリング法は、主に、酸化物、窒化物、炭化物などの化合物をリアクティブスパッタリング法で成膜する際に用いられる。 Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing metal conductive films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using the reactive sputtering method.
　なお、ＣＶＤ法は、プラズマを利用するプラズマＣＶＤ（ＰＥＣＶＤ）法、熱を利用する熱ＣＶＤ（ＴＣＶＤ：Ｔｈｅｒｍａｌ　ＣＶＤ）法、光を利用する光ＣＶＤ（Ｐｈｏｔｏ　ＣＶＤ）法などに分類できる。さらに用いる原料ガスによって金属ＣＶＤ（ＭＣＶＤ：Ｍｅｔａｌ　ＣＶＤ）法、有機金属ＣＶＤ（ＭＯＣＶＤ：Ｍｅｔａｌ　Ｏｒｇａｎｉｃ　ＣＶＤ）法に分けることができる。 CVD methods can be classified into plasma CVD (PECVD) methods, which use plasma, thermal CVD (TCVD: Thermal CVD) methods, which use heat, and photo CVD (Photo CVD) methods, which use light. They can also be further divided into metal CVD (MCVD: Metal CVD) methods and metal organic CVD (MOCVD: Metal CVD) methods, depending on the source gas used.
　プラズマＣＶＤ法は、比較的低温で高品質の膜が得られる。また、熱ＣＶＤ法は、プラズマを用いないため、被処理物へのプラズマダメージを小さくすることが可能な成膜方法である。例えば、半導体装置に含まれる配線、電極、素子（トランジスタ、容量素子など）などは、プラズマから電荷を受け取ることでチャージアップする場合がある。このとき、蓄積した電荷によって、半導体装置に含まれる配線、電極、素子などが破壊される場合がある。一方、プラズマを用いない熱ＣＶＤ法の場合、こういったプラズマダメージが生じないため、半導体装置の歩留まりを高くすることができる。また、熱ＣＶＤ法では、成膜中のプラズマダメージが生じないため、欠陥の少ない膜が得られる。 The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can reduce plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, with the thermal CVD method, which does not use plasma, such plasma damage does not occur, and the yield of semiconductor devices can be increased. Furthermore, with the thermal CVD method, no plasma damage occurs during film formation, so films with fewer defects can be obtained.
　また、ＡＬＤ法としては、プリカーサ及びリアクタントの反応を熱エネルギーのみで行う熱ＡＬＤ法、プラズマ励起されたリアクタントを用いるＰＥＡＬＤ法などを用いることができる。 Also, the ALD method can be a thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy, or a PEALD method in which a plasma-excited reactant is used.
　ＣＶＤ法及びＡＬＤ法は、ターゲットなどから放出される粒子が堆積するスパッタリング法とは異なる。したがって、被処理物の形状の影響を受けにくく、良好な段差被覆性を有する成膜方法である。特に、ＡＬＤ法は、優れた段差被覆性と、優れた厚さの均一性と、を有するため、アスペクト比の高い開口部の表面を被覆する場合などに好適である。ただし、ＡＬＤ法は、比較的成膜速度が遅いため、成膜速度の速いＣＶＤ法などの他の成膜方法と組み合わせて用いることが好ましい場合もある。 The CVD and ALD methods are different from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.
　また、ＣＶＤ法では、原料ガスの流量比によって、任意の組成の膜を成膜することができる。例えば、ＣＶＤ法では、成膜しながら原料ガスの流量比を変化させることによって、組成が連続的に変化した膜を成膜することができる。原料ガスの流量比を変化させながら成膜する場合、複数の成膜室を用いて成膜する場合と比べて、搬送または圧力調整に掛かる時間を要さない分、成膜に掛かる時間を短くすることができる。したがって、半導体装置の生産性を高めることができる場合がある。 Also, with the CVD method, a film of any composition can be formed by changing the flow rate ratio of the source gases. For example, with the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers, since no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.
　また、ＡＬＤ法では、異なる複数種のプリカーサを同時に導入することで任意の組成の膜を成膜することができる。または、異なる複数種のプリカーサを導入する場合、各プリカーサのサイクル数を制御することで任意の組成の膜を成膜することができる。 Also, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different types of precursors. Alternatively, when multiple different types of precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor.
　まず、基板（図示しない）を準備し、当該基板上に絶縁体２１５を成膜する（図１１Ａ乃至図１１Ｄ参照）。上述の通り、絶縁体２１５は、絶縁体２８２、及び絶縁体２８３のいずれか一、または複数の積層膜と同様の絶縁体を用いることができる。絶縁体２１５の成膜方法は、例えば、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、または、ＡＬＤ法を用いることができる。成膜ガスに水素を含む分子を用いなくてもよいスパッタリング法を用いることで、絶縁体２１５中の水素濃度を低減できるので好ましい。 First, a substrate (not shown) is prepared, and an insulator 215 is formed on the substrate (see Figures 11A to 11D). As described above, the insulator 215 can be an insulator similar to one or more stacked films of the insulators 282 and 283. The method for forming the insulator 215 can be, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The sputtering method, which does not require the use of molecules containing hydrogen in the film formation gas, is preferable because it can reduce the hydrogen concentration in the insulator 215.
　次に、絶縁体２１５上に絶縁体２１６を成膜する。絶縁体２１６の成膜は、スパッタリング法を用いて行うことが好ましい。成膜ガスに水素を含む分子を用いなくてもよいスパッタリング法を用いることで、絶縁体２１６中の水素濃度を低減できる。ただし、絶縁体２１６の成膜は、スパッタリング法に限られるものではなく、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを適宜用いてもよい。本実施の形態では、絶縁体２１６として、スパッタリング法を用いて酸化シリコンを成膜する。 Next, the insulator 216 is formed on the insulator 215. The insulator 216 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the film formation gas, the hydrogen concentration in the insulator 216 can be reduced. However, the formation of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate. In this embodiment, a silicon oxide film is formed as the insulator 216 by a sputtering method.
　絶縁体２１５、及び絶縁体２１６は、大気に暴露することなく連続して成膜することが好ましい。例えば、マルチチャンバー方式の成膜装置を用いればよい。これにより、絶縁体２１５、及び絶縁体２１６を、膜中の水素を低減して成膜し、さらに、各成膜工程の合間に膜中に水素が混入するのを低減できる。 It is preferable to deposit the insulators 215 and 216 in succession without exposing them to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This allows the insulators 215 and 216 to be deposited with reduced hydrogen in the films, and further reduces the incorporation of hydrogen into the films between each deposition process.
　次に、絶縁体２１６に絶縁体２１５に達する開口を形成する。開口の形成はウェットエッチングを用いてもよいが、ドライエッチングを用いるほうが微細加工には好ましい。また、絶縁体２１５は、絶縁体２１６をエッチングして溝を形成する際のエッチングストッパ膜として機能する絶縁体を選択することが好ましい。例えば、溝を形成する絶縁体２１６に酸化シリコンまたは酸化窒化シリコンを用いた場合は、絶縁体２１５は窒化シリコン、酸化アルミニウム、酸化ハフニウムなどを用いるとよい。 Next, an opening is formed in the insulator 216, reaching the insulator 215. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 215, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form the groove. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, the insulator 215 may be silicon nitride, aluminum oxide, hafnium oxide, or the like.
　開口の形成後に、導電体２０５ａとなる導電膜を成膜する。導電体２０５ａとなる導電膜は、酸素の透過を抑制する機能を有する導電体を含むことが望ましい。例えば、窒化タンタル、窒化タングステン、窒化チタンなどを用いることができる。または、酸素の透過を抑制する機能を有する導電体と、タンタル、タングステン、チタン、モリブデン、アルミニウム、銅、モリブデンタングステン合金との積層膜とすることができる。導電体２０５ａとなる導電膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 After the opening is formed, a conductive film that will become the conductor 205a is formed. The conductive film that will become the conductor 205a desirably contains a conductor that has a function of suppressing oxygen transmission. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, it can be a laminated film of a conductor that has a function of suppressing oxygen transmission and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film that will become the conductor 205a can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc.
　本実施の形態では、導電体２０５ａとなる導電膜として窒化チタンを成膜する。このような金属窒化物を導電体２０５ｂの下層に用いることにより、絶縁体２１６などによって、導電体２０５ｂが酸化されるのを抑制できる。また、導電体２０５ｂとして銅などの拡散しやすい金属を用いても、当該金属が導電体２０５ａから外に拡散するのを防ぐことができる。 In this embodiment, titanium nitride is deposited as the conductive film that becomes conductor 205a. By using such a metal nitride as the lower layer of conductor 205b, it is possible to prevent conductor 205b from being oxidized by insulator 216 and the like. Furthermore, even if a metal that easily diffuses, such as copper, is used as conductor 205b, it is possible to prevent the metal from diffusing out of conductor 205a.
　次に、導電体２０５ｂとなる導電膜を成膜する。導電体２０５ｂとなる導電膜としては、タンタル、タングステン、チタン、モリブデン、アルミニウム、銅、モリブデンタングステン合金などを用いることができる。該導電膜の成膜は、メッキ法、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる。本実施の形態では、導電体２０５ｂとなる導電膜として、タングステンを成膜する。 Next, a conductive film that will become the conductor 205b is formed. Tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy, or the like can be used as the conductive film that will become the conductor 205b. The conductive film can be formed by plating, sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, tungsten is formed as the conductive film that will become the conductor 205b.
　次に、ＣＭＰ処理を行うことで、導電体２０５ａとなる導電膜および導電体２０５ｂとなる導電膜の一部を除去し、絶縁体２１６を露出する（図１１Ａ乃至図１１Ｄ参照）。その結果、開口部のみに、導電体２０５ａおよび導電体２０５ｂが残存する。なお、当該ＣＭＰ処理により、絶縁体２１６の一部が除去される場合がある。 Next, a CMP process is performed to remove a portion of the conductive film that will become conductor 205a and a portion of the conductive film that will become conductor 205b, exposing insulator 216 (see Figures 11A to 11D). As a result, conductor 205a and conductor 205b remain only in the openings. Note that the CMP process may remove a portion of insulator 216.
　次に、絶縁体２１６上及び導電体２０５上に絶縁体２２１を成膜する（図１２Ａ乃至図１２Ｄ参照）。 Next, a film of insulator 221 is formed on insulator 216 and conductor 205 (see Figures 12A to 12D).
　絶縁体２２１は、酸素、水素、及び水に対してバリア性を有する絶縁体を用いればよい。絶縁体２２１は、例えば、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、または、ＡＬＤ法を用いて成膜することができる。本実施の形態では、絶縁体２２１として、ＰＥＡＬＤ法を用いて、窒化シリコンを成膜する。 The insulator 221 may be an insulator having barrier properties against oxygen, hydrogen, and water. The insulator 221 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, a silicon nitride film is formed as the insulator 221 by a PEALD method.
　次に、絶縁体２２１上に絶縁体２２２を成膜する（図１２Ａ乃至図１２Ｄ参照）。 Next, a film of insulator 222 is formed on insulator 221 (see Figures 12A to 12D).
　絶縁体２２２として、アルミニウム及びハフニウムの一方または双方の酸化物を含む絶縁体を成膜するとよい。なお、アルミニウム及びハフニウムの一方または双方の酸化物を含む絶縁体として、例えば、酸化アルミニウム、酸化ハフニウム、または、アルミニウム及びハフニウムを含む酸化物（ハフニウムアルミネート）を用いることが好ましい。または、ハフニウムジルコニウム酸化物を用いることが好ましい。アルミニウム及びハフニウムの一方または双方の酸化物を含む絶縁体は、酸素、水素、及び水に対するバリア性を有する。絶縁体２２２が、水素及び水に対するバリア性を有することで、トランジスタの周辺に設けられた構造体に含まれる水素、及び水が、絶縁体２２２を通じてトランジスタの内側へ拡散することが抑制され、酸化物２３０中の酸素欠損の生成を抑制できる。 As the insulator 222, it is preferable to form a film of an insulator containing one or both of aluminum and hafnium oxides. Note that, as the insulator containing one or both of aluminum and hafnium oxides, it is preferable to use, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Alternatively, it is preferable to use hafnium zirconium oxide. An insulator containing one or both of aluminum and hafnium oxides has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, the hydrogen and water contained in the structure provided around the transistor are prevented from diffusing into the inside of the transistor through the insulator 222, and the generation of oxygen vacancies in the oxide 230 can be suppressed.
　絶縁体２２２は、例えば、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、または、ＡＬＤ法を用いて成膜することができる。本実施の形態では、絶縁体２２２として、ＡＬＤ法を用いて、酸化ハフニウムを成膜する。 The insulator 222 can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, a hafnium oxide film is formed as the insulator 222 by ALD.
　次に、絶縁体２２２上に絶縁膜を成膜し、当該絶縁膜をエッチングして絶縁体２２３を形成する（図１２Ａ乃至図１２Ｄ参照）。絶縁体２２３は、絶縁体２２５を形成するための犠牲層として機能する。絶縁体２２３としては、例えば、絶縁体２１６に用いることができる絶縁体を用いればよい。 Next, an insulating film is formed on the insulator 222, and the insulating film is etched to form the insulator 223 (see Figures 12A to 12D). The insulator 223 functions as a sacrificial layer for forming the insulator 225. As the insulator 223, for example, an insulator that can be used for the insulator 216 may be used.
　絶縁体２２３は、例えば、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、または、ＡＬＤ法を用いて成膜することができる。本実施の形態では、絶縁体２２３として、スパッタリング法を用いて、酸化シリコンを成膜する。 The insulator 223 can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, a silicon oxide film is formed as the insulator 223 by sputtering.
　絶縁体２２３は、リソグラフィ法を用いて島状に加工すればよい。当該加工には、ドライエッチング法またはウェットエッチング法を用いることができる。ドライエッチング法による加工は微細加工に適している。 The insulator 223 can be processed into an island shape using lithography. This can be done using dry etching or wet etching. Dry etching is suitable for fine processing.
　図１２Ｃ及び図１２Ｄに示すように、絶縁体２２３の側面が、絶縁体２２２の上面に対し、垂直または概略垂直になる構成にしてもよい。このような構成にすることで、複数のトランジスタを設ける際に、小面積化、高密度化が可能となる。 As shown in Figures 12C and 12D, the side of the insulator 223 may be configured to be perpendicular or approximately perpendicular to the top surface of the insulator 222. This configuration allows for a smaller area and higher density when providing multiple transistors.
　なお、絶縁体２２３の成膜前に、加熱処理を行ってもよい。当該加熱処理は、減圧下で行い、大気に暴露することなく、連続して絶縁体２２３を成膜してもよい。このような処理を行うことによって、絶縁体２２２の表面に吸着している水分及び水素を除去し、さらに絶縁体２２２中の水分濃度及び水素濃度を低減させることができる。ここで、絶縁体２２２の下面に接して絶縁体２２１を設けておくことで、当該加熱処理によって、絶縁体２２１より下方から水分、または水素などの不純物が侵入するのを防ぐことができる。加熱処理の温度は、１００℃以上４００℃以下が好ましい。本実施の形態では、加熱処理の温度を２５０℃とする。 Note that a heat treatment may be performed before the formation of the insulator 223. The heat treatment may be performed under reduced pressure, and the insulator 223 may be continuously formed without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 222 can be removed, and the moisture concentration and hydrogen concentration in the insulator 222 can be further reduced. Here, by providing the insulator 221 in contact with the lower surface of the insulator 222, the heat treatment can prevent impurities such as moisture or hydrogen from entering from below the insulator 221. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is 250°C.
　次に、絶縁体２２３を覆って、絶縁体２２５となる絶縁膜２２５ｆを成膜する（図１３Ａ乃至図１３Ｄ参照）。絶縁膜２２５ｆは、後の工程で絶縁体２２５となる絶縁膜であり、上述の絶縁体を用いることができる。絶縁膜２２５ｆは、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法を用いて成膜することができる。 Next, insulating film 225f, which will become insulator 225, is formed to cover insulator 223 (see Figures 13A to 13D). Insulating film 225f is an insulating film that will become insulator 225 in a later process, and the insulators described above can be used. Insulating film 225f can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
　絶縁膜２２５ｆは、絶縁体２２３に沿って成膜されるので、被覆性が良好であることが好ましい。よって、絶縁膜２２５ｆは、良好な被覆性を有するＡＬＤ法などを用いて成膜することが好ましい。また、絶縁体２２５は、アスペクト比が高いことが好ましいので、絶縁膜２２５ｆは膜厚が薄いことが好ましい。よって、薄い膜厚での膜厚調整が可能なＡＬＤ法を用いて、絶縁膜２２５ｆを成膜することが好ましい。例えば、絶縁膜２２５ｆとして、熱ＡＬＤ法を用いて酸化ハフニウムを成膜することが好ましい。このように絶縁膜２２５ｆを成膜することで、絶縁膜２２５ｆは、絶縁体２２３の上面及び側面に接して形成される。 Since the insulating film 225f is formed along the insulator 223, it is preferable that the insulating film 225f has good coverage. Therefore, it is preferable that the insulating film 225f is formed using an ALD method or the like that has good coverage. Also, since it is preferable that the insulator 225 has a high aspect ratio, it is preferable that the insulating film 225f has a thin film thickness. Therefore, it is preferable to form the insulating film 225f using an ALD method that allows the film thickness to be adjusted to a thin film thickness. For example, it is preferable to form a film of hafnium oxide as the insulating film 225f using a thermal ALD method. By forming the insulating film 225f in this manner, the insulating film 225f is formed in contact with the upper surface and side surfaces of the insulator 223.
　次に、絶縁膜２２５ｆの一部を異方性エッチングによって除去し、さらに絶縁体２２３を除去する（図１４Ａ乃至図１４Ｄ参照）。これにより、アスペクト比が高い絶縁体２２５を形成することができる。絶縁体２２５を用いることで、占有面積を大きくせずに、トランジスタ２００のチャネル幅を大きくすることができるので、トランジスタ２００の、オン電流、電界効果移動度、及び周波数特性を向上させることができる。また、占有面積を大きくせずに、酸化物２３０ｂと、導電体２４２ａ及び導電体２４２ｂとの接触面積を大きくすることができるので、トランジスタ２００の、オン電流、電界効果移動度、及び周波数特性を向上させることができる。 Next, a portion of the insulating film 225f is removed by anisotropic etching, and then the insulator 223 is removed (see Figures 14A to 14D). This allows the insulator 225 to have a high aspect ratio. By using the insulator 225, the channel width of the transistor 200 can be increased without increasing the occupation area, and therefore the on-current, field effect mobility, and frequency characteristics of the transistor 200 can be improved. In addition, the contact area between the oxide 230b and the conductors 242a and 242b can be increased without increasing the occupation area, and therefore the on-current, field effect mobility, and frequency characteristics of the transistor 200 can be improved.
　図１４Ａ乃至図１４Ｄに示すように、２個の絶縁体２２５を形成することで、絶縁体２２３の大きさに合わせて、２個の絶縁体２２５の距離を設定することができる。よって、絶縁体２２５の距離を小さくし、トランジスタ２００ａ、及びトランジスタ２００ｂの占有面積を低減し、半導体装置、及び記憶装置の高集積化を図ることができる。これにより、記憶装置の記憶容量を増大させることができる。 As shown in Figures 14A to 14D, by forming two insulators 225, the distance between the two insulators 225 can be set to match the size of the insulator 223. Therefore, the distance between the insulators 225 can be reduced, the area occupied by the transistors 200a and 200b can be reduced, and the semiconductor device and memory device can be highly integrated. This can increase the memory capacity of the memory device.
　絶縁膜２２５ｆの異方性エッチングには、ドライエッチング法を用いることが好ましい。 It is preferable to use a dry etching method for anisotropic etching of the insulating film 225f.
　ドライエッチング処理用のエッチングガスとしては、ハロゲンを含むエッチングガスを用いることができ、具体的には、フッ素、塩素、及び臭素のうち、一または複数を含むエッチングガスを用いることができる。例えば、エッチングガスとして、Ｃ４Ｆ６ガス、Ｃ５Ｆ６ガス、Ｃ４Ｆ８ガス、ＣＦ４ガス、ＳＦ６ガス、ＣＨＦ３ガス、ＣＨ２Ｆ２ガス、Ｃｌ２ガス、ＢＣｌ３ガス、ＳｉＣｌ４ガス、またはＢＢｒ３ガスなどを単独または２以上のガスを混合して用いることができる。また、上記のエッチングガスに酸素ガス、炭酸ガス、窒素ガス、ヘリウムガス、アルゴンガス、水素ガス、または炭化水素ガスなどを適宜添加することができる。また、ドライエッチング処理の被処理物によっては、ハロゲンガスを含まず、炭化水素ガスまたは水素ガスを含むガスを、エッチングガスとして用いることができる。エッチングガスに用いる炭化水素としては、メタン（ＣＨ４）、エタン（Ｃ２Ｈ６）、プロパン（Ｃ３Ｈ８）、ブタン（Ｃ４Ｈ１０）、エチレン（Ｃ２Ｈ４）、プロピレン（Ｃ３Ｈ６）、アセチレン（Ｃ２Ｈ２）、およびプロピン（Ｃ３Ｈ４）の一または複数を用いることができる。エッチング条件は、エッチングする対象に合わせて適宜設定することができる。 As the etching gas for the dry etching process, an etching gas containing halogen can be used, specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, as the etching gas, C4F6 gas , C5F6 gas , C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, CH2F2 gas, Cl2 gas, BCl3 gas, SiCl4 gas, or BBr3 gas can be used alone or in a mixture of two or more gases. In addition, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be appropriately added to the above etching gas. In addition, depending on the object to be treated in the dry etching process, a gas containing no halogen gas but a hydrocarbon gas or hydrogen gas can be used as the etching gas. The hydrocarbon used in the etching gas may be one or more of methane ( CH4 ), ethane ( C2H6 ) , propane ( C3H8 ), butane ( C4H10 ), ethylene (C2H4), propylene (C3H6), acetylene (C2H2), and propyne (C3H4 ) . The etching conditions may be appropriately set according to the object to be etched.
　ドライエッチング装置としては、平行平板型電極を有する容量結合型プラズマ（ＣＣＰ：Ｃａｐａｃｉｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ）エッチング装置を用いることができる。平行平板型電極を有する容量結合型プラズマエッチング装置は、平行平板型電極の一方の電極に高周波電圧を印加する構成でもよい。または平行平板型電極の一方の電極に複数の異なった高周波電圧を印加する構成でもよい。または平行平板型電極それぞれに同じ周波数の高周波電圧を印加する構成でもよい。または平行平板型電極それぞれに周波数の異なる高周波電圧を印加する構成でもよい。または高密度プラズマ源を有するドライエッチング装置を用いることができる。高密度プラズマ源を有するドライエッチング装置は、例えば、誘導結合型プラズマ（ＩＣＰ：Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ）エッチング装置などを用いることができる。エッチング装置は、エッチングする対象に合わせて適宜設定することができる。 As the dry etching device, a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used. The capacitively coupled plasma etching device having parallel plate electrodes can be configured to apply a high frequency voltage to one of the parallel plate electrodes. Alternatively, it can be configured to apply a plurality of different high frequency voltages to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply high frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching device having a high density plasma source can be used. As the dry etching device having a high density plasma source, for example, an inductively coupled plasma (ICP) etching device can be used. The etching device can be appropriately set according to the object to be etched.
　例えば、絶縁膜２２５ｆに酸化ハフニウムを用いる場合、ＣＣＰエッチング装置で、エッチングガスとして、Ｃ４Ｆ８、Ｈ２、及びＡｒの混合ガスを用いればよい。 For example, when hafnium oxide is used for the insulating film 225f, a mixed gas of C 4 F 8 , H 2 , and Ar may be used as an etching gas in a CCP etching apparatus.
　なお、絶縁体２２３の除去は、上記加工には、ドライエッチング法またはウェットエッチング法を用いることができる。例えば、絶縁体２２３は、ウェットエッチング法を用いて除去すればよい。 The removal of the insulator 223 can be performed by dry etching or wet etching. For example, the insulator 223 can be removed by wet etching.
　また、絶縁体２２５は、異方性エッチングで形成した時点では、絶縁体２２３の側面に接してサイドウォール状に形成される。つまり、絶縁体２２３を囲んで周状に絶縁体２２５が形成される。周状に絶縁体２２５を維持して半導体装置を作製すると、図５Ａ乃至図５Ｄに示すように、絶縁体２２５がトランジスタ２００ａとトランジスタ２００ｂで一体物になる。 Insulator 225, when formed by anisotropic etching, is formed in a sidewall shape in contact with the side surface of insulator 223. In other words, insulator 225 is formed in a circumferential shape surrounding insulator 223. When a semiconductor device is manufactured while maintaining insulator 225 in a circumferential shape, insulator 225 becomes an integral part of transistors 200a and 200b, as shown in Figures 5A to 5D.
　ここで、図１４に示す構成では、サイドウォール状絶縁体のうち、半導体装置の構成上必要ない部分を除去して絶縁体２２５を形成している。このような絶縁体２２５を形成する場合、絶縁膜２２５ｆの異方性エッチングを行う前に、絶縁体２２５の不要な部分を先にエッチングする構成にしてもよい。 In the configuration shown in FIG. 14, the insulator 225 is formed by removing the portion of the sidewall-shaped insulator that is not necessary for the configuration of the semiconductor device. When forming such an insulator 225, the unnecessary portion of the insulator 225 may be etched first before anisotropic etching of the insulating film 225f is performed.
　次に、絶縁体２２２及び絶縁体２２５上に、酸化膜２３０ａｆを成膜し、酸化膜２３０ａｆ上に、酸化膜２３０ｂｆを成膜する（図１５Ａ乃至図１５Ｄ参照）。酸化膜２３０ａｆとしては、上記酸化物２３０ａに対応する金属酸化物を、酸化膜２３０ｂｆとしては、上記酸化物２３０ｂに対応する金属酸化物を、用いればよい。なお、酸化膜２３０ａｆ及び酸化膜２３０ｂｆは、大気環境にさらさずに連続して成膜することが好ましい。大気開放せずに成膜することで、酸化膜２３０ａｆ上及び酸化膜２３０ｂｆ上に大気環境からの不純物または水分が付着することを防ぐことができ、酸化膜２３０ａｆと酸化膜２３０ｂｆとの界面または界面近傍を清浄に保つことができる。 Next, an oxide film 230af is formed on the insulator 222 and the insulator 225, and an oxide film 230bf is formed on the oxide film 230af (see FIGS. 15A to 15D). A metal oxide corresponding to the oxide 230a may be used as the oxide film 230af, and a metal oxide corresponding to the oxide 230b may be used as the oxide film 230bf. It is preferable that the oxide films 230af and 230bf are successively formed without being exposed to the air environment. By forming the films without exposing them to the air, it is possible to prevent impurities or moisture from the air environment from adhering to the oxide films 230af and 230bf, and it is possible to keep the interface or the vicinity of the interface between the oxide films 230af and 230bf clean.
　酸化膜２３０ａｆ及び酸化膜２３０ｂｆは、それぞれ、例えば、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、または、ＡＬＤ法を用いて成膜することができる。 Oxide film 230af and oxide film 230bf can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
　酸化膜２３０ａｆ及び酸化膜２３０ｂｆの成膜は、被覆性の良好なＡＬＤ法を用いることが好ましい。ＡＬＤ法を用いることで、絶縁体２２５の側面に、酸化膜２３０ａｆ及び酸化膜２３０ｂｆを被覆性良く成膜することができる。これにより、トランジスタ２００において、絶縁体２２５のＡ３側の側面、及びＡ４側の側面にもチャネル形成領域を設けることができるので、トランジスタ２００のチャネル幅を大きくすることができる。よって、トランジスタ２００の電界効果移動度、オン電流、及び周波数特性を良好にすることができる。 The oxide film 230af and the oxide film 230bf are preferably formed by the ALD method, which has good coverage. By using the ALD method, the oxide film 230af and the oxide film 230bf can be formed with good coverage on the side surface of the insulator 225. This allows channel formation regions to be provided on the side surface of the insulator 225 on the A3 side and the A4 side in the transistor 200, so that the channel width of the transistor 200 can be increased. This allows the field effect mobility, on-current, and frequency characteristics of the transistor 200 to be improved.
　ここで、ＡＬＤ法は、原料ガスの導入量によって、得られる膜の組成を制御することができる。例えば、ＡＬＤ法では、原料ガスの導入量、導入回数（パルス回数ともいう）、１パルスに要する時間（パルス時間ともいう）などを調節することによって、任意の組成の酸化膜２３０ａｆ及び酸化膜２３０ｂｆを成膜することができる。また、例えば、ＡＬＤ法では、成膜しながら原料ガスを変化させることによって、組成が連続的に変化した酸化膜２３０ａｆ及び酸化膜２３０ｂｆを成膜することができる。原料ガスを変化させながら成膜する場合、複数の成膜室を用いて成膜する場合と比べて、搬送及び圧力調整に掛かる時間を要さない分、成膜に掛かる時間を短くすることができる。したがって、半導体装置の生産性を高めることができる場合がある。 Here, the ALD method can control the composition of the film obtained by adjusting the amount of raw material gas introduced. For example, the ALD method can form oxide film 230af and oxide film 230bf of any composition by adjusting the amount of raw material gas introduced, the number of introductions (also called the number of pulses), the time required for one pulse (also called the pulse time), etc. Also, for example, the ALD method can form oxide film 230af and oxide film 230bf whose composition changes continuously by changing the raw material gas while forming the film. When forming a film while changing the raw material gas, the time required for film formation can be shortened compared to forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.
　酸化膜２３０ａｆは、ＡＬＤ法を用いて、Ｉｎ：Ｇａ：Ｚｎ＝１：３：２［原子数比］の金属酸化物層、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］の金属酸化物層、または、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］の金属酸化物層を成膜すればよい。また、酸化膜２３０ｂｆは、ＡＬＤ法を用いて、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］の金属酸化物層、またはＩｎ：Ｚｎ＝４：１［原子数比］の金属酸化物層を成膜すればよい。また、酸化膜２３０ａｆ、及び酸化膜２３０ｂｆは、上記金属酸化物層の積層構造にしてもよい。例えば、酸化膜２３０ｂｆを、Ｉｎ：Ｚｎ＝４：１［原子数比］の金属酸化物層、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］の金属酸化物層の順に積層した積層膜にしてもよい。なお、上記酸化膜２３０ｂｆにおいて、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］の金属酸化物層の代わりに、Ｉｎ：Ｇａ：Ｚｎ＝１：３：２［原子数比］の金属酸化物層、またはＩｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］の金属酸化物層を用いてもよい。 The oxide film 230af may be formed by using the ALD method as a metal oxide layer having an In:Ga:Zn=1:3:2 [atomic ratio], a metal oxide layer having an In:Ga:Zn=1:3:4 [atomic ratio], or a metal oxide layer having an In:Ga:Zn=1:1:1 [atomic ratio]. The oxide film 230bf may be formed by using the ALD method as a metal oxide layer having an In:Ga:Zn=1:1:1 [atomic ratio], or a metal oxide layer having an In:Zn=4:1 [atomic ratio]. The oxide film 230af and the oxide film 230bf may be formed as a laminated structure of the above metal oxide layers. For example, the oxide film 230bf may be formed as a laminated film in which a metal oxide layer having an In:Zn=4:1 [atomic ratio] and a metal oxide layer having an In:Ga:Zn=1:1:1 [atomic ratio] are laminated in this order. In addition, in the oxide film 230bf, instead of the metal oxide layer with In:Ga:Zn = 1:1:1 [atomic ratio], a metal oxide layer with In:Ga:Zn = 1:3:2 [atomic ratio] or a metal oxide layer with In:Ga:Zn = 1:3:4 [atomic ratio] may be used.
　また、酸化膜２３０ａｆ及び酸化膜２３０ｂｆの成膜はスパッタリング法を用いてもよい。例えば、酸化膜２３０ａｆ及び酸化膜２３０ｂｆをスパッタリング法によって成膜する場合は、スパッタリングガスとして、酸素、または、酸素と貴ガスの混合ガスを用いる。スパッタリングガスに含まれる酸素の割合を高めることで、成膜される酸化膜中の過剰酸素を増やすことができる。また、上記の酸化膜をスパッタリング法によって成膜する場合は、Ｉｎ−Ｍ−Ｚｎ酸化物ターゲットなどを用いることができる。 The oxide film 230af and the oxide film 230bf may be formed by sputtering. For example, when the oxide film 230af and the oxide film 230bf are formed by sputtering, oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the oxide film to be formed can be increased. When the oxide film is formed by sputtering, an In-M-Zn oxide target or the like can be used.
　また、酸化膜２３０ｂｆをスパッタリング法で形成する場合、スパッタリングガスに含まれる酸素の割合を、３０％を超えて１００％以下、好ましくは７０％以上１００％以下として成膜すると、酸素過剰型の酸化物半導体が形成される。酸素過剰型の酸化物半導体をチャネル形成領域に用いたトランジスタは、比較的高い信頼性が得られる。ただし、本発明の一態様はこれに限定されない。酸化膜２３０ｂｆをスパッタリング法で形成する場合、スパッタリングガスに含まれる酸素の割合を１％以上３０％以下、好ましくは５％以上２０％以下として成膜すると、酸素欠乏型の酸化物半導体が形成される。酸素欠乏型の酸化物半導体をチャネル形成領域に用いたトランジスタは、比較的高い電界効果移動度が得られる。また、基板を加熱しながら成膜を行うことによって、当該酸化膜の結晶性を向上させることができる。 When the oxide film 230bf is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and not more than 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor in a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited to this. When the oxide film 230bf is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%,. A transistor using an oxygen-deficient oxide semiconductor in a channel formation region can have relatively high field effect mobility. In addition, the crystallinity of the oxide film can be improved by forming the film while heating the substrate.
　本実施の形態では、酸化膜２３０ａｆを、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝１：３：２［原子数比］の酸化物ターゲット、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］の酸化物ターゲット、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］の酸化物ターゲット、またはＩｎ：Ｇａ：Ｚｎ＝１：１：１．２［原子数比］の酸化物ターゲットを用いて成膜する。また、酸化膜２３０ｂｆを、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］の酸化物ターゲット、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１．２［原子数比］の酸化物ターゲット、Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］の酸化物ターゲット、Ｉｎ：Ｇａ：Ｚｎ＝１：１：２［原子数比］の酸化物ターゲット、またはＩｎ：Ｚｎ＝４：１［原子数比］の酸化物ターゲットを用いて成膜する。なお、各酸化膜は、成膜条件、及び原子数比を適宜選択することで、酸化物２３０ａ、及び酸化物２３０ｂに求める特性に合わせて形成するとよい。 In this embodiment, the oxide film 230af is formed by sputtering using an oxide target with an In:Ga:Zn=1:3:2 atomic ratio, an oxide target with an In:Ga:Zn=1:3:4 atomic ratio, an oxide target with an In:Ga:Zn=1:1:1 atomic ratio, or an oxide target with an In:Ga:Zn=1:1:1.2 atomic ratio. The oxide film 230bf is formed by sputtering using an oxide target with an In:Ga:Zn=1:1:1 atomic ratio, an oxide target with an In:Ga:Zn=1:1:1.2 atomic ratio, an oxide target with an In:Ga:Zn=4:2:4.1 atomic ratio, an oxide target with an In:Ga:Zn=1:1:2 atomic ratio, or an oxide target with an In:Zn=4:1 atomic ratio. Each oxide film can be formed according to the desired characteristics of oxide 230a and oxide 230b by appropriately selecting the film formation conditions and atomic ratio.
　また、例えば、酸化膜２３０ａｆをスパッタリング法で成膜し、酸化膜２３０ｂｆをＡＬＤ法で成膜してもよい。ここで、酸化膜２３０ａｆおよび酸化膜２３０ｂｆのいずれか一方または両方を積層構造にしてもよい。例えば、酸化膜２３０ａｆは、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］の酸化物ターゲット、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１．２［原子数比］の酸化物ターゲット、Ｉｎ：Ｇａ：Ｚｎ＝１：３：２［原子数比］の酸化物ターゲット、またはＩｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］の酸化物ターゲットのいずれかを用いて、スパッタリング法で成膜すればよい。 Also, for example, the oxide film 230af may be formed by a sputtering method, and the oxide film 230bf may be formed by an ALD method. Here, either or both of the oxide film 230af and the oxide film 230bf may have a laminated structure. For example, the oxide film 230af may be formed by a sputtering method using an oxide target with an In:Ga:Zn=1:1:1 [atomic ratio], an oxide target with an In:Ga:Zn=1:1:1.2 [atomic ratio], an oxide target with an In:Ga:Zn=1:3:2 [atomic ratio], or an oxide target with an In:Ga:Zn=1:3:4 [atomic ratio].
　また、酸化膜２３０ｂｆは、ＡＬＤ法を用いて成膜した、上述の金属酸化物層を用いることができる。例えば、酸化膜２３０ｂｆは、Ｉｎ：Ｚｎ＝４：１［原子数比］の金属酸化物層、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］の金属酸化物層の順に積層した積層膜を成膜すればよい。 The oxide film 230bf may be the above-mentioned metal oxide layer formed using the ALD method. For example, the oxide film 230bf may be a laminated film formed by stacking a metal oxide layer having an In:Zn=4:1 atomic ratio and a metal oxide layer having an In:Ga:Zn=1:1:1 atomic ratio in that order.
　酸化膜２３０ａｆをスパッタリング法で成膜することで結晶性を高めることができる。例えば、酸化膜２３０ａｆの結晶性を高めてから、酸化膜２３０ａｆ上に、酸化膜２３０ｂｆを成膜することで、酸化膜２３０ｂｆの一部または全部を結晶化することができる。すなわち、酸化膜２３０ａｆの結晶性を高めることで、酸化膜２３０ｂｆの結晶性も高めることが可能となる。例えば、酸化膜２３０ａｆが、ＣＡＡＣ構造の酸化物半導体膜の場合、酸化膜２３０ａｆ上に形成する酸化膜２３０ｂｆもＣＡＡＣ構造の酸化物半導体とすることができる。 The crystallinity of the oxide film 230af can be increased by forming the oxide film 230af by sputtering. For example, by increasing the crystallinity of the oxide film 230af and then forming the oxide film 230bf on the oxide film 230af, a part or all of the oxide film 230bf can be crystallized. In other words, by increasing the crystallinity of the oxide film 230af, it is possible to increase the crystallinity of the oxide film 230bf as well. For example, if the oxide film 230af is an oxide semiconductor film with a CAAC structure, the oxide film 230bf formed on the oxide film 230af can also be an oxide semiconductor with a CAAC structure.
　また、ＡＬＤ法を用いて酸化膜２３０ｂｆを成膜することで、薄い膜を制御性良く成膜することができる。これにより、酸化膜２３０ｂｆを、設計通りの薄い膜厚にすることができる。このような、酸化膜２３０ａｆ及び酸化膜２３０ｂｆを用いることで、トランジスタ２００の電気特性の向上、及び信頼性の向上を図ることができる。 Furthermore, by forming the oxide film 230bf using the ALD method, a thin film can be formed with good controllability. This allows the oxide film 230bf to have a thin film thickness as designed. By using such oxide film 230af and oxide film 230bf, it is possible to improve the electrical characteristics and reliability of the transistor 200.
　なお、酸化膜２３０ａｆ、及び酸化膜２３０ｂｆを、大気に暴露することなく、成膜することが好ましい。例えば、マルチチャンバー方式の成膜装置を用いることが好ましい。これにより、酸化膜２３０ａｆ、及び酸化膜２３０ｂｆについて、各成膜工程の合間に膜中に水素が混入することを低減できる。 It is preferable to form the oxide film 230af and the oxide film 230bf without exposing them to the atmosphere. For example, it is preferable to use a multi-chamber type film forming apparatus. This can reduce the inclusion of hydrogen in the oxide film 230af and the oxide film 230bf between each film forming process.
　次に、加熱処理を行うことが好ましい。加熱処理は、酸化膜２３０ａｆ、及び酸化膜２３０ｂｆが多結晶化しない温度範囲で行えばよい。加熱処理の温度は、１００℃以上、２５０℃以上、または３５０℃以上であり、かつ、６５０℃以下、６００℃以下、または５５０℃以下であると好ましい。 Next, it is preferable to perform a heat treatment. The heat treatment may be performed within a temperature range in which the oxide film 230af and the oxide film 230bf do not become polycrystallized. The temperature of the heat treatment is preferably 100°C or higher, 250°C or higher, or 350°C or higher, and 650°C or lower, 600°C or lower, or 550°C or lower.
　なお、加熱処理は、窒素ガスもしくは不活性ガスの雰囲気、または酸化性ガスを１０ｐｐｍ以上、１％以上、もしくは１０％以上含む雰囲気で行う。例えば、窒素ガスと酸素ガスの混合雰囲気で加熱処理をする場合、酸素ガスを２０％程度にすることが好ましい。また、加熱処理は減圧状態で行ってもよい。または、窒素ガスもしくは不活性ガスの雰囲気で加熱処理した後に、脱離した酸素を補うために酸化性ガスを１０ｐｐｍ以上、１％以上、または１０％以上含む雰囲気で加熱処理を行ってもよい。 The heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to set the oxygen gas concentration at about 20%. The heat treatment may be carried out under reduced pressure. Alternatively, after the heat treatment in a nitrogen gas or inert gas atmosphere, the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the oxygen that has been released.
　また、上記加熱処理で用いるガスは、高純度化されていることが好ましい。例えば、上記加熱処理で用いるガスに含まれる水分量は、１ｐｐｂ以下が好ましく、０．１ｐｐｂ以下がより好ましく、０．０５ｐｐｂ以下がさらに好ましい。高純度化されたガスを用いて加熱処理を行うことで、酸化膜２３０ａｆ、及び酸化膜２３０ｂｆなどに水分等が取り込まれることを可能な限り防ぐことができる。 In addition, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into the oxide film 230af and the oxide film 230bf as much as possible.
　本実施の形態では、加熱処理として、窒素ガスと酸素ガスの流量比を４：１として、４５０℃の温度で１時間の処理を行う。このような酸素ガスを含む加熱処理によって、酸化膜２３０ａｆ及び酸化膜２３０ｂｆ中の炭素、水、水素などの不純物を低減できる。このように膜中の不純物を低減することで、酸化膜２３０ａｆ及び酸化膜２３０ｂｆの結晶性を向上させ、より密度の高い、緻密な構造にすることができる。これにより、酸化膜２３０ａｆ及び酸化膜２３０ｂｆ中の結晶領域を増大させ、酸化膜２３０ａｆ及び酸化膜２３０ｂｆ中における、結晶領域の面内ばらつきを低減できる。よって、トランジスタの電気特性の面内ばらつきを低減できる。 In this embodiment, the heat treatment is performed at a temperature of 450° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas of 4:1. This heat treatment including oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 230af and the oxide film 230bf. By reducing the impurities in the film in this way, the crystallinity of the oxide film 230af and the oxide film 230bf can be improved, resulting in a denser and more compact structure. This increases the crystalline region in the oxide film 230af and the oxide film 230bf, and reduces the in-plane variation of the crystalline region in the oxide film 230af and the oxide film 230bf. This reduces the in-plane variation of the electrical characteristics of the transistor.
　また、加熱処理を行うことで、絶縁体２１６、酸化膜２３０ａｆ、及び酸化膜２３０ｂｆ中の水素が絶縁体２２５及び絶縁体２２２内に吸い取られる。別言すると、絶縁体２１６、酸化膜２３０ａｆ、及び酸化膜２３０ｂｆ中の水素が、絶縁体２２５及び絶縁体２２２に拡散する。従って、絶縁体２２５及び絶縁体２２２の水素濃度は高くなるが、絶縁体２１６、酸化膜２３０ａｆ、及び酸化膜２３０ｂｆ中のそれぞれの水素濃度は低下する。なお、絶縁体２２２の下面に接して絶縁体２２１を設けておくことで、当該加熱処理において、絶縁体２２１より下方から水分、または水素などの不純物が侵入するのを防ぐことができる。 In addition, by performing the heat treatment, hydrogen in the insulator 216, the oxide film 230af, and the oxide film 230bf is absorbed into the insulator 225 and the insulator 222. In other words, hydrogen in the insulator 216, the oxide film 230af, and the oxide film 230bf diffuses into the insulator 225 and the insulator 222. Therefore, the hydrogen concentration in the insulator 225 and the insulator 222 increases, but the hydrogen concentration in the insulator 216, the oxide film 230af, and the oxide film 230bf decreases. Note that by providing the insulator 221 in contact with the lower surface of the insulator 222, it is possible to prevent impurities such as moisture or hydrogen from entering from below the insulator 221 during the heat treatment.
　特に、酸化膜２３０ａｆ及び酸化膜２３０ｂｆ（後の酸化物２３０ａ及び酸化物２３０ｂ）は、トランジスタ２００のチャネル形成領域として機能する。水素濃度が低減された酸化膜２３０ａｆ及び酸化膜２３０ｂｆを用いて形成されたトランジスタ２００は、良好な信頼性を有するため好ましい。 In particular, oxide film 230af and oxide film 230bf (later oxide 230a and oxide 230b) function as a channel formation region of transistor 200. Transistor 200 formed using oxide film 230af and oxide film 230bf in which the hydrogen concentration is reduced is preferable because it has good reliability.
　次に、酸化膜２３０ｂｆ上に、導電膜２４２ｆを成膜する（図１５Ａ乃至図１５Ｄ参照）。導電膜２４２ｆとしては、上記導電体２４２ａ、２４２ｂに対応する導電体を用いればよい。酸化膜２３０ｂｆの成膜後に、エッチング工程などを挟まずに、酸化膜２３０ｂｆ上に接して導電膜２４２ｆを成膜することで、酸化膜２３０ｂｆの上面を、導電膜２４２ｆで保護することができる。これにより、トランジスタを構成する酸化物２３０に不純物が拡散するのを低減することができるので、半導体装置の電気特性及び信頼性の向上を図ることができる。 Next, a conductive film 242f is formed on the oxide film 230bf (see Figures 15A to 15D). Conductors corresponding to the above-mentioned conductors 242a and 242b may be used as the conductive film 242f. After the oxide film 230bf is formed, the conductive film 242f is formed on and in contact with the oxide film 230bf without an etching process or the like, so that the upper surface of the oxide film 230bf can be protected by the conductive film 242f. This can reduce the diffusion of impurities into the oxide 230 that constitutes the transistor, thereby improving the electrical characteristics and reliability of the semiconductor device.
　導電膜２４２ｆは、例えば、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法を用いて成膜することができる。ＡＬＤ法を用いることで、絶縁体２２５の側面に、導電膜２４２ｆを被覆性良く成膜することができる。例えば、導電膜２４２ｆとして、ＡＬＤ法を用いて窒化タンタルを成膜すればよい。このように、被覆性良く導電膜２４２ｆを成膜することで、占有面積を大きくせずに、酸化物２３０ｂと、導電体２４２ａ及び導電体２４２ｂとの接触面積を大きくすることができる。これにより、トランジスタ２００の、オン電流、及び周波数特性を向上させることができる。 The conductive film 242f can be formed, for example, by sputtering, CVD, MBE, PLD, or ALD. By using the ALD method, the conductive film 242f can be formed with good coverage on the side surface of the insulator 225. For example, tantalum nitride can be formed as the conductive film 242f by the ALD method. By forming the conductive film 242f with good coverage in this way, the contact area between the oxide 230b and the conductors 242a and 242b can be increased without increasing the occupied area. This can improve the on-current and frequency characteristics of the transistor 200.
　次に、リソグラフィ法を用いて、酸化膜２３０ａｆ、酸化膜２３０ｂｆ、及び導電膜２４２ｆを島状に加工して、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２Ａを形成する（図１６Ａ乃至図１６Ｄ参照）。 Next, the oxide film 230af, the oxide film 230bf, and the conductive film 242f are processed into an island shape using lithography to form the oxide 230a, the oxide 230b, and the conductor 242A (see Figures 16A to 16D).
　これにより、トランジスタ２００ａを形成する、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２Ａと、トランジスタ２００ｂを形成する、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２Ａと、が分離される。このとき、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２Ａは、トランジスタ２００ａを形成する絶縁体２２５と、トランジスタ２００ｂを形成する絶縁体２２５を、それぞれ覆って形成されることが好ましい。 As a result, the oxide 230a, oxide 230b, and conductor 242A that form the transistor 200a are separated from the oxide 230a, oxide 230b, and conductor 242A that form the transistor 200b. At this time, it is preferable that the oxide 230a, oxide 230b, and conductor 242A are formed so as to cover the insulator 225 that forms the transistor 200a and the insulator 225 that forms the transistor 200b, respectively.
　上記加工には、ドライエッチング法またはウェットエッチング法を用いることができる。ドライエッチング法による加工は微細加工に適している。なお、ドライエッチング法の条件、及びドライエッチング装置については、上記の記載を参照することができる。また、酸化膜２３０ａｆ、酸化膜２３０ｂｆ、及び導電膜２４２ｆの加工は、それぞれ異なる条件で行ってもよい。 The above processing can be performed using a dry etching method or a wet etching method. Processing using the dry etching method is suitable for fine processing. Note that the above description can be referred to for the conditions of the dry etching method and the dry etching apparatus. In addition, the processing of the oxide film 230af, the oxide film 230bf, and the conductive film 242f may be performed under different conditions.
　ここで、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２Ａを一括で島状に加工することが好ましい。ここで、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２Ａの二つ以上の側端部が、互いに一致または概略一致する。このような構成にすることで、本発明の一態様に係る半導体装置の工程数を削減することができる。よって、生産性の良好な半導体装置の作製方法を提供することができる。 Here, it is preferable to process oxide 230a, oxide 230b, and conductor 242A into an island shape collectively. Here, two or more side ends of oxide 230a, oxide 230b, and conductor 242A coincide or approximately coincide with each other. By adopting such a configuration, the number of steps for manufacturing a semiconductor device according to one embodiment of the present invention can be reduced. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.
　また、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２Ａは、少なくとも一部が導電体２０５と重なるように形成する。また、絶縁体２２２が、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２Ａと重畳しない領域において、絶縁体２２２が露出する。 Furthermore, oxide 230a, oxide 230b, and conductor 242A are formed so that at least a portion of them overlaps with conductor 205. Furthermore, insulator 222 is exposed in the region where insulator 222 does not overlap with oxide 230a, oxide 230b, and conductor 242A.
　図１６Ｂに示すように、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２Ａの側面が、絶縁体２２２の上面に対し、垂直または概略垂直になる構成にしてもよい。このような構成にすることで、複数のトランジスタを設ける際に、小面積化、高密度化が可能となる。 As shown in FIG. 16B, the side surfaces of oxide 230a, oxide 230b, and conductor 242A may be configured to be perpendicular or approximately perpendicular to the top surface of insulator 222. By using such a configuration, it is possible to reduce the area and increase the density when providing multiple transistors.
　ただし、上記に限られず、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２Ａの側面がテーパー形状になっていてもよい。酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２Ａの側面のテーパー角は、例えば、６０°以上９０°未満であってもよい。このように側面をテーパー形状にすることで、これより後の工程において、絶縁体２７５などの被覆性が向上し、鬆などの欠陥を低減できる。 However, without being limited to the above, the side surfaces of oxide 230a, oxide 230b, and conductor 242A may be tapered. The taper angle of the side surfaces of oxide 230a, oxide 230b, and conductor 242A may be, for example, 60° or more and less than 90°. By tapering the side surfaces in this manner, the coverage of insulator 275 and the like is improved in subsequent processes, and defects such as voids can be reduced.
　なお、リソグラフィ法では、まず、マスクを介してレジストを露光する。次に、露光された領域を、現像液を用いて除去または残存させてレジストマスクを形成する。次に、当該レジストマスクを介してエッチング処理することで、導電体、半導体、または絶縁体などを所望の形状に加工することができる。例えば、ＫｒＦエキシマレーザ光、ＡｒＦエキシマレーザ光、ＥＵＶ（Ｅｘｔｒｅｍｅ　Ｕｌｔｒａｖｉｏｌｅｔ）光などを用いて、レジストを露光することでレジストマスクを形成することができる。また、基板と投影レンズとの間に液体（例えば水）を満たして露光する、液浸技術を用いてもよい。また、前述した光に代えて、電子ビームまたはイオンビームを用いてもよい。なお、電子ビームまたはイオンビームを用いる場合には、マスクを用いなくてもよい場合がある。 In the lithography method, the resist is first exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, a conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. In addition, a liquid immersion technique can be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed. In addition, an electron beam or an ion beam can be used instead of the light described above. In addition, when an electron beam or an ion beam is used, a mask may not be used.
　なお、加工後に不要になったレジストマスクは、酸素プラズマを用いたアッシング（以下、酸素プラズマ処理と呼ぶ場合がある。）などのドライエッチング処理を行う、ウェットエッチング処理を行う、ドライエッチング処理後にウェットエッチング処理を行う、またはウェットエッチング処理後にドライエッチング処理を行うことで、除去することができる。 In addition, the resist mask that is no longer needed after processing can be removed by performing a dry etching process such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.
　さらに、レジストマスクの下に絶縁体または導電体からなるハードマスクを用いてもよい。ハードマスクを用いる場合、導電膜２４２ｆ上にハードマスク材料となる絶縁膜または導電膜を形成し、その上にレジストマスクを形成し、ハードマスク材料をエッチングすることで所望の形状のハードマスクを形成することができる。導電膜２４２ｆなどのエッチングは、レジストマスクを除去してから行ってもよいし、レジストマスクを残したまま行ってもよい。後者の場合、エッチング中にレジストマスクが消失することがある。酸化膜２３０ｂｆなどのエッチング後にハードマスクをエッチングにより除去してもよい。一方、ハードマスクの材料が後工程に影響が無い、あるいは後工程で利用できる場合、必ずしもハードマスクを除去する必要は無い。 Furthermore, a hard mask made of an insulator or conductor may be used under the resist mask. When using a hard mask, an insulating film or conductive film that will be the hard mask material is formed on the conductive film 242f, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of the desired shape. Etching of the conductive film 242f etc. may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the oxide film 230bf etc. On the other hand, if the material of the hard mask does not affect the later process or can be used in the later process, it is not necessarily necessary to remove the hard mask.
　また、被加工物とレジストマスクの間に、ＳＯＣ（Ｓｐｉｎ　Ｏｎ　Ｃａｒｂｏｎ）膜、及びＳＯＧ（Ｓｐｉｎ　Ｏｎ　Ｇｌａｓｓ）膜を成膜する構成にしてもよい。ＳＯＣ膜及びＳＯＧ膜をマスクとして用いることで、レジストマスクとの密着性を向上させ、マスクパターンの耐久性を向上させることができる。例えば、被加工物の上に、ＳＯＣ膜、ＳＯＧ膜、レジストマスクの順に成膜してリソグラフィ法を行うことができる。 Also, a configuration may be adopted in which an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film are formed between the workpiece and the resist mask. By using the SOC film and the SOG film as a mask, it is possible to improve adhesion with the resist mask and improve the durability of the mask pattern. For example, a SOC film, an SOG film, and a resist mask can be formed in this order on the workpiece, and then lithography can be performed.
　なお、図１６Ａ乃至図１６Ｄに示す工程において、導電膜２４２ｆを導電体２４２ａと導電体２４２ｂに分断し、導電体２４２ａと導電体２４２ｂの分断に用いたマスクを用いて、酸化膜２３０ａｆ、及び酸化膜２３０ｂｆを異方性エッチングしてもよい。このような構成にすることで、図７Ａ乃至図７Ｄ、及び図８に示すように、導電体２４２ａ及び導電体２４２ｂと重畳しない領域において、酸化物２３０ａ及び酸化物２３０ｂを、絶縁体２２５に対してサイドウォール状に形成することができる。 16A to 16D, the conductive film 242f may be divided into the conductor 242a and the conductor 242b, and the oxide film 230af and the oxide film 230bf may be anisotropically etched using the mask used to divide the conductor 242a and the conductor 242b. With this configuration, the oxide 230a and the oxide 230b can be formed in a sidewall shape with respect to the insulator 225 in the regions that do not overlap with the conductor 242a and the conductor 242b, as shown in FIGS. 7A to 7D and 8.
　次に、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２Ａを覆って、絶縁体２７５を成膜し、さらに絶縁体２７５上に絶縁体２８０を成膜する（図１７Ａ乃至図１７Ｄ参照）。絶縁体２７５、及び絶縁体２８０としては、上述の絶縁体を用いればよい。 Next, a film of insulator 275 is formed to cover oxide 230a, oxide 230b, and conductor 242A, and then a film of insulator 280 is formed on insulator 275 (see Figures 17A to 17D). The insulators described above may be used as insulator 275 and insulator 280.
　ここで、絶縁体２７５は、絶縁体２２２の上面に接することが好ましい。 Here, it is preferable that the insulator 275 contacts the upper surface of the insulator 222.
　絶縁体２８０としては、絶縁体２８０となる絶縁膜を形成し、当該絶縁膜にＣＭＰ処理を行うことで、上面が平坦な絶縁体を形成することが好ましい。なお、絶縁体２８０上に、例えば、スパッタリング法によって窒化シリコンを成膜し、該窒化シリコンを絶縁体２８０に達するまで、ＣＭＰ処理を行ってもよい。 As the insulator 280, it is preferable to form an insulating film that will become the insulator 280, and then perform CMP processing on the insulating film to form an insulator with a flat upper surface. Note that it is also possible to form a film of silicon nitride on the insulator 280, for example, by a sputtering method, and then perform CMP processing on the silicon nitride until it reaches the insulator 280.
　絶縁体２７５及び絶縁体２８０は、それぞれ、例えば、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法を用いて成膜することができる。 Insulator 275 and insulator 280 can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
　絶縁体２７５には、酸素の透過を抑制する機能を有する絶縁体を用いることが好ましい。例えば、絶縁体２７５として、ＰＥＡＬＤ法を用いて窒化シリコンを成膜することが好ましい。または、絶縁体２７５として、スパッタリング法を用いて、酸化アルミニウムを成膜し、その上にＰＥＡＬＤ法を用いて窒化シリコンを成膜することが好ましい。絶縁体２７５を上記のような構造とすることで、水、水素などの不純物、及び酸素の拡散を抑制する機能の向上を図ることができる。 For the insulator 275, it is preferable to use an insulator that has a function of suppressing oxygen transmission. For example, it is preferable to form a silicon nitride film as the insulator 275 by using a PEALD method. Alternatively, it is preferable to form an aluminum oxide film as the insulator 275 by using a sputtering method and then form a silicon nitride film thereon by using a PEALD method. By making the insulator 275 have the above structure, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.
　このようにして、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２Ａを、酸素の拡散を抑制する機能を有する絶縁体２７５で覆うことができる。これにより、のちの工程で、酸化物２３０ａ、酸化物２３０ｂ、及び導電体２４２Ａに、絶縁体２８０などから酸素が直接拡散することを低減できる。 In this way, the oxide 230a, the oxide 230b, and the conductor 242A can be covered with the insulator 275, which has the function of suppressing the diffusion of oxygen. This makes it possible to reduce the direct diffusion of oxygen from the insulator 280, etc., to the oxide 230a, the oxide 230b, and the conductor 242A in a later process.
　また、絶縁体２８０として、スパッタリング法を用いて酸化シリコンを成膜することが好ましい。絶縁体２８０となる絶縁膜を、酸素を含む雰囲気で、スパッタリング法で成膜することで、過剰酸素を含む絶縁体２８０を形成することができる。また、成膜ガスに水素を含む分子を用いなくてもよいスパッタリング法を用いることで、絶縁体２８０中の水素濃度を低減できる。なお、当該絶縁膜の成膜前に、加熱処理を行ってもよい。加熱処理は、減圧下で行い、大気に暴露することなく、連続して当該絶縁膜を成膜してもよい。このような処理を行うことによって、絶縁体２７５の表面などに吸着している水分及び水素を除去し、さらに酸化物２３０ａ、及び酸化物２３０ｂ中の水分濃度及び水素濃度を低減できる。当該加熱処理には、上述した加熱処理条件を用いることができる。 Furthermore, it is preferable to form a film of silicon oxide as the insulator 280 by a sputtering method. By forming an insulating film to be the insulator 280 by a sputtering method in an atmosphere containing oxygen, the insulator 280 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of molecules containing hydrogen in the film formation gas, the hydrogen concentration in the insulator 280 can be reduced. Note that a heat treatment may be performed before the formation of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be continuously formed without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 275, etc., can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced. The heat treatment conditions described above can be used for the heat treatment.
　次に、リソグラフィ法を用いて、導電体２４２Ａ、絶縁体２７５、及び絶縁体２８０を加工して、酸化物２３０ｂ及び絶縁体２２２に達する開口を形成する（図１８Ａ乃至図１８Ｄ参照）。ここで、導電体２４２Ａが分断されて、導電体２４２ａ及び導電体２４２ｂが形成される。上記開口は、酸化物２３０ｂと導電体２０５とが重なる領域に形成する。 Next, lithography is used to process the conductor 242A, the insulator 275, and the insulator 280 to form an opening that reaches the oxide 230b and the insulator 222 (see Figures 18A to 18D). Here, the conductor 242A is divided to form the conductor 242a and the conductor 242b. The opening is formed in the region where the oxide 230b and the conductor 205 overlap.
　リソグラフィ法は、上記の方法を適宜用いることができる。上記絶縁体２８０の開口を微細に加工するには、ＥＵＶ光などの短波長の光、または電子ビームを用いたリソグラフィ法を用いることが好ましい。 The above-mentioned lithography methods can be used as appropriate. To finely process the openings in the insulator 280, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.
　上記加工は、ドライエッチング法を用いて行うことが好ましい。ドライエッチング法は、異方性エッチングが可能なので、アスペクト比が高い開口を形成するのに好適である。なお、ドライエッチング法の条件、及びドライエッチング装置については、上記の記載を参照することができる。 The above processing is preferably carried out using a dry etching method. Dry etching is suitable for forming openings with high aspect ratios because it allows for anisotropic etching. Please refer to the above description for the conditions for the dry etching method and the dry etching apparatus.
　なお、導電体２４２Ａの加工後に、酸素プラズマを用いたアッシング処理を行ってもよい。このような酸素プラズマ処理を行うことで、上記エッチング処理で発生し、酸化物２３０などに拡散した不純物を除去することができる。当該不純物は、上記エッチング処理の被加工物に含まれる成分、及び、エッチングに使用されるガスなどに含まれる成分に起因したものが挙げられる。例えば、塩素、フッ素、タンタル、シリコン、ハフニウムなどが挙げられる。特に、上記エッチング処理に示すように、導電体２４２Ａの加工で塩素ガスを用いると、塩素ガスを含む雰囲気に酸化物２３０が曝されるので、酸化物２３０に付着した塩素を除去することが好ましい。このように酸化物２３０に付着した不純物を除去することで、トランジスタの電気特性、及び信頼性を向上させることができる。 After processing the conductor 242A, an ashing process using oxygen plasma may be performed. By performing such an oxygen plasma process, impurities that are generated in the above etching process and diffused into the oxide 230, etc. can be removed. The impurities include those that originate from components contained in the workpiece of the above etching process and components contained in the gas used in the etching process. Examples of the impurities include chlorine, fluorine, tantalum, silicon, and hafnium. In particular, as shown in the above etching process, if chlorine gas is used in processing the conductor 242A, the oxide 230 is exposed to an atmosphere containing chlorine gas, so it is preferable to remove the chlorine attached to the oxide 230. By removing the impurities attached to the oxide 230 in this way, the electrical characteristics and reliability of the transistor can be improved.
　また、上記エッチング工程で酸化物２３０ｂ表面に付着した不純物などを除去するために、洗浄処理を行ってもよい。洗浄方法としては、洗浄液など用いたウェット洗浄（ウェットエッチング処理ということもできる）、プラズマを用いたプラズマ処理、熱処理による洗浄などがあり、上記洗浄を適宜組み合わせて行ってもよい。なお、当該洗浄処理によって、上記溝部が深くなる場合がある。 Furthermore, a cleaning process may be performed to remove impurities that have adhered to the surface of oxide 230b during the etching process. Cleaning methods include wet cleaning using a cleaning solution (which may also be called wet etching), plasma processing using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.
　ウェット洗浄としては、アンモニア水、シュウ酸、リン酸、及びフッ化水素酸のうち一つまたは複数を炭酸水または純水で希釈した水溶液、純水、炭酸水などを用いて行ってもよい。または、これらの水溶液、純水、または炭酸水を用いた超音波洗浄を行ってもよい。または、これらの洗浄を適宜組み合わせて行ってもよい。 Wet cleaning may be performed using an aqueous solution of one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid diluted with carbonated water or pure water, pure water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.
　なお、本明細書等では、フッ化水素酸を純水で希釈した水溶液を希釈フッ化水素酸と呼び、アンモニア水を純水で希釈した水溶液を希釈アンモニア水と呼ぶ場合がある。また、当該水溶液の濃度、温度などは、除去したい不純物、洗浄される半導体装置の構成などによって、適宜調整する。希釈アンモニア水のアンモニア濃度は０．０１％以上５％以下が好ましく、０．１％以上０．５％以下がより好ましい。また、希釈フッ化水素酸のフッ化水素濃度は０．０１ｐｐｍ以上１００ｐｐｍ以下が好ましく、０．１ｐｐｍ以上１０ｐｐｍ以下がより好ましい。 In this specification, an aqueous solution in which hydrofluoric acid is diluted with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution in which ammonia water is diluted with pure water may be referred to as diluted ammonia water. The concentration and temperature of the aqueous solution are adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.
　なお、超音波洗浄には、２００ｋＨｚ以上の周波数を用いることが好ましく、９００ｋＨｚ以上の周波数を用いることがより好ましい。当該周波数を用いることで、酸化物２３０ｂなどへのダメージを低減することができる。 It is preferable to use a frequency of 200 kHz or more for ultrasonic cleaning, and more preferably a frequency of 900 kHz or more. By using such a frequency, damage to the oxide 230b, etc. can be reduced.
　また、上記洗浄処理を複数回行ってもよく、洗浄処理毎に洗浄液を変更してもよい。例えば、第１の洗浄処理として希釈フッ化水素酸、または希釈アンモニア水を用いた処理を行い、第２の洗浄処理として純水、または炭酸水を用いた処理を行ってもよい。 The above cleaning process may be performed multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.
　上記洗浄処理として、本実施の形態では、希釈アンモニア水を用いてウェット洗浄を行う。当該洗浄処理を行うことで、酸化物２３０ａ、酸化物２３０ｂなどの表面に付着または内部に拡散した不純物を除去することができる。さらに、酸化物２３０ａ、酸化物２３０ｂなどの結晶性を高めることができる。 In the present embodiment, as the above-mentioned cleaning process, wet cleaning is performed using diluted ammonia water. By performing this cleaning process, impurities attached to the surfaces of oxide 230a, oxide 230b, etc. or diffused inside can be removed. Furthermore, the crystallinity of oxide 230a, oxide 230b, etc. can be improved.
　上記エッチング後、または上記洗浄後に加熱処理を行うことが好ましい。加熱処理の温度は、１００℃以上、２５０℃以上、または３５０℃以上であり、かつ、６５０℃以下、６００℃以下、５５０℃以下、または４００℃以下であると好ましい。なお、加熱処理は、窒素ガスもしくは不活性ガスの雰囲気、または酸化性ガスを１０ｐｐｍ以上、１％以上、もしくは１０％以上含む雰囲気で行う。当該加熱処理は、酸素を含む雰囲気で行うことが好ましく、例えば、窒素ガスと酸素ガスの流量比を４：１として、３５０℃の温度で１時間の処理を行うことが好ましい。これにより、酸化物２３０ａ及び酸化物２３０ｂに酸素を供給して、酸素欠損の低減を図ることができる。また、このような熱処理を行うことで、酸化物２３０ｂの結晶性を向上させることができる。さらに、酸化物２３０ａ及び酸化物２３０ｂ中に残存した水素に供給された酸素が反応することで、当該水素をＨ２Ｏとして除去する（脱水化する）ことができる。これにより、酸化物２３０ａ及び酸化物２３０ｂ中に残存していた水素が酸素欠損に再結合してＶＯＨが形成されることを抑制できる。これにより、酸化物２３０が設けられたトランジスタの電気特性を良好にし、信頼性を向上させることができる。また、同一基板上に複数形成されるトランジスタの電気特性のばらつきを抑制することができる。なお、上記加熱処理は減圧状態で行ってもよい。または、酸素雰囲気で加熱処理した後に、大気に露出せずに連続して窒素雰囲気で加熱処理を行ってもよい。 It is preferable to perform a heat treatment after the etching or the cleaning. The temperature of the heat treatment is preferably 100° C. or more, 250° C. or more, or 350° C. or more, and 650° C. or less, 600° C. or less, 550° C. or less, or 400° C. or less. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment is preferably performed in an atmosphere containing oxygen, and is preferably performed, for example, at a temperature of 350° C. for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. This makes it possible to supply oxygen to the oxide 230a and the oxide 230b and reduce oxygen deficiency. In addition, by performing such a heat treatment, the crystallinity of the oxide 230b can be improved. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 230a and the oxide 230b, and the hydrogen can be removed as H 2 O (dehydrated). This can prevent hydrogen remaining in the oxide 230a and the oxide 230b from recombining with oxygen vacancies to form VOH . This can improve the electrical characteristics of the transistor provided with the oxide 230, thereby improving the reliability. In addition, it can prevent variations in the electrical characteristics of a plurality of transistors formed on the same substrate. Note that the heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.
　なお、酸化物２３０ｂに、導電体２４２ａ及び導電体２４２ｂが接した状態で加熱処理を行う場合、酸化物２３０ｂにおける導電体２４２ａと重なる領域、及び、導電体２４２ｂと重なる領域は、それぞれシート抵抗が低下することがある。また、キャリア濃度が増加することがある。したがって、酸化物２３０ｂにおける導電体２４２ａと重なる領域、及び、導電体２４２ｂと重なる領域を、自己整合的に低抵抗化することができる。 When heat treatment is performed with the conductor 242a and the conductor 242b in contact with the oxide 230b, the sheet resistance may decrease in the region of the oxide 230b that overlaps with the conductor 242a and the region that overlaps with the conductor 242b. The carrier concentration may also increase. Therefore, the resistance of the region of the oxide 230b that overlaps with the conductor 242a and the region that overlaps with the conductor 242b can be reduced in a self-aligned manner.
　次に、絶縁体２８０などに形成された開口を埋めるように、絶縁体２５０となる絶縁膜２５０Ａを成膜する（図１９Ａ乃至図１９Ｄ参照）。ここで、絶縁膜２５０Ａは、絶縁体２８０、絶縁体２７５、導電体２４２ａ、導電体２４２ｂ、絶縁体２２２、酸化物２３０ａ、及び酸化物２３０ｂに接する。 Next, an insulating film 250A that will become the insulator 250 is formed so as to fill the openings formed in the insulator 280 and the like (see Figures 19A to 19D). Here, the insulating film 250A contacts the insulator 280, the insulator 275, the conductor 242a, the conductor 242b, the insulator 222, the oxide 230a, and the oxide 230b.
　絶縁膜２５０Ａは、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、または、ＡＬＤ法を用いて成膜することができる。例えば、絶縁膜２５０ＡはＡＬＤ法を用いて成膜することが好ましい。上述の絶縁体２５０と同様に、絶縁膜２５０Ａは薄い膜厚で形成することが好ましく、膜厚のバラつきが小さくなるようにする必要がある。これに対して、ＡＬＤ法は、プリカーサと、リアクタント（例えば酸化剤など）を交互に導入して行う成膜方法であり、このサイクルを繰り返す回数によって膜厚を調節することができるため、精密な膜厚調節が可能である。また、絶縁膜２５０Ａは、上記開口の底面及び側面に、被覆性良く成膜される必要がある。ＡＬＤ法を用いることで、上記開口の底面及び側面において、原子の層を一層ずつ堆積させることができるため、絶縁膜２５０Ａを当該開口に対して良好な被覆性で形成できる。 The insulating film 250A can be formed by sputtering, CVD, MBE, PLD, or ALD. For example, the insulating film 250A is preferably formed by ALD. As with the insulator 250 described above, the insulating film 250A is preferably formed to a thin thickness, and it is necessary to reduce the variation in thickness. In contrast, the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizing agent) are alternately introduced, and the thickness can be adjusted by the number of times this cycle is repeated, allowing for precise thickness adjustment. In addition, the insulating film 250A needs to be formed with good coverage on the bottom and side surfaces of the opening. By using the ALD method, layers of atoms can be deposited one by one on the bottom and side surfaces of the opening, so that the insulating film 250A can be formed with good coverage on the opening.
　また、絶縁膜２５０ＡをＡＬＤ法で成膜する場合、酸化剤として、オゾン（Ｏ３）、酸素（Ｏ２）、水（Ｈ２Ｏ）などを用いることができる。水素を含まない、オゾン（Ｏ３）、酸素（Ｏ２）などを酸化剤として用いることで、酸化物２３０ｂに拡散する水素を低減できる。 When the insulating film 250A is formed by the ALD method, ozone ( O3 ), oxygen ( O2 ), water ( H2O ), etc. can be used as an oxidizing agent. By using ozone ( O3 ), oxygen ( O2 ), etc. that do not contain hydrogen as an oxidizing agent, the amount of hydrogen diffusing into the oxide 230b can be reduced.
　絶縁体２５０は、図２などで示したように、積層構造にすることができる。例えば、図２Ａに示すように、絶縁体２５０を絶縁体２５０ａ乃至絶縁体２５０ｄの積層構造にすることができる。この場合、絶縁体２５０ａとして、酸化アルミニウムを熱ＡＬＤ法によって成膜し、絶縁体２５０ｂとして、酸化シリコンをＰＥＡＬＤ法によって成膜し、絶縁体２５０ｃとして、酸化ハフニウムを熱ＡＬＤ法によって成膜し、絶縁体２５０ｄとして、窒化シリコンをＰＥＡＬＤ法によって成膜することができる。 The insulator 250 can have a layered structure as shown in FIG. 2 and the like. For example, as shown in FIG. 2A, the insulator 250 can have a layered structure of insulators 250a to 250d. In this case, aluminum oxide can be deposited by thermal ALD as the insulator 250a, silicon oxide can be deposited by PEALD as the insulator 250b, hafnium oxide can be deposited by thermal ALD as the insulator 250c, and silicon nitride can be deposited by PEALD as the insulator 250d.
　また、絶縁膜２５０Ａの成膜後、または絶縁膜２５０Ａを構成するいずれかの絶縁体の成膜後に、酸素を含む雰囲気でマイクロ波処理を行うことが好ましい。ここで、マイクロ波処理とは、例えばマイクロ波を用いて高密度プラズマを発生させる電源を有する装置を用いた処理のことを指す。また、本明細書などにおいて、マイクロ波とは、３００ＭＨｚ以上３００ＧＨｚ以下の周波数を有する電磁波を指すものとする。 Furthermore, after the formation of the insulating film 250A or after the formation of any of the insulators that make up the insulating film 250A, it is preferable to perform microwave treatment in an atmosphere that contains oxygen. Here, microwave treatment refers to treatment using, for example, an apparatus having a power source that generates high-density plasma using microwaves. Furthermore, in this specification and the like, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.
　マイクロ波処理では、例えばマイクロ波を用いた高密度プラズマを発生させる電源を有する、マイクロ波処理装置を用いることが好ましい。ここで、マイクロ波処理装置の周波数は、３００ＭＨｚ以上３００ＧＨｚ以下が好ましく、２．４ＧＨｚ以上２．５ＧＨｚ以下がより好ましく、例えば、２．４５ＧＨｚにすることができる。高密度プラズマを用いることより、高密度の酸素ラジカルを生成することができる。また、マイクロ波処理装置のマイクロ波を印加する電源の電力は、１０００Ｗ以上１００００Ｗ以下が好ましく、２０００Ｗ以上５０００Ｗ以下がより好ましい。また、マイクロ波処理装置は基板側にＲＦを印加する電源を有してもよい。また、基板側にＲＦを印加することで、高密度プラズマによって生成された酸素イオンを、効率よく酸化物２３０ｂ中に導くことができる。 In the microwave processing, it is preferable to use a microwave processing device having a power source that generates high-density plasma using microwaves. Here, the frequency of the microwave processing device is preferably 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, and can be set to, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. In addition, the power of the power source that applies microwaves in the microwave processing device is preferably 1000 W or more and 10,000 W or less, more preferably 2000 W or more and 5000 W or less. In addition, the microwave processing device may have a power source that applies RF to the substrate side. In addition, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the oxide 230b.
　また、上記マイクロ波処理は、減圧下で行うことが好ましく、圧力は、１０Ｐａ以上１０００Ｐａ以下が好ましく、３００Ｐａ以上７００Ｐａ以下がより好ましい。また、処理温度は、７５０℃以下が好ましく、５００℃以下がより好ましく、例えば２５０℃程度とすることができる。また、酸素プラズマ処理を行った後に、外気に曝すことなく、連続して加熱処理を行ってもよい。加熱処理の温度は、例えば、１００℃以上７５０℃以下が好ましく、３００℃以上５００℃以下がより好ましい。 The microwave treatment is preferably carried out under reduced pressure, with the pressure being preferably 10 Pa to 1000 Pa, and more preferably 300 Pa to 700 Pa. The treatment temperature is preferably 750°C or less, and more preferably 500°C or less, and can be, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out continuously without exposure to the outside air. The heat treatment temperature is, for example, preferably 100°C to 750°C, and more preferably 300°C to 500°C.
　また、例えば、上記マイクロ波処理は、酸素ガスとアルゴンガスを用いて行うことができる。ここで、酸素流量比（Ｏ２／（Ｏ２＋Ａｒ））は、０％より大きく、１００％以下とする。好ましくは、酸素流量比（Ｏ２／（Ｏ２＋Ａｒ））を、０％より大きく、５０％以下とする。より好ましくは、酸素流量比（Ｏ２／（Ｏ２＋Ａｒ））を、１０％以上、４０％以下とする。さらに好ましくは、酸素流量比（Ｏ２／（Ｏ２＋Ａｒ））を、１０％以上、３０％以下とする。このように、酸素を含む雰囲気でマイクロ波処理を行うことで、酸化物２３０ｂ中のキャリア濃度を低下させることができる。また、マイクロ波処理において、チャンバーに過剰な量の酸素が導入されないようにすることで、酸化物２３０ｂでキャリア濃度が過剰に低下することを防ぐことができる。 Also, for example, the microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O 2 /(O 2 +Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio (O 2 /(O 2 +Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio (O 2 /(O 2 +Ar)) is greater than 10% and less than 40%. More preferably, the oxygen flow ratio (O 2 /(O 2 +Ar)) is greater than 10% and less than 30%. In this way, by performing the microwave treatment in an atmosphere containing oxygen, the carrier concentration in the oxide 230b can be reduced. Also, by preventing an excessive amount of oxygen from being introduced into the chamber in the microwave treatment, the carrier concentration in the oxide 230b can be prevented from being excessively reduced.
　酸素を含む雰囲気でマイクロ波処理を行うことで、マイクロ波、またはＲＦ等の高周波を用いて酸素ガスをプラズマ化し、当該酸素プラズマを酸化物２３０ｂの、導電体２４２ａと導電体２４２ｂとの間の領域に作用させることができる。プラズマ、マイクロ波などの作用により、当該領域におけるＶＯＨを酸素欠損と水素とに分断し、水素を当該領域から除去することができる。ここで、図２Ａなどに示す構造にする場合、絶縁体２５０ａとして、水素を捕獲または水素を固着する機能を有する絶縁膜（例えば、酸化アルミニウムなど）を用いることが好ましい。このような構成にすることで、マイクロ波処理により生じた水素を、絶縁体２５０ａに捕獲、または固着させることができる。このようにして、チャネル形成領域に含まれるＶＯＨを低減できる。以上により、チャネル形成領域中の酸素欠損、及びＶＯＨを低減し、キャリア濃度を低下させることができる。また、チャネル形成領域で形成された酸素欠損に、上記酸素プラズマで発生した酸素ラジカルを供給することで、さらに、チャネル形成領域中の酸素欠損を低減し、キャリア濃度を低下させることができる。 By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region between the conductor 242a and the conductor 242b of the oxide 230b. By the action of plasma, microwaves, or the like, VOH in the region can be separated into oxygen vacancies and hydrogen, and hydrogen can be removed from the region. Here, when the structure shown in FIG. 2A or the like is used, it is preferable to use an insulating film (e.g., aluminum oxide) having a function of capturing or fixing hydrogen as the insulator 250a. With such a configuration, hydrogen generated by the microwave treatment can be captured or fixed to the insulator 250a. In this way, VOH contained in the channel formation region can be reduced. As described above, oxygen vacancies and VOH in the channel formation region can be reduced, and the carrier concentration can be reduced. In addition, by supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be reduced.
　チャネル形成領域中に注入される酸素は、酸素原子、酸素分子、酸素イオン、及び酸素ラジカル（Ｏラジカルともいう、不対電子をもつ原子、分子、またはイオン）など様々な形態がある。なお、チャネル形成領域中に注入される酸素は、上述の形態のいずれか一または複数であればよく、特に酸素ラジカルであると好適である。また、絶縁体２５０の膜質を向上させることができるため、トランジスタの信頼性が向上する。 The oxygen injected into the channel formation region can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also called O radicals, which are atoms, molecules, or ions with an unpaired electron). The oxygen injected into the channel formation region can be in one or more of the above forms, and is particularly preferably in the form of oxygen radicals. In addition, the film quality of the insulator 250 can be improved, thereby improving the reliability of the transistor.
　また、マイクロ波処理を行うことで、酸化物２３０ｂ中の炭素などの不純物も除去することができる。酸化物２３０ｂ中の不純物である炭素を除去することで、酸化物２３０ｂの結晶性向上を図ることができる。これにより、酸化物２３０ｂをＣＡＡＣ−ＯＳにすることができる。特に、酸化物２３０ｂをＡＬＤ法で成膜した場合、プリカーサに含まれる炭素が酸化物２３０ｂ中に取り込まれることがあるので、マイクロ波処理で炭素を除去することが好ましい。 In addition, by performing microwave treatment, impurities such as carbon in the oxide 230b can also be removed. By removing carbon, which is an impurity in the oxide 230b, the crystallinity of the oxide 230b can be improved. This allows the oxide 230b to become CAAC-OS. In particular, when the oxide 230b is formed by the ALD method, carbon contained in the precursor may be incorporated into the oxide 230b, so it is preferable to remove the carbon by microwave treatment.
　一方、酸化物２３０ｂには、導電体２４２ａ、２４２ｂのいずれかと重なる領域が存在する。当該領域は、ソース領域またはドレイン領域として機能することができる。ここで、導電体２４２ａ、２４２ｂは、酸素を含む雰囲気でマイクロ波処理を行う際、マイクロ波、ＲＦ等の高周波、酸素プラズマなどの作用に対する遮蔽膜として機能することが好ましい。このため、導電体２４２ａ、２４２ｂは、３００ＭＨｚ以上３００ＧＨｚ以下、例えば、２．４ＧＨｚ以上２．５ＧＨｚ以下の電磁波を遮蔽する機能を有することが好ましい。 On the other hand, there is a region in oxide 230b that overlaps with either conductor 242a or 242b. This region can function as a source region or a drain region. Here, conductors 242a and 242b preferably function as a shielding film against the action of microwaves, high frequency waves such as RF, oxygen plasma, etc., when microwave processing is performed in an atmosphere containing oxygen. For this reason, conductors 242a and 242b preferably have the function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.
　導電体２４２ａ、２４２ｂは、マイクロ波、またはＲＦ等の高周波、酸素プラズマなどの作用を遮蔽するため、これらの作用は、酸化物２３０ｂの導電体２４２ａ、２４２ｂのいずれかと重なる領域には及ばない。これにより、マイクロ波処理によって、ソース領域及びドレイン領域で、ＶＯＨの低減、及び過剰な量の酸素供給が発生しないため、キャリア濃度の低下を防ぐことができる。 The conductors 242a and 242b shield against the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc., and therefore these effects do not extend to the regions of the oxide 230b that overlap with either of the conductors 242a and 242b. As a result, the microwave treatment does not reduce VOH in the source and drain regions, and does not supply an excessive amount of oxygen, thereby preventing a decrease in carrier concentration.
　以上のようにして、酸化物半導体のチャネル形成領域で選択的に酸素欠損、及びＶＯＨを除去して、チャネル形成領域をｉ型または実質的にｉ型とすることができる。さらに、ソース領域またはドレイン領域として機能する領域に過剰な酸素が供給されることを抑制し、マイクロ波処理を行う前の導電性（低抵抗領域である状態）を維持することができる。これにより、トランジスタの電気特性の変動を抑制し、基板面内でトランジスタの電気特性がばらつくことを抑制できる。 In this manner, oxygen vacancies and VOH can be selectively removed from the channel formation region of the oxide semiconductor to make the channel formation region i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions functioning as source and drain regions can be suppressed, and the conductivity (the state of being a low-resistance region) before the microwave treatment can be maintained. This can suppress fluctuations in the electrical characteristics of the transistor, and can suppress variations in the electrical characteristics of the transistor within the substrate surface.
　なお、マイクロ波処理では、マイクロ波と酸化物２３０ｂ中の分子の電磁気的な相互作用により、酸化物２３０ｂに直接的に熱エネルギーを伝達する場合がある。この熱エネルギーにより、酸化物２３０ｂが加熱される場合がある。このような加熱処理をマイクロ波アニールと呼ぶ場合がある。マイクロ波処理を、酸素を含む雰囲気中で行うことで、酸素アニールと同等の効果が得られる場合がある。また、酸化物２３０ｂに水素が含まれる場合、この熱エネルギーが酸化物２３０ｂ中の水素に伝わり、これにより活性化した水素が酸化物２３０ｂから放出されることが考えられる。 In addition, in microwave processing, thermal energy may be directly transferred to the oxide 230b due to electromagnetic interaction between the microwaves and the molecules in the oxide 230b. This thermal energy may heat the oxide 230b. This type of heating process may be called microwave annealing. By performing microwave processing in an atmosphere containing oxygen, it may be possible to obtain an effect equivalent to that of oxygen annealing. Furthermore, if the oxide 230b contains hydrogen, it is thought that this thermal energy is transferred to the hydrogen in the oxide 230b, which activates the hydrogen and causes it to be released from the oxide 230b.
　また、マイクロ波処理を行って、絶縁体２５０の膜質を改質することで、水素、水、不純物等の拡散を抑制できる。従って、導電体２６０となる導電膜の成膜などの後工程、または熱処理などの後処理により、絶縁体２５０を介して、水素、水、不純物等が、酸化物２３０ｂ、酸化物２３０ａなどへ拡散することを抑制できる。このように、絶縁体２５０の膜質を向上させることで、トランジスタの信頼性を向上させることができる。 Furthermore, by performing microwave processing to modify the film quality of the insulator 250, the diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, by performing a post-process such as forming a conductive film that becomes the conductor 260, or a post-process such as heat treatment, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. through the insulator 250 into the oxide 230b, the oxide 230a, etc. In this way, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.
　また、マイクロ波処理後に減圧状態を保ったままで、加熱処理を行ってもよい。このような処理を行うことで、当該絶縁膜中、酸化物２３０ｂ中、及び酸化物２３０ａ中の水素を効率よく除去できる。また、水素の一部は、導電体２４２ａ、２４２ｂにゲッタリングされる場合がある。または、マイクロ波処理後に減圧状態を保ったままで、加熱処理を行うステップを複数回繰り返して行ってもよい。加熱処理を繰り返し行うことで、当該絶縁膜中、酸化物２３０ｂ中、及び酸化物２３０ａ中の水素をさらに効率よく除去できる。なお、加熱処理温度は、３００℃以上５００℃以下とすることが好ましい。また、上記マイクロ波処理、すなわちマイクロ波アニールが該加熱処理を兼ねてもよい。マイクロ波アニールにより、酸化物２３０ｂなどが十分加熱される場合、該加熱処理を行わなくてもよい。 Furthermore, a heat treatment may be performed while maintaining the reduced pressure state after the microwave treatment. By performing such a treatment, hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be efficiently removed. Also, some of the hydrogen may be gettered to the conductors 242a and 242b. Alternatively, a step of performing a heat treatment may be repeated multiple times while maintaining the reduced pressure state after the microwave treatment. By repeatedly performing the heat treatment, hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be more efficiently removed. The heat treatment temperature is preferably 300°C or higher and 500°C or lower. Furthermore, the microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If the oxide 230b, etc. is sufficiently heated by the microwave annealing, the heat treatment may not be performed.
　絶縁体２５０を絶縁体２５０ａ乃至絶縁体２５０ｄの積層構造にする場合、絶縁体２５０ｂの成膜後にマイクロ波処理を行うことが好ましい。さらに、絶縁体２５０ｃの成膜後にもう一度マイクロ波処理を行ってもよい。このように、酸素を含む雰囲気でのマイクロ波処理は、複数回（少なくとも２回以上）の処理としてもよい。 When the insulator 250 has a layered structure of insulators 250a to 250d, it is preferable to perform microwave treatment after the formation of insulator 250b. Furthermore, microwave treatment may be performed again after the formation of insulator 250c. In this way, microwave treatment in an oxygen-containing atmosphere may be performed multiple times (at least two or more times).
　次に、導電体２６０ａとなる導電膜２６０Ａと、導電体２６０ｂとなる導電膜２６０Ｂと、を順に成膜する（図２０Ａ乃至図２０Ｄ参照）。導電膜２６０Ａ、及び、導電膜２６０Ｂは、それぞれ、例えば、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、メッキ法または、ＡＬＤ法を用いて成膜することができる。本実施の形態では、ＡＬＤ法を用いて、導電膜２６０Ａとして窒化チタンを成膜し、ＣＶＤ法を用いて導電膜２６０Ｂとしてタングステンを成膜する。 Next, conductive film 260A that will become conductor 260a and conductive film 260B that will become conductor 260b are formed in this order (see Figures 20A to 20D). Conductive film 260A and conductive film 260B can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method. In this embodiment, titanium nitride is formed as conductive film 260A using the ALD method, and tungsten is formed as conductive film 260B using the CVD method.
　次に、ＣＭＰ処理によって、絶縁膜２５０Ａ、導電膜２６０Ａ、及び、導電膜２６０Ｂを、絶縁体２８０が露出するまで研磨する。つまり、絶縁膜２５０Ａ、導電膜２６０Ａ、及び、導電膜２６０Ｂの、上記開口から露出した部分を除去する。これによって、導電体２０５と重なる開口の中に、絶縁体２５０、及び導電体２６０（導電体２６０ａ及び導電体２６０ｂ）を形成する（図２１Ａ乃至図２１Ｄ参照）。 Next, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed. In other words, the portions of the insulating film 250A, the conductive film 260A, and the conductive film 260B exposed from the openings are removed. This forms the insulator 250 and the conductor 260 (conductor 260a and conductor 260b) in the openings that overlap the conductor 205 (see Figures 21A to 21D).
　これにより、絶縁体２５０は、上記開口内で、絶縁体２８０、絶縁体２７５、導電体２４２ａ、導電体２４２ｂ、酸化物２３０ｂ、酸化物２３０ａ、及び絶縁体２２２に接して設けられる。また、導電体２６０は、絶縁体２５０を介して、上記開口を埋め込むように配置される。このようにして、トランジスタ２００が形成される。 As a result, insulator 250 is provided in the opening in contact with insulator 280, insulator 275, conductor 242a, conductor 242b, oxide 230b, oxide 230a, and insulator 222. Conductor 260 is also arranged to fill the opening via insulator 250. In this manner, transistor 200 is formed.
　次に、絶縁体２５０上、導電体２６０上、及び絶縁体２８０上に、絶縁体２８２を形成する。絶縁体２８２は、例えば、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法を用いて成膜する行うことができる。絶縁体２８２の成膜は、スパッタリング法を用いて行うことが好ましい。成膜ガスに水素を含む分子を用いなくてもよいスパッタリング法を用いることで、絶縁体２８２中の水素濃度を低減できる。 Next, the insulator 282 is formed on the insulator 250, the conductor 260, and the insulator 280. The insulator 282 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 282 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the film formation gas, the hydrogen concentration in the insulator 282 can be reduced.
　また、スパッタリング法を用いて、酸素を含む雰囲気で絶縁体２８２の成膜を行うことで、成膜しながら、絶縁体２８０に酸素を添加できる。これにより、絶縁体２８０に過剰酸素を含ませることができる。このとき、基板加熱を行いながら、絶縁体２８２を成膜することが好ましい。このように絶縁体２８２を成膜することで、絶縁体２８０から、絶縁体２５０を介して酸化物２３０ｂまで拡散させ、好適な量の酸素を酸化物２３０ｂに供給することができる。また、絶縁体２５０中に絶縁体２５０ａを設けておくことで、過剰な量の酸素が絶縁体２５０中に供給され、導電体２４２ａ、２４２ｂの絶縁体２５０近傍が過剰に酸化されるのを防ぐことができる。 Furthermore, by forming the insulator 282 in an oxygen-containing atmosphere using a sputtering method, oxygen can be added to the insulator 280 while the film is being formed. This allows the insulator 280 to contain excess oxygen. At this time, it is preferable to form the insulator 282 while heating the substrate. By forming the insulator 282 in this manner, oxygen can be diffused from the insulator 280 through the insulator 250 to the oxide 230b, and a suitable amount of oxygen can be supplied to the oxide 230b. Furthermore, by providing the insulator 250a in the insulator 250, an excess amount of oxygen can be supplied into the insulator 250, which can prevent the conductors 242a and 242b near the insulator 250 from being excessively oxidized.
　本実施の形態では、絶縁体２８２として、酸素ガスを含む雰囲気でアルミニウムターゲットを用いて、スパッタリング法で酸化アルミニウムを成膜する。スパッタリング法で基板に印加するＲＦ電力の大きさによって、絶縁体２８２より下層へ注入する酸素量を制御することができる。例えば、ＲＦ電力が小さいほど絶縁体２８２より下層へ注入する酸素量が減り、絶縁体２８２の膜厚が薄くても当該酸素量は飽和しやすくなる。また、ＲＦ電力が大きいほど絶縁体２８２より下層へ注入する酸素量が増える。ＲＦ電力を小さくすることで、絶縁体２８０へ注入される酸素量を抑制できる。また、絶縁体２８２を２層の積層構造で成膜してもよい。このとき、例えば、絶縁体２８２の下層を、基板に印加するＲＦ電力を印加しないで成膜し、絶縁体２８２の上層を、基板にＲＦ電力を印加して成膜する。 In this embodiment, an aluminum oxide film is formed as the insulator 282 by sputtering using an aluminum target in an atmosphere containing oxygen gas. The amount of oxygen injected into the layer below the insulator 282 can be controlled by the magnitude of the RF power applied to the substrate by the sputtering method. For example, the smaller the RF power, the less the amount of oxygen injected into the layer below the insulator 282, and the amount of oxygen is likely to be saturated even if the insulator 282 is thin. Also, the larger the RF power, the more the amount of oxygen injected into the layer below the insulator 282. By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed. The insulator 282 may also be formed in a two-layer laminate structure. At this time, for example, the lower layer of the insulator 282 is formed without applying RF power to the substrate, and the upper layer of the insulator 282 is formed by applying RF power to the substrate.
　なお、ＲＦの周波数は、１０ＭＨｚ以上が好ましい。代表的には、１３．５６ＭＨｚである。ＲＦの周波数が高いほど基板へ与えるダメージを小さくすることができる。 The RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage it can cause to the substrate.
　また、絶縁体２８２の成膜前に、加熱処理を行ってもよい。当該加熱処理は、減圧下で行い、大気に暴露することなく、連続して絶縁体２８２を成膜してもよい。このような処理を行うことによって、絶縁体２８０の表面に吸着している水分及び水素を除去し、さらに絶縁体２８０中の水分濃度及び水素濃度を低減させることができる。加熱処理の温度は、１００℃以上４００℃以下が好ましい。本実施の形態では、加熱処理の温度を２５０℃とする。 Also, a heat treatment may be performed before the formation of the insulator 282. The heat treatment may be performed under reduced pressure, and the insulator 282 may be continuously formed without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 can be removed, and the moisture concentration and hydrogen concentration in the insulator 280 can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is 250°C.
　次に、絶縁体２８２上に、絶縁体２８３を形成する。絶縁体２８３は、例えば、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法を用いて成膜する行うことができる。絶縁体２８３の成膜は、スパッタリング法を用いて行うことが好ましい。成膜ガスに水素を含む分子を用いなくてもよいスパッタリング法を用いることで、絶縁体２８３中の水素濃度を低減できる。本実施の形態では、絶縁体２８３として、スパッタリング法を用いて、窒化シリコンを成膜する。 Next, the insulator 283 is formed on the insulator 282. The insulator 283 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 283 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the film formation gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, a silicon nitride film is formed as the insulator 283 by a sputtering method.
　ここで、絶縁体２８２及び絶縁体２８３は、大気環境にさらさずに連続して成膜することが好ましい。大気開放せずに成膜することで、絶縁体２８２及び絶縁体２８３上に大気環境からの不純物または水分が付着することを防ぐことができ、絶縁体２８２及び絶縁体２８３との界面または界面近傍を清浄に保つことができる。 Here, it is preferable to deposit the insulators 282 and 283 in succession without exposing them to the atmospheric environment. Depositing them without exposing them to the atmosphere can prevent impurities or moisture from the atmospheric environment from adhering to the insulators 282 and 283, and can keep the interface or the vicinity of the interface between the insulators 282 and 283 clean.
　また、絶縁体２８３の成膜後に、加熱処理を行ってもよい。当該加熱処理の温度は、１００℃以上４００℃以下が好ましい。加熱処理を行うことで、絶縁体２８０、絶縁体２５０、及び酸化物２３０に含まれる水素が絶縁体２８２内に吸い取られる。別言すると、絶縁体２８０、絶縁体２５０、及び酸化物２３０に含まれる水素が絶縁体２８２に拡散する。従って、絶縁体２８２の水素濃度は高くなるが、絶縁体２８０、絶縁体２５０、及び酸化物２３０のそれぞれの水素濃度は低下する。なお、絶縁体２８２の上面に接して絶縁体２８３を設けておくことで、当該加熱処理において、絶縁体２８３より上方から水分、または水素などの不純物が侵入するのを防ぐことができる。また、加熱処理を行うことで、酸化物２３０に含まれる水素が絶縁体２２２内に吸い取られる。別言すると、酸化物２３０に含まれる水素が絶縁体２２２に拡散する。従って、絶縁体２２２の水素濃度は高くなるが、酸化物２３０中の水素濃度は低下する。なお、絶縁体２２２の下面に接して絶縁体２２１を設けておくことで、当該加熱処理において、絶縁体２２１より下方から水分、または水素などの不純物が侵入するのを防ぐことができる。 Further, after the formation of the insulator 283, a heat treatment may be performed. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. By performing the heat treatment, hydrogen contained in the insulator 280, the insulator 250, and the oxide 230 is absorbed into the insulator 282. In other words, hydrogen contained in the insulator 280, the insulator 250, and the oxide 230 diffuses into the insulator 282. Therefore, the hydrogen concentration in the insulator 282 increases, but the hydrogen concentrations in the insulators 280, the insulator 250, and the oxide 230 decrease. Note that by providing the insulator 283 in contact with the upper surface of the insulator 282, impurities such as moisture or hydrogen can be prevented from entering from above the insulator 283 during the heat treatment. Furthermore, by performing the heat treatment, hydrogen contained in the oxide 230 is absorbed into the insulator 222. In other words, hydrogen contained in the oxide 230 diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentration in the oxide 230 decreases. By providing the insulator 221 in contact with the lower surface of the insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 during the heat treatment.
　次に、絶縁体２７５、絶縁体２８０、絶縁体２８２、及び絶縁体２８３に、導電体２４２ａに達する開口と、導電体２４２ｂに達する開口を形成する（図１Ａ乃至図１Ｄ参照）。当該開口の形成は、リソグラフィ法を用いて行えばよい。なお、図１Ａで当該開口の形状は、上面視において円形状にしているが、これに限られるものではない。例えば、当該開口が、上面視において、楕円などの略円形状、四角形などの多角形状、四角形等の多角形の角部を丸めた形状になっていてもよい。 Next, an opening reaching conductor 242a and an opening reaching conductor 242b are formed in insulators 275, 280, 282, and 283 (see Figures 1A to 1D). The openings may be formed using a lithography method. Note that, although the shape of the opening is circular in top view in Figure 1A, this is not limited to this. For example, the opening may be approximately circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in top view.
　次に、絶縁体２４１となる絶縁膜を成膜し、当該絶縁膜を異方性エッチングして、導電体２４２ａに達する開口に絶縁体２４１ａを形成し、導電体２４２ｂに達する開口に絶縁体２４１ｂを形成する（図１Ａ乃至図１Ｄ参照）。絶縁体２４１となる絶縁膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法などを用いて行うことができる。絶縁体２４１となる絶縁膜としては、酸素の透過を抑制する機能を有する絶縁膜を用いることが好ましい。例えば、ＡＬＤ法を用いて、酸化アルミニウムを成膜し、その上に、ＰＥＡＬＤ法を用いて、窒化シリコンを成膜することが好ましい。窒化シリコンは水素に対するブロッキング性が高いので好ましい。 Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241a in the opening that reaches the conductor 242a, and the insulator 241b in the opening that reaches the conductor 242b (see Figures 1A to 1D). The insulating film that will become the insulator 241 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to use an insulating film that has a function of suppressing oxygen permeation as the insulating film that will become the insulator 241. For example, it is preferable to form a film of aluminum oxide using the ALD method, and then form a film of silicon nitride thereon using the PEALD method. Silicon nitride is preferable because it has high blocking properties against hydrogen.
　また、絶縁体２４１となる絶縁膜の異方性エッチングとしては、例えばドライエッチング法などを用いればよい。開口の側壁部に絶縁体２４１を設けることで、外方からの酸素の透過を抑制し、次に形成する導電体２４０ａおよび導電体２４０ｂの酸化を防止することができる。また、導電体２４０ａおよび導電体２４０ｂに、絶縁体２８０などに含まれる、水、水素などの不純物が拡散することを防ぐことができる。 The anisotropic etching of the insulating film that will become the insulator 241 can be performed, for example, by dry etching. By providing the insulator 241 on the sidewall of the opening, it is possible to suppress the transmission of oxygen from the outside and prevent the oxidation of the conductors 240a and 240b that will be formed next. It is also possible to prevent impurities such as water and hydrogen contained in the insulator 280 from diffusing into the conductors 240a and 240b.
　次に、導電体２４０ａおよび導電体２４０ｂとなる導電膜を成膜する。導電体２４０ａおよび導電体２４０ｂとなる導電膜は、水、水素など不純物の透過を抑制する機能を有する導電体を含む積層構造とすることが望ましい。たとえば、窒化タンタル、窒化チタンなどと、タングステン、モリブデン、銅など、と、の積層とすることができる。導電体２４０ａおよび導電体２４０ｂとなる導電膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。 Next, a conductive film that will become conductor 240a and conductor 240b is formed. The conductive film that will become conductor 240a and conductor 240b is desirably a laminated structure that includes a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. The conductive film that will become conductor 240a and conductor 240b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc.
　次に、ＣＭＰ処理を行うことで、導電体２４０ａおよび導電体２４０ｂとなる導電膜の一部を除去し、絶縁体２８３の上面を露出する。その結果、開口のみに、当該導電膜が残存することで上面が平坦な導電体２４０ａおよび導電体２４０ｂを形成することができる（図１Ａ乃至図１Ｄ参照）。なお、当該ＣＭＰ処理により、絶縁体２８３の上面の一部が除去される場合がある。 Next, a CMP process is performed to remove a portion of the conductive film that will become conductor 240a and conductor 240b, exposing the upper surface of insulator 283. As a result, the conductive film remains only in the openings, forming conductors 240a and 240b with flat upper surfaces (see Figures 1A to 1D). Note that the CMP process may remove a portion of the upper surface of insulator 283.
　上記のように、導電体２４２ａに接する導電体２４０ａを設けることで、トランジスタ２００のソース及びドレインの一方として機能する導電体２４０ａを配線と電気的に接続させることができる。また、導電体２４２ｂに接する導電体２４０ｂを設けることで、トランジスタ２００のソース及びドレインの他方として機能する導電体２４０ｂを配線と電気的に接続させることができる。 As described above, by providing conductor 240a in contact with conductor 242a, conductor 240a, which functions as one of the source and drain of transistor 200, can be electrically connected to wiring. Furthermore, by providing conductor 240b in contact with conductor 242b, conductor 240b, which functions as the other of the source and drain of transistor 200, can be electrically connected to wiring.
　なお、導電体２４０ａおよび導電体２４０ｂ上に、配線として機能する導電膜、またはプラグとして機能する導電膜を形成することができる。 In addition, a conductive film that functions as wiring or a conductive film that functions as a plug can be formed on the conductor 240a and the conductor 240b.
　以上により、図１に示す半導体装置を作製できる。 By the above steps, the semiconductor device shown in Figure 1 can be manufactured.
　本実施の形態は、他の実施の形態と適宜組み合わせることができる。また、本明細書において、１つの実施の形態の中に、複数の構成例が示される場合は、構成例を適宜組み合わせることが可能である。 This embodiment can be combined with other embodiments as appropriate. In addition, in this specification, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.
（実施の形態２）
　本実施の形態では、先の実施の形態に示すＯＳトランジスタと、チャネル形成領域にシリコンを有するトランジスタ（Ｓｉトランジスタともいう）との比較について説明する。 (Embodiment 2)
In this embodiment, a comparison between the OS transistor described in the above embodiment and a transistor having silicon in a channel formation region (also referred to as a Si transistor) will be described.
［ＯＳトランジスタ］
　ＯＳトランジスタには、キャリア濃度の低い酸化物半導体を用いることが好ましい。例えば、酸化物半導体のチャネル形成領域のキャリア濃度は１×１０１８ｃｍ−３以下、好ましくは１×１０１７ｃｍ−３未満、より好ましくは１×１０１６ｃｍ−３未満、さらに好ましくは１×１０１３ｃｍ−３未満、さらに好ましくは１×１０１０ｃｍ−３未満であり、１×１０−９ｃｍ−３以上である。なお、酸化物半導体膜のキャリア濃度を低くする場合においては、酸化物半導体膜中の不純物濃度を低くし、欠陥準位密度を低くすればよい。本明細書等において、不純物濃度が低く、欠陥準位密度の低いことを高純度真性又は実質的に高純度真性と言う。なお、キャリア濃度の低い酸化物半導体を、高純度真性又は実質的に高純度真性な酸化物半導体と呼ぶ場合がある。 [OS Transistor]
For the OS transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of a channel formation region of the oxide semiconductor is 1×10 18 cm −3 or less, preferably less than 1×10 17 cm −3 , more preferably less than 1×10 16 cm −3 , further preferably less than 1×10 13 cm −3 , and further preferably less than 1×10 10 cm −3 and 1×10 −9 cm −3 or more. Note that in order to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
　また、高純度真性又は実質的に高純度真性である酸化物半導体は、欠陥準位密度が低いため、トラップ準位密度も低くなる場合がある。また、酸化物半導体のトラップ準位に捕獲された電荷は、消失するまでに要する時間が長く、あたかも固定電荷のように振る舞うことがある。そのため、トラップ準位密度の高い酸化物半導体にチャネル形成領域が形成されるトランジスタは、電気特性が不安定となる場合がある。 Furthermore, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Furthermore, charges captured in the trap states of the oxide semiconductor may take a long time to disappear and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.
　従って、トランジスタの電気特性を安定にするためには、酸化物半導体中の不純物濃度を低減することが有効である。また、酸化物半導体中の不純物濃度を低減するためには、近接する膜中の不純物濃度も低減することが好ましい。不純物としては、水素、窒素等が挙げられる。なお、酸化物半導体中の不純物とは、例えば、酸化物半導体を構成する主成分以外をいう。例えば、濃度が０．１原子％未満の元素は不純物と言える。 Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen and nitrogen. Note that impurities in an oxide semiconductor refer to, for example, anything other than the main component that constitutes the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.
　また、ＯＳトランジスタは、酸化物半導体中のチャネル形成領域に不純物および酸素欠損が存在すると、電気特性が変動しやすく、信頼性が悪くなる場合がある。また、ＯＳトランジスタは、酸化物半導体中の酸素欠損に水素が入った欠陥（以下、ＶＯＨと呼ぶ場合がある）を形成し、キャリアとなる電子を生成する場合がある。また、チャネル形成領域にＶＯＨが形成されると、チャネル形成領域中のドナー濃度が増加する場合がある。チャネル形成領域中のドナー濃度が増加するにつれ、しきい値電圧がばらつくことがある。このため、酸化物半導体中のチャネル形成領域に酸素欠損が含まれていると、トランジスタはノーマリーオン特性（ゲート電極に電圧を印加しなくてもチャネルが存在し、トランジスタに電流が流れる特性）となりやすい。したがって、酸化物半導体中のチャネル形成領域では、不純物、酸素欠損、およびＶＯＨはできる限り低減されていることが好ましい。 In addition, when impurities and oxygen vacancies are present in a channel formation region in an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, which may result in poor reliability. In addition, an OS transistor may form a defect in which hydrogen enters an oxygen vacancy in an oxide semiconductor (hereinafter, this may be referred to as VOH ), and generate electrons that serve as carriers. When VOH is formed in the channel formation region, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may vary. For this reason, when an oxygen vacancy is present in a channel formation region in an oxide semiconductor, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and a current flows through the transistor even when no voltage is applied to a gate electrode). Therefore, it is preferable that impurities, oxygen vacancies, and VOH be reduced as much as possible in the channel formation region in an oxide semiconductor.
　また、酸化物半導体のバンドギャップは、シリコンのバンドギャップ（代表的には１．１ｅＶ）よりも大きいことが好ましく、好ましくは２ｅＶ以上、より好ましくは２．５ｅＶ以上、さらに好ましくは３．０ｅＶ以上である。シリコンよりも、バンドギャップの大きい酸化物半導体を用いることで、トランジスタのオフ電流（Ｉｏｆｆとも呼称する）を低減することができる。 The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-current (also referred to as Ioff) of the transistor can be reduced.
　また、Ｓｉトランジスタでは、トランジスタの微細化が進むにつれて、短チャネル効果（ショートチャネル効果：Ｓｈｏｒｔ　Ｃｈａｎｎｅｌ　Ｅｆｆｅｃｔ：ＳＣＥともいう）が発現する。そのため、Ｓｉトランジスタでは、微細化が困難となる。短チャネル効果が発現する要因の一つとして、シリコンのバンドギャップが小さいことが挙げられる。一方、ＯＳトランジスタは、バンドギャップの大きい半導体材料である、酸化物半導体を用いるため、短チャネル効果の抑制を図ることができる。別言すると、ＯＳトランジスタは、短チャネル効果がない、または短チャネル効果が極めて少ないトランジスタである。 Furthermore, in Si transistors, as transistors are miniaturized, a short channel effect (also referred to as SCE) occurs. This makes miniaturization of Si transistors difficult. One of the factors that causes the short channel effect is the small band gap of silicon. On the other hand, OS transistors use oxide semiconductors, which are semiconductor materials with a wide band gap, and therefore the short channel effect can be suppressed. In other words, OS transistors are transistors that do not have the short channel effect or have an extremely small short channel effect.
　なお、短チャネル効果とは、トランジスタの微細化（チャネル長の縮小）に伴って顕在化する電気特性の劣化である。短チャネル効果の具体例としては、しきい値電圧の低下、サブスレッショルドスイング値（Ｓ値と表記することがある）の増大、漏れ電流の増大などがある。ここで、Ｓ値とは、ドレイン電圧一定にてドレイン電流を１桁変化させるサブスレッショルド領域でのゲート電圧の変化量をいう。 The short channel effect is a degradation of electrical characteristics that becomes evident as transistors are miniaturized (reduced channel length). Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes written as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.
　また、短チャネル効果に対する耐性の指標として、特性長（Ｃｈａｒａｃｔｅｒｉｓｔｉｃ　Ｌｅｎｇｔｈ）が広く用いられている。特性長とは、チャネル形成領域のポテンシャルの曲がりやすさの指標である。特性長が小さいほどポテンシャルが急峻に立ち上がるため、短チャネル効果に強いといえる。 Furthermore, the characteristic length is widely used as an index of resistance to short channel effects. Characteristic length is an index of how easily the potential of the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to short channel effects.
　ＯＳトランジスタは蓄積型のトランジスタであり、Ｓｉトランジスタは反転型のトランジスタである。したがって、Ｓｉトランジスタと比較して、ＯＳトランジスタは、ソース領域−チャネル形成領域間の特性長、及びドレイン領域−チャネル形成領域間の特性長が小さい。したがって、ＯＳトランジスタは、Ｓｉトランジスタよりも短チャネル効果に強い。すなわち、チャネル長の短いトランジスタを作製したい場合においては、ＯＳトランジスタは、Ｓｉトランジスタよりも好適である。 OS transistors are accumulation-type transistors, while Si transistors are inversion-type transistors. Therefore, compared to Si transistors, OS transistors have smaller characteristic lengths between the source region and the channel-forming region, and between the drain region and the channel-forming region. Therefore, OS transistors are more resistant to the short-channel effect than Si transistors. In other words, when it is desired to manufacture a transistor with a short channel length, OS transistors are more suitable than Si transistors.
　チャネル形成領域がｉ型又は実質的にｉ型となるまで、酸化物半導体のキャリア濃度を下げた場合においても、短チャネルのトランジスタではＣｏｎｄｕｃｔｉｏｎ−Ｂａｎｄ−Ｌｏｗｅｒｉｎｇ（ＣＢＬ）効果により、チャネル形成領域の伝導帯下端が下がるため、ソース領域またはドレイン領域と、チャネル形成領域との間の伝導帯下端のエネルギー差は、０．１ｅＶ以上０．２ｅＶ以下まで小さくなる可能性がある。これにより、ＯＳトランジスタは、チャネル形成領域がｎ−型の領域となり、ソース領域およびドレイン領域がｎ＋型の領域となる、ｎ＋／ｎ−／ｎ＋の蓄積型ｊｕｎｃｔｉｏｎ−ｌｅｓｓトランジスタ構造、または、ｎ＋／ｎ−／ｎ＋の蓄積型ｎｏｎ−ｊｕｎｃｔｉｏｎトランジスタ構造と、捉えることもできる。 Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band bottom of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, so that the energy difference between the conduction band bottom between the source region or drain region and the channel formation region can be reduced to 0.1 eV to 0.2 eV. Thus, the OS transistor can also be regarded as having an n + / n − /n + accumulation-type junction-less transistor structure or an n + /n − /n + accumulation-type non-junction transistor structure in which the channel formation region is an n − type region and the source region and drain region are n + type regions.
　ＯＳトランジスタを、上記の構造とすることで、半導体装置を微細化または高集積化しても良好な電気特性を有することができる。例えば、ＯＳトランジスタのゲート長が、２０ｎｍ以下、１５ｎｍ以下、１０ｎｍ以下、７ｎｍ以下、または６ｎｍ以下であって、１ｎｍ以上、３ｎｍ以上、または５ｎｍ以上であっても、良好な電気特性を得ることができる。一方で、Ｓｉトランジスタは、短チャネル効果が発現するため、２０ｎｍ以下、または１５ｎｍ以下のゲート長とすることが困難な場合がある。したがって、ＯＳトランジスタは、Ｓｉトランジスタと比較してチャネル長の短いトランジスタに好適に用いることができる。なお、ゲート長とは、トランジスタ動作時にキャリアがチャネル形成領域内部を移動する方向における、ゲート電極の長さであり、トランジスタの平面視における、ゲート電極の底面の幅をいう。 By using the above-mentioned structure, the OS transistor can have good electrical characteristics even when the semiconductor device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, it may be difficult to achieve a gate length of 20 nm or less or 15 nm or less in a Si transistor because of the short channel effect. Therefore, the OS transistor can be suitably used as a transistor having a shorter channel length than that of a Si transistor. Note that the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region when the transistor is operating, and refers to the width of the bottom surface of the gate electrode in a plan view of the transistor.
　また、ＯＳトランジスタを微細化することで、トランジスタの周波数特性を向上させることができる。具体的には、トランジスタの遮断周波数を向上させることができる。ＯＳトランジスタのゲート長が上記範囲のいずれかである場合、トランジスタの遮断周波数を、例えば室温環境下で、５０ＧＨｚ以上、好ましくは１００ＧＨｚ以上、さらに好ましくは１５０ＧＨｚ以上とすることができる。 Furthermore, miniaturization of the OS transistor can improve the frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of the OS transistor is within any of the above ranges, the cutoff frequency of the transistor can be set to, for example, 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more in a room temperature environment.
　以上の説明の通り、ＯＳトランジスタは、Ｓｉトランジスタと比較し、オフ電流が小さいこと、チャネル長の短いトランジスタの作製が可能なこと、といった優れた効果を有する。 As explained above, compared to Si transistors, OS transistors have the excellent advantages of having a smaller off-state current and being able to fabricate transistors with a short channel length.
　本実施の形態に示す構成、構造、方法などは、他の実施の形態などに示す構成、構造、方法などと適宜組み合わせて用いることができる。 The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments.
（実施の形態３）
　本実施の形態では、本発明の一態様のトランジスタを用いた記憶装置について図２２乃至図２８を用いて説明する。 (Embodiment 3)
In this embodiment, a memory device including a transistor of one embodiment of the present invention will be described with reference to FIGS.
　本実施の形態では、上記実施の形態で説明したトランジスタを有するメモリセルを用いた記憶装置の構成例について説明する。本実施の形態では、積層されたメモリセルを有する層と、メモリセルに保持したデータ電位を増幅して出力する機能を有する機能回路を有する層が設けられた、記憶装置の構成例について説明する。 In this embodiment, a configuration example of a memory device using a memory cell having a transistor described in the above embodiment is described. In this embodiment, a configuration example of a memory device is described in which a layer having stacked memory cells and a layer having a functional circuit having a function of amplifying and outputting a data potential held in the memory cell are provided.
［記憶装置の構成例］
　図２２に、本発明の一態様の記憶装置のブロック図を示す。 [Example of storage device configuration]
FIG. 22 illustrates a block diagram of a storage device of one embodiment of the present invention.
　図２２に示す記憶装置３００は、駆動回路２１と、メモリアレイ２０と、を有する。メモリアレイ２０は、複数のメモリセル１０と、複数の機能回路５１を有する機能層５０と、を有する。 The memory device 300 shown in FIG. 22 has a drive circuit 21 and a memory array 20. The memory array 20 has a plurality of memory cells 10 and a functional layer 50 having a plurality of functional circuits 51.
　図２２では、メモリアレイ２０がｍ行ｎ列（ｍ及びｎは２以上の整数。）のマトリクス状に配置された複数のメモリセル１０を有する例を示している。また、図２２では、機能回路５１を、ビット線として機能する配線ＢＬごとに設ける例を示しており、機能層５０が、ｎ本の配線ＢＬに対応して設けられたｎ個の機能回路５１を有する例を示している。 FIG. 22 shows an example in which the memory array 20 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more). FIG. 22 also shows an example in which a functional circuit 51 is provided for each wiring BL that functions as a bit line, and an example in which the functional layer 50 has n functional circuits 51 provided corresponding to the n wirings BL.
　図２２では、１行１列目のメモリセル１０をメモリセル１０［１，１］と示し、ｍ行ｎ列目のメモリセル１０をメモリセル１０［ｍ，ｎ］と示している。また、本実施の形態などでは、任意の行を示す場合にｉ行と記す場合がある。また、任意の列を示す場合にｊ列と記す場合がある。よって、ｉは１以上ｍ以下の整数であり、ｊは１以上ｎ以下の整数である。また、本実施の形態などでは、ｉ行ｊ列目のメモリセル１０をメモリセル１０［ｉ，ｊ］と示している。なお、本実施の形態などにおいて、「ｉ＋α」（αは正または負の整数）と示す場合は、「ｉ＋α」は１を下回らず、ｍを超えない。同様に、「ｊ＋α」と示す場合は、「ｊ＋α」は１を下回らず、ｎを超えない。 22, the memory cell 10 in the first row and first column is indicated as memory cell 10[1,1], and the memory cell 10 in the mth row and nth column is indicated as memory cell 10[m,n]. In this embodiment and the like, an arbitrary row may be indicated as row i. An arbitrary column may be indicated as column j. Thus, i is an integer between 1 and m, and j is an integer between 1 and n. In this embodiment and the like, the memory cell 10 in the ith row and jth column is indicated as memory cell 10[i,j]. In this embodiment and the like, when "i+α" (α is a positive or negative integer) is indicated, "i+α" is not less than 1 and does not exceed m. Similarly, when "j+α" is indicated, "j+α" is not less than 1 and does not exceed n.
　また、メモリアレイ２０は、行方向に延在するｍ本の配線ＷＬと、行方向に延在するｍ本の配線ＰＬと、列方向に延在するｎ本の配線ＢＬと、を備える。本実施の形態などでは、１本目（１行目）に設けられた配線ＷＬを配線ＷＬ［１］と示し、ｍ本目（ｍ行目）に設けられた配線ＷＬを配線ＷＬ［ｍ］と示す。同様に、１本目（１行目）に設けられた配線ＰＬを配線ＰＬ［１］と示し、ｍ本目（ｍ行目）に設けられた配線ＰＬを配線ＰＬ［ｍ］と示す。同様に、１本目（１列目）に設けられた配線ＢＬを配線ＢＬ［１］と示し、ｎ本目（ｎ列目）に設けられた配線ＢＬを配線ＢＬ［ｎ］と示す。 The memory array 20 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment and the like, the first wiring WL (first row) is indicated as wiring WL[1], and the mth wiring WL (mth row) is indicated as wiring WL[m]. Similarly, the first wiring PL (first row) is indicated as wiring PL[1], and the mth wiring PL (mth row) is indicated as wiring PL[m]. Similarly, the first wiring BL (first column) is indicated as wiring BL[1], and the nth wiring BL (nth column) is indicated as wiring BL[n].
　ｉ行目に設けられた複数のメモリセル１０は、ｉ行目の配線ＷＬ（配線ＷＬ［ｉ］）とｉ行目の配線ＰＬ（配線ＰＬ［ｉ］）に電気的に接続される。ｊ列目に設けられた複数のメモリセル１０は、ｊ列目の配線ＢＬ（配線ＢＬ［ｊ］）と電気的に接続される。 The multiple memory cells 10 in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The multiple memory cells 10 in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).
　メモリアレイ２０には、ＤＯＳＲＡＭ（登録商標）（Ｄｙｎａｍｉｃ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）を適用することができる。ＤＯＳＲＡＭは、１Ｔ（トランジスタ）１Ｃ（容量）型のメモリセルを有するＲＡＭであり、アクセストランジスタがＯＳトランジスタであるメモリのことをいう。ＯＳトランジスタはオフ状態でソースとドレインとの間を流れる電流、つまりリーク電流が極めて小さい。ＤＯＳＲＡＭは、アクセストランジスタをオフ（非導通状態）にすることで、容量素子（キャパシタ）に保持しているデータに応じた電荷を長時間保持することが可能である。そのためＤＯＳＲＡＭは、チャネル形成領域にシリコンを有するトランジスタ（Ｓｉトランジスタ）で構成されるＤＲＡＭと比較して、リフレッシュ動作の頻度を低減できる。その結果、低消費電力化を図ることができる。また、ＯＳトランジスタの周波数特性は高いため、記憶装置の読み出し、及び書き込みを高速に行うことができる。これにより、動作速度が速い記憶装置を提供することができる。 The memory array 20 can be a DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM having 1T (transistor) 1C (capacitor) type memory cells, and the access transistor is an OS transistor. The current flowing between the source and drain of an OS transistor in the off state, that is, the leakage current, is extremely small. By turning off (non-conducting) the access transistor, DOSRAM can hold a charge corresponding to the data held in the capacitance element (capacitor) for a long time. Therefore, DOSRAM can reduce the frequency of refresh operations compared to DRAM composed of transistors (Si transistors) having silicon in the channel formation region. As a result, it is possible to reduce power consumption. In addition, since the frequency characteristics of OS transistors are high, reading and writing of the storage device can be performed at high speed. This makes it possible to provide a storage device with high operating speed.
　図２２に示すメモリアレイ２０では、複数のメモリアレイ２０［１］乃至２０［ｍ］を積層して設けることができる。メモリアレイ２０が有するメモリアレイ２０［１］乃至２０［ｍ］は、駆動回路２１が設けられる基板表面の垂直方向に配置することで、メモリセル１０のメモリ密度の向上を図ることができる。 In the memory array 20 shown in FIG. 22, multiple memory arrays 20[1] to 20[m] can be stacked. The memory arrays 20[1] to 20[m] of the memory array 20 can be arranged in the vertical direction of the substrate surface on which the drive circuit 21 is provided, thereby improving the memory density of the memory cells 10.
　配線ＢＬは、データの書き込み及び読み出しを行うためのビット線として機能する。配線ＷＬは、スイッチとして機能するアクセストランジスタのオンまたはオフ（導通状態または非導通状態）を制御するためのワード線として機能する。配線ＰＬは、容量素子に接続される定電位線としての機能を有する。なお、アクセストランジスタであるＯＳトランジスタのバックゲートにバックゲート電位を伝える機能を有する配線として、配線ＣＬ（図示せず）を別途設けることができる。また、配線ＰＬが、バックゲート電位を伝える機能を兼ねる構成にしてもよい。 The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on or off (conductive or non-conductive state) of an access transistor that functions as a switch. The wiring PL functions as a constant potential line connected to a capacitance element. Note that a wiring CL (not shown) can be separately provided as a wiring having a function of transmitting a backgate potential to the backgate of the OS transistor that is the access transistor. The wiring PL may also be configured to have a function of transmitting a backgate potential.
　メモリアレイ２０［１］乃至２０［ｍ］がそれぞれ有するメモリセル１０は、配線ＢＬを介して機能回路５１に接続される。配線ＢＬは、駆動回路２１が設けられる基板表面の垂直方向に配置することができる。メモリアレイ２０［１］乃至２０［ｍ］が有するメモリセル１０から延びて設けられる配線ＢＬを基板表面の垂直方向に設けることで、メモリアレイ２０と機能回路５１との間の配線の長さを短くできる。そのため、ビット線に接続される２つの回路の間の信号伝搬距離を短くでき、ビット線の抵抗及び寄生容量が大幅に削減されるため、消費電力及び信号遅延の低減が実現できる。またメモリセル１０が有する容量素子の容量を小さくしても、記憶装置を動作させることが可能となる。 The memory cells 10 in each of the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 via wiring BL. The wiring BL can be arranged in a vertical direction to the substrate surface on which the driver circuit 21 is provided. By arranging the wiring BL extending from the memory cells 10 in the memory arrays 20[1] to 20[m] in a vertical direction to the substrate surface, the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened. As a result, the signal propagation distance between the two circuits connected to the bit line can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thereby reducing power consumption and signal delay. In addition, the memory device can be operated even if the capacitance of the capacitive element in the memory cell 10 is reduced.
　機能回路５１は、メモリセル１０に保持したデータ電位を増幅し、後述する配線ＧＢＬ（図示せず）を介して駆動回路２１が有するセンスアンプ４６に出力する機能を有する。当該構成にすることで、データ読み出し時に配線ＢＬのわずかな電位差を増幅することができる。配線ＧＢＬは、配線ＢＬと同様に駆動回路２１が設けられる基板表面の垂直方向に配置することができる。メモリアレイ２０［１］乃至２０［ｍ］が有するメモリセル１０から延びて設けられる配線ＢＬ及び配線ＧＢＬを基板表面の垂直方向に設けることで、機能回路５１とセンスアンプ４６との間の配線の長さを短くできる。そのため、配線ＧＢＬに接続される２つの回路の間の信号伝搬距離を短くでき、配線ＧＢＬの抵抗及び寄生容量が大幅に削減されるため、消費電力及び信号遅延の低減が実現できる。 The functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 of the driver circuit 21 via the wiring GBL (not shown) described later. This configuration makes it possible to amplify the slight potential difference of the wiring BL when reading data. The wiring GBL can be arranged in the vertical direction of the substrate surface on which the driver circuit 21 is provided, just like the wiring BL. By arranging the wiring BL and wiring GBL extending from the memory cell 10 of the memory arrays 20[1] to 20[m] in the vertical direction of the substrate surface, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, the signal propagation distance between the two circuits connected to the wiring GBL can be shortened, and the resistance and parasitic capacitance of the wiring GBL can be significantly reduced, thereby reducing power consumption and signal delay.
　なお配線ＢＬは、メモリセル１０が有するトランジスタの半導体層に接して設けられる。あるいは配線ＢＬは、メモリセル１０が有するトランジスタの半導体層のソースまたはドレインとして機能する領域に接して設けられる。あるいは配線ＢＬは、メモリセル１０が有するトランジスタの半導体層のソースまたはドレインとして機能する領域と接して設けられる導電体に接して設けられる。つまり配線ＢＬは、メモリアレイ２０の各層におけるメモリセル１０が有するトランジスタのソースまたはドレインの一方のそれぞれと、機能回路５１と、を垂直方向で電気的に接続するための配線であるといえる。 The wiring BL is provided in contact with the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in contact with a conductor that is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the memory cell 10. In other words, the wiring BL can be said to be a wiring for electrically connecting one of the source or drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51 in the vertical direction.
　メモリアレイ２０は、駆動回路２１上に重ねて設けることができる。駆動回路２１とメモリアレイ２０を重ねて設けることで、駆動回路２１とメモリアレイ２０の間の信号伝搬距離を短くすることができる。よって、駆動回路２１とメモリアレイ２０の間の抵抗及び寄生容量が低減され、消費電力及び信号遅延の低減が実現できる。また、記憶装置３００の小型化が実現できる。 The memory array 20 can be stacked on the drive circuit 21. By stacking the drive circuit 21 and the memory array 20, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. This reduces the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20, and reduces power consumption and signal delay. In addition, the storage device 300 can be made smaller.
　機能回路５１は、ＤＯＳＲＡＭのメモリセル１０が有するトランジスタと同様にＯＳトランジスタを用いることで、メモリアレイ２０［１］乃至２０［ｍ］と同様にしてＳｉトランジスタを用いた回路上などに自由に配置可能であるため、集積化を容易に行うことができる。機能回路５１で信号を増幅する構成とすることで後段の回路であるセンスアンプ４６等の回路を小型化できるため、記憶装置３００の小型化を図ることができる。 The functional circuit 51 uses OS transistors similar to the transistors in the memory cells 10 of the DOSRAM, and can be freely arranged on circuits using Si transistors similar to the memory arrays 20[1] to 20[m], making integration easy. By configuring the functional circuit 51 to amplify signals, the circuits in the subsequent stage, such as the sense amplifier 46, can be made smaller, and the memory device 300 can be made smaller.
　駆動回路２１は、ＰＳＷ２２（パワースイッチ）、ＰＳＷ２３、及び周辺回路３１を有する。周辺回路３１は、周辺回路４１、コントロール回路３２（Ｃｏｎｔｒｏｌ　Ｃｉｒｃｕｉｔ）、及び電圧生成回路３３を有する。 The drive circuit 21 has a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 has a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.
　記憶装置３００において、各回路、各信号及び各電圧は、必要に応じて、適宜取捨することができる。あるいは、他の回路または他の信号を追加してもよい。信号ＢＷ、信号ＣＥ、信号ＧＷ、信号ＣＬＫ、信号ＷＡＫＥ、信号ＡＤＤＲ、信号ＷＤＡ、信号ＰＯＮ１、信号ＰＯＮ２は外部からの入力信号であり、信号ＲＤＡは外部への出力信号である。信号ＣＬＫはクロック信号である。 In the storage device 300, each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside. Signal CLK is a clock signal.
　また、信号ＢＷ、信号ＣＥ、及び信号ＧＷは制御信号である。信号ＣＥはチップイネーブル信号であり、信号ＧＷはグローバル書き込みイネーブル信号であり、信号ＢＷはバイト書き込みイネーブル信号である。信号ＡＤＤＲはアドレス信号である。信号ＷＤＡは書き込みデータであり、信号ＲＤＡは読み出しデータである。信号ＰＯＮ１、信号ＰＯＮ２は、パワーゲーティング制御用信号である。なお、信号ＰＯＮ１、信号ＰＯＮ２は、コントロール回路３２で生成してもよい。 Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are signals for power gating control. Signals PON1 and PON2 may be generated by control circuit 32.
　コントロール回路３２は、記憶装置３００の動作全般を制御する機能を有するロジック回路である。例えば、コントロール回路は、信号ＣＥ、信号ＧＷ及び信号ＢＷを論理演算して、記憶装置３００の動作モード（例えば、書き込み動作、読み出し動作）を決定する。または、コントロール回路３２は、この動作モードが実行されるように、周辺回路４１の制御信号を生成する。 The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
　電圧生成回路３３は負電圧を生成する機能を有する。信号ＷＡＫＥは、信号ＣＬＫの電圧生成回路３３への入力を制御する機能を有する。例えば、信号ＷＡＫＥにＨレベルの信号が与えられると、信号ＣＬＫが電圧生成回路３３へ入力され、電圧生成回路３３は負電圧を生成する。 The voltage generation circuit 33 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.
　周辺回路４１は、メモリセル１０に対するデータの書き込み及び読み出しを行うための回路である。また周辺回路４１は、機能回路５１を制御するための各種信号を出力する回路である。周辺回路４１は、行デコーダ４２（Ｒｏｗ　Ｄｅｃｏｄｅｒ）、列デコーダ４４（Ｃｏｌｕｍｎ　Ｄｅｃｏｄｅｒ）、行ドライバ４３（Ｒｏｗ　Ｄｒｉｖｅｒ）、列ドライバ４５（Ｃｏｌｕｍｎ　Ｄｒｉｖｅｒ）、入力回路４７（Ｉｎｐｕｔ　Ｃｉｒ．）、出力回路４８（Ｏｕｔｐｕｔ　Ｃｉｒ．）、センスアンプ４６（Ｓｅｎｓｅ　Ａｍｐｌｉｆｉｅｒ）を有する。 The peripheral circuit 41 is a circuit for writing and reading data to the memory cells 10. The peripheral circuit 41 is also a circuit for outputting various signals for controlling the functional circuit 51. The peripheral circuit 41 has a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.
　行デコーダ４２及び列デコーダ４４は、信号ＡＤＤＲをデコードする機能を有する。行デコーダ４２は、アクセスする行を指定するための回路であり、列デコーダ４４は、アクセスする列を指定するための回路である。行ドライバ４３は、行デコーダ４２が指定する配線ＷＬを選択する機能を有する。列ドライバ４５は、データをメモリセル１０に書き込む機能、メモリセル１０からデータを読み出す機能、読み出したデータを保持する機能等を有する。 The row decoder 42 and column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying the row to be accessed, and the column decoder 44 is a circuit for specifying the column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cell 10, reading data from the memory cell 10, and retaining the read data.
　入力回路４７は、信号ＷＤＡを保持する機能を有する。入力回路４７が保持するデータは、列ドライバ４５に出力される。入力回路４７の出力データが、メモリセル１０に書き込むデータ（Ｄｉｎ）である。列ドライバ４５がメモリセル１０から読み出したデータ（Ｄｏｕｔ）は、出力回路４８に出力される。出力回路４８は、Ｄｏｕｔを保持する機能を有する。また、出力回路４８は、Ｄｏｕｔを記憶装置３００の外部に出力する機能を有する。出力回路４８から出力されるデータが信号ＲＤＡである。 The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is the signal RDA.
　ＰＳＷ２２は周辺回路３１へのＶＤＤの供給を制御する機能を有する。ＰＳＷ２３は、行ドライバ４３へのＶＨＭの供給を制御する機能を有する。ここでは、記憶装置３００の高電源電圧がＶＤＤであり、低電源電圧はＧＮＤ（接地電位）である。また、ＶＨＭは、ワード線を高レベルにするために用いられる高電源電圧であり、ＶＤＤよりも高い。信号ＰＯＮ１によってＰＳＷ２２のオン・オフが制御され、信号ＰＯＮ２によってＰＳＷ２３のオン・オフが制御される。図２２では、周辺回路３１において、ＶＤＤが供給される電源ドメインの数を１としているが、複数にすることもできる。この場合、各電源ドメインに対してパワースイッチを設ければよい。 PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 300 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD. The on/off of PSW22 is controlled by signal PON1, and the on/off of PSW23 is controlled by signal PON2. In FIG. 22, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it is also possible to have multiple power domains. In this case, a power switch can be provided for each power supply domain.
　メモリアレイ２０［１］乃至２０［ｍ］（ｍは２以上の整数）及び機能層５０を有するメモリアレイ２０は、駆動回路２１上に複数層のメモリアレイ２０を重ねて設けることができる。複数層のメモリアレイ２０を重ねて設けることで、メモリセル１０のメモリ密度を高めることができる。図２３Ａに、駆動回路２１上に機能層５０と、５層（ｍ＝５）のメモリアレイ２０［１］乃至２０［５］と、を重ねて有する記憶装置３００の斜視図を示している。 The memory array 20 having memory arrays 20[1] to 20[m] (m is an integer of 2 or more) and a functional layer 50 can be provided by stacking multiple layers of memory arrays 20 on a driving circuit 21. By stacking multiple layers of memory arrays 20, the memory density of the memory cells 10 can be increased. Figure 23A shows a perspective view of a storage device 300 having a functional layer 50 and five layers (m=5) of memory arrays 20[1] to 20[5] stacked on a driving circuit 21.
　図２３Ａでは、１層目に設けられたメモリアレイ２０をメモリアレイ２０［１］と示し、２層目に設けられたメモリアレイ２０をメモリアレイ２０［２］と示し、５層目に設けられたメモリアレイ２０をメモリアレイ２０［５］と示している。また図２３Ａにおいて、Ｘ方向に延びて設けられる配線ＷＬ、配線ＰＬ及び配線ＣＬと、Ｚ方向（駆動回路が設けられる基板表面に垂直な方向）に延びて設けられる配線ＢＬと、を図示している。なお、図面を見やすくするため、メモリアレイ２０それぞれが有する配線ＷＬ及び配線ＰＬの記載を一部省略している。 In FIG. 23A, the memory array 20 provided in the first layer is shown as memory array 20[1], the memory array 20 provided in the second layer is shown as memory array 20[2], and the memory array 20 provided in the fifth layer is shown as memory array 20[5]. Also shown in FIG. 23A are wiring WL, wiring PL, and wiring CL extending in the X direction, and wiring BL extending in the Z direction (the direction perpendicular to the substrate surface on which the drive circuit is provided). Note that to make the drawing easier to understand, some of the wiring WL and wiring PL of each memory array 20 have been omitted.
　図２３Ｂに、図２３Ａで図示した配線ＢＬに接続された機能回路５１、及び配線ＢＬに接続されたメモリアレイ２０［１］乃至２０［５］が有するメモリセル１０の構成例を説明する模式図を示す。また図２３Ｂでは、機能回路５１と駆動回路２１との間に設けられる配線ＧＢＬを図示している。なお、１つの配線ＢＬに複数のメモリセル（メモリセル１０）が電気的に接続される構成を「メモリストリング」ともいう。なお図面において、配線ＧＢＬは、視認性を高めるため、太線で図示する場合がある。 FIG. 23B is a schematic diagram illustrating an example of the configuration of the functional circuit 51 connected to the wiring BL shown in FIG. 23A, and the memory cells 10 in the memory arrays 20[1] to 20[5] connected to the wiring BL. FIG. 23B also illustrates the wiring GBL provided between the functional circuit 51 and the driver circuit 21. Note that a configuration in which multiple memory cells (memory cells 10) are electrically connected to one wiring BL is also referred to as a "memory string." Note that in the drawings, the wiring GBL may be illustrated with a thick line to improve visibility.
　図２３Ｂでは、配線ＢＬに接続されるメモリセル１０の回路構成の一例を図示している。メモリセル１０は、トランジスタ１１及び容量素子１２を有する。トランジスタ１１、容量素子１２、及び各配線（配線ＢＬ、及び配線ＷＬなど）についても、例えば配線ＢＬ［１］及び配線ＷＬ［１］を配線ＢＬ及び配線ＷＬなどのようにいう場合がある。ここで、トランジスタ１１は、実施の形態１で示したトランジスタ２００と対応する。 FIG. 23B illustrates an example of a circuit configuration of a memory cell 10 connected to wiring BL. The memory cell 10 has a transistor 11 and a capacitor 12. The transistor 11, the capacitor 12, and each wiring (such as wiring BL and wiring WL) may also be referred to as wiring BL[1] and wiring WL[1], for example. Here, the transistor 11 corresponds to the transistor 200 described in embodiment 1.
　メモリセル１０において、トランジスタ１１のソースまたはドレインの一方は配線ＢＬに接続される。トランジスタ１１のソースまたはドレインの他方は容量素子１２の一方の電極に接続される。容量素子１２の他方の電極は、配線ＰＬに接続される。トランジスタ１１のゲートは配線ＷＬに接続される。トランジスタ１１のバックゲートは配線ＣＬに接続される。 In memory cell 10, one of the source and drain of transistor 11 is connected to wiring BL. The other of the source and drain of transistor 11 is connected to one electrode of capacitance element 12. The other electrode of capacitance element 12 is connected to wiring PL. The gate of transistor 11 is connected to wiring WL. The backgate of transistor 11 is connected to wiring CL.
　配線ＰＬは、容量素子１２の電位を保持するための定電位を与える配線である。配線ＣＬは、トランジスタ１１のしきい値電圧を制御するための定電位を与える配線である。配線ＰＬと配線ＣＬは、同じ電位でもよい。この場合、２つの配線を接続することで、メモリセル１０に接続される配線数を削減することができる。 The wiring PL is a wiring that provides a constant potential to maintain the potential of the capacitance element 12. The wiring CL is a wiring that provides a constant potential to control the threshold voltage of the transistor 11. The wiring PL and the wiring CL may be at the same potential. In this case, by connecting the two wirings, the number of wirings connected to the memory cell 10 can be reduced.
　図２３Ｂに図示する配線ＧＢＬは、駆動回路２１と機能層５０との間を電気的に接続するように設けられる。図２４Ａでは、機能回路５１、及びメモリアレイ２０［１］乃至２０［ｍ］を繰り返し単位７０とする記憶装置３００の模式図を示している。なお図２４Ａでは、配線ＧＢＬを１本図示しているが、配線ＧＢＬは機能層５０に設けられる機能回路５１の数に応じて適宜設ければよい。 The wiring GBL shown in FIG. 23B is provided to electrically connect the drive circuit 21 and the functional layer 50. FIG. 24A shows a schematic diagram of a memory device 300 in which a functional circuit 51 and memory arrays 20[1] to 20[m] are repeated as a unit 70. Note that while FIG. 24A shows one wiring GBL, the wiring GBL may be provided as appropriate according to the number of functional circuits 51 provided in the functional layer 50.
　なお配線ＧＢＬは、機能回路５１が有するトランジスタの半導体層に接して設けられる。あるいは配線ＧＢＬは、機能回路５１が有するトランジスタの半導体層のソースまたはドレインとして機能する領域に接して設けられる。あるいは配線ＧＢＬは、機能回路５１が有するトランジスタの半導体層のソースまたはドレインとして機能する領域と接して設けられる導電体に接して設けられる。つまり配線ＧＢＬは、機能層５０における機能回路５１が有するトランジスタのソースまたはドレインの一方と、駆動回路２１と、を垂直方向で電気的に接続するための配線であるといえる。 The wiring GBL is provided in contact with the semiconductor layer of the transistor in the functional circuit 51. Alternatively, the wiring GBL is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor in the functional circuit 51. Alternatively, the wiring GBL is provided in contact with a conductor that is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor in the functional circuit 51. In other words, the wiring GBL can be said to be a wiring for electrically connecting one of the source or drain of the transistor in the functional circuit 51 in the functional layer 50 to the driver circuit 21 in the vertical direction.
　また機能回路５１、及びメモリアレイ２０［１］乃至２０［ｍ］を有する繰り返し単位７０は、さらに積層する構成としてもよい。本発明の一態様の記憶装置３００Ａは、図２４Ｂに図示するように繰り返し単位７０［１］乃至７０［ｐ］（ｐは２以上の整数）とすることができる。配線ＧＢＬは繰り返し単位７０が有する機能層５０に接続される。配線ＧＢＬは、機能回路５１の数に応じて適宜設ければよい。 Furthermore, the repeating unit 70 including the functional circuit 51 and the memory arrays 20[1] to 20[m] may be further stacked. The memory device 300A of one embodiment of the present invention can have repeating units 70[1] to 70[p] (p is an integer of 2 or more) as illustrated in FIG. 24B. The wiring GBL is connected to the functional layer 50 included in the repeating unit 70. The wiring GBL may be provided as appropriate depending on the number of functional circuits 51.
　本発明の一形態では、ＯＳトランジスタを積層して設けるとともに、ビット線として機能する配線を、駆動回路２１が設けられる基板表面の垂直方向に配置する。メモリアレイ２０から延びて設けられるビット線として機能する配線を基板表面の垂直方向に設けることで、メモリアレイ２０と駆動回路２１との間の配線の長さを短くできる。そのため、ビット線の寄生容量を大幅に削減できる。 In one embodiment of the present invention, OS transistors are stacked, and wiring that functions as bit lines is arranged in a vertical direction to the substrate surface on which the driver circuit 21 is provided. By arranging the wiring that functions as bit lines extending from the memory array 20 in a vertical direction to the substrate surface, the length of the wiring between the memory array 20 and the driver circuit 21 can be shortened. This allows the parasitic capacitance of the bit lines to be significantly reduced.
　また本発明の一形態は、メモリアレイ２０が設けられる層において、メモリセル１０に保持したデータ電位を増幅して出力する機能を有する機能回路５１を有する機能層５０を備えている。当該構成にすることで、データ読み出し時にビット線として機能する配線ＢＬのわずかな電位差を増幅して、駆動回路２１が有するセンスアンプ４６を駆動することができる。センスアンプ等の回路を小型化できるため、記憶装置３００の小型化を図ることができる。またメモリセル１０が有する容量素子１２の容量を小さくしても記憶装置３００を動作させることが可能となる。 In one embodiment of the present invention, the layer in which the memory array 20 is provided includes a functional layer 50 having a functional circuit 51 that has a function of amplifying and outputting the data potential held in the memory cell 10. With this configuration, the slight potential difference of the wiring BL that functions as a bit line when reading data can be amplified to drive the sense amplifier 46 of the drive circuit 21. Since the circuits such as the sense amplifier can be miniaturized, the memory device 300 can be miniaturized. In addition, the memory device 300 can be operated even if the capacitance of the capacitive element 12 in the memory cell 10 is reduced.
　なお、上記においては、メモリアレイ２０［１］乃至２０［ｍ］を有する記憶装置について説明したが、本発明に係る半導体装置は、メモリアレイ２０［１］だけを有する単層の記憶装置についても用いることができる。 Although the above describes a memory device having memory arrays 20[1] to 20[m], the semiconductor device according to the present invention can also be used for a single-layer memory device having only memory array 20[1].
［メモリアレイ２０及び機能回路５１の構成例］
　図２５を用いて、図２２乃至図２４で説明した機能回路５１の構成例、及びメモリアレイ２０及び駆動回路２１が有するセンスアンプ４６の構成例について説明する。図２５では、異なる配線ＢＬ（配線ＢＬ＿Ａ、配線ＢＬ＿Ｂ）に接続されたメモリセル１０（メモリセル１０＿Ａ、メモリセル１０＿Ｂ）に接続された機能回路５１（機能回路５１＿Ａ、機能回路５１＿Ｂ）に接続される配線ＧＢＬ（配線ＧＢＬ＿Ａ、配線ＧＢＬ＿Ｂ）に接続された駆動回路２１を図示している。図２５に図示する駆動回路２１として、センスアンプ４６の他、プリチャージ回路７１＿Ａ、プリチャージ回路７１＿Ｂ、スイッチ回路７２＿Ａ、スイッチ回路７２＿Ｂ及び書き込み読み出し回路７３を図示している。 [Example of configuration of memory array 20 and functional circuit 51]
25, a configuration example of the functional circuit 51 described in FIG. 22 to FIG. 24 and a configuration example of the sense amplifier 46 included in the memory array 20 and the driver circuit 21 will be described. In FIG. 25, the driver circuit 21 connected to wirings GBL (wirings GBL_A, GBL_B) connected to functional circuits 51 (functional circuits 51_A, 51_B) connected to memory cells 10 (memory cells 10_A, 10_B) connected to different wirings BL (wirings BL_A, BL_B) is illustrated. As the driver circuit 21 illustrated in FIG. 25, in addition to the sense amplifier 46, a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write/read circuit 73 are illustrated.
　機能回路５１＿Ａ、５１＿Ｂとして、トランジスタ５２＿ａ、５２＿ｂ、５３＿ａ、５３＿ｂ、５４＿ａ、５４＿ｂ、５５＿ａ、５５＿ｂを図示している。図２５に図示するトランジスタ５２＿ａ、５２＿ｂ、５３＿ａ、５３＿ｂ、５４＿ａ、５４＿ｂ、５５＿ａ、５５＿ｂは、メモリセル１０が有するトランジスタ１１と同様にＯＳトランジスタである。機能回路５１を有する機能層５０は、メモリアレイ２０［１］乃至２０［ｍ］と同様に、駆動回路２１上に積層して設けることができる。 Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are illustrated as functional circuits 51_A and 51_B. The transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b illustrated in FIG. 25 are OS transistors, similar to the transistor 11 included in the memory cell 10. The functional layer 50 including the functional circuit 51 can be stacked on the driver circuit 21, similar to the memory arrays 20[1] to 20[m].
　配線ＢＬ＿Ａは、トランジスタ５２＿ａのゲートに接続され、配線ＢＬ＿Ｂはトランジスタ５２＿ｂのゲートに接続される。配線ＧＢＬ＿Ａは、トランジスタ５３＿ａ、５４＿ａのソースまたはドレインの一方が接続される。配線ＧＢＬ＿Ｂは、トランジスタ５３＿ｂ、５４＿ｂのソースまたはドレインの一方が接続される。配線ＧＢＬ＿Ａ、ＧＢＬ＿Ｂは、配線ＢＬ＿Ａ、ＢＬ＿Ｂと同様に垂直方向に設けられ、駆動回路２１が有するトランジスタに接続される。トランジスタ５３＿ａ、５３＿ｂ、５４＿ａ、５４＿ｂ、５５＿ａ、５５＿ｂのゲートには、図２５に示すように、それぞれ、選択信号ＭＵＸ、制御信号ＷＥ、または制御信号ＲＥが与えられる。 Wiring BL_A is connected to the gate of transistor 52_a, and wiring BL_B is connected to the gate of transistor 52_b. One of the sources or drains of transistors 53_a and 54_a is connected to wiring GBL_A. One of the sources or drains of transistors 53_b and 54_b is connected to wiring GBL_B. Wirings GBL_A and GBL_B are provided vertically like wirings BL_A and BL_B, and are connected to transistors in driver circuit 21. As shown in FIG. 25, a selection signal MUX, a control signal WE, or a control signal RE is applied to the gates of transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b, respectively.
　図２５に示すセンスアンプ４６、プリチャージ回路７１＿Ａ、及びプリチャージ回路７１＿Ｂを構成するトランジスタ８１＿１乃至８１＿６、及び８２＿１乃至８２＿４は、Ｓｉトランジスタで構成される。スイッチ回路７２＿Ａ及びスイッチ回路７２＿Ｂを構成するスイッチ８３＿Ａ乃至８３＿ＤもＳｉトランジスタで構成することができる。トランジスタ５３＿ａ、５３＿ｂ、５４＿ａ、５４＿ｂのソースまたはドレインの一方は、プリチャージ回路７１＿Ａ、プリチャージ回路７１＿Ｂ、センスアンプ４６、スイッチ回路７２＿Ａを構成するトランジスタまたはスイッチに接続される。 The transistors 81_1 to 81_6 and 82_1 to 82_4 constituting the sense amplifier 46, precharge circuit 71_A, and precharge circuit 71_B shown in FIG. 25 are composed of Si transistors. The switches 83_A to 83_D constituting the switch circuit 72_A and switch circuit 72_B can also be composed of Si transistors. One of the sources or drains of the transistors 53_a, 53_b, 54_a, and 54_b is connected to the transistors or switches constituting the precharge circuit 71_A, precharge circuit 71_B, sense amplifier 46, and switch circuit 72_A.
　プリチャージ回路７１＿Ａは、ｎチャネル型のトランジスタ８１＿１乃至８１＿３を有する。プリチャージ回路７１＿Ａは、プリチャージ線ＰＣＬ１に与えられるプリチャージ信号に応じて、配線ＢＬ＿Ａ及び配線ＢＬ＿Ｂを高電源電位（ＶＤＤ）と低電源電位（ＶＳＳ）の間の電位ＶＤＤ／２に相当する中間電位ＶＰＣにプリチャージするための回路である。 The precharge circuit 71_A has n-channel transistors 81_1 to 81_3. The precharge circuit 71_A is a circuit for precharging the wiring BL_A and the wiring BL_B to an intermediate potential VPC that corresponds to a potential VDD/2 between a high power supply potential (VDD) and a low power supply potential (VSS) in response to a precharge signal provided to a precharge line PCL1.
　プリチャージ回路７１＿Ｂは、ｎチャネル型のトランジスタ８１＿４乃至８１＿６を有する。プリチャージ回路７１＿Ｂは、プリチャージ線ＰＣＬ２に与えられるプリチャージ信号に応じて、配線ＧＢＬ＿Ａ及び配線ＧＢＬ＿ＢをＶＤＤとＶＳＳの間の電位ＶＤＤ／２に相当する中間電位ＶＰＣにプリチャージするための回路である。 The precharge circuit 71_B has n-channel transistors 81_4 to 81_6. The precharge circuit 71_B is a circuit for precharging the wiring GBL_A and the wiring GBL_B to an intermediate potential VPC that corresponds to a potential VDD/2 between VDD and VSS in response to a precharge signal provided to the precharge line PCL2.
　センスアンプ４６は、配線ＶＨＨまたは配線ＶＬＬに接続された、ｐチャネル型のトランジスタ８２＿１、８２＿２及びｎチャネル型のトランジスタ８２＿３、８２＿４を有する。配線ＶＨＨまたは配線ＶＬＬは、ＶＤＤまたはＶＳＳを与える機能を有する配線である。トランジスタ８２＿１乃至８２＿４は、インバータループを構成するトランジスタである。メモリセル１０＿Ａ、１０＿Ｂを選択することでプリチャージされた配線ＢＬ＿Ａ及び配線ＢＬ＿Ｂの電位が変化し、当該変化に応じて配線ＧＢＬ＿Ａ及び配線ＧＢＬ＿Ｂの電位をＶＤＤまたはＶＳＳとする。配線ＧＢＬ＿Ａ及び配線ＧＢＬ＿Ｂの電位は、スイッチ８３＿Ｃ及びスイッチ８３＿Ｄ、及び書き込み読み出し回路７３を介して外部に出力することができる。配線ＢＬ＿Ａ及び配線ＢＬ＿Ｂ、並びに配線ＧＢＬ＿Ａ及び配線ＧＢＬ＿Ｂは、ビット線対に相当する。書き込み読み出し回路７３は、信号ＥＮ＿ｄａｔａに応じて、データ信号の書き込みが制御される。 The sense amplifier 46 has p-channel transistors 82_1 and 82_2 and n-channel transistors 82_3 and 82_4 connected to the wiring VHH or wiring VLL. The wiring VHH or wiring VLL is a wiring that has a function of providing VDD or VSS. The transistors 82_1 to 82_4 are transistors that form an inverter loop. The potentials of the precharged wirings BL_A and BL_B change by selecting memory cells 10_A and 10_B, and the potentials of the wirings GBL_A and GBL_B are set to VDD or VSS in response to the change. The potentials of the wirings GBL_A and GBL_B can be output to the outside via the switches 83_C and 83_D, and the write/read circuit 73. The wirings BL_A and BL_B, and the wirings GBL_A and GBL_B correspond to bit line pairs. The write/read circuit 73 controls the writing of data signals according to the signal EN_data.
　スイッチ回路７２＿Ａは、センスアンプ４６と配線ＧＢＬ＿Ａ及び配線ＧＢＬ＿Ｂとの間の導通状態を制御するための回路である。スイッチ回路７２＿Ａは、切り替え信号ＣＳＥＬ１の制御によってオンまたはオフが切り替えられる。スイッチ８３＿Ａ及び８３＿Ｂが、ｎチャネルトランジスタの場合、切り替え信号ＣＳＥＬ１がハイレベルでオン、ローレベルでオフとなる。スイッチ回路７２＿Ｂは、書き込み読み出し回路７３と、センスアンプ４６に接続されるビット線対との間の導通状態を制御するための回路である。スイッチ回路７２＿Ｂは、切り替え信号ＣＳＥＬ２の制御によってオンまたはオフが切り替えられる。スイッチ８３＿Ｃ及び８３＿Ｄは、スイッチ８３＿Ａ及び８３＿Ｂと同様に動作すればよい。 The switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wiring GBL_A and wiring GBL_B. The switch circuit 72_A is switched on or off under the control of the switching signal CSEL1. When the switches 83_A and 83_B are n-channel transistors, the switching signal CSEL1 is on at a high level and off at a low level. The switch circuit 72_B is a circuit for controlling the conduction state between the write/read circuit 73 and the bit line pair connected to the sense amplifier 46. The switch circuit 72_B is switched on or off under the control of the switching signal CSEL2. The switches 83_C and 83_D may operate in the same manner as the switches 83_A and 83_B.
　図２５に示すように記憶装置３００は、メモリセル１０と、機能回路５１と、センスアンプ４６と、を最短距離になる垂直方向に設けられる配線ＢＬ及び配線ＧＢＬを介して接続する構成とすることができる。機能回路５１を構成するトランジスタを有する機能層５０が増えるものの、配線ＢＬの負荷が低減されることで、書き込み時間の短縮、およびデータを読み出しやすくすること、ができる。 As shown in FIG. 25, the memory device 300 can be configured to connect the memory cell 10, the functional circuit 51, and the sense amplifier 46 via wiring BL and wiring GBL that are provided in the vertical direction, which is the shortest distance. Although the number of functional layers 50 having transistors that constitute the functional circuit 51 increases, the load on the wiring BL is reduced, which shortens the write time and makes it easier to read data.
　また図２５に示すように機能回路５１＿Ａ、５１＿Ｂが有する各トランジスタは、制御信号ＷＥ、ＲＥ、及び選択信号ＭＵＸに応じて制御される。各トランジスタは、制御信号及び選択信号に応じて、配線ＧＢＬを介して配線ＢＬの電位を駆動回路２１に出力することができる。機能回路５１＿Ａ、５１＿Ｂは、ＯＳトランジスタで構成されるセンスアンプとして機能させることができる。当該構成にすることで、読み出し時に配線ＢＬのわずかな電位差を増幅して、Ｓｉトランジスタを用いたセンスアンプ４６を駆動することができる。 As shown in FIG. 25, each transistor in the functional circuits 51_A and 51_B is controlled in response to control signals WE, RE, and a selection signal MUX. Each transistor can output the potential of the wiring BL to the driver circuit 21 via the wiring GBL in response to the control signal and selection signal. The functional circuits 51_A and 51_B can function as sense amplifiers made up of OS transistors. With this configuration, a slight potential difference in the wiring BL can be amplified during reading to drive the sense amplifier 46 using Si transistors.
＜メモリセルの構成例＞
　図２６Ａを用いて、上記記憶装置に用いられるメモリセル１０の構成例について説明する。 <Example of memory cell configuration>
An example of the configuration of a memory cell 10 used in the memory device will be described with reference to FIG. 26A.
　なお、図２６Ａにおいて、Ｘ方向は、図示するトランジスタのチャネル長方向と平行であり、Ｙ方向は、Ｘ方向に垂直であり、Ｚ方向は、Ｘ方向及びＹ方向に垂直である。 In FIG. 26A, the X direction is parallel to the channel length direction of the illustrated transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions.
　図２６Ａに示すように、メモリセル１０は、トランジスタ１１及び容量素子１２を有する。トランジスタ１１の上には、絶縁体２８５が設けられ、絶縁体２８５の上には、絶縁体２８４が設けられている。絶縁体２８５、及び絶縁体２８４は、絶縁体２１６に用いることが可能な絶縁体を用いればよい。なお、トランジスタ１１は、先の実施の形態に示すトランジスタ２００と同様の構成を有し、同じ構成要素には同符号を付す。トランジスタ２００の詳細については、先の実施の形態を参照することができる。また、トランジスタ１１のソースまたはドレインの一方（導電体２４２ｂ）に接して導電体２４０ｂが設けられる。導電体２４０ｂは、Ｚ方向に延伸して設けられており、配線ＢＬとして機能する。 26A, the memory cell 10 includes a transistor 11 and a capacitor 12. An insulator 285 is provided on the transistor 11, and an insulator 284 is provided on the insulator 285. The insulators 285 and 284 may be made of an insulator that can be used for the insulator 216. The transistor 11 has a similar structure to the transistor 200 described in the previous embodiment, and the same components are denoted by the same reference numerals. For details of the transistor 200, the previous embodiment can be referred to. A conductor 240b is provided in contact with one of the source and drain (conductor 242b) of the transistor 11. The conductor 240b is provided extending in the Z direction and functions as a wiring BL.
　容量素子１２は、導電体２４２ａ上の導電体１５３と、導電体１５３上の絶縁体１５４と、絶縁体１５４上の導電体１６０（導電体１６０ａ及び導電体１６０ｂ）と、を有する。 The capacitance element 12 has a conductor 153 on the conductor 242a, an insulator 154 on the conductor 153, and a conductor 160 (conductor 160a and conductor 160b) on the insulator 154.
　導電体１５３、絶縁体１５４、及び、導電体１６０は、それぞれ、少なくとも一部が、絶縁体２７５、絶縁体２８０、絶縁体２８２、絶縁体２８３及び絶縁体２８５に設けられた開口の内部に配置されている。導電体１５３、絶縁体１５４、及び、導電体１６０のそれぞれの端部は、少なくとも絶縁体２８２上に位置し、好ましくは絶縁体２８５上に位置する。絶縁体１５４は、導電体１５３の端部を覆うように設けられる。これにより、導電体１５３と導電体１６０とを電気的に絶縁させることができる。 At least a portion of conductor 153, insulator 154, and conductor 160 are disposed inside openings provided in insulators 275, 280, 282, 283, and 285, respectively. The ends of conductors 153, 154, and 160 are located at least on insulator 282, and preferably on insulator 285. Insulator 154 is disposed so as to cover the end of conductor 153. This allows electrical insulation between conductor 153 and conductor 160.
　絶縁体２７５、絶縁体２８０、絶縁体２８２、絶縁体２８３及び絶縁体２８５に設けられる開口の深さを深くする（つまり、絶縁体２７５、絶縁体２８０、絶縁体２８２、絶縁体２８３及び絶縁体２８５のうち一つまたは複数の厚さを厚くする）ほど、容量素子１２の静電容量を大きくすることができる。容量素子１２の単位面積当たりの静電容量を大きくすることで、記憶装置の微細化または高集積化を図ることができる。 The deeper the openings provided in insulators 275, 280, 282, 283, and 285 are (i.e., the thicker one or more of insulators 275, 280, 282, 283, and 285 are), the larger the capacitance of capacitive element 12 can be. Increasing the capacitance per unit area of capacitive element 12 allows for miniaturization or high integration of the memory device.
　導電体１５３は、容量素子１２の一方の電極（下部電極）として機能する領域を有する。絶縁体１５４は、容量素子１２の誘電体として機能する領域を有する。導電体１６０は、容量素子１２の他方の電極（上部電極）として機能する領域を有する。また、導電体２６０の上部を延伸させて、図２３Ａ及び図２３Ｂに示す配線ＰＬとして機能させることができる。容量素子１２は、ＭＩＭ（Ｍｅｔａｌ−Ｉｎｓｕｌａｔｏｒ−Ｍｅｔａｌ）容量を構成している。 The conductor 153 has a region that functions as one electrode (lower electrode) of the capacitance element 12. The insulator 154 has a region that functions as a dielectric of the capacitance element 12. The conductor 160 has a region that functions as the other electrode (upper electrode) of the capacitance element 12. In addition, the upper part of the conductor 260 can be extended to function as the wiring PL shown in Figures 23A and 23B. The capacitance element 12 constitutes a MIM (Metal-Insulator-Metal) capacitance.
　また、酸化物２３０上に重畳して設けられた導電体２４２ａは、容量素子１２の導電体１５３と電気的に接続する電極として機能する。 The conductor 242a overlapping the oxide 230 functions as an electrode electrically connected to the conductor 153 of the capacitor 12.
　容量素子１２が有する導電体１５３及び導電体１６０は、それぞれ、導電体２０５、または導電体２６０に用いることができる各種導電体を用いて形成することができる。導電体１５３及び導電体１６０は、それぞれ、ＡＬＤ法またはＣＶＤ法などの被覆性の良好な成膜法を用いて成膜することが好ましい。例えば、導電体１５３として、ＡＬＤ法またはＣＶＤ法を用いて成膜した窒化チタンまたは窒化タンタルを用いることができる。 The conductor 153 and the conductor 160 of the capacitor 12 can be formed using various conductors that can be used for the conductor 205 or the conductor 260, respectively. The conductor 153 and the conductor 160 are preferably formed using a film formation method with good coating properties, such as the ALD method or the CVD method. For example, the conductor 153 can be made of titanium nitride or tantalum nitride formed using the ALD method or the CVD method.
　また、導電体１５３の下面には、導電体２４２ａの上面が接する。ここで、導電体２４２ａとして、導電性の良好な導電性材料を用いることで、導電体１５３と導電体２４２ａとの接触抵抗を低減することができる。 The upper surface of conductor 242a contacts the lower surface of conductor 153. By using a conductive material with good conductivity for conductor 242a, the contact resistance between conductor 153 and conductor 242a can be reduced.
　また、導電体１６０ａとして、ＡＬＤ法またはＣＶＤ法を用いて成膜した窒化チタンを用い、導電体１６０ｂとして、ＣＶＤ法を用いて成膜したタングステンを用いることができる。なお、絶縁体１５４に対するタングステンの密着性が十分高い場合は、導電体１６０として、ＣＶＤ法を用いて成膜したタングステンの単層構造を用いてもよい。 The conductor 160a may be made of titanium nitride formed using the ALD method or the CVD method, and the conductor 160b may be made of tungsten formed using the CVD method. If the adhesion of tungsten to the insulator 154 is sufficiently high, the conductor 160 may be a single layer structure of tungsten formed using the CVD method.
　容量素子１２が有する絶縁体１５４には、高誘電率（ｈｉｇｈ−ｋ）材料（高い比誘電率の材料）を用いることが好ましい。絶縁体１５４は、ＡＬＤ法またはＣＶＤ法などの被覆性の良好な成膜法を用いて成膜することが好ましい。 The insulator 154 of the capacitance element 12 is preferably made of a high-k material (a material with a high relative dielectric constant). The insulator 154 is preferably formed using a film formation method with good coating properties, such as the ALD method or the CVD method.
　高誘電率（ｈｉｇｈ−ｋ）材料の絶縁体としては、例えば、アルミニウム、ハフニウム、ジルコニウム、及びガリウムなどから選ばれた金属元素を一種以上含む、酸化物、酸化窒化物、窒化酸化物、及び窒化物が挙げられる。また、上記酸化物、酸化窒化物、窒化酸化物、または窒化物に、シリコンを含有させてもよい。また、上記の材料からなる絶縁体を積層して用いることもできる。 Examples of high-dielectric constant (high-k) insulators include oxides, oxynitrides, oxynitrides, and nitrides that contain one or more metal elements selected from aluminum, hafnium, zirconium, and gallium. Silicon may also be contained in the oxides, oxynitrides, oxynitrides, or nitrides. Insulators made of the above materials may also be stacked.
　例えば、高誘電率（ｈｉｇｈ−ｋ）材料の絶縁体として、例えば、酸化アルミニウム、酸化ハフニウム、酸化ジルコニウム、アルミニウム及びハフニウムを有する酸化物、アルミニウム及びハフニウムを有する酸化窒化物、シリコン及びハフニウムを有する酸化物、シリコン及びハフニウムを有する酸化窒化物、シリコン及びジルコニウムを有する酸化物、シリコン及びジルコニウムを有する酸化窒化物、ハフニウム及びジルコニウムを有する酸化物、並びに、ハフニウム及びジルコニウムを有する酸化窒化物が挙げられる。このようなｈｉｇｈ−ｋ材料を用いることで、リーク電流を抑制できる程度に絶縁体１５４を厚くし、且つ容量素子１２の静電容量を十分確保することができる。 For example, examples of insulators made of high dielectric constant (high-k) materials include aluminum oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, oxides having silicon and zirconium, oxynitrides having silicon and zirconium, oxides having hafnium and zirconium, and oxynitrides having hafnium and zirconium. By using such high-k materials, the insulator 154 can be made thick enough to suppress leakage current, and the capacitance of the capacitance element 12 can be sufficiently ensured.
　また、上記の材料からなる絶縁体を積層して用いることが好ましく、高誘電率（ｈｉｇｈ−ｋ）材料と、当該高誘電率（ｈｉｇｈ−ｋ）材料より絶縁耐力が大きい材料との積層構造を用いることが好ましい。例えば、絶縁体１５４として、酸化ジルコニウム、酸化アルミニウム、酸化ジルコニウムの順番で積層された絶縁体を用いることができる。また、例えば、酸化ジルコニウム、酸化アルミニウム、酸化ジルコニウム、酸化アルミニウムの順番で積層された絶縁体を用いることができる。また、例えば、ハフニウムジルコニウム酸化物、酸化アルミニウム、ハフニウムジルコニウム酸化物、酸化アルミニウムの順番で積層された絶縁膜を用いることができる。酸化アルミニウムのような、比較的絶縁耐力が大きい絶縁体を積層して用いることで、絶縁耐力が向上し、容量素子１２の静電破壊を抑制することができる。 It is also preferable to use insulators made of the above materials in a laminated structure, and it is preferable to use a laminated structure of a high dielectric constant (high-k) material and a material having a higher dielectric strength than the high dielectric constant (high-k) material. For example, an insulator laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used as the insulator 154. Also, for example, an insulator laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. Also, for example, an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By using an insulator with a relatively high dielectric strength such as aluminum oxide in a laminated structure, the dielectric strength is improved and electrostatic breakdown of the capacitance element 12 can be suppressed.
　また、絶縁体１５４として、強誘電性を有しうる材料を用いてもよい。強誘電性を有しうる材料としては、酸化ハフニウム、酸化ジルコニウム、ＨｆＺｒＯＸ（Ｘは０よりも大きい実数とする）などの金属酸化物が挙げられる。また、強誘電性を有しうる材料としては、酸化ハフニウムに元素Ｊ１（ここでの元素Ｊ１は、ジルコニウム、シリコン、アルミニウム、ガドリニウム、イットリウム、ランタン、ストロンチウムなどから選ばれた一つまたは複数）を添加した材料が挙げられる。ここで、ハフニウム原子の原子数と元素Ｊ１の原子数の比は適宜設定することができ、例えば、ハフニウム原子の原子数と元素Ｊ１の原子数の比を１：１またはその近傍にすればよい。また、強誘電性を有しうる材料としては、酸化ジルコニウムに元素Ｊ２（ここでの元素Ｊ２は、ハフニウム、シリコン、アルミニウム、ガドリニウム、イットリウム、ランタン、ストロンチウムなどから選ばれた一つまたは複数）を添加した材料、などが挙げられる。また、ジルコニウム原子の原子数と元素Ｊ２の原子数の比は適宜設定することができ、例えば、ジルコニウム原子の原子数と元素Ｊ２の原子数の比を１：１またはその近傍にすればよい。また、強誘電性を有しうる材料として、チタン酸鉛（ＰｂＴｉＯＸ）、チタン酸バリウムストロンチウム（ＢＳＴ）、チタン酸ストロンチウム、チタン酸ジルコン酸鉛（ＰＺＴ）、タンタル酸ビスマス酸ストロンチウム（ＳＢＴ）、ビスマスフェライト（ＢＦＯ）、チタン酸バリウム、などのペロブスカイト構造を有する圧電性セラミックスを用いてもよい。 Also, a material that can have ferroelectricity may be used as the insulator 154. Examples of materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (X is a real number greater than 0). Examples of materials that can have ferroelectricity include a material in which an element J1 (here, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. Here, the ratio of the number of atoms of hafnium atoms to the number of atoms of the element J1 can be set appropriately, and for example, the ratio of the number of atoms of hafnium atoms to the number of atoms of the element J1 may be set to 1:1 or close to 1:1. Examples of materials that can have ferroelectricity include a material in which an element J2 (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. In addition, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 may be set to 1: 1 or close to 1. In addition, as a material that can have ferroelectricity, piezoelectric ceramics having a perovskite structure, such as lead titanate (PbTiO x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may be used.
　また、強誘電性を有しうる材料としては、元素Ｍ１と、元素Ｍ２と、窒素と、を有する金属窒化物が挙げられる。ここで、元素Ｍ１は、アルミニウム、ガリウム、インジウムなどから選ばれた一つまたは複数である。また、元素Ｍ２は、ホウ素、スカンジウム、イットリウム、ランタン、セリウム、ネオジム、ユーロピウム、チタン、ジルコニウム、ハフニウム、バナジウム、ニオブ、タンタル、クロムなどから選ばれた一つまたは複数である。なお、元素Ｍ１の原子数と元素Ｍ２の原子数の比は適宜設定することができる。また、元素Ｍ１と、窒素と、を有する金属酸化物は、元素Ｍ２を含まなくても、強誘電性を有する場合がある。また、強誘電性を有しうる材料としては、上記金属窒化物に元素Ｍ３が添加された材料が挙げられる。なお、元素Ｍ３は、マグネシウム、カルシウム、ストロンチウム、亜鉛、カドミウムなどから選ばれた一つまたは複数である。ここで、元素Ｍ１の原子数、元素Ｍ２の原子数、および元素Ｍ３の原子数の比は適宜設定することができる。 Also, examples of materials that can have ferroelectricity include metal nitrides having element M1, element M2, and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Also, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. It should be noted that the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Also, metal oxides having element M1 and nitrogen may have ferroelectricity even if they do not contain element M2. Also, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above metal nitride. It should be noted that element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.
　また、強誘電性を有しうる材料としては、ＳｒＴａＯ２Ｎ、ＢａＴａＯ２Ｎなどのペロブスカイト型酸窒化物、κアルミナ型構造のＧａＦｅＯ３などが挙げられる。 Furthermore, examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO 2 N and BaTaO 2 N, and GaFeO 3 with a κ-alumina structure.
　なお、上記の説明においては、金属酸化物、及び金属窒化物について例示したがこれに限定されない。例えば、上述の金属酸化物に窒素が添加された金属酸窒化物、または上述の金属窒化物に酸素が添加された金属窒酸化物などを用いてもよい。 In the above explanation, metal oxides and metal nitrides are given as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, etc. may also be used.
　また、強誘電性を有しうる材料としては、例えば、上記に列挙した材料から選ばれた複数の材料からなる混合物または化合物を用いることができる。または、絶縁体１５４を、上記に列挙した材料から選ばれた複数の材料からなる積層構造とすることができる。ところで、上記に列挙した材料などは、成膜条件だけでなく、各種プロセスなどによっても結晶構造（特性）が変わり得る可能性があるため、本明細書等では強誘電性を発現する材料のみを強誘電体と呼ぶだけでなく、強誘電性を有しうる材料とも呼んでいる。 Also, as a material that can have ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the insulator 154 can have a layered structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials that can have ferroelectricity.
　強誘電体は、絶縁体であって、外部から電場を与えることによって内部に分極が生じ、かつ当該電場をゼロにしても分極が残る性質を有する。このため、当該材料を誘電体として用いた容量素子（以下、強誘電体キャパシタと呼ぶ場合がある）を用いて、不揮発性の記憶素子を形成することができる。強誘電体キャパシタを用いた、不揮発性の記憶素子は、ＦｅＲＡＭ（Ｆｅｒｒｏｅｌｅｃｔｒｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）、強誘電体メモリなどと呼ばれることがある。例えば、強誘電体メモリは、トランジスタと、強誘電体キャパシタを有し、トランジスタのソースおよびドレインの一方が、強誘電体キャパシタの一方の端子に電気的に接続された構成を有する。よって、容量素子１２として強誘電体キャパシタを用いる場合、本実施の形態で示す記憶装置は、強誘電体メモリとして機能する。 A ferroelectric is an insulator that is polarized when an electric field is applied from the outside, and has the property that the polarization remains even when the electric field is made zero. For this reason, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element that uses a ferroelectric capacitor is sometimes called a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, etc. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance element 12, the memory device shown in this embodiment functions as a ferroelectric memory.
　絶縁体２７５、絶縁体２８０、絶縁体２８２、絶縁体２８３及び絶縁体２８５に設けられる開口の深さを深くする（つまり、絶縁体２７５、絶縁体２８０、絶縁体２８２、絶縁体２８３及び絶縁体２８５のうち一つまたは複数の厚さを厚くする）ほど、容量素子１２の静電容量を大きくすることができる。ここで、絶縁体２７５、絶縁体２８２、及び絶縁体２８３はバリア絶縁体として機能するので、半導体装置に求められるバリア性に応じて膜厚を設定することが好ましい。また、絶縁体２８０の膜厚に応じて、ゲート電極として機能する導電体２６０の膜厚が決定されるので、絶縁体２８０の膜厚は、半導体装置に求められる導電体２６０の膜厚に合わせて設定することが好ましい。 The deeper the openings in the insulators 275, 280, 282, 283, and 285 are (i.e., the thicker one or more of the insulators 275, 280, 282, 283, and 285 are), the larger the capacitance of the capacitance element 12 can be. Here, since the insulators 275, 282, and 283 function as barrier insulators, it is preferable to set the film thickness according to the barrier properties required for the semiconductor device. In addition, since the film thickness of the conductor 260 that functions as a gate electrode is determined according to the film thickness of the insulator 280, it is preferable to set the film thickness of the insulator 280 according to the film thickness of the conductor 260 required for the semiconductor device.
　よって、絶縁体２８５の膜厚を調節することで、容量素子１２の静電容量を設定することが好ましい。例えば、絶縁体２８５の膜厚を５０ｎｍ以上２５０ｎｍ以下の範囲で設定し、上記開口の深さを１５０ｎｍ以上３５０ｎｍ以下程度にすればよい。このような範囲で容量素子１２を形成することで、容量素子１２に十分な静電容量を有せしめ、且つ複数のメモリセルの層を積層する半導体装置において、一つの層の高さが過剰に高くならないようにすることができる。なお、複数のメモリセルの層のそれぞれにおいて、各メモリセルに設けられる容量素子の静電容量を異ならせる構成としてもよい。当該構成の場合、例えば、各メモリセルの層に設けられる絶縁体２８５の膜厚を異ならせればよい。 Therefore, it is preferable to set the capacitance of the capacitance element 12 by adjusting the film thickness of the insulator 285. For example, the film thickness of the insulator 285 may be set in the range of 50 nm to 250 nm, and the depth of the opening may be set to approximately 150 nm to 350 nm. By forming the capacitance element 12 in such a range, it is possible to provide the capacitance element 12 with sufficient capacitance, and to prevent the height of one layer from becoming excessively high in a semiconductor device in which multiple memory cell layers are stacked. Note that a configuration may be adopted in which the capacitance of the capacitance element provided in each memory cell is different in each of the multiple memory cell layers. In this configuration, for example, the film thickness of the insulator 285 provided in each memory cell layer may be different.
　なお、容量素子１２が配置された、絶縁体２８５等に設けられた開口部において、当該開口部の側壁は、絶縁体２２２の上面に対して垂直または概略垂直であってもよく、テーパー形状であってもよい。側壁をテーパー形状にすることで、絶縁体２８５等の開口部に設ける導電体１５３などの被覆性が向上し、鬆などの欠陥を低減できる。 In addition, in the opening provided in the insulator 285 or the like in which the capacitive element 12 is disposed, the sidewall of the opening may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may be tapered. By making the sidewall tapered, the coverage of the conductor 153 or the like provided in the opening of the insulator 285 or the like is improved, and defects such as voids can be reduced.
　また、酸化物２３０上に重畳して設けられた導電体２４２ｂは、導電体２４０ｂと電気的に接続する配線として機能する。例えば、図２６Ａでは、導電体２４２ｂの上面及び側端部が、Ｚ方向に延在する導電体２４０ｂと電気的に接続している。特に図２６Ａでは、導電体２４２ｂの上面及び側端部が、導電体２４０ｂと接している。 Furthermore, the conductor 242b provided on the oxide 230 functions as wiring that electrically connects to the conductor 240b. For example, in FIG. 26A, the upper surface and side end of the conductor 242b are electrically connected to the conductor 240b extending in the Z direction. In particular, in FIG. 26A, the upper surface and side end of the conductor 242b are in contact with the conductor 240b.
　導電体２４０ｂが直接、導電体２４２ｂの上面、及び側端部の少なくとも一と接することで、別途接続用の電極を設ける必要がないため、メモリアレイの占有面積を低減できる。また、メモリセルの集積度が向上し、記憶装置の記憶容量を増大できる。なお、導電体２４０ｂは、導電体２４２ｂの上面の一部、及び側端部と接することが好ましい。導電体２４０ｂが導電体２４２ｂの複数面と接することで、導電体２４０ｂと導電体２４２ｂの接触抵抗を低減できる。 By directly contacting the conductor 240b with at least one of the upper surface and side end of the conductor 242b, there is no need to provide a separate electrode for connection, and the area occupied by the memory array can be reduced. In addition, the integration density of memory cells is improved, and the memory capacity of the storage device can be increased. Note that it is preferable that the conductor 240b contacts a part of the upper surface and the side end of the conductor 242b. By contacting multiple surfaces of the conductor 242b with the conductor 240b, the contact resistance between the conductor 240b and the conductor 242b can be reduced.
　導電体２４０ｂは、絶縁体２１６、絶縁体２２１、絶縁体２２２、絶縁体２７５、絶縁体２８０、絶縁体２８２、絶縁体２８３、絶縁体２８５、及び、絶縁体２８４に形成された開口内に設けられている。 Conductor 240b is provided in openings formed in insulators 216, 221, 222, 275, 280, 282, 283, 285, and 284.
　また、図２６Ａに示すように、導電体２４０ｂの側面に接して絶縁体２４１ｂが設けられることが好ましい。具体的には、絶縁体２１６、絶縁体２２１、絶縁体２２２、絶縁体２７５、絶縁体２８０、絶縁体２８２、絶縁体２８３、絶縁体２８５、及び、絶縁体２８４の開口の内壁に接して絶縁体２４１ｂが設けられる。また、当該開口内に突出して形成される、酸化物２３０の側面にも絶縁体２４１が形成される。ここで、導電体２４２ｂの少なくとも一部は、絶縁体２４１ｂから露出しており、導電体２４０ｂに接している。つまり、導電体２４０ｂは、絶縁体２４１ｂを介して、上記開口の内部を埋め込むように設けられる。 Furthermore, as shown in FIG. 26A, it is preferable that the insulator 241b is provided in contact with the side surface of the conductor 240b. Specifically, the insulator 241b is provided in contact with the inner walls of the openings of the insulators 216, 221, 222, 275, 280, 282, 283, 285, and 284. The insulator 241 is also formed on the side surface of the oxide 230 that is formed to protrude into the opening. Here, at least a portion of the conductor 242b is exposed from the insulator 241b and is in contact with the conductor 240b. In other words, the conductor 240b is provided so as to fill the inside of the opening via the insulator 241b.
　なお、図２６Ａに示すように、導電体２４２ｂより下に形成される絶縁体２４１ｂの最上部は、導電体２４２ｂの上面よりも下方に位置することが好ましい。当該構成にすることで、導電体２４０ｂが導電体２４２ｂの側端部の少なくとも一部と接することができる。なお、導電体２４２ｂより下に形成される絶縁体２４１ｂは、酸化物２３０の側面と接する領域を有することが好ましい。当該構成にすることで、絶縁体２８０等に含まれる水、水素等の不純物が、導電体２４０ｂを通じて酸化物２３０に混入するのを抑制できる。 As shown in FIG. 26A, the top of the insulator 241b formed below the conductor 242b is preferably located below the top surface of the conductor 242b. This configuration allows the conductor 240b to contact at least a portion of the side end of the conductor 242b. The insulator 241b formed below the conductor 242b preferably has an area that contacts the side of the oxide 230. This configuration can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide 230 through the conductor 240b.
　なお、導電体２４０ｂ、及び絶縁体２４１ｂが配置された、開口部において、当該開口部の側壁は、絶縁体２２２の上面に対して垂直または概略垂直であってもよく、テーパー形状であってもよい。側壁をテーパー形状にすることで、当該開口部に設ける絶縁体２４１ｂなどの被覆性が向上する。 In the opening where the conductor 240b and the insulator 241b are disposed, the sidewall of the opening may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may be tapered. By making the sidewall tapered, the coverage of the insulator 241b and the like provided in the opening is improved.
　また、図２６Ａに示すメモリセル１０では、容量素子１２の導電体１５３が、トランジスタ１１の導電体２４２ａに接する構成にしたが、本発明はこれに限られるものではない。例えば、図２６Ｂに示すように、トランジスタ１１に導電体２４０ａを設け、その上に容量素子１２を設ける構成にしてもよい。 In addition, in the memory cell 10 shown in FIG. 26A, the conductor 153 of the capacitance element 12 is in contact with the conductor 242a of the transistor 11, but the present invention is not limited to this. For example, as shown in FIG. 26B, a configuration may be used in which a conductor 240a is provided in the transistor 11 and the capacitance element 12 is provided on top of that.
　図２６Ｂに示すメモリセル１０では、絶縁体２８３上に絶縁体２８６を設け、絶縁体２８６上に絶縁体２８７を設け、絶縁体２８７上に絶縁体２８８を設けることができる。絶縁体２８６、絶縁体２８７、及び絶縁体２８８は、絶縁体２８４に用いることができる絶縁体を用いればよい。また、絶縁体２８６に埋め込まれるように導電体２４６ａ及び導電体２４６ｂが設けられる。導電体２４６ａ及び導電体２４６ｂは、配線または電極として機能し、導電体２０５に用いることができる導電体を用いればよい。また、絶縁体２８７及び絶縁体２８８に埋め込まれるように、容量素子１２が設けられる。図２６Ｂに示す容量素子１２は、図２６Ａと同様の構造を有する。また、図２６Ｂに示すトランジスタ１１は、図１Ｂなどに示すトランジスタ２００と同様に、絶縁体２８０などに埋め込まれた導電体２４０ａ、導電体２４０ｂ、絶縁体２４１ａ、及び絶縁体２４１ｂを有する。 In the memory cell 10 shown in FIG. 26B, an insulator 286 can be provided on the insulator 283, an insulator 287 can be provided on the insulator 286, and an insulator 288 can be provided on the insulator 287. The insulators 286, 287, and 288 may be made of an insulator that can be used for the insulator 284. Conductors 246a and 246b are provided so as to be embedded in the insulator 286. Conductors 246a and 246b function as wirings or electrodes, and may be made of a conductor that can be used for the conductor 205. A capacitor 12 is provided so as to be embedded in the insulator 287 and the insulator 288. The capacitor 12 shown in FIG. 26B has a structure similar to that of FIG. 26A. Also, the transistor 11 shown in FIG. 26B has a conductor 240a, a conductor 240b, an insulator 241a, and an insulator 241b embedded in an insulator 280, similar to the transistor 200 shown in FIG. 1B, etc.
　図２６Ｂに示すように、導電体２４０ａは導電体２４２ａに接し、導電体２４６ａは導電体２４０ａに接し、導電体１５３は導電体２４６ａに接する。よって、容量素子１２の下部電極である導電体１５３は、導電体２４６ａ、及び導電体２４０ａを介して、トランジスタ１１のソース及びドレインの一方である導電体２４２ａに電気的に接続される。 As shown in FIG. 26B, conductor 240a contacts conductor 242a, conductor 246a contacts conductor 240a, and conductor 153 contacts conductor 246a. Therefore, conductor 153, which is the lower electrode of capacitance element 12, is electrically connected to conductor 242a, which is one of the source and drain of transistor 11, via conductor 246a and conductor 240a.
　また、図２６Ｂに示すように、導電体２４０ｂは導電体２４２ｂに接し、導電体２４６ｂは導電体２４０ｂに接する。ここで、導電体２４６ｂを同一層で引き回すことで、配線ＢＬとして機能させることができる。この場合、図２６Ｂに示すメモリセル１０は、同一層に行列状に設けられて、メモリアレイを形成する。また、これに限られることなく、図２６Ａに示す導電体２４０ｂと同様に、Ｚ方向に延伸して設ける構成にしてもよい。 Furthermore, as shown in FIG. 26B, conductor 240b contacts conductor 242b, and conductor 246b contacts conductor 240b. Here, conductor 246b can be routed in the same layer to function as wiring BL. In this case, the memory cells 10 shown in FIG. 26B are arranged in a matrix in the same layer to form a memory array. Furthermore, without being limited to this, they may be configured to extend in the Z direction, similar to conductor 240b shown in FIG. 26A.
　また、図２６Ｂに示すメモリセル１０では、導電体２４６ａと導電体２４６ｂを同一層に形成する構成にしたが、本発明はこれに限られるものではない。例えば、図２７Ａに示すように、導電体２４６ａを導電体２４６ｂより上の層に設ける構成にしてもよい。 In addition, in the memory cell 10 shown in FIG. 26B, the conductor 246a and the conductor 246b are configured to be formed in the same layer, but the present invention is not limited to this. For example, as shown in FIG. 27A, the conductor 246a may be configured to be provided in a layer above the conductor 246b.
　図２７Ａに示すメモリセル１０では、絶縁体２８６上に絶縁体２８９を設け、絶縁体２８９上に絶縁体２９０を設けることができる。絶縁体２８９は、絶縁体２８３に用いることができる絶縁体を用いればよく、絶縁体２９０は、絶縁体２８４に用いることができる絶縁体を用いればよい。また、絶縁体２９０に埋め込まれるように導電体２４６ａが設けられる。 In the memory cell 10 shown in FIG. 27A, an insulator 289 can be provided on the insulator 286, and an insulator 290 can be provided on the insulator 289. The insulator 289 can be an insulator that can be used for the insulator 283, and the insulator 290 can be an insulator that can be used for the insulator 284. In addition, a conductor 246a is provided so as to be embedded in the insulator 290.
　上記のような構成にすることで、導電体２４６ｂに干渉することなく、導電体２４６ａをトランジスタ１１上に重畳して配置することができる。よって、導電体２４６ａ上に設けられる容量素子１２を、トランジスタ１１上に重畳して配置することができる。ここで、容量素子１２の少なくとも一部、例えば、導電体１５３、絶縁体１５４、及び導電体１６０が重なる部位が、酸化物２３０、及び導電体２６０と重畳することが好ましい。このような構成にすることで、占有面積を大きく増やすことなく、トランジスタ１１及び容量素子１２を有するメモリセル１０を設けることができる。これにより、記憶装置の単位面積あたりの記憶容量を大きくすることができる。 By using the above-mentioned configuration, the conductor 246a can be arranged overlapping the transistor 11 without interfering with the conductor 246b. Therefore, the capacitor 12 provided on the conductor 246a can be arranged overlapping the transistor 11. Here, it is preferable that at least a part of the capacitor 12, for example, the part where the conductor 153, the insulator 154, and the conductor 160 overlap, overlaps with the oxide 230 and the conductor 260. By using such a configuration, a memory cell 10 having the transistor 11 and the capacitor 12 can be provided without significantly increasing the occupied area. This allows the storage capacity per unit area of the storage device to be increased.
　なお、絶縁体２８９は、導電体２４６ａを形成する際にエッチングストッパとして機能することが好ましい。このような構成にすることで、導電体２４６ａの一部が導電体２４６ｂに重畳しても、当該導電体２４６ａの一部が、導電体２４６ｂに接するのを防ぐことができる。 It is preferable that the insulator 289 functions as an etching stopper when forming the conductor 246a. With this configuration, even if a part of the conductor 246a overlaps with the conductor 246b, the part of the conductor 246a can be prevented from contacting the conductor 246b.
　また、図２６Ａに示すメモリセル１０では、容量素子１２が、トランジスタ１１上に設けられる構成にしたが、本発明はこれに限られるものではない。例えば、図２７Ｂに示すように、トランジスタ１１の下に容量素子１２が設けられる構成にしてもよい。 In addition, in the memory cell 10 shown in FIG. 26A, the capacitance element 12 is configured to be provided on the transistor 11, but the present invention is not limited to this. For example, as shown in FIG. 27B, the capacitance element 12 may be configured to be provided below the transistor 11.
　図２７Ｂに示すメモリセル１０では、絶縁体２１６の下に、図１Ｂと同様に絶縁体２１５を設け、絶縁体２１５の下に絶縁体２９１を設け、絶縁体２９１の下に絶縁体２９２を設け、絶縁体２９２の下に絶縁体２９３を設けることができる。絶縁体２９１、絶縁体２９２、及び絶縁体２９３は、絶縁体２８４に用いることができる絶縁体を用いればよい。また、絶縁体２９３に埋め込まれるように導電体２９４が設けられる。導電体２９４は、配線または電極として機能し、導電体２０５に用いることができる導電体を用いればよい。また、絶縁体２９１及び絶縁体２９２に埋め込まれるように、容量素子１２が設けられる。図２７Ｂに示す容量素子１２は、図２６Ａと同様の構造を有する。また、絶縁体２１５及び絶縁体２１６に埋め込まれるように導電体２０６が設けられる。導電体２０６は、デュアルダマシン法を用いることで、導電体２０５と同じ工程で形成することができる。また、絶縁体２２１、絶縁体２２２、絶縁体２７５、絶縁体２８０、絶縁体２８２、及び絶縁体２８３に埋め込まれるように、導電体２４０ｃ、及び絶縁体２４１ｃが設けられる。導電体２４０ｃは、導電体２４０ａ及び導電体２４０ｂと同じ工程で形成することができ、絶縁体２４１ｃは、絶縁体２４１ａ及び絶縁体２４１ｂと同じ工程で形成することができる。 In the memory cell 10 shown in FIG. 27B, an insulator 215 can be provided under the insulator 216 as in FIG. 1B, an insulator 291 can be provided under the insulator 215, an insulator 292 can be provided under the insulator 291, and an insulator 293 can be provided under the insulator 292. The insulators 291, 292, and 293 may be made of an insulator that can be used for the insulator 284. A conductor 294 is provided so as to be embedded in the insulator 293. The conductor 294 may be made of a conductor that functions as a wiring or an electrode and can be used for the conductor 205. A capacitor 12 is provided so as to be embedded in the insulators 291 and 292. The capacitor 12 shown in FIG. 27B has a structure similar to that of FIG. 26A. A conductor 206 is provided so as to be embedded in the insulators 215 and 216. The conductor 206 can be formed in the same process as the conductor 205 by using a dual damascene method. Conductor 240c and insulator 241c are provided so as to be embedded in insulator 221, insulator 222, insulator 275, insulator 280, insulator 282, and insulator 283. Conductor 240c can be formed in the same process as conductor 240a and conductor 240b, and insulator 241c can be formed in the same process as insulator 241a and insulator 241b.
　図２７Ｂに示すように、導電体２４０ａは導電体２４２ａに接し、導電体２４６ａは導電体２４０ａに接し、導電体２４０ｃは導電体２４６ａに接し、導電体２０６は導電体２４０ｃに接し、導電体１６０は導電体２０６に接する。よって、容量素子１２の上部電極である導電体１６０は、導電体２０６、導電体２４０ｃ、導電体２４６ａ、及び導電体２４０ａを介して、トランジスタ１１のソース及びドレインの一方である導電体２４２ａに電気的に接続される。 As shown in FIG. 27B, conductor 240a contacts conductor 242a, conductor 246a contacts conductor 240a, conductor 240c contacts conductor 246a, conductor 206 contacts conductor 240c, and conductor 160 contacts conductor 206. Thus, conductor 160, which is the upper electrode of capacitance element 12, is electrically connected to conductor 242a, which is one of the source and drain of transistor 11, via conductor 206, conductor 240c, conductor 246a, and conductor 240a.
　また、図２７Ｂに示すように、導電体２９４は導電体１５３に接する。ここで、導電体１５３は、配線ＰＬとして機能させることができる。 Furthermore, as shown in FIG. 27B, the conductor 294 contacts the conductor 153. Here, the conductor 153 can function as the wiring PL.
　上記のような構成にすることで、容量素子１２を、トランジスタ１１の下に重畳して配置することができる。ここで、容量素子１２の少なくとも一部、例えば、導電体１５３、絶縁体１５４、及び導電体１６０が重なる部位が、酸化物２３０、及び導電体２６０と重畳することが好ましい。このような構成にすることで、占有面積を大きく増やすことなく、トランジスタ１１及び容量素子１２を有するメモリセル１０を設けることができる。これにより、記憶装置の単位面積あたりの記憶容量を大きくすることができる。 By using the above-mentioned configuration, the capacitor 12 can be arranged overlapping under the transistor 11. Here, it is preferable that at least a portion of the capacitor 12, for example, the portion where the conductor 153, the insulator 154, and the conductor 160 overlap, overlaps with the oxide 230 and the conductor 260. By using such a configuration, it is possible to provide a memory cell 10 having the transistor 11 and the capacitor 12 without significantly increasing the occupied area. This allows the storage capacity per unit area of the storage device to be increased.
＜記憶装置３００の構成例＞
　図２８を用いて、上記記憶装置３００の構成例について説明する。 <Configuration example of storage device 300>
An example of the configuration of the storage device 300 will be described with reference to FIG.
　記憶装置３００は、トランジスタ３１０等を有する層である、駆動回路２１と、駆動回路２１上の、トランジスタ５２、５３、５４、５５等を有する層である、機能層５０と、機能層５０上のメモリアレイ２０［１］乃至２０［ｍ］と、を有する。なお、トランジスタ５２は、上記トランジスタ５２＿ａ、５２＿ｂに対応し、トランジスタ５３は、上記トランジスタ５３＿ａ、５３＿ｂに対応し、トランジスタ５４は、上記トランジスタ５４＿ａ、５４＿ｂに対応し、トランジスタ５５は、上記トランジスタ５５＿ａ、５５＿ｂに対応する。 The memory device 300 has a driver circuit 21, which is a layer having transistors 310 and the like, a functional layer 50 on the driver circuit 21, which is a layer having transistors 52, 53, 54, 55 and the like, and memory arrays 20[1] to 20[m] on the functional layer 50. Note that the transistor 52 corresponds to the transistors 52_a and 52_b described above, the transistor 53 corresponds to the transistors 53_a and 53_b described above, the transistor 54 corresponds to the transistors 54_a and 54_b described above, and the transistor 55 corresponds to the transistors 55_a and 55_b described above.
　図２８では、駆動回路２１が有するトランジスタ３１０を例示している。トランジスタ３１０は、基板３１１上に設けられ、ゲートとして機能する導電体３１６、ゲート絶縁体として機能する絶縁体３１５、基板３１１の一部を含む半導体領域３１３、及びソース領域またはドレイン領域として機能する低抵抗領域３１４ａ、及び低抵抗領域３１４ｂを有する。トランジスタ３１０は、ｐチャネル型のトランジスタ、あるいはｎチャネル型のトランジスタのいずれでもよい。基板３１１としては、例えば単結晶シリコン基板を用いることができる。 In FIG. 28, a transistor 310 included in the driver circuit 21 is illustrated. The transistor 310 is provided on a substrate 311, and has a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 including a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. The transistor 310 may be either a p-channel transistor or an n-channel transistor. For example, a single crystal silicon substrate can be used as the substrate 311.
　ここで、図２８に示すトランジスタ３１０はチャネルが形成される半導体領域３１３（基板３１１の一部）が凸形状を有する。また、半導体領域３１３の側面及び上面を、絶縁体３１５を介して、導電体３１６が覆うように設けられている。なお、導電体３１６は仕事関数を調整する材料を用いてもよい。このようなトランジスタ３１０は半導体基板の凸部を利用していることからＦｉｎ型トランジスタとも呼ばれる。なお、凸部の上部に接して、凸部を形成するためのマスクとして機能する絶縁体を有していてもよい。また、ここでは半導体基板の一部を加工して凸部を形成する場合を示したが、ＳＯＩ（Ｓｉｌｉｃｏｎ　ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板を加工して凸形状を有する半導体膜を形成してもよい。 Here, in the transistor 310 shown in FIG. 28, the semiconductor region 313 (part of the substrate 311) in which the channel is formed has a convex shape. Also, the side and top surface of the semiconductor region 313 are covered with a conductor 316 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a Fin-type transistor because it uses the convex portion of the semiconductor substrate. Note that an insulator that contacts the top of the convex portion and functions as a mask for forming the convex portion may be provided. Also, here, a case where a convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may be formed by processing an SOI (Silicon on Insulator) substrate.
　なお、図２８に示すトランジスタ３１０は一例であり、その構造に限定されず、回路構成または駆動方法に応じて適切なトランジスタを用いることができる。 Note that the transistor 310 shown in FIG. 28 is just an example, and the structure is not limited to this, and an appropriate transistor can be used depending on the circuit configuration or driving method.
　各構造体の間には、層間膜、配線、及びプラグ等が設けられた配線層が設けられていてもよい。また、配線層は、設計に応じて複数層設けることができる。また、本明細書等において、配線と、配線と電気的に接続するプラグとが一体物であってもよい。すなわち、導電体の一部が配線として機能する場合、及び導電体の一部がプラグとして機能する場合もある。 A wiring layer having an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers may be provided depending on the design. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.
　例えば、トランジスタ３１０上には、層間膜として、絶縁体３２０、絶縁体３２２、絶縁体３２４、及び絶縁体３２６が順に積層して設けられている。また、絶縁体３２０及び絶縁体３２２には導電体３２８などが埋め込まれている。また、絶縁体３２４及び絶縁体３２６には導電体３３０などが埋め込まれている。なお、導電体３２８及び導電体３３０はコンタクトプラグまたは配線として機能する。 For example, on the transistor 310, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film. Conductors 328 and the like are embedded in the insulators 320 and 322. Conductors 330 and the like are embedded in the insulators 324 and 326. Conductors 328 and 330 function as contact plugs or wiring.
　また、層間膜として機能する絶縁体は、その下方の凹凸形状を被覆する平坦化膜として機能してもよい。例えば、絶縁体３２２の上面は、平坦性を高めるために化学機械研磨（ＣＭＰ：Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）法等を用いた平坦化処理により平坦化されていてもよい。 The insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.
　また、図２８では、機能層５０が有するトランジスタ５２、５３、５５を例示している。トランジスタ５２、５３、５５は、メモリセル１０が有するトランジスタ１１と同様の構成を有する。トランジスタ５２、５３、５５は、互いのソース及びドレインが直列に接続されている。 FIG. 28 also illustrates transistors 52, 53, and 55 in the functional layer 50. The transistors 52, 53, and 55 have the same configuration as the transistor 11 in the memory cell 10. The sources and drains of the transistors 52, 53, and 55 are connected in series.
　トランジスタ５２、５３、５５上に、絶縁体２０８が設けられ、絶縁体２０８に形成された開口に導電体２０７が設けられる。さらに、絶縁体２０８上に絶縁体２１０が設けられ、絶縁体２１０に形成された開口に導電体２０９が設けられる。さらに、絶縁体２１０上に絶縁体２１２が設けられ、絶縁体２１２上に絶縁体２１４が設けられる。絶縁体２１２及び絶縁体２１４に形成された開口には、メモリアレイ２０［１］に設けられた導電体２４０ｂの一部が埋め込まれている。ここで、絶縁体２０８、及び絶縁体２１０は、絶縁体２１６に用いることが可能な絶縁体を用いることができる。また、絶縁体２１２は、絶縁体２８３に用いることが可能な絶縁体を用いることができる。また、絶縁体２１４は、絶縁体２８２に用いることが可能な絶縁体を用いることができる。 An insulator 208 is provided on the transistors 52, 53, and 55, and a conductor 207 is provided in an opening formed in the insulator 208. Furthermore, an insulator 210 is provided on the insulator 208, and a conductor 209 is provided in an opening formed in the insulator 210. Furthermore, an insulator 212 is provided on the insulator 210, and an insulator 214 is provided on the insulator 212. A part of the conductor 240b provided in the memory array 20[1] is embedded in the openings formed in the insulators 212 and 214. Here, the insulators 208 and 210 can be made of an insulator that can be used for the insulator 216. Furthermore, the insulator 212 can be made of an insulator that can be used for the insulator 283. Furthermore, the insulator 214 can be made of an insulator that can be used for the insulator 282.
　導電体２０７の下面は、トランジスタ５２の導電体２６０の上面に接して設けられる。また、導電体２０７の上面は、導電体２０９の下面に接して設けられる。また、導電体２０９の上面は、メモリアレイ２０［１］に設けられた導電体２４０ｂの下面に接して設けられる。このような構成にすることで、配線ＢＬに相当する導電体２４０ｂと、トランジスタ５２のゲートを電気的に接続することができる。 The bottom surface of conductor 207 is in contact with the top surface of conductor 260 of transistor 52. The top surface of conductor 207 is in contact with the bottom surface of conductor 209. The top surface of conductor 209 is in contact with the bottom surface of conductor 240b provided in memory array 20[1]. With this configuration, conductor 240b, which corresponds to wiring BL, can be electrically connected to the gate of transistor 52.
　メモリアレイ２０［１］乃至２０［ｍ］は、それぞれ、複数のメモリセル１０を含む。各メモリセル１０が有する導電体２４０ｂは、上の層の導電体２４０ｂ、及び下の層の導電体２４０ｂと電気的に接続される。 Memory arrays 20[1] to 20[m] each include a plurality of memory cells 10. The conductor 240b of each memory cell 10 is electrically connected to the conductor 240b in the upper layer and the conductor 240b in the lower layer.
　図２８に示すように、隣接するメモリセル１０において、導電体２４０ｂが共有されている。また、隣接するメモリセル１０において、導電体２４０ｂを境に、右側の構成と左側の構成と、が対称に配置される。 As shown in FIG. 28, the conductor 240b is shared between adjacent memory cells 10. In addition, in adjacent memory cells 10, the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductor 240b.
　ここで、下の層（例えばメモリアレイ２０［１］の層）の容量素子１２の上部電極として機能する導電体１６０と、上の層（例えば、メモリアレイ２０［２］の層）のトランジスタ１１の第２のゲート電極として機能する導電体２０５は、同じ層に形成することができる。言い換えると、下の層の容量素子１２の導電体１６０と、上の層のトランジスタ１１の導電体２０５は、同一の絶縁体２１６に形成された開口に埋め込まれるように形成することができる。さらに、上の層のトランジスタ１１の導電体２０５を、下の層の容量素子１２の導電体１６０に用いる導電膜を加工して形成することもできる。このとき、上の層のトランジスタ１１の導電体２０５は、下の層の容量素子１２の導電体１６０と同一の材料を有する。 Here, the conductor 160 functioning as the upper electrode of the capacitance element 12 in the lower layer (e.g., the layer of the memory array 20[1]) and the conductor 205 functioning as the second gate electrode of the transistor 11 in the upper layer (e.g., the layer of the memory array 20[2]) can be formed in the same layer. In other words, the conductor 160 of the capacitance element 12 in the lower layer and the conductor 205 of the transistor 11 in the upper layer can be formed so as to be embedded in an opening formed in the same insulator 216. Furthermore, the conductor 205 of the transistor 11 in the upper layer can also be formed by processing the conductive film used for the conductor 160 of the capacitance element 12 in the lower layer. In this case, the conductor 205 of the transistor 11 in the upper layer has the same material as the conductor 160 of the capacitance element 12 in the lower layer.
　以上のように、下の層の容量素子１２の導電体１６０と、上の層のトランジスタ１１の導電体２０５を同時に形成することで、本実施の形態に係る記憶装置の作製工程を削減し、当該記憶装置の生産性を向上することができる。 As described above, by simultaneously forming the conductor 160 of the capacitive element 12 in the lower layer and the conductor 205 of the transistor 11 in the upper layer, it is possible to reduce the manufacturing process of the memory device according to this embodiment and improve the productivity of the memory device.
　上述のメモリアレイ２０では、複数のメモリアレイ２０［１］乃至２０［ｍ］を積層して設けることができる。メモリアレイ２０が有するメモリアレイ２０［１］乃至２０［ｍ］は、駆動回路２１が設けられる基板表面の垂直方向に配置することで、メモリセル１０のメモリ密度の向上を図ることができる。またメモリアレイ２０は、垂直方向に繰り返し同じ製造工程を用いて作製することができる。記憶装置３００は、メモリアレイ２０の製造コストの低減を図ることができる。 In the memory array 20 described above, multiple memory arrays 20[1] to 20[m] can be stacked. The memory arrays 20[1] to 20[m] of the memory array 20 can be arranged in the vertical direction of the substrate surface on which the drive circuit 21 is provided, thereby improving the memory density of the memory cells 10. The memory array 20 can also be manufactured using the same manufacturing process repeatedly in the vertical direction. The storage device 300 can reduce the manufacturing cost of the memory array 20.
　本実施の形態は、他の実施の形態と適宜組み合わせることができる。 This embodiment can be combined with other embodiments as appropriate.
（実施の形態４）
　本実施の形態では、本発明の一態様の記憶装置が実装されたチップの一例について、図２９を用いて説明する。 (Embodiment 4)
In this embodiment, an example of a chip on which a memory device of one embodiment of the present invention is mounted will be described with reference to FIGS.
　図２９Ａ及び図２９Ｂに示すチップ１２００には、複数の回路（システム）が実装されている。このように、複数の回路（システム）を一つのチップに集積する技術を、システムオンチップ（Ｓｙｓｔｅｍ　ｏｎ　Ｃｈｉｐ：ＳｏＣ）と呼ぶ場合がある。 The chip 1200 shown in Figures 29A and 29B has multiple circuits (systems) implemented on it. This technology of integrating multiple circuits (systems) on a single chip is sometimes called a system on chip (SoC).
　図２９Ａに示すように、チップ１２００は、ＣＰＵ１２１１、ＧＰＵ１２１２、一または複数のアナログ演算部１２１３、一または複数のメモリコントローラ１２１４、一または複数のインターフェース１２１５、一または複数のネットワーク回路１２１６等を有する。 As shown in FIG. 29A, the chip 1200 has a CPU 1211, a GPU 1212, one or more analog computing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.
　チップ１２００には、バンプ（図示しない）が設けられ、図２９Ｂに示すように、パッケージ基板１２０１の第１の面と接続する。また、パッケージ基板１２０１の第１の面の裏面には、複数のバンプ１２０２が設けられており、マザーボード１２０３と接続する。 Bumps (not shown) are provided on the chip 1200, and as shown in FIG. 29B, they are connected to the first surface of the package substrate 1201. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201, and they are connected to the motherboard 1203.
　マザーボード１２０３には、ＤＲＡＭ１２２１、フラッシュメモリ１２２２等の記憶装置が設けられていてもよい。例えば、ＤＲＡＭ１２２１に先の実施の形態に示すＤＯＳＲＡＭを用いることができる。これにより、ＤＲＡＭ１２２１を、低消費電力化、高速化、及び大容量化させることができる。 The motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222. For example, the DOSRAM described in the previous embodiment may be used for the DRAM 1221. This allows the DRAM 1221 to consume less power, operate at a higher speed, and have a larger capacity.
　ＣＰＵ１２１１は、複数のＣＰＵコアを有することが好ましい。また、ＧＰＵ１２１２は、複数のＧＰＵコアを有することが好ましい。また、ＣＰＵ１２１１、及びＧＰＵ１２１２は、それぞれ一時的にデータを格納するメモリを有していてもよい。または、ＣＰＵ１２１１、及びＧＰＵ１２１２に共通のメモリが、チップ１２００に設けられていてもよい。該メモリには、前述したＤＯＳＲＡＭを用いることができる。また、ＧＰＵ１２１２は、多数のデータの並列計算に適しており、画像処理または積和演算に用いることができる。ＧＰＵ１２１２に、先の実施の形態に記載のＯＳトランジスタを用いた画像処理回路、または、積和演算回路を設けることで、画像処理、または積和演算を低消費電力で実行することが可能になる。 The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The memory may be the DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data, and may be used for image processing or multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the OS transistor described in the previous embodiment, it becomes possible to perform image processing or multiply-and-accumulate operations with low power consumption.
　また、ＣＰＵ１２１１、及びＧＰＵ１２１２が同一チップに設けられていることで、ＣＰＵ１２１１、及びＧＰＵ１２１２間の配線を短くすることができ、ＣＰＵ１２１１からＧＰＵ１２１２へのデータ転送、ＣＰＵ１２１１、及びＧＰＵ１２１２が有するメモリ間のデータ転送、及びＧＰＵ１２１２での演算後に、ＧＰＵ１２１２からＣＰＵ１２１１への演算結果の転送を高速に行うことができる。 In addition, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data can be transferred from the CPU 1211 to the GPU 1212, data can be transferred between the memories of the CPU 1211 and GPU 1212, and the results of calculations performed by the GPU 1212 can be transferred from the GPU 1212 to the CPU 1211 at high speed.
　アナログ演算部１２１３はＡ／Ｄ（アナログ／デジタル）変換回路、及びＤ／Ａ（デジタル／アナログ）変換回路の一、または両方を有する。また、アナログ演算部１２１３に上記積和演算回路を設けてもよい。 The analog calculation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.
　メモリコントローラ１２１４は、ＤＲＡＭ１２２１のコントローラとして機能する回路、及びフラッシュメモリ１２２２のインターフェースとして機能する回路を有する。 The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.
　インターフェース１２１５は、表示装置、スピーカー、マイクロフォン、カメラ、コントローラなどの外部接続機器とのインターフェース回路を有する。コントローラとは、マウス、キーボード、ゲーム用コントローラなどを含む。このようなインターフェースとして、ＵＳＢ（Ｕｎｉｖｅｒｓａｌ　Ｓｅｒｉａｌ　Ｂｕｓ）、ＨＤＭＩ（登録商標）（Ｈｉｇｈ−Ｄｅｆｉｎｉｔｉｏｎ　Ｍｕｌｔｉｍｅｄｉａ　Ｉｎｔｅｒｆａｃｅ）などを用いることができる。 The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include mice, keyboards, and game controllers. Examples of such interfaces that can be used include USB (Universal Serial Bus) and HDMI (registered trademark) (High-Definition Multimedia Interface).
　ネットワーク回路１２１６は、ＬＡＮ（Ｌｏｃａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）などのネットワークと接続するための回路を有する。また、ネットワークセキュリティー用の回路を有してもよい。 The network circuit 1216 has a circuit for connecting to a network such as a LAN (Local Area Network). It may also have a circuit for network security.
　チップ１２００には、上記回路（システム）を同一の製造プロセスで形成することが可能である。そのため、チップ１２００に必要な回路の数が増えても、製造プロセスを増やす必要が無く、チップ１２００を低コストで作製することができる。 The above circuits (systems) can be formed in chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, there is no need to increase the manufacturing process, and chip 1200 can be manufactured at low cost.
　ＧＰＵ１２１２を有するチップ１２００が設けられたパッケージ基板１２０１、ＤＲＡＭ１２２１、及びフラッシュメモリ１２２２が設けられたマザーボード１２０３は、ＧＰＵモジュール１２０４と呼ぶことができる。 The package substrate 1201 on which the chip 1200 having the GPU 1212 is provided, the motherboard 1203 on which the DRAM 1221 and the flash memory 1222 are provided, can be called a GPU module 1204.
　ＧＰＵモジュール１２０４は、ＳｏＣ技術を用いたチップ１２００を有しているため、そのサイズを小さくすることができる。また、画像処理に優れていることから、スマートフォン、タブレット端末、ラップトップＰＣ、携帯型（持ち出し可能な）ゲーム機などの携帯型電子機器に用いることが好適である。また、ＧＰＵ１２１２を用いた積和演算回路により、ディープニューラルネットワーク（ＤＮＮ）、畳み込みニューラルネットワーク（ＣＮＮ）、再帰型ニューラルネットワーク（ＲＮＮ）、自己符号化器、深層ボルツマンマシン（ＤＢＭ）、深層信念ネットワーク（ＤＢＮ）などの手法を実行できるため、チップ１２００をＡＩチップ、またはＧＰＵモジュール１２０４をＡＩシステムモジュールとして用いることができる。 The GPU module 1204 has the chip 1200 using SoC technology, so its size can be reduced. In addition, because it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles. In addition, the product-sum calculation circuit using the GPU 1212 can execute techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), so the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.
　本実施の形態は、他の実施の形態と適宜組み合わせることができる。 This embodiment can be combined with other embodiments as appropriate.
（実施の形態５）
　本実施の形態では、上記実施の形態で説明した半導体装置を用いることができる、電子部品、電子機器、大型計算機、宇宙用機器、およびデータセンター（Ｄａｔａ　Ｃｅｎｔｅｒ：ＤＣとも呼称する）について説明する。本発明の一態様の半導体装置を用いた、電子部品、電子機器、大型計算機、宇宙用機器、およびデータセンターは、低消費電力化といった高性能化に有効である。 (Embodiment 5)
In this embodiment, electronic components, electronic devices, large scale computers, space equipment, and data centers (also referred to as data centers (DCs)) in which the semiconductor device described in the above embodiment can be used will be described. The electronic components, electronic devices, large scale computers, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.
［電子部品］
　電子部品７００が実装された基板（実装基板７０４）の斜視図を、図３０Ａに示す。図３０Ａに示す電子部品７００は、モールド７１１内に半導体装置７１０を有している。図３０Ａは、電子部品７００の内部を示すために、一部の記載を省略している。電子部品７００は、モールド７１１の外側にランド７１２を有する。ランド７１２は電極パッド７１３と電気的に接続され、電極パッド７１３は半導体装置７１０とワイヤ７１４を介して電気的に接続されている。電子部品７００は、例えばプリント基板７０２に実装される。このような電子部品が複数組み合わされて、それぞれがプリント基板７０２上で電気的に接続されることで実装基板７０４が完成する。 [Electronic Components]
FIG. 30A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 700 is mounted. The electronic component 700 shown in FIG. 30A has a semiconductor device 710 in a mold 711. In FIG. 30A, some parts are omitted in order to show the inside of the electronic component 700. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
　また、半導体装置７１０は、駆動回路層７１５と、記憶層７１６と、を有する。なお、記憶層７１６は、複数のメモリセルアレイが積層された構成である。駆動回路層７１５と、記憶層７１６と、が積層された構成は、モノリシック積層の構成とすることができる。モノリシック積層の構成では、ＴＳＶ（Ｔｈｒｏｕｇｈ　Ｓｉｌｉｃｏｎ　Ｖｉａ）などの貫通電極技術、および、Ｃｕ−Ｃｕ直接接合などの接合技術、を用いることなく、各層間を接続することができる。駆動回路層７１５と、記憶層７１６と、をモノリシック積層の構成とすることで、例えば、プロセッサ上にメモリが直接形成される、いわゆるオンチップメモリの構成とすることができる。オンチップメモリの構成とすることで、プロセッサと、メモリとのインターフェース部分の動作を高速にすることが可能となる。 The semiconductor device 710 also has a drive circuit layer 715 and a memory layer 716. The memory layer 716 is configured by stacking a plurality of memory cell arrays. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) and bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stack, for example, a so-called on-chip memory configuration in which the memory is formed directly on the processor can be formed. By configuring the on-chip memory, it is possible to increase the speed of the operation of the interface between the processor and the memory.
　また、オンチップメモリの構成とすることで、ＴＳＶなどの貫通電極を用いる技術と比較し、接続配線などのサイズを小さくすることが可能であるため、接続ピン数を増加させることも可能となる。接続ピン数を増加させることで、並列動作が可能となるため、メモリのバンド幅（メモリバンド幅ともいう）を向上させることが可能となる。 In addition, by configuring the memory as an on-chip memory, it is possible to reduce the size of the connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).
　また、記憶層７１６が有する、複数のメモリセルアレイを、ＯＳトランジスタを用いて形成し、当該複数のメモリセルアレイをモノリシックで積層することが好ましい。複数のメモリセルアレイをモノリシック積層の構成とすることで、メモリのバンド幅、及びメモリのアクセスレイテンシのいずれか一または双方を向上させることができる。なお、バンド幅とは、単位時間あたりのデータ転送量であり、アクセスレイテンシとは、アクセスしてからデータのやり取りが始まるまでの時間である。なお、記憶層７１６にＳｉトランジスタを用いる構成の場合、ＯＳトランジスタと比較し、モノリシック積層の構成とすることが困難である。そのため、モノリシック積層の構成において、ＯＳトランジスタは、Ｓｉトランジスタよりも優れた構造であるといえる。 Furthermore, it is preferable that the multiple memory cell arrays in the memory layer 716 are formed using OS transistors and the multiple memory cell arrays are monolithically stacked. By configuring the multiple memory cell arrays as monolithic stacks, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is difficult to configure the memory layer 716 as a monolithic stack compared to OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in the monolithic stack configuration.
　また、半導体装置７１０を、ダイと呼称してもよい。なお、本明細書等において、ダイとは、半導体チップの製造工程で、例えば円盤状の基板（ウエハともいう）などに回路パターンを形成し、さいの目状に切り分けて得られたチップ片を表す。なお、ダイに用いることのできる半導体材料として、例えば、シリコン（Ｓｉ）、炭化ケイ素（ＳｉＣ）、または窒化ガリウム（ＧａＮ）などが挙げられる。例えば、シリコン基板（シリコンウエハともいう）から得られたダイを、シリコンダイという場合がある。 The semiconductor device 710 may also be referred to as a die. In this specification and the like, a die refers to a chip piece obtained during the manufacturing process of a semiconductor chip by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.
　次に、電子部品７３０の斜視図を図３０Ｂに示す。電子部品７３０は、ＳｉＰ（Ｓｙｓｔｅｍ　ｉｎ　Ｐａｃｋａｇｅ）又はＭＣＭ（Ｍｕｌｔｉ　Ｃｈｉｐ　Ｍｏｄｕｌｅ）の一例である。電子部品７３０は、パッケージ基板７３２（プリント基板）上にインターポーザ７３１が設けられ、インターポーザ７３１上に半導体装置７３５、及び複数の半導体装置７１０が設けられている。 Next, a perspective view of electronic component 730 is shown in FIG. 30B. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.
　電子部品７３０では、半導体装置７１０を広帯域メモリ（ＨＢＭ：Ｈｉｇｈ　Ｂａｎｄｗｉｄｔｈ　Ｍｅｍｏｒｙ）として用いる例を示している。また、半導体装置７３５は、ＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）、ＧＰＵ（Ｇｒａｐｈｉｃｓ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）、又はＦＰＧＡ（Ｆｉｅｌｄ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｇａｔｅ　Ａｒｒａｙ）等の集積回路に用いることができる。 In electronic component 730, an example is shown in which semiconductor device 710 is used as a high bandwidth memory (HBM). In addition, semiconductor device 735 can be used in integrated circuits such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).
　パッケージ基板７３２は、例えば、セラミックス基板、プラスチック基板、又は、ガラスエポキシ基板を用いることができる。インターポーザ７３１は、例えば、シリコンインターポーザ、又は樹脂インターポーザを用いることができる。 The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.
　インターポーザ７３１は、複数の配線を有し、端子ピッチの異なる複数の集積回路を電気的に接続する機能を有する。複数の配線は、単層又は多層で設けられる。また、インターポーザ７３１は、インターポーザ７３１上に設けられた集積回路をパッケージ基板７３２に設けられた電極と電気的に接続する機能を有する。これらのことから、インターポーザを「再配線基板」又は「中間基板」と呼ぶ場合がある。また、インターポーザ７３１に貫通電極を設けて、当該貫通電極を用いて集積回路とパッケージ基板７３２を電気的に接続する場合もある。また、シリコンインターポーザでは、貫通電極として、ＴＳＶを用いることもできる。 The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, a through electrode is provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrode. In addition, in a silicon interposer, a TSV can also be used as the through electrode.
　ＨＢＭでは、広いメモリバンド幅を実現するために多くの配線を接続する必要がある。このため、ＨＢＭを実装するインターポーザには、微細かつ高密度の配線形成が求められる。よって、ＨＢＭを実装するインターポーザには、シリコンインターポーザを用いることが好ましい。 In an HBM, many wiring connections are required to achieve a wide memory bandwidth. For this reason, the interposer that implements the HBM requires fine, high-density wiring. For this reason, it is preferable to use a silicon interposer for the interposer that implements the HBM.
　また、シリコンインターポーザを用いた、ＳｉＰ及びＭＣＭ等では、集積回路とインターポーザ間の膨張係数の違いによる信頼性の低下が生じにくい。また、シリコンインターポーザは表面の平坦性が高いため、シリコンインターポーザ上に設ける集積回路とシリコンインターポーザ間の接続不良が生じにくい。特に、インターポーザ上に複数の集積回路を横に並べて配置する２．５Ｄパッケージ（２．５次元実装）では、シリコンインターポーザを用いることが好ましい。 Furthermore, in SiP and MCM using silicon interposers, deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.
　一方で、シリコンインターポーザ、及びＴＳＶなどを用いて端子ピッチの異なる複数の集積回路を電気的に接続する場合、当該端子ピッチの幅などのスペースが必要となる。そのため、電子部品７３０のサイズを小さくしようとした場合、上記の端子ピッチの幅が問題になり、広いメモリバンド幅を実現するために必要な多くの配線を設けることが、困難になる場合がある。そこで、上述したように、ＯＳトランジスタを用いたモノリシック積層の構成が好適である。ＴＳＶを用いて積層したメモリセルアレイと、モノリシック積層したメモリセルアレイと、を組み合わせた複合化構造としてもよい。 On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSV, or the like, space is required for the width of the terminal pitch. Therefore, when trying to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacking configuration using OS transistors is preferable. A composite structure may be used that combines a memory cell array stacked using TSVs and a monolithic stacking memory cell array.
　また、電子部品７３０と重ねてヒートシンク（放熱板）を設けてもよい。ヒートシンクを設ける場合は、インターポーザ７３１上に設ける集積回路の高さを揃えることが好ましい。例えば、本実施の形態に示す電子部品７３０では、半導体装置７１０と半導体装置７３５の高さを揃えることが好ましい。 A heat sink (heat sink) may be provided overlapping the electronic component 730. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the semiconductor device 735.
　電子部品７３０を他の基板に実装するため、パッケージ基板７３２の底部に電極７３３を設けてもよい。図３０Ｂでは、電極７３３を半田ボールで形成する例を示している。パッケージ基板７３２の底部に半田ボールをマトリクス状に設けることで、ＢＧＡ（Ｂａｌｌ　Ｇｒｉｄ　Ａｒｒａｙ）実装を実現できる。また、電極７３３を導電性のピンで形成してもよい。パッケージ基板７３２の底部に導電性のピンをマトリクス状に設けることで、ＰＧＡ（Ｐｉｎ　Ｇｒｉｄ　Ａｒｒａｙ）実装を実現できる。 In order to mount the electronic component 730 on another substrate, electrodes 733 may be provided on the bottom of the package substrate 732. FIG. 30B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. The electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.
　電子部品７３０は、ＢＧＡ及びＰＧＡに限らず様々な実装方法を用いて他の基板に実装することができる。実装方法としては、例えば、ＳＰＧＡ（Ｓｔａｇｇｅｒｅｄ　Ｐｉｎ　Ｇｒｉｄ　Ａｒｒａｙ）、ＬＧＡ（Ｌａｎｄ　Ｇｒｉｄ　Ａｒｒａｙ）、ＱＦＰ（Ｑｕａｄ　Ｆｌａｔ　Ｐａｃｋａｇｅ）、ＱＦＪ（Ｑｕａｄ　Ｆｌａｔ　Ｊ−ｌｅａｄｅｄ　ｐａｃｋａｇｅ）、及び、ＱＦＮ（Ｑｕａｄ　Ｆｌａｔ　Ｎｏｎ−ｌｅａｄｅｄ　ｐａｃｋａｇｅ）が挙げられる。 The electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).
［電子機器］
　次に、電子機器６５００の斜視図を図３１Ａに示す。図３１Ａに示す電子機器６５００は、スマートフォンとして用いることのできる携帯情報端末機である。電子機器６５００は、筐体６５０１、表示部６５０２、電源ボタン６５０３、ボタン６５０４、スピーカ６５０５、マイク６５０６、カメラ６５０７、光源６５０８、及び制御装置６５０９などを有する。なお、制御装置６５０９としては、例えば、ＣＰＵ、ＧＰＵ、及び記憶装置の中から選ばれるいずれか一または複数を有する。本発明の一態様の半導体装置は、表示部６５０２、制御装置６５０９などに適用することができる。 [Electronics]
Next, a perspective view of an electronic device 6500 is shown in FIG. 31A. The electronic device 6500 shown in FIG. 31A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.
　図３１Ｂに示す電子機器６６００は、ノート型パーソナルコンピュータとして用いることのできる情報端末機である。電子機器６６００は、筐体６６１１、キーボード６６１２、ポインティングデバイス６６１３、外部接続ポート６６１４、表示部６６１５、制御装置６６１６などを有する。なお、制御装置６６１６としては、例えば、ＣＰＵ、ＧＰＵ、及び記憶装置の中から選ばれるいずれか一または複数を有する。本発明の一態様の半導体装置は、表示部６６１５、制御装置６６１６などに適用することができる。なお、本発明の一態様の半導体装置を、上述の制御装置６５０９、及び制御装置６６１６に用いることで、消費電力を低減させることができるため好適である。 The electronic device 6600 shown in FIG. 31B is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention for the above-described control device 6509 and control device 6616 is preferable because power consumption can be reduced.
［大型計算機］
　次に、大型計算機５６００の斜視図を図３１Ｃに示す。図３１Ｃに示す大型計算機５６００には、ラック５６１０にラックマウント型の計算機５６２０が複数格納されている。なお、大型計算機５６００を、スーパーコンピュータと呼称してもよい。 [Mainframe computers]
Next, Fig. 31C shows a perspective view of the large scale computer 5600. The large scale computer 5600 shown in Fig. 31C has a rack 5610 housing a plurality of rack-mounted computers 5620. The large scale computer 5600 may also be called a supercomputer.
　計算機５６２０は、例えば、図３１Ｄに示す斜視図の構成とすることができる。図３１Ｄにおいて、計算機５６２０は、マザーボード５６３０を有し、マザーボード５６３０は、複数のスロット５６３１、複数の接続端子を有する。スロット５６３１には、ＰＣカード５６２１が挿入されている。加えて、ＰＣカード５６２１は、接続端子５６２３、接続端子５６２４、接続端子５６２５を有し、それぞれ、マザーボード５６３０に接続されている。 Computer 5620 can be configured, for example, as shown in the perspective view of FIG. 31D. In FIG. 31D, computer 5620 has motherboard 5630, which has multiple slots 5631 and multiple connection terminals. PC card 5621 is inserted into slot 5631. In addition, PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to motherboard 5630.
　図３１Ｅに示すＰＣカード５６２１は、ＣＰＵ、ＧＰＵ、記憶装置などを備えた処理ボードの一例である。ＰＣカード５６２１は、ボード５６２２を有する。また、ボード５６２２は、接続端子５６２３と、接続端子５６２４と、接続端子５６２５と、半導体装置５６２６と、半導体装置５６２７と、半導体装置５６２８と、接続端子５６２９と、を有する。なお、図３１Ｅには、半導体装置５６２６、半導体装置５６２７、および半導体装置５６２８以外の半導体装置を図示しているが、それらの半導体装置については、以下に記載する半導体装置５６２６、半導体装置５６２７、および半導体装置５６２８の説明を参照すればよい。 PC card 5621 shown in FIG. 31E is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that FIG. 31E illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for those semiconductor devices, please refer to the explanation of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 described below.
　接続端子５６２９は、マザーボード５６３０のスロット５６３１に挿入することができる形状を有しており、接続端子５６２９は、ＰＣカード５６２１とマザーボード５６３０とを接続するためのインターフェースとして機能する。接続端子５６２９の規格としては、例えば、ＰＣＩｅなどが挙げられる。 The connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.
　接続端子５６２３、接続端子５６２４、接続端子５６２５は、例えば、ＰＣカード５６２１に対して電力供給、信号入力などを行うためのインターフェースとすることができる。また、例えば、ＰＣカード５６２１によって計算された信号の出力などを行うためのインターフェースとすることができる。接続端子５６２３、接続端子５６２４、接続端子５６２５のそれぞれの規格としては、例えば、ＵＳＢ（Ｕｎｉｖｅｒｓａｌ　Ｓｅｒｉａｌ　Ｂｕｓ）、ＳＡＴＡ（Ｓｅｒｉａｌ　ＡＴＡ）、ＳＣＳＩ（Ｓｍａｌｌ　Ｃｏｍｐｕｔｅｒ　Ｓｙｓｔｅｍ　Ｉｎｔｅｒｆａｃｅ）などが挙げられる。また、接続端子５６２３、接続端子５６２４、接続端子５６２５から映像信号を出力する場合、それぞれの規格としては、ＨＤＭＩ（登録商標）などが挙げられる。 Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).
　半導体装置５６２６は、信号の入出力を行う端子（図示しない。）を有しており、当該端子をボード５６２２が備えるソケット（図示しない。）に対して差し込むことで、半導体装置５６２６とボード５６２２を電気的に接続することができる。 The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
　半導体装置５６２７は、複数の端子を有しており、当該端子をボード５６２２が備える配線に対して、例えば、リフロー方式のはんだ付けを行うことで、半導体装置５６２７とボード５６２２を電気的に接続することができる。半導体装置５６２７としては、例えば、ＦＰＧＡ、ＧＰＵ、ＣＰＵなどが挙げられる。半導体装置５６２７として、例えば、電子部品７３０を用いることができる。 The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.
　半導体装置５６２８は、複数の端子を有しており、当該端子をボード５６２２が備える配線に対して、例えば、リフロー方式のはんだ付けを行うことで、半導体装置５６２８とボード５６２２を電気的に接続することができる。半導体装置５６２８としては、例えば、記憶装置などが挙げられる。半導体装置５６２８として、例えば、電子部品７００を用いることができる。 The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method. An example of the semiconductor device 5628 is a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.
　大型計算機５６００は並列計算機としても機能できる。大型計算機５６００を並列計算機として用いることで、例えば、人工知能の学習、および推論に必要な大規模の計算を行うことができる。 The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.
［宇宙用機器］
　本発明の一態様の半導体装置は、情報を処理および記憶する機器などの宇宙用機器に好適に用いることができる。 [Space equipment]
The semiconductor device of one embodiment of the present invention can be suitably used in space equipment, such as equipment for processing and storing data.
　本発明の一態様の半導体装置は、ＯＳトランジスタを含むことができる。当該ＯＳトランジスタは、放射線照射による電気特性の変動が小さい。つまり放射線に対する耐性が高いため、放射線が入射しうる環境において好適に用いることができる。例えば、ＯＳトランジスタは、宇宙空間にて使用する場合に好適に用いることができる。 The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor has small changes in electrical characteristics due to radiation exposure. In other words, the OS transistor has high resistance to radiation and can be preferably used in an environment where radiation may be incident. For example, the OS transistor can be preferably used in outer space.
　図３２には、宇宙用機器の一例として、人工衛星６８００を示している。人工衛星６８００は、機体６８０１と、ソーラーパネル６８０２と、アンテナ６８０３と、二次電池６８０５と、制御装置６８０７と、を有する。なお、図３２においては、宇宙空間に惑星６８０４を例示している。なお、宇宙空間とは、例えば、高度１００ｋｍ以上を指すが、本明細書に記載の宇宙空間は、熱圏、中間圏、及び成層圏を含んでもよい。 In FIG. 32, an artificial satellite 6800 is shown as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In FIG. 32, a planet 6804 is shown as an example of outer space. Note that outer space refers to an altitude of 100 km or more, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.
　また、図３２には、図示していないが、二次電池６８０５に、バッテリマネジメントシステム（ＢＭＳともいう）、またはバッテリ制御回路を設けてもよい。上述のバッテリマネジメントシステム、またはバッテリ制御回路に、ＯＳトランジスタを用いると、消費電力が低く、且つ宇宙空間においても高い信頼性を有するため好適である。 Although not shown in FIG. 32, the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit. The use of OS transistors in the above-mentioned battery management system or battery control circuit is preferable because it has low power consumption and high reliability even in outer space.
　また、宇宙空間は、地上に比べて１００倍以上、放射線量の高い環境である。なお、放射線として、例えば、Ｘ線、及びガンマ線に代表される電磁波（電磁放射線）、並びにアルファ線、ベータ線、中性子線、陽子線、重イオン線、中間子線などに代表される粒子放射線が挙げられる。 In addition, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
　ソーラーパネル６８０２に太陽光が照射されることにより、人工衛星６８００が動作するために必要な電力が生成される。しかしながら、例えばソーラーパネルに太陽光が照射されない状況、またはソーラーパネルに照射される太陽光の光量が少ない状況では、生成される電力が少なくなる。よって、人工衛星６８００が動作するために必要な電力が生成されない可能性がある。生成される電力が少ない状況下であっても人工衛星６８００を動作させるために、人工衛星６８００に二次電池６８０５を設けるとよい。なお、ソーラーパネルは、太陽電池モジュールと呼ばれる場合がある。 When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or where the amount of sunlight irradiating the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is advisable to provide the satellite 6800 with a secondary battery 6805. The solar panel may be called a solar cell module.
　人工衛星６８００は、信号を生成することができる。当該信号は、アンテナ６８０３を介して送信され、たとえば地上に設けられた受信機、または他の人工衛星が当該信号を受信することができる。人工衛星６８００が送信した信号を受信することにより、当該信号を受信した受信機の位置を測定することができる。以上より、人工衛星６８００は、衛星測位システムを構成することができる。 Satellite 6800 can generate a signal. The signal is transmitted via antenna 6803, and can be received, for example, by a receiver installed on the ground or by another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be measured. As described above, satellite 6800 can constitute a satellite positioning system.
　また、制御装置６８０７は、人工衛星６８００を制御する機能を有する。制御装置６８０７としては、例えば、ＣＰＵ、ＧＰＵ、及び記憶装置の中から選ばれるいずれか一または複数を用いて構成される。なお、制御装置６８０７には、本発明の一態様である半導体装置を用いると好適である。ＯＳトランジスタは、Ｓｉトランジスタと比較し、放射線照射による電気特性の変動が小さい。つまり放射線が入射しうる環境においても信頼性が高く、好適に用いることができる。 The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device. Note that a semiconductor device according to one embodiment of the present invention is preferably used for the control device 6807. Compared to a Si transistor, an OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure. In other words, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.
　また、人工衛星６８００は、センサを有する構成とすることができる。たとえば、可視光センサを有する構成とすることにより、人工衛星６８００は、地上に設けられている物体に当たって反射された太陽光を検出する機能を有することができる。または、熱赤外センサを有する構成とすることにより、人工衛星６８００は、地表から放出される熱赤外線を検出する機能を有することができる。以上より、人工衛星６８００は、たとえば地球観測衛星としての機能を有することができる。 The artificial satellite 6800 can also be configured to have a sensor. For example, by configuring it to have a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground. Or, by configuring it to have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
　なお、本実施の形態においては、宇宙用機器の一例として、人工衛星について例示したがこれに限定されない。例えば、本発明の一態様の半導体装置は、宇宙船、宇宙カプセル、宇宙探査機などの宇宙用機器に好適に用いることができる。 Note that in this embodiment, an artificial satellite is given as an example of space equipment, but the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.
　以上の説明の通り、ＯＳトランジスタは、Ｓｉトランジスタと比較し、広いメモリバンド幅の実現が可能なこと、放射線耐性が高いこと、といった優れた効果を有する。 As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.
［データセンター］
　本発明の一態様の半導体装置は、例えば、データセンターなどに適用されるストレージシステムに好適に用いることができる。データセンターは、データの不変性を保障するなど、データの長期的な管理を行うことが求められる。データを長期的に管理する場合、膨大なデータを記憶するためのストレージおよびサーバの設置、データを保持するための安定した電源の確保、あるいはデータの保持に要する冷却設備の確保、など建屋の大型化が必要となる。 [Data Center]
The semiconductor device according to one embodiment of the present invention can be suitably used in a storage system applied to a data center or the like. The data center is required to perform long-term management of data, such as by ensuring the immutability of the data. In order to manage data for a long period of time, it is necessary to increase the size of the building, for example, by installing storage and servers for storing a huge amount of data, by securing a stable power source for holding the data, or by securing cooling equipment required for holding the data.
　データセンターに適用されるストレージシステムに本発明の一態様の半導体装置を用いることにより、データの保持に要する電力の低減、データを保持する半導体装置の小型化を図ることができる。そのため、ストレージシステムの小型化、データを保持するための電源の小型化、冷却設備の小規模化、などを図ることができる。そのため、データセンターの省スペース化を図ることができる。 By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores the data. This makes it possible to miniaturize the storage system, miniaturize the power source for storing data, and reduce the scale of cooling equipment. This makes it possible to save space in the data center.
　また、本発明の一態様の半導体装置は、消費電力が少ないため、回路からの発熱を低減することができる。よって、当該発熱によるその回路自体、周辺回路、およびモジュールへの悪影響を低減できる。また、本発明の一態様の半導体装置を用いることにより、高温環境下においても動作が安定したデータセンターを実現できる。よってデータセンターの信頼性を高めることができる。 In addition, the semiconductor device of one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. This reduces adverse effects of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. This improves the reliability of the data center.
　図３３にデータセンターに適用可能なストレージシステムを示す。図３３に示すストレージシステム７０００は、ホスト７００１（Ｈｏｓｔ　Ｃｏｍｐｕｔｅｒと図示）として複数のサーバ７００１ｓｂを有する。また、ストレージ７００３（Ｓｔｏｒａｇｅと図示）として複数の記憶装置７００３ｍｄを有する。ホスト７００１とストレージ７００３とは、ストレージエリアネットワーク７００４（ＳＡＮ：Ｓｔｏｒａｇｅ　Ａｒｅａ　Ｎｅｔｗｏｒｋと図示）およびストレージ制御回路７００２（Ｓｔｏｒａｇｅ　Ｃｏｎｔｒｏｌｌｅｒと図示）を介して接続されている形態を図示している。 Figure 33 shows a storage system applicable to a data center. The storage system 7000 shown in Figure 33 has multiple servers 7001sb as hosts 7001 (illustrated as Host Computer). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).
　ホスト７００１は、ストレージ７００３に記憶されたデータにアクセスするコンピュータに相当する。ホスト７００１同士は、ネットワークで互いに接続されていてもよい。 The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.
　ストレージ７００３は、フラッシュメモリを用いることで、データのアクセススピード、つまりデータの記憶及び出力に要する時間を短くしているものの、当該時間は、ストレージ７００３内のキャッシュメモリとして用いることのできるＤＲＡＭが要する時間に比べて格段に長い。ストレージシステムでは、ストレージ７００３のアクセススピードの長さの問題を解決するために、通常ストレージ７００３内にキャッシュメモリを設けてデータの記憶及び出力を短くしている。 Storage 7003 uses flash memory to reduce data access speed, that is, the time required to store and output data, but this time is significantly longer than the time required by DRAM that can be used as cache memory in storage 7003. In storage systems, to solve the problem of the long access speed of storage 7003, cache memory is usually provided in storage 7003 to reduce the time required to store and output data.
　上述のキャッシュメモリは、ストレージ制御回路７００２およびストレージ７００３内に用いられる。ホスト７００１とストレージ７００３との間でやり取りされるデータは、ストレージ制御回路７００２およびストレージ７００３内の当該キャッシュメモリに記憶されたのち、ホスト７００１またはストレージ７００３に出力される。 The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.
　上述のキャッシュメモリのデータを記憶するためのトランジスタとして、ＯＳトランジスタを用いてデータに応じた電位を保持する構成とすることで、リフレッシュする頻度を減らし、消費電力を小さくすることができる。またメモリセルアレイを積層する構成とすることでストレージの小型化が可能である。 By using OS transistors as transistors for storing data in the above-mentioned cache memory and configuring them to hold a potential according to the data, it is possible to reduce the frequency of refreshes and lower power consumption. In addition, by configuring memory cell arrays in a stacked structure, it is possible to miniaturize the storage.
　なお、本発明の一態様の半導体装置を、電子部品、電子機器、大型計算機、宇宙用機器、およびデータセンターの中から選ばれるいずれか一または複数に適用することで、消費電力を低減させる効果が期待される。そのため、半導体装置の高性能化、または高集積化に伴うエネルギー需要の増加が見込まれる中、本発明の一態様の半導体装置を用いることで、二酸化炭素（ＣＯ２）に代表される、温室効果ガスの排出量を低減させることも可能となる。また、本発明の一態様の半導体装置は、低消費電力であるため地球温暖化対策としても有効である。 Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO 2 ). In addition, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming because of its low power consumption.
　本実施の形態に示す構成、構造、方法などは、他の実施の形態などに示す構成、構造、方法などと適宜組み合わせて用いることができる。 The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments.
ＡＤＤＲ：信号、ＢＬ［１］：配線、ＢＬ［ｊ］：配線、ＢＬ［ｎ］：配線、ＢＬ＿Ａ：配線、ＢＬ＿Ｂ：配線、ＢＬ：配線、ＢＷ：信号、ＣＥ：信号、ＣＬＫ：信号、ＥＮ＿ｄａｔａ：信号、ＧＢＬ＿Ａ：配線、ＧＢＬ＿Ｂ：配線、ＧＢＬ：配線、ＧＷ：信号、ＭＵＸ：選択信号、ＰＬ［１］：配線、ＰＬ［ｉ］：配線、ＰＬ［ｍ］：配線、ＰＬ：配線、ＲＤＡ：信号、ＲＥ：制御信号、ＶＨＨ：配線、ＶＬＬ：配線、ＶＰＣ：中間電位、ＷＡＫＥ：信号、ＷＤＡ：信号、ＷＥ：制御信号、ＷＬ［１］：配線、ＷＬ［ｉ］：配線、ＷＬ［ｍ］：配線、ＷＬ：配線、１０［１，１］：メモリセル、１０［ｉ，ｊ］：メモリセル、１０［ｍ，ｎ］：メモリセル、１０＿Ａ：メモリセル、１０＿Ｂ：メモリセル、１０：メモリセル、１１：トランジスタ、１２：容量素子、２０［１］：メモリアレイ、２０［２］：メモリアレイ、２０［５］：メモリアレイ、２０［ｍ］：メモリアレイ、２０：メモリアレイ、２１：駆動回路、２２：ＰＳＷ、２３：ＰＳＷ、３１：周辺回路、３２：コントロール回路、３３：電圧生成回路、４１：周辺回路、４２：行デコーダ、４３：行ドライバ、４４：列デコーダ、４５：列ドライバ、４６：センスアンプ、４７：入力回路、４８：出力回路、５０：機能層、５１＿Ａ：機能回路、５１＿Ｂ：機能回路、５１：機能回路、５２＿ａ：トランジスタ、５２＿ｂ：トランジスタ、５２：トランジスタ、５３＿ａ：トランジスタ、５３＿ｂ：トランジスタ、５３：トランジスタ、５４＿ａ：トランジスタ、５４＿ｂ：トランジスタ、５４：トランジスタ、５５＿ａ：トランジスタ、５５＿ｂ：トランジスタ、５５：トランジスタ、７０［１］：繰り返し単位、７０：繰り返し単位、７１＿Ａ：プリチャージ回路、７１＿Ｂ：プリチャージ回路、７２＿Ａ：スイッチ回路、７２＿Ｂ：スイッチ回路、７３：書き込み読み出し回路、８１＿１：トランジスタ、８１＿３：トランジスタ、８１＿４：トランジスタ、８１＿６：トランジスタ、８２＿１：トランジスタ、８２＿２：トランジスタ、８２＿３：トランジスタ、８２＿４：トランジスタ、８３＿Ａ：スイッチ、８３＿Ｂ：スイッチ、８３＿Ｃ：スイッチ、８３＿Ｄ：スイッチ、１５３：導電体、１５４：絶縁体、１６０ａ：導電体、１６０ｂ：導電体、１６０：導電体、２００ａ：トランジスタ、２００ａＤ：トランジスタ、２００ａＥ：トランジスタ、２００ｂ：トランジスタ、２００：トランジスタ、２０５ａ：導電体、２０５ｂ：導電体、２０５：導電体、２０６：導電体、２０７：導電体、２０８：絶縁体、２０９：導電体、２１０：絶縁体、２１２：絶縁体、２１４：絶縁体、２１５：絶縁体、２１６：絶縁体、２２１：絶縁体、２２２：絶縁体、２２３：絶縁体、２２５ｆ：絶縁膜、２２５：絶縁体、２３０ａ：酸化物、２３０ａＤ：酸化物、２３０ａＥ：酸化物、２３０ａｆ：酸化膜、２３０ｂ：酸化物、２３０ｂＤ：酸化物、２３０ｂＥ：酸化物、２３０ｂｆ：酸化膜、２３０Ｄ：酸化物、２３０Ｅ：酸化物、２３０：酸化物、２４０ａ：導電体、２４０ａＤ：導電体、２４０ａＥ：導電体、２４０ｂ：導電体、２４０ｂＤ：導電体、２４０ｂＥ：導電体、２４０ｃ：導電体、２４０：導電体、２４１ａ：絶縁体、２４１ａＤ：絶縁体、２４１ａＥ：絶縁体、２４１ｂ：絶縁体、２４１ｂＤ：絶縁体、２４１ｂＥ：絶縁体、２４１ｃ：絶縁体、２４１：絶縁体、２４２Ａ：導電体、２４２ａ：導電体、２４２ａＤ：導電体、２４２ａＥ：導電体、２４２ｂ：導電体、２４２ｂＤ：導電体、２４２ｂＥ：導電体、２４２ｆ：導電膜、２４２：導電体、２４６ａ：導電体、２４６ｂ：導電体、２５０ａ：絶縁体、２５０Ａ：絶縁膜、２５０ｂ：絶縁体、２５０ｃ：絶縁体、２５０ｄ：絶縁体、２５０：絶縁体、２５５：絶縁体、２６０ａ：導電体、２６０Ａ：導電膜、２６０ｂ：導電体、２６０Ｂ：導電膜、２６０：導電体、２７５：絶縁体、２８０：絶縁体、２８２：絶縁体、２８３：絶縁体、２８４：絶縁体、２８５：絶縁体、２８６：絶縁体、２８７：絶縁体、２８８：絶縁体、２８９：絶縁体、２９０：絶縁体、２９１：絶縁体、２９２：絶縁体、２９３：絶縁体、２９４：導電体、３００Ａ：記憶装置、３００：記憶装置、３１０：トランジスタ、３１１：基板、３１３：半導体領域、３１４ａ：低抵抗領域、３１４ｂ：低抵抗領域、３１５：絶縁体、３１６：導電体、３２０：絶縁体、３２２：絶縁体、３２４：絶縁体、３２６：絶縁体、３２８：導電体、３３０：導電体、７００：電子部品、７０２：プリント基板、７０４：実装基板、７１０：半導体装置、７１１：モールド、７１２：ランド、７１３：電極パッド、７１４：ワイヤ、７１５：駆動回路層、７１６：記憶層、７３０：電子部品、７３１：インターポーザ、７３２：パッケージ基板、７３３：電極、７３５：半導体装置、１２００：チップ、１２０１：パッケージ基板、１２０２：バンプ、１２０３：マザーボード、１２０４：ＧＰＵモジュール、１２１１：ＣＰＵ、１２１２：ＧＰＵ、１２１３：アナログ演算部、１２１４：メモリコントローラ、１２１５：インターフェース、１２１６：ネットワーク回路、１２２１：ＤＲＡＭ、１２２２：フラッシュメモリ、５６００：大型計算機、５６１０：ラック、５６２０：計算機、５６２１：ＰＣカード、５６２２：ボード、５６２３：接続端子、５６２４：接続端子、５６２５：接続端子、５６２６：半導体装置、５６２７：半導体装置、５６２８：半導体装置、５６２９：接続端子、５６３０：マザーボード、５６３１：スロット、６５００：電子機器、６５０１：筐体、６５０２：表示部、６５０３：電源ボタン、６５０４：ボタン、６５０５：スピーカ、６５０６：マイク、６５０７：カメラ、６５０８：光源、６５０９：制御装置、６６００：電子機器、６６１１：筐体、６６１２：キーボード、６６１３：ポインティングデバイス、６６１４：外部接続ポート、６６１５：表示部、６６１６：制御装置、６８００：人工衛星、６８０１：機体、６８０２：ソーラーパネル、６８０３：アンテナ、６８０４：惑星、６８０５：二次電池、６８０７：制御装置、７０００：ストレージシステム、７００１ｓｂ：サーバ、７００１：ホスト、７００２：ストレージ制御回路、７００３ｍｄ：記憶装置、７００３：ストレージ ADDR: signal, BL[1]: wiring, BL[j]: wiring, BL[n]: wiring, BL_A: wiring, BL_B: wiring, BL: wiring, BW: signal, CE: signal, CLK: signal, EN_data: signal, GBL_A: wiring, GBL_B: wiring, GBL: wiring, GW: signal, MUX: selection signal, PL[1]: wiring, PL[i]: wiring, PL[m]: wiring, PL: wiring, RDA : signal, RE: control signal, VHH: wiring, VLL: wiring, VPC: intermediate potential, WAKE: signal, WDA: signal, WE: control signal, WL[1]: wiring, WL[i]: wiring, WL[m]: wiring, WL: wiring, 10[1,1]: memory cell, 10[i,j]: memory cell, 10[m,n]: memory cell, 10_A: memory cell, 10_B: memory cell, 10: memory cell, 1 1: transistor, 12: capacitive element, 20[1]: memory array, 20[2]: memory array, 20[5]: memory array, 20[m]: memory array, 20: memory array, 21: drive circuit, 22: PSW, 23: PSW, 31: peripheral circuit, 32: control circuit, 33: voltage generation circuit, 41: peripheral circuit, 42: row decoder, 43: row driver, 44: column decoder, 45: column driver, 46: sense amplifier, 47: input circuit, 48: output circuit, 50: functional layer, 51_A: functional circuit, 51_B: functional circuit, 51: functional circuit, 52_a: transistor, 52_b: transistor, 52: transistor, 53_a: transistor, 53_b: transistor, 53: transistor, 54_a: transistor, 54_b: transistor, 54 : transistor, 55_a: transistor, 55_b: transistor, 55: transistor, 70[1]: repeat unit, 70: repeat unit, 71_A: precharge circuit, 71_B: precharge circuit, 72_A: switch circuit, 72_B: switch circuit, 73: write/read circuit, 81_1: transistor, 81_3: transistor, 81_4: transistor, 81_6: transistor, 82_1: transistor, 82_2: transistor, 82_3: transistor, 82_4: transistor, 83_A: switch, 83_B: switch, 83_C: switch, 83_D: switch, 153: conductor, 154: insulator, 160a: conductor, 160b: conductor, 160: conductor, 200a: transistor, 200aD: transistor 200aE: transistor, 200b: transistor, 200: transistor, 205a: conductor, 205b: conductor, 205: conductor, 206: conductor, 207: conductor, 208: insulator, 209: conductor, 210: insulator, 212: insulator, 214: insulator, 215: insulator, 216: insulator, 221: insulator, 222: insulator, 223: insulator, 22 5f: insulating film, 225: insulator, 230a: oxide, 230aD: oxide, 230aE: oxide, 230af: oxide film, 230b: oxide, 230bD: oxide, 230bE: oxide, 230bf: oxide film, 230D: oxide, 230E: oxide, 230: oxide, 240a: conductor, 240aD: conductor, 240aE: conductor, 240b: conductor, 240bD: conductor conductor, 240bE: conductor, 240c: conductor, 240: conductor, 241a: insulator, 241aD: insulator, 241aE: insulator, 241b: insulator, 241bD: insulator, 241bE: insulator, 241c: insulator, 241: insulator, 242A: conductor, 242a: conductor, 242aD: conductor, 242aE: conductor, 242b: conductor, 242bD: conductor, 242 bE: conductor, 242f: conductive film, 242: conductor, 246a: conductor, 246b: conductor, 250a: insulator, 250A: insulating film, 250b: insulator, 250c: insulator, 250d: insulator, 250: insulator, 255: insulator, 260a: conductor, 260A: conductive film, 260b: conductor, 260B: conductive film, 260: conductor, 275: insulator, 280: insulator, 28 2: insulator, 283: insulator, 284: insulator, 285: insulator, 286: insulator, 287: insulator, 288: insulator, 289: insulator, 290: insulator, 291: insulator, 292: insulator, 293: insulator, 294: conductor, 300A: memory device, 300: memory device, 310: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: Low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 700: electronic component, 702: printed circuit board, 704: mounting board, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730 : Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 1200: Chip, 1201: Package substrate, 1202: Bump, 1203: Motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: Analogue calculation unit, 1214: Memory controller, 1215: Interface, 1216: Network circuit, 1221: DRAM, 1222: Flash memory, 5600: Mainframe, 5610: Rack, 5620: Calculator, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connection terminal, 5630: Motherboard, 5631: slot, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001sb: server, 7001: host, 7002: storage control circuit, 7003md: storage device, 7003: storage

Claims (9)

  1. 　基板上の第１の絶縁体と、
    　前記第１の絶縁体を覆う酸化物半導体と、
    　前記酸化物半導体上の第１の導電体及び第２の導電体と、
    　前記第１の導電体、及び前記第２の導電体上に配置され、前記第１の導電体と前記第２の導電体の間の領域と重畳する開口を有する、第２の絶縁体と、
    　前記開口内に配置され、前記酸化物半導体上に配置される第３の絶縁体と、
    　前記開口内に配置され、前記第３の絶縁体上に配置される、第３の導電体と、を有し、
    　チャネル幅方向の断面視において、前記第１の絶縁体の高さは、前記第１の絶縁体の幅より長い、
    　半導体装置。     a first insulator on a substrate;
    an oxide semiconductor covering the first insulator;
    a first conductor and a second conductor on the oxide semiconductor;
    a second insulator disposed on the first conductor and the second conductor and having an opening overlapping a region between the first conductor and the second conductor;
    a third insulator disposed in the opening and on the oxide semiconductor;
    a third conductor disposed in the opening and on the third insulator;
    In a cross-sectional view in a channel width direction, a height of the first insulator is longer than a width of the first insulator.
    Semiconductor device.
  2. 　請求項１において、
    　平面視において、前記第２の絶縁体の開口の側面は、前記第１の導電体の側面、及び前記第２の導電体の側面と一致または概略一致する、
    　半導体装置。     In claim 1,
    In a plan view, a side surface of the opening of the second insulator coincides or approximately coincides with a side surface of the first conductor and a side surface of the second conductor.
    Semiconductor device.
  3. 　請求項１において、
    　チャネル幅方向の断面視において、前記第１の絶縁体の高さは、前記第１の絶縁体の幅の２倍以上２０倍以下である、半導体装置。     In claim 1,
    A semiconductor device, wherein, in a cross-sectional view in a channel width direction, the height of the first insulator is equal to or greater than two times and equal to or less than twenty times the width of the first insulator.
  4. 　請求項１において、
    　前記第１の導電体は、トランジスタのソース電極及びドレイン電極の一方として機能し、
    　前記第２の導電体は、前記トランジスタのソース電極及びドレイン電極の他方として機能し、
    　前記第３の導電体は、前記トランジスタのゲート電極として機能する、
    　半導体装置。     In claim 1,
    the first conductor functions as one of a source electrode and a drain electrode of a transistor;
    the second conductor functions as the other of the source electrode and the drain electrode of the transistor;
    the third conductor functions as a gate electrode of the transistor;
    Semiconductor device.
  5. 　請求項４において、
    　チャネル幅方向の断面視において、
    　前記第１の絶縁体の一方の側面において、前記酸化物半導体と前記第３の導電体が前記第３の絶縁体を挟んで対向し、
    　前記第１の絶縁体の他方の側面において、前記酸化物半導体と前記第３の導電体が前記第３の絶縁体を挟んで対向する、
    　半導体装置。     In claim 4,
    In a cross-sectional view in the channel width direction,
    the oxide semiconductor and the third conductor face each other on one side surface of the first insulator with the third insulator therebetween;
    the oxide semiconductor and the third conductor face each other on the other side surface of the first insulator, with the third insulator interposed therebetween;
    Semiconductor device.
  6. 　請求項４において、
    　チャネル幅方向の断面視において、
    　前記第１の導電体は、前記第１の絶縁体の一方の側面側、及び他方の側面側において、前記酸化物半導体と接し、
    　前記第２の導電体は、前記第１の絶縁体の一方の側面側、及び他方の側面側において、前記酸化物半導体と接する、
    　半導体装置。     In claim 4,
    In a cross-sectional view in the channel width direction,
    the first conductor is in contact with the oxide semiconductor on one side surface and the other side surface of the first insulator;
    the second conductor is in contact with the oxide semiconductor on one side surface and the other side surface of the first insulator;
    Semiconductor device.
  7. 　請求項１乃至請求項６のいずれか一項において、
    　前記酸化物半導体は、Ｉｎ、Ｇａ、及びＺｎの中から選ばれるいずれか一または複数を有する、
    　半導体装置。     In any one of claims 1 to 6,
    The oxide semiconductor contains one or more selected from the group consisting of In, Ga, and Zn.
    Semiconductor device.
  8. 　請求項７に記載の半導体装置と、容量素子と、を有し、
    　前記容量素子の一方の電極が、前記半導体装置の前記第１の導電体と電気的に接続される、
    　記憶装置。     A semiconductor device comprising: the semiconductor device according to claim 7; and a capacitive element;
    one electrode of the capacitance element is electrically connected to the first conductor of the semiconductor device;
    Storage device.
  9. 　請求項８において、
    　前記容量素子は、前記第３の導電体上に配置され、
    　前記容量素子の少なくとも一部は、前記酸化物半導体、及び前記第３の導電体と重畳する、
    　記憶装置。     In claim 8,
    the capacitive element is disposed on the third conductor;
    at least a part of the capacitor overlaps with the oxide semiconductor and the third conductor;
    Storage device.
PCT/IB2023/060031 2022-10-14 2023-10-06 Semiconductor device and storage device WO2024079586A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013165260A (en) * 2012-01-10 2013-08-22 Semiconductor Energy Lab Co Ltd Semiconductor device and semiconductor device manufacture method
JP2016157943A (en) * 2015-02-25 2016-09-01 株式会社半導体エネルギー研究所 Semiconductor device
WO2020115595A1 (en) * 2018-12-07 2020-06-11 株式会社半導体エネルギー研究所 Semiconductor device, and semiconductor device fabrication method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013165260A (en) * 2012-01-10 2013-08-22 Semiconductor Energy Lab Co Ltd Semiconductor device and semiconductor device manufacture method
JP2016157943A (en) * 2015-02-25 2016-09-01 株式会社半導体エネルギー研究所 Semiconductor device
WO2020115595A1 (en) * 2018-12-07 2020-06-11 株式会社半導体エネルギー研究所 Semiconductor device, and semiconductor device fabrication method

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